root/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_enum.h

   1 /*
   2  * GFX_8_1 Register documentation
   3  *
   4  * Copyright (C) 2014  Advanced Micro Devices, Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included
  14  * in all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  20  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 
  24 #ifndef GFX_8_1_ENUM_H
  25 #define GFX_8_1_ENUM_H
  26 
  27 typedef enum SurfaceNumber {
  28         NUMBER_UNORM                                     = 0x0,
  29         NUMBER_SNORM                                     = 0x1,
  30         NUMBER_USCALED                                   = 0x2,
  31         NUMBER_SSCALED                                   = 0x3,
  32         NUMBER_UINT                                      = 0x4,
  33         NUMBER_SINT                                      = 0x5,
  34         NUMBER_SRGB                                      = 0x6,
  35         NUMBER_FLOAT                                     = 0x7,
  36 } SurfaceNumber;
  37 typedef enum SurfaceSwap {
  38         SWAP_STD                                         = 0x0,
  39         SWAP_ALT                                         = 0x1,
  40         SWAP_STD_REV                                     = 0x2,
  41         SWAP_ALT_REV                                     = 0x3,
  42 } SurfaceSwap;
  43 typedef enum CBMode {
  44         CB_DISABLE                                       = 0x0,
  45         CB_NORMAL                                        = 0x1,
  46         CB_ELIMINATE_FAST_CLEAR                          = 0x2,
  47         CB_RESOLVE                                       = 0x3,
  48         CB_DECOMPRESS                                    = 0x4,
  49         CB_FMASK_DECOMPRESS                              = 0x5,
  50         CB_DCC_DECOMPRESS                                = 0x6,
  51 } CBMode;
  52 typedef enum RoundMode {
  53         ROUND_BY_HALF                                    = 0x0,
  54         ROUND_TRUNCATE                                   = 0x1,
  55 } RoundMode;
  56 typedef enum SourceFormat {
  57         EXPORT_4C_32BPC                                  = 0x0,
  58         EXPORT_4C_16BPC                                  = 0x1,
  59         EXPORT_2C_32BPC_GR                               = 0x2,
  60         EXPORT_2C_32BPC_AR                               = 0x3,
  61 } SourceFormat;
  62 typedef enum BlendOp {
  63         BLEND_ZERO                                       = 0x0,
  64         BLEND_ONE                                        = 0x1,
  65         BLEND_SRC_COLOR                                  = 0x2,
  66         BLEND_ONE_MINUS_SRC_COLOR                        = 0x3,
  67         BLEND_SRC_ALPHA                                  = 0x4,
  68         BLEND_ONE_MINUS_SRC_ALPHA                        = 0x5,
  69         BLEND_DST_ALPHA                                  = 0x6,
  70         BLEND_ONE_MINUS_DST_ALPHA                        = 0x7,
  71         BLEND_DST_COLOR                                  = 0x8,
  72         BLEND_ONE_MINUS_DST_COLOR                        = 0x9,
  73         BLEND_SRC_ALPHA_SATURATE                         = 0xa,
  74         BLEND_BOTH_SRC_ALPHA                             = 0xb,
  75         BLEND_BOTH_INV_SRC_ALPHA                         = 0xc,
  76         BLEND_CONSTANT_COLOR                             = 0xd,
  77         BLEND_ONE_MINUS_CONSTANT_COLOR                   = 0xe,
  78         BLEND_SRC1_COLOR                                 = 0xf,
  79         BLEND_INV_SRC1_COLOR                             = 0x10,
  80         BLEND_SRC1_ALPHA                                 = 0x11,
  81         BLEND_INV_SRC1_ALPHA                             = 0x12,
  82         BLEND_CONSTANT_ALPHA                             = 0x13,
  83         BLEND_ONE_MINUS_CONSTANT_ALPHA                   = 0x14,
  84 } BlendOp;
  85 typedef enum CombFunc {
  86         COMB_DST_PLUS_SRC                                = 0x0,
  87         COMB_SRC_MINUS_DST                               = 0x1,
  88         COMB_MIN_DST_SRC                                 = 0x2,
  89         COMB_MAX_DST_SRC                                 = 0x3,
  90         COMB_DST_MINUS_SRC                               = 0x4,
  91 } CombFunc;
  92 typedef enum BlendOpt {
  93         FORCE_OPT_AUTO                                   = 0x0,
  94         FORCE_OPT_DISABLE                                = 0x1,
  95         FORCE_OPT_ENABLE_IF_SRC_A_0                      = 0x2,
  96         FORCE_OPT_ENABLE_IF_SRC_RGB_0                    = 0x3,
  97         FORCE_OPT_ENABLE_IF_SRC_ARGB_0                   = 0x4,
  98         FORCE_OPT_ENABLE_IF_SRC_A_1                      = 0x5,
  99         FORCE_OPT_ENABLE_IF_SRC_RGB_1                    = 0x6,
 100         FORCE_OPT_ENABLE_IF_SRC_ARGB_1                   = 0x7,
 101 } BlendOpt;
 102 typedef enum CmaskCode {
 103         CMASK_CLR00_F0                                   = 0x0,
 104         CMASK_CLR00_F1                                   = 0x1,
 105         CMASK_CLR00_F2                                   = 0x2,
 106         CMASK_CLR00_FX                                   = 0x3,
 107         CMASK_CLR01_F0                                   = 0x4,
 108         CMASK_CLR01_F1                                   = 0x5,
 109         CMASK_CLR01_F2                                   = 0x6,
 110         CMASK_CLR01_FX                                   = 0x7,
 111         CMASK_CLR10_F0                                   = 0x8,
 112         CMASK_CLR10_F1                                   = 0x9,
 113         CMASK_CLR10_F2                                   = 0xa,
 114         CMASK_CLR10_FX                                   = 0xb,
 115         CMASK_CLR11_F0                                   = 0xc,
 116         CMASK_CLR11_F1                                   = 0xd,
 117         CMASK_CLR11_F2                                   = 0xe,
 118         CMASK_CLR11_FX                                   = 0xf,
 119 } CmaskCode;
 120 typedef enum CmaskAddr {
 121         CMASK_ADDR_TILED                                 = 0x0,
 122         CMASK_ADDR_LINEAR                                = 0x1,
 123         CMASK_ADDR_COMPATIBLE                            = 0x2,
 124 } CmaskAddr;
 125 typedef enum CBPerfSel {
 126         CB_PERF_SEL_NONE                                 = 0x0,
 127         CB_PERF_SEL_BUSY                                 = 0x1,
 128         CB_PERF_SEL_CORE_SCLK_VLD                        = 0x2,
 129         CB_PERF_SEL_REG_SCLK0_VLD                        = 0x3,
 130         CB_PERF_SEL_REG_SCLK1_VLD                        = 0x4,
 131         CB_PERF_SEL_DRAWN_QUAD                           = 0x5,
 132         CB_PERF_SEL_DRAWN_PIXEL                          = 0x6,
 133         CB_PERF_SEL_DRAWN_QUAD_FRAGMENT                  = 0x7,
 134         CB_PERF_SEL_DRAWN_TILE                           = 0x8,
 135         CB_PERF_SEL_DB_CB_TILE_VALID_READY               = 0x9,
 136         CB_PERF_SEL_DB_CB_TILE_VALID_READYB              = 0xa,
 137         CB_PERF_SEL_DB_CB_TILE_VALIDB_READY              = 0xb,
 138         CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB             = 0xc,
 139         CB_PERF_SEL_CM_FC_TILE_VALID_READY               = 0xd,
 140         CB_PERF_SEL_CM_FC_TILE_VALID_READYB              = 0xe,
 141         CB_PERF_SEL_CM_FC_TILE_VALIDB_READY              = 0xf,
 142         CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB             = 0x10,
 143         CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY          = 0x11,
 144         CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB         = 0x12,
 145         CB_PERF_SEL_DB_CB_LQUAD_VALID_READY              = 0x13,
 146         CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB             = 0x14,
 147         CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY             = 0x15,
 148         CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB            = 0x16,
 149         CB_PERF_SEL_LQUAD_NO_TILE                        = 0x17,
 150         CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R          = 0x18,
 151         CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR         = 0x19,
 152         CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR         = 0x1a,
 153         CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR       = 0x1b,
 154         CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR     = 0x1c,
 155         CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 0x1d,
 156         CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR= 0x1e,
 157         CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT    = 0x1f,
 158         CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID         = 0x20,
 159         CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK= 0x21,
 160         CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK      = 0x22,
 161         CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL         = 0x23,
 162         CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY            = 0x24,
 163         CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB           = 0x25,
 164         CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY           = 0x26,
 165         CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB          = 0x27,
 166         CB_PERF_SEL_FOP_IN_VALID_READY                   = 0x28,
 167         CB_PERF_SEL_FOP_IN_VALID_READYB                  = 0x29,
 168         CB_PERF_SEL_FOP_IN_VALIDB_READY                  = 0x2a,
 169         CB_PERF_SEL_FOP_IN_VALIDB_READYB                 = 0x2b,
 170         CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY           = 0x2c,
 171         CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB          = 0x2d,
 172         CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY          = 0x2e,
 173         CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB         = 0x2f,
 174         CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY            = 0x30,
 175         CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB           = 0x31,
 176         CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY           = 0x32,
 177         CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB          = 0x33,
 178         CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY            = 0x34,
 179         CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB           = 0x35,
 180         CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY           = 0x36,
 181         CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB          = 0x37,
 182         CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY        = 0x38,
 183         CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB       = 0x39,
 184         CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY       = 0x3a,
 185         CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB      = 0x3b,
 186         CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY         = 0x3c,
 187         CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB        = 0x3d,
 188         CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY        = 0x3e,
 189         CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB       = 0x3f,
 190         CB_PERF_SEL_CC_BC_CS_FRAG_VALID                  = 0x40,
 191         CB_PERF_SEL_CM_CACHE_HIT                         = 0x41,
 192         CB_PERF_SEL_CM_CACHE_TAG_MISS                    = 0x42,
 193         CB_PERF_SEL_CM_CACHE_SECTOR_MISS                 = 0x43,
 194         CB_PERF_SEL_CM_CACHE_REEVICTION_STALL            = 0x44,
 195         CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x45,
 196         CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL = 0x46,
 197         CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x47,
 198         CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL           = 0x48,
 199         CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL          = 0x49,
 200         CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL            = 0x4a,
 201         CB_PERF_SEL_CM_CACHE_STALL                       = 0x4b,
 202         CB_PERF_SEL_CM_CACHE_FLUSH                       = 0x4c,
 203         CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED                = 0x4d,
 204         CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED             = 0x4e,
 205         CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED       = 0x4f,
 206         CB_PERF_SEL_FC_CACHE_HIT                         = 0x50,
 207         CB_PERF_SEL_FC_CACHE_TAG_MISS                    = 0x51,
 208         CB_PERF_SEL_FC_CACHE_SECTOR_MISS                 = 0x52,
 209         CB_PERF_SEL_FC_CACHE_REEVICTION_STALL            = 0x53,
 210         CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x54,
 211         CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x55,
 212         CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x56,
 213         CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL           = 0x57,
 214         CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL          = 0x58,
 215         CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL            = 0x59,
 216         CB_PERF_SEL_FC_CACHE_STALL                       = 0x5a,
 217         CB_PERF_SEL_FC_CACHE_FLUSH                       = 0x5b,
 218         CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED                = 0x5c,
 219         CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED             = 0x5d,
 220         CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED       = 0x5e,
 221         CB_PERF_SEL_CC_CACHE_HIT                         = 0x5f,
 222         CB_PERF_SEL_CC_CACHE_TAG_MISS                    = 0x60,
 223         CB_PERF_SEL_CC_CACHE_SECTOR_MISS                 = 0x61,
 224         CB_PERF_SEL_CC_CACHE_REEVICTION_STALL            = 0x62,
 225         CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x63,
 226         CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x64,
 227         CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x65,
 228         CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL           = 0x66,
 229         CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL          = 0x67,
 230         CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL            = 0x68,
 231         CB_PERF_SEL_CC_CACHE_STALL                       = 0x69,
 232         CB_PERF_SEL_CC_CACHE_FLUSH                       = 0x6a,
 233         CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED                = 0x6b,
 234         CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED             = 0x6c,
 235         CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED       = 0x6d,
 236         CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION        = 0x6e,
 237         CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC      = 0x6f,
 238         CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY             = 0x70,
 239         CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB            = 0x71,
 240         CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY            = 0x72,
 241         CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB           = 0x73,
 242         CB_PERF_SEL_CM_MC_WRITE_REQUEST                  = 0x74,
 243         CB_PERF_SEL_FC_MC_WRITE_REQUEST                  = 0x75,
 244         CB_PERF_SEL_CC_MC_WRITE_REQUEST                  = 0x76,
 245         CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT       = 0x77,
 246         CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT       = 0x78,
 247         CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT       = 0x79,
 248         CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY             = 0x7a,
 249         CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB            = 0x7b,
 250         CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY            = 0x7c,
 251         CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB           = 0x7d,
 252         CB_PERF_SEL_CM_MC_READ_REQUEST                   = 0x7e,
 253         CB_PERF_SEL_FC_MC_READ_REQUEST                   = 0x7f,
 254         CB_PERF_SEL_CC_MC_READ_REQUEST                   = 0x80,
 255         CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT        = 0x81,
 256         CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT        = 0x82,
 257         CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT        = 0x83,
 258         CB_PERF_SEL_CM_TQ_FULL                           = 0x84,
 259         CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL      = 0x85,
 260         CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL              = 0x86,
 261         CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL              = 0x87,
 262         CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL   = 0x88,
 263         CB_PERF_SEL_FOP_FMASK_RAW_STALL                  = 0x89,
 264         CB_PERF_SEL_FOP_FMASK_BYPASS_STALL               = 0x8a,
 265         CB_PERF_SEL_CC_SF_FULL                           = 0x8b,
 266         CB_PERF_SEL_CC_RB_FULL                           = 0x8c,
 267         CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL     = 0x8d,
 268         CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL      = 0x8e,
 269         CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL             = 0x8f,
 270         CB_PERF_SEL_EVENT                                = 0x90,
 271         CB_PERF_SEL_EVENT_CACHE_FLUSH_TS                 = 0x91,
 272         CB_PERF_SEL_EVENT_CONTEXT_DONE                   = 0x92,
 273         CB_PERF_SEL_EVENT_CACHE_FLUSH                    = 0x93,
 274         CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT   = 0x94,
 275         CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT      = 0x95,
 276         CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS       = 0x96,
 277         CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META          = 0x97,
 278         CB_PERF_SEL_CC_SURFACE_SYNC                      = 0x98,
 279         CB_PERF_SEL_CMASK_READ_DATA_0xC                  = 0x99,
 280         CB_PERF_SEL_CMASK_READ_DATA_0xD                  = 0x9a,
 281         CB_PERF_SEL_CMASK_READ_DATA_0xE                  = 0x9b,
 282         CB_PERF_SEL_CMASK_READ_DATA_0xF                  = 0x9c,
 283         CB_PERF_SEL_CMASK_WRITE_DATA_0xC                 = 0x9d,
 284         CB_PERF_SEL_CMASK_WRITE_DATA_0xD                 = 0x9e,
 285         CB_PERF_SEL_CMASK_WRITE_DATA_0xE                 = 0x9f,
 286         CB_PERF_SEL_CMASK_WRITE_DATA_0xF                 = 0xa0,
 287         CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT              = 0xa1,
 288         CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT         = 0xa2,
 289         CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT      = 0xa3,
 290         CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE    = 0xa4,
 291         CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE   = 0xa5,
 292         CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE   = 0xa6,
 293         CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE   = 0xa7,
 294         CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE   = 0xa8,
 295         CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE   = 0xa9,
 296         CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE   = 0xaa,
 297         CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE   = 0xab,
 298         CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE     = 0xac,
 299         CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE    = 0xad,
 300         CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE    = 0xae,
 301         CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE    = 0xaf,
 302         CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE    = 0xb0,
 303         CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE    = 0xb1,
 304         CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE    = 0xb2,
 305         CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE    = 0xb3,
 306         CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT                = 0xb4,
 307         CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS               = 0xb5,
 308         CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS               = 0xb6,
 309         CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS               = 0xb7,
 310         CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS               = 0xb8,
 311         CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS               = 0xb9,
 312         CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS               = 0xba,
 313         CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT              = 0xbb,
 314         CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS             = 0xbc,
 315         CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS             = 0xbd,
 316         CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS             = 0xbe,
 317         CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS             = 0xbf,
 318         CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS             = 0xc0,
 319         CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS             = 0xc1,
 320         CB_PERF_SEL_QUAD_READS_FRAGMENT_0                = 0xc2,
 321         CB_PERF_SEL_QUAD_READS_FRAGMENT_1                = 0xc3,
 322         CB_PERF_SEL_QUAD_READS_FRAGMENT_2                = 0xc4,
 323         CB_PERF_SEL_QUAD_READS_FRAGMENT_3                = 0xc5,
 324         CB_PERF_SEL_QUAD_READS_FRAGMENT_4                = 0xc6,
 325         CB_PERF_SEL_QUAD_READS_FRAGMENT_5                = 0xc7,
 326         CB_PERF_SEL_QUAD_READS_FRAGMENT_6                = 0xc8,
 327         CB_PERF_SEL_QUAD_READS_FRAGMENT_7                = 0xc9,
 328         CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0               = 0xca,
 329         CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1               = 0xcb,
 330         CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2               = 0xcc,
 331         CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3               = 0xcd,
 332         CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4               = 0xce,
 333         CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5               = 0xcf,
 334         CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6               = 0xd0,
 335         CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7               = 0xd1,
 336         CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST         = 0xd2,
 337         CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS          = 0xd3,
 338         CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS        = 0xd4,
 339         CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED= 0xd5,
 340         CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED= 0xd6,
 341         CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED       = 0xd7,
 342         CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST      = 0xd8,
 343         CB_PERF_SEL_DRAWN_BUSY                           = 0xd9,
 344         CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY              = 0xda,
 345         CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY               = 0xdb,
 346         CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY               = 0xdc,
 347         CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY               = 0xdd,
 348         CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED= 0xde,
 349         CB_PERF_SEL_FC_SEQUENCER_CLEAR                   = 0xdf,
 350         CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR    = 0xe0,
 351         CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS        = 0xe1,
 352         CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE= 0xe2,
 353         CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL             = 0xe3,
 354         CB_PERF_SEL_FC_DOC_IS_STALLED                    = 0xe4,
 355         CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED             = 0xe5,
 356         CB_PERF_SEL_FC_DOC_MRTS_COMBINED                 = 0xe6,
 357         CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS                = 0xe7,
 358         CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT                 = 0xe8,
 359         CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS                = 0xe9,
 360         CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT                 = 0xea,
 361         CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL         = 0xeb,
 362         CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR            = 0xec,
 363         CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS           = 0xed,
 364         CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS           = 0xee,
 365         CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS           = 0xef,
 366         CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS     = 0xf0,
 367         CB_PERF_SEL_FC_DCC_CACHE_HIT                     = 0xf1,
 368         CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS                = 0xf2,
 369         CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS             = 0xf3,
 370         CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL        = 0xf4,
 371         CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0xf5,
 372         CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL= 0xf6,
 373         CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0xf7,
 374         CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL       = 0xf8,
 375         CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL      = 0xf9,
 376         CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL        = 0xfa,
 377         CB_PERF_SEL_FC_DCC_CACHE_STALL                   = 0xfb,
 378         CB_PERF_SEL_FC_DCC_CACHE_FLUSH                   = 0xfc,
 379         CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED            = 0xfd,
 380         CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED         = 0xfe,
 381         CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED   = 0xff,
 382         CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT             = 0x100,
 383         CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST              = 0x101,
 384         CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT   = 0x102,
 385         CB_PERF_SEL_FC_MC_DCC_READ_REQUEST               = 0x103,
 386         CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT    = 0x104,
 387         CB_PERF_SEL_CC_DCC_RDREQ_STALL                   = 0x105,
 388         CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN            = 0x106,
 389         CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT           = 0x107,
 390         CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN              = 0x108,
 391         CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT             = 0x109,
 392         CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR              = 0x10a,
 393         CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1     = 0x10b,
 394         CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2= 0x10c,
 395         CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1= 0x10d,
 396         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1= 0x10e,
 397         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1= 0x10f,
 398         CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2= 0x110,
 399         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1= 0x111,
 400         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2= 0x112,
 401         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1= 0x113,
 402         CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1= 0x114,
 403         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2= 0x115,
 404         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2= 0x116,
 405         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2= 0x117,
 406         CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2= 0x118,
 407         CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1= 0x119,
 408         CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1       = 0x11a,
 409         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2= 0x11b,
 410         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3= 0x11c,
 411         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4= 0x11d,
 412         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1= 0x11e,
 413         CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2       = 0x11f,
 414         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3= 0x120,
 415         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4= 0x121,
 416         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1= 0x122,
 417         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2= 0x123,
 418         CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3       = 0x124,
 419         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4= 0x125,
 420         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1= 0x126,
 421         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2= 0x127,
 422         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3= 0x128,
 423         CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1= 0x129,
 424         CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2= 0x12a,
 425         CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3= 0x12b,
 426         CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4= 0x12c,
 427         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1= 0x12d,
 428         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2= 0x12e,
 429         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3= 0x12f,
 430         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4= 0x130,
 431         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1= 0x131,
 432         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2= 0x132,
 433         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3= 0x133,
 434         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4= 0x134,
 435         CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1= 0x135,
 436         CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2= 0x136,
 437         CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3= 0x137,
 438         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1= 0x138,
 439         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1= 0x139,
 440         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1= 0x13a,
 441         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1= 0x13b,
 442         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1= 0x13c,
 443         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1= 0x13d,
 444         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1= 0x13e,
 445         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1= 0x13f,
 446         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2= 0x140,
 447         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2= 0x141,
 448         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2= 0x142,
 449         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2= 0x143,
 450         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2= 0x144,
 451         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2= 0x145,
 452         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2= 0x146,
 453         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1= 0x147,
 454         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1= 0x148,
 455         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1= 0x149,
 456         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1= 0x14a,
 457         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2= 0x14b,
 458         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2= 0x14c,
 459         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2= 0x14d,
 460         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2= 0x14e,
 461         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2= 0x14f,
 462         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2= 0x150,
 463         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2= 0x151,
 464         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1= 0x152,
 465         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1= 0x153,
 466         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1= 0x154,
 467         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1= 0x155,
 468         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1= 0x156,
 469         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2= 0x157,
 470         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3= 0x158,
 471         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4= 0x159,
 472         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5= 0x15a,
 473         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6= 0x15b,
 474         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0  = 0x15c,
 475         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1  = 0x15d,
 476         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1= 0x15e,
 477         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2= 0x15f,
 478         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3= 0x160,
 479         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4= 0x161,
 480         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5= 0x162,
 481         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0  = 0x163,
 482         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1  = 0x164,
 483         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1= 0x165,
 484         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1= 0x166,
 485         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1= 0x167,
 486         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1= 0x168,
 487         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1= 0x169,
 488         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1= 0x16a,
 489         CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1  = 0x16b,
 490         CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1  = 0x16c,
 491         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2= 0x16d,
 492         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2= 0x16e,
 493         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2= 0x16f,
 494         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2= 0x170,
 495         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2= 0x171,
 496         CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2  = 0x172,
 497         CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2  = 0x173,
 498         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1        = 0x174,
 499         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2        = 0x175,
 500         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3        = 0x176,
 501         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4        = 0x177,
 502         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5        = 0x178,
 503         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6        = 0x179,
 504         CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7        = 0x17a,
 505         CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED       = 0x17b,
 506         CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1           = 0x17c,
 507         CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1           = 0x17d,
 508         CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2           = 0x17e,
 509         CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3           = 0x17f,
 510         CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1           = 0x180,
 511         CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2           = 0x181,
 512         CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3           = 0x182,
 513         CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4           = 0x183,
 514         CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5           = 0x184,
 515         CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1           = 0x185,
 516         CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2           = 0x186,
 517         CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3           = 0x187,
 518         CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4           = 0x188,
 519         CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5           = 0x189,
 520         CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6           = 0x18a,
 521         CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7           = 0x18b,
 522         CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH             = 0x18c,
 523         CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT             = 0x18d,
 524         CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT            = 0x18e,
 525         CB_PERF_SEL_RBP_SPLIT_MICROTILE                  = 0x18f,
 526         CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK             = 0x190,
 527         CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK        = 0x191,
 528         CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING          = 0x192,
 529         CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS       = 0x193,
 530         CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD         = 0x194,
 531 } CBPerfSel;
 532 typedef enum CBPerfOpFilterSel {
 533         CB_PERF_OP_FILTER_SEL_WRITE_ONLY                 = 0x0,
 534         CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION          = 0x1,
 535         CB_PERF_OP_FILTER_SEL_RESOLVE                    = 0x2,
 536         CB_PERF_OP_FILTER_SEL_DECOMPRESS                 = 0x3,
 537         CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS           = 0x4,
 538         CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR       = 0x5,
 539 } CBPerfOpFilterSel;
 540 typedef enum CBPerfClearFilterSel {
 541         CB_PERF_CLEAR_FILTER_SEL_NONCLEAR                = 0x0,
 542         CB_PERF_CLEAR_FILTER_SEL_CLEAR                   = 0x1,
 543 } CBPerfClearFilterSel;
 544 typedef enum CP_RING_ID {
 545         RINGID0                                          = 0x0,
 546         RINGID1                                          = 0x1,
 547         RINGID2                                          = 0x2,
 548         RINGID3                                          = 0x3,
 549 } CP_RING_ID;
 550 typedef enum CP_PIPE_ID {
 551         PIPE_ID0                                         = 0x0,
 552         PIPE_ID1                                         = 0x1,
 553         PIPE_ID2                                         = 0x2,
 554         PIPE_ID3                                         = 0x3,
 555 } CP_PIPE_ID;
 556 typedef enum CP_ME_ID {
 557         ME_ID0                                           = 0x0,
 558         ME_ID1                                           = 0x1,
 559         ME_ID2                                           = 0x2,
 560         ME_ID3                                           = 0x3,
 561 } CP_ME_ID;
 562 typedef enum SPM_PERFMON_STATE {
 563         STRM_PERFMON_STATE_DISABLE_AND_RESET             = 0x0,
 564         STRM_PERFMON_STATE_START_COUNTING                = 0x1,
 565         STRM_PERFMON_STATE_STOP_COUNTING                 = 0x2,
 566         STRM_PERFMON_STATE_RESERVED_3                    = 0x3,
 567         STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM     = 0x4,
 568         STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM        = 0x5,
 569 } SPM_PERFMON_STATE;
 570 typedef enum CP_PERFMON_STATE {
 571         CP_PERFMON_STATE_DISABLE_AND_RESET               = 0x0,
 572         CP_PERFMON_STATE_START_COUNTING                  = 0x1,
 573         CP_PERFMON_STATE_STOP_COUNTING                   = 0x2,
 574         CP_PERFMON_STATE_RESERVED_3                      = 0x3,
 575         CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM       = 0x4,
 576         CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM          = 0x5,
 577 } CP_PERFMON_STATE;
 578 typedef enum CP_PERFMON_ENABLE_MODE {
 579         CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT              = 0x0,
 580         CP_PERFMON_ENABLE_MODE_RESERVED_1                = 0x1,
 581         CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE        = 0x2,
 582         CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE       = 0x3,
 583 } CP_PERFMON_ENABLE_MODE;
 584 typedef enum CPG_PERFCOUNT_SEL {
 585         CPG_PERF_SEL_ALWAYS_COUNT                        = 0x0,
 586         CPG_PERF_SEL_RBIU_FIFO_FULL                      = 0x1,
 587         CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR             = 0x2,
 588         CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL          = 0x3,
 589         CPG_PERF_SEL_CP_GRBM_DWORDS_SENT                 = 0x4,
 590         CPG_PERF_SEL_ME_PARSER_BUSY                      = 0x5,
 591         CPG_PERF_SEL_COUNT_TYPE0_PACKETS                 = 0x6,
 592         CPG_PERF_SEL_COUNT_TYPE3_PACKETS                 = 0x7,
 593         CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS            = 0x8,
 594         CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS              = 0x9,
 595         CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS          = 0xa,
 596         CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS          = 0xb,
 597         CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ             = 0xc,
 598         CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ            = 0xd,
 599         CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX          = 0xe,
 600         CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS        = 0xf,
 601         CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE        = 0x10,
 602         CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM   = 0x11,
 603         CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY            = 0x12,
 604         CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY            = 0x13,
 605         CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY           = 0x14,
 606         CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ       = 0x15,
 607         CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP        = 0x16,
 608         CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ        = 0x17,
 609         CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX     = 0x18,
 610         CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU          = 0x19,
 611         CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS        = 0x1a,
 612         CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH         = 0x1b,
 613         CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER               = 0x1c,
 614         CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER             = 0x1d,
 615         CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS     = 0x1e,
 616         CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY       = 0x1f,
 617         CPG_PERF_SEL_DYNAMIC_CLK_VALID                   = 0x20,
 618         CPG_PERF_SEL_REGISTER_CLK_VALID                  = 0x21,
 619         CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT              = 0x22,
 620         CPG_PERF_SEL_MIU_READ_REQUEST_SENT               = 0x23,
 621         CPG_PERF_SEL_CE_STALL_RAM_DUMP                   = 0x24,
 622         CPG_PERF_SEL_CE_STALL_RAM_WRITE                  = 0x25,
 623         CPG_PERF_SEL_CE_STALL_ON_INC_FIFO                = 0x26,
 624         CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO             = 0x27,
 625         CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU           = 0x28,
 626         CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ           = 0x29,
 627         CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG          = 0x2a,
 628         CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER              = 0x2b,
 629         CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE             = 0x2c,
 630         CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS             = 0x2d,
 631         CPG_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE          = 0x2e,
 632         CPG_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS          = 0x2f,
 633         CPG_PERF_SEL_ATCL1_STALL_ON_TRANSLATION          = 0x30,
 634 } CPG_PERFCOUNT_SEL;
 635 typedef enum CPF_PERFCOUNT_SEL {
 636         CPF_PERF_SEL_ALWAYS_COUNT                        = 0x0,
 637         CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE      = 0x1,
 638         CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE        = 0x2,
 639         CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS        = 0x3,
 640         CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING          = 0x4,
 641         CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1           = 0x5,
 642         CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2           = 0x6,
 643         CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE         = 0x7,
 644         CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS       = 0x8,
 645         CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR                 = 0x9,
 646         CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR              = 0xa,
 647         CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS            = 0xb,
 648         CPF_PERF_SEL_GRBM_DWORDS_SENT                    = 0xc,
 649         CPF_PERF_SEL_DYNAMIC_CLOCK_VALID                 = 0xd,
 650         CPF_PERF_SEL_REGISTER_CLOCK_VALID                = 0xe,
 651         CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND              = 0xf,
 652         CPF_PERF_SEL_MIU_READ_REQUEST_SEND               = 0x10,
 653         CPF_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE          = 0x11,
 654         CPF_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS          = 0x12,
 655         CPF_PERF_SEL_ATCL1_STALL_ON_TRANSLATION          = 0x13,
 656 } CPF_PERFCOUNT_SEL;
 657 typedef enum CPC_PERFCOUNT_SEL {
 658         CPC_PERF_SEL_ALWAYS_COUNT                        = 0x0,
 659         CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE             = 0x1,
 660         CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION           = 0x2,
 661         CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE             = 0x3,
 662         CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE             = 0x4,
 663         CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE             = 0x5,
 664         CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY        = 0x6,
 665         CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF   = 0x7,
 666         CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ         = 0x8,
 667         CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ          = 0x9,
 668         CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE         = 0xa,
 669         CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ          = 0xb,
 670         CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF     = 0xc,
 671         CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE          = 0xd,
 672         CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY        = 0xe,
 673         CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF   = 0xf,
 674         CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ         = 0x10,
 675         CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ          = 0x11,
 676         CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE         = 0x12,
 677         CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ          = 0x13,
 678         CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF     = 0x14,
 679         CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE          = 0x15,
 680         CPC_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE          = 0x16,
 681         CPC_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS          = 0x17,
 682         CPC_PERF_SEL_ATCL1_STALL_ON_TRANSLATION          = 0x18,
 683 } CPC_PERFCOUNT_SEL;
 684 typedef enum CP_ALPHA_TAG_RAM_SEL {
 685         CPG_TAG_RAM                                      = 0x0,
 686         CPC_TAG_RAM                                      = 0x1,
 687         CPF_TAG_RAM                                      = 0x2,
 688         RSV_TAG_RAM                                      = 0x3,
 689 } CP_ALPHA_TAG_RAM_SEL;
 690 #define SEM_ECC_ERROR                             0x0
 691 #define SEM_RESERVED                              0x1
 692 #define SEM_FAILED                                0x2
 693 #define SEM_PASSED                                0x3
 694 #define IQ_QUEUE_SLEEP                            0x0
 695 #define IQ_OFFLOAD_RETRY                          0x1
 696 #define IQ_SCH_WAVE_MSG                           0x2
 697 #define IQ_SEM_REARM                              0x3
 698 #define IQ_DEQUEUE_RETRY                          0x4
 699 #define IQ_INTR_TYPE_PQ                           0x0
 700 #define IQ_INTR_TYPE_IB                           0x1
 701 #define IQ_INTR_TYPE_MQD                          0x2
 702 #define VMID_SZ                                   0x4
 703 #define CONFIG_SPACE_START                        0x2000
 704 #define CONFIG_SPACE_END                          0x9fff
 705 #define CONFIG_SPACE1_START                       0x2000
 706 #define CONFIG_SPACE1_END                         0x2bff
 707 #define CONFIG_SPACE2_START                       0x3000
 708 #define CONFIG_SPACE2_END                         0x9fff
 709 #define UCONFIG_SPACE_START                       0xc000
 710 #define UCONFIG_SPACE_END                         0xffff
 711 #define PERSISTENT_SPACE_START                    0x2c00
 712 #define PERSISTENT_SPACE_END                      0x2fff
 713 #define CONTEXT_SPACE_START                       0xa000
 714 #define CONTEXT_SPACE_END                         0xbfff
 715 typedef enum ForceControl {
 716         FORCE_OFF                                        = 0x0,
 717         FORCE_ENABLE                                     = 0x1,
 718         FORCE_DISABLE                                    = 0x2,
 719         FORCE_RESERVED                                   = 0x3,
 720 } ForceControl;
 721 typedef enum ZSamplePosition {
 722         Z_SAMPLE_CENTER                                  = 0x0,
 723         Z_SAMPLE_CENTROID                                = 0x1,
 724 } ZSamplePosition;
 725 typedef enum ZOrder {
 726         LATE_Z                                           = 0x0,
 727         EARLY_Z_THEN_LATE_Z                              = 0x1,
 728         RE_Z                                             = 0x2,
 729         EARLY_Z_THEN_RE_Z                                = 0x3,
 730 } ZOrder;
 731 typedef enum ZpassControl {
 732         ZPASS_DISABLE                                    = 0x0,
 733         ZPASS_SAMPLES                                    = 0x1,
 734         ZPASS_PIXELS                                     = 0x2,
 735 } ZpassControl;
 736 typedef enum ZModeForce {
 737         NO_FORCE                                         = 0x0,
 738         FORCE_EARLY_Z                                    = 0x1,
 739         FORCE_LATE_Z                                     = 0x2,
 740         FORCE_RE_Z                                       = 0x3,
 741 } ZModeForce;
 742 typedef enum ZLimitSumm {
 743         FORCE_SUMM_OFF                                   = 0x0,
 744         FORCE_SUMM_MINZ                                  = 0x1,
 745         FORCE_SUMM_MAXZ                                  = 0x2,
 746         FORCE_SUMM_BOTH                                  = 0x3,
 747 } ZLimitSumm;
 748 typedef enum CompareFrag {
 749         FRAG_NEVER                                       = 0x0,
 750         FRAG_LESS                                        = 0x1,
 751         FRAG_EQUAL                                       = 0x2,
 752         FRAG_LEQUAL                                      = 0x3,
 753         FRAG_GREATER                                     = 0x4,
 754         FRAG_NOTEQUAL                                    = 0x5,
 755         FRAG_GEQUAL                                      = 0x6,
 756         FRAG_ALWAYS                                      = 0x7,
 757 } CompareFrag;
 758 typedef enum StencilOp {
 759         STENCIL_KEEP                                     = 0x0,
 760         STENCIL_ZERO                                     = 0x1,
 761         STENCIL_ONES                                     = 0x2,
 762         STENCIL_REPLACE_TEST                             = 0x3,
 763         STENCIL_REPLACE_OP                               = 0x4,
 764         STENCIL_ADD_CLAMP                                = 0x5,
 765         STENCIL_SUB_CLAMP                                = 0x6,
 766         STENCIL_INVERT                                   = 0x7,
 767         STENCIL_ADD_WRAP                                 = 0x8,
 768         STENCIL_SUB_WRAP                                 = 0x9,
 769         STENCIL_AND                                      = 0xa,
 770         STENCIL_OR                                       = 0xb,
 771         STENCIL_XOR                                      = 0xc,
 772         STENCIL_NAND                                     = 0xd,
 773         STENCIL_NOR                                      = 0xe,
 774         STENCIL_XNOR                                     = 0xf,
 775 } StencilOp;
 776 typedef enum ConservativeZExport {
 777         EXPORT_ANY_Z                                     = 0x0,
 778         EXPORT_LESS_THAN_Z                               = 0x1,
 779         EXPORT_GREATER_THAN_Z                            = 0x2,
 780         EXPORT_RESERVED                                  = 0x3,
 781 } ConservativeZExport;
 782 typedef enum DbPSLControl {
 783         PSLC_AUTO                                        = 0x0,
 784         PSLC_ON_HANG_ONLY                                = 0x1,
 785         PSLC_ASAP                                        = 0x2,
 786         PSLC_COUNTDOWN                                   = 0x3,
 787 } DbPSLControl;
 788 typedef enum PerfCounter_Vals {
 789         DB_PERF_SEL_SC_DB_tile_sends                     = 0x0,
 790         DB_PERF_SEL_SC_DB_tile_busy                      = 0x1,
 791         DB_PERF_SEL_SC_DB_tile_stalls                    = 0x2,
 792         DB_PERF_SEL_SC_DB_tile_events                    = 0x3,
 793         DB_PERF_SEL_SC_DB_tile_tiles                     = 0x4,
 794         DB_PERF_SEL_SC_DB_tile_covered                   = 0x5,
 795         DB_PERF_SEL_hiz_tc_read_starved                  = 0x6,
 796         DB_PERF_SEL_hiz_tc_write_stall                   = 0x7,
 797         DB_PERF_SEL_hiz_qtiles_culled                    = 0x8,
 798         DB_PERF_SEL_his_qtiles_culled                    = 0x9,
 799         DB_PERF_SEL_DB_SC_tile_sends                     = 0xa,
 800         DB_PERF_SEL_DB_SC_tile_busy                      = 0xb,
 801         DB_PERF_SEL_DB_SC_tile_stalls                    = 0xc,
 802         DB_PERF_SEL_DB_SC_tile_df_stalls                 = 0xd,
 803         DB_PERF_SEL_DB_SC_tile_tiles                     = 0xe,
 804         DB_PERF_SEL_DB_SC_tile_culled                    = 0xf,
 805         DB_PERF_SEL_DB_SC_tile_hier_kill                 = 0x10,
 806         DB_PERF_SEL_DB_SC_tile_fast_ops                  = 0x11,
 807         DB_PERF_SEL_DB_SC_tile_no_ops                    = 0x12,
 808         DB_PERF_SEL_DB_SC_tile_tile_rate                 = 0x13,
 809         DB_PERF_SEL_DB_SC_tile_ssaa_kill                 = 0x14,
 810         DB_PERF_SEL_DB_SC_tile_fast_z_ops                = 0x15,
 811         DB_PERF_SEL_DB_SC_tile_fast_stencil_ops          = 0x16,
 812         DB_PERF_SEL_SC_DB_quad_sends                     = 0x17,
 813         DB_PERF_SEL_SC_DB_quad_busy                      = 0x18,
 814         DB_PERF_SEL_SC_DB_quad_squads                    = 0x19,
 815         DB_PERF_SEL_SC_DB_quad_tiles                     = 0x1a,
 816         DB_PERF_SEL_SC_DB_quad_pixels                    = 0x1b,
 817         DB_PERF_SEL_SC_DB_quad_killed_tiles              = 0x1c,
 818         DB_PERF_SEL_DB_SC_quad_sends                     = 0x1d,
 819         DB_PERF_SEL_DB_SC_quad_busy                      = 0x1e,
 820         DB_PERF_SEL_DB_SC_quad_stalls                    = 0x1f,
 821         DB_PERF_SEL_DB_SC_quad_tiles                     = 0x20,
 822         DB_PERF_SEL_DB_SC_quad_lit_quad                  = 0x21,
 823         DB_PERF_SEL_DB_CB_tile_sends                     = 0x22,
 824         DB_PERF_SEL_DB_CB_tile_busy                      = 0x23,
 825         DB_PERF_SEL_DB_CB_tile_stalls                    = 0x24,
 826         DB_PERF_SEL_SX_DB_quad_sends                     = 0x25,
 827         DB_PERF_SEL_SX_DB_quad_busy                      = 0x26,
 828         DB_PERF_SEL_SX_DB_quad_stalls                    = 0x27,
 829         DB_PERF_SEL_SX_DB_quad_quads                     = 0x28,
 830         DB_PERF_SEL_SX_DB_quad_pixels                    = 0x29,
 831         DB_PERF_SEL_SX_DB_quad_exports                   = 0x2a,
 832         DB_PERF_SEL_SH_quads_outstanding_sum             = 0x2b,
 833         DB_PERF_SEL_DB_CB_lquad_sends                    = 0x2c,
 834         DB_PERF_SEL_DB_CB_lquad_busy                     = 0x2d,
 835         DB_PERF_SEL_DB_CB_lquad_stalls                   = 0x2e,
 836         DB_PERF_SEL_DB_CB_lquad_quads                    = 0x2f,
 837         DB_PERF_SEL_tile_rd_sends                        = 0x30,
 838         DB_PERF_SEL_mi_tile_rd_outstanding_sum           = 0x31,
 839         DB_PERF_SEL_quad_rd_sends                        = 0x32,
 840         DB_PERF_SEL_quad_rd_busy                         = 0x33,
 841         DB_PERF_SEL_quad_rd_mi_stall                     = 0x34,
 842         DB_PERF_SEL_quad_rd_rw_collision                 = 0x35,
 843         DB_PERF_SEL_quad_rd_tag_stall                    = 0x36,
 844         DB_PERF_SEL_quad_rd_32byte_reqs                  = 0x37,
 845         DB_PERF_SEL_quad_rd_panic                        = 0x38,
 846         DB_PERF_SEL_mi_quad_rd_outstanding_sum           = 0x39,
 847         DB_PERF_SEL_quad_rdret_sends                     = 0x3a,
 848         DB_PERF_SEL_quad_rdret_busy                      = 0x3b,
 849         DB_PERF_SEL_tile_wr_sends                        = 0x3c,
 850         DB_PERF_SEL_tile_wr_acks                         = 0x3d,
 851         DB_PERF_SEL_mi_tile_wr_outstanding_sum           = 0x3e,
 852         DB_PERF_SEL_quad_wr_sends                        = 0x3f,
 853         DB_PERF_SEL_quad_wr_busy                         = 0x40,
 854         DB_PERF_SEL_quad_wr_mi_stall                     = 0x41,
 855         DB_PERF_SEL_quad_wr_coherency_stall              = 0x42,
 856         DB_PERF_SEL_quad_wr_acks                         = 0x43,
 857         DB_PERF_SEL_mi_quad_wr_outstanding_sum           = 0x44,
 858         DB_PERF_SEL_Tile_Cache_misses                    = 0x45,
 859         DB_PERF_SEL_Tile_Cache_hits                      = 0x46,
 860         DB_PERF_SEL_Tile_Cache_flushes                   = 0x47,
 861         DB_PERF_SEL_Tile_Cache_surface_stall             = 0x48,
 862         DB_PERF_SEL_Tile_Cache_starves                   = 0x49,
 863         DB_PERF_SEL_Tile_Cache_mem_return_starve         = 0x4a,
 864         DB_PERF_SEL_tcp_dispatcher_reads                 = 0x4b,
 865         DB_PERF_SEL_tcp_prefetcher_reads                 = 0x4c,
 866         DB_PERF_SEL_tcp_preloader_reads                  = 0x4d,
 867         DB_PERF_SEL_tcp_dispatcher_flushes               = 0x4e,
 868         DB_PERF_SEL_tcp_prefetcher_flushes               = 0x4f,
 869         DB_PERF_SEL_tcp_preloader_flushes                = 0x50,
 870         DB_PERF_SEL_Depth_Tile_Cache_sends               = 0x51,
 871         DB_PERF_SEL_Depth_Tile_Cache_busy                = 0x52,
 872         DB_PERF_SEL_Depth_Tile_Cache_starves             = 0x53,
 873         DB_PERF_SEL_Depth_Tile_Cache_dtile_locked        = 0x54,
 874         DB_PERF_SEL_Depth_Tile_Cache_alloc_stall         = 0x55,
 875         DB_PERF_SEL_Depth_Tile_Cache_misses              = 0x56,
 876         DB_PERF_SEL_Depth_Tile_Cache_hits                = 0x57,
 877         DB_PERF_SEL_Depth_Tile_Cache_flushes             = 0x58,
 878         DB_PERF_SEL_Depth_Tile_Cache_noop_tile           = 0x59,
 879         DB_PERF_SEL_Depth_Tile_Cache_detailed_noop       = 0x5a,
 880         DB_PERF_SEL_Depth_Tile_Cache_event               = 0x5b,
 881         DB_PERF_SEL_Depth_Tile_Cache_tile_frees          = 0x5c,
 882         DB_PERF_SEL_Depth_Tile_Cache_data_frees          = 0x5d,
 883         DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve   = 0x5e,
 884         DB_PERF_SEL_Stencil_Cache_misses                 = 0x5f,
 885         DB_PERF_SEL_Stencil_Cache_hits                   = 0x60,
 886         DB_PERF_SEL_Stencil_Cache_flushes                = 0x61,
 887         DB_PERF_SEL_Stencil_Cache_starves                = 0x62,
 888         DB_PERF_SEL_Stencil_Cache_frees                  = 0x63,
 889         DB_PERF_SEL_Z_Cache_separate_Z_misses            = 0x64,
 890         DB_PERF_SEL_Z_Cache_separate_Z_hits              = 0x65,
 891         DB_PERF_SEL_Z_Cache_separate_Z_flushes           = 0x66,
 892         DB_PERF_SEL_Z_Cache_separate_Z_starves           = 0x67,
 893         DB_PERF_SEL_Z_Cache_pmask_misses                 = 0x68,
 894         DB_PERF_SEL_Z_Cache_pmask_hits                   = 0x69,
 895         DB_PERF_SEL_Z_Cache_pmask_flushes                = 0x6a,
 896         DB_PERF_SEL_Z_Cache_pmask_starves                = 0x6b,
 897         DB_PERF_SEL_Z_Cache_frees                        = 0x6c,
 898         DB_PERF_SEL_Plane_Cache_misses                   = 0x6d,
 899         DB_PERF_SEL_Plane_Cache_hits                     = 0x6e,
 900         DB_PERF_SEL_Plane_Cache_flushes                  = 0x6f,
 901         DB_PERF_SEL_Plane_Cache_starves                  = 0x70,
 902         DB_PERF_SEL_Plane_Cache_frees                    = 0x71,
 903         DB_PERF_SEL_flush_expanded_stencil               = 0x72,
 904         DB_PERF_SEL_flush_compressed_stencil             = 0x73,
 905         DB_PERF_SEL_flush_single_stencil                 = 0x74,
 906         DB_PERF_SEL_planes_flushed                       = 0x75,
 907         DB_PERF_SEL_flush_1plane                         = 0x76,
 908         DB_PERF_SEL_flush_2plane                         = 0x77,
 909         DB_PERF_SEL_flush_3plane                         = 0x78,
 910         DB_PERF_SEL_flush_4plane                         = 0x79,
 911         DB_PERF_SEL_flush_5plane                         = 0x7a,
 912         DB_PERF_SEL_flush_6plane                         = 0x7b,
 913         DB_PERF_SEL_flush_7plane                         = 0x7c,
 914         DB_PERF_SEL_flush_8plane                         = 0x7d,
 915         DB_PERF_SEL_flush_9plane                         = 0x7e,
 916         DB_PERF_SEL_flush_10plane                        = 0x7f,
 917         DB_PERF_SEL_flush_11plane                        = 0x80,
 918         DB_PERF_SEL_flush_12plane                        = 0x81,
 919         DB_PERF_SEL_flush_13plane                        = 0x82,
 920         DB_PERF_SEL_flush_14plane                        = 0x83,
 921         DB_PERF_SEL_flush_15plane                        = 0x84,
 922         DB_PERF_SEL_flush_16plane                        = 0x85,
 923         DB_PERF_SEL_flush_expanded_z                     = 0x86,
 924         DB_PERF_SEL_earlyZ_waiting_for_postZ_done        = 0x87,
 925         DB_PERF_SEL_reZ_waiting_for_postZ_done           = 0x88,
 926         DB_PERF_SEL_dk_tile_sends                        = 0x89,
 927         DB_PERF_SEL_dk_tile_busy                         = 0x8a,
 928         DB_PERF_SEL_dk_tile_quad_starves                 = 0x8b,
 929         DB_PERF_SEL_dk_tile_stalls                       = 0x8c,
 930         DB_PERF_SEL_dk_squad_sends                       = 0x8d,
 931         DB_PERF_SEL_dk_squad_busy                        = 0x8e,
 932         DB_PERF_SEL_dk_squad_stalls                      = 0x8f,
 933         DB_PERF_SEL_Op_Pipe_Busy                         = 0x90,
 934         DB_PERF_SEL_Op_Pipe_MC_Read_stall                = 0x91,
 935         DB_PERF_SEL_qc_busy                              = 0x92,
 936         DB_PERF_SEL_qc_xfc                               = 0x93,
 937         DB_PERF_SEL_qc_conflicts                         = 0x94,
 938         DB_PERF_SEL_qc_full_stall                        = 0x95,
 939         DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ         = 0x96,
 940         DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ         = 0x97,
 941         DB_PERF_SEL_tsc_insert_summarize_stall           = 0x98,
 942         DB_PERF_SEL_tl_busy                              = 0x99,
 943         DB_PERF_SEL_tl_dtc_read_starved                  = 0x9a,
 944         DB_PERF_SEL_tl_z_fetch_stall                     = 0x9b,
 945         DB_PERF_SEL_tl_stencil_stall                     = 0x9c,
 946         DB_PERF_SEL_tl_z_decompress_stall                = 0x9d,
 947         DB_PERF_SEL_tl_stencil_locked_stall              = 0x9e,
 948         DB_PERF_SEL_tl_events                            = 0x9f,
 949         DB_PERF_SEL_tl_summarize_squads                  = 0xa0,
 950         DB_PERF_SEL_tl_flush_expand_squads               = 0xa1,
 951         DB_PERF_SEL_tl_expand_squads                     = 0xa2,
 952         DB_PERF_SEL_tl_preZ_squads                       = 0xa3,
 953         DB_PERF_SEL_tl_postZ_squads                      = 0xa4,
 954         DB_PERF_SEL_tl_preZ_noop_squads                  = 0xa5,
 955         DB_PERF_SEL_tl_postZ_noop_squads                 = 0xa6,
 956         DB_PERF_SEL_tl_tile_ops                          = 0xa7,
 957         DB_PERF_SEL_tl_in_xfc                            = 0xa8,
 958         DB_PERF_SEL_tl_in_single_stencil_expand_stall    = 0xa9,
 959         DB_PERF_SEL_tl_in_fast_z_stall                   = 0xaa,
 960         DB_PERF_SEL_tl_out_xfc                           = 0xab,
 961         DB_PERF_SEL_tl_out_squads                        = 0xac,
 962         DB_PERF_SEL_zf_plane_multicycle                  = 0xad,
 963         DB_PERF_SEL_PostZ_Samples_passing_Z              = 0xae,
 964         DB_PERF_SEL_PostZ_Samples_failing_Z              = 0xaf,
 965         DB_PERF_SEL_PostZ_Samples_failing_S              = 0xb0,
 966         DB_PERF_SEL_PreZ_Samples_passing_Z               = 0xb1,
 967         DB_PERF_SEL_PreZ_Samples_failing_Z               = 0xb2,
 968         DB_PERF_SEL_PreZ_Samples_failing_S               = 0xb3,
 969         DB_PERF_SEL_ts_tc_update_stall                   = 0xb4,
 970         DB_PERF_SEL_sc_kick_start                        = 0xb5,
 971         DB_PERF_SEL_sc_kick_end                          = 0xb6,
 972         DB_PERF_SEL_clock_reg_active                     = 0xb7,
 973         DB_PERF_SEL_clock_main_active                    = 0xb8,
 974         DB_PERF_SEL_clock_mem_export_active              = 0xb9,
 975         DB_PERF_SEL_esr_ps_out_busy                      = 0xba,
 976         DB_PERF_SEL_esr_ps_lqf_busy                      = 0xbb,
 977         DB_PERF_SEL_esr_ps_lqf_stall                     = 0xbc,
 978         DB_PERF_SEL_etr_out_send                         = 0xbd,
 979         DB_PERF_SEL_etr_out_busy                         = 0xbe,
 980         DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall  = 0xbf,
 981         DB_PERF_SEL_etr_out_cb_tile_stall                = 0xc0,
 982         DB_PERF_SEL_etr_out_esr_stall                    = 0xc1,
 983         DB_PERF_SEL_esr_ps_sqq_busy                      = 0xc2,
 984         DB_PERF_SEL_esr_ps_sqq_stall                     = 0xc3,
 985         DB_PERF_SEL_esr_eot_fwd_busy                     = 0xc4,
 986         DB_PERF_SEL_esr_eot_fwd_holding_squad            = 0xc5,
 987         DB_PERF_SEL_esr_eot_fwd_forward                  = 0xc6,
 988         DB_PERF_SEL_esr_sqq_zi_busy                      = 0xc7,
 989         DB_PERF_SEL_esr_sqq_zi_stall                     = 0xc8,
 990         DB_PERF_SEL_postzl_sq_pt_busy                    = 0xc9,
 991         DB_PERF_SEL_postzl_sq_pt_stall                   = 0xca,
 992         DB_PERF_SEL_postzl_se_busy                       = 0xcb,
 993         DB_PERF_SEL_postzl_se_stall                      = 0xcc,
 994         DB_PERF_SEL_postzl_partial_launch                = 0xcd,
 995         DB_PERF_SEL_postzl_full_launch                   = 0xce,
 996         DB_PERF_SEL_postzl_partial_waiting               = 0xcf,
 997         DB_PERF_SEL_postzl_tile_mem_stall                = 0xd0,
 998         DB_PERF_SEL_postzl_tile_init_stall               = 0xd1,
 999         DB_PEFF_SEL_prezl_tile_mem_stall                 = 0xd2,
1000         DB_PERF_SEL_prezl_tile_init_stall                = 0xd3,
1001         DB_PERF_SEL_dtt_sm_clash_stall                   = 0xd4,
1002         DB_PERF_SEL_dtt_sm_slot_stall                    = 0xd5,
1003         DB_PERF_SEL_dtt_sm_miss_stall                    = 0xd6,
1004         DB_PERF_SEL_mi_rdreq_busy                        = 0xd7,
1005         DB_PERF_SEL_mi_rdreq_stall                       = 0xd8,
1006         DB_PERF_SEL_mi_wrreq_busy                        = 0xd9,
1007         DB_PERF_SEL_mi_wrreq_stall                       = 0xda,
1008         DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop     = 0xdb,
1009         DB_PERF_SEL_dkg_tile_rate_tile                   = 0xdc,
1010         DB_PERF_SEL_prezl_src_in_sends                   = 0xdd,
1011         DB_PERF_SEL_prezl_src_in_stall                   = 0xde,
1012         DB_PERF_SEL_prezl_src_in_squads                  = 0xdf,
1013         DB_PERF_SEL_prezl_src_in_squads_unrolled         = 0xe0,
1014         DB_PERF_SEL_prezl_src_in_tile_rate               = 0xe1,
1015         DB_PERF_SEL_prezl_src_in_tile_rate_unrolled      = 0xe2,
1016         DB_PERF_SEL_prezl_src_out_stall                  = 0xe3,
1017         DB_PERF_SEL_postzl_src_in_sends                  = 0xe4,
1018         DB_PERF_SEL_postzl_src_in_stall                  = 0xe5,
1019         DB_PERF_SEL_postzl_src_in_squads                 = 0xe6,
1020         DB_PERF_SEL_postzl_src_in_squads_unrolled        = 0xe7,
1021         DB_PERF_SEL_postzl_src_in_tile_rate              = 0xe8,
1022         DB_PERF_SEL_postzl_src_in_tile_rate_unrolled     = 0xe9,
1023         DB_PERF_SEL_postzl_src_out_stall                 = 0xea,
1024         DB_PERF_SEL_esr_ps_src_in_sends                  = 0xeb,
1025         DB_PERF_SEL_esr_ps_src_in_stall                  = 0xec,
1026         DB_PERF_SEL_esr_ps_src_in_squads                 = 0xed,
1027         DB_PERF_SEL_esr_ps_src_in_squads_unrolled        = 0xee,
1028         DB_PERF_SEL_esr_ps_src_in_tile_rate              = 0xef,
1029         DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled     = 0xf0,
1030         DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate= 0xf1,
1031         DB_PERF_SEL_esr_ps_src_out_stall                 = 0xf2,
1032         DB_PERF_SEL_depth_bounds_qtiles_culled           = 0xf3,
1033         DB_PERF_SEL_PreZ_Samples_failing_DB              = 0xf4,
1034         DB_PERF_SEL_PostZ_Samples_failing_DB             = 0xf5,
1035         DB_PERF_SEL_flush_compressed                     = 0xf6,
1036         DB_PERF_SEL_flush_plane_le4                      = 0xf7,
1037         DB_PERF_SEL_tiles_z_fully_summarized             = 0xf8,
1038         DB_PERF_SEL_tiles_stencil_fully_summarized       = 0xf9,
1039         DB_PERF_SEL_tiles_z_clear_on_expclear            = 0xfa,
1040         DB_PERF_SEL_tiles_s_clear_on_expclear            = 0xfb,
1041         DB_PERF_SEL_tiles_decomp_on_expclear             = 0xfc,
1042         DB_PERF_SEL_tiles_compressed_to_decompressed     = 0xfd,
1043         DB_PERF_SEL_Op_Pipe_Prez_Busy                    = 0xfe,
1044         DB_PERF_SEL_Op_Pipe_Postz_Busy                   = 0xff,
1045         DB_PERF_SEL_di_dt_stall                          = 0x100,
1046         DB_PERF_SEL_DB_SC_quad_double_quad               = 0x101,
1047         DB_PERF_SEL_SX_DB_quad_export_quads              = 0x102,
1048         DB_PERF_SEL_SX_DB_quad_double_format             = 0x103,
1049         DB_PERF_SEL_SX_DB_quad_fast_format               = 0x104,
1050         DB_PERF_SEL_SX_DB_quad_slow_format               = 0x105,
1051         DB_PERF_SEL_DB_CB_lquad_export_quads             = 0x106,
1052         DB_PERF_SEL_DB_CB_lquad_double_format            = 0x107,
1053         DB_PERF_SEL_DB_CB_lquad_fast_format              = 0x108,
1054         DB_PERF_SEL_DB_CB_lquad_slow_format              = 0x109,
1055 } PerfCounter_Vals;
1056 typedef enum RingCounterControl {
1057         COUNTER_RING_SPLIT                               = 0x0,
1058         COUNTER_RING_0                                   = 0x1,
1059         COUNTER_RING_1                                   = 0x2,
1060 } RingCounterControl;
1061 typedef enum PixelPipeCounterId {
1062         PIXEL_PIPE_OCCLUSION_COUNT_0                     = 0x0,
1063         PIXEL_PIPE_OCCLUSION_COUNT_1                     = 0x1,
1064         PIXEL_PIPE_OCCLUSION_COUNT_2                     = 0x2,
1065         PIXEL_PIPE_OCCLUSION_COUNT_3                     = 0x3,
1066         PIXEL_PIPE_SCREEN_MIN_EXTENTS_0                  = 0x4,
1067         PIXEL_PIPE_SCREEN_MAX_EXTENTS_0                  = 0x5,
1068         PIXEL_PIPE_SCREEN_MIN_EXTENTS_1                  = 0x6,
1069         PIXEL_PIPE_SCREEN_MAX_EXTENTS_1                  = 0x7,
1070 } PixelPipeCounterId;
1071 typedef enum PixelPipeStride {
1072         PIXEL_PIPE_STRIDE_32_BITS                        = 0x0,
1073         PIXEL_PIPE_STRIDE_64_BITS                        = 0x1,
1074         PIXEL_PIPE_STRIDE_128_BITS                       = 0x2,
1075         PIXEL_PIPE_STRIDE_256_BITS                       = 0x3,
1076 } PixelPipeStride;
1077 typedef enum GB_EDC_DED_MODE {
1078         GB_EDC_DED_MODE_LOG                              = 0x0,
1079         GB_EDC_DED_MODE_HALT                             = 0x1,
1080         GB_EDC_DED_MODE_INT_HALT                         = 0x2,
1081 } GB_EDC_DED_MODE;
1082 #define GB_TILING_CONFIG_TABLE_SIZE               0x20
1083 #define GB_TILING_CONFIG_MACROTABLE_SIZE          0x10
1084 typedef enum GRBM_PERF_SEL {
1085         GRBM_PERF_SEL_COUNT                              = 0x0,
1086         GRBM_PERF_SEL_USER_DEFINED                       = 0x1,
1087         GRBM_PERF_SEL_GUI_ACTIVE                         = 0x2,
1088         GRBM_PERF_SEL_CP_BUSY                            = 0x3,
1089         GRBM_PERF_SEL_CP_COHER_BUSY                      = 0x4,
1090         GRBM_PERF_SEL_CP_DMA_BUSY                        = 0x5,
1091         GRBM_PERF_SEL_CB_BUSY                            = 0x6,
1092         GRBM_PERF_SEL_DB_BUSY                            = 0x7,
1093         GRBM_PERF_SEL_PA_BUSY                            = 0x8,
1094         GRBM_PERF_SEL_SC_BUSY                            = 0x9,
1095         GRBM_PERF_SEL_RESERVED_6                         = 0xa,
1096         GRBM_PERF_SEL_SPI_BUSY                           = 0xb,
1097         GRBM_PERF_SEL_SX_BUSY                            = 0xc,
1098         GRBM_PERF_SEL_TA_BUSY                            = 0xd,
1099         GRBM_PERF_SEL_CB_CLEAN                           = 0xe,
1100         GRBM_PERF_SEL_DB_CLEAN                           = 0xf,
1101         GRBM_PERF_SEL_RESERVED_5                         = 0x10,
1102         GRBM_PERF_SEL_VGT_BUSY                           = 0x11,
1103         GRBM_PERF_SEL_RESERVED_4                         = 0x12,
1104         GRBM_PERF_SEL_RESERVED_3                         = 0x13,
1105         GRBM_PERF_SEL_RESERVED_2                         = 0x14,
1106         GRBM_PERF_SEL_RESERVED_1                         = 0x15,
1107         GRBM_PERF_SEL_RESERVED_0                         = 0x16,
1108         GRBM_PERF_SEL_IA_BUSY                            = 0x17,
1109         GRBM_PERF_SEL_IA_NO_DMA_BUSY                     = 0x18,
1110         GRBM_PERF_SEL_GDS_BUSY                           = 0x19,
1111         GRBM_PERF_SEL_BCI_BUSY                           = 0x1a,
1112         GRBM_PERF_SEL_RLC_BUSY                           = 0x1b,
1113         GRBM_PERF_SEL_TC_BUSY                            = 0x1c,
1114         GRBM_PERF_SEL_CPG_BUSY                           = 0x1d,
1115         GRBM_PERF_SEL_CPC_BUSY                           = 0x1e,
1116         GRBM_PERF_SEL_CPF_BUSY                           = 0x1f,
1117         GRBM_PERF_SEL_WD_BUSY                            = 0x20,
1118         GRBM_PERF_SEL_WD_NO_DMA_BUSY                     = 0x21,
1119 } GRBM_PERF_SEL;
1120 typedef enum GRBM_SE0_PERF_SEL {
1121         GRBM_SE0_PERF_SEL_COUNT                          = 0x0,
1122         GRBM_SE0_PERF_SEL_USER_DEFINED                   = 0x1,
1123         GRBM_SE0_PERF_SEL_CB_BUSY                        = 0x2,
1124         GRBM_SE0_PERF_SEL_DB_BUSY                        = 0x3,
1125         GRBM_SE0_PERF_SEL_SC_BUSY                        = 0x4,
1126         GRBM_SE0_PERF_SEL_RESERVED_1                     = 0x5,
1127         GRBM_SE0_PERF_SEL_SPI_BUSY                       = 0x6,
1128         GRBM_SE0_PERF_SEL_SX_BUSY                        = 0x7,
1129         GRBM_SE0_PERF_SEL_TA_BUSY                        = 0x8,
1130         GRBM_SE0_PERF_SEL_CB_CLEAN                       = 0x9,
1131         GRBM_SE0_PERF_SEL_DB_CLEAN                       = 0xa,
1132         GRBM_SE0_PERF_SEL_RESERVED_0                     = 0xb,
1133         GRBM_SE0_PERF_SEL_PA_BUSY                        = 0xc,
1134         GRBM_SE0_PERF_SEL_VGT_BUSY                       = 0xd,
1135         GRBM_SE0_PERF_SEL_BCI_BUSY                       = 0xe,
1136 } GRBM_SE0_PERF_SEL;
1137 typedef enum GRBM_SE1_PERF_SEL {
1138         GRBM_SE1_PERF_SEL_COUNT                          = 0x0,
1139         GRBM_SE1_PERF_SEL_USER_DEFINED                   = 0x1,
1140         GRBM_SE1_PERF_SEL_CB_BUSY                        = 0x2,
1141         GRBM_SE1_PERF_SEL_DB_BUSY                        = 0x3,
1142         GRBM_SE1_PERF_SEL_SC_BUSY                        = 0x4,
1143         GRBM_SE1_PERF_SEL_RESERVED_1                     = 0x5,
1144         GRBM_SE1_PERF_SEL_SPI_BUSY                       = 0x6,
1145         GRBM_SE1_PERF_SEL_SX_BUSY                        = 0x7,
1146         GRBM_SE1_PERF_SEL_TA_BUSY                        = 0x8,
1147         GRBM_SE1_PERF_SEL_CB_CLEAN                       = 0x9,
1148         GRBM_SE1_PERF_SEL_DB_CLEAN                       = 0xa,
1149         GRBM_SE1_PERF_SEL_RESERVED_0                     = 0xb,
1150         GRBM_SE1_PERF_SEL_PA_BUSY                        = 0xc,
1151         GRBM_SE1_PERF_SEL_VGT_BUSY                       = 0xd,
1152         GRBM_SE1_PERF_SEL_BCI_BUSY                       = 0xe,
1153 } GRBM_SE1_PERF_SEL;
1154 typedef enum GRBM_SE2_PERF_SEL {
1155         GRBM_SE2_PERF_SEL_COUNT                          = 0x0,
1156         GRBM_SE2_PERF_SEL_USER_DEFINED                   = 0x1,
1157         GRBM_SE2_PERF_SEL_CB_BUSY                        = 0x2,
1158         GRBM_SE2_PERF_SEL_DB_BUSY                        = 0x3,
1159         GRBM_SE2_PERF_SEL_SC_BUSY                        = 0x4,
1160         GRBM_SE2_PERF_SEL_RESERVED_1                     = 0x5,
1161         GRBM_SE2_PERF_SEL_SPI_BUSY                       = 0x6,
1162         GRBM_SE2_PERF_SEL_SX_BUSY                        = 0x7,
1163         GRBM_SE2_PERF_SEL_TA_BUSY                        = 0x8,
1164         GRBM_SE2_PERF_SEL_CB_CLEAN                       = 0x9,
1165         GRBM_SE2_PERF_SEL_DB_CLEAN                       = 0xa,
1166         GRBM_SE2_PERF_SEL_RESERVED_0                     = 0xb,
1167         GRBM_SE2_PERF_SEL_PA_BUSY                        = 0xc,
1168         GRBM_SE2_PERF_SEL_VGT_BUSY                       = 0xd,
1169         GRBM_SE2_PERF_SEL_BCI_BUSY                       = 0xe,
1170 } GRBM_SE2_PERF_SEL;
1171 typedef enum GRBM_SE3_PERF_SEL {
1172         GRBM_SE3_PERF_SEL_COUNT                          = 0x0,
1173         GRBM_SE3_PERF_SEL_USER_DEFINED                   = 0x1,
1174         GRBM_SE3_PERF_SEL_CB_BUSY                        = 0x2,
1175         GRBM_SE3_PERF_SEL_DB_BUSY                        = 0x3,
1176         GRBM_SE3_PERF_SEL_SC_BUSY                        = 0x4,
1177         GRBM_SE3_PERF_SEL_RESERVED_1                     = 0x5,
1178         GRBM_SE3_PERF_SEL_SPI_BUSY                       = 0x6,
1179         GRBM_SE3_PERF_SEL_SX_BUSY                        = 0x7,
1180         GRBM_SE3_PERF_SEL_TA_BUSY                        = 0x8,
1181         GRBM_SE3_PERF_SEL_CB_CLEAN                       = 0x9,
1182         GRBM_SE3_PERF_SEL_DB_CLEAN                       = 0xa,
1183         GRBM_SE3_PERF_SEL_RESERVED_0                     = 0xb,
1184         GRBM_SE3_PERF_SEL_PA_BUSY                        = 0xc,
1185         GRBM_SE3_PERF_SEL_VGT_BUSY                       = 0xd,
1186         GRBM_SE3_PERF_SEL_BCI_BUSY                       = 0xe,
1187 } GRBM_SE3_PERF_SEL;
1188 typedef enum SU_PERFCNT_SEL {
1189         PERF_PAPC_PASX_REQ                               = 0x0,
1190         PERF_PAPC_PASX_DISABLE_PIPE                      = 0x1,
1191         PERF_PAPC_PASX_FIRST_VECTOR                      = 0x2,
1192         PERF_PAPC_PASX_SECOND_VECTOR                     = 0x3,
1193         PERF_PAPC_PASX_FIRST_DEAD                        = 0x4,
1194         PERF_PAPC_PASX_SECOND_DEAD                       = 0x5,
1195         PERF_PAPC_PASX_VTX_KILL_DISCARD                  = 0x6,
1196         PERF_PAPC_PASX_VTX_NAN_DISCARD                   = 0x7,
1197         PERF_PAPC_PA_INPUT_PRIM                          = 0x8,
1198         PERF_PAPC_PA_INPUT_NULL_PRIM                     = 0x9,
1199         PERF_PAPC_PA_INPUT_EVENT_FLAG                    = 0xa,
1200         PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT               = 0xb,
1201         PERF_PAPC_PA_INPUT_END_OF_PACKET                 = 0xc,
1202         PERF_PAPC_PA_INPUT_EXTENDED_EVENT                = 0xd,
1203         PERF_PAPC_CLPR_CULL_PRIM                         = 0xe,
1204         PERF_PAPC_CLPR_VVUCP_CULL_PRIM                   = 0xf,
1205         PERF_PAPC_CLPR_VV_CULL_PRIM                      = 0x10,
1206         PERF_PAPC_CLPR_UCP_CULL_PRIM                     = 0x11,
1207         PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM                = 0x12,
1208         PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM                 = 0x13,
1209         PERF_PAPC_CLPR_CULL_TO_NULL_PRIM                 = 0x14,
1210         PERF_PAPC_CLPR_VVUCP_CLIP_PRIM                   = 0x15,
1211         PERF_PAPC_CLPR_VV_CLIP_PRIM                      = 0x16,
1212         PERF_PAPC_CLPR_UCP_CLIP_PRIM                     = 0x17,
1213         PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE              = 0x18,
1214         PERF_PAPC_CLPR_CLIP_PLANE_CNT_1                  = 0x19,
1215         PERF_PAPC_CLPR_CLIP_PLANE_CNT_2                  = 0x1a,
1216         PERF_PAPC_CLPR_CLIP_PLANE_CNT_3                  = 0x1b,
1217         PERF_PAPC_CLPR_CLIP_PLANE_CNT_4                  = 0x1c,
1218         PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8                = 0x1d,
1219         PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12               = 0x1e,
1220         PERF_PAPC_CLPR_CLIP_PLANE_NEAR                   = 0x1f,
1221         PERF_PAPC_CLPR_CLIP_PLANE_FAR                    = 0x20,
1222         PERF_PAPC_CLPR_CLIP_PLANE_LEFT                   = 0x21,
1223         PERF_PAPC_CLPR_CLIP_PLANE_RIGHT                  = 0x22,
1224         PERF_PAPC_CLPR_CLIP_PLANE_TOP                    = 0x23,
1225         PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM                 = 0x24,
1226         PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM                = 0x25,
1227         PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM             = 0x26,
1228         PERF_PAPC_CLSM_NULL_PRIM                         = 0x27,
1229         PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM              = 0x28,
1230         PERF_PAPC_CLSM_CULL_TO_NULL_PRIM                 = 0x29,
1231         PERF_PAPC_CLSM_OUT_PRIM_CNT_1                    = 0x2a,
1232         PERF_PAPC_CLSM_OUT_PRIM_CNT_2                    = 0x2b,
1233         PERF_PAPC_CLSM_OUT_PRIM_CNT_3                    = 0x2c,
1234         PERF_PAPC_CLSM_OUT_PRIM_CNT_4                    = 0x2d,
1235         PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8                  = 0x2e,
1236         PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13                 = 0x2f,
1237         PERF_PAPC_CLIPGA_VTE_KILL_PRIM                   = 0x30,
1238         PERF_PAPC_SU_INPUT_PRIM                          = 0x31,
1239         PERF_PAPC_SU_INPUT_CLIP_PRIM                     = 0x32,
1240         PERF_PAPC_SU_INPUT_NULL_PRIM                     = 0x33,
1241         PERF_PAPC_SU_INPUT_PRIM_DUAL                     = 0x34,
1242         PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL                = 0x35,
1243         PERF_PAPC_SU_ZERO_AREA_CULL_PRIM                 = 0x36,
1244         PERF_PAPC_SU_BACK_FACE_CULL_PRIM                 = 0x37,
1245         PERF_PAPC_SU_FRONT_FACE_CULL_PRIM                = 0x38,
1246         PERF_PAPC_SU_POLYMODE_FACE_CULL                  = 0x39,
1247         PERF_PAPC_SU_POLYMODE_BACK_CULL                  = 0x3a,
1248         PERF_PAPC_SU_POLYMODE_FRONT_CULL                 = 0x3b,
1249         PERF_PAPC_SU_POLYMODE_INVALID_FILL               = 0x3c,
1250         PERF_PAPC_SU_OUTPUT_PRIM                         = 0x3d,
1251         PERF_PAPC_SU_OUTPUT_CLIP_PRIM                    = 0x3e,
1252         PERF_PAPC_SU_OUTPUT_NULL_PRIM                    = 0x3f,
1253         PERF_PAPC_SU_OUTPUT_EVENT_FLAG                   = 0x40,
1254         PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT              = 0x41,
1255         PERF_PAPC_SU_OUTPUT_END_OF_PACKET                = 0x42,
1256         PERF_PAPC_SU_OUTPUT_POLYMODE_FACE                = 0x43,
1257         PERF_PAPC_SU_OUTPUT_POLYMODE_BACK                = 0x44,
1258         PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT               = 0x45,
1259         PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE              = 0x46,
1260         PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK              = 0x47,
1261         PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT             = 0x48,
1262         PERF_PAPC_SU_OUTPUT_PRIM_DUAL                    = 0x49,
1263         PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL               = 0x4a,
1264         PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL                = 0x4b,
1265         PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL           = 0x4c,
1266         PERF_PAPC_PASX_REQ_IDLE                          = 0x4d,
1267         PERF_PAPC_PASX_REQ_BUSY                          = 0x4e,
1268         PERF_PAPC_PASX_REQ_STALLED                       = 0x4f,
1269         PERF_PAPC_PASX_REC_IDLE                          = 0x50,
1270         PERF_PAPC_PASX_REC_BUSY                          = 0x51,
1271         PERF_PAPC_PASX_REC_STARVED_SX                    = 0x52,
1272         PERF_PAPC_PASX_REC_STALLED                       = 0x53,
1273         PERF_PAPC_PASX_REC_STALLED_POS_MEM               = 0x54,
1274         PERF_PAPC_PASX_REC_STALLED_CCGSM_IN              = 0x55,
1275         PERF_PAPC_CCGSM_IDLE                             = 0x56,
1276         PERF_PAPC_CCGSM_BUSY                             = 0x57,
1277         PERF_PAPC_CCGSM_STALLED                          = 0x58,
1278         PERF_PAPC_CLPRIM_IDLE                            = 0x59,
1279         PERF_PAPC_CLPRIM_BUSY                            = 0x5a,
1280         PERF_PAPC_CLPRIM_STALLED                         = 0x5b,
1281         PERF_PAPC_CLPRIM_STARVED_CCGSM                   = 0x5c,
1282         PERF_PAPC_CLIPSM_IDLE                            = 0x5d,
1283         PERF_PAPC_CLIPSM_BUSY                            = 0x5e,
1284         PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH             = 0x5f,
1285         PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ               = 0x60,
1286         PERF_PAPC_CLIPSM_WAIT_CLIPGA                     = 0x61,
1287         PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP             = 0x62,
1288         PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM                 = 0x63,
1289         PERF_PAPC_CLIPGA_IDLE                            = 0x64,
1290         PERF_PAPC_CLIPGA_BUSY                            = 0x65,
1291         PERF_PAPC_CLIPGA_STARVED_VTE_CLIP                = 0x66,
1292         PERF_PAPC_CLIPGA_STALLED                         = 0x67,
1293         PERF_PAPC_CLIP_IDLE                              = 0x68,
1294         PERF_PAPC_CLIP_BUSY                              = 0x69,
1295         PERF_PAPC_SU_IDLE                                = 0x6a,
1296         PERF_PAPC_SU_BUSY                                = 0x6b,
1297         PERF_PAPC_SU_STARVED_CLIP                        = 0x6c,
1298         PERF_PAPC_SU_STALLED_SC                          = 0x6d,
1299         PERF_PAPC_CL_DYN_SCLK_VLD                        = 0x6e,
1300         PERF_PAPC_SU_DYN_SCLK_VLD                        = 0x6f,
1301         PERF_PAPC_PA_REG_SCLK_VLD                        = 0x70,
1302         PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL          = 0x71,
1303         PERF_PAPC_PASX_SE0_REQ                           = 0x72,
1304         PERF_PAPC_PASX_SE1_REQ                           = 0x73,
1305         PERF_PAPC_PASX_SE0_FIRST_VECTOR                  = 0x74,
1306         PERF_PAPC_PASX_SE0_SECOND_VECTOR                 = 0x75,
1307         PERF_PAPC_PASX_SE1_FIRST_VECTOR                  = 0x76,
1308         PERF_PAPC_PASX_SE1_SECOND_VECTOR                 = 0x77,
1309         PERF_PAPC_SU_SE0_PRIM_FILTER_CULL                = 0x78,
1310         PERF_PAPC_SU_SE1_PRIM_FILTER_CULL                = 0x79,
1311         PERF_PAPC_SU_SE01_PRIM_FILTER_CULL               = 0x7a,
1312         PERF_PAPC_SU_SE0_OUTPUT_PRIM                     = 0x7b,
1313         PERF_PAPC_SU_SE1_OUTPUT_PRIM                     = 0x7c,
1314         PERF_PAPC_SU_SE01_OUTPUT_PRIM                    = 0x7d,
1315         PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM                = 0x7e,
1316         PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM                = 0x7f,
1317         PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM               = 0x80,
1318         PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT          = 0x81,
1319         PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT          = 0x82,
1320         PERF_PAPC_SU_SE0_STALLED_SC                      = 0x83,
1321         PERF_PAPC_SU_SE1_STALLED_SC                      = 0x84,
1322         PERF_PAPC_SU_SE01_STALLED_SC                     = 0x85,
1323         PERF_PAPC_CLSM_CLIPPING_PRIM                     = 0x86,
1324         PERF_PAPC_SU_CULLED_PRIM                         = 0x87,
1325         PERF_PAPC_SU_OUTPUT_EOPG                         = 0x88,
1326         PERF_PAPC_SU_SE2_PRIM_FILTER_CULL                = 0x89,
1327         PERF_PAPC_SU_SE3_PRIM_FILTER_CULL                = 0x8a,
1328         PERF_PAPC_SU_SE2_OUTPUT_PRIM                     = 0x8b,
1329         PERF_PAPC_SU_SE3_OUTPUT_PRIM                     = 0x8c,
1330         PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM                = 0x8d,
1331         PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM                = 0x8e,
1332         PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET            = 0x8f,
1333         PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET            = 0x90,
1334         PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET            = 0x91,
1335         PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET            = 0x92,
1336         PERF_PAPC_SU_SE0_OUTPUT_EOPG                     = 0x93,
1337         PERF_PAPC_SU_SE1_OUTPUT_EOPG                     = 0x94,
1338         PERF_PAPC_SU_SE2_OUTPUT_EOPG                     = 0x95,
1339         PERF_PAPC_SU_SE3_OUTPUT_EOPG                     = 0x96,
1340         PERF_PAPC_SU_SE2_STALLED_SC                      = 0x97,
1341         PERF_PAPC_SU_SE3_STALLED_SC                      = 0x98,
1342 } SU_PERFCNT_SEL;
1343 typedef enum SC_PERFCNT_SEL {
1344         SC_SRPS_WINDOW_VALID                             = 0x0,
1345         SC_PSSW_WINDOW_VALID                             = 0x1,
1346         SC_TPQZ_WINDOW_VALID                             = 0x2,
1347         SC_QZQP_WINDOW_VALID                             = 0x3,
1348         SC_TRPK_WINDOW_VALID                             = 0x4,
1349         SC_SRPS_WINDOW_VALID_BUSY                        = 0x5,
1350         SC_PSSW_WINDOW_VALID_BUSY                        = 0x6,
1351         SC_TPQZ_WINDOW_VALID_BUSY                        = 0x7,
1352         SC_QZQP_WINDOW_VALID_BUSY                        = 0x8,
1353         SC_TRPK_WINDOW_VALID_BUSY                        = 0x9,
1354         SC_STARVED_BY_PA                                 = 0xa,
1355         SC_STALLED_BY_PRIMFIFO                           = 0xb,
1356         SC_STALLED_BY_DB_TILE                            = 0xc,
1357         SC_STARVED_BY_DB_TILE                            = 0xd,
1358         SC_STALLED_BY_TILEORDERFIFO                      = 0xe,
1359         SC_STALLED_BY_TILEFIFO                           = 0xf,
1360         SC_STALLED_BY_DB_QUAD                            = 0x10,
1361         SC_STARVED_BY_DB_QUAD                            = 0x11,
1362         SC_STALLED_BY_QUADFIFO                           = 0x12,
1363         SC_STALLED_BY_BCI                                = 0x13,
1364         SC_STALLED_BY_SPI                                = 0x14,
1365         SC_SCISSOR_DISCARD                               = 0x15,
1366         SC_BB_DISCARD                                    = 0x16,
1367         SC_SUPERTILE_COUNT                               = 0x17,
1368         SC_SUPERTILE_PER_PRIM_H0                         = 0x18,
1369         SC_SUPERTILE_PER_PRIM_H1                         = 0x19,
1370         SC_SUPERTILE_PER_PRIM_H2                         = 0x1a,
1371         SC_SUPERTILE_PER_PRIM_H3                         = 0x1b,
1372         SC_SUPERTILE_PER_PRIM_H4                         = 0x1c,
1373         SC_SUPERTILE_PER_PRIM_H5                         = 0x1d,
1374         SC_SUPERTILE_PER_PRIM_H6                         = 0x1e,
1375         SC_SUPERTILE_PER_PRIM_H7                         = 0x1f,
1376         SC_SUPERTILE_PER_PRIM_H8                         = 0x20,
1377         SC_SUPERTILE_PER_PRIM_H9                         = 0x21,
1378         SC_SUPERTILE_PER_PRIM_H10                        = 0x22,
1379         SC_SUPERTILE_PER_PRIM_H11                        = 0x23,
1380         SC_SUPERTILE_PER_PRIM_H12                        = 0x24,
1381         SC_SUPERTILE_PER_PRIM_H13                        = 0x25,
1382         SC_SUPERTILE_PER_PRIM_H14                        = 0x26,
1383         SC_SUPERTILE_PER_PRIM_H15                        = 0x27,
1384         SC_SUPERTILE_PER_PRIM_H16                        = 0x28,
1385         SC_TILE_PER_PRIM_H0                              = 0x29,
1386         SC_TILE_PER_PRIM_H1                              = 0x2a,
1387         SC_TILE_PER_PRIM_H2                              = 0x2b,
1388         SC_TILE_PER_PRIM_H3                              = 0x2c,
1389         SC_TILE_PER_PRIM_H4                              = 0x2d,
1390         SC_TILE_PER_PRIM_H5                              = 0x2e,
1391         SC_TILE_PER_PRIM_H6                              = 0x2f,
1392         SC_TILE_PER_PRIM_H7                              = 0x30,
1393         SC_TILE_PER_PRIM_H8                              = 0x31,
1394         SC_TILE_PER_PRIM_H9                              = 0x32,
1395         SC_TILE_PER_PRIM_H10                             = 0x33,
1396         SC_TILE_PER_PRIM_H11                             = 0x34,
1397         SC_TILE_PER_PRIM_H12                             = 0x35,
1398         SC_TILE_PER_PRIM_H13                             = 0x36,
1399         SC_TILE_PER_PRIM_H14                             = 0x37,
1400         SC_TILE_PER_PRIM_H15                             = 0x38,
1401         SC_TILE_PER_PRIM_H16                             = 0x39,
1402         SC_TILE_PER_SUPERTILE_H0                         = 0x3a,
1403         SC_TILE_PER_SUPERTILE_H1                         = 0x3b,
1404         SC_TILE_PER_SUPERTILE_H2                         = 0x3c,
1405         SC_TILE_PER_SUPERTILE_H3                         = 0x3d,
1406         SC_TILE_PER_SUPERTILE_H4                         = 0x3e,
1407         SC_TILE_PER_SUPERTILE_H5                         = 0x3f,
1408         SC_TILE_PER_SUPERTILE_H6                         = 0x40,
1409         SC_TILE_PER_SUPERTILE_H7                         = 0x41,
1410         SC_TILE_PER_SUPERTILE_H8                         = 0x42,
1411         SC_TILE_PER_SUPERTILE_H9                         = 0x43,
1412         SC_TILE_PER_SUPERTILE_H10                        = 0x44,
1413         SC_TILE_PER_SUPERTILE_H11                        = 0x45,
1414         SC_TILE_PER_SUPERTILE_H12                        = 0x46,
1415         SC_TILE_PER_SUPERTILE_H13                        = 0x47,
1416         SC_TILE_PER_SUPERTILE_H14                        = 0x48,
1417         SC_TILE_PER_SUPERTILE_H15                        = 0x49,
1418         SC_TILE_PER_SUPERTILE_H16                        = 0x4a,
1419         SC_TILE_PICKED_H1                                = 0x4b,
1420         SC_TILE_PICKED_H2                                = 0x4c,
1421         SC_TILE_PICKED_H3                                = 0x4d,
1422         SC_TILE_PICKED_H4                                = 0x4e,
1423         SC_QZ0_MULTI_GPU_TILE_DISCARD                    = 0x4f,
1424         SC_QZ1_MULTI_GPU_TILE_DISCARD                    = 0x50,
1425         SC_QZ2_MULTI_GPU_TILE_DISCARD                    = 0x51,
1426         SC_QZ3_MULTI_GPU_TILE_DISCARD                    = 0x52,
1427         SC_QZ0_TILE_COUNT                                = 0x53,
1428         SC_QZ1_TILE_COUNT                                = 0x54,
1429         SC_QZ2_TILE_COUNT                                = 0x55,
1430         SC_QZ3_TILE_COUNT                                = 0x56,
1431         SC_QZ0_TILE_COVERED_COUNT                        = 0x57,
1432         SC_QZ1_TILE_COVERED_COUNT                        = 0x58,
1433         SC_QZ2_TILE_COVERED_COUNT                        = 0x59,
1434         SC_QZ3_TILE_COVERED_COUNT                        = 0x5a,
1435         SC_QZ0_TILE_NOT_COVERED_COUNT                    = 0x5b,
1436         SC_QZ1_TILE_NOT_COVERED_COUNT                    = 0x5c,
1437         SC_QZ2_TILE_NOT_COVERED_COUNT                    = 0x5d,
1438         SC_QZ3_TILE_NOT_COVERED_COUNT                    = 0x5e,
1439         SC_QZ0_QUAD_PER_TILE_H0                          = 0x5f,
1440         SC_QZ0_QUAD_PER_TILE_H1                          = 0x60,
1441         SC_QZ0_QUAD_PER_TILE_H2                          = 0x61,
1442         SC_QZ0_QUAD_PER_TILE_H3                          = 0x62,
1443         SC_QZ0_QUAD_PER_TILE_H4                          = 0x63,
1444         SC_QZ0_QUAD_PER_TILE_H5                          = 0x64,
1445         SC_QZ0_QUAD_PER_TILE_H6                          = 0x65,
1446         SC_QZ0_QUAD_PER_TILE_H7                          = 0x66,
1447         SC_QZ0_QUAD_PER_TILE_H8                          = 0x67,
1448         SC_QZ0_QUAD_PER_TILE_H9                          = 0x68,
1449         SC_QZ0_QUAD_PER_TILE_H10                         = 0x69,
1450         SC_QZ0_QUAD_PER_TILE_H11                         = 0x6a,
1451         SC_QZ0_QUAD_PER_TILE_H12                         = 0x6b,
1452         SC_QZ0_QUAD_PER_TILE_H13                         = 0x6c,
1453         SC_QZ0_QUAD_PER_TILE_H14                         = 0x6d,
1454         SC_QZ0_QUAD_PER_TILE_H15                         = 0x6e,
1455         SC_QZ0_QUAD_PER_TILE_H16                         = 0x6f,
1456         SC_QZ1_QUAD_PER_TILE_H0                          = 0x70,
1457         SC_QZ1_QUAD_PER_TILE_H1                          = 0x71,
1458         SC_QZ1_QUAD_PER_TILE_H2                          = 0x72,
1459         SC_QZ1_QUAD_PER_TILE_H3                          = 0x73,
1460         SC_QZ1_QUAD_PER_TILE_H4                          = 0x74,
1461         SC_QZ1_QUAD_PER_TILE_H5                          = 0x75,
1462         SC_QZ1_QUAD_PER_TILE_H6                          = 0x76,
1463         SC_QZ1_QUAD_PER_TILE_H7                          = 0x77,
1464         SC_QZ1_QUAD_PER_TILE_H8                          = 0x78,
1465         SC_QZ1_QUAD_PER_TILE_H9                          = 0x79,
1466         SC_QZ1_QUAD_PER_TILE_H10                         = 0x7a,
1467         SC_QZ1_QUAD_PER_TILE_H11                         = 0x7b,
1468         SC_QZ1_QUAD_PER_TILE_H12                         = 0x7c,
1469         SC_QZ1_QUAD_PER_TILE_H13                         = 0x7d,
1470         SC_QZ1_QUAD_PER_TILE_H14                         = 0x7e,
1471         SC_QZ1_QUAD_PER_TILE_H15                         = 0x7f,
1472         SC_QZ1_QUAD_PER_TILE_H16                         = 0x80,
1473         SC_QZ2_QUAD_PER_TILE_H0                          = 0x81,
1474         SC_QZ2_QUAD_PER_TILE_H1                          = 0x82,
1475         SC_QZ2_QUAD_PER_TILE_H2                          = 0x83,
1476         SC_QZ2_QUAD_PER_TILE_H3                          = 0x84,
1477         SC_QZ2_QUAD_PER_TILE_H4                          = 0x85,
1478         SC_QZ2_QUAD_PER_TILE_H5                          = 0x86,
1479         SC_QZ2_QUAD_PER_TILE_H6                          = 0x87,
1480         SC_QZ2_QUAD_PER_TILE_H7                          = 0x88,
1481         SC_QZ2_QUAD_PER_TILE_H8                          = 0x89,
1482         SC_QZ2_QUAD_PER_TILE_H9                          = 0x8a,
1483         SC_QZ2_QUAD_PER_TILE_H10                         = 0x8b,
1484         SC_QZ2_QUAD_PER_TILE_H11                         = 0x8c,
1485         SC_QZ2_QUAD_PER_TILE_H12                         = 0x8d,
1486         SC_QZ2_QUAD_PER_TILE_H13                         = 0x8e,
1487         SC_QZ2_QUAD_PER_TILE_H14                         = 0x8f,
1488         SC_QZ2_QUAD_PER_TILE_H15                         = 0x90,
1489         SC_QZ2_QUAD_PER_TILE_H16                         = 0x91,
1490         SC_QZ3_QUAD_PER_TILE_H0                          = 0x92,
1491         SC_QZ3_QUAD_PER_TILE_H1                          = 0x93,
1492         SC_QZ3_QUAD_PER_TILE_H2                          = 0x94,
1493         SC_QZ3_QUAD_PER_TILE_H3                          = 0x95,
1494         SC_QZ3_QUAD_PER_TILE_H4                          = 0x96,
1495         SC_QZ3_QUAD_PER_TILE_H5                          = 0x97,
1496         SC_QZ3_QUAD_PER_TILE_H6                          = 0x98,
1497         SC_QZ3_QUAD_PER_TILE_H7                          = 0x99,
1498         SC_QZ3_QUAD_PER_TILE_H8                          = 0x9a,
1499         SC_QZ3_QUAD_PER_TILE_H9                          = 0x9b,
1500         SC_QZ3_QUAD_PER_TILE_H10                         = 0x9c,
1501         SC_QZ3_QUAD_PER_TILE_H11                         = 0x9d,
1502         SC_QZ3_QUAD_PER_TILE_H12                         = 0x9e,
1503         SC_QZ3_QUAD_PER_TILE_H13                         = 0x9f,
1504         SC_QZ3_QUAD_PER_TILE_H14                         = 0xa0,
1505         SC_QZ3_QUAD_PER_TILE_H15                         = 0xa1,
1506         SC_QZ3_QUAD_PER_TILE_H16                         = 0xa2,
1507         SC_QZ0_QUAD_COUNT                                = 0xa3,
1508         SC_QZ1_QUAD_COUNT                                = 0xa4,
1509         SC_QZ2_QUAD_COUNT                                = 0xa5,
1510         SC_QZ3_QUAD_COUNT                                = 0xa6,
1511         SC_P0_HIZ_TILE_COUNT                             = 0xa7,
1512         SC_P1_HIZ_TILE_COUNT                             = 0xa8,
1513         SC_P2_HIZ_TILE_COUNT                             = 0xa9,
1514         SC_P3_HIZ_TILE_COUNT                             = 0xaa,
1515         SC_P0_HIZ_QUAD_PER_TILE_H0                       = 0xab,
1516         SC_P0_HIZ_QUAD_PER_TILE_H1                       = 0xac,
1517         SC_P0_HIZ_QUAD_PER_TILE_H2                       = 0xad,
1518         SC_P0_HIZ_QUAD_PER_TILE_H3                       = 0xae,
1519         SC_P0_HIZ_QUAD_PER_TILE_H4                       = 0xaf,
1520         SC_P0_HIZ_QUAD_PER_TILE_H5                       = 0xb0,
1521         SC_P0_HIZ_QUAD_PER_TILE_H6                       = 0xb1,
1522         SC_P0_HIZ_QUAD_PER_TILE_H7                       = 0xb2,
1523         SC_P0_HIZ_QUAD_PER_TILE_H8                       = 0xb3,
1524         SC_P0_HIZ_QUAD_PER_TILE_H9                       = 0xb4,
1525         SC_P0_HIZ_QUAD_PER_TILE_H10                      = 0xb5,
1526         SC_P0_HIZ_QUAD_PER_TILE_H11                      = 0xb6,
1527         SC_P0_HIZ_QUAD_PER_TILE_H12                      = 0xb7,
1528         SC_P0_HIZ_QUAD_PER_TILE_H13                      = 0xb8,
1529         SC_P0_HIZ_QUAD_PER_TILE_H14                      = 0xb9,
1530         SC_P0_HIZ_QUAD_PER_TILE_H15                      = 0xba,
1531         SC_P0_HIZ_QUAD_PER_TILE_H16                      = 0xbb,
1532         SC_P1_HIZ_QUAD_PER_TILE_H0                       = 0xbc,
1533         SC_P1_HIZ_QUAD_PER_TILE_H1                       = 0xbd,
1534         SC_P1_HIZ_QUAD_PER_TILE_H2                       = 0xbe,
1535         SC_P1_HIZ_QUAD_PER_TILE_H3                       = 0xbf,
1536         SC_P1_HIZ_QUAD_PER_TILE_H4                       = 0xc0,
1537         SC_P1_HIZ_QUAD_PER_TILE_H5                       = 0xc1,
1538         SC_P1_HIZ_QUAD_PER_TILE_H6                       = 0xc2,
1539         SC_P1_HIZ_QUAD_PER_TILE_H7                       = 0xc3,
1540         SC_P1_HIZ_QUAD_PER_TILE_H8                       = 0xc4,
1541         SC_P1_HIZ_QUAD_PER_TILE_H9                       = 0xc5,
1542         SC_P1_HIZ_QUAD_PER_TILE_H10                      = 0xc6,
1543         SC_P1_HIZ_QUAD_PER_TILE_H11                      = 0xc7,
1544         SC_P1_HIZ_QUAD_PER_TILE_H12                      = 0xc8,
1545         SC_P1_HIZ_QUAD_PER_TILE_H13                      = 0xc9,
1546         SC_P1_HIZ_QUAD_PER_TILE_H14                      = 0xca,
1547         SC_P1_HIZ_QUAD_PER_TILE_H15                      = 0xcb,
1548         SC_P1_HIZ_QUAD_PER_TILE_H16                      = 0xcc,
1549         SC_P2_HIZ_QUAD_PER_TILE_H0                       = 0xcd,
1550         SC_P2_HIZ_QUAD_PER_TILE_H1                       = 0xce,
1551         SC_P2_HIZ_QUAD_PER_TILE_H2                       = 0xcf,
1552         SC_P2_HIZ_QUAD_PER_TILE_H3                       = 0xd0,
1553         SC_P2_HIZ_QUAD_PER_TILE_H4                       = 0xd1,
1554         SC_P2_HIZ_QUAD_PER_TILE_H5                       = 0xd2,
1555         SC_P2_HIZ_QUAD_PER_TILE_H6                       = 0xd3,
1556         SC_P2_HIZ_QUAD_PER_TILE_H7                       = 0xd4,
1557         SC_P2_HIZ_QUAD_PER_TILE_H8                       = 0xd5,
1558         SC_P2_HIZ_QUAD_PER_TILE_H9                       = 0xd6,
1559         SC_P2_HIZ_QUAD_PER_TILE_H10                      = 0xd7,
1560         SC_P2_HIZ_QUAD_PER_TILE_H11                      = 0xd8,
1561         SC_P2_HIZ_QUAD_PER_TILE_H12                      = 0xd9,
1562         SC_P2_HIZ_QUAD_PER_TILE_H13                      = 0xda,
1563         SC_P2_HIZ_QUAD_PER_TILE_H14                      = 0xdb,
1564         SC_P2_HIZ_QUAD_PER_TILE_H15                      = 0xdc,
1565         SC_P2_HIZ_QUAD_PER_TILE_H16                      = 0xdd,
1566         SC_P3_HIZ_QUAD_PER_TILE_H0                       = 0xde,
1567         SC_P3_HIZ_QUAD_PER_TILE_H1                       = 0xdf,
1568         SC_P3_HIZ_QUAD_PER_TILE_H2                       = 0xe0,
1569         SC_P3_HIZ_QUAD_PER_TILE_H3                       = 0xe1,
1570         SC_P3_HIZ_QUAD_PER_TILE_H4                       = 0xe2,
1571         SC_P3_HIZ_QUAD_PER_TILE_H5                       = 0xe3,
1572         SC_P3_HIZ_QUAD_PER_TILE_H6                       = 0xe4,
1573         SC_P3_HIZ_QUAD_PER_TILE_H7                       = 0xe5,
1574         SC_P3_HIZ_QUAD_PER_TILE_H8                       = 0xe6,
1575         SC_P3_HIZ_QUAD_PER_TILE_H9                       = 0xe7,
1576         SC_P3_HIZ_QUAD_PER_TILE_H10                      = 0xe8,
1577         SC_P3_HIZ_QUAD_PER_TILE_H11                      = 0xe9,
1578         SC_P3_HIZ_QUAD_PER_TILE_H12                      = 0xea,
1579         SC_P3_HIZ_QUAD_PER_TILE_H13                      = 0xeb,
1580         SC_P3_HIZ_QUAD_PER_TILE_H14                      = 0xec,
1581         SC_P3_HIZ_QUAD_PER_TILE_H15                      = 0xed,
1582         SC_P3_HIZ_QUAD_PER_TILE_H16                      = 0xee,
1583         SC_P0_HIZ_QUAD_COUNT                             = 0xef,
1584         SC_P1_HIZ_QUAD_COUNT                             = 0xf0,
1585         SC_P2_HIZ_QUAD_COUNT                             = 0xf1,
1586         SC_P3_HIZ_QUAD_COUNT                             = 0xf2,
1587         SC_P0_DETAIL_QUAD_COUNT                          = 0xf3,
1588         SC_P1_DETAIL_QUAD_COUNT                          = 0xf4,
1589         SC_P2_DETAIL_QUAD_COUNT                          = 0xf5,
1590         SC_P3_DETAIL_QUAD_COUNT                          = 0xf6,
1591         SC_P0_DETAIL_QUAD_WITH_1_PIX                     = 0xf7,
1592         SC_P0_DETAIL_QUAD_WITH_2_PIX                     = 0xf8,
1593         SC_P0_DETAIL_QUAD_WITH_3_PIX                     = 0xf9,
1594         SC_P0_DETAIL_QUAD_WITH_4_PIX                     = 0xfa,
1595         SC_P1_DETAIL_QUAD_WITH_1_PIX                     = 0xfb,
1596         SC_P1_DETAIL_QUAD_WITH_2_PIX                     = 0xfc,
1597         SC_P1_DETAIL_QUAD_WITH_3_PIX                     = 0xfd,
1598         SC_P1_DETAIL_QUAD_WITH_4_PIX                     = 0xfe,
1599         SC_P2_DETAIL_QUAD_WITH_1_PIX                     = 0xff,
1600         SC_P2_DETAIL_QUAD_WITH_2_PIX                     = 0x100,
1601         SC_P2_DETAIL_QUAD_WITH_3_PIX                     = 0x101,
1602         SC_P2_DETAIL_QUAD_WITH_4_PIX                     = 0x102,
1603         SC_P3_DETAIL_QUAD_WITH_1_PIX                     = 0x103,
1604         SC_P3_DETAIL_QUAD_WITH_2_PIX                     = 0x104,
1605         SC_P3_DETAIL_QUAD_WITH_3_PIX                     = 0x105,
1606         SC_P3_DETAIL_QUAD_WITH_4_PIX                     = 0x106,
1607         SC_EARLYZ_QUAD_COUNT                             = 0x107,
1608         SC_EARLYZ_QUAD_WITH_1_PIX                        = 0x108,
1609         SC_EARLYZ_QUAD_WITH_2_PIX                        = 0x109,
1610         SC_EARLYZ_QUAD_WITH_3_PIX                        = 0x10a,
1611         SC_EARLYZ_QUAD_WITH_4_PIX                        = 0x10b,
1612         SC_PKR_QUAD_PER_ROW_H1                           = 0x10c,
1613         SC_PKR_QUAD_PER_ROW_H2                           = 0x10d,
1614         SC_PKR_4X2_QUAD_SPLIT                            = 0x10e,
1615         SC_PKR_4X2_FILL_QUAD                             = 0x10f,
1616         SC_PKR_END_OF_VECTOR                             = 0x110,
1617         SC_PKR_CONTROL_XFER                              = 0x111,
1618         SC_PKR_DBHANG_FORCE_EOV                          = 0x112,
1619         SC_REG_SCLK_BUSY                                 = 0x113,
1620         SC_GRP0_DYN_SCLK_BUSY                            = 0x114,
1621         SC_GRP1_DYN_SCLK_BUSY                            = 0x115,
1622         SC_GRP2_DYN_SCLK_BUSY                            = 0x116,
1623         SC_GRP3_DYN_SCLK_BUSY                            = 0x117,
1624         SC_GRP4_DYN_SCLK_BUSY                            = 0x118,
1625         SC_PA0_SC_DATA_FIFO_RD                           = 0x119,
1626         SC_PA0_SC_DATA_FIFO_WE                           = 0x11a,
1627         SC_PA1_SC_DATA_FIFO_RD                           = 0x11b,
1628         SC_PA1_SC_DATA_FIFO_WE                           = 0x11c,
1629         SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES           = 0x11d,
1630         SC_PS_ARB_XFC_ONLY_PRIM_CYCLES                   = 0x11e,
1631         SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM              = 0x11f,
1632         SC_PS_ARB_STALLED_FROM_BELOW                     = 0x120,
1633         SC_PS_ARB_STARVED_FROM_ABOVE                     = 0x121,
1634         SC_PS_ARB_SC_BUSY                                = 0x122,
1635         SC_PS_ARB_PA_SC_BUSY                             = 0x123,
1636         SC_PA2_SC_DATA_FIFO_RD                           = 0x124,
1637         SC_PA2_SC_DATA_FIFO_WE                           = 0x125,
1638         SC_PA3_SC_DATA_FIFO_RD                           = 0x126,
1639         SC_PA3_SC_DATA_FIFO_WE                           = 0x127,
1640         SC_PA_SC_DEALLOC_0_0_WE                          = 0x128,
1641         SC_PA_SC_DEALLOC_0_1_WE                          = 0x129,
1642         SC_PA_SC_DEALLOC_1_0_WE                          = 0x12a,
1643         SC_PA_SC_DEALLOC_1_1_WE                          = 0x12b,
1644         SC_PA_SC_DEALLOC_2_0_WE                          = 0x12c,
1645         SC_PA_SC_DEALLOC_2_1_WE                          = 0x12d,
1646         SC_PA_SC_DEALLOC_3_0_WE                          = 0x12e,
1647         SC_PA_SC_DEALLOC_3_1_WE                          = 0x12f,
1648         SC_PA0_SC_EOP_WE                                 = 0x130,
1649         SC_PA0_SC_EOPG_WE                                = 0x131,
1650         SC_PA0_SC_EVENT_WE                               = 0x132,
1651         SC_PA1_SC_EOP_WE                                 = 0x133,
1652         SC_PA1_SC_EOPG_WE                                = 0x134,
1653         SC_PA1_SC_EVENT_WE                               = 0x135,
1654         SC_PA2_SC_EOP_WE                                 = 0x136,
1655         SC_PA2_SC_EOPG_WE                                = 0x137,
1656         SC_PA2_SC_EVENT_WE                               = 0x138,
1657         SC_PA3_SC_EOP_WE                                 = 0x139,
1658         SC_PA3_SC_EOPG_WE                                = 0x13a,
1659         SC_PA3_SC_EVENT_WE                               = 0x13b,
1660         SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO   = 0x13c,
1661         SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH                  = 0x13d,
1662         SC_PS_ARB_NULL_PRIM_BUBBLE_POP                   = 0x13e,
1663         SC_PS_ARB_EOP_POP_SYNC_POP                       = 0x13f,
1664         SC_PS_ARB_EVENT_SYNC_POP                         = 0x140,
1665         SC_SC_PS_ENG_MULTICYCLE_BUBBLE                   = 0x141,
1666         SC_PA0_SC_FPOV_WE                                = 0x142,
1667         SC_PA1_SC_FPOV_WE                                = 0x143,
1668         SC_PA2_SC_FPOV_WE                                = 0x144,
1669         SC_PA3_SC_FPOV_WE                                = 0x145,
1670         SC_PA0_SC_LPOV_WE                                = 0x146,
1671         SC_PA1_SC_LPOV_WE                                = 0x147,
1672         SC_PA2_SC_LPOV_WE                                = 0x148,
1673         SC_PA3_SC_LPOV_WE                                = 0x149,
1674         SC_SC_SPI_DEALLOC_0_0                            = 0x14a,
1675         SC_SC_SPI_DEALLOC_0_1                            = 0x14b,
1676         SC_SC_SPI_DEALLOC_0_2                            = 0x14c,
1677         SC_SC_SPI_DEALLOC_1_0                            = 0x14d,
1678         SC_SC_SPI_DEALLOC_1_1                            = 0x14e,
1679         SC_SC_SPI_DEALLOC_1_2                            = 0x14f,
1680         SC_SC_SPI_DEALLOC_2_0                            = 0x150,
1681         SC_SC_SPI_DEALLOC_2_1                            = 0x151,
1682         SC_SC_SPI_DEALLOC_2_2                            = 0x152,
1683         SC_SC_SPI_DEALLOC_3_0                            = 0x153,
1684         SC_SC_SPI_DEALLOC_3_1                            = 0x154,
1685         SC_SC_SPI_DEALLOC_3_2                            = 0x155,
1686         SC_SC_SPI_FPOV_0                                 = 0x156,
1687         SC_SC_SPI_FPOV_1                                 = 0x157,
1688         SC_SC_SPI_FPOV_2                                 = 0x158,
1689         SC_SC_SPI_FPOV_3                                 = 0x159,
1690         SC_SC_SPI_EVENT                                  = 0x15a,
1691         SC_PS_TS_EVENT_FIFO_PUSH                         = 0x15b,
1692         SC_PS_TS_EVENT_FIFO_POP                          = 0x15c,
1693         SC_PS_CTX_DONE_FIFO_PUSH                         = 0x15d,
1694         SC_PS_CTX_DONE_FIFO_POP                          = 0x15e,
1695         SC_MULTICYCLE_BUBBLE_FREEZE                      = 0x15f,
1696         SC_EOP_SYNC_WINDOW                               = 0x160,
1697         SC_PA0_SC_NULL_WE                                = 0x161,
1698         SC_PA0_SC_NULL_DEALLOC_WE                        = 0x162,
1699         SC_PA0_SC_DATA_FIFO_EOPG_RD                      = 0x163,
1700         SC_PA0_SC_DATA_FIFO_EOP_RD                       = 0x164,
1701         SC_PA0_SC_DEALLOC_0_RD                           = 0x165,
1702         SC_PA0_SC_DEALLOC_1_RD                           = 0x166,
1703         SC_PA1_SC_DATA_FIFO_EOPG_RD                      = 0x167,
1704         SC_PA1_SC_DATA_FIFO_EOP_RD                       = 0x168,
1705         SC_PA1_SC_DEALLOC_0_RD                           = 0x169,
1706         SC_PA1_SC_DEALLOC_1_RD                           = 0x16a,
1707         SC_PA1_SC_NULL_WE                                = 0x16b,
1708         SC_PA1_SC_NULL_DEALLOC_WE                        = 0x16c,
1709         SC_PA2_SC_DATA_FIFO_EOPG_RD                      = 0x16d,
1710         SC_PA2_SC_DATA_FIFO_EOP_RD                       = 0x16e,
1711         SC_PA2_SC_DEALLOC_0_RD                           = 0x16f,
1712         SC_PA2_SC_DEALLOC_1_RD                           = 0x170,
1713         SC_PA2_SC_NULL_WE                                = 0x171,
1714         SC_PA2_SC_NULL_DEALLOC_WE                        = 0x172,
1715         SC_PA3_SC_DATA_FIFO_EOPG_RD                      = 0x173,
1716         SC_PA3_SC_DATA_FIFO_EOP_RD                       = 0x174,
1717         SC_PA3_SC_DEALLOC_0_RD                           = 0x175,
1718         SC_PA3_SC_DEALLOC_1_RD                           = 0x176,
1719         SC_PA3_SC_NULL_WE                                = 0x177,
1720         SC_PA3_SC_NULL_DEALLOC_WE                        = 0x178,
1721         SC_PS_PA0_SC_FIFO_EMPTY                          = 0x179,
1722         SC_PS_PA0_SC_FIFO_FULL                           = 0x17a,
1723         SC_PA0_PS_DATA_SEND                              = 0x17b,
1724         SC_PS_PA1_SC_FIFO_EMPTY                          = 0x17c,
1725         SC_PS_PA1_SC_FIFO_FULL                           = 0x17d,
1726         SC_PA1_PS_DATA_SEND                              = 0x17e,
1727         SC_PS_PA2_SC_FIFO_EMPTY                          = 0x17f,
1728         SC_PS_PA2_SC_FIFO_FULL                           = 0x180,
1729         SC_PA2_PS_DATA_SEND                              = 0x181,
1730         SC_PS_PA3_SC_FIFO_EMPTY                          = 0x182,
1731         SC_PS_PA3_SC_FIFO_FULL                           = 0x183,
1732         SC_PA3_PS_DATA_SEND                              = 0x184,
1733         SC_BUSY_PROCESSING_MULTICYCLE_PRIM               = 0x185,
1734         SC_BUSY_CNT_NOT_ZERO                             = 0x186,
1735         SC_BM_BUSY                                       = 0x187,
1736         SC_BACKEND_BUSY                                  = 0x188,
1737         SC_SCF_SCB_INTERFACE_BUSY                        = 0x189,
1738         SC_SCB_BUSY                                      = 0x18a,
1739         SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY    = 0x18b,
1740         SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL         = 0x18c,
1741 } SC_PERFCNT_SEL;
1742 typedef enum SePairXsel {
1743         RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE           = 0x0,
1744         RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE          = 0x1,
1745         RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE          = 0x2,
1746         RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE          = 0x3,
1747 } SePairXsel;
1748 typedef enum SePairYsel {
1749         RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE           = 0x0,
1750         RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE          = 0x1,
1751         RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE          = 0x2,
1752         RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE          = 0x3,
1753 } SePairYsel;
1754 typedef enum SePairMap {
1755         RASTER_CONFIG_SE_PAIR_MAP_0                      = 0x0,
1756         RASTER_CONFIG_SE_PAIR_MAP_1                      = 0x1,
1757         RASTER_CONFIG_SE_PAIR_MAP_2                      = 0x2,
1758         RASTER_CONFIG_SE_PAIR_MAP_3                      = 0x3,
1759 } SePairMap;
1760 typedef enum SeXsel {
1761         RASTER_CONFIG_SE_XSEL_8_WIDE_TILE                = 0x0,
1762         RASTER_CONFIG_SE_XSEL_16_WIDE_TILE               = 0x1,
1763         RASTER_CONFIG_SE_XSEL_32_WIDE_TILE               = 0x2,
1764         RASTER_CONFIG_SE_XSEL_64_WIDE_TILE               = 0x3,
1765 } SeXsel;
1766 typedef enum SeYsel {
1767         RASTER_CONFIG_SE_YSEL_8_WIDE_TILE                = 0x0,
1768         RASTER_CONFIG_SE_YSEL_16_WIDE_TILE               = 0x1,
1769         RASTER_CONFIG_SE_YSEL_32_WIDE_TILE               = 0x2,
1770         RASTER_CONFIG_SE_YSEL_64_WIDE_TILE               = 0x3,
1771 } SeYsel;
1772 typedef enum SeMap {
1773         RASTER_CONFIG_SE_MAP_0                           = 0x0,
1774         RASTER_CONFIG_SE_MAP_1                           = 0x1,
1775         RASTER_CONFIG_SE_MAP_2                           = 0x2,
1776         RASTER_CONFIG_SE_MAP_3                           = 0x3,
1777 } SeMap;
1778 typedef enum ScXsel {
1779         RASTER_CONFIG_SC_XSEL_8_WIDE_TILE                = 0x0,
1780         RASTER_CONFIG_SC_XSEL_16_WIDE_TILE               = 0x1,
1781         RASTER_CONFIG_SC_XSEL_32_WIDE_TILE               = 0x2,
1782         RASTER_CONFIG_SC_XSEL_64_WIDE_TILE               = 0x3,
1783 } ScXsel;
1784 typedef enum ScYsel {
1785         RASTER_CONFIG_SC_YSEL_8_WIDE_TILE                = 0x0,
1786         RASTER_CONFIG_SC_YSEL_16_WIDE_TILE               = 0x1,
1787         RASTER_CONFIG_SC_YSEL_32_WIDE_TILE               = 0x2,
1788         RASTER_CONFIG_SC_YSEL_64_WIDE_TILE               = 0x3,
1789 } ScYsel;
1790 typedef enum ScMap {
1791         RASTER_CONFIG_SC_MAP_0                           = 0x0,
1792         RASTER_CONFIG_SC_MAP_1                           = 0x1,
1793         RASTER_CONFIG_SC_MAP_2                           = 0x2,
1794         RASTER_CONFIG_SC_MAP_3                           = 0x3,
1795 } ScMap;
1796 typedef enum PkrXsel2 {
1797         RASTER_CONFIG_PKR_XSEL2_0                        = 0x0,
1798         RASTER_CONFIG_PKR_XSEL2_1                        = 0x1,
1799         RASTER_CONFIG_PKR_XSEL2_2                        = 0x2,
1800         RASTER_CONFIG_PKR_XSEL2_3                        = 0x3,
1801 } PkrXsel2;
1802 typedef enum PkrXsel {
1803         RASTER_CONFIG_PKR_XSEL_0                         = 0x0,
1804         RASTER_CONFIG_PKR_XSEL_1                         = 0x1,
1805         RASTER_CONFIG_PKR_XSEL_2                         = 0x2,
1806         RASTER_CONFIG_PKR_XSEL_3                         = 0x3,
1807 } PkrXsel;
1808 typedef enum PkrYsel {
1809         RASTER_CONFIG_PKR_YSEL_0                         = 0x0,
1810         RASTER_CONFIG_PKR_YSEL_1                         = 0x1,
1811         RASTER_CONFIG_PKR_YSEL_2                         = 0x2,
1812         RASTER_CONFIG_PKR_YSEL_3                         = 0x3,
1813 } PkrYsel;
1814 typedef enum PkrMap {
1815         RASTER_CONFIG_PKR_MAP_0                          = 0x0,
1816         RASTER_CONFIG_PKR_MAP_1                          = 0x1,
1817         RASTER_CONFIG_PKR_MAP_2                          = 0x2,
1818         RASTER_CONFIG_PKR_MAP_3                          = 0x3,
1819 } PkrMap;
1820 typedef enum RbXsel {
1821         RASTER_CONFIG_RB_XSEL_0                          = 0x0,
1822         RASTER_CONFIG_RB_XSEL_1                          = 0x1,
1823 } RbXsel;
1824 typedef enum RbYsel {
1825         RASTER_CONFIG_RB_YSEL_0                          = 0x0,
1826         RASTER_CONFIG_RB_YSEL_1                          = 0x1,
1827 } RbYsel;
1828 typedef enum RbXsel2 {
1829         RASTER_CONFIG_RB_XSEL2_0                         = 0x0,
1830         RASTER_CONFIG_RB_XSEL2_1                         = 0x1,
1831         RASTER_CONFIG_RB_XSEL2_2                         = 0x2,
1832         RASTER_CONFIG_RB_XSEL2_3                         = 0x3,
1833 } RbXsel2;
1834 typedef enum RbMap {
1835         RASTER_CONFIG_RB_MAP_0                           = 0x0,
1836         RASTER_CONFIG_RB_MAP_1                           = 0x1,
1837         RASTER_CONFIG_RB_MAP_2                           = 0x2,
1838         RASTER_CONFIG_RB_MAP_3                           = 0x3,
1839 } RbMap;
1840 typedef enum CSDATA_TYPE {
1841         CSDATA_TYPE_TG                                   = 0x0,
1842         CSDATA_TYPE_STATE                                = 0x1,
1843         CSDATA_TYPE_EVENT                                = 0x2,
1844         CSDATA_TYPE_PRIVATE                              = 0x3,
1845 } CSDATA_TYPE;
1846 #define CSDATA_TYPE_WIDTH                         0x2
1847 #define CSDATA_ADDR_WIDTH                         0x7
1848 #define CSDATA_DATA_WIDTH                         0x20
1849 typedef enum SPI_SAMPLE_CNTL {
1850         CENTROIDS_ONLY                                   = 0x0,
1851         CENTERS_ONLY                                     = 0x1,
1852         CENTROIDS_AND_CENTERS                            = 0x2,
1853         UNDEF                                            = 0x3,
1854 } SPI_SAMPLE_CNTL;
1855 typedef enum SPI_FOG_MODE {
1856         SPI_FOG_NONE                                     = 0x0,
1857         SPI_FOG_EXP                                      = 0x1,
1858         SPI_FOG_EXP2                                     = 0x2,
1859         SPI_FOG_LINEAR                                   = 0x3,
1860 } SPI_FOG_MODE;
1861 typedef enum SPI_PNT_SPRITE_OVERRIDE {
1862         SPI_PNT_SPRITE_SEL_0                             = 0x0,
1863         SPI_PNT_SPRITE_SEL_1                             = 0x1,
1864         SPI_PNT_SPRITE_SEL_S                             = 0x2,
1865         SPI_PNT_SPRITE_SEL_T                             = 0x3,
1866         SPI_PNT_SPRITE_SEL_NONE                          = 0x4,
1867 } SPI_PNT_SPRITE_OVERRIDE;
1868 typedef enum SPI_PERFCNT_SEL {
1869         SPI_PERF_VS_WINDOW_VALID                         = 0x0,
1870         SPI_PERF_VS_BUSY                                 = 0x1,
1871         SPI_PERF_VS_FIRST_WAVE                           = 0x2,
1872         SPI_PERF_VS_LAST_WAVE                            = 0x3,
1873         SPI_PERF_VS_LSHS_DEALLOC                         = 0x4,
1874         SPI_PERF_VS_PC_STALL                             = 0x5,
1875         SPI_PERF_VS_POS0_STALL                           = 0x6,
1876         SPI_PERF_VS_POS1_STALL                           = 0x7,
1877         SPI_PERF_VS_CRAWLER_STALL                        = 0x8,
1878         SPI_PERF_VS_EVENT_WAVE                           = 0x9,
1879         SPI_PERF_VS_WAVE                                 = 0xa,
1880         SPI_PERF_VS_PERS_UPD_FULL0                       = 0xb,
1881         SPI_PERF_VS_PERS_UPD_FULL1                       = 0xc,
1882         SPI_PERF_VS_LATE_ALLOC_FULL                      = 0xd,
1883         SPI_PERF_VS_FIRST_SUBGRP                         = 0xe,
1884         SPI_PERF_VS_LAST_SUBGRP                          = 0xf,
1885         SPI_PERF_GS_WINDOW_VALID                         = 0x10,
1886         SPI_PERF_GS_BUSY                                 = 0x11,
1887         SPI_PERF_GS_CRAWLER_STALL                        = 0x12,
1888         SPI_PERF_GS_EVENT_WAVE                           = 0x13,
1889         SPI_PERF_GS_WAVE                                 = 0x14,
1890         SPI_PERF_GS_PERS_UPD_FULL0                       = 0x15,
1891         SPI_PERF_GS_PERS_UPD_FULL1                       = 0x16,
1892         SPI_PERF_GS_FIRST_SUBGRP                         = 0x17,
1893         SPI_PERF_GS_LAST_SUBGRP                          = 0x18,
1894         SPI_PERF_ES_WINDOW_VALID                         = 0x19,
1895         SPI_PERF_ES_BUSY                                 = 0x1a,
1896         SPI_PERF_ES_CRAWLER_STALL                        = 0x1b,
1897         SPI_PERF_ES_FIRST_WAVE                           = 0x1c,
1898         SPI_PERF_ES_LAST_WAVE                            = 0x1d,
1899         SPI_PERF_ES_LSHS_DEALLOC                         = 0x1e,
1900         SPI_PERF_ES_EVENT_WAVE                           = 0x1f,
1901         SPI_PERF_ES_WAVE                                 = 0x20,
1902         SPI_PERF_ES_PERS_UPD_FULL0                       = 0x21,
1903         SPI_PERF_ES_PERS_UPD_FULL1                       = 0x22,
1904         SPI_PERF_ES_FIRST_SUBGRP                         = 0x23,
1905         SPI_PERF_ES_LAST_SUBGRP                          = 0x24,
1906         SPI_PERF_HS_WINDOW_VALID                         = 0x25,
1907         SPI_PERF_HS_BUSY                                 = 0x26,
1908         SPI_PERF_HS_CRAWLER_STALL                        = 0x27,
1909         SPI_PERF_HS_FIRST_WAVE                           = 0x28,
1910         SPI_PERF_HS_LAST_WAVE                            = 0x29,
1911         SPI_PERF_HS_LSHS_DEALLOC                         = 0x2a,
1912         SPI_PERF_HS_EVENT_WAVE                           = 0x2b,
1913         SPI_PERF_HS_WAVE                                 = 0x2c,
1914         SPI_PERF_HS_PERS_UPD_FULL0                       = 0x2d,
1915         SPI_PERF_HS_PERS_UPD_FULL1                       = 0x2e,
1916         SPI_PERF_LS_WINDOW_VALID                         = 0x2f,
1917         SPI_PERF_LS_BUSY                                 = 0x30,
1918         SPI_PERF_LS_CRAWLER_STALL                        = 0x31,
1919         SPI_PERF_LS_FIRST_WAVE                           = 0x32,
1920         SPI_PERF_LS_LAST_WAVE                            = 0x33,
1921         SPI_PERF_OFFCHIP_LDS_STALL_LS                    = 0x34,
1922         SPI_PERF_LS_EVENT_WAVE                           = 0x35,
1923         SPI_PERF_LS_WAVE                                 = 0x36,
1924         SPI_PERF_LS_PERS_UPD_FULL0                       = 0x37,
1925         SPI_PERF_LS_PERS_UPD_FULL1                       = 0x38,
1926         SPI_PERF_CSG_WINDOW_VALID                        = 0x39,
1927         SPI_PERF_CSG_BUSY                                = 0x3a,
1928         SPI_PERF_CSG_NUM_THREADGROUPS                    = 0x3b,
1929         SPI_PERF_CSG_CRAWLER_STALL                       = 0x3c,
1930         SPI_PERF_CSG_EVENT_WAVE                          = 0x3d,
1931         SPI_PERF_CSG_WAVE                                = 0x3e,
1932         SPI_PERF_CSN_WINDOW_VALID                        = 0x3f,
1933         SPI_PERF_CSN_BUSY                                = 0x40,
1934         SPI_PERF_CSN_NUM_THREADGROUPS                    = 0x41,
1935         SPI_PERF_CSN_CRAWLER_STALL                       = 0x42,
1936         SPI_PERF_CSN_EVENT_WAVE                          = 0x43,
1937         SPI_PERF_CSN_WAVE                                = 0x44,
1938         SPI_PERF_PS_CTL_WINDOW_VALID                     = 0x45,
1939         SPI_PERF_PS_CTL_BUSY                             = 0x46,
1940         SPI_PERF_PS_CTL_ACTIVE                           = 0x47,
1941         SPI_PERF_PS_CTL_DEALLOC_BIN0                     = 0x48,
1942         SPI_PERF_PS_CTL_FPOS_BIN1_STALL                  = 0x49,
1943         SPI_PERF_PS_CTL_EVENT_WAVE                       = 0x4a,
1944         SPI_PERF_PS_CTL_WAVE                             = 0x4b,
1945         SPI_PERF_PS_CTL_OPT_WAVE                         = 0x4c,
1946         SPI_PERF_PS_CTL_PASS_BIN0                        = 0x4d,
1947         SPI_PERF_PS_CTL_PASS_BIN1                        = 0x4e,
1948         SPI_PERF_PS_CTL_FPOS_BIN2                        = 0x4f,
1949         SPI_PERF_PS_CTL_PRIM_BIN0                        = 0x50,
1950         SPI_PERF_PS_CTL_PRIM_BIN1                        = 0x51,
1951         SPI_PERF_PS_CTL_CNF_BIN2                         = 0x52,
1952         SPI_PERF_PS_CTL_CNF_BIN3                         = 0x53,
1953         SPI_PERF_PS_CTL_CRAWLER_STALL                    = 0x54,
1954         SPI_PERF_PS_CTL_LDS_RES_FULL                     = 0x55,
1955         SPI_PERF_PS_PERS_UPD_FULL0                       = 0x56,
1956         SPI_PERF_PS_PERS_UPD_FULL1                       = 0x57,
1957         SPI_PERF_PIX_ALLOC_PEND_CNT                      = 0x58,
1958         SPI_PERF_PIX_ALLOC_SCB_STALL                     = 0x59,
1959         SPI_PERF_PIX_ALLOC_DB0_STALL                     = 0x5a,
1960         SPI_PERF_PIX_ALLOC_DB1_STALL                     = 0x5b,
1961         SPI_PERF_PIX_ALLOC_DB2_STALL                     = 0x5c,
1962         SPI_PERF_PIX_ALLOC_DB3_STALL                     = 0x5d,
1963         SPI_PERF_LDS0_PC_VALID                           = 0x5e,
1964         SPI_PERF_LDS1_PC_VALID                           = 0x5f,
1965         SPI_PERF_RA_PIPE_REQ_BIN2                        = 0x60,
1966         SPI_PERF_RA_TASK_REQ_BIN3                        = 0x61,
1967         SPI_PERF_RA_WR_CTL_FULL                          = 0x62,
1968         SPI_PERF_RA_REQ_NO_ALLOC                         = 0x63,
1969         SPI_PERF_RA_REQ_NO_ALLOC_PS                      = 0x64,
1970         SPI_PERF_RA_REQ_NO_ALLOC_VS                      = 0x65,
1971         SPI_PERF_RA_REQ_NO_ALLOC_GS                      = 0x66,
1972         SPI_PERF_RA_REQ_NO_ALLOC_ES                      = 0x67,
1973         SPI_PERF_RA_REQ_NO_ALLOC_HS                      = 0x68,
1974         SPI_PERF_RA_REQ_NO_ALLOC_LS                      = 0x69,
1975         SPI_PERF_RA_REQ_NO_ALLOC_CSG                     = 0x6a,
1976         SPI_PERF_RA_REQ_NO_ALLOC_CSN                     = 0x6b,
1977         SPI_PERF_RA_RES_STALL_PS                         = 0x6c,
1978         SPI_PERF_RA_RES_STALL_VS                         = 0x6d,
1979         SPI_PERF_RA_RES_STALL_GS                         = 0x6e,
1980         SPI_PERF_RA_RES_STALL_ES                         = 0x6f,
1981         SPI_PERF_RA_RES_STALL_HS                         = 0x70,
1982         SPI_PERF_RA_RES_STALL_LS                         = 0x71,
1983         SPI_PERF_RA_RES_STALL_CSG                        = 0x72,
1984         SPI_PERF_RA_RES_STALL_CSN                        = 0x73,
1985         SPI_PERF_RA_TMP_STALL_PS                         = 0x74,
1986         SPI_PERF_RA_TMP_STALL_VS                         = 0x75,
1987         SPI_PERF_RA_TMP_STALL_GS                         = 0x76,
1988         SPI_PERF_RA_TMP_STALL_ES                         = 0x77,
1989         SPI_PERF_RA_TMP_STALL_HS                         = 0x78,
1990         SPI_PERF_RA_TMP_STALL_LS                         = 0x79,
1991         SPI_PERF_RA_TMP_STALL_CSG                        = 0x7a,
1992         SPI_PERF_RA_TMP_STALL_CSN                        = 0x7b,
1993         SPI_PERF_RA_WAVE_SIMD_FULL_PS                    = 0x7c,
1994         SPI_PERF_RA_WAVE_SIMD_FULL_VS                    = 0x7d,
1995         SPI_PERF_RA_WAVE_SIMD_FULL_GS                    = 0x7e,
1996         SPI_PERF_RA_WAVE_SIMD_FULL_ES                    = 0x7f,
1997         SPI_PERF_RA_WAVE_SIMD_FULL_HS                    = 0x80,
1998         SPI_PERF_RA_WAVE_SIMD_FULL_LS                    = 0x81,
1999         SPI_PERF_RA_WAVE_SIMD_FULL_CSG                   = 0x82,
2000         SPI_PERF_RA_WAVE_SIMD_FULL_CSN                   = 0x83,
2001         SPI_PERF_RA_VGPR_SIMD_FULL_PS                    = 0x84,
2002         SPI_PERF_RA_VGPR_SIMD_FULL_VS                    = 0x85,
2003         SPI_PERF_RA_VGPR_SIMD_FULL_GS                    = 0x86,
2004         SPI_PERF_RA_VGPR_SIMD_FULL_ES                    = 0x87,
2005         SPI_PERF_RA_VGPR_SIMD_FULL_HS                    = 0x88,
2006         SPI_PERF_RA_VGPR_SIMD_FULL_LS                    = 0x89,
2007         SPI_PERF_RA_VGPR_SIMD_FULL_CSG                   = 0x8a,
2008         SPI_PERF_RA_VGPR_SIMD_FULL_CSN                   = 0x8b,
2009         SPI_PERF_RA_SGPR_SIMD_FULL_PS                    = 0x8c,
2010         SPI_PERF_RA_SGPR_SIMD_FULL_VS                    = 0x8d,
2011         SPI_PERF_RA_SGPR_SIMD_FULL_GS                    = 0x8e,
2012         SPI_PERF_RA_SGPR_SIMD_FULL_ES                    = 0x8f,
2013         SPI_PERF_RA_SGPR_SIMD_FULL_HS                    = 0x90,
2014         SPI_PERF_RA_SGPR_SIMD_FULL_LS                    = 0x91,
2015         SPI_PERF_RA_SGPR_SIMD_FULL_CSG                   = 0x92,
2016         SPI_PERF_RA_SGPR_SIMD_FULL_CSN                   = 0x93,
2017         SPI_PERF_RA_LDS_CU_FULL_PS                       = 0x94,
2018         SPI_PERF_RA_LDS_CU_FULL_LS                       = 0x95,
2019         SPI_PERF_RA_LDS_CU_FULL_ES                       = 0x96,
2020         SPI_PERF_RA_LDS_CU_FULL_CSG                      = 0x97,
2021         SPI_PERF_RA_LDS_CU_FULL_CSN                      = 0x98,
2022         SPI_PERF_RA_BAR_CU_FULL_HS                       = 0x99,
2023         SPI_PERF_RA_BAR_CU_FULL_CSG                      = 0x9a,
2024         SPI_PERF_RA_BAR_CU_FULL_CSN                      = 0x9b,
2025         SPI_PERF_RA_BULKY_CU_FULL_CSG                    = 0x9c,
2026         SPI_PERF_RA_BULKY_CU_FULL_CSN                    = 0x9d,
2027         SPI_PERF_RA_TGLIM_CU_FULL_CSG                    = 0x9e,
2028         SPI_PERF_RA_TGLIM_CU_FULL_CSN                    = 0x9f,
2029         SPI_PERF_RA_WVLIM_STALL_PS                       = 0xa0,
2030         SPI_PERF_RA_WVLIM_STALL_VS                       = 0xa1,
2031         SPI_PERF_RA_WVLIM_STALL_GS                       = 0xa2,
2032         SPI_PERF_RA_WVLIM_STALL_ES                       = 0xa3,
2033         SPI_PERF_RA_WVLIM_STALL_HS                       = 0xa4,
2034         SPI_PERF_RA_WVLIM_STALL_LS                       = 0xa5,
2035         SPI_PERF_RA_WVLIM_STALL_CSG                      = 0xa6,
2036         SPI_PERF_RA_WVLIM_STALL_CSN                      = 0xa7,
2037         SPI_PERF_RA_PS_LOCK_NA                           = 0xa8,
2038         SPI_PERF_RA_VS_LOCK                              = 0xa9,
2039         SPI_PERF_RA_GS_LOCK                              = 0xaa,
2040         SPI_PERF_RA_ES_LOCK                              = 0xab,
2041         SPI_PERF_RA_HS_LOCK                              = 0xac,
2042         SPI_PERF_RA_LS_LOCK                              = 0xad,
2043         SPI_PERF_RA_CSG_LOCK                             = 0xae,
2044         SPI_PERF_RA_CSN_LOCK                             = 0xaf,
2045         SPI_PERF_RA_RSV_UPD                              = 0xb0,
2046         SPI_PERF_EXP_ARB_COL_CNT                         = 0xb1,
2047         SPI_PERF_EXP_ARB_PAR_CNT                         = 0xb2,
2048         SPI_PERF_EXP_ARB_POS_CNT                         = 0xb3,
2049         SPI_PERF_EXP_ARB_GDS_CNT                         = 0xb4,
2050         SPI_PERF_CLKGATE_BUSY_STALL                      = 0xb5,
2051         SPI_PERF_CLKGATE_ACTIVE_STALL                    = 0xb6,
2052         SPI_PERF_CLKGATE_ALL_CLOCKS_ON                   = 0xb7,
2053         SPI_PERF_CLKGATE_CGTT_DYN_ON                     = 0xb8,
2054         SPI_PERF_CLKGATE_CGTT_REG_ON                     = 0xb9,
2055         SPI_PERF_NUM_VS_POS_EXPORTS                      = 0xba,
2056         SPI_PERF_NUM_VS_PARAM_EXPORTS                    = 0xbb,
2057         SPI_PERF_NUM_PS_COL_EXPORTS                      = 0xbc,
2058         SPI_PERF_ES_GRP_FIFO_FULL                        = 0xbd,
2059         SPI_PERF_GS_GRP_FIFO_FULL                        = 0xbe,
2060         SPI_PERF_HS_GRP_FIFO_FULL                        = 0xbf,
2061         SPI_PERF_LS_GRP_FIFO_FULL                        = 0xc0,
2062         SPI_PERF_VS_ALLOC_CNT                            = 0xc1,
2063         SPI_PERF_VS_LATE_ALLOC_ACCUM                     = 0xc2,
2064         SPI_PERF_PC_ALLOC_CNT                            = 0xc3,
2065         SPI_PERF_PC_ALLOC_ACCUM                          = 0xc4,
2066 } SPI_PERFCNT_SEL;
2067 typedef enum SPI_SHADER_FORMAT {
2068         SPI_SHADER_NONE                                  = 0x0,
2069         SPI_SHADER_1COMP                                 = 0x1,
2070         SPI_SHADER_2COMP                                 = 0x2,
2071         SPI_SHADER_4COMPRESS                             = 0x3,
2072         SPI_SHADER_4COMP                                 = 0x4,
2073 } SPI_SHADER_FORMAT;
2074 typedef enum SPI_SHADER_EX_FORMAT {
2075         SPI_SHADER_ZERO                                  = 0x0,
2076         SPI_SHADER_32_R                                  = 0x1,
2077         SPI_SHADER_32_GR                                 = 0x2,
2078         SPI_SHADER_32_AR                                 = 0x3,
2079         SPI_SHADER_FP16_ABGR                             = 0x4,
2080         SPI_SHADER_UNORM16_ABGR                          = 0x5,
2081         SPI_SHADER_SNORM16_ABGR                          = 0x6,
2082         SPI_SHADER_UINT16_ABGR                           = 0x7,
2083         SPI_SHADER_SINT16_ABGR                           = 0x8,
2084         SPI_SHADER_32_ABGR                               = 0x9,
2085 } SPI_SHADER_EX_FORMAT;
2086 typedef enum CLKGATE_SM_MODE {
2087         ON_SEQ                                           = 0x0,
2088         OFF_SEQ                                          = 0x1,
2089         PROG_SEQ                                         = 0x2,
2090         READ_SEQ                                         = 0x3,
2091         SM_MODE_RESERVED                                 = 0x4,
2092 } CLKGATE_SM_MODE;
2093 typedef enum CLKGATE_BASE_MODE {
2094         MULT_8                                           = 0x0,
2095         MULT_16                                          = 0x1,
2096 } CLKGATE_BASE_MODE;
2097 typedef enum SQ_TEX_CLAMP {
2098         SQ_TEX_WRAP                                      = 0x0,
2099         SQ_TEX_MIRROR                                    = 0x1,
2100         SQ_TEX_CLAMP_LAST_TEXEL                          = 0x2,
2101         SQ_TEX_MIRROR_ONCE_LAST_TEXEL                    = 0x3,
2102         SQ_TEX_CLAMP_HALF_BORDER                         = 0x4,
2103         SQ_TEX_MIRROR_ONCE_HALF_BORDER                   = 0x5,
2104         SQ_TEX_CLAMP_BORDER                              = 0x6,
2105         SQ_TEX_MIRROR_ONCE_BORDER                        = 0x7,
2106 } SQ_TEX_CLAMP;
2107 typedef enum SQ_TEX_XY_FILTER {
2108         SQ_TEX_XY_FILTER_POINT                           = 0x0,
2109         SQ_TEX_XY_FILTER_BILINEAR                        = 0x1,
2110         SQ_TEX_XY_FILTER_ANISO_POINT                     = 0x2,
2111         SQ_TEX_XY_FILTER_ANISO_BILINEAR                  = 0x3,
2112 } SQ_TEX_XY_FILTER;
2113 typedef enum SQ_TEX_Z_FILTER {
2114         SQ_TEX_Z_FILTER_NONE                             = 0x0,
2115         SQ_TEX_Z_FILTER_POINT                            = 0x1,
2116         SQ_TEX_Z_FILTER_LINEAR                           = 0x2,
2117 } SQ_TEX_Z_FILTER;
2118 typedef enum SQ_TEX_MIP_FILTER {
2119         SQ_TEX_MIP_FILTER_NONE                           = 0x0,
2120         SQ_TEX_MIP_FILTER_POINT                          = 0x1,
2121         SQ_TEX_MIP_FILTER_LINEAR                         = 0x2,
2122         SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ                = 0x3,
2123 } SQ_TEX_MIP_FILTER;
2124 typedef enum SQ_TEX_ANISO_RATIO {
2125         SQ_TEX_ANISO_RATIO_1                             = 0x0,
2126         SQ_TEX_ANISO_RATIO_2                             = 0x1,
2127         SQ_TEX_ANISO_RATIO_4                             = 0x2,
2128         SQ_TEX_ANISO_RATIO_8                             = 0x3,
2129         SQ_TEX_ANISO_RATIO_16                            = 0x4,
2130 } SQ_TEX_ANISO_RATIO;
2131 typedef enum SQ_TEX_DEPTH_COMPARE {
2132         SQ_TEX_DEPTH_COMPARE_NEVER                       = 0x0,
2133         SQ_TEX_DEPTH_COMPARE_LESS                        = 0x1,
2134         SQ_TEX_DEPTH_COMPARE_EQUAL                       = 0x2,
2135         SQ_TEX_DEPTH_COMPARE_LESSEQUAL                   = 0x3,
2136         SQ_TEX_DEPTH_COMPARE_GREATER                     = 0x4,
2137         SQ_TEX_DEPTH_COMPARE_NOTEQUAL                    = 0x5,
2138         SQ_TEX_DEPTH_COMPARE_GREATEREQUAL                = 0x6,
2139         SQ_TEX_DEPTH_COMPARE_ALWAYS                      = 0x7,
2140 } SQ_TEX_DEPTH_COMPARE;
2141 typedef enum SQ_TEX_BORDER_COLOR {
2142         SQ_TEX_BORDER_COLOR_TRANS_BLACK                  = 0x0,
2143         SQ_TEX_BORDER_COLOR_OPAQUE_BLACK                 = 0x1,
2144         SQ_TEX_BORDER_COLOR_OPAQUE_WHITE                 = 0x2,
2145         SQ_TEX_BORDER_COLOR_REGISTER                     = 0x3,
2146 } SQ_TEX_BORDER_COLOR;
2147 typedef enum SQ_RSRC_BUF_TYPE {
2148         SQ_RSRC_BUF                                      = 0x0,
2149         SQ_RSRC_BUF_RSVD_1                               = 0x1,
2150         SQ_RSRC_BUF_RSVD_2                               = 0x2,
2151         SQ_RSRC_BUF_RSVD_3                               = 0x3,
2152 } SQ_RSRC_BUF_TYPE;
2153 typedef enum SQ_RSRC_IMG_TYPE {
2154         SQ_RSRC_IMG_RSVD_0                               = 0x0,
2155         SQ_RSRC_IMG_RSVD_1                               = 0x1,
2156         SQ_RSRC_IMG_RSVD_2                               = 0x2,
2157         SQ_RSRC_IMG_RSVD_3                               = 0x3,
2158         SQ_RSRC_IMG_RSVD_4                               = 0x4,
2159         SQ_RSRC_IMG_RSVD_5                               = 0x5,
2160         SQ_RSRC_IMG_RSVD_6                               = 0x6,
2161         SQ_RSRC_IMG_RSVD_7                               = 0x7,
2162         SQ_RSRC_IMG_1D                                   = 0x8,
2163         SQ_RSRC_IMG_2D                                   = 0x9,
2164         SQ_RSRC_IMG_3D                                   = 0xa,
2165         SQ_RSRC_IMG_CUBE                                 = 0xb,
2166         SQ_RSRC_IMG_1D_ARRAY                             = 0xc,
2167         SQ_RSRC_IMG_2D_ARRAY                             = 0xd,
2168         SQ_RSRC_IMG_2D_MSAA                              = 0xe,
2169         SQ_RSRC_IMG_2D_MSAA_ARRAY                        = 0xf,
2170 } SQ_RSRC_IMG_TYPE;
2171 typedef enum SQ_RSRC_FLAT_TYPE {
2172         SQ_RSRC_FLAT_RSVD_0                              = 0x0,
2173         SQ_RSRC_FLAT                                     = 0x1,
2174         SQ_RSRC_FLAT_RSVD_2                              = 0x2,
2175         SQ_RSRC_FLAT_RSVD_3                              = 0x3,
2176 } SQ_RSRC_FLAT_TYPE;
2177 typedef enum SQ_IMG_FILTER_TYPE {
2178         SQ_IMG_FILTER_MODE_BLEND                         = 0x0,
2179         SQ_IMG_FILTER_MODE_MIN                           = 0x1,
2180         SQ_IMG_FILTER_MODE_MAX                           = 0x2,
2181 } SQ_IMG_FILTER_TYPE;
2182 typedef enum SQ_SEL_XYZW01 {
2183         SQ_SEL_0                                         = 0x0,
2184         SQ_SEL_1                                         = 0x1,
2185         SQ_SEL_RESERVED_0                                = 0x2,
2186         SQ_SEL_RESERVED_1                                = 0x3,
2187         SQ_SEL_X                                         = 0x4,
2188         SQ_SEL_Y                                         = 0x5,
2189         SQ_SEL_Z                                         = 0x6,
2190         SQ_SEL_W                                         = 0x7,
2191 } SQ_SEL_XYZW01;
2192 typedef enum SQ_WAVE_TYPE {
2193         SQ_WAVE_TYPE_PS                                  = 0x0,
2194         SQ_WAVE_TYPE_VS                                  = 0x1,
2195         SQ_WAVE_TYPE_GS                                  = 0x2,
2196         SQ_WAVE_TYPE_ES                                  = 0x3,
2197         SQ_WAVE_TYPE_HS                                  = 0x4,
2198         SQ_WAVE_TYPE_LS                                  = 0x5,
2199         SQ_WAVE_TYPE_CS                                  = 0x6,
2200         SQ_WAVE_TYPE_PS1                                 = 0x7,
2201 } SQ_WAVE_TYPE;
2202 typedef enum SQ_THREAD_TRACE_TOKEN_TYPE {
2203         SQ_THREAD_TRACE_TOKEN_MISC                       = 0x0,
2204         SQ_THREAD_TRACE_TOKEN_TIMESTAMP                  = 0x1,
2205         SQ_THREAD_TRACE_TOKEN_REG                        = 0x2,
2206         SQ_THREAD_TRACE_TOKEN_WAVE_START                 = 0x3,
2207         SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC                 = 0x4,
2208         SQ_THREAD_TRACE_TOKEN_REG_CSPRIV                 = 0x5,
2209         SQ_THREAD_TRACE_TOKEN_WAVE_END                   = 0x6,
2210         SQ_THREAD_TRACE_TOKEN_EVENT                      = 0x7,
2211         SQ_THREAD_TRACE_TOKEN_EVENT_CS                   = 0x8,
2212         SQ_THREAD_TRACE_TOKEN_EVENT_GFX1                 = 0x9,
2213         SQ_THREAD_TRACE_TOKEN_INST                       = 0xa,
2214         SQ_THREAD_TRACE_TOKEN_INST_PC                    = 0xb,
2215         SQ_THREAD_TRACE_TOKEN_INST_USERDATA              = 0xc,
2216         SQ_THREAD_TRACE_TOKEN_ISSUE                      = 0xd,
2217         SQ_THREAD_TRACE_TOKEN_PERF                       = 0xe,
2218         SQ_THREAD_TRACE_TOKEN_REG_CS                     = 0xf,
2219 } SQ_THREAD_TRACE_TOKEN_TYPE;
2220 typedef enum SQ_THREAD_TRACE_MISC_TOKEN_TYPE {
2221         SQ_THREAD_TRACE_MISC_TOKEN_TIME                  = 0x0,
2222         SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET            = 0x1,
2223         SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST           = 0x2,
2224         SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC             = 0x3,
2225         SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN    = 0x4,
2226         SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END      = 0x5,
2227         SQ_THREAD_TRACE_MISC_TOKEN_SAVECTX               = 0x6,
2228         SQ_THREAD_TRACE_MISC_TOKEN_SHOOT_DOWN            = 0x7,
2229 } SQ_THREAD_TRACE_MISC_TOKEN_TYPE;
2230 typedef enum SQ_THREAD_TRACE_INST_TYPE {
2231         SQ_THREAD_TRACE_INST_TYPE_SMEM_RD                = 0x0,
2232         SQ_THREAD_TRACE_INST_TYPE_SALU_32                = 0x1,
2233         SQ_THREAD_TRACE_INST_TYPE_VMEM_RD                = 0x2,
2234         SQ_THREAD_TRACE_INST_TYPE_VMEM_WR                = 0x3,
2235         SQ_THREAD_TRACE_INST_TYPE_FLAT_WR                = 0x4,
2236         SQ_THREAD_TRACE_INST_TYPE_VALU_32                = 0x5,
2237         SQ_THREAD_TRACE_INST_TYPE_LDS                    = 0x6,
2238         SQ_THREAD_TRACE_INST_TYPE_PC                     = 0x7,
2239         SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS             = 0x8,
2240         SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX             = 0x9,
2241         SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL         = 0xa,
2242         SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS         = 0xb,
2243         SQ_THREAD_TRACE_INST_TYPE_JUMP                   = 0xc,
2244         SQ_THREAD_TRACE_INST_TYPE_NEXT                   = 0xd,
2245         SQ_THREAD_TRACE_INST_TYPE_FLAT_RD                = 0xe,
2246         SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG              = 0xf,
2247         SQ_THREAD_TRACE_INST_TYPE_SMEM_WR                = 0x10,
2248         SQ_THREAD_TRACE_INST_TYPE_SALU_64                = 0x11,
2249         SQ_THREAD_TRACE_INST_TYPE_VALU_64                = 0x12,
2250         SQ_THREAD_TRACE_INST_TYPE_SMEM_RD_REPLAY         = 0x13,
2251         SQ_THREAD_TRACE_INST_TYPE_SMEM_WR_REPLAY         = 0x14,
2252         SQ_THREAD_TRACE_INST_TYPE_VMEM_RD_REPLAY         = 0x15,
2253         SQ_THREAD_TRACE_INST_TYPE_VMEM_WR_REPLAY         = 0x16,
2254         SQ_THREAD_TRACE_INST_TYPE_FLAT_RD_REPLAY         = 0x17,
2255         SQ_THREAD_TRACE_INST_TYPE_FLAT_WR_REPLAY         = 0x18,
2256 } SQ_THREAD_TRACE_INST_TYPE;
2257 typedef enum SQ_THREAD_TRACE_REG_TYPE {
2258         SQ_THREAD_TRACE_REG_TYPE_EVENT                   = 0x0,
2259         SQ_THREAD_TRACE_REG_TYPE_DRAW                    = 0x1,
2260         SQ_THREAD_TRACE_REG_TYPE_DISPATCH                = 0x2,
2261         SQ_THREAD_TRACE_REG_TYPE_USERDATA                = 0x3,
2262         SQ_THREAD_TRACE_REG_TYPE_MARKER                  = 0x4,
2263         SQ_THREAD_TRACE_REG_TYPE_GFXDEC                  = 0x5,
2264         SQ_THREAD_TRACE_REG_TYPE_SHDEC                   = 0x6,
2265         SQ_THREAD_TRACE_REG_TYPE_OTHER                   = 0x7,
2266 } SQ_THREAD_TRACE_REG_TYPE;
2267 typedef enum SQ_THREAD_TRACE_REG_OP {
2268         SQ_THREAD_TRACE_REG_OP_READ                      = 0x0,
2269         SQ_THREAD_TRACE_REG_OP_WRITE                     = 0x1,
2270 } SQ_THREAD_TRACE_REG_OP;
2271 typedef enum SQ_THREAD_TRACE_MODE_SEL {
2272         SQ_THREAD_TRACE_MODE_OFF                         = 0x0,
2273         SQ_THREAD_TRACE_MODE_ON                          = 0x1,
2274 } SQ_THREAD_TRACE_MODE_SEL;
2275 typedef enum SQ_THREAD_TRACE_CAPTURE_MODE {
2276         SQ_THREAD_TRACE_CAPTURE_MODE_ALL                 = 0x0,
2277         SQ_THREAD_TRACE_CAPTURE_MODE_SELECT              = 0x1,
2278         SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL       = 0x2,
2279 } SQ_THREAD_TRACE_CAPTURE_MODE;
2280 typedef enum SQ_THREAD_TRACE_VM_ID_MASK {
2281         SQ_THREAD_TRACE_VM_ID_MASK_SINGLE                = 0x0,
2282         SQ_THREAD_TRACE_VM_ID_MASK_ALL                   = 0x1,
2283         SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL         = 0x2,
2284 } SQ_THREAD_TRACE_VM_ID_MASK;
2285 typedef enum SQ_THREAD_TRACE_WAVE_MASK {
2286         SQ_THREAD_TRACE_WAVE_MASK_NONE                   = 0x0,
2287         SQ_THREAD_TRACE_WAVE_MASK_ALL                    = 0x1,
2288 } SQ_THREAD_TRACE_WAVE_MASK;
2289 typedef enum SQ_THREAD_TRACE_ISSUE {
2290         SQ_THREAD_TRACE_ISSUE_NULL                       = 0x0,
2291         SQ_THREAD_TRACE_ISSUE_STALL                      = 0x1,
2292         SQ_THREAD_TRACE_ISSUE_INST                       = 0x2,
2293         SQ_THREAD_TRACE_ISSUE_IMMED                      = 0x3,
2294 } SQ_THREAD_TRACE_ISSUE;
2295 typedef enum SQ_THREAD_TRACE_ISSUE_MASK {
2296         SQ_THREAD_TRACE_ISSUE_MASK_ALL                   = 0x0,
2297         SQ_THREAD_TRACE_ISSUE_MASK_STALLED               = 0x1,
2298         SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED     = 0x2,
2299         SQ_THREAD_TRACE_ISSUE_MASK_IMMED                 = 0x3,
2300 } SQ_THREAD_TRACE_ISSUE_MASK;
2301 typedef enum SQ_PERF_SEL {
2302         SQ_PERF_SEL_NONE                                 = 0x0,
2303         SQ_PERF_SEL_ACCUM_PREV                           = 0x1,
2304         SQ_PERF_SEL_CYCLES                               = 0x2,
2305         SQ_PERF_SEL_BUSY_CYCLES                          = 0x3,
2306         SQ_PERF_SEL_WAVES                                = 0x4,
2307         SQ_PERF_SEL_LEVEL_WAVES                          = 0x5,
2308         SQ_PERF_SEL_WAVES_EQ_64                          = 0x6,
2309         SQ_PERF_SEL_WAVES_LT_64                          = 0x7,
2310         SQ_PERF_SEL_WAVES_LT_48                          = 0x8,
2311         SQ_PERF_SEL_WAVES_LT_32                          = 0x9,
2312         SQ_PERF_SEL_WAVES_LT_16                          = 0xa,
2313         SQ_PERF_SEL_WAVES_CU                             = 0xb,
2314         SQ_PERF_SEL_LEVEL_WAVES_CU                       = 0xc,
2315         SQ_PERF_SEL_BUSY_CU_CYCLES                       = 0xd,
2316         SQ_PERF_SEL_ITEMS                                = 0xe,
2317         SQ_PERF_SEL_QUADS                                = 0xf,
2318         SQ_PERF_SEL_EVENTS                               = 0x10,
2319         SQ_PERF_SEL_SURF_SYNCS                           = 0x11,
2320         SQ_PERF_SEL_TTRACE_REQS                          = 0x12,
2321         SQ_PERF_SEL_TTRACE_INFLIGHT_REQS                 = 0x13,
2322         SQ_PERF_SEL_TTRACE_STALL                         = 0x14,
2323         SQ_PERF_SEL_MSG_CNTR                             = 0x15,
2324         SQ_PERF_SEL_MSG_PERF                             = 0x16,
2325         SQ_PERF_SEL_MSG_GSCNT                            = 0x17,
2326         SQ_PERF_SEL_MSG_INTERRUPT                        = 0x18,
2327         SQ_PERF_SEL_INSTS                                = 0x19,
2328         SQ_PERF_SEL_INSTS_VALU                           = 0x1a,
2329         SQ_PERF_SEL_INSTS_VMEM_WR                        = 0x1b,
2330         SQ_PERF_SEL_INSTS_VMEM_RD                        = 0x1c,
2331         SQ_PERF_SEL_INSTS_VMEM                           = 0x1d,
2332         SQ_PERF_SEL_INSTS_SALU                           = 0x1e,
2333         SQ_PERF_SEL_INSTS_SMEM                           = 0x1f,
2334         SQ_PERF_SEL_INSTS_FLAT                           = 0x20,
2335         SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY                  = 0x21,
2336         SQ_PERF_SEL_INSTS_LDS                            = 0x22,
2337         SQ_PERF_SEL_INSTS_GDS                            = 0x23,
2338         SQ_PERF_SEL_INSTS_EXP                            = 0x24,
2339         SQ_PERF_SEL_INSTS_EXP_GDS                        = 0x25,
2340         SQ_PERF_SEL_INSTS_BRANCH                         = 0x26,
2341         SQ_PERF_SEL_INSTS_SENDMSG                        = 0x27,
2342         SQ_PERF_SEL_INSTS_VSKIPPED                       = 0x28,
2343         SQ_PERF_SEL_INST_LEVEL_VMEM                      = 0x29,
2344         SQ_PERF_SEL_INST_LEVEL_SMEM                      = 0x2a,
2345         SQ_PERF_SEL_INST_LEVEL_LDS                       = 0x2b,
2346         SQ_PERF_SEL_INST_LEVEL_GDS                       = 0x2c,
2347         SQ_PERF_SEL_INST_LEVEL_EXP                       = 0x2d,
2348         SQ_PERF_SEL_WAVE_CYCLES                          = 0x2e,
2349         SQ_PERF_SEL_WAVE_READY                           = 0x2f,
2350         SQ_PERF_SEL_WAIT_CNT_VM                          = 0x30,
2351         SQ_PERF_SEL_WAIT_CNT_LGKM                        = 0x31,
2352         SQ_PERF_SEL_WAIT_CNT_EXP                         = 0x32,
2353         SQ_PERF_SEL_WAIT_CNT_ANY                         = 0x33,
2354         SQ_PERF_SEL_WAIT_BARRIER                         = 0x34,
2355         SQ_PERF_SEL_WAIT_EXP_ALLOC                       = 0x35,
2356         SQ_PERF_SEL_WAIT_SLEEP                           = 0x36,
2357         SQ_PERF_SEL_WAIT_OTHER                           = 0x37,
2358         SQ_PERF_SEL_WAIT_ANY                             = 0x38,
2359         SQ_PERF_SEL_WAIT_TTRACE                          = 0x39,
2360         SQ_PERF_SEL_WAIT_IFETCH                          = 0x3a,
2361         SQ_PERF_SEL_WAIT_INST_VMEM                       = 0x3b,
2362         SQ_PERF_SEL_WAIT_INST_SCA                        = 0x3c,
2363         SQ_PERF_SEL_WAIT_INST_LDS                        = 0x3d,
2364         SQ_PERF_SEL_WAIT_INST_VALU                       = 0x3e,
2365         SQ_PERF_SEL_WAIT_INST_EXP_GDS                    = 0x3f,
2366         SQ_PERF_SEL_WAIT_INST_MISC                       = 0x40,
2367         SQ_PERF_SEL_WAIT_INST_FLAT                       = 0x41,
2368         SQ_PERF_SEL_ACTIVE_INST_ANY                      = 0x42,
2369         SQ_PERF_SEL_ACTIVE_INST_VMEM                     = 0x43,
2370         SQ_PERF_SEL_ACTIVE_INST_LDS                      = 0x44,
2371         SQ_PERF_SEL_ACTIVE_INST_VALU                     = 0x45,
2372         SQ_PERF_SEL_ACTIVE_INST_SCA                      = 0x46,
2373         SQ_PERF_SEL_ACTIVE_INST_EXP_GDS                  = 0x47,
2374         SQ_PERF_SEL_ACTIVE_INST_MISC                     = 0x48,
2375         SQ_PERF_SEL_ACTIVE_INST_FLAT                     = 0x49,
2376         SQ_PERF_SEL_INST_CYCLES_VMEM_WR                  = 0x4a,
2377         SQ_PERF_SEL_INST_CYCLES_VMEM_RD                  = 0x4b,
2378         SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR                = 0x4c,
2379         SQ_PERF_SEL_INST_CYCLES_VMEM_DATA                = 0x4d,
2380         SQ_PERF_SEL_INST_CYCLES_VMEM_CMD                 = 0x4e,
2381         SQ_PERF_SEL_INST_CYCLES_VMEM                     = 0x4f,
2382         SQ_PERF_SEL_INST_CYCLES_LDS                      = 0x50,
2383         SQ_PERF_SEL_INST_CYCLES_VALU                     = 0x51,
2384         SQ_PERF_SEL_INST_CYCLES_EXP                      = 0x52,
2385         SQ_PERF_SEL_INST_CYCLES_GDS                      = 0x53,
2386         SQ_PERF_SEL_INST_CYCLES_SCA                      = 0x54,
2387         SQ_PERF_SEL_INST_CYCLES_SMEM                     = 0x55,
2388         SQ_PERF_SEL_INST_CYCLES_SALU                     = 0x56,
2389         SQ_PERF_SEL_INST_CYCLES_EXP_GDS                  = 0x57,
2390         SQ_PERF_SEL_INST_CYCLES_MISC                     = 0x58,
2391         SQ_PERF_SEL_THREAD_CYCLES_VALU                   = 0x59,
2392         SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX               = 0x5a,
2393         SQ_PERF_SEL_IFETCH                               = 0x5b,
2394         SQ_PERF_SEL_IFETCH_LEVEL                         = 0x5c,
2395         SQ_PERF_SEL_CBRANCH_FORK                         = 0x5d,
2396         SQ_PERF_SEL_CBRANCH_FORK_SPLIT                   = 0x5e,
2397         SQ_PERF_SEL_VALU_LDS_DIRECT_RD                   = 0x5f,
2398         SQ_PERF_SEL_VALU_LDS_INTERP_OP                   = 0x60,
2399         SQ_PERF_SEL_LDS_BANK_CONFLICT                    = 0x61,
2400         SQ_PERF_SEL_LDS_ADDR_CONFLICT                    = 0x62,
2401         SQ_PERF_SEL_LDS_UNALIGNED_STALL                  = 0x63,
2402         SQ_PERF_SEL_LDS_MEM_VIOLATIONS                   = 0x64,
2403         SQ_PERF_SEL_LDS_ATOMIC_RETURN                    = 0x65,
2404         SQ_PERF_SEL_LDS_IDX_ACTIVE                       = 0x66,
2405         SQ_PERF_SEL_VALU_DEP_STALL                       = 0x67,
2406         SQ_PERF_SEL_VALU_STARVE                          = 0x68,
2407         SQ_PERF_SEL_EXP_REQ_FIFO_FULL                    = 0x69,
2408         SQ_PERF_SEL_LDS_BACK2BACK_STALL                  = 0x6a,
2409         SQ_PERF_SEL_LDS_DATA_FIFO_FULL                   = 0x6b,
2410         SQ_PERF_SEL_LDS_CMD_FIFO_FULL                    = 0x6c,
2411         SQ_PERF_SEL_VMEM_BACK2BACK_STALL                 = 0x6d,
2412         SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL               = 0x6e,
2413         SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL                = 0x6f,
2414         SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY                = 0x70,
2415         SQ_PERF_SEL_VMEM_WR_BACK2BACK_STALL              = 0x71,
2416         SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL            = 0x72,
2417         SQ_PERF_SEL_VALU_SRC_C_CONFLICT                  = 0x73,
2418         SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT              = 0x74,
2419         SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT              = 0x75,
2420         SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT                 = 0x76,
2421         SQ_PERF_SEL_LDS_SRC_CD_CONFLICT                  = 0x77,
2422         SQ_PERF_SEL_SRC_CD_BUSY                          = 0x78,
2423         SQ_PERF_SEL_PT_POWER_STALL                       = 0x79,
2424         SQ_PERF_SEL_USER0                                = 0x7a,
2425         SQ_PERF_SEL_USER1                                = 0x7b,
2426         SQ_PERF_SEL_USER2                                = 0x7c,
2427         SQ_PERF_SEL_USER3                                = 0x7d,
2428         SQ_PERF_SEL_USER4                                = 0x7e,
2429         SQ_PERF_SEL_USER5                                = 0x7f,
2430         SQ_PERF_SEL_USER6                                = 0x80,
2431         SQ_PERF_SEL_USER7                                = 0x81,
2432         SQ_PERF_SEL_USER8                                = 0x82,
2433         SQ_PERF_SEL_USER9                                = 0x83,
2434         SQ_PERF_SEL_USER10                               = 0x84,
2435         SQ_PERF_SEL_USER11                               = 0x85,
2436         SQ_PERF_SEL_USER12                               = 0x86,
2437         SQ_PERF_SEL_USER13                               = 0x87,
2438         SQ_PERF_SEL_USER14                               = 0x88,
2439         SQ_PERF_SEL_USER15                               = 0x89,
2440         SQ_PERF_SEL_USER_LEVEL0                          = 0x8a,
2441         SQ_PERF_SEL_USER_LEVEL1                          = 0x8b,
2442         SQ_PERF_SEL_USER_LEVEL2                          = 0x8c,
2443         SQ_PERF_SEL_USER_LEVEL3                          = 0x8d,
2444         SQ_PERF_SEL_USER_LEVEL4                          = 0x8e,
2445         SQ_PERF_SEL_USER_LEVEL5                          = 0x8f,
2446         SQ_PERF_SEL_USER_LEVEL6                          = 0x90,
2447         SQ_PERF_SEL_USER_LEVEL7                          = 0x91,
2448         SQ_PERF_SEL_USER_LEVEL8                          = 0x92,
2449         SQ_PERF_SEL_USER_LEVEL9                          = 0x93,
2450         SQ_PERF_SEL_USER_LEVEL10                         = 0x94,
2451         SQ_PERF_SEL_USER_LEVEL11                         = 0x95,
2452         SQ_PERF_SEL_USER_LEVEL12                         = 0x96,
2453         SQ_PERF_SEL_USER_LEVEL13                         = 0x97,
2454         SQ_PERF_SEL_USER_LEVEL14                         = 0x98,
2455         SQ_PERF_SEL_USER_LEVEL15                         = 0x99,
2456         SQ_PERF_SEL_POWER_VALU                           = 0x9a,
2457         SQ_PERF_SEL_POWER_VALU0                          = 0x9b,
2458         SQ_PERF_SEL_POWER_VALU1                          = 0x9c,
2459         SQ_PERF_SEL_POWER_VALU2                          = 0x9d,
2460         SQ_PERF_SEL_POWER_GPR_RD                         = 0x9e,
2461         SQ_PERF_SEL_POWER_GPR_WR                         = 0x9f,
2462         SQ_PERF_SEL_POWER_LDS_BUSY                       = 0xa0,
2463         SQ_PERF_SEL_POWER_ALU_BUSY                       = 0xa1,
2464         SQ_PERF_SEL_POWER_TEX_BUSY                       = 0xa2,
2465         SQ_PERF_SEL_ACCUM_PREV_HIRES                     = 0xa3,
2466         SQ_PERF_SEL_WAVES_RESTORED                       = 0xa4,
2467         SQ_PERF_SEL_WAVES_SAVED                          = 0xa5,
2468         SQ_PERF_SEL_DUMMY_LAST                           = 0xa7,
2469         SQC_PERF_SEL_ICACHE_INPUT_VALID_READY            = 0xa8,
2470         SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB           = 0xa9,
2471         SQC_PERF_SEL_ICACHE_INPUT_VALIDB                 = 0xaa,
2472         SQC_PERF_SEL_DCACHE_INPUT_VALID_READY            = 0xab,
2473         SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB           = 0xac,
2474         SQC_PERF_SEL_DCACHE_INPUT_VALIDB                 = 0xad,
2475         SQC_PERF_SEL_TC_REQ                              = 0xae,
2476         SQC_PERF_SEL_TC_INST_REQ                         = 0xaf,
2477         SQC_PERF_SEL_TC_DATA_READ_REQ                    = 0xb0,
2478         SQC_PERF_SEL_TC_DATA_WRITE_REQ                   = 0xb1,
2479         SQC_PERF_SEL_TC_DATA_ATOMIC_REQ                  = 0xb2,
2480         SQC_PERF_SEL_TC_STALL                            = 0xb3,
2481         SQC_PERF_SEL_TC_STARVE                           = 0xb4,
2482         SQC_PERF_SEL_ICACHE_BUSY_CYCLES                  = 0xb5,
2483         SQC_PERF_SEL_ICACHE_REQ                          = 0xb6,
2484         SQC_PERF_SEL_ICACHE_HITS                         = 0xb7,
2485         SQC_PERF_SEL_ICACHE_MISSES                       = 0xb8,
2486         SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE             = 0xb9,
2487         SQC_PERF_SEL_ICACHE_INVAL_INST                   = 0xba,
2488         SQC_PERF_SEL_ICACHE_INVAL_ASYNC                  = 0xbb,
2489         SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT     = 0xbc,
2490         SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB      = 0xbd,
2491         SQC_PERF_SEL_ICACHE_CACHE_STALLED                = 0xbe,
2492         SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO = 0xbf,
2493         SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX     = 0xc0,
2494         SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT           = 0xc1,
2495         SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0xc2,
2496         SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO  = 0xc3,
2497         SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF     = 0xc4,
2498         SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT   = 0xc5,
2499         SQC_PERF_SEL_DCACHE_BUSY_CYCLES                  = 0xc6,
2500         SQC_PERF_SEL_DCACHE_REQ                          = 0xc7,
2501         SQC_PERF_SEL_DCACHE_HITS                         = 0xc8,
2502         SQC_PERF_SEL_DCACHE_MISSES                       = 0xc9,
2503         SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE             = 0xca,
2504         SQC_PERF_SEL_DCACHE_HIT_LRU_READ                 = 0xcb,
2505         SQC_PERF_SEL_DCACHE_MISS_EVICT_READ              = 0xcc,
2506         SQC_PERF_SEL_DCACHE_WC_LRU_WRITE                 = 0xcd,
2507         SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE               = 0xce,
2508         SQC_PERF_SEL_DCACHE_ATOMIC                       = 0xcf,
2509         SQC_PERF_SEL_DCACHE_VOLATILE                     = 0xd0,
2510         SQC_PERF_SEL_DCACHE_INVAL_INST                   = 0xd1,
2511         SQC_PERF_SEL_DCACHE_INVAL_ASYNC                  = 0xd2,
2512         SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST          = 0xd3,
2513         SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC         = 0xd4,
2514         SQC_PERF_SEL_DCACHE_WB_INST                      = 0xd5,
2515         SQC_PERF_SEL_DCACHE_WB_ASYNC                     = 0xd6,
2516         SQC_PERF_SEL_DCACHE_WB_VOLATILE_INST             = 0xd7,
2517         SQC_PERF_SEL_DCACHE_WB_VOLATILE_ASYNC            = 0xd8,
2518         SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT     = 0xd9,
2519         SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB      = 0xda,
2520         SQC_PERF_SEL_DCACHE_CACHE_STALLED                = 0xdb,
2521         SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX     = 0xdc,
2522         SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT           = 0xdd,
2523         SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT            = 0xde,
2524         SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED        = 0xdf,
2525         SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE= 0xe0,
2526         SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT      = 0xe1,
2527         SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH      = 0xe2,
2528         SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE       = 0xe3,
2529         SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0xe4,
2530         SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO  = 0xe5,
2531         SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF     = 0xe6,
2532         SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT   = 0xe7,
2533         SQC_PERF_SEL_DCACHE_REQ_READ_1                   = 0xe8,
2534         SQC_PERF_SEL_DCACHE_REQ_READ_2                   = 0xe9,
2535         SQC_PERF_SEL_DCACHE_REQ_READ_4                   = 0xea,
2536         SQC_PERF_SEL_DCACHE_REQ_READ_8                   = 0xeb,
2537         SQC_PERF_SEL_DCACHE_REQ_READ_16                  = 0xec,
2538         SQC_PERF_SEL_DCACHE_REQ_TIME                     = 0xed,
2539         SQC_PERF_SEL_DCACHE_REQ_WRITE_1                  = 0xee,
2540         SQC_PERF_SEL_DCACHE_REQ_WRITE_2                  = 0xef,
2541         SQC_PERF_SEL_DCACHE_REQ_WRITE_4                  = 0xf0,
2542         SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE                = 0xf1,
2543         SQC_PERF_SEL_SQ_DCACHE_REQS                      = 0xf2,
2544         SQC_PERF_SEL_DCACHE_FLAT_REQ                     = 0xf3,
2545         SQC_PERF_SEL_DCACHE_NONFLAT_REQ                  = 0xf4,
2546         SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL               = 0xf5,
2547         SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL               = 0xf6,
2548         SQC_PERF_SEL_TC_INFLIGHT_LEVEL                   = 0xf7,
2549         SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL            = 0xf8,
2550         SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL            = 0xf9,
2551         SQC_PERF_SEL_ICACHE_GATCL1_TRANSLATION_MISS      = 0xfa,
2552         SQC_PERF_SEL_ICACHE_GATCL1_PERMISSION_MISS       = 0xfb,
2553         SQC_PERF_SEL_ICACHE_GATCL1_REQUEST               = 0xfc,
2554         SQC_PERF_SEL_ICACHE_GATCL1_STALL_INFLIGHT_MAX    = 0xfd,
2555         SQC_PERF_SEL_ICACHE_GATCL1_STALL_LRU_INFLIGHT    = 0xfe,
2556         SQC_PERF_SEL_ICACHE_GATCL1_LFIFO_FULL            = 0xff,
2557         SQC_PERF_SEL_ICACHE_GATCL1_STALL_LFIFO_NOT_RES   = 0x100,
2558         SQC_PERF_SEL_ICACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS= 0x101,
2559         SQC_PERF_SEL_ICACHE_GATCL1_ATCL2_INFLIGHT        = 0x102,
2560         SQC_PERF_SEL_ICACHE_GATCL1_STALL_MISSFIFO_FULL   = 0x103,
2561         SQC_PERF_SEL_DCACHE_GATCL1_TRANSLATION_MISS      = 0x104,
2562         SQC_PERF_SEL_DCACHE_GATCL1_PERMISSION_MISS       = 0x105,
2563         SQC_PERF_SEL_DCACHE_GATCL1_REQUEST               = 0x106,
2564         SQC_PERF_SEL_DCACHE_GATCL1_STALL_INFLIGHT_MAX    = 0x107,
2565         SQC_PERF_SEL_DCACHE_GATCL1_STALL_LRU_INFLIGHT    = 0x108,
2566         SQC_PERF_SEL_DCACHE_GATCL1_LFIFO_FULL            = 0x109,
2567         SQC_PERF_SEL_DCACHE_GATCL1_STALL_LFIFO_NOT_RES   = 0x10a,
2568         SQC_PERF_SEL_DCACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS= 0x10b,
2569         SQC_PERF_SEL_DCACHE_GATCL1_ATCL2_INFLIGHT        = 0x10c,
2570         SQC_PERF_SEL_DCACHE_GATCL1_STALL_MISSFIFO_FULL   = 0x10d,
2571         SQC_PERF_SEL_DCACHE_GATCL1_STALL_MULTI_MISS      = 0x10e,
2572         SQC_PERF_SEL_DCACHE_GATCL1_HIT_FIFO_FULL         = 0x10f,
2573         SQC_PERF_SEL_DUMMY_LAST                          = 0x110,
2574         SQ_PERF_SEL_INSTS_SMEM_NORM                      = 0x111,
2575         SQ_PERF_SEL_ATC_INSTS_VMEM                       = 0x112,
2576         SQ_PERF_SEL_ATC_INST_LEVEL_VMEM                  = 0x113,
2577         SQ_PERF_SEL_ATC_XNACK_FIRST                      = 0x114,
2578         SQ_PERF_SEL_ATC_XNACK_ALL                        = 0x115,
2579         SQ_PERF_SEL_ATC_XNACK_FIFO_FULL                  = 0x116,
2580         SQ_PERF_SEL_ATC_INSTS_SMEM                       = 0x117,
2581         SQ_PERF_SEL_ATC_INST_LEVEL_SMEM                  = 0x118,
2582         SQ_PERF_SEL_IFETCH_XNACK                         = 0x119,
2583         SQ_PERF_SEL_TLB_SHOOTDOWN                        = 0x11a,
2584         SQ_PERF_SEL_TLB_SHOOTDOWN_CYCLES                 = 0x11b,
2585         SQ_PERF_SEL_INSTS_VMEM_WR_REPLAY                 = 0x11c,
2586         SQ_PERF_SEL_INSTS_VMEM_RD_REPLAY                 = 0x11d,
2587         SQ_PERF_SEL_INSTS_VMEM_REPLAY                    = 0x11e,
2588         SQ_PERF_SEL_INSTS_SMEM_REPLAY                    = 0x11f,
2589         SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY               = 0x120,
2590         SQ_PERF_SEL_INSTS_FLAT_REPLAY                    = 0x121,
2591         SQ_PERF_SEL_ATC_INSTS_VMEM_REPLAY                = 0x122,
2592         SQ_PERF_SEL_ATC_INSTS_SMEM_REPLAY                = 0x123,
2593         SQ_PERF_SEL_DUMMY_LAST1                          = 0x12a,
2594 } SQ_PERF_SEL;
2595 typedef enum SQ_CAC_POWER_SEL {
2596         SQ_CAC_POWER_VALU                                = 0x0,
2597         SQ_CAC_POWER_VALU0                               = 0x1,
2598         SQ_CAC_POWER_VALU1                               = 0x2,
2599         SQ_CAC_POWER_VALU2                               = 0x3,
2600         SQ_CAC_POWER_GPR_RD                              = 0x4,
2601         SQ_CAC_POWER_GPR_WR                              = 0x5,
2602         SQ_CAC_POWER_LDS_BUSY                            = 0x6,
2603         SQ_CAC_POWER_ALU_BUSY                            = 0x7,
2604         SQ_CAC_POWER_TEX_BUSY                            = 0x8,
2605 } SQ_CAC_POWER_SEL;
2606 typedef enum SQ_IND_CMD_CMD {
2607         SQ_IND_CMD_CMD_NULL                              = 0x0,
2608         SQ_IND_CMD_CMD_SETHALT                           = 0x1,
2609         SQ_IND_CMD_CMD_SAVECTX                           = 0x2,
2610         SQ_IND_CMD_CMD_KILL                              = 0x3,
2611         SQ_IND_CMD_CMD_DEBUG                             = 0x4,
2612         SQ_IND_CMD_CMD_TRAP                              = 0x5,
2613         SQ_IND_CMD_CMD_SET_SPI_PRIO                      = 0x6,
2614 } SQ_IND_CMD_CMD;
2615 typedef enum SQ_IND_CMD_MODE {
2616         SQ_IND_CMD_MODE_SINGLE                           = 0x0,
2617         SQ_IND_CMD_MODE_BROADCAST                        = 0x1,
2618         SQ_IND_CMD_MODE_BROADCAST_QUEUE                  = 0x2,
2619         SQ_IND_CMD_MODE_BROADCAST_PIPE                   = 0x3,
2620         SQ_IND_CMD_MODE_BROADCAST_ME                     = 0x4,
2621 } SQ_IND_CMD_MODE;
2622 typedef enum SQ_EDC_INFO_SOURCE {
2623         SQ_EDC_INFO_SOURCE_INVALID                       = 0x0,
2624         SQ_EDC_INFO_SOURCE_INST                          = 0x1,
2625         SQ_EDC_INFO_SOURCE_SGPR                          = 0x2,
2626         SQ_EDC_INFO_SOURCE_VGPR                          = 0x3,
2627         SQ_EDC_INFO_SOURCE_LDS                           = 0x4,
2628         SQ_EDC_INFO_SOURCE_GDS                           = 0x5,
2629         SQ_EDC_INFO_SOURCE_TA                            = 0x6,
2630 } SQ_EDC_INFO_SOURCE;
2631 typedef enum SQ_ROUND_MODE {
2632         SQ_ROUND_NEAREST_EVEN                            = 0x0,
2633         SQ_ROUND_PLUS_INFINITY                           = 0x1,
2634         SQ_ROUND_MINUS_INFINITY                          = 0x2,
2635         SQ_ROUND_TO_ZERO                                 = 0x3,
2636 } SQ_ROUND_MODE;
2637 typedef enum SQ_INTERRUPT_WORD_ENCODING {
2638         SQ_INTERRUPT_WORD_ENCODING_AUTO                  = 0x0,
2639         SQ_INTERRUPT_WORD_ENCODING_INST                  = 0x1,
2640         SQ_INTERRUPT_WORD_ENCODING_ERROR                 = 0x2,
2641 } SQ_INTERRUPT_WORD_ENCODING;
2642 typedef enum ENUM_SQ_EXPORT_RAT_INST {
2643         SQ_EXPORT_RAT_INST_NOP                           = 0x0,
2644         SQ_EXPORT_RAT_INST_STORE_TYPED                   = 0x1,
2645         SQ_EXPORT_RAT_INST_STORE_RAW                     = 0x2,
2646         SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM             = 0x3,
2647         SQ_EXPORT_RAT_INST_CMPXCHG_INT                   = 0x4,
2648         SQ_EXPORT_RAT_INST_CMPXCHG_FLT                   = 0x5,
2649         SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM               = 0x6,
2650         SQ_EXPORT_RAT_INST_ADD                           = 0x7,
2651         SQ_EXPORT_RAT_INST_SUB                           = 0x8,
2652         SQ_EXPORT_RAT_INST_RSUB                          = 0x9,
2653         SQ_EXPORT_RAT_INST_MIN_INT                       = 0xa,
2654         SQ_EXPORT_RAT_INST_MIN_UINT                      = 0xb,
2655         SQ_EXPORT_RAT_INST_MAX_INT                       = 0xc,
2656         SQ_EXPORT_RAT_INST_MAX_UINT                      = 0xd,
2657         SQ_EXPORT_RAT_INST_AND                           = 0xe,
2658         SQ_EXPORT_RAT_INST_OR                            = 0xf,
2659         SQ_EXPORT_RAT_INST_XOR                           = 0x10,
2660         SQ_EXPORT_RAT_INST_MSKOR                         = 0x11,
2661         SQ_EXPORT_RAT_INST_INC_UINT                      = 0x12,
2662         SQ_EXPORT_RAT_INST_DEC_UINT                      = 0x13,
2663         SQ_EXPORT_RAT_INST_STORE_DWORD                   = 0x14,
2664         SQ_EXPORT_RAT_INST_STORE_SHORT                   = 0x15,
2665         SQ_EXPORT_RAT_INST_STORE_BYTE                    = 0x16,
2666         SQ_EXPORT_RAT_INST_NOP_RTN                       = 0x20,
2667         SQ_EXPORT_RAT_INST_XCHG_RTN                      = 0x22,
2668         SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN              = 0x23,
2669         SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN               = 0x24,
2670         SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN               = 0x25,
2671         SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN           = 0x26,
2672         SQ_EXPORT_RAT_INST_ADD_RTN                       = 0x27,
2673         SQ_EXPORT_RAT_INST_SUB_RTN                       = 0x28,
2674         SQ_EXPORT_RAT_INST_RSUB_RTN                      = 0x29,
2675         SQ_EXPORT_RAT_INST_MIN_INT_RTN                   = 0x2a,
2676         SQ_EXPORT_RAT_INST_MIN_UINT_RTN                  = 0x2b,
2677         SQ_EXPORT_RAT_INST_MAX_INT_RTN                   = 0x2c,
2678         SQ_EXPORT_RAT_INST_MAX_UINT_RTN                  = 0x2d,
2679         SQ_EXPORT_RAT_INST_AND_RTN                       = 0x2e,
2680         SQ_EXPORT_RAT_INST_OR_RTN                        = 0x2f,
2681         SQ_EXPORT_RAT_INST_XOR_RTN                       = 0x30,
2682         SQ_EXPORT_RAT_INST_MSKOR_RTN                     = 0x31,
2683         SQ_EXPORT_RAT_INST_INC_UINT_RTN                  = 0x32,
2684         SQ_EXPORT_RAT_INST_DEC_UINT_RTN                  = 0x33,
2685 } ENUM_SQ_EXPORT_RAT_INST;
2686 typedef enum SQ_IBUF_ST {
2687         SQ_IBUF_IB_IDLE                                  = 0x0,
2688         SQ_IBUF_IB_INI_WAIT_GNT                          = 0x1,
2689         SQ_IBUF_IB_INI_WAIT_DRET                         = 0x2,
2690         SQ_IBUF_IB_LE_4DW                                = 0x3,
2691         SQ_IBUF_IB_WAIT_DRET                             = 0x4,
2692         SQ_IBUF_IB_EMPTY_WAIT_DRET                       = 0x5,
2693         SQ_IBUF_IB_DRET                                  = 0x6,
2694         SQ_IBUF_IB_EMPTY_WAIT_GNT                        = 0x7,
2695 } SQ_IBUF_ST;
2696 typedef enum SQ_INST_STR_ST {
2697         SQ_INST_STR_IB_WAVE_NORML                        = 0x0,
2698         SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV            = 0x1,
2699         SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV             = 0x2,
2700         SQ_INST_STR_IB_WAVE_INST_SKIP_AV                 = 0x3,
2701         SQ_INST_STR_IB_WAVE_SETVSKIP_ST0                 = 0x4,
2702         SQ_INST_STR_IB_WAVE_SETVSKIP_ST1                 = 0x5,
2703         SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT               = 0x6,
2704         SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT        = 0x7,
2705 } SQ_INST_STR_ST;
2706 typedef enum SQ_WAVE_IB_ECC_ST {
2707         SQ_WAVE_IB_ECC_CLEAN                             = 0x0,
2708         SQ_WAVE_IB_ECC_ERR_CONTINUE                      = 0x1,
2709         SQ_WAVE_IB_ECC_ERR_HALT                          = 0x2,
2710         SQ_WAVE_IB_ECC_WITH_ERR_MSG                      = 0x3,
2711 } SQ_WAVE_IB_ECC_ST;
2712 typedef enum SH_MEM_ADDRESS_MODE {
2713         SH_MEM_ADDRESS_MODE_GPUVM64                      = 0x0,
2714         SH_MEM_ADDRESS_MODE_GPUVM32                      = 0x1,
2715         SH_MEM_ADDRESS_MODE_HSA64                        = 0x2,
2716         SH_MEM_ADDRESS_MODE_HSA32                        = 0x3,
2717 } SH_MEM_ADDRESS_MODE;
2718 typedef enum SH_MEM_ALIGNMENT_MODE {
2719         SH_MEM_ALIGNMENT_MODE_DWORD                      = 0x0,
2720         SH_MEM_ALIGNMENT_MODE_DWORD_STRICT               = 0x1,
2721         SH_MEM_ALIGNMENT_MODE_STRICT                     = 0x2,
2722         SH_MEM_ALIGNMENT_MODE_UNALIGNED                  = 0x3,
2723 } SH_MEM_ALIGNMENT_MODE;
2724 typedef enum SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX {
2725         SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_WREXEC   = 0x18,
2726         SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_RESTORE  = 0x19,
2727 } SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX;
2728 #define SQ_WAVE_TYPE_PS0                          0x0
2729 #define SQIND_GLOBAL_REGS_OFFSET                  0x0
2730 #define SQIND_GLOBAL_REGS_SIZE                    0x8
2731 #define SQIND_LOCAL_REGS_OFFSET                   0x8
2732 #define SQIND_LOCAL_REGS_SIZE                     0x8
2733 #define SQIND_WAVE_HWREGS_OFFSET                  0x10
2734 #define SQIND_WAVE_HWREGS_SIZE                    0x1f0
2735 #define SQIND_WAVE_SGPRS_OFFSET                   0x200
2736 #define SQIND_WAVE_SGPRS_SIZE                     0x200
2737 #define SQ_GFXDEC_BEGIN                           0xa000
2738 #define SQ_GFXDEC_END                             0xc000
2739 #define SQ_GFXDEC_STATE_ID_SHIFT                  0xa
2740 #define SQDEC_BEGIN                               0x2300
2741 #define SQDEC_END                                 0x23ff
2742 #define SQPERFSDEC_BEGIN                          0xd9c0
2743 #define SQPERFSDEC_END                            0xda40
2744 #define SQPERFDDEC_BEGIN                          0xd1c0
2745 #define SQPERFDDEC_END                            0xd240
2746 #define SQGFXUDEC_BEGIN                           0xc330
2747 #define SQGFXUDEC_END                             0xc380
2748 #define SQPWRDEC_BEGIN                            0xf08c
2749 #define SQPWRDEC_END                              0xf094
2750 #define SQ_DISPATCHER_GFX_MIN                     0x10
2751 #define SQ_DISPATCHER_GFX_CNT_PER_RING            0x8
2752 #define SQ_MAX_PGM_SGPRS                          0x68
2753 #define SQ_MAX_PGM_VGPRS                          0x100
2754 #define SQ_THREAD_TRACE_TIME_UNIT                 0x4
2755 #define SQ_EX_MODE_EXCP_VALU_BASE                 0x0
2756 #define SQ_EX_MODE_EXCP_VALU_SIZE                 0x7
2757 #define SQ_EX_MODE_EXCP_INVALID                   0x0
2758 #define SQ_EX_MODE_EXCP_INPUT_DENORM              0x1
2759 #define SQ_EX_MODE_EXCP_DIV0                      0x2
2760 #define SQ_EX_MODE_EXCP_OVERFLOW                  0x3
2761 #define SQ_EX_MODE_EXCP_UNDERFLOW                 0x4
2762 #define SQ_EX_MODE_EXCP_INEXACT                   0x5
2763 #define SQ_EX_MODE_EXCP_INT_DIV0                  0x6
2764 #define SQ_EX_MODE_EXCP_ADDR_WATCH                0x7
2765 #define SQ_EX_MODE_EXCP_MEM_VIOL                  0x8
2766 #define INST_ID_PRIV_START                        0x80000000
2767 #define INST_ID_ECC_INTERRUPT_MSG                 0xfffffff0
2768 #define INST_ID_TTRACE_NEW_PC_MSG                 0xfffffff1
2769 #define INST_ID_HW_TRAP                           0xfffffff2
2770 #define INST_ID_KILL_SEQ                          0xfffffff3
2771 #define INST_ID_SPI_WREXEC                        0xfffffff4
2772 #define INST_ID_HOST_REG_TRAP_MSG                 0xfffffffe
2773 #define SQ_ENC_SOP1_BITS                          0xbe800000
2774 #define SQ_ENC_SOP1_MASK                          0xff800000
2775 #define SQ_ENC_SOP1_FIELD                         0x17d
2776 #define SQ_ENC_SOPC_BITS                          0xbf000000
2777 #define SQ_ENC_SOPC_MASK                          0xff800000
2778 #define SQ_ENC_SOPC_FIELD                         0x17e
2779 #define SQ_ENC_SOPP_BITS                          0xbf800000
2780 #define SQ_ENC_SOPP_MASK                          0xff800000
2781 #define SQ_ENC_SOPP_FIELD                         0x17f
2782 #define SQ_ENC_SOPK_BITS                          0xb0000000
2783 #define SQ_ENC_SOPK_MASK                          0xf0000000
2784 #define SQ_ENC_SOPK_FIELD                         0xb
2785 #define SQ_ENC_SOP2_BITS                          0x80000000
2786 #define SQ_ENC_SOP2_MASK                          0xc0000000
2787 #define SQ_ENC_SOP2_FIELD                         0x2
2788 #define SQ_ENC_SMEM_BITS                          0xc0000000
2789 #define SQ_ENC_SMEM_MASK                          0xfc000000
2790 #define SQ_ENC_SMEM_FIELD                         0x30
2791 #define SQ_ENC_VOP1_BITS                          0x7e000000
2792 #define SQ_ENC_VOP1_MASK                          0xfe000000
2793 #define SQ_ENC_VOP1_FIELD                         0x3f
2794 #define SQ_ENC_VOPC_BITS                          0x7c000000
2795 #define SQ_ENC_VOPC_MASK                          0xfe000000
2796 #define SQ_ENC_VOPC_FIELD                         0x3e
2797 #define SQ_ENC_VOP2_BITS                          0x0
2798 #define SQ_ENC_VOP2_MASK                          0x80000000
2799 #define SQ_ENC_VOP2_FIELD                         0x0
2800 #define SQ_ENC_VINTRP_BITS                        0xd4000000
2801 #define SQ_ENC_VINTRP_MASK                        0xfc000000
2802 #define SQ_ENC_VINTRP_FIELD                       0x35
2803 #define SQ_ENC_VOP3_BITS                          0xd0000000
2804 #define SQ_ENC_VOP3_MASK                          0xfc000000
2805 #define SQ_ENC_VOP3_FIELD                         0x34
2806 #define SQ_ENC_DS_BITS                            0xd8000000
2807 #define SQ_ENC_DS_MASK                            0xfc000000
2808 #define SQ_ENC_DS_FIELD                           0x36
2809 #define SQ_ENC_MUBUF_BITS                         0xe0000000
2810 #define SQ_ENC_MUBUF_MASK                         0xfc000000
2811 #define SQ_ENC_MUBUF_FIELD                        0x38
2812 #define SQ_ENC_MTBUF_BITS                         0xe8000000
2813 #define SQ_ENC_MTBUF_MASK                         0xfc000000
2814 #define SQ_ENC_MTBUF_FIELD                        0x3a
2815 #define SQ_ENC_MIMG_BITS                          0xf0000000
2816 #define SQ_ENC_MIMG_MASK                          0xfc000000
2817 #define SQ_ENC_MIMG_FIELD                         0x3c
2818 #define SQ_ENC_EXP_BITS                           0xc4000000
2819 #define SQ_ENC_EXP_MASK                           0xfc000000
2820 #define SQ_ENC_EXP_FIELD                          0x31
2821 #define SQ_ENC_FLAT_BITS                          0xdc000000
2822 #define SQ_ENC_FLAT_MASK                          0xfc000000
2823 #define SQ_ENC_FLAT_FIELD                         0x37
2824 #define SQ_V_OP3_INTRP_OFFSET                     0x274
2825 #define SQ_WAITCNT_VM_SHIFT                       0x0
2826 #define SQ_SENDMSG_STREAMID_SIZE                  0x2
2827 #define SQ_V_OPC_COUNT                            0x100
2828 #define SQ_V_OP3_INTRP_COUNT                      0xc
2829 #define SQ_XLATE_VOP3_TO_VOP2_OFFSET              0x100
2830 #define SQ_HWREG_OFFSET_SIZE                      0x5
2831 #define SQ_HWREG_OFFSET_SHIFT                     0x6
2832 #define SQ_V_OP3_3IN_OFFSET                       0x1c0
2833 #define SQ_NUM_ATTR                               0x21
2834 #define SQ_NUM_VGPR                               0x100
2835 #define SQ_XLATE_VOP3_TO_VINTRP_COUNT             0x4
2836 #define SQ_SENDMSG_MSG_SIZE                       0x4
2837 #define SQ_NUM_TTMP                               0xc
2838 #define SQ_HWREG_ID_SIZE                          0x6
2839 #define SQ_SENDMSG_GSOP_SIZE                      0x2
2840 #define SQ_NUM_SGPR                               0x66
2841 #define SQ_EXP_NUM_MRT                            0x8
2842 #define SQ_SENDMSG_SYSTEM_SIZE                    0x3
2843 #define SQ_WAITCNT_LGKM_SHIFT                     0x8
2844 #define SQ_XLATE_VOP3_TO_VOP2_COUNT               0x40
2845 #define SQ_V_OP3_3IN_COUNT                        0xb0
2846 #define SQ_V_INTRP_COUNT                          0x4
2847 #define SQ_WAITCNT_EXP_SIZE                       0x3
2848 #define SQ_SENDMSG_SYSTEM_SHIFT                   0x4
2849 #define SQ_EXP_NUM_GDS                            0x5
2850 #define SQ_HWREG_SIZE_SHIFT                       0xb
2851 #define SQ_XLATE_VOP3_TO_VOPC_OFFSET              0x0
2852 #define SQ_V_OP3_2IN_COUNT                        0x80
2853 #define SQ_XLATE_VOP3_TO_VINTRP_OFFSET            0x270
2854 #define SQ_SENDMSG_MSG_SHIFT                      0x0
2855 #define SQ_WAITCNT_EXP_SHIFT                      0x4
2856 #define SQ_WAITCNT_VM_SIZE                        0x4
2857 #define SQ_XLATE_VOP3_TO_VOP1_OFFSET              0x140
2858 #define SQ_SENDMSG_GSOP_SHIFT                     0x4
2859 #define SQ_XLATE_VOP3_TO_VOP1_COUNT               0x80
2860 #define SQ_SRC_VGPR_BIT                           0x100
2861 #define SQ_V_OP2_COUNT                            0x40
2862 #define SQ_EXP_NUM_PARAM                          0x20
2863 #define SQ_V_OP1_COUNT                            0x80
2864 #define SQ_SENDMSG_STREAMID_SHIFT                 0x8
2865 #define SQ_V_OP3_2IN_OFFSET                       0x280
2866 #define SQ_WAITCNT_LGKM_SIZE                      0x4
2867 #define SQ_XLATE_VOP3_TO_VOPC_COUNT               0x100
2868 #define SQ_EXP_NUM_POS                            0x4
2869 #define SQ_HWREG_SIZE_SIZE                        0x5
2870 #define SQ_HWREG_ID_SHIFT                         0x0
2871 #define SQ_S_MOV_B32                              0x0
2872 #define SQ_S_MOV_B64                              0x1
2873 #define SQ_S_CMOV_B32                             0x2
2874 #define SQ_S_CMOV_B64                             0x3
2875 #define SQ_S_NOT_B32                              0x4
2876 #define SQ_S_NOT_B64                              0x5
2877 #define SQ_S_WQM_B32                              0x6
2878 #define SQ_S_WQM_B64                              0x7
2879 #define SQ_S_BREV_B32                             0x8
2880 #define SQ_S_BREV_B64                             0x9
2881 #define SQ_S_BCNT0_I32_B32                        0xa
2882 #define SQ_S_BCNT0_I32_B64                        0xb
2883 #define SQ_S_BCNT1_I32_B32                        0xc
2884 #define SQ_S_BCNT1_I32_B64                        0xd
2885 #define SQ_S_FF0_I32_B32                          0xe
2886 #define SQ_S_FF0_I32_B64                          0xf
2887 #define SQ_S_FF1_I32_B32                          0x10
2888 #define SQ_S_FF1_I32_B64                          0x11
2889 #define SQ_S_FLBIT_I32_B32                        0x12
2890 #define SQ_S_FLBIT_I32_B64                        0x13
2891 #define SQ_S_FLBIT_I32                            0x14
2892 #define SQ_S_FLBIT_I32_I64                        0x15
2893 #define SQ_S_SEXT_I32_I8                          0x16
2894 #define SQ_S_SEXT_I32_I16                         0x17
2895 #define SQ_S_BITSET0_B32                          0x18
2896 #define SQ_S_BITSET0_B64                          0x19
2897 #define SQ_S_BITSET1_B32                          0x1a
2898 #define SQ_S_BITSET1_B64                          0x1b
2899 #define SQ_S_GETPC_B64                            0x1c
2900 #define SQ_S_SETPC_B64                            0x1d
2901 #define SQ_S_SWAPPC_B64                           0x1e
2902 #define SQ_S_RFE_B64                              0x1f
2903 #define SQ_S_AND_SAVEEXEC_B64                     0x20
2904 #define SQ_S_OR_SAVEEXEC_B64                      0x21
2905 #define SQ_S_XOR_SAVEEXEC_B64                     0x22
2906 #define SQ_S_ANDN2_SAVEEXEC_B64                   0x23
2907 #define SQ_S_ORN2_SAVEEXEC_B64                    0x24
2908 #define SQ_S_NAND_SAVEEXEC_B64                    0x25
2909 #define SQ_S_NOR_SAVEEXEC_B64                     0x26
2910 #define SQ_S_XNOR_SAVEEXEC_B64                    0x27
2911 #define SQ_S_QUADMASK_B32                         0x28
2912 #define SQ_S_QUADMASK_B64                         0x29
2913 #define SQ_S_MOVRELS_B32                          0x2a
2914 #define SQ_S_MOVRELS_B64                          0x2b
2915 #define SQ_S_MOVRELD_B32                          0x2c
2916 #define SQ_S_MOVRELD_B64                          0x2d
2917 #define SQ_S_CBRANCH_JOIN                         0x2e
2918 #define SQ_S_MOV_REGRD_B32                        0x2f
2919 #define SQ_S_ABS_I32                              0x30
2920 #define SQ_S_MOV_FED_B32                          0x31
2921 #define SQ_S_SET_GPR_IDX_IDX                      0x32
2922 #define SQ_ATTR0                                  0x0
2923 #define SQ_S_MOVK_I32                             0x0
2924 #define SQ_S_CMOVK_I32                            0x1
2925 #define SQ_S_CMPK_EQ_I32                          0x2
2926 #define SQ_S_CMPK_LG_I32                          0x3
2927 #define SQ_S_CMPK_GT_I32                          0x4
2928 #define SQ_S_CMPK_GE_I32                          0x5
2929 #define SQ_S_CMPK_LT_I32                          0x6
2930 #define SQ_S_CMPK_LE_I32                          0x7
2931 #define SQ_S_CMPK_EQ_U32                          0x8
2932 #define SQ_S_CMPK_LG_U32                          0x9
2933 #define SQ_S_CMPK_GT_U32                          0xa
2934 #define SQ_S_CMPK_GE_U32                          0xb
2935 #define SQ_S_CMPK_LT_U32                          0xc
2936 #define SQ_S_CMPK_LE_U32                          0xd
2937 #define SQ_S_ADDK_I32                             0xe
2938 #define SQ_S_MULK_I32                             0xf
2939 #define SQ_S_CBRANCH_I_FORK                       0x10
2940 #define SQ_S_GETREG_B32                           0x11
2941 #define SQ_S_SETREG_B32                           0x12
2942 #define SQ_S_GETREG_REGRD_B32                     0x13
2943 #define SQ_S_SETREG_IMM32_B32                     0x14
2944 #define SQ_TBA_LO                                 0x6c
2945 #define SQ_TBA_HI                                 0x6d
2946 #define SQ_TMA_LO                                 0x6e
2947 #define SQ_TMA_HI                                 0x6f
2948 #define SQ_TTMP0                                  0x70
2949 #define SQ_TTMP1                                  0x71
2950 #define SQ_TTMP2                                  0x72
2951 #define SQ_TTMP3                                  0x73
2952 #define SQ_TTMP4                                  0x74
2953 #define SQ_TTMP5                                  0x75
2954 #define SQ_TTMP6                                  0x76
2955 #define SQ_TTMP7                                  0x77
2956 #define SQ_TTMP8                                  0x78
2957 #define SQ_TTMP9                                  0x79
2958 #define SQ_TTMP10                                 0x7a
2959 #define SQ_TTMP11                                 0x7b
2960 #define SQ_VGPR0                                  0x0
2961 #define SQ_EXP                                    0x0
2962 #define SQ_EXP_MRT0                               0x0
2963 #define SQ_EXP_MRTZ                               0x8
2964 #define SQ_EXP_NULL                               0x9
2965 #define SQ_EXP_POS0                               0xc
2966 #define SQ_EXP_PARAM0                             0x20
2967 #define SQ_CNT1                                   0x0
2968 #define SQ_CNT2                                   0x1
2969 #define SQ_CNT3                                   0x2
2970 #define SQ_CNT4                                   0x3
2971 #define SQ_S_LOAD_DWORD                           0x0
2972 #define SQ_S_LOAD_DWORDX2                         0x1
2973 #define SQ_S_LOAD_DWORDX4                         0x2
2974 #define SQ_S_LOAD_DWORDX8                         0x3
2975 #define SQ_S_LOAD_DWORDX16                        0x4
2976 #define SQ_S_BUFFER_LOAD_DWORD                    0x8
2977 #define SQ_S_BUFFER_LOAD_DWORDX2                  0x9
2978 #define SQ_S_BUFFER_LOAD_DWORDX4                  0xa
2979 #define SQ_S_BUFFER_LOAD_DWORDX8                  0xb
2980 #define SQ_S_BUFFER_LOAD_DWORDX16                 0xc
2981 #define SQ_S_STORE_DWORD                          0x10
2982 #define SQ_S_STORE_DWORDX2                        0x11
2983 #define SQ_S_STORE_DWORDX4                        0x12
2984 #define SQ_S_BUFFER_STORE_DWORD                   0x18
2985 #define SQ_S_BUFFER_STORE_DWORDX2                 0x19
2986 #define SQ_S_BUFFER_STORE_DWORDX4                 0x1a
2987 #define SQ_S_DCACHE_INV                           0x20
2988 #define SQ_S_DCACHE_WB                            0x21
2989 #define SQ_S_DCACHE_INV_VOL                       0x22
2990 #define SQ_S_DCACHE_WB_VOL                        0x23
2991 #define SQ_S_MEMTIME                              0x24
2992 #define SQ_S_MEMREALTIME                          0x25
2993 #define SQ_S_ATC_PROBE                            0x26
2994 #define SQ_S_ATC_PROBE_BUFFER                     0x27
2995 #define SQ_S_BUFFER_ATOMIC_SWAP                   0x40
2996 #define SQ_S_BUFFER_ATOMIC_CMPSWAP                0x41
2997 #define SQ_S_BUFFER_ATOMIC_ADD                    0x42
2998 #define SQ_S_BUFFER_ATOMIC_SUB                    0x43
2999 #define SQ_S_BUFFER_ATOMIC_SMIN                   0x44
3000 #define SQ_S_BUFFER_ATOMIC_UMIN                   0x45
3001 #define SQ_S_BUFFER_ATOMIC_SMAX                   0x46
3002 #define SQ_S_BUFFER_ATOMIC_UMAX                   0x47
3003 #define SQ_S_BUFFER_ATOMIC_AND                    0x48
3004 #define SQ_S_BUFFER_ATOMIC_OR                     0x49
3005 #define SQ_S_BUFFER_ATOMIC_XOR                    0x4a
3006 #define SQ_S_BUFFER_ATOMIC_INC                    0x4b
3007 #define SQ_S_BUFFER_ATOMIC_DEC                    0x4c
3008 #define SQ_S_BUFFER_ATOMIC_SWAP_X2                0x60
3009 #define SQ_S_BUFFER_ATOMIC_CMPSWAP_X2             0x61
3010 #define SQ_S_BUFFER_ATOMIC_ADD_X2                 0x62
3011 #define SQ_S_BUFFER_ATOMIC_SUB_X2                 0x63
3012 #define SQ_S_BUFFER_ATOMIC_SMIN_X2                0x64
3013 #define SQ_S_BUFFER_ATOMIC_UMIN_X2                0x65
3014 #define SQ_S_BUFFER_ATOMIC_SMAX_X2                0x66
3015 #define SQ_S_BUFFER_ATOMIC_UMAX_X2                0x67
3016 #define SQ_S_BUFFER_ATOMIC_AND_X2                 0x68
3017 #define SQ_S_BUFFER_ATOMIC_OR_X2                  0x69
3018 #define SQ_S_BUFFER_ATOMIC_XOR_X2                 0x6a
3019 #define SQ_S_BUFFER_ATOMIC_INC_X2                 0x6b
3020 #define SQ_S_BUFFER_ATOMIC_DEC_X2                 0x6c
3021 #define SQ_F                                      0x0
3022 #define SQ_LT                                     0x1
3023 #define SQ_EQ                                     0x2
3024 #define SQ_LE                                     0x3
3025 #define SQ_GT                                     0x4
3026 #define SQ_LG                                     0x5
3027 #define SQ_GE                                     0x6
3028 #define SQ_O                                      0x7
3029 #define SQ_U                                      0x8
3030 #define SQ_NGE                                    0x9
3031 #define SQ_NLG                                    0xa
3032 #define SQ_NGT                                    0xb
3033 #define SQ_NLE                                    0xc
3034 #define SQ_NEQ                                    0xd
3035 #define SQ_NLT                                    0xe
3036 #define SQ_TRU                                    0xf
3037 #define SQ_V_CMP_CLASS_F32                        0x10
3038 #define SQ_V_CMPX_CLASS_F32                       0x11
3039 #define SQ_V_CMP_CLASS_F64                        0x12
3040 #define SQ_V_CMPX_CLASS_F64                       0x13
3041 #define SQ_V_CMP_CLASS_F16                        0x14
3042 #define SQ_V_CMPX_CLASS_F16                       0x15
3043 #define SQ_V_CMP_F_F16                            0x20
3044 #define SQ_V_CMP_LT_F16                           0x21
3045 #define SQ_V_CMP_EQ_F16                           0x22
3046 #define SQ_V_CMP_LE_F16                           0x23
3047 #define SQ_V_CMP_GT_F16                           0x24
3048 #define SQ_V_CMP_LG_F16                           0x25
3049 #define SQ_V_CMP_GE_F16                           0x26
3050 #define SQ_V_CMP_O_F16                            0x27
3051 #define SQ_V_CMP_U_F16                            0x28
3052 #define SQ_V_CMP_NGE_F16                          0x29
3053 #define SQ_V_CMP_NLG_F16                          0x2a
3054 #define SQ_V_CMP_NGT_F16                          0x2b
3055 #define SQ_V_CMP_NLE_F16                          0x2c
3056 #define SQ_V_CMP_NEQ_F16                          0x2d
3057 #define SQ_V_CMP_NLT_F16                          0x2e
3058 #define SQ_V_CMP_TRU_F16                          0x2f
3059 #define SQ_V_CMPX_F_F16                           0x30
3060 #define SQ_V_CMPX_LT_F16                          0x31
3061 #define SQ_V_CMPX_EQ_F16                          0x32
3062 #define SQ_V_CMPX_LE_F16                          0x33
3063 #define SQ_V_CMPX_GT_F16                          0x34
3064 #define SQ_V_CMPX_LG_F16                          0x35
3065 #define SQ_V_CMPX_GE_F16                          0x36
3066 #define SQ_V_CMPX_O_F16                           0x37
3067 #define SQ_V_CMPX_U_F16                           0x38
3068 #define SQ_V_CMPX_NGE_F16                         0x39
3069 #define SQ_V_CMPX_NLG_F16                         0x3a
3070 #define SQ_V_CMPX_NGT_F16                         0x3b
3071 #define SQ_V_CMPX_NLE_F16                         0x3c
3072 #define SQ_V_CMPX_NEQ_F16                         0x3d
3073 #define SQ_V_CMPX_NLT_F16                         0x3e
3074 #define SQ_V_CMPX_TRU_F16                         0x3f
3075 #define SQ_V_CMP_F_F32                            0x40
3076 #define SQ_V_CMP_LT_F32                           0x41
3077 #define SQ_V_CMP_EQ_F32                           0x42
3078 #define SQ_V_CMP_LE_F32                           0x43
3079 #define SQ_V_CMP_GT_F32                           0x44
3080 #define SQ_V_CMP_LG_F32                           0x45
3081 #define SQ_V_CMP_GE_F32                           0x46
3082 #define SQ_V_CMP_O_F32                            0x47
3083 #define SQ_V_CMP_U_F32                            0x48
3084 #define SQ_V_CMP_NGE_F32                          0x49
3085 #define SQ_V_CMP_NLG_F32                          0x4a
3086 #define SQ_V_CMP_NGT_F32                          0x4b
3087 #define SQ_V_CMP_NLE_F32                          0x4c
3088 #define SQ_V_CMP_NEQ_F32                          0x4d
3089 #define SQ_V_CMP_NLT_F32                          0x4e
3090 #define SQ_V_CMP_TRU_F32                          0x4f
3091 #define SQ_V_CMPX_F_F32                           0x50
3092 #define SQ_V_CMPX_LT_F32                          0x51
3093 #define SQ_V_CMPX_EQ_F32                          0x52
3094 #define SQ_V_CMPX_LE_F32                          0x53
3095 #define SQ_V_CMPX_GT_F32                          0x54
3096 #define SQ_V_CMPX_LG_F32                          0x55
3097 #define SQ_V_CMPX_GE_F32                          0x56
3098 #define SQ_V_CMPX_O_F32                           0x57
3099 #define SQ_V_CMPX_U_F32                           0x58
3100 #define SQ_V_CMPX_NGE_F32                         0x59
3101 #define SQ_V_CMPX_NLG_F32                         0x5a
3102 #define SQ_V_CMPX_NGT_F32                         0x5b
3103 #define SQ_V_CMPX_NLE_F32                         0x5c
3104 #define SQ_V_CMPX_NEQ_F32                         0x5d
3105 #define SQ_V_CMPX_NLT_F32                         0x5e
3106 #define SQ_V_CMPX_TRU_F32                         0x5f
3107 #define SQ_V_CMP_F_F64                            0x60
3108 #define SQ_V_CMP_LT_F64                           0x61
3109 #define SQ_V_CMP_EQ_F64                           0x62
3110 #define SQ_V_CMP_LE_F64                           0x63
3111 #define SQ_V_CMP_GT_F64                           0x64
3112 #define SQ_V_CMP_LG_F64                           0x65
3113 #define SQ_V_CMP_GE_F64                           0x66
3114 #define SQ_V_CMP_O_F64                            0x67
3115 #define SQ_V_CMP_U_F64                            0x68
3116 #define SQ_V_CMP_NGE_F64                          0x69
3117 #define SQ_V_CMP_NLG_F64                          0x6a
3118 #define SQ_V_CMP_NGT_F64                          0x6b
3119 #define SQ_V_CMP_NLE_F64                          0x6c
3120 #define SQ_V_CMP_NEQ_F64                          0x6d
3121 #define SQ_V_CMP_NLT_F64                          0x6e
3122 #define SQ_V_CMP_TRU_F64                          0x6f
3123 #define SQ_V_CMPX_F_F64                           0x70
3124 #define SQ_V_CMPX_LT_F64                          0x71
3125 #define SQ_V_CMPX_EQ_F64                          0x72
3126 #define SQ_V_CMPX_LE_F64                          0x73
3127 #define SQ_V_CMPX_GT_F64                          0x74
3128 #define SQ_V_CMPX_LG_F64                          0x75
3129 #define SQ_V_CMPX_GE_F64                          0x76
3130 #define SQ_V_CMPX_O_F64                           0x77
3131 #define SQ_V_CMPX_U_F64                           0x78
3132 #define SQ_V_CMPX_NGE_F64                         0x79
3133 #define SQ_V_CMPX_NLG_F64                         0x7a
3134 #define SQ_V_CMPX_NGT_F64                         0x7b
3135 #define SQ_V_CMPX_NLE_F64                         0x7c
3136 #define SQ_V_CMPX_NEQ_F64                         0x7d
3137 #define SQ_V_CMPX_NLT_F64                         0x7e
3138 #define SQ_V_CMPX_TRU_F64                         0x7f
3139 #define SQ_V_CMP_F_I16                            0xa0
3140 #define SQ_V_CMP_LT_I16                           0xa1
3141 #define SQ_V_CMP_EQ_I16                           0xa2
3142 #define SQ_V_CMP_LE_I16                           0xa3
3143 #define SQ_V_CMP_GT_I16                           0xa4
3144 #define SQ_V_CMP_NE_I16                           0xa5
3145 #define SQ_V_CMP_GE_I16                           0xa6
3146 #define SQ_V_CMP_T_I16                            0xa7
3147 #define SQ_V_CMP_F_U16                            0xa8
3148 #define SQ_V_CMP_LT_U16                           0xa9
3149 #define SQ_V_CMP_EQ_U16                           0xaa
3150 #define SQ_V_CMP_LE_U16                           0xab
3151 #define SQ_V_CMP_GT_U16                           0xac
3152 #define SQ_V_CMP_NE_U16                           0xad
3153 #define SQ_V_CMP_GE_U16                           0xae
3154 #define SQ_V_CMP_T_U16                            0xaf
3155 #define SQ_V_CMPX_F_I16                           0xb0
3156 #define SQ_V_CMPX_LT_I16                          0xb1
3157 #define SQ_V_CMPX_EQ_I16                          0xb2
3158 #define SQ_V_CMPX_LE_I16                          0xb3
3159 #define SQ_V_CMPX_GT_I16                          0xb4
3160 #define SQ_V_CMPX_NE_I16                          0xb5
3161 #define SQ_V_CMPX_GE_I16                          0xb6
3162 #define SQ_V_CMPX_T_I16                           0xb7
3163 #define SQ_V_CMPX_F_U16                           0xb8
3164 #define SQ_V_CMPX_LT_U16                          0xb9
3165 #define SQ_V_CMPX_EQ_U16                          0xba
3166 #define SQ_V_CMPX_LE_U16                          0xbb
3167 #define SQ_V_CMPX_GT_U16                          0xbc
3168 #define SQ_V_CMPX_NE_U16                          0xbd
3169 #define SQ_V_CMPX_GE_U16                          0xbe
3170 #define SQ_V_CMPX_T_U16                           0xbf
3171 #define SQ_V_CMP_F_I32                            0xc0
3172 #define SQ_V_CMP_LT_I32                           0xc1
3173 #define SQ_V_CMP_EQ_I32                           0xc2
3174 #define SQ_V_CMP_LE_I32                           0xc3
3175 #define SQ_V_CMP_GT_I32                           0xc4
3176 #define SQ_V_CMP_NE_I32                           0xc5
3177 #define SQ_V_CMP_GE_I32                           0xc6
3178 #define SQ_V_CMP_T_I32                            0xc7
3179 #define SQ_V_CMP_F_U32                            0xc8
3180 #define SQ_V_CMP_LT_U32                           0xc9
3181 #define SQ_V_CMP_EQ_U32                           0xca
3182 #define SQ_V_CMP_LE_U32                           0xcb
3183 #define SQ_V_CMP_GT_U32                           0xcc
3184 #define SQ_V_CMP_NE_U32                           0xcd
3185 #define SQ_V_CMP_GE_U32                           0xce
3186 #define SQ_V_CMP_T_U32                            0xcf
3187 #define SQ_V_CMPX_F_I32                           0xd0
3188 #define SQ_V_CMPX_LT_I32                          0xd1
3189 #define SQ_V_CMPX_EQ_I32                          0xd2
3190 #define SQ_V_CMPX_LE_I32                          0xd3
3191 #define SQ_V_CMPX_GT_I32                          0xd4
3192 #define SQ_V_CMPX_NE_I32                          0xd5
3193 #define SQ_V_CMPX_GE_I32                          0xd6
3194 #define SQ_V_CMPX_T_I32                           0xd7
3195 #define SQ_V_CMPX_F_U32                           0xd8
3196 #define SQ_V_CMPX_LT_U32                          0xd9
3197 #define SQ_V_CMPX_EQ_U32                          0xda
3198 #define SQ_V_CMPX_LE_U32                          0xdb
3199 #define SQ_V_CMPX_GT_U32                          0xdc
3200 #define SQ_V_CMPX_NE_U32                          0xdd
3201 #define SQ_V_CMPX_GE_U32                          0xde
3202 #define SQ_V_CMPX_T_U32                           0xdf
3203 #define SQ_V_CMP_F_I64                            0xe0
3204 #define SQ_V_CMP_LT_I64                           0xe1
3205 #define SQ_V_CMP_EQ_I64                           0xe2
3206 #define SQ_V_CMP_LE_I64                           0xe3
3207 #define SQ_V_CMP_GT_I64                           0xe4
3208 #define SQ_V_CMP_NE_I64                           0xe5
3209 #define SQ_V_CMP_GE_I64                           0xe6
3210 #define SQ_V_CMP_T_I64                            0xe7
3211 #define SQ_V_CMP_F_U64                            0xe8
3212 #define SQ_V_CMP_LT_U64                           0xe9
3213 #define SQ_V_CMP_EQ_U64                           0xea
3214 #define SQ_V_CMP_LE_U64                           0xeb
3215 #define SQ_V_CMP_GT_U64                           0xec
3216 #define SQ_V_CMP_NE_U64                           0xed
3217 #define SQ_V_CMP_GE_U64                           0xee
3218 #define SQ_V_CMP_T_U64                            0xef
3219 #define SQ_V_CMPX_F_I64                           0xf0
3220 #define SQ_V_CMPX_LT_I64                          0xf1
3221 #define SQ_V_CMPX_EQ_I64                          0xf2
3222 #define SQ_V_CMPX_LE_I64                          0xf3
3223 #define SQ_V_CMPX_GT_I64                          0xf4
3224 #define SQ_V_CMPX_NE_I64                          0xf5
3225 #define SQ_V_CMPX_GE_I64                          0xf6
3226 #define SQ_V_CMPX_T_I64                           0xf7
3227 #define SQ_V_CMPX_F_U64                           0xf8
3228 #define SQ_V_CMPX_LT_U64                          0xf9
3229 #define SQ_V_CMPX_EQ_U64                          0xfa
3230 #define SQ_V_CMPX_LE_U64                          0xfb
3231 #define SQ_V_CMPX_GT_U64                          0xfc
3232 #define SQ_V_CMPX_NE_U64                          0xfd
3233 #define SQ_V_CMPX_GE_U64                          0xfe
3234 #define SQ_V_CMPX_T_U64                           0xff
3235 #define SQ_L1                                     0x1
3236 #define SQ_L2                                     0x2
3237 #define SQ_L3                                     0x3
3238 #define SQ_L4                                     0x4
3239 #define SQ_L5                                     0x5
3240 #define SQ_L6                                     0x6
3241 #define SQ_L7                                     0x7
3242 #define SQ_L8                                     0x8
3243 #define SQ_L9                                     0x9
3244 #define SQ_L10                                    0xa
3245 #define SQ_L11                                    0xb
3246 #define SQ_L12                                    0xc
3247 #define SQ_L13                                    0xd
3248 #define SQ_L14                                    0xe
3249 #define SQ_L15                                    0xf
3250 #define SQ_SGPR0                                  0x0
3251 #define SQ_SDWA_UNUSED_PAD                        0x0
3252 #define SQ_SDWA_UNUSED_SEXT                       0x1
3253 #define SQ_SDWA_UNUSED_PRESERVE                   0x2
3254 #define SQ_F                                      0x0
3255 #define SQ_LT                                     0x1
3256 #define SQ_EQ                                     0x2
3257 #define SQ_LE                                     0x3
3258 #define SQ_GT                                     0x4
3259 #define SQ_NE                                     0x5
3260 #define SQ_GE                                     0x6
3261 #define SQ_T                                      0x7
3262 #define SQ_SRC_64_INT                             0xc0
3263 #define SQ_SRC_M_1_INT                            0xc1
3264 #define SQ_SRC_M_2_INT                            0xc2
3265 #define SQ_SRC_M_3_INT                            0xc3
3266 #define SQ_SRC_M_4_INT                            0xc4
3267 #define SQ_SRC_M_5_INT                            0xc5
3268 #define SQ_SRC_M_6_INT                            0xc6
3269 #define SQ_SRC_M_7_INT                            0xc7
3270 #define SQ_SRC_M_8_INT                            0xc8
3271 #define SQ_SRC_M_9_INT                            0xc9
3272 #define SQ_SRC_M_10_INT                           0xca
3273 #define SQ_SRC_M_11_INT                           0xcb
3274 #define SQ_SRC_M_12_INT                           0xcc
3275 #define SQ_SRC_M_13_INT                           0xcd
3276 #define SQ_SRC_M_14_INT                           0xce
3277 #define SQ_SRC_M_15_INT                           0xcf
3278 #define SQ_SRC_M_16_INT                           0xd0
3279 #define SQ_SRC_0_5                                0xf0
3280 #define SQ_SRC_M_0_5                              0xf1
3281 #define SQ_SRC_1                                  0xf2
3282 #define SQ_SRC_M_1                                0xf3
3283 #define SQ_SRC_2                                  0xf4
3284 #define SQ_SRC_M_2                                0xf5
3285 #define SQ_SRC_4                                  0xf6
3286 #define SQ_SRC_M_4                                0xf7
3287 #define SQ_SRC_INV_2PI                            0xf8
3288 #define SQ_SRC_0                                  0x80
3289 #define SQ_SRC_1_INT                              0x81
3290 #define SQ_SRC_2_INT                              0x82
3291 #define SQ_SRC_3_INT                              0x83
3292 #define SQ_SRC_4_INT                              0x84
3293 #define SQ_SRC_5_INT                              0x85
3294 #define SQ_SRC_6_INT                              0x86
3295 #define SQ_SRC_7_INT                              0x87
3296 #define SQ_SRC_8_INT                              0x88
3297 #define SQ_SRC_9_INT                              0x89
3298 #define SQ_SRC_10_INT                             0x8a
3299 #define SQ_SRC_11_INT                             0x8b
3300 #define SQ_SRC_12_INT                             0x8c
3301 #define SQ_SRC_13_INT                             0x8d
3302 #define SQ_SRC_14_INT                             0x8e
3303 #define SQ_SRC_15_INT                             0x8f
3304 #define SQ_SRC_16_INT                             0x90
3305 #define SQ_SRC_17_INT                             0x91
3306 #define SQ_SRC_18_INT                             0x92
3307 #define SQ_SRC_19_INT                             0x93
3308 #define SQ_SRC_20_INT                             0x94
3309 #define SQ_SRC_21_INT                             0x95
3310 #define SQ_SRC_22_INT                             0x96
3311 #define SQ_SRC_23_INT                             0x97
3312 #define SQ_SRC_24_INT                             0x98
3313 #define SQ_SRC_25_INT                             0x99
3314 #define SQ_SRC_26_INT                             0x9a
3315 #define SQ_SRC_27_INT                             0x9b
3316 #define SQ_SRC_28_INT                             0x9c
3317 #define SQ_SRC_29_INT                             0x9d
3318 #define SQ_SRC_30_INT                             0x9e
3319 #define SQ_SRC_31_INT                             0x9f
3320 #define SQ_SRC_32_INT                             0xa0
3321 #define SQ_SRC_33_INT                             0xa1
3322 #define SQ_SRC_34_INT                             0xa2
3323 #define SQ_SRC_35_INT                             0xa3
3324 #define SQ_SRC_36_INT                             0xa4
3325 #define SQ_SRC_37_INT                             0xa5
3326 #define SQ_SRC_38_INT                             0xa6
3327 #define SQ_SRC_39_INT                             0xa7
3328 #define SQ_SRC_40_INT                             0xa8
3329 #define SQ_SRC_41_INT                             0xa9
3330 #define SQ_SRC_42_INT                             0xaa
3331 #define SQ_SRC_43_INT                             0xab
3332 #define SQ_SRC_44_INT                             0xac
3333 #define SQ_SRC_45_INT                             0xad
3334 #define SQ_SRC_46_INT                             0xae
3335 #define SQ_SRC_47_INT                             0xaf
3336 #define SQ_SRC_48_INT                             0xb0
3337 #define SQ_SRC_49_INT                             0xb1
3338 #define SQ_SRC_50_INT                             0xb2
3339 #define SQ_SRC_51_INT                             0xb3
3340 #define SQ_SRC_52_INT                             0xb4
3341 #define SQ_SRC_53_INT                             0xb5
3342 #define SQ_SRC_54_INT                             0xb6
3343 #define SQ_SRC_55_INT                             0xb7
3344 #define SQ_SRC_56_INT                             0xb8
3345 #define SQ_SRC_57_INT                             0xb9
3346 #define SQ_SRC_58_INT                             0xba
3347 #define SQ_SRC_59_INT                             0xbb
3348 #define SQ_SRC_60_INT                             0xbc
3349 #define SQ_SRC_61_INT                             0xbd
3350 #define SQ_SRC_62_INT                             0xbe
3351 #define SQ_SRC_63_INT                             0xbf
3352 #define SQ_DS_ADD_U32                             0x0
3353 #define SQ_DS_SUB_U32                             0x1
3354 #define SQ_DS_RSUB_U32                            0x2
3355 #define SQ_DS_INC_U32                             0x3
3356 #define SQ_DS_DEC_U32                             0x4
3357 #define SQ_DS_MIN_I32                             0x5
3358 #define SQ_DS_MAX_I32                             0x6
3359 #define SQ_DS_MIN_U32                             0x7
3360 #define SQ_DS_MAX_U32                             0x8
3361 #define SQ_DS_AND_B32                             0x9
3362 #define SQ_DS_OR_B32                              0xa
3363 #define SQ_DS_XOR_B32                             0xb
3364 #define SQ_DS_MSKOR_B32                           0xc
3365 #define SQ_DS_WRITE_B32                           0xd
3366 #define SQ_DS_WRITE2_B32                          0xe
3367 #define SQ_DS_WRITE2ST64_B32                      0xf
3368 #define SQ_DS_CMPST_B32                           0x10
3369 #define SQ_DS_CMPST_F32                           0x11
3370 #define SQ_DS_MIN_F32                             0x12
3371 #define SQ_DS_MAX_F32                             0x13
3372 #define SQ_DS_NOP                                 0x14
3373 #define SQ_DS_ADD_F32                             0x15
3374 #define SQ_DS_WRITE_B8                            0x1e
3375 #define SQ_DS_WRITE_B16                           0x1f
3376 #define SQ_DS_ADD_RTN_U32                         0x20
3377 #define SQ_DS_SUB_RTN_U32                         0x21
3378 #define SQ_DS_RSUB_RTN_U32                        0x22
3379 #define SQ_DS_INC_RTN_U32                         0x23
3380 #define SQ_DS_DEC_RTN_U32                         0x24
3381 #define SQ_DS_MIN_RTN_I32                         0x25
3382 #define SQ_DS_MAX_RTN_I32                         0x26
3383 #define SQ_DS_MIN_RTN_U32                         0x27
3384 #define SQ_DS_MAX_RTN_U32                         0x28
3385 #define SQ_DS_AND_RTN_B32                         0x29
3386 #define SQ_DS_OR_RTN_B32                          0x2a
3387 #define SQ_DS_XOR_RTN_B32                         0x2b
3388 #define SQ_DS_MSKOR_RTN_B32                       0x2c
3389 #define SQ_DS_WRXCHG_RTN_B32                      0x2d
3390 #define SQ_DS_WRXCHG2_RTN_B32                     0x2e
3391 #define SQ_DS_WRXCHG2ST64_RTN_B32                 0x2f
3392 #define SQ_DS_CMPST_RTN_B32                       0x30
3393 #define SQ_DS_CMPST_RTN_F32                       0x31
3394 #define SQ_DS_MIN_RTN_F32                         0x32
3395 #define SQ_DS_MAX_RTN_F32                         0x33
3396 #define SQ_DS_WRAP_RTN_B32                        0x34
3397 #define SQ_DS_ADD_RTN_F32                         0x35
3398 #define SQ_DS_READ_B32                            0x36
3399 #define SQ_DS_READ2_B32                           0x37
3400 #define SQ_DS_READ2ST64_B32                       0x38
3401 #define SQ_DS_READ_I8                             0x39
3402 #define SQ_DS_READ_U8                             0x3a
3403 #define SQ_DS_READ_I16                            0x3b
3404 #define SQ_DS_READ_U16                            0x3c
3405 #define SQ_DS_SWIZZLE_B32                         0x3d
3406 #define SQ_DS_PERMUTE_B32                         0x3e
3407 #define SQ_DS_BPERMUTE_B32                        0x3f
3408 #define SQ_DS_ADD_U64                             0x40
3409 #define SQ_DS_SUB_U64                             0x41
3410 #define SQ_DS_RSUB_U64                            0x42
3411 #define SQ_DS_INC_U64                             0x43
3412 #define SQ_DS_DEC_U64                             0x44
3413 #define SQ_DS_MIN_I64                             0x45
3414 #define SQ_DS_MAX_I64                             0x46
3415 #define SQ_DS_MIN_U64                             0x47
3416 #define SQ_DS_MAX_U64                             0x48
3417 #define SQ_DS_AND_B64                             0x49
3418 #define SQ_DS_OR_B64                              0x4a
3419 #define SQ_DS_XOR_B64                             0x4b
3420 #define SQ_DS_MSKOR_B64                           0x4c
3421 #define SQ_DS_WRITE_B64                           0x4d
3422 #define SQ_DS_WRITE2_B64                          0x4e
3423 #define SQ_DS_WRITE2ST64_B64                      0x4f
3424 #define SQ_DS_CMPST_B64                           0x50
3425 #define SQ_DS_CMPST_F64                           0x51
3426 #define SQ_DS_MIN_F64                             0x52
3427 #define SQ_DS_MAX_F64                             0x53
3428 #define SQ_DS_ADD_RTN_U64                         0x60
3429 #define SQ_DS_SUB_RTN_U64                         0x61
3430 #define SQ_DS_RSUB_RTN_U64                        0x62
3431 #define SQ_DS_INC_RTN_U64                         0x63
3432 #define SQ_DS_DEC_RTN_U64                         0x64
3433 #define SQ_DS_MIN_RTN_I64                         0x65
3434 #define SQ_DS_MAX_RTN_I64                         0x66
3435 #define SQ_DS_MIN_RTN_U64                         0x67
3436 #define SQ_DS_MAX_RTN_U64                         0x68
3437 #define SQ_DS_AND_RTN_B64                         0x69
3438 #define SQ_DS_OR_RTN_B64                          0x6a
3439 #define SQ_DS_XOR_RTN_B64                         0x6b
3440 #define SQ_DS_MSKOR_RTN_B64                       0x6c
3441 #define SQ_DS_WRXCHG_RTN_B64                      0x6d
3442 #define SQ_DS_WRXCHG2_RTN_B64                     0x6e
3443 #define SQ_DS_WRXCHG2ST64_RTN_B64                 0x6f
3444 #define SQ_DS_CMPST_RTN_B64                       0x70
3445 #define SQ_DS_CMPST_RTN_F64                       0x71
3446 #define SQ_DS_MIN_RTN_F64                         0x72
3447 #define SQ_DS_MAX_RTN_F64                         0x73
3448 #define SQ_DS_READ_B64                            0x76
3449 #define SQ_DS_READ2_B64                           0x77
3450 #define SQ_DS_READ2ST64_B64                       0x78
3451 #define SQ_DS_CONDXCHG32_RTN_B64                  0x7e
3452 #define SQ_DS_ADD_SRC2_U32                        0x80
3453 #define SQ_DS_SUB_SRC2_U32                        0x81
3454 #define SQ_DS_RSUB_SRC2_U32                       0x82
3455 #define SQ_DS_INC_SRC2_U32                        0x83
3456 #define SQ_DS_DEC_SRC2_U32                        0x84
3457 #define SQ_DS_MIN_SRC2_I32                        0x85
3458 #define SQ_DS_MAX_SRC2_I32                        0x86
3459 #define SQ_DS_MIN_SRC2_U32                        0x87
3460 #define SQ_DS_MAX_SRC2_U32                        0x88
3461 #define SQ_DS_AND_SRC2_B32                        0x89
3462 #define SQ_DS_OR_SRC2_B32                         0x8a
3463 #define SQ_DS_XOR_SRC2_B32                        0x8b
3464 #define SQ_DS_WRITE_SRC2_B32                      0x8d
3465 #define SQ_DS_MIN_SRC2_F32                        0x92
3466 #define SQ_DS_MAX_SRC2_F32                        0x93
3467 #define SQ_DS_ADD_SRC2_F32                        0x95
3468 #define SQ_DS_GWS_SEMA_RELEASE_ALL                0x98
3469 #define SQ_DS_GWS_INIT                            0x99
3470 #define SQ_DS_GWS_SEMA_V                          0x9a
3471 #define SQ_DS_GWS_SEMA_BR                         0x9b
3472 #define SQ_DS_GWS_SEMA_P                          0x9c
3473 #define SQ_DS_GWS_BARRIER                         0x9d
3474 #define SQ_DS_CONSUME                             0xbd
3475 #define SQ_DS_APPEND                              0xbe
3476 #define SQ_DS_ORDERED_COUNT                       0xbf
3477 #define SQ_DS_ADD_SRC2_U64                        0xc0
3478 #define SQ_DS_SUB_SRC2_U64                        0xc1
3479 #define SQ_DS_RSUB_SRC2_U64                       0xc2
3480 #define SQ_DS_INC_SRC2_U64                        0xc3
3481 #define SQ_DS_DEC_SRC2_U64                        0xc4
3482 #define SQ_DS_MIN_SRC2_I64                        0xc5
3483 #define SQ_DS_MAX_SRC2_I64                        0xc6
3484 #define SQ_DS_MIN_SRC2_U64                        0xc7
3485 #define SQ_DS_MAX_SRC2_U64                        0xc8
3486 #define SQ_DS_AND_SRC2_B64                        0xc9
3487 #define SQ_DS_OR_SRC2_B64                         0xca
3488 #define SQ_DS_XOR_SRC2_B64                        0xcb
3489 #define SQ_DS_WRITE_SRC2_B64                      0xcd
3490 #define SQ_DS_MIN_SRC2_F64                        0xd2
3491 #define SQ_DS_MAX_SRC2_F64                        0xd3
3492 #define SQ_DS_WRITE_B96                           0xde
3493 #define SQ_DS_WRITE_B128                          0xdf
3494 #define SQ_DS_CONDXCHG32_RTN_B128                 0xfd
3495 #define SQ_DS_READ_B96                            0xfe
3496 #define SQ_DS_READ_B128                           0xff
3497 #define SQ_BUFFER_LOAD_FORMAT_X                   0x0
3498 #define SQ_BUFFER_LOAD_FORMAT_XY                  0x1
3499 #define SQ_BUFFER_LOAD_FORMAT_XYZ                 0x2
3500 #define SQ_BUFFER_LOAD_FORMAT_XYZW                0x3
3501 #define SQ_BUFFER_STORE_FORMAT_X                  0x4
3502 #define SQ_BUFFER_STORE_FORMAT_XY                 0x5
3503 #define SQ_BUFFER_STORE_FORMAT_XYZ                0x6
3504 #define SQ_BUFFER_STORE_FORMAT_XYZW               0x7
3505 #define SQ_BUFFER_LOAD_FORMAT_D16_X               0x8
3506 #define SQ_BUFFER_LOAD_FORMAT_D16_XY              0x9
3507 #define SQ_BUFFER_LOAD_FORMAT_D16_XYZ             0xa
3508 #define SQ_BUFFER_LOAD_FORMAT_D16_XYZW            0xb
3509 #define SQ_BUFFER_STORE_FORMAT_D16_X              0xc
3510 #define SQ_BUFFER_STORE_FORMAT_D16_XY             0xd
3511 #define SQ_BUFFER_STORE_FORMAT_D16_XYZ            0xe
3512 #define SQ_BUFFER_STORE_FORMAT_D16_XYZW           0xf
3513 #define SQ_BUFFER_LOAD_UBYTE                      0x10
3514 #define SQ_BUFFER_LOAD_SBYTE                      0x11
3515 #define SQ_BUFFER_LOAD_USHORT                     0x12
3516 #define SQ_BUFFER_LOAD_SSHORT                     0x13
3517 #define SQ_BUFFER_LOAD_DWORD                      0x14
3518 #define SQ_BUFFER_LOAD_DWORDX2                    0x15
3519 #define SQ_BUFFER_LOAD_DWORDX3                    0x16
3520 #define SQ_BUFFER_LOAD_DWORDX4                    0x17
3521 #define SQ_BUFFER_STORE_BYTE                      0x18
3522 #define SQ_BUFFER_STORE_SHORT                     0x1a
3523 #define SQ_BUFFER_STORE_DWORD                     0x1c
3524 #define SQ_BUFFER_STORE_DWORDX2                   0x1d
3525 #define SQ_BUFFER_STORE_DWORDX3                   0x1e
3526 #define SQ_BUFFER_STORE_DWORDX4                   0x1f
3527 #define SQ_BUFFER_STORE_LDS_DWORD                 0x3d
3528 #define SQ_BUFFER_WBINVL1                         0x3e
3529 #define SQ_BUFFER_WBINVL1_VOL                     0x3f
3530 #define SQ_BUFFER_ATOMIC_SWAP                     0x40
3531 #define SQ_BUFFER_ATOMIC_CMPSWAP                  0x41
3532 #define SQ_BUFFER_ATOMIC_ADD                      0x42
3533 #define SQ_BUFFER_ATOMIC_SUB                      0x43
3534 #define SQ_BUFFER_ATOMIC_SMIN                     0x44
3535 #define SQ_BUFFER_ATOMIC_UMIN                     0x45
3536 #define SQ_BUFFER_ATOMIC_SMAX                     0x46
3537 #define SQ_BUFFER_ATOMIC_UMAX                     0x47
3538 #define SQ_BUFFER_ATOMIC_AND                      0x48
3539 #define SQ_BUFFER_ATOMIC_OR                       0x49
3540 #define SQ_BUFFER_ATOMIC_XOR                      0x4a
3541 #define SQ_BUFFER_ATOMIC_INC                      0x4b
3542 #define SQ_BUFFER_ATOMIC_DEC                      0x4c
3543 #define SQ_BUFFER_ATOMIC_SWAP_X2                  0x60
3544 #define SQ_BUFFER_ATOMIC_CMPSWAP_X2               0x61
3545 #define SQ_BUFFER_ATOMIC_ADD_X2                   0x62
3546 #define SQ_BUFFER_ATOMIC_SUB_X2                   0x63
3547 #define SQ_BUFFER_ATOMIC_SMIN_X2                  0x64
3548 #define SQ_BUFFER_ATOMIC_UMIN_X2                  0x65
3549 #define SQ_BUFFER_ATOMIC_SMAX_X2                  0x66
3550 #define SQ_BUFFER_ATOMIC_UMAX_X2                  0x67
3551 #define SQ_BUFFER_ATOMIC_AND_X2                   0x68
3552 #define SQ_BUFFER_ATOMIC_OR_X2                    0x69
3553 #define SQ_BUFFER_ATOMIC_XOR_X2                   0x6a
3554 #define SQ_BUFFER_ATOMIC_INC_X2                   0x6b
3555 #define SQ_BUFFER_ATOMIC_DEC_X2                   0x6c
3556 #define SQ_EXEC_LO                                0x7e
3557 #define SQ_EXEC_HI                                0x7f
3558 #define SQ_SRC_SCC                                0xfd
3559 #define SQ_OMOD_OFF                               0x0
3560 #define SQ_OMOD_M2                                0x1
3561 #define SQ_OMOD_M4                                0x2
3562 #define SQ_OMOD_D2                                0x3
3563 #define SQ_DPP_QUAD_PERM                          0x0
3564 #define SQ_DPP_ROW_SL1                            0x101
3565 #define SQ_DPP_ROW_SL2                            0x102
3566 #define SQ_DPP_ROW_SL3                            0x103
3567 #define SQ_DPP_ROW_SL4                            0x104
3568 #define SQ_DPP_ROW_SL5                            0x105
3569 #define SQ_DPP_ROW_SL6                            0x106
3570 #define SQ_DPP_ROW_SL7                            0x107
3571 #define SQ_DPP_ROW_SL8                            0x108
3572 #define SQ_DPP_ROW_SL9                            0x109
3573 #define SQ_DPP_ROW_SL10                           0x10a
3574 #define SQ_DPP_ROW_SL11                           0x10b
3575 #define SQ_DPP_ROW_SL12                           0x10c
3576 #define SQ_DPP_ROW_SL13                           0x10d
3577 #define SQ_DPP_ROW_SL14                           0x10e
3578 #define SQ_DPP_ROW_SL15                           0x10f
3579 #define SQ_DPP_ROW_SR1                            0x111
3580 #define SQ_DPP_ROW_SR2                            0x112
3581 #define SQ_DPP_ROW_SR3                            0x113
3582 #define SQ_DPP_ROW_SR4                            0x114
3583 #define SQ_DPP_ROW_SR5                            0x115
3584 #define SQ_DPP_ROW_SR6                            0x116
3585 #define SQ_DPP_ROW_SR7                            0x117
3586 #define SQ_DPP_ROW_SR8                            0x118
3587 #define SQ_DPP_ROW_SR9                            0x119
3588 #define SQ_DPP_ROW_SR10                           0x11a
3589 #define SQ_DPP_ROW_SR11                           0x11b
3590 #define SQ_DPP_ROW_SR12                           0x11c
3591 #define SQ_DPP_ROW_SR13                           0x11d
3592 #define SQ_DPP_ROW_SR14                           0x11e
3593 #define SQ_DPP_ROW_SR15                           0x11f
3594 #define SQ_DPP_ROW_RR1                            0x121
3595 #define SQ_DPP_ROW_RR2                            0x122
3596 #define SQ_DPP_ROW_RR3                            0x123
3597 #define SQ_DPP_ROW_RR4                            0x124
3598 #define SQ_DPP_ROW_RR5                            0x125
3599 #define SQ_DPP_ROW_RR6                            0x126
3600 #define SQ_DPP_ROW_RR7                            0x127
3601 #define SQ_DPP_ROW_RR8                            0x128
3602 #define SQ_DPP_ROW_RR9                            0x129
3603 #define SQ_DPP_ROW_RR10                           0x12a
3604 #define SQ_DPP_ROW_RR11                           0x12b
3605 #define SQ_DPP_ROW_RR12                           0x12c
3606 #define SQ_DPP_ROW_RR13                           0x12d
3607 #define SQ_DPP_ROW_RR14                           0x12e
3608 #define SQ_DPP_ROW_RR15                           0x12f
3609 #define SQ_DPP_WF_SL1                             0x130
3610 #define SQ_DPP_WF_RL1                             0x134
3611 #define SQ_DPP_WF_SR1                             0x138
3612 #define SQ_DPP_WF_RR1                             0x13c
3613 #define SQ_DPP_ROW_MIRROR                         0x140
3614 #define SQ_DPP_ROW_HALF_MIRROR                    0x141
3615 #define SQ_DPP_ROW_BCAST15                        0x142
3616 #define SQ_DPP_ROW_BCAST31                        0x143
3617 #define SQ_EXP_GDS0                               0x18
3618 #define SQ_GS_OP_NOP                              0x0
3619 #define SQ_GS_OP_CUT                              0x1
3620 #define SQ_GS_OP_EMIT                             0x2
3621 #define SQ_GS_OP_EMIT_CUT                         0x3
3622 #define SQ_IMAGE_LOAD                             0x0
3623 #define SQ_IMAGE_LOAD_MIP                         0x1
3624 #define SQ_IMAGE_LOAD_PCK                         0x2
3625 #define SQ_IMAGE_LOAD_PCK_SGN                     0x3
3626 #define SQ_IMAGE_LOAD_MIP_PCK                     0x4
3627 #define SQ_IMAGE_LOAD_MIP_PCK_SGN                 0x5
3628 #define SQ_IMAGE_STORE                            0x8
3629 #define SQ_IMAGE_STORE_MIP                        0x9
3630 #define SQ_IMAGE_STORE_PCK                        0xa
3631 #define SQ_IMAGE_STORE_MIP_PCK                    0xb
3632 #define SQ_IMAGE_GET_RESINFO                      0xe
3633 #define SQ_IMAGE_ATOMIC_SWAP                      0x10
3634 #define SQ_IMAGE_ATOMIC_CMPSWAP                   0x11
3635 #define SQ_IMAGE_ATOMIC_ADD                       0x12
3636 #define SQ_IMAGE_ATOMIC_SUB                       0x13
3637 #define SQ_IMAGE_ATOMIC_SMIN                      0x14
3638 #define SQ_IMAGE_ATOMIC_UMIN                      0x15
3639 #define SQ_IMAGE_ATOMIC_SMAX                      0x16
3640 #define SQ_IMAGE_ATOMIC_UMAX                      0x17
3641 #define SQ_IMAGE_ATOMIC_AND                       0x18
3642 #define SQ_IMAGE_ATOMIC_OR                        0x19
3643 #define SQ_IMAGE_ATOMIC_XOR                       0x1a
3644 #define SQ_IMAGE_ATOMIC_INC                       0x1b
3645 #define SQ_IMAGE_ATOMIC_DEC                       0x1c
3646 #define SQ_IMAGE_SAMPLE                           0x20
3647 #define SQ_IMAGE_SAMPLE_CL                        0x21
3648 #define SQ_IMAGE_SAMPLE_D                         0x22
3649 #define SQ_IMAGE_SAMPLE_D_CL                      0x23
3650 #define SQ_IMAGE_SAMPLE_L                         0x24
3651 #define SQ_IMAGE_SAMPLE_B                         0x25
3652 #define SQ_IMAGE_SAMPLE_B_CL                      0x26
3653 #define SQ_IMAGE_SAMPLE_LZ                        0x27
3654 #define SQ_IMAGE_SAMPLE_C                         0x28
3655 #define SQ_IMAGE_SAMPLE_C_CL                      0x29
3656 #define SQ_IMAGE_SAMPLE_C_D                       0x2a
3657 #define SQ_IMAGE_SAMPLE_C_D_CL                    0x2b
3658 #define SQ_IMAGE_SAMPLE_C_L                       0x2c
3659 #define SQ_IMAGE_SAMPLE_C_B                       0x2d
3660 #define SQ_IMAGE_SAMPLE_C_B_CL                    0x2e
3661 #define SQ_IMAGE_SAMPLE_C_LZ                      0x2f
3662 #define SQ_IMAGE_SAMPLE_O                         0x30
3663 #define SQ_IMAGE_SAMPLE_CL_O                      0x31
3664 #define SQ_IMAGE_SAMPLE_D_O                       0x32
3665 #define SQ_IMAGE_SAMPLE_D_CL_O                    0x33
3666 #define SQ_IMAGE_SAMPLE_L_O                       0x34
3667 #define SQ_IMAGE_SAMPLE_B_O                       0x35
3668 #define SQ_IMAGE_SAMPLE_B_CL_O                    0x36
3669 #define SQ_IMAGE_SAMPLE_LZ_O                      0x37
3670 #define SQ_IMAGE_SAMPLE_C_O                       0x38
3671 #define SQ_IMAGE_SAMPLE_C_CL_O                    0x39
3672 #define SQ_IMAGE_SAMPLE_C_D_O                     0x3a
3673 #define SQ_IMAGE_SAMPLE_C_D_CL_O                  0x3b
3674 #define SQ_IMAGE_SAMPLE_C_L_O                     0x3c
3675 #define SQ_IMAGE_SAMPLE_C_B_O                     0x3d
3676 #define SQ_IMAGE_SAMPLE_C_B_CL_O                  0x3e
3677 #define SQ_IMAGE_SAMPLE_C_LZ_O                    0x3f
3678 #define SQ_IMAGE_GATHER4                          0x40
3679 #define SQ_IMAGE_GATHER4_CL                       0x41
3680 #define SQ_IMAGE_GATHER4_L                        0x44
3681 #define SQ_IMAGE_GATHER4_B                        0x45
3682 #define SQ_IMAGE_GATHER4_B_CL                     0x46
3683 #define SQ_IMAGE_GATHER4_LZ                       0x47
3684 #define SQ_IMAGE_GATHER4_C                        0x48
3685 #define SQ_IMAGE_GATHER4_C_CL                     0x49
3686 #define SQ_IMAGE_GATHER4_C_L                      0x4c
3687 #define SQ_IMAGE_GATHER4_C_B                      0x4d
3688 #define SQ_IMAGE_GATHER4_C_B_CL                   0x4e
3689 #define SQ_IMAGE_GATHER4_C_LZ                     0x4f
3690 #define SQ_IMAGE_GATHER4_O                        0x50
3691 #define SQ_IMAGE_GATHER4_CL_O                     0x51
3692 #define SQ_IMAGE_GATHER4_L_O                      0x54
3693 #define SQ_IMAGE_GATHER4_B_O                      0x55
3694 #define SQ_IMAGE_GATHER4_B_CL_O                   0x56
3695 #define SQ_IMAGE_GATHER4_LZ_O                     0x57
3696 #define SQ_IMAGE_GATHER4_C_O                      0x58
3697 #define SQ_IMAGE_GATHER4_C_CL_O                   0x59
3698 #define SQ_IMAGE_GATHER4_C_L_O                    0x5c
3699 #define SQ_IMAGE_GATHER4_C_B_O                    0x5d
3700 #define SQ_IMAGE_GATHER4_C_B_CL_O                 0x5e
3701 #define SQ_IMAGE_GATHER4_C_LZ_O                   0x5f
3702 #define SQ_IMAGE_GET_LOD                          0x60
3703 #define SQ_IMAGE_SAMPLE_CD                        0x68
3704 #define SQ_IMAGE_SAMPLE_CD_CL                     0x69
3705 #define SQ_IMAGE_SAMPLE_C_CD                      0x6a
3706 #define SQ_IMAGE_SAMPLE_C_CD_CL                   0x6b
3707 #define SQ_IMAGE_SAMPLE_CD_O                      0x6c
3708 #define SQ_IMAGE_SAMPLE_CD_CL_O                   0x6d
3709 #define SQ_IMAGE_SAMPLE_C_CD_O                    0x6e
3710 #define SQ_IMAGE_SAMPLE_C_CD_CL_O                 0x6f
3711 #define SQ_IMAGE_RSRC256                          0x7e
3712 #define SQ_IMAGE_SAMPLER                          0x7f
3713 #define SQ_SRC_VCCZ                               0xfb
3714 #define SQ_SRC_VGPR0                              0x100
3715 #define SQ_SDWA_BYTE_0                            0x0
3716 #define SQ_SDWA_BYTE_1                            0x1
3717 #define SQ_SDWA_BYTE_2                            0x2
3718 #define SQ_SDWA_BYTE_3                            0x3
3719 #define SQ_SDWA_WORD_0                            0x4
3720 #define SQ_SDWA_WORD_1                            0x5
3721 #define SQ_SDWA_DWORD                             0x6
3722 #define SQ_XNACK_MASK_LO                          0x68
3723 #define SQ_XNACK_MASK_HI                          0x69
3724 #define SQ_TBUFFER_LOAD_FORMAT_X                  0x0
3725 #define SQ_TBUFFER_LOAD_FORMAT_XY                 0x1
3726 #define SQ_TBUFFER_LOAD_FORMAT_XYZ                0x2
3727 #define SQ_TBUFFER_LOAD_FORMAT_XYZW               0x3
3728 #define SQ_TBUFFER_STORE_FORMAT_X                 0x4
3729 #define SQ_TBUFFER_STORE_FORMAT_XY                0x5
3730 #define SQ_TBUFFER_STORE_FORMAT_XYZ               0x6
3731 #define SQ_TBUFFER_STORE_FORMAT_XYZW              0x7
3732 #define SQ_TBUFFER_LOAD_FORMAT_D16_X              0x8
3733 #define SQ_TBUFFER_LOAD_FORMAT_D16_XY             0x9
3734 #define SQ_TBUFFER_LOAD_FORMAT_D16_XYZ            0xa
3735 #define SQ_TBUFFER_LOAD_FORMAT_D16_XYZW           0xb
3736 #define SQ_TBUFFER_STORE_FORMAT_D16_X             0xc
3737 #define SQ_TBUFFER_STORE_FORMAT_D16_XY            0xd
3738 #define SQ_TBUFFER_STORE_FORMAT_D16_XYZ           0xe
3739 #define SQ_TBUFFER_STORE_FORMAT_D16_XYZW          0xf
3740 #define SQ_CHAN_X                                 0x0
3741 #define SQ_CHAN_Y                                 0x1
3742 #define SQ_CHAN_Z                                 0x2
3743 #define SQ_CHAN_W                                 0x3
3744 #define SQ_V_NOP                                  0x0
3745 #define SQ_V_MOV_B32                              0x1
3746 #define SQ_V_READFIRSTLANE_B32                    0x2
3747 #define SQ_V_CVT_I32_F64                          0x3
3748 #define SQ_V_CVT_F64_I32                          0x4
3749 #define SQ_V_CVT_F32_I32                          0x5
3750 #define SQ_V_CVT_F32_U32                          0x6
3751 #define SQ_V_CVT_U32_F32                          0x7
3752 #define SQ_V_CVT_I32_F32                          0x8
3753 #define SQ_V_MOV_FED_B32                          0x9
3754 #define SQ_V_CVT_F16_F32                          0xa
3755 #define SQ_V_CVT_F32_F16                          0xb
3756 #define SQ_V_CVT_RPI_I32_F32                      0xc
3757 #define SQ_V_CVT_FLR_I32_F32                      0xd
3758 #define SQ_V_CVT_OFF_F32_I4                       0xe
3759 #define SQ_V_CVT_F32_F64                          0xf
3760 #define SQ_V_CVT_F64_F32                          0x10
3761 #define SQ_V_CVT_F32_UBYTE0                       0x11
3762 #define SQ_V_CVT_F32_UBYTE1                       0x12
3763 #define SQ_V_CVT_F32_UBYTE2                       0x13
3764 #define SQ_V_CVT_F32_UBYTE3                       0x14
3765 #define SQ_V_CVT_U32_F64                          0x15
3766 #define SQ_V_CVT_F64_U32                          0x16
3767 #define SQ_V_TRUNC_F64                            0x17
3768 #define SQ_V_CEIL_F64                             0x18
3769 #define SQ_V_RNDNE_F64                            0x19
3770 #define SQ_V_FLOOR_F64                            0x1a
3771 #define SQ_V_FRACT_F32                            0x1b
3772 #define SQ_V_TRUNC_F32                            0x1c
3773 #define SQ_V_CEIL_F32                             0x1d
3774 #define SQ_V_RNDNE_F32                            0x1e
3775 #define SQ_V_FLOOR_F32                            0x1f
3776 #define SQ_V_EXP_F32                              0x20
3777 #define SQ_V_LOG_F32                              0x21
3778 #define SQ_V_RCP_F32                              0x22
3779 #define SQ_V_RCP_IFLAG_F32                        0x23
3780 #define SQ_V_RSQ_F32                              0x24
3781 #define SQ_V_RCP_F64                              0x25
3782 #define SQ_V_RSQ_F64                              0x26
3783 #define SQ_V_SQRT_F32                             0x27
3784 #define SQ_V_SQRT_F64                             0x28
3785 #define SQ_V_SIN_F32                              0x29
3786 #define SQ_V_COS_F32                              0x2a
3787 #define SQ_V_NOT_B32                              0x2b
3788 #define SQ_V_BFREV_B32                            0x2c
3789 #define SQ_V_FFBH_U32                             0x2d
3790 #define SQ_V_FFBL_B32                             0x2e
3791 #define SQ_V_FFBH_I32                             0x2f
3792 #define SQ_V_FREXP_EXP_I32_F64                    0x30
3793 #define SQ_V_FREXP_MANT_F64                       0x31
3794 #define SQ_V_FRACT_F64                            0x32
3795 #define SQ_V_FREXP_EXP_I32_F32                    0x33
3796 #define SQ_V_FREXP_MANT_F32                       0x34
3797 #define SQ_V_CLREXCP                              0x35
3798 #define SQ_V_MOVRELD_B32                          0x36
3799 #define SQ_V_MOVRELS_B32                          0x37
3800 #define SQ_V_MOVRELSD_B32                         0x38
3801 #define SQ_V_CVT_F16_U16                          0x39
3802 #define SQ_V_CVT_F16_I16                          0x3a
3803 #define SQ_V_CVT_U16_F16                          0x3b
3804 #define SQ_V_CVT_I16_F16                          0x3c
3805 #define SQ_V_RCP_F16                              0x3d
3806 #define SQ_V_SQRT_F16                             0x3e
3807 #define SQ_V_RSQ_F16                              0x3f
3808 #define SQ_V_LOG_F16                              0x40
3809 #define SQ_V_EXP_F16                              0x41
3810 #define SQ_V_FREXP_MANT_F16                       0x42
3811 #define SQ_V_FREXP_EXP_I16_F16                    0x43
3812 #define SQ_V_FLOOR_F16                            0x44
3813 #define SQ_V_CEIL_F16                             0x45
3814 #define SQ_V_TRUNC_F16                            0x46
3815 #define SQ_V_RNDNE_F16                            0x47
3816 #define SQ_V_FRACT_F16                            0x48
3817 #define SQ_V_SIN_F16                              0x49
3818 #define SQ_V_COS_F16                              0x4a
3819 #define SQ_V_EXP_LEGACY_F32                       0x4b
3820 #define SQ_V_LOG_LEGACY_F32                       0x4c
3821 #define SQ_V_CVT_NORM_I16_F16                     0x4d
3822 #define SQ_V_CVT_NORM_U16_F16                     0x4e
3823 #define SQ_SRC_SDWA                               0xf9
3824 #define SQ_V_OPC_OFFSET                           0x0
3825 #define SQ_V_OP2_OFFSET                           0x100
3826 #define SQ_V_OP1_OFFSET                           0x140
3827 #define SQ_V_INTRP_OFFSET                         0x270
3828 #define SQ_V_INTERP_P1_F32                        0x0
3829 #define SQ_V_INTERP_P2_F32                        0x1
3830 #define SQ_V_INTERP_MOV_F32                       0x2
3831 #define SQ_S_NOP                                  0x0
3832 #define SQ_S_ENDPGM                               0x1
3833 #define SQ_S_BRANCH                               0x2
3834 #define SQ_S_WAKEUP                               0x3
3835 #define SQ_S_CBRANCH_SCC0                         0x4
3836 #define SQ_S_CBRANCH_SCC1                         0x5
3837 #define SQ_S_CBRANCH_VCCZ                         0x6
3838 #define SQ_S_CBRANCH_VCCNZ                        0x7
3839 #define SQ_S_CBRANCH_EXECZ                        0x8
3840 #define SQ_S_CBRANCH_EXECNZ                       0x9
3841 #define SQ_S_BARRIER                              0xa
3842 #define SQ_S_SETKILL                              0xb
3843 #define SQ_S_WAITCNT                              0xc
3844 #define SQ_S_SETHALT                              0xd
3845 #define SQ_S_SLEEP                                0xe
3846 #define SQ_S_SETPRIO                              0xf
3847 #define SQ_S_SENDMSG                              0x10
3848 #define SQ_S_SENDMSGHALT                          0x11
3849 #define SQ_S_TRAP                                 0x12
3850 #define SQ_S_ICACHE_INV                           0x13
3851 #define SQ_S_INCPERFLEVEL                         0x14
3852 #define SQ_S_DECPERFLEVEL                         0x15
3853 #define SQ_S_TTRACEDATA                           0x16
3854 #define SQ_S_CBRANCH_CDBGSYS                      0x17
3855 #define SQ_S_CBRANCH_CDBGUSER                     0x18
3856 #define SQ_S_CBRANCH_CDBGSYS_OR_USER              0x19
3857 #define SQ_S_CBRANCH_CDBGSYS_AND_USER             0x1a
3858 #define SQ_S_ENDPGM_SAVED                         0x1b
3859 #define SQ_S_SET_GPR_IDX_OFF                      0x1c
3860 #define SQ_S_SET_GPR_IDX_MODE                     0x1d
3861 #define SQ_SRC_DPP                                0xfa
3862 #define SQ_SRC_LITERAL                            0xff
3863 #define SQ_VCC_LO                                 0x6a
3864 #define SQ_VCC_HI                                 0x6b
3865 #define SQ_PARAM_P10                              0x0
3866 #define SQ_PARAM_P20                              0x1
3867 #define SQ_PARAM_P0                               0x2
3868 #define SQ_SRC_LDS_DIRECT                         0xfe
3869 #define SQ_V_CNDMASK_B32                          0x0
3870 #define SQ_V_ADD_F32                              0x1
3871 #define SQ_V_SUB_F32                              0x2
3872 #define SQ_V_SUBREV_F32                           0x3
3873 #define SQ_V_MUL_LEGACY_F32                       0x4
3874 #define SQ_V_MUL_F32                              0x5
3875 #define SQ_V_MUL_I32_I24                          0x6
3876 #define SQ_V_MUL_HI_I32_I24                       0x7
3877 #define SQ_V_MUL_U32_U24                          0x8
3878 #define SQ_V_MUL_HI_U32_U24                       0x9
3879 #define SQ_V_MIN_F32                              0xa
3880 #define SQ_V_MAX_F32                              0xb
3881 #define SQ_V_MIN_I32                              0xc
3882 #define SQ_V_MAX_I32                              0xd
3883 #define SQ_V_MIN_U32                              0xe
3884 #define SQ_V_MAX_U32                              0xf
3885 #define SQ_V_LSHRREV_B32                          0x10
3886 #define SQ_V_ASHRREV_I32                          0x11
3887 #define SQ_V_LSHLREV_B32                          0x12
3888 #define SQ_V_AND_B32                              0x13
3889 #define SQ_V_OR_B32                               0x14
3890 #define SQ_V_XOR_B32                              0x15
3891 #define SQ_V_MAC_F32                              0x16
3892 #define SQ_V_MADMK_F32                            0x17
3893 #define SQ_V_MADAK_F32                            0x18
3894 #define SQ_V_ADD_U32                              0x19
3895 #define SQ_V_SUB_U32                              0x1a
3896 #define SQ_V_SUBREV_U32                           0x1b
3897 #define SQ_V_ADDC_U32                             0x1c
3898 #define SQ_V_SUBB_U32                             0x1d
3899 #define SQ_V_SUBBREV_U32                          0x1e
3900 #define SQ_V_ADD_F16                              0x1f
3901 #define SQ_V_SUB_F16                              0x20
3902 #define SQ_V_SUBREV_F16                           0x21
3903 #define SQ_V_MUL_F16                              0x22
3904 #define SQ_V_MAC_F16                              0x23
3905 #define SQ_V_MADMK_F16                            0x24
3906 #define SQ_V_MADAK_F16                            0x25
3907 #define SQ_V_ADD_U16                              0x26
3908 #define SQ_V_SUB_U16                              0x27
3909 #define SQ_V_SUBREV_U16                           0x28
3910 #define SQ_V_MUL_LO_U16                           0x29
3911 #define SQ_V_LSHLREV_B16                          0x2a
3912 #define SQ_V_LSHRREV_B16                          0x2b
3913 #define SQ_V_ASHRREV_I16                          0x2c
3914 #define SQ_V_MAX_F16                              0x2d
3915 #define SQ_V_MIN_F16                              0x2e
3916 #define SQ_V_MAX_U16                              0x2f
3917 #define SQ_V_MAX_I16                              0x30
3918 #define SQ_V_MIN_U16                              0x31
3919 #define SQ_V_MIN_I16                              0x32
3920 #define SQ_V_LDEXP_F16                            0x33
3921 #define SQ_FLAT_LOAD_UBYTE                        0x10
3922 #define SQ_FLAT_LOAD_SBYTE                        0x11
3923 #define SQ_FLAT_LOAD_USHORT                       0x12
3924 #define SQ_FLAT_LOAD_SSHORT                       0x13
3925 #define SQ_FLAT_LOAD_DWORD                        0x14
3926 #define SQ_FLAT_LOAD_DWORDX2                      0x15
3927 #define SQ_FLAT_LOAD_DWORDX3                      0x16
3928 #define SQ_FLAT_LOAD_DWORDX4                      0x17
3929 #define SQ_FLAT_STORE_BYTE                        0x18
3930 #define SQ_FLAT_STORE_SHORT                       0x1a
3931 #define SQ_FLAT_STORE_DWORD                       0x1c
3932 #define SQ_FLAT_STORE_DWORDX2                     0x1d
3933 #define SQ_FLAT_STORE_DWORDX3                     0x1e
3934 #define SQ_FLAT_STORE_DWORDX4                     0x1f
3935 #define SQ_FLAT_ATOMIC_SWAP                       0x40
3936 #define SQ_FLAT_ATOMIC_CMPSWAP                    0x41
3937 #define SQ_FLAT_ATOMIC_ADD                        0x42
3938 #define SQ_FLAT_ATOMIC_SUB                        0x43
3939 #define SQ_FLAT_ATOMIC_SMIN                       0x44
3940 #define SQ_FLAT_ATOMIC_UMIN                       0x45
3941 #define SQ_FLAT_ATOMIC_SMAX                       0x46
3942 #define SQ_FLAT_ATOMIC_UMAX                       0x47
3943 #define SQ_FLAT_ATOMIC_AND                        0x48
3944 #define SQ_FLAT_ATOMIC_OR                         0x49
3945 #define SQ_FLAT_ATOMIC_XOR                        0x4a
3946 #define SQ_FLAT_ATOMIC_INC                        0x4b
3947 #define SQ_FLAT_ATOMIC_DEC                        0x4c
3948 #define SQ_FLAT_ATOMIC_SWAP_X2                    0x60
3949 #define SQ_FLAT_ATOMIC_CMPSWAP_X2                 0x61
3950 #define SQ_FLAT_ATOMIC_ADD_X2                     0x62
3951 #define SQ_FLAT_ATOMIC_SUB_X2                     0x63
3952 #define SQ_FLAT_ATOMIC_SMIN_X2                    0x64
3953 #define SQ_FLAT_ATOMIC_UMIN_X2                    0x65
3954 #define SQ_FLAT_ATOMIC_SMAX_X2                    0x66
3955 #define SQ_FLAT_ATOMIC_UMAX_X2                    0x67
3956 #define SQ_FLAT_ATOMIC_AND_X2                     0x68
3957 #define SQ_FLAT_ATOMIC_OR_X2                      0x69
3958 #define SQ_FLAT_ATOMIC_XOR_X2                     0x6a
3959 #define SQ_FLAT_ATOMIC_INC_X2                     0x6b
3960 #define SQ_FLAT_ATOMIC_DEC_X2                     0x6c
3961 #define SQ_S_CMP_EQ_I32                           0x0
3962 #define SQ_S_CMP_LG_I32                           0x1
3963 #define SQ_S_CMP_GT_I32                           0x2
3964 #define SQ_S_CMP_GE_I32                           0x3
3965 #define SQ_S_CMP_LT_I32                           0x4
3966 #define SQ_S_CMP_LE_I32                           0x5
3967 #define SQ_S_CMP_EQ_U32                           0x6
3968 #define SQ_S_CMP_LG_U32                           0x7
3969 #define SQ_S_CMP_GT_U32                           0x8
3970 #define SQ_S_CMP_GE_U32                           0x9
3971 #define SQ_S_CMP_LT_U32                           0xa
3972 #define SQ_S_CMP_LE_U32                           0xb
3973 #define SQ_S_BITCMP0_B32                          0xc
3974 #define SQ_S_BITCMP1_B32                          0xd
3975 #define SQ_S_BITCMP0_B64                          0xe
3976 #define SQ_S_BITCMP1_B64                          0xf
3977 #define SQ_S_SETVSKIP                             0x10
3978 #define SQ_S_SET_GPR_IDX_ON                       0x11
3979 #define SQ_S_CMP_EQ_U64                           0x12
3980 #define SQ_S_CMP_LG_U64                           0x13
3981 #define SQ_M0                                     0x7c
3982 #define SQ_V_MAD_LEGACY_F32                       0x1c0
3983 #define SQ_V_MAD_F32                              0x1c1
3984 #define SQ_V_MAD_I32_I24                          0x1c2
3985 #define SQ_V_MAD_U32_U24                          0x1c3
3986 #define SQ_V_CUBEID_F32                           0x1c4
3987 #define SQ_V_CUBESC_F32                           0x1c5
3988 #define SQ_V_CUBETC_F32                           0x1c6
3989 #define SQ_V_CUBEMA_F32                           0x1c7
3990 #define SQ_V_BFE_U32                              0x1c8
3991 #define SQ_V_BFE_I32                              0x1c9
3992 #define SQ_V_BFI_B32                              0x1ca
3993 #define SQ_V_FMA_F32                              0x1cb
3994 #define SQ_V_FMA_F64                              0x1cc
3995 #define SQ_V_LERP_U8                              0x1cd
3996 #define SQ_V_ALIGNBIT_B32                         0x1ce
3997 #define SQ_V_ALIGNBYTE_B32                        0x1cf
3998 #define SQ_V_MIN3_F32                             0x1d0
3999 #define SQ_V_MIN3_I32                             0x1d1
4000 #define SQ_V_MIN3_U32                             0x1d2
4001 #define SQ_V_MAX3_F32                             0x1d3
4002 #define SQ_V_MAX3_I32                             0x1d4
4003 #define SQ_V_MAX3_U32                             0x1d5
4004 #define SQ_V_MED3_F32                             0x1d6
4005 #define SQ_V_MED3_I32                             0x1d7
4006 #define SQ_V_MED3_U32                             0x1d8
4007 #define SQ_V_SAD_U8                               0x1d9
4008 #define SQ_V_SAD_HI_U8                            0x1da
4009 #define SQ_V_SAD_U16                              0x1db
4010 #define SQ_V_SAD_U32                              0x1dc
4011 #define SQ_V_CVT_PK_U8_F32                        0x1dd
4012 #define SQ_V_DIV_FIXUP_F32                        0x1de
4013 #define SQ_V_DIV_FIXUP_F64                        0x1df
4014 #define SQ_V_DIV_SCALE_F32                        0x1e0
4015 #define SQ_V_DIV_SCALE_F64                        0x1e1
4016 #define SQ_V_DIV_FMAS_F32                         0x1e2
4017 #define SQ_V_DIV_FMAS_F64                         0x1e3
4018 #define SQ_V_MSAD_U8                              0x1e4
4019 #define SQ_V_QSAD_PK_U16_U8                       0x1e5
4020 #define SQ_V_MQSAD_PK_U16_U8                      0x1e6
4021 #define SQ_V_MQSAD_U32_U8                         0x1e7
4022 #define SQ_V_MAD_U64_U32                          0x1e8
4023 #define SQ_V_MAD_I64_I32                          0x1e9
4024 #define SQ_V_MAD_F16                              0x1ea
4025 #define SQ_V_MAD_U16                              0x1eb
4026 #define SQ_V_MAD_I16                              0x1ec
4027 #define SQ_V_PERM_B32                             0x1ed
4028 #define SQ_V_FMA_F16                              0x1ee
4029 #define SQ_V_DIV_FIXUP_F16                        0x1ef
4030 #define SQ_V_CVT_PKACCUM_U8_F32                   0x1f0
4031 #define SQ_V_INTERP_P1LL_F16                      0x274
4032 #define SQ_V_INTERP_P1LV_F16                      0x275
4033 #define SQ_V_INTERP_P2_F16                        0x276
4034 #define SQ_V_ADD_F64                              0x280
4035 #define SQ_V_MUL_F64                              0x281
4036 #define SQ_V_MIN_F64                              0x282
4037 #define SQ_V_MAX_F64                              0x283
4038 #define SQ_V_LDEXP_F64                            0x284
4039 #define SQ_V_MUL_LO_U32                           0x285
4040 #define SQ_V_MUL_HI_U32                           0x286
4041 #define SQ_V_MUL_HI_I32                           0x287
4042 #define SQ_V_LDEXP_F32                            0x288
4043 #define SQ_V_READLANE_B32                         0x289
4044 #define SQ_V_WRITELANE_B32                        0x28a
4045 #define SQ_V_BCNT_U32_B32                         0x28b
4046 #define SQ_V_MBCNT_LO_U32_B32                     0x28c
4047 #define SQ_V_MBCNT_HI_U32_B32                     0x28d
4048 #define SQ_V_MAC_LEGACY_F32                       0x28e
4049 #define SQ_V_LSHLREV_B64                          0x28f
4050 #define SQ_V_LSHRREV_B64                          0x290
4051 #define SQ_V_ASHRREV_I64                          0x291
4052 #define SQ_V_TRIG_PREOP_F64                       0x292
4053 #define SQ_V_BFM_B32                              0x293
4054 #define SQ_V_CVT_PKNORM_I16_F32                   0x294
4055 #define SQ_V_CVT_PKNORM_U16_F32                   0x295
4056 #define SQ_V_CVT_PKRTZ_F16_F32                    0x296
4057 #define SQ_V_CVT_PK_U16_U32                       0x297
4058 #define SQ_V_CVT_PK_I16_I32                       0x298
4059 #define SQ_V_CVT_PKNORM_I16_F16                   0x299
4060 #define SQ_V_CVT_PKNORM_U16_F16                   0x29a
4061 #define SQ_VCC_ALL                                0x0
4062 #define SQ_SRC_EXECZ                              0xfc
4063 #define SQ_FLAT_SCRATCH_LO                        0x66
4064 #define SQ_FLAT_SCRATCH_HI                        0x67
4065 #define SQ_SYSMSG_OP_ECC_ERR_INTERRUPT            0x1
4066 #define SQ_SYSMSG_OP_REG_RD                       0x2
4067 #define SQ_SYSMSG_OP_HOST_TRAP_ACK                0x3
4068 #define SQ_SYSMSG_OP_TTRACE_PC                    0x4
4069 #define SQ_HW_REG_MODE                            0x1
4070 #define SQ_HW_REG_STATUS                          0x2
4071 #define SQ_HW_REG_TRAPSTS                         0x3
4072 #define SQ_HW_REG_HW_ID                           0x4
4073 #define SQ_HW_REG_GPR_ALLOC                       0x5
4074 #define SQ_HW_REG_LDS_ALLOC                       0x6
4075 #define SQ_HW_REG_IB_STS                          0x7
4076 #define SQ_HW_REG_PC_LO                           0x8
4077 #define SQ_HW_REG_PC_HI                           0x9
4078 #define SQ_HW_REG_INST_DW0                        0xa
4079 #define SQ_HW_REG_INST_DW1                        0xb
4080 #define SQ_HW_REG_IB_DBG0                         0xc
4081 #define SQ_HW_REG_IB_DBG1                         0xd
4082 #define SQ_DPP_BOUND_OFF                          0x0
4083 #define SQ_DPP_BOUND_ZERO                         0x1
4084 #define SQ_R1                                     0x1
4085 #define SQ_R2                                     0x2
4086 #define SQ_R3                                     0x3
4087 #define SQ_R4                                     0x4
4088 #define SQ_R5                                     0x5
4089 #define SQ_R6                                     0x6
4090 #define SQ_R7                                     0x7
4091 #define SQ_R8                                     0x8
4092 #define SQ_R9                                     0x9
4093 #define SQ_R10                                    0xa
4094 #define SQ_R11                                    0xb
4095 #define SQ_R12                                    0xc
4096 #define SQ_R13                                    0xd
4097 #define SQ_R14                                    0xe
4098 #define SQ_R15                                    0xf
4099 #define SQ_S_ADD_U32                              0x0
4100 #define SQ_S_SUB_U32                              0x1
4101 #define SQ_S_ADD_I32                              0x2
4102 #define SQ_S_SUB_I32                              0x3
4103 #define SQ_S_ADDC_U32                             0x4
4104 #define SQ_S_SUBB_U32                             0x5
4105 #define SQ_S_MIN_I32                              0x6
4106 #define SQ_S_MIN_U32                              0x7
4107 #define SQ_S_MAX_I32                              0x8
4108 #define SQ_S_MAX_U32                              0x9
4109 #define SQ_S_CSELECT_B32                          0xa
4110 #define SQ_S_CSELECT_B64                          0xb
4111 #define SQ_S_AND_B32                              0xc
4112 #define SQ_S_AND_B64                              0xd
4113 #define SQ_S_OR_B32                               0xe
4114 #define SQ_S_OR_B64                               0xf
4115 #define SQ_S_XOR_B32                              0x10
4116 #define SQ_S_XOR_B64                              0x11
4117 #define SQ_S_ANDN2_B32                            0x12
4118 #define SQ_S_ANDN2_B64                            0x13
4119 #define SQ_S_ORN2_B32                             0x14
4120 #define SQ_S_ORN2_B64                             0x15
4121 #define SQ_S_NAND_B32                             0x16
4122 #define SQ_S_NAND_B64                             0x17
4123 #define SQ_S_NOR_B32                              0x18
4124 #define SQ_S_NOR_B64                              0x19
4125 #define SQ_S_XNOR_B32                             0x1a
4126 #define SQ_S_XNOR_B64                             0x1b
4127 #define SQ_S_LSHL_B32                             0x1c
4128 #define SQ_S_LSHL_B64                             0x1d
4129 #define SQ_S_LSHR_B32                             0x1e
4130 #define SQ_S_LSHR_B64                             0x1f
4131 #define SQ_S_ASHR_I32                             0x20
4132 #define SQ_S_ASHR_I64                             0x21
4133 #define SQ_S_BFM_B32                              0x22
4134 #define SQ_S_BFM_B64                              0x23
4135 #define SQ_S_MUL_I32                              0x24
4136 #define SQ_S_BFE_U32                              0x25
4137 #define SQ_S_BFE_I32                              0x26
4138 #define SQ_S_BFE_U64                              0x27
4139 #define SQ_S_BFE_I64                              0x28
4140 #define SQ_S_CBRANCH_G_FORK                       0x29
4141 #define SQ_S_ABSDIFF_I32                          0x2a
4142 #define SQ_S_RFE_RESTORE_B64                      0x2b
4143 #define SQ_MSG_INTERRUPT                          0x1
4144 #define SQ_MSG_GS                                 0x2
4145 #define SQ_MSG_GS_DONE                            0x3
4146 #define SQ_MSG_SAVEWAVE                           0x4
4147 #define SQ_MSG_SYSMSG                             0xf
4148 typedef enum SX_BLEND_OPT {
4149         BLEND_OPT_PRESERVE_NONE_IGNORE_ALL               = 0x0,
4150         BLEND_OPT_PRESERVE_ALL_IGNORE_NONE               = 0x1,
4151         BLEND_OPT_PRESERVE_C1_IGNORE_C0                  = 0x2,
4152         BLEND_OPT_PRESERVE_C0_IGNORE_C1                  = 0x3,
4153         BLEND_OPT_PRESERVE_A1_IGNORE_A0                  = 0x4,
4154         BLEND_OPT_PRESERVE_A0_IGNORE_A1                  = 0x5,
4155         BLEND_OPT_PRESERVE_NONE_IGNORE_A0                = 0x6,
4156         BLEND_OPT_PRESERVE_NONE_IGNORE_NONE              = 0x7,
4157 } SX_BLEND_OPT;
4158 typedef enum SX_OPT_COMB_FCN {
4159         OPT_COMB_NONE                                    = 0x0,
4160         OPT_COMB_ADD                                     = 0x1,
4161         OPT_COMB_SUBTRACT                                = 0x2,
4162         OPT_COMB_MIN                                     = 0x3,
4163         OPT_COMB_MAX                                     = 0x4,
4164         OPT_COMB_REVSUBTRACT                             = 0x5,
4165         OPT_COMB_BLEND_DISABLED                          = 0x6,
4166         OPT_COMB_SAFE_ADD                                = 0x7,
4167 } SX_OPT_COMB_FCN;
4168 typedef enum SX_DOWNCONVERT_FORMAT {
4169         SX_RT_EXPORT_NO_CONVERSION                       = 0x0,
4170         SX_RT_EXPORT_32_R                                = 0x1,
4171         SX_RT_EXPORT_32_A                                = 0x2,
4172         SX_RT_EXPORT_10_11_11                            = 0x3,
4173         SX_RT_EXPORT_2_10_10_10                          = 0x4,
4174         SX_RT_EXPORT_8_8_8_8                             = 0x5,
4175         SX_RT_EXPORT_5_6_5                               = 0x6,
4176         SX_RT_EXPORT_1_5_5_5                             = 0x7,
4177         SX_RT_EXPORT_4_4_4_4                             = 0x8,
4178         SX_RT_EXPORT_16_16_GR                            = 0x9,
4179         SX_RT_EXPORT_16_16_AR                            = 0xa,
4180 } SX_DOWNCONVERT_FORMAT;
4181 typedef enum TEX_BORDER_COLOR_TYPE {
4182         TEX_BorderColor_TransparentBlack                 = 0x0,
4183         TEX_BorderColor_OpaqueBlack                      = 0x1,
4184         TEX_BorderColor_OpaqueWhite                      = 0x2,
4185         TEX_BorderColor_Register                         = 0x3,
4186 } TEX_BORDER_COLOR_TYPE;
4187 typedef enum TEX_CHROMA_KEY {
4188         TEX_ChromaKey_Disabled                           = 0x0,
4189         TEX_ChromaKey_Kill                               = 0x1,
4190         TEX_ChromaKey_Blend                              = 0x2,
4191         TEX_ChromaKey_RESERVED_3                         = 0x3,
4192 } TEX_CHROMA_KEY;
4193 typedef enum TEX_CLAMP {
4194         TEX_Clamp_Repeat                                 = 0x0,
4195         TEX_Clamp_Mirror                                 = 0x1,
4196         TEX_Clamp_ClampToLast                            = 0x2,
4197         TEX_Clamp_MirrorOnceToLast                       = 0x3,
4198         TEX_Clamp_ClampHalfToBorder                      = 0x4,
4199         TEX_Clamp_MirrorOnceHalfToBorder                 = 0x5,
4200         TEX_Clamp_ClampToBorder                          = 0x6,
4201         TEX_Clamp_MirrorOnceToBorder                     = 0x7,
4202 } TEX_CLAMP;
4203 typedef enum TEX_COORD_TYPE {
4204         TEX_CoordType_Unnormalized                       = 0x0,
4205         TEX_CoordType_Normalized                         = 0x1,
4206 } TEX_COORD_TYPE;
4207 typedef enum TEX_DEPTH_COMPARE_FUNCTION {
4208         TEX_DepthCompareFunction_Never                   = 0x0,
4209         TEX_DepthCompareFunction_Less                    = 0x1,
4210         TEX_DepthCompareFunction_Equal                   = 0x2,
4211         TEX_DepthCompareFunction_LessEqual               = 0x3,
4212         TEX_DepthCompareFunction_Greater                 = 0x4,
4213         TEX_DepthCompareFunction_NotEqual                = 0x5,
4214         TEX_DepthCompareFunction_GreaterEqual            = 0x6,
4215         TEX_DepthCompareFunction_Always                  = 0x7,
4216 } TEX_DEPTH_COMPARE_FUNCTION;
4217 typedef enum TEX_DIM {
4218         TEX_Dim_1D                                       = 0x0,
4219         TEX_Dim_2D                                       = 0x1,
4220         TEX_Dim_3D                                       = 0x2,
4221         TEX_Dim_CubeMap                                  = 0x3,
4222         TEX_Dim_1DArray                                  = 0x4,
4223         TEX_Dim_2DArray                                  = 0x5,
4224         TEX_Dim_2D_MSAA                                  = 0x6,
4225         TEX_Dim_2DArray_MSAA                             = 0x7,
4226 } TEX_DIM;
4227 typedef enum TEX_FORMAT_COMP {
4228         TEX_FormatComp_Unsigned                          = 0x0,
4229         TEX_FormatComp_Signed                            = 0x1,
4230         TEX_FormatComp_UnsignedBiased                    = 0x2,
4231         TEX_FormatComp_RESERVED_3                        = 0x3,
4232 } TEX_FORMAT_COMP;
4233 typedef enum TEX_MAX_ANISO_RATIO {
4234         TEX_MaxAnisoRatio_1to1                           = 0x0,
4235         TEX_MaxAnisoRatio_2to1                           = 0x1,
4236         TEX_MaxAnisoRatio_4to1                           = 0x2,
4237         TEX_MaxAnisoRatio_8to1                           = 0x3,
4238         TEX_MaxAnisoRatio_16to1                          = 0x4,
4239         TEX_MaxAnisoRatio_RESERVED_5                     = 0x5,
4240         TEX_MaxAnisoRatio_RESERVED_6                     = 0x6,
4241         TEX_MaxAnisoRatio_RESERVED_7                     = 0x7,
4242 } TEX_MAX_ANISO_RATIO;
4243 typedef enum TEX_MIP_FILTER {
4244         TEX_MipFilter_None                               = 0x0,
4245         TEX_MipFilter_Point                              = 0x1,
4246         TEX_MipFilter_Linear                             = 0x2,
4247         TEX_MipFilter_Point_Aniso_Adj                    = 0x3,
4248 } TEX_MIP_FILTER;
4249 typedef enum TEX_REQUEST_SIZE {
4250         TEX_RequestSize_32B                              = 0x0,
4251         TEX_RequestSize_64B                              = 0x1,
4252         TEX_RequestSize_128B                             = 0x2,
4253         TEX_RequestSize_2X64B                            = 0x3,
4254 } TEX_REQUEST_SIZE;
4255 typedef enum TEX_SAMPLER_TYPE {
4256         TEX_SamplerType_Invalid                          = 0x0,
4257         TEX_SamplerType_Valid                            = 0x1,
4258 } TEX_SAMPLER_TYPE;
4259 typedef enum TEX_XY_FILTER {
4260         TEX_XYFilter_Point                               = 0x0,
4261         TEX_XYFilter_Linear                              = 0x1,
4262         TEX_XYFilter_AnisoPoint                          = 0x2,
4263         TEX_XYFilter_AnisoLinear                         = 0x3,
4264 } TEX_XY_FILTER;
4265 typedef enum TEX_Z_FILTER {
4266         TEX_ZFilter_None                                 = 0x0,
4267         TEX_ZFilter_Point                                = 0x1,
4268         TEX_ZFilter_Linear                               = 0x2,
4269         TEX_ZFilter_RESERVED_3                           = 0x3,
4270 } TEX_Z_FILTER;
4271 typedef enum VTX_CLAMP {
4272         VTX_Clamp_ClampToZero                            = 0x0,
4273         VTX_Clamp_ClampToNAN                             = 0x1,
4274 } VTX_CLAMP;
4275 typedef enum VTX_FETCH_TYPE {
4276         VTX_FetchType_VertexData                         = 0x0,
4277         VTX_FetchType_InstanceData                       = 0x1,
4278         VTX_FetchType_NoIndexOffset                      = 0x2,
4279         VTX_FetchType_RESERVED_3                         = 0x3,
4280 } VTX_FETCH_TYPE;
4281 typedef enum VTX_FORMAT_COMP_ALL {
4282         VTX_FormatCompAll_Unsigned                       = 0x0,
4283         VTX_FormatCompAll_Signed                         = 0x1,
4284 } VTX_FORMAT_COMP_ALL;
4285 typedef enum VTX_MEM_REQUEST_SIZE {
4286         VTX_MemRequestSize_32B                           = 0x0,
4287         VTX_MemRequestSize_64B                           = 0x1,
4288 } VTX_MEM_REQUEST_SIZE;
4289 typedef enum TVX_DATA_FORMAT {
4290         TVX_FMT_INVALID                                  = 0x0,
4291         TVX_FMT_8                                        = 0x1,
4292         TVX_FMT_4_4                                      = 0x2,
4293         TVX_FMT_3_3_2                                    = 0x3,
4294         TVX_FMT_RESERVED_4                               = 0x4,
4295         TVX_FMT_16                                       = 0x5,
4296         TVX_FMT_16_FLOAT                                 = 0x6,
4297         TVX_FMT_8_8                                      = 0x7,
4298         TVX_FMT_5_6_5                                    = 0x8,
4299         TVX_FMT_6_5_5                                    = 0x9,
4300         TVX_FMT_1_5_5_5                                  = 0xa,
4301         TVX_FMT_4_4_4_4                                  = 0xb,
4302         TVX_FMT_5_5_5_1                                  = 0xc,
4303         TVX_FMT_32                                       = 0xd,
4304         TVX_FMT_32_FLOAT                                 = 0xe,
4305         TVX_FMT_16_16                                    = 0xf,
4306         TVX_FMT_16_16_FLOAT                              = 0x10,
4307         TVX_FMT_8_24                                     = 0x11,
4308         TVX_FMT_8_24_FLOAT                               = 0x12,
4309         TVX_FMT_24_8                                     = 0x13,
4310         TVX_FMT_24_8_FLOAT                               = 0x14,
4311         TVX_FMT_10_11_11                                 = 0x15,
4312         TVX_FMT_10_11_11_FLOAT                           = 0x16,
4313         TVX_FMT_11_11_10                                 = 0x17,
4314         TVX_FMT_11_11_10_FLOAT                           = 0x18,
4315         TVX_FMT_2_10_10_10                               = 0x19,
4316         TVX_FMT_8_8_8_8                                  = 0x1a,
4317         TVX_FMT_10_10_10_2                               = 0x1b,
4318         TVX_FMT_X24_8_32_FLOAT                           = 0x1c,
4319         TVX_FMT_32_32                                    = 0x1d,
4320         TVX_FMT_32_32_FLOAT                              = 0x1e,
4321         TVX_FMT_16_16_16_16                              = 0x1f,
4322         TVX_FMT_16_16_16_16_FLOAT                        = 0x20,
4323         TVX_FMT_RESERVED_33                              = 0x21,
4324         TVX_FMT_32_32_32_32                              = 0x22,
4325         TVX_FMT_32_32_32_32_FLOAT                        = 0x23,
4326         TVX_FMT_RESERVED_36                              = 0x24,
4327         TVX_FMT_1                                        = 0x25,
4328         TVX_FMT_1_REVERSED                               = 0x26,
4329         TVX_FMT_GB_GR                                    = 0x27,
4330         TVX_FMT_BG_RG                                    = 0x28,
4331         TVX_FMT_32_AS_8                                  = 0x29,
4332         TVX_FMT_32_AS_8_8                                = 0x2a,
4333         TVX_FMT_5_9_9_9_SHAREDEXP                        = 0x2b,
4334         TVX_FMT_8_8_8                                    = 0x2c,
4335         TVX_FMT_16_16_16                                 = 0x2d,
4336         TVX_FMT_16_16_16_FLOAT                           = 0x2e,
4337         TVX_FMT_32_32_32                                 = 0x2f,
4338         TVX_FMT_32_32_32_FLOAT                           = 0x30,
4339         TVX_FMT_BC1                                      = 0x31,
4340         TVX_FMT_BC2                                      = 0x32,
4341         TVX_FMT_BC3                                      = 0x33,
4342         TVX_FMT_BC4                                      = 0x34,
4343         TVX_FMT_BC5                                      = 0x35,
4344         TVX_FMT_APC0                                     = 0x36,
4345         TVX_FMT_APC1                                     = 0x37,
4346         TVX_FMT_APC2                                     = 0x38,
4347         TVX_FMT_APC3                                     = 0x39,
4348         TVX_FMT_APC4                                     = 0x3a,
4349         TVX_FMT_APC5                                     = 0x3b,
4350         TVX_FMT_APC6                                     = 0x3c,
4351         TVX_FMT_APC7                                     = 0x3d,
4352         TVX_FMT_CTX1                                     = 0x3e,
4353         TVX_FMT_RESERVED_63                              = 0x3f,
4354 } TVX_DATA_FORMAT;
4355 typedef enum TVX_DST_SEL {
4356         TVX_DstSel_X                                     = 0x0,
4357         TVX_DstSel_Y                                     = 0x1,
4358         TVX_DstSel_Z                                     = 0x2,
4359         TVX_DstSel_W                                     = 0x3,
4360         TVX_DstSel_0f                                    = 0x4,
4361         TVX_DstSel_1f                                    = 0x5,
4362         TVX_DstSel_RESERVED_6                            = 0x6,
4363         TVX_DstSel_Mask                                  = 0x7,
4364 } TVX_DST_SEL;
4365 typedef enum TVX_ENDIAN_SWAP {
4366         TVX_EndianSwap_None                              = 0x0,
4367         TVX_EndianSwap_8in16                             = 0x1,
4368         TVX_EndianSwap_8in32                             = 0x2,
4369         TVX_EndianSwap_8in64                             = 0x3,
4370 } TVX_ENDIAN_SWAP;
4371 typedef enum TVX_INST {
4372         TVX_Inst_NormalVertexFetch                       = 0x0,
4373         TVX_Inst_SemanticVertexFetch                     = 0x1,
4374         TVX_Inst_RESERVED_2                              = 0x2,
4375         TVX_Inst_LD                                      = 0x3,
4376         TVX_Inst_GetTextureResInfo                       = 0x4,
4377         TVX_Inst_GetNumberOfSamples                      = 0x5,
4378         TVX_Inst_GetLOD                                  = 0x6,
4379         TVX_Inst_GetGradientsH                           = 0x7,
4380         TVX_Inst_GetGradientsV                           = 0x8,
4381         TVX_Inst_SetTextureOffsets                       = 0x9,
4382         TVX_Inst_KeepGradients                           = 0xa,
4383         TVX_Inst_SetGradientsH                           = 0xb,
4384         TVX_Inst_SetGradientsV                           = 0xc,
4385         TVX_Inst_Pass                                    = 0xd,
4386         TVX_Inst_GetBufferResInfo                        = 0xe,
4387         TVX_Inst_RESERVED_15                             = 0xf,
4388         TVX_Inst_Sample                                  = 0x10,
4389         TVX_Inst_Sample_L                                = 0x11,
4390         TVX_Inst_Sample_LB                               = 0x12,
4391         TVX_Inst_Sample_LZ                               = 0x13,
4392         TVX_Inst_Sample_G                                = 0x14,
4393         TVX_Inst_Gather4                                 = 0x15,
4394         TVX_Inst_Sample_G_LB                             = 0x16,
4395         TVX_Inst_Gather4_O                               = 0x17,
4396         TVX_Inst_Sample_C                                = 0x18,
4397         TVX_Inst_Sample_C_L                              = 0x19,
4398         TVX_Inst_Sample_C_LB                             = 0x1a,
4399         TVX_Inst_Sample_C_LZ                             = 0x1b,
4400         TVX_Inst_Sample_C_G                              = 0x1c,
4401         TVX_Inst_Gather4_C                               = 0x1d,
4402         TVX_Inst_Sample_C_G_LB                           = 0x1e,
4403         TVX_Inst_Gather4_C_O                             = 0x1f,
4404 } TVX_INST;
4405 typedef enum TVX_NUM_FORMAT_ALL {
4406         TVX_NumFormatAll_Norm                            = 0x0,
4407         TVX_NumFormatAll_Int                             = 0x1,
4408         TVX_NumFormatAll_Scaled                          = 0x2,
4409         TVX_NumFormatAll_RESERVED_3                      = 0x3,
4410 } TVX_NUM_FORMAT_ALL;
4411 typedef enum TVX_SRC_SEL {
4412         TVX_SrcSel_X                                     = 0x0,
4413         TVX_SrcSel_Y                                     = 0x1,
4414         TVX_SrcSel_Z                                     = 0x2,
4415         TVX_SrcSel_W                                     = 0x3,
4416         TVX_SrcSel_0f                                    = 0x4,
4417         TVX_SrcSel_1f                                    = 0x5,
4418 } TVX_SRC_SEL;
4419 typedef enum TVX_SRF_MODE_ALL {
4420         TVX_SRFModeAll_ZCMO                              = 0x0,
4421         TVX_SRFModeAll_NZ                                = 0x1,
4422 } TVX_SRF_MODE_ALL;
4423 typedef enum TVX_TYPE {
4424         TVX_Type_InvalidTextureResource                  = 0x0,
4425         TVX_Type_InvalidVertexBuffer                     = 0x1,
4426         TVX_Type_ValidTextureResource                    = 0x2,
4427         TVX_Type_ValidVertexBuffer                       = 0x3,
4428 } TVX_TYPE;
4429 typedef enum TC_OP_MASKS {
4430         TC_OP_MASK_FLUSH_DENROM                          = 0x8,
4431         TC_OP_MASK_64                                    = 0x20,
4432         TC_OP_MASK_NO_RTN                                = 0x40,
4433 } TC_OP_MASKS;
4434 typedef enum TC_OP {
4435         TC_OP_READ                                       = 0x0,
4436         TC_OP_ATOMIC_FCMPSWAP_RTN_32                     = 0x1,
4437         TC_OP_ATOMIC_FMIN_RTN_32                         = 0x2,
4438         TC_OP_ATOMIC_FMAX_RTN_32                         = 0x3,
4439         TC_OP_RESERVED_FOP_RTN_32_0                      = 0x4,
4440         TC_OP_RESERVED_FOP_RTN_32_1                      = 0x5,
4441         TC_OP_RESERVED_FOP_RTN_32_2                      = 0x6,
4442         TC_OP_ATOMIC_SWAP_RTN_32                         = 0x7,
4443         TC_OP_ATOMIC_CMPSWAP_RTN_32                      = 0x8,
4444         TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32        = 0x9,
4445         TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32            = 0xa,
4446         TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32            = 0xb,
4447         TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_0         = 0xc,
4448         TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1         = 0xd,
4449         TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2         = 0xe,
4450         TC_OP_ATOMIC_ADD_RTN_32                          = 0xf,
4451         TC_OP_ATOMIC_SUB_RTN_32                          = 0x10,
4452         TC_OP_ATOMIC_SMIN_RTN_32                         = 0x11,
4453         TC_OP_ATOMIC_UMIN_RTN_32                         = 0x12,
4454         TC_OP_ATOMIC_SMAX_RTN_32                         = 0x13,
4455         TC_OP_ATOMIC_UMAX_RTN_32                         = 0x14,
4456         TC_OP_ATOMIC_AND_RTN_32                          = 0x15,
4457         TC_OP_ATOMIC_OR_RTN_32                           = 0x16,
4458         TC_OP_ATOMIC_XOR_RTN_32                          = 0x17,
4459         TC_OP_ATOMIC_INC_RTN_32                          = 0x18,
4460         TC_OP_ATOMIC_DEC_RTN_32                          = 0x19,
4461         TC_OP_WBINVL1_VOL                                = 0x1a,
4462         TC_OP_WBINVL1_SD                                 = 0x1b,
4463         TC_OP_RESERVED_NON_FLOAT_RTN_32_0                = 0x1c,
4464         TC_OP_RESERVED_NON_FLOAT_RTN_32_1                = 0x1d,
4465         TC_OP_RESERVED_NON_FLOAT_RTN_32_2                = 0x1e,
4466         TC_OP_RESERVED_NON_FLOAT_RTN_32_3                = 0x1f,
4467         TC_OP_WRITE                                      = 0x20,
4468         TC_OP_ATOMIC_FCMPSWAP_RTN_64                     = 0x21,
4469         TC_OP_ATOMIC_FMIN_RTN_64                         = 0x22,
4470         TC_OP_ATOMIC_FMAX_RTN_64                         = 0x23,
4471         TC_OP_RESERVED_FOP_RTN_64_0                      = 0x24,
4472         TC_OP_RESERVED_FOP_RTN_64_1                      = 0x25,
4473         TC_OP_RESERVED_FOP_RTN_64_2                      = 0x26,
4474         TC_OP_ATOMIC_SWAP_RTN_64                         = 0x27,
4475         TC_OP_ATOMIC_CMPSWAP_RTN_64                      = 0x28,
4476         TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64        = 0x29,
4477         TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64            = 0x2a,
4478         TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64            = 0x2b,
4479         TC_OP_WBINVL2_SD                                 = 0x2c,
4480         TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0         = 0x2d,
4481         TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1         = 0x2e,
4482         TC_OP_ATOMIC_ADD_RTN_64                          = 0x2f,
4483         TC_OP_ATOMIC_SUB_RTN_64                          = 0x30,
4484         TC_OP_ATOMIC_SMIN_RTN_64                         = 0x31,
4485         TC_OP_ATOMIC_UMIN_RTN_64                         = 0x32,
4486         TC_OP_ATOMIC_SMAX_RTN_64                         = 0x33,
4487         TC_OP_ATOMIC_UMAX_RTN_64                         = 0x34,
4488         TC_OP_ATOMIC_AND_RTN_64                          = 0x35,
4489         TC_OP_ATOMIC_OR_RTN_64                           = 0x36,
4490         TC_OP_ATOMIC_XOR_RTN_64                          = 0x37,
4491         TC_OP_ATOMIC_INC_RTN_64                          = 0x38,
4492         TC_OP_ATOMIC_DEC_RTN_64                          = 0x39,
4493         TC_OP_WBL2_NC                                    = 0x3a,
4494         TC_OP_RESERVED_NON_FLOAT_RTN_64_0                = 0x3b,
4495         TC_OP_RESERVED_NON_FLOAT_RTN_64_1                = 0x3c,
4496         TC_OP_RESERVED_NON_FLOAT_RTN_64_2                = 0x3d,
4497         TC_OP_RESERVED_NON_FLOAT_RTN_64_3                = 0x3e,
4498         TC_OP_RESERVED_NON_FLOAT_RTN_64_4                = 0x3f,
4499         TC_OP_WBINVL1                                    = 0x40,
4500         TC_OP_ATOMIC_FCMPSWAP_32                         = 0x41,
4501         TC_OP_ATOMIC_FMIN_32                             = 0x42,
4502         TC_OP_ATOMIC_FMAX_32                             = 0x43,
4503         TC_OP_RESERVED_FOP_32_0                          = 0x44,
4504         TC_OP_RESERVED_FOP_32_1                          = 0x45,
4505         TC_OP_RESERVED_FOP_32_2                          = 0x46,
4506         TC_OP_ATOMIC_SWAP_32                             = 0x47,
4507         TC_OP_ATOMIC_CMPSWAP_32                          = 0x48,
4508         TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32            = 0x49,
4509         TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32                = 0x4a,
4510         TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32                = 0x4b,
4511         TC_OP_RESERVED_FOP_FLUSH_DENORM_32_0             = 0x4c,
4512         TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1             = 0x4d,
4513         TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2             = 0x4e,
4514         TC_OP_ATOMIC_ADD_32                              = 0x4f,
4515         TC_OP_ATOMIC_SUB_32                              = 0x50,
4516         TC_OP_ATOMIC_SMIN_32                             = 0x51,
4517         TC_OP_ATOMIC_UMIN_32                             = 0x52,
4518         TC_OP_ATOMIC_SMAX_32                             = 0x53,
4519         TC_OP_ATOMIC_UMAX_32                             = 0x54,
4520         TC_OP_ATOMIC_AND_32                              = 0x55,
4521         TC_OP_ATOMIC_OR_32                               = 0x56,
4522         TC_OP_ATOMIC_XOR_32                              = 0x57,
4523         TC_OP_ATOMIC_INC_32                              = 0x58,
4524         TC_OP_ATOMIC_DEC_32                              = 0x59,
4525         TC_OP_INVL2_NC                                   = 0x5a,
4526         TC_OP_RESERVED_NON_FLOAT_32_0                    = 0x5b,
4527         TC_OP_RESERVED_NON_FLOAT_32_1                    = 0x5c,
4528         TC_OP_RESERVED_NON_FLOAT_32_2                    = 0x5d,
4529         TC_OP_RESERVED_NON_FLOAT_32_3                    = 0x5e,
4530         TC_OP_RESERVED_NON_FLOAT_32_4                    = 0x5f,
4531         TC_OP_WBINVL2                                    = 0x60,
4532         TC_OP_ATOMIC_FCMPSWAP_64                         = 0x61,
4533         TC_OP_ATOMIC_FMIN_64                             = 0x62,
4534         TC_OP_ATOMIC_FMAX_64                             = 0x63,
4535         TC_OP_RESERVED_FOP_64_0                          = 0x64,
4536         TC_OP_RESERVED_FOP_64_1                          = 0x65,
4537         TC_OP_RESERVED_FOP_64_2                          = 0x66,
4538         TC_OP_ATOMIC_SWAP_64                             = 0x67,
4539         TC_OP_ATOMIC_CMPSWAP_64                          = 0x68,
4540         TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64            = 0x69,
4541         TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64                = 0x6a,
4542         TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64                = 0x6b,
4543         TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0             = 0x6c,
4544         TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1             = 0x6d,
4545         TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2             = 0x6e,
4546         TC_OP_ATOMIC_ADD_64                              = 0x6f,
4547         TC_OP_ATOMIC_SUB_64                              = 0x70,
4548         TC_OP_ATOMIC_SMIN_64                             = 0x71,
4549         TC_OP_ATOMIC_UMIN_64                             = 0x72,
4550         TC_OP_ATOMIC_SMAX_64                             = 0x73,
4551         TC_OP_ATOMIC_UMAX_64                             = 0x74,
4552         TC_OP_ATOMIC_AND_64                              = 0x75,
4553         TC_OP_ATOMIC_OR_64                               = 0x76,
4554         TC_OP_ATOMIC_XOR_64                              = 0x77,
4555         TC_OP_ATOMIC_INC_64                              = 0x78,
4556         TC_OP_ATOMIC_DEC_64                              = 0x79,
4557         TC_OP_WBINVL2_NC                                 = 0x7a,
4558         TC_OP_RESERVED_NON_FLOAT_64_0                    = 0x7b,
4559         TC_OP_RESERVED_NON_FLOAT_64_1                    = 0x7c,
4560         TC_OP_RESERVED_NON_FLOAT_64_2                    = 0x7d,
4561         TC_OP_RESERVED_NON_FLOAT_64_3                    = 0x7e,
4562         TC_OP_RESERVED_NON_FLOAT_64_4                    = 0x7f,
4563 } TC_OP;
4564 typedef enum TC_CHUB_REQ_CREDITS_ENUM {
4565         TC_CHUB_REQ_CREDITS                              = 0x10,
4566 } TC_CHUB_REQ_CREDITS_ENUM;
4567 typedef enum CHUB_TC_RET_CREDITS_ENUM {
4568         CHUB_TC_RET_CREDITS                              = 0x20,
4569 } CHUB_TC_RET_CREDITS_ENUM;
4570 typedef enum TC_NACKS {
4571         TC_NACK_NO_FAULT                                 = 0x0,
4572         TC_NACK_PAGE_FAULT                               = 0x1,
4573         TC_NACK_PROTECTION_FAULT                         = 0x2,
4574         TC_NACK_DATA_ERROR                               = 0x3,
4575 } TC_NACKS;
4576 typedef enum TCC_PERF_SEL {
4577         TCC_PERF_SEL_NONE                                = 0x0,
4578         TCC_PERF_SEL_CYCLE                               = 0x1,
4579         TCC_PERF_SEL_BUSY                                = 0x2,
4580         TCC_PERF_SEL_REQ                                 = 0x3,
4581         TCC_PERF_SEL_STREAMING_REQ                       = 0x4,
4582         TCC_PERF_SEL_EXE_REQ                             = 0x5,
4583         TCC_PERF_SEL_COMPRESSED_REQ                      = 0x6,
4584         TCC_PERF_SEL_COMPRESSED_0_REQ                    = 0x7,
4585         TCC_PERF_SEL_METADATA_REQ                        = 0x8,
4586         TCC_PERF_SEL_NC_VIRTUAL_REQ                      = 0x9,
4587         TCC_PERF_SEL_NC_PHYSICAL_REQ                     = 0xa,
4588         TCC_PERF_SEL_UC_VIRTUAL_REQ                      = 0xb,
4589         TCC_PERF_SEL_UC_PHYSICAL_REQ                     = 0xc,
4590         TCC_PERF_SEL_CC_PHYSICAL_REQ                     = 0xd,
4591         TCC_PERF_SEL_PROBE                               = 0xe,
4592         TCC_PERF_SEL_READ                                = 0xf,
4593         TCC_PERF_SEL_WRITE                               = 0x10,
4594         TCC_PERF_SEL_ATOMIC                              = 0x11,
4595         TCC_PERF_SEL_HIT                                 = 0x12,
4596         TCC_PERF_SEL_MISS                                = 0x13,
4597         TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT                = 0x14,
4598         TCC_PERF_SEL_FULLY_WRITTEN_HIT                   = 0x15,
4599         TCC_PERF_SEL_WRITEBACK                           = 0x16,
4600         TCC_PERF_SEL_LATENCY_FIFO_FULL                   = 0x17,
4601         TCC_PERF_SEL_SRC_FIFO_FULL                       = 0x18,
4602         TCC_PERF_SEL_HOLE_FIFO_FULL                      = 0x19,
4603         TCC_PERF_SEL_MC_WRREQ                            = 0x1a,
4604         TCC_PERF_SEL_MC_WRREQ_UNCACHED                   = 0x1b,
4605         TCC_PERF_SEL_MC_WRREQ_STALL                      = 0x1c,
4606         TCC_PERF_SEL_MC_WRREQ_CREDIT_STALL               = 0x1d,
4607         TCC_PERF_SEL_MC_WRREQ_MC_HALT_STALL              = 0x1e,
4608         TCC_PERF_SEL_TOO_MANY_MC_WRREQS_STALL            = 0x1f,
4609         TCC_PERF_SEL_MC_WRREQ_LEVEL                      = 0x20,
4610         TCC_PERF_SEL_MC_ATOMIC                           = 0x21,
4611         TCC_PERF_SEL_MC_ATOMIC_LEVEL                     = 0x22,
4612         TCC_PERF_SEL_MC_RDREQ                            = 0x23,
4613         TCC_PERF_SEL_MC_RDREQ_UNCACHED                   = 0x24,
4614         TCC_PERF_SEL_MC_RDREQ_MDC                        = 0x25,
4615         TCC_PERF_SEL_MC_RDREQ_COMPRESSED                 = 0x26,
4616         TCC_PERF_SEL_MC_RDREQ_CREDIT_STALL               = 0x27,
4617         TCC_PERF_SEL_MC_RDREQ_MC_HALT_STALL              = 0x28,
4618         TCC_PERF_SEL_MC_RDREQ_LEVEL                      = 0x29,
4619         TCC_PERF_SEL_TAG_STALL                           = 0x2a,
4620         TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL       = 0x2b,
4621         TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL  = 0x2c,
4622         TCC_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL= 0x2d,
4623         TCC_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL= 0x2e,
4624         TCC_PERF_SEL_TAG_PROBE_STALL                     = 0x2f,
4625         TCC_PERF_SEL_TAG_PROBE_FILTER_STALL              = 0x30,
4626         TCC_PERF_SEL_READ_RETURN_TIMEOUT                 = 0x31,
4627         TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT              = 0x32,
4628         TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE             = 0x33,
4629         TCC_PERF_SEL_BUBBLE                              = 0x34,
4630         TCC_PERF_SEL_RETURN_ACK                          = 0x35,
4631         TCC_PERF_SEL_RETURN_DATA                         = 0x36,
4632         TCC_PERF_SEL_RETURN_HOLE                         = 0x37,
4633         TCC_PERF_SEL_RETURN_ACK_HOLE                     = 0x38,
4634         TCC_PERF_SEL_IB_REQ                              = 0x39,
4635         TCC_PERF_SEL_IB_STALL                            = 0x3a,
4636         TCC_PERF_SEL_IB_TAG_STALL                        = 0x3b,
4637         TCC_PERF_SEL_IB_MDC_STALL                        = 0x3c,
4638         TCC_PERF_SEL_TCA_LEVEL                           = 0x3d,
4639         TCC_PERF_SEL_HOLE_LEVEL                          = 0x3e,
4640         TCC_PERF_SEL_MC_RDRET_NACK                       = 0x3f,
4641         TCC_PERF_SEL_MC_WRRET_NACK                       = 0x40,
4642         TCC_PERF_SEL_NORMAL_WRITEBACK                    = 0x41,
4643         TCC_PERF_SEL_TC_OP_WBL2_NC_WRITEBACK             = 0x42,
4644         TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK             = 0x43,
4645         TCC_PERF_SEL_TC_OP_WBINVL2_NC_WRITEBACK          = 0x44,
4646         TCC_PERF_SEL_TC_OP_WBINVL2_SD_WRITEBACK          = 0x45,
4647         TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK              = 0x46,
4648         TCC_PERF_SEL_NORMAL_EVICT                        = 0x47,
4649         TCC_PERF_SEL_TC_OP_WBL2_NC_EVICT                 = 0x48,
4650         TCC_PERF_SEL_TC_OP_INVL2_NC_EVICT                = 0x49,
4651         TCC_PERF_SEL_TC_OP_WBINVL2_EVICT                 = 0x4a,
4652         TCC_PERF_SEL_TC_OP_WBINVL2_NC_EVICT              = 0x4b,
4653         TCC_PERF_SEL_TC_OP_WBINVL2_SD_EVICT              = 0x4c,
4654         TCC_PERF_SEL_ALL_TC_OP_INV_EVICT                 = 0x4d,
4655         TCC_PERF_SEL_PROBE_EVICT                         = 0x4e,
4656         TCC_PERF_SEL_TC_OP_WBL2_NC_CYCLE                 = 0x4f,
4657         TCC_PERF_SEL_TC_OP_INVL2_NC_CYCLE                = 0x50,
4658         TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE                 = 0x51,
4659         TCC_PERF_SEL_TC_OP_WBINVL2_NC_CYCLE              = 0x52,
4660         TCC_PERF_SEL_TC_OP_WBINVL2_SD_CYCLE              = 0x53,
4661         TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE           = 0x54,
4662         TCC_PERF_SEL_TC_OP_WBL2_NC_START                 = 0x55,
4663         TCC_PERF_SEL_TC_OP_INVL2_NC_START                = 0x56,
4664         TCC_PERF_SEL_TC_OP_WBINVL2_START                 = 0x57,
4665         TCC_PERF_SEL_TC_OP_WBINVL2_NC_START              = 0x58,
4666         TCC_PERF_SEL_TC_OP_WBINVL2_SD_START              = 0x59,
4667         TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START           = 0x5a,
4668         TCC_PERF_SEL_TC_OP_WBL2_NC_FINISH                = 0x5b,
4669         TCC_PERF_SEL_TC_OP_INVL2_NC_FINISH               = 0x5c,
4670         TCC_PERF_SEL_TC_OP_WBINVL2_FINISH                = 0x5d,
4671         TCC_PERF_SEL_TC_OP_WBINVL2_NC_FINISH             = 0x5e,
4672         TCC_PERF_SEL_TC_OP_WBINVL2_SD_FINISH             = 0x5f,
4673         TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH          = 0x60,
4674         TCC_PERF_SEL_MDC_REQ                             = 0x61,
4675         TCC_PERF_SEL_MDC_LEVEL                           = 0x62,
4676         TCC_PERF_SEL_MDC_TAG_HIT                         = 0x63,
4677         TCC_PERF_SEL_MDC_SECTOR_HIT                      = 0x64,
4678         TCC_PERF_SEL_MDC_SECTOR_MISS                     = 0x65,
4679         TCC_PERF_SEL_MDC_TAG_STALL                       = 0x66,
4680         TCC_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL= 0x67,
4681         TCC_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL= 0x68,
4682         TCC_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL= 0x69,
4683         TCC_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION     = 0x6a,
4684         TCC_PERF_SEL_PROBE_FILTER_DISABLED               = 0x6b,
4685         TCC_PERF_SEL_CLIENT0_REQ                         = 0x80,
4686         TCC_PERF_SEL_CLIENT1_REQ                         = 0x81,
4687         TCC_PERF_SEL_CLIENT2_REQ                         = 0x82,
4688         TCC_PERF_SEL_CLIENT3_REQ                         = 0x83,
4689         TCC_PERF_SEL_CLIENT4_REQ                         = 0x84,
4690         TCC_PERF_SEL_CLIENT5_REQ                         = 0x85,
4691         TCC_PERF_SEL_CLIENT6_REQ                         = 0x86,
4692         TCC_PERF_SEL_CLIENT7_REQ                         = 0x87,
4693         TCC_PERF_SEL_CLIENT8_REQ                         = 0x88,
4694         TCC_PERF_SEL_CLIENT9_REQ                         = 0x89,
4695         TCC_PERF_SEL_CLIENT10_REQ                        = 0x8a,
4696         TCC_PERF_SEL_CLIENT11_REQ                        = 0x8b,
4697         TCC_PERF_SEL_CLIENT12_REQ                        = 0x8c,
4698         TCC_PERF_SEL_CLIENT13_REQ                        = 0x8d,
4699         TCC_PERF_SEL_CLIENT14_REQ                        = 0x8e,
4700         TCC_PERF_SEL_CLIENT15_REQ                        = 0x8f,
4701         TCC_PERF_SEL_CLIENT16_REQ                        = 0x90,
4702         TCC_PERF_SEL_CLIENT17_REQ                        = 0x91,
4703         TCC_PERF_SEL_CLIENT18_REQ                        = 0x92,
4704         TCC_PERF_SEL_CLIENT19_REQ                        = 0x93,
4705         TCC_PERF_SEL_CLIENT20_REQ                        = 0x94,
4706         TCC_PERF_SEL_CLIENT21_REQ                        = 0x95,
4707         TCC_PERF_SEL_CLIENT22_REQ                        = 0x96,
4708         TCC_PERF_SEL_CLIENT23_REQ                        = 0x97,
4709         TCC_PERF_SEL_CLIENT24_REQ                        = 0x98,
4710         TCC_PERF_SEL_CLIENT25_REQ                        = 0x99,
4711         TCC_PERF_SEL_CLIENT26_REQ                        = 0x9a,
4712         TCC_PERF_SEL_CLIENT27_REQ                        = 0x9b,
4713         TCC_PERF_SEL_CLIENT28_REQ                        = 0x9c,
4714         TCC_PERF_SEL_CLIENT29_REQ                        = 0x9d,
4715         TCC_PERF_SEL_CLIENT30_REQ                        = 0x9e,
4716         TCC_PERF_SEL_CLIENT31_REQ                        = 0x9f,
4717         TCC_PERF_SEL_CLIENT32_REQ                        = 0xa0,
4718         TCC_PERF_SEL_CLIENT33_REQ                        = 0xa1,
4719         TCC_PERF_SEL_CLIENT34_REQ                        = 0xa2,
4720         TCC_PERF_SEL_CLIENT35_REQ                        = 0xa3,
4721         TCC_PERF_SEL_CLIENT36_REQ                        = 0xa4,
4722         TCC_PERF_SEL_CLIENT37_REQ                        = 0xa5,
4723         TCC_PERF_SEL_CLIENT38_REQ                        = 0xa6,
4724         TCC_PERF_SEL_CLIENT39_REQ                        = 0xa7,
4725         TCC_PERF_SEL_CLIENT40_REQ                        = 0xa8,
4726         TCC_PERF_SEL_CLIENT41_REQ                        = 0xa9,
4727         TCC_PERF_SEL_CLIENT42_REQ                        = 0xaa,
4728         TCC_PERF_SEL_CLIENT43_REQ                        = 0xab,
4729         TCC_PERF_SEL_CLIENT44_REQ                        = 0xac,
4730         TCC_PERF_SEL_CLIENT45_REQ                        = 0xad,
4731         TCC_PERF_SEL_CLIENT46_REQ                        = 0xae,
4732         TCC_PERF_SEL_CLIENT47_REQ                        = 0xaf,
4733         TCC_PERF_SEL_CLIENT48_REQ                        = 0xb0,
4734         TCC_PERF_SEL_CLIENT49_REQ                        = 0xb1,
4735         TCC_PERF_SEL_CLIENT50_REQ                        = 0xb2,
4736         TCC_PERF_SEL_CLIENT51_REQ                        = 0xb3,
4737         TCC_PERF_SEL_CLIENT52_REQ                        = 0xb4,
4738         TCC_PERF_SEL_CLIENT53_REQ                        = 0xb5,
4739         TCC_PERF_SEL_CLIENT54_REQ                        = 0xb6,
4740         TCC_PERF_SEL_CLIENT55_REQ                        = 0xb7,
4741         TCC_PERF_SEL_CLIENT56_REQ                        = 0xb8,
4742         TCC_PERF_SEL_CLIENT57_REQ                        = 0xb9,
4743         TCC_PERF_SEL_CLIENT58_REQ                        = 0xba,
4744         TCC_PERF_SEL_CLIENT59_REQ                        = 0xbb,
4745         TCC_PERF_SEL_CLIENT60_REQ                        = 0xbc,
4746         TCC_PERF_SEL_CLIENT61_REQ                        = 0xbd,
4747         TCC_PERF_SEL_CLIENT62_REQ                        = 0xbe,
4748         TCC_PERF_SEL_CLIENT63_REQ                        = 0xbf,
4749         TCC_PERF_SEL_CLIENT64_REQ                        = 0xc0,
4750         TCC_PERF_SEL_CLIENT65_REQ                        = 0xc1,
4751         TCC_PERF_SEL_CLIENT66_REQ                        = 0xc2,
4752         TCC_PERF_SEL_CLIENT67_REQ                        = 0xc3,
4753         TCC_PERF_SEL_CLIENT68_REQ                        = 0xc4,
4754         TCC_PERF_SEL_CLIENT69_REQ                        = 0xc5,
4755         TCC_PERF_SEL_CLIENT70_REQ                        = 0xc6,
4756         TCC_PERF_SEL_CLIENT71_REQ                        = 0xc7,
4757         TCC_PERF_SEL_CLIENT72_REQ                        = 0xc8,
4758         TCC_PERF_SEL_CLIENT73_REQ                        = 0xc9,
4759         TCC_PERF_SEL_CLIENT74_REQ                        = 0xca,
4760         TCC_PERF_SEL_CLIENT75_REQ                        = 0xcb,
4761         TCC_PERF_SEL_CLIENT76_REQ                        = 0xcc,
4762         TCC_PERF_SEL_CLIENT77_REQ                        = 0xcd,
4763         TCC_PERF_SEL_CLIENT78_REQ                        = 0xce,
4764         TCC_PERF_SEL_CLIENT79_REQ                        = 0xcf,
4765         TCC_PERF_SEL_CLIENT80_REQ                        = 0xd0,
4766         TCC_PERF_SEL_CLIENT81_REQ                        = 0xd1,
4767         TCC_PERF_SEL_CLIENT82_REQ                        = 0xd2,
4768         TCC_PERF_SEL_CLIENT83_REQ                        = 0xd3,
4769         TCC_PERF_SEL_CLIENT84_REQ                        = 0xd4,
4770         TCC_PERF_SEL_CLIENT85_REQ                        = 0xd5,
4771         TCC_PERF_SEL_CLIENT86_REQ                        = 0xd6,
4772         TCC_PERF_SEL_CLIENT87_REQ                        = 0xd7,
4773         TCC_PERF_SEL_CLIENT88_REQ                        = 0xd8,
4774         TCC_PERF_SEL_CLIENT89_REQ                        = 0xd9,
4775         TCC_PERF_SEL_CLIENT90_REQ                        = 0xda,
4776         TCC_PERF_SEL_CLIENT91_REQ                        = 0xdb,
4777         TCC_PERF_SEL_CLIENT92_REQ                        = 0xdc,
4778         TCC_PERF_SEL_CLIENT93_REQ                        = 0xdd,
4779         TCC_PERF_SEL_CLIENT94_REQ                        = 0xde,
4780         TCC_PERF_SEL_CLIENT95_REQ                        = 0xdf,
4781         TCC_PERF_SEL_CLIENT96_REQ                        = 0xe0,
4782         TCC_PERF_SEL_CLIENT97_REQ                        = 0xe1,
4783         TCC_PERF_SEL_CLIENT98_REQ                        = 0xe2,
4784         TCC_PERF_SEL_CLIENT99_REQ                        = 0xe3,
4785         TCC_PERF_SEL_CLIENT100_REQ                       = 0xe4,
4786         TCC_PERF_SEL_CLIENT101_REQ                       = 0xe5,
4787         TCC_PERF_SEL_CLIENT102_REQ                       = 0xe6,
4788         TCC_PERF_SEL_CLIENT103_REQ                       = 0xe7,
4789         TCC_PERF_SEL_CLIENT104_REQ                       = 0xe8,
4790         TCC_PERF_SEL_CLIENT105_REQ                       = 0xe9,
4791         TCC_PERF_SEL_CLIENT106_REQ                       = 0xea,
4792         TCC_PERF_SEL_CLIENT107_REQ                       = 0xeb,
4793         TCC_PERF_SEL_CLIENT108_REQ                       = 0xec,
4794         TCC_PERF_SEL_CLIENT109_REQ                       = 0xed,
4795         TCC_PERF_SEL_CLIENT110_REQ                       = 0xee,
4796         TCC_PERF_SEL_CLIENT111_REQ                       = 0xef,
4797         TCC_PERF_SEL_CLIENT112_REQ                       = 0xf0,
4798         TCC_PERF_SEL_CLIENT113_REQ                       = 0xf1,
4799         TCC_PERF_SEL_CLIENT114_REQ                       = 0xf2,
4800         TCC_PERF_SEL_CLIENT115_REQ                       = 0xf3,
4801         TCC_PERF_SEL_CLIENT116_REQ                       = 0xf4,
4802         TCC_PERF_SEL_CLIENT117_REQ                       = 0xf5,
4803         TCC_PERF_SEL_CLIENT118_REQ                       = 0xf6,
4804         TCC_PERF_SEL_CLIENT119_REQ                       = 0xf7,
4805         TCC_PERF_SEL_CLIENT120_REQ                       = 0xf8,
4806         TCC_PERF_SEL_CLIENT121_REQ                       = 0xf9,
4807         TCC_PERF_SEL_CLIENT122_REQ                       = 0xfa,
4808         TCC_PERF_SEL_CLIENT123_REQ                       = 0xfb,
4809         TCC_PERF_SEL_CLIENT124_REQ                       = 0xfc,
4810         TCC_PERF_SEL_CLIENT125_REQ                       = 0xfd,
4811         TCC_PERF_SEL_CLIENT126_REQ                       = 0xfe,
4812         TCC_PERF_SEL_CLIENT127_REQ                       = 0xff,
4813 } TCC_PERF_SEL;
4814 typedef enum TCA_PERF_SEL {
4815         TCA_PERF_SEL_NONE                                = 0x0,
4816         TCA_PERF_SEL_CYCLE                               = 0x1,
4817         TCA_PERF_SEL_BUSY                                = 0x2,
4818         TCA_PERF_SEL_FORCED_HOLE_TCC0                    = 0x3,
4819         TCA_PERF_SEL_FORCED_HOLE_TCC1                    = 0x4,
4820         TCA_PERF_SEL_FORCED_HOLE_TCC2                    = 0x5,
4821         TCA_PERF_SEL_FORCED_HOLE_TCC3                    = 0x6,
4822         TCA_PERF_SEL_FORCED_HOLE_TCC4                    = 0x7,
4823         TCA_PERF_SEL_FORCED_HOLE_TCC5                    = 0x8,
4824         TCA_PERF_SEL_FORCED_HOLE_TCC6                    = 0x9,
4825         TCA_PERF_SEL_FORCED_HOLE_TCC7                    = 0xa,
4826         TCA_PERF_SEL_REQ_TCC0                            = 0xb,
4827         TCA_PERF_SEL_REQ_TCC1                            = 0xc,
4828         TCA_PERF_SEL_REQ_TCC2                            = 0xd,
4829         TCA_PERF_SEL_REQ_TCC3                            = 0xe,
4830         TCA_PERF_SEL_REQ_TCC4                            = 0xf,
4831         TCA_PERF_SEL_REQ_TCC5                            = 0x10,
4832         TCA_PERF_SEL_REQ_TCC6                            = 0x11,
4833         TCA_PERF_SEL_REQ_TCC7                            = 0x12,
4834         TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0            = 0x13,
4835         TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1            = 0x14,
4836         TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2            = 0x15,
4837         TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3            = 0x16,
4838         TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4            = 0x17,
4839         TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5            = 0x18,
4840         TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6            = 0x19,
4841         TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7            = 0x1a,
4842         TCA_PERF_SEL_CROSSBAR_STALL_TCC0                 = 0x1b,
4843         TCA_PERF_SEL_CROSSBAR_STALL_TCC1                 = 0x1c,
4844         TCA_PERF_SEL_CROSSBAR_STALL_TCC2                 = 0x1d,
4845         TCA_PERF_SEL_CROSSBAR_STALL_TCC3                 = 0x1e,
4846         TCA_PERF_SEL_CROSSBAR_STALL_TCC4                 = 0x1f,
4847         TCA_PERF_SEL_CROSSBAR_STALL_TCC5                 = 0x20,
4848         TCA_PERF_SEL_CROSSBAR_STALL_TCC6                 = 0x21,
4849         TCA_PERF_SEL_CROSSBAR_STALL_TCC7                 = 0x22,
4850 } TCA_PERF_SEL;
4851 typedef enum TA_TC_ADDR_MODES {
4852         TA_TC_ADDR_MODE_DEFAULT                          = 0x0,
4853         TA_TC_ADDR_MODE_COMP0                            = 0x1,
4854         TA_TC_ADDR_MODE_COMP1                            = 0x2,
4855         TA_TC_ADDR_MODE_COMP2                            = 0x3,
4856         TA_TC_ADDR_MODE_COMP3                            = 0x4,
4857         TA_TC_ADDR_MODE_UNALIGNED                        = 0x5,
4858         TA_TC_ADDR_MODE_BORDER_COLOR                     = 0x6,
4859 } TA_TC_ADDR_MODES;
4860 typedef enum TA_PERFCOUNT_SEL {
4861         TA_PERF_SEL_NULL                                 = 0x0,
4862         TA_PERF_SEL_sh_fifo_busy                         = 0x1,
4863         TA_PERF_SEL_sh_fifo_cmd_busy                     = 0x2,
4864         TA_PERF_SEL_sh_fifo_addr_busy                    = 0x3,
4865         TA_PERF_SEL_sh_fifo_data_busy                    = 0x4,
4866         TA_PERF_SEL_sh_fifo_data_sfifo_busy              = 0x5,
4867         TA_PERF_SEL_sh_fifo_data_tfifo_busy              = 0x6,
4868         TA_PERF_SEL_gradient_busy                        = 0x7,
4869         TA_PERF_SEL_gradient_fifo_busy                   = 0x8,
4870         TA_PERF_SEL_lod_busy                             = 0x9,
4871         TA_PERF_SEL_lod_fifo_busy                        = 0xa,
4872         TA_PERF_SEL_addresser_busy                       = 0xb,
4873         TA_PERF_SEL_addresser_fifo_busy                  = 0xc,
4874         TA_PERF_SEL_aligner_busy                         = 0xd,
4875         TA_PERF_SEL_write_path_busy                      = 0xe,
4876         TA_PERF_SEL_ta_busy                              = 0xf,
4877         TA_PERF_SEL_sq_ta_cmd_cycles                     = 0x10,
4878         TA_PERF_SEL_sp_ta_addr_cycles                    = 0x11,
4879         TA_PERF_SEL_sp_ta_data_cycles                    = 0x12,
4880         TA_PERF_SEL_ta_fa_data_state_cycles              = 0x13,
4881         TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles   = 0x14,
4882         TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles   = 0x15,
4883         TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles= 0x16,
4884         TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles= 0x17,
4885         TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles= 0x18,
4886         TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles= 0x19,
4887         TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles= 0x1a,
4888         TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles= 0x1b,
4889         TA_PERF_SEL_RESERVED_28                          = 0x1c,
4890         TA_PERF_SEL_RESERVED_29                          = 0x1d,
4891         TA_PERF_SEL_sh_fifo_addr_cycles                  = 0x1e,
4892         TA_PERF_SEL_sh_fifo_data_cycles                  = 0x1f,
4893         TA_PERF_SEL_total_wavefronts                     = 0x20,
4894         TA_PERF_SEL_gradient_cycles                      = 0x21,
4895         TA_PERF_SEL_walker_cycles                        = 0x22,
4896         TA_PERF_SEL_aligner_cycles                       = 0x23,
4897         TA_PERF_SEL_image_wavefronts                     = 0x24,
4898         TA_PERF_SEL_image_read_wavefronts                = 0x25,
4899         TA_PERF_SEL_image_write_wavefronts               = 0x26,
4900         TA_PERF_SEL_image_atomic_wavefronts              = 0x27,
4901         TA_PERF_SEL_image_total_cycles                   = 0x28,
4902         TA_PERF_SEL_RESERVED_41                          = 0x29,
4903         TA_PERF_SEL_RESERVED_42                          = 0x2a,
4904         TA_PERF_SEL_RESERVED_43                          = 0x2b,
4905         TA_PERF_SEL_buffer_wavefronts                    = 0x2c,
4906         TA_PERF_SEL_buffer_read_wavefronts               = 0x2d,
4907         TA_PERF_SEL_buffer_write_wavefronts              = 0x2e,
4908         TA_PERF_SEL_buffer_atomic_wavefronts             = 0x2f,
4909         TA_PERF_SEL_buffer_coalescable_wavefronts        = 0x30,
4910         TA_PERF_SEL_buffer_total_cycles                  = 0x31,
4911         TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles= 0x32,
4912         TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles= 0x33,
4913         TA_PERF_SEL_buffer_coalesced_read_cycles         = 0x34,
4914         TA_PERF_SEL_buffer_coalesced_write_cycles        = 0x35,
4915         TA_PERF_SEL_addr_stalled_by_tc_cycles            = 0x36,
4916         TA_PERF_SEL_addr_stalled_by_td_cycles            = 0x37,
4917         TA_PERF_SEL_data_stalled_by_tc_cycles            = 0x38,
4918         TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles= 0x39,
4919         TA_PERF_SEL_addresser_stalled_cycles             = 0x3a,
4920         TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles= 0x3b,
4921         TA_PERF_SEL_aniso_stalled_cycles                 = 0x3c,
4922         TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles   = 0x3d,
4923         TA_PERF_SEL_deriv_stalled_cycles                 = 0x3e,
4924         TA_PERF_SEL_aniso_gt1_cycle_quads                = 0x3f,
4925         TA_PERF_SEL_color_1_cycle_pixels                 = 0x40,
4926         TA_PERF_SEL_color_2_cycle_pixels                 = 0x41,
4927         TA_PERF_SEL_color_3_cycle_pixels                 = 0x42,
4928         TA_PERF_SEL_color_4_cycle_pixels                 = 0x43,
4929         TA_PERF_SEL_mip_1_cycle_pixels                   = 0x44,
4930         TA_PERF_SEL_mip_2_cycle_pixels                   = 0x45,
4931         TA_PERF_SEL_vol_1_cycle_pixels                   = 0x46,
4932         TA_PERF_SEL_vol_2_cycle_pixels                   = 0x47,
4933         TA_PERF_SEL_bilin_point_1_cycle_pixels           = 0x48,
4934         TA_PERF_SEL_mipmap_lod_0_samples                 = 0x49,
4935         TA_PERF_SEL_mipmap_lod_1_samples                 = 0x4a,
4936         TA_PERF_SEL_mipmap_lod_2_samples                 = 0x4b,
4937         TA_PERF_SEL_mipmap_lod_3_samples                 = 0x4c,
4938         TA_PERF_SEL_mipmap_lod_4_samples                 = 0x4d,
4939         TA_PERF_SEL_mipmap_lod_5_samples                 = 0x4e,
4940         TA_PERF_SEL_mipmap_lod_6_samples                 = 0x4f,
4941         TA_PERF_SEL_mipmap_lod_7_samples                 = 0x50,
4942         TA_PERF_SEL_mipmap_lod_8_samples                 = 0x51,
4943         TA_PERF_SEL_mipmap_lod_9_samples                 = 0x52,
4944         TA_PERF_SEL_mipmap_lod_10_samples                = 0x53,
4945         TA_PERF_SEL_mipmap_lod_11_samples                = 0x54,
4946         TA_PERF_SEL_mipmap_lod_12_samples                = 0x55,
4947         TA_PERF_SEL_mipmap_lod_13_samples                = 0x56,
4948         TA_PERF_SEL_mipmap_lod_14_samples                = 0x57,
4949         TA_PERF_SEL_mipmap_invalid_samples               = 0x58,
4950         TA_PERF_SEL_aniso_1_cycle_quads                  = 0x59,
4951         TA_PERF_SEL_aniso_2_cycle_quads                  = 0x5a,
4952         TA_PERF_SEL_aniso_4_cycle_quads                  = 0x5b,
4953         TA_PERF_SEL_aniso_6_cycle_quads                  = 0x5c,
4954         TA_PERF_SEL_aniso_8_cycle_quads                  = 0x5d,
4955         TA_PERF_SEL_aniso_10_cycle_quads                 = 0x5e,
4956         TA_PERF_SEL_aniso_12_cycle_quads                 = 0x5f,
4957         TA_PERF_SEL_aniso_14_cycle_quads                 = 0x60,
4958         TA_PERF_SEL_aniso_16_cycle_quads                 = 0x61,
4959         TA_PERF_SEL_write_path_input_cycles              = 0x62,
4960         TA_PERF_SEL_write_path_output_cycles             = 0x63,
4961         TA_PERF_SEL_flat_wavefronts                      = 0x64,
4962         TA_PERF_SEL_flat_read_wavefronts                 = 0x65,
4963         TA_PERF_SEL_flat_write_wavefronts                = 0x66,
4964         TA_PERF_SEL_flat_atomic_wavefronts               = 0x67,
4965         TA_PERF_SEL_flat_coalesceable_wavefronts         = 0x68,
4966         TA_PERF_SEL_reg_sclk_vld                         = 0x69,
4967         TA_PERF_SEL_local_cg_dyn_sclk_grp0_en            = 0x6a,
4968         TA_PERF_SEL_local_cg_dyn_sclk_grp1_en            = 0x6b,
4969         TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en       = 0x6c,
4970         TA_PERF_SEL_local_cg_dyn_sclk_grp4_en            = 0x6d,
4971         TA_PERF_SEL_local_cg_dyn_sclk_grp5_en            = 0x6e,
4972         TA_PERF_SEL_xnack_on_phase0                      = 0x6f,
4973         TA_PERF_SEL_xnack_on_phase1                      = 0x70,
4974         TA_PERF_SEL_xnack_on_phase2                      = 0x71,
4975         TA_PERF_SEL_xnack_on_phase3                      = 0x72,
4976         TA_PERF_SEL_first_xnack_on_phase0                = 0x73,
4977         TA_PERF_SEL_first_xnack_on_phase1                = 0x74,
4978         TA_PERF_SEL_first_xnack_on_phase2                = 0x75,
4979         TA_PERF_SEL_first_xnack_on_phase3                = 0x76,
4980 } TA_PERFCOUNT_SEL;
4981 typedef enum TD_PERFCOUNT_SEL {
4982         TD_PERF_SEL_none                                 = 0x0,
4983         TD_PERF_SEL_td_busy                              = 0x1,
4984         TD_PERF_SEL_input_busy                           = 0x2,
4985         TD_PERF_SEL_output_busy                          = 0x3,
4986         TD_PERF_SEL_lerp_busy                            = 0x4,
4987         TD_PERF_SEL_reg_sclk_vld                         = 0x5,
4988         TD_PERF_SEL_local_cg_dyn_sclk_grp0_en            = 0x6,
4989         TD_PERF_SEL_local_cg_dyn_sclk_grp1_en            = 0x7,
4990         TD_PERF_SEL_local_cg_dyn_sclk_grp4_en            = 0x8,
4991         TD_PERF_SEL_local_cg_dyn_sclk_grp5_en            = 0x9,
4992         TD_PERF_SEL_tc_td_fifo_full                      = 0xa,
4993         TD_PERF_SEL_constant_state_full                  = 0xb,
4994         TD_PERF_SEL_sample_state_full                    = 0xc,
4995         TD_PERF_SEL_output_fifo_full                     = 0xd,
4996         TD_PERF_SEL_RESERVED_14                          = 0xe,
4997         TD_PERF_SEL_tc_stall                             = 0xf,
4998         TD_PERF_SEL_pc_stall                             = 0x10,
4999         TD_PERF_SEL_gds_stall                            = 0x11,
5000         TD_PERF_SEL_RESERVED_18                          = 0x12,
5001         TD_PERF_SEL_RESERVED_19                          = 0x13,
5002         TD_PERF_SEL_gather4_wavefront                    = 0x14,
5003         TD_PERF_SEL_sample_c_wavefront                   = 0x15,
5004         TD_PERF_SEL_load_wavefront                       = 0x16,
5005         TD_PERF_SEL_atomic_wavefront                     = 0x17,
5006         TD_PERF_SEL_store_wavefront                      = 0x18,
5007         TD_PERF_SEL_ldfptr_wavefront                     = 0x19,
5008         TD_PERF_SEL_RESERVED_26                          = 0x1a,
5009         TD_PERF_SEL_RESERVED_27                          = 0x1b,
5010         TD_PERF_SEL_d16_en_wavefront                     = 0x1c,
5011         TD_PERF_SEL_bicubic_filter_wavefront             = 0x1d,
5012         TD_PERF_SEL_bypass_filter_wavefront              = 0x1e,
5013         TD_PERF_SEL_min_max_filter_wavefront             = 0x1f,
5014         TD_PERF_SEL_coalescable_wavefront                = 0x20,
5015         TD_PERF_SEL_coalesced_phase                      = 0x21,
5016         TD_PERF_SEL_four_phase_wavefront                 = 0x22,
5017         TD_PERF_SEL_eight_phase_wavefront                = 0x23,
5018         TD_PERF_SEL_sixteen_phase_wavefront              = 0x24,
5019         TD_PERF_SEL_four_phase_forward_wavefront         = 0x25,
5020         TD_PERF_SEL_write_ack_wavefront                  = 0x26,
5021         TD_PERF_SEL_RESERVED_39                          = 0x27,
5022         TD_PERF_SEL_user_defined_border                  = 0x28,
5023         TD_PERF_SEL_white_border                         = 0x29,
5024         TD_PERF_SEL_opaque_black_border                  = 0x2a,
5025         TD_PERF_SEL_RESERVED_43                          = 0x2b,
5026         TD_PERF_SEL_RESERVED_44                          = 0x2c,
5027         TD_PERF_SEL_nack                                 = 0x2d,
5028         TD_PERF_SEL_td_sp_traffic                        = 0x2e,
5029         TD_PERF_SEL_consume_gds_traffic                  = 0x2f,
5030         TD_PERF_SEL_addresscmd_poison                    = 0x30,
5031         TD_PERF_SEL_data_poison                          = 0x31,
5032         TD_PERF_SEL_start_cycle_0                        = 0x32,
5033         TD_PERF_SEL_start_cycle_1                        = 0x33,
5034         TD_PERF_SEL_start_cycle_2                        = 0x34,
5035         TD_PERF_SEL_start_cycle_3                        = 0x35,
5036         TD_PERF_SEL_null_cycle_output                    = 0x36,
5037         TD_PERF_SEL_d16_data_packed                      = 0x37,
5038 } TD_PERFCOUNT_SEL;
5039 typedef enum TCP_PERFCOUNT_SELECT {
5040         TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES           = 0x0,
5041         TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES           = 0x1,
5042         TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES            = 0x2,
5043         TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES            = 0x3,
5044         TCP_PERF_SEL_TD_TCP_STALL_CYCLES                 = 0x4,
5045         TCP_PERF_SEL_TCR_TCP_STALL_CYCLES                = 0x5,
5046         TCP_PERF_SEL_LOD_STALL_CYCLES                    = 0x6,
5047         TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES       = 0x7,
5048         TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES      = 0x8,
5049         TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES     = 0x9,
5050         TCP_PERF_SEL_ALLOC_STALL_CYCLES                  = 0xa,
5051         TCP_PERF_SEL_LFIFO_STALL_CYCLES                  = 0xb,
5052         TCP_PERF_SEL_RFIFO_STALL_CYCLES                  = 0xc,
5053         TCP_PERF_SEL_TCR_RDRET_STALL                     = 0xd,
5054         TCP_PERF_SEL_WRITE_CONFLICT_STALL                = 0xe,
5055         TCP_PERF_SEL_HOLE_READ_STALL                     = 0xf,
5056         TCP_PERF_SEL_READCONFLICT_STALL_CYCLES           = 0x10,
5057         TCP_PERF_SEL_PENDING_STALL_CYCLES                = 0x11,
5058         TCP_PERF_SEL_READFIFO_STALL_CYCLES               = 0x12,
5059         TCP_PERF_SEL_TCP_LATENCY                         = 0x13,
5060         TCP_PERF_SEL_TCC_READ_REQ_LATENCY                = 0x14,
5061         TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY               = 0x15,
5062         TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY          = 0x16,
5063         TCP_PERF_SEL_TCC_READ_REQ                        = 0x17,
5064         TCP_PERF_SEL_TCC_WRITE_REQ                       = 0x18,
5065         TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ             = 0x19,
5066         TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ          = 0x1a,
5067         TCP_PERF_SEL_TOTAL_LOCAL_READ                    = 0x1b,
5068         TCP_PERF_SEL_TOTAL_GLOBAL_READ                   = 0x1c,
5069         TCP_PERF_SEL_TOTAL_LOCAL_WRITE                   = 0x1d,
5070         TCP_PERF_SEL_TOTAL_GLOBAL_WRITE                  = 0x1e,
5071         TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET               = 0x1f,
5072         TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET            = 0x20,
5073         TCP_PERF_SEL_TOTAL_WBINVL1                       = 0x21,
5074         TCP_PERF_SEL_IMG_READ_FMT_1                      = 0x22,
5075         TCP_PERF_SEL_IMG_READ_FMT_8                      = 0x23,
5076         TCP_PERF_SEL_IMG_READ_FMT_16                     = 0x24,
5077         TCP_PERF_SEL_IMG_READ_FMT_32                     = 0x25,
5078         TCP_PERF_SEL_IMG_READ_FMT_32_AS_8                = 0x26,
5079         TCP_PERF_SEL_IMG_READ_FMT_32_AS_16               = 0x27,
5080         TCP_PERF_SEL_IMG_READ_FMT_32_AS_128              = 0x28,
5081         TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE             = 0x29,
5082         TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE             = 0x2a,
5083         TCP_PERF_SEL_IMG_READ_FMT_96                     = 0x2b,
5084         TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE            = 0x2c,
5085         TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE            = 0x2d,
5086         TCP_PERF_SEL_IMG_READ_FMT_BC1                    = 0x2e,
5087         TCP_PERF_SEL_IMG_READ_FMT_BC2                    = 0x2f,
5088         TCP_PERF_SEL_IMG_READ_FMT_BC3                    = 0x30,
5089         TCP_PERF_SEL_IMG_READ_FMT_BC4                    = 0x31,
5090         TCP_PERF_SEL_IMG_READ_FMT_BC5                    = 0x32,
5091         TCP_PERF_SEL_IMG_READ_FMT_BC6                    = 0x33,
5092         TCP_PERF_SEL_IMG_READ_FMT_BC7                    = 0x34,
5093         TCP_PERF_SEL_IMG_READ_FMT_I8                     = 0x35,
5094         TCP_PERF_SEL_IMG_READ_FMT_I16                    = 0x36,
5095         TCP_PERF_SEL_IMG_READ_FMT_I32                    = 0x37,
5096         TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8               = 0x38,
5097         TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16              = 0x39,
5098         TCP_PERF_SEL_IMG_READ_FMT_D8                     = 0x3a,
5099         TCP_PERF_SEL_IMG_READ_FMT_D16                    = 0x3b,
5100         TCP_PERF_SEL_IMG_READ_FMT_D32                    = 0x3c,
5101         TCP_PERF_SEL_IMG_WRITE_FMT_8                     = 0x3d,
5102         TCP_PERF_SEL_IMG_WRITE_FMT_16                    = 0x3e,
5103         TCP_PERF_SEL_IMG_WRITE_FMT_32                    = 0x3f,
5104         TCP_PERF_SEL_IMG_WRITE_FMT_64                    = 0x40,
5105         TCP_PERF_SEL_IMG_WRITE_FMT_128                   = 0x41,
5106         TCP_PERF_SEL_IMG_WRITE_FMT_D8                    = 0x42,
5107         TCP_PERF_SEL_IMG_WRITE_FMT_D16                   = 0x43,
5108         TCP_PERF_SEL_IMG_WRITE_FMT_D32                   = 0x44,
5109         TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32          = 0x45,
5110         TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32       = 0x46,
5111         TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64          = 0x47,
5112         TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64       = 0x48,
5113         TCP_PERF_SEL_BUF_READ_FMT_8                      = 0x49,
5114         TCP_PERF_SEL_BUF_READ_FMT_16                     = 0x4a,
5115         TCP_PERF_SEL_BUF_READ_FMT_32                     = 0x4b,
5116         TCP_PERF_SEL_BUF_WRITE_FMT_8                     = 0x4c,
5117         TCP_PERF_SEL_BUF_WRITE_FMT_16                    = 0x4d,
5118         TCP_PERF_SEL_BUF_WRITE_FMT_32                    = 0x4e,
5119         TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32          = 0x4f,
5120         TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32       = 0x50,
5121         TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64          = 0x51,
5122         TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64       = 0x52,
5123         TCP_PERF_SEL_ARR_LINEAR_GENERAL                  = 0x53,
5124         TCP_PERF_SEL_ARR_LINEAR_ALIGNED                  = 0x54,
5125         TCP_PERF_SEL_ARR_1D_THIN1                        = 0x55,
5126         TCP_PERF_SEL_ARR_1D_THICK                        = 0x56,
5127         TCP_PERF_SEL_ARR_2D_THIN1                        = 0x57,
5128         TCP_PERF_SEL_ARR_2D_THICK                        = 0x58,
5129         TCP_PERF_SEL_ARR_2D_XTHICK                       = 0x59,
5130         TCP_PERF_SEL_ARR_3D_THIN1                        = 0x5a,
5131         TCP_PERF_SEL_ARR_3D_THICK                        = 0x5b,
5132         TCP_PERF_SEL_ARR_3D_XTHICK                       = 0x5c,
5133         TCP_PERF_SEL_DIM_1D                              = 0x5d,
5134         TCP_PERF_SEL_DIM_2D                              = 0x5e,
5135         TCP_PERF_SEL_DIM_3D                              = 0x5f,
5136         TCP_PERF_SEL_DIM_1D_ARRAY                        = 0x60,
5137         TCP_PERF_SEL_DIM_2D_ARRAY                        = 0x61,
5138         TCP_PERF_SEL_DIM_2D_MSAA                         = 0x62,
5139         TCP_PERF_SEL_DIM_2D_ARRAY_MSAA                   = 0x63,
5140         TCP_PERF_SEL_DIM_CUBE_ARRAY                      = 0x64,
5141         TCP_PERF_SEL_CP_TCP_INVALIDATE                   = 0x65,
5142         TCP_PERF_SEL_TA_TCP_STATE_READ                   = 0x66,
5143         TCP_PERF_SEL_TAGRAM0_REQ                         = 0x67,
5144         TCP_PERF_SEL_TAGRAM1_REQ                         = 0x68,
5145         TCP_PERF_SEL_TAGRAM2_REQ                         = 0x69,
5146         TCP_PERF_SEL_TAGRAM3_REQ                         = 0x6a,
5147         TCP_PERF_SEL_GATE_EN1                            = 0x6b,
5148         TCP_PERF_SEL_GATE_EN2                            = 0x6c,
5149         TCP_PERF_SEL_CORE_REG_SCLK_VLD                   = 0x6d,
5150         TCP_PERF_SEL_TCC_REQ                             = 0x6e,
5151         TCP_PERF_SEL_TCC_NON_READ_REQ                    = 0x6f,
5152         TCP_PERF_SEL_TCC_BYPASS_READ_REQ                 = 0x70,
5153         TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ             = 0x71,
5154         TCP_PERF_SEL_TCC_VOLATILE_READ_REQ               = 0x72,
5155         TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ        = 0x73,
5156         TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ    = 0x74,
5157         TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ                = 0x75,
5158         TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ            = 0x76,
5159         TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ       = 0x77,
5160         TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ              = 0x78,
5161         TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ   = 0x79,
5162         TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ               = 0x7a,
5163         TCP_PERF_SEL_TCC_ATOMIC_REQ                      = 0x7b,
5164         TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ             = 0x7c,
5165         TCP_PERF_SEL_TCC_DATA_BUS_BUSY                   = 0x7d,
5166         TCP_PERF_SEL_TOTAL_ACCESSES                      = 0x7e,
5167         TCP_PERF_SEL_TOTAL_READ                          = 0x7f,
5168         TCP_PERF_SEL_TOTAL_HIT_LRU_READ                  = 0x80,
5169         TCP_PERF_SEL_TOTAL_HIT_EVICT_READ                = 0x81,
5170         TCP_PERF_SEL_TOTAL_MISS_LRU_READ                 = 0x82,
5171         TCP_PERF_SEL_TOTAL_MISS_EVICT_READ               = 0x83,
5172         TCP_PERF_SEL_TOTAL_NON_READ                      = 0x84,
5173         TCP_PERF_SEL_TOTAL_WRITE                         = 0x85,
5174         TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE                = 0x86,
5175         TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE              = 0x87,
5176         TCP_PERF_SEL_TOTAL_WBINVL1_VOL                   = 0x88,
5177         TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES         = 0x89,
5178         TCP_PERF_SEL_DISPLAY_MICROTILING                 = 0x8a,
5179         TCP_PERF_SEL_THIN_MICROTILING                    = 0x8b,
5180         TCP_PERF_SEL_DEPTH_MICROTILING                   = 0x8c,
5181         TCP_PERF_SEL_ARR_PRT_THIN1                       = 0x8d,
5182         TCP_PERF_SEL_ARR_PRT_2D_THIN1                    = 0x8e,
5183         TCP_PERF_SEL_ARR_PRT_3D_THIN1                    = 0x8f,
5184         TCP_PERF_SEL_ARR_PRT_THICK                       = 0x90,
5185         TCP_PERF_SEL_ARR_PRT_2D_THICK                    = 0x91,
5186         TCP_PERF_SEL_ARR_PRT_3D_THICK                    = 0x92,
5187         TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL               = 0x93,
5188         TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL               = 0x94,
5189         TCP_PERF_SEL_UNALIGNED                           = 0x95,
5190         TCP_PERF_SEL_ROTATED_MICROTILING                 = 0x96,
5191         TCP_PERF_SEL_THICK_MICROTILING                   = 0x97,
5192         TCP_PERF_SEL_ATC                                 = 0x98,
5193         TCP_PERF_SEL_POWER_STALL                         = 0x99,
5194         TCP_PERF_SEL_RESERVED_154                        = 0x9a,
5195         TCP_PERF_SEL_TCC_LRU_REQ                         = 0x9b,
5196         TCP_PERF_SEL_TCC_STREAM_REQ                      = 0x9c,
5197         TCP_PERF_SEL_TCC_NC_READ_REQ                     = 0x9d,
5198         TCP_PERF_SEL_TCC_NC_WRITE_REQ                    = 0x9e,
5199         TCP_PERF_SEL_TCC_NC_ATOMIC_REQ                   = 0x9f,
5200         TCP_PERF_SEL_TCC_UC_READ_REQ                     = 0xa0,
5201         TCP_PERF_SEL_TCC_UC_WRITE_REQ                    = 0xa1,
5202         TCP_PERF_SEL_TCC_UC_ATOMIC_REQ                   = 0xa2,
5203         TCP_PERF_SEL_TCC_CC_READ_REQ                     = 0xa3,
5204         TCP_PERF_SEL_TCC_CC_WRITE_REQ                    = 0xa4,
5205         TCP_PERF_SEL_TCC_CC_ATOMIC_REQ                   = 0xa5,
5206         TCP_PERF_SEL_TCC_DCC_REQ                         = 0xa6,
5207         TCP_PERF_SEL_TCC_PHYSICAL_REQ                    = 0xa7,
5208         TCP_PERF_SEL_UNORDERED_MTYPE_STALL               = 0xa8,
5209         TCP_PERF_SEL_VOLATILE                            = 0xa9,
5210         TCP_PERF_SEL_TC_TA_XNACK_STALL                   = 0xaa,
5211         TCP_PERF_SEL_ATCL1_SERIALIZATION_STALL           = 0xab,
5212         TCP_PERF_SEL_SHOOTDOWN                           = 0xac,
5213         TCP_PERF_SEL_GATCL1_TRANSLATION_MISS             = 0xad,
5214         TCP_PERF_SEL_GATCL1_PERMISSION_MISS              = 0xae,
5215         TCP_PERF_SEL_GATCL1_REQUEST                      = 0xaf,
5216         TCP_PERF_SEL_GATCL1_STALL_INFLIGHT_MAX           = 0xb0,
5217         TCP_PERF_SEL_GATCL1_STALL_LRU_INFLIGHT           = 0xb1,
5218         TCP_PERF_SEL_GATCL1_LFIFO_FULL                   = 0xb2,
5219         TCP_PERF_SEL_GATCL1_STALL_LFIFO_NOT_RES          = 0xb3,
5220         TCP_PERF_SEL_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS= 0xb4,
5221         TCP_PERF_SEL_GATCL1_ATCL2_INFLIGHT               = 0xb5,
5222         TCP_PERF_SEL_GATCL1_STALL_MISSFIFO_FULL          = 0xb6,
5223         TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGB               = 0xb7,
5224         TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA              = 0xb8,
5225         TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA1             = 0xb9,
5226         TCP_PERF_SEL_IMG_READ_FMT_ETC2_R                 = 0xba,
5227         TCP_PERF_SEL_IMG_READ_FMT_ETC2_RG                = 0xbb,
5228         TCP_PERF_SEL_IMG_READ_FMT_8_AS_32                = 0xbc,
5229         TCP_PERF_SEL_IMG_READ_FMT_8_AS_64                = 0xbd,
5230         TCP_PERF_SEL_IMG_READ_FMT_16_AS_64               = 0xbe,
5231         TCP_PERF_SEL_IMG_READ_FMT_16_AS_128              = 0xbf,
5232         TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_32               = 0xc0,
5233         TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_64               = 0xc1,
5234         TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_64              = 0xc2,
5235         TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_128             = 0xc3,
5236 } TCP_PERFCOUNT_SELECT;
5237 typedef enum TCP_CACHE_POLICIES {
5238         TCP_CACHE_POLICY_MISS_LRU                        = 0x0,
5239         TCP_CACHE_POLICY_MISS_EVICT                      = 0x1,
5240         TCP_CACHE_POLICY_HIT_LRU                         = 0x2,
5241         TCP_CACHE_POLICY_HIT_EVICT                       = 0x3,
5242 } TCP_CACHE_POLICIES;
5243 typedef enum TCP_CACHE_STORE_POLICIES {
5244         TCP_CACHE_STORE_POLICY_WT_LRU                    = 0x0,
5245         TCP_CACHE_STORE_POLICY_WT_EVICT                  = 0x1,
5246 } TCP_CACHE_STORE_POLICIES;
5247 typedef enum TCP_WATCH_MODES {
5248         TCP_WATCH_MODE_READ                              = 0x0,
5249         TCP_WATCH_MODE_NONREAD                           = 0x1,
5250         TCP_WATCH_MODE_ATOMIC                            = 0x2,
5251         TCP_WATCH_MODE_ALL                               = 0x3,
5252 } TCP_WATCH_MODES;
5253 typedef enum TCP_DSM_DATA_SEL {
5254         TCP_DSM_DISABLE                                  = 0x0,
5255         TCP_DSM_SEL0                                     = 0x1,
5256         TCP_DSM_SEL1                                     = 0x2,
5257         TCP_DSM_SEL_BOTH                                 = 0x3,
5258 } TCP_DSM_DATA_SEL;
5259 typedef enum TCP_DSM_SINGLE_WRITE {
5260         TCP_DSM_SINGLE_WRITE_EN                          = 0x1,
5261 } TCP_DSM_SINGLE_WRITE;
5262 typedef enum VGT_OUT_PRIM_TYPE {
5263         VGT_OUT_POINT                                    = 0x0,
5264         VGT_OUT_LINE                                     = 0x1,
5265         VGT_OUT_TRI                                      = 0x2,
5266         VGT_OUT_RECT_V0                                  = 0x3,
5267         VGT_OUT_RECT_V1                                  = 0x4,
5268         VGT_OUT_RECT_V2                                  = 0x5,
5269         VGT_OUT_RECT_V3                                  = 0x6,
5270         VGT_OUT_RESERVED                                 = 0x7,
5271         VGT_TE_QUAD                                      = 0x8,
5272         VGT_TE_PRIM_INDEX_LINE                           = 0x9,
5273         VGT_TE_PRIM_INDEX_TRI                            = 0xa,
5274         VGT_TE_PRIM_INDEX_QUAD                           = 0xb,
5275         VGT_OUT_LINE_ADJ                                 = 0xc,
5276         VGT_OUT_TRI_ADJ                                  = 0xd,
5277         VGT_OUT_PATCH                                    = 0xe,
5278 } VGT_OUT_PRIM_TYPE;
5279 typedef enum VGT_DI_PRIM_TYPE {
5280         DI_PT_NONE                                       = 0x0,
5281         DI_PT_POINTLIST                                  = 0x1,
5282         DI_PT_LINELIST                                   = 0x2,
5283         DI_PT_LINESTRIP                                  = 0x3,
5284         DI_PT_TRILIST                                    = 0x4,
5285         DI_PT_TRIFAN                                     = 0x5,
5286         DI_PT_TRISTRIP                                   = 0x6,
5287         DI_PT_UNUSED_0                                   = 0x7,
5288         DI_PT_UNUSED_1                                   = 0x8,
5289         DI_PT_PATCH                                      = 0x9,
5290         DI_PT_LINELIST_ADJ                               = 0xa,
5291         DI_PT_LINESTRIP_ADJ                              = 0xb,
5292         DI_PT_TRILIST_ADJ                                = 0xc,
5293         DI_PT_TRISTRIP_ADJ                               = 0xd,
5294         DI_PT_UNUSED_3                                   = 0xe,
5295         DI_PT_UNUSED_4                                   = 0xf,
5296         DI_PT_TRI_WITH_WFLAGS                            = 0x10,
5297         DI_PT_RECTLIST                                   = 0x11,
5298         DI_PT_LINELOOP                                   = 0x12,
5299         DI_PT_QUADLIST                                   = 0x13,
5300         DI_PT_QUADSTRIP                                  = 0x14,
5301         DI_PT_POLYGON                                    = 0x15,
5302         DI_PT_2D_COPY_RECT_LIST_V0                       = 0x16,
5303         DI_PT_2D_COPY_RECT_LIST_V1                       = 0x17,
5304         DI_PT_2D_COPY_RECT_LIST_V2                       = 0x18,
5305         DI_PT_2D_COPY_RECT_LIST_V3                       = 0x19,
5306         DI_PT_2D_FILL_RECT_LIST                          = 0x1a,
5307         DI_PT_2D_LINE_STRIP                              = 0x1b,
5308         DI_PT_2D_TRI_STRIP                               = 0x1c,
5309 } VGT_DI_PRIM_TYPE;
5310 typedef enum VGT_DI_SOURCE_SELECT {
5311         DI_SRC_SEL_DMA                                   = 0x0,
5312         DI_SRC_SEL_IMMEDIATE                             = 0x1,
5313         DI_SRC_SEL_AUTO_INDEX                            = 0x2,
5314         DI_SRC_SEL_RESERVED                              = 0x3,
5315 } VGT_DI_SOURCE_SELECT;
5316 typedef enum VGT_DI_MAJOR_MODE_SELECT {
5317         DI_MAJOR_MODE_0                                  = 0x0,
5318         DI_MAJOR_MODE_1                                  = 0x1,
5319 } VGT_DI_MAJOR_MODE_SELECT;
5320 typedef enum VGT_DI_INDEX_SIZE {
5321         DI_INDEX_SIZE_16_BIT                             = 0x0,
5322         DI_INDEX_SIZE_32_BIT                             = 0x1,
5323         DI_INDEX_SIZE_8_BIT                              = 0x2,
5324 } VGT_DI_INDEX_SIZE;
5325 typedef enum VGT_EVENT_TYPE {
5326         Reserved_0x00                                    = 0x0,
5327         SAMPLE_STREAMOUTSTATS1                           = 0x1,
5328         SAMPLE_STREAMOUTSTATS2                           = 0x2,
5329         SAMPLE_STREAMOUTSTATS3                           = 0x3,
5330         CACHE_FLUSH_TS                                   = 0x4,
5331         CONTEXT_DONE                                     = 0x5,
5332         CACHE_FLUSH                                      = 0x6,
5333         CS_PARTIAL_FLUSH                                 = 0x7,
5334         VGT_STREAMOUT_SYNC                               = 0x8,
5335         Reserved_0x09                                    = 0x9,
5336         VGT_STREAMOUT_RESET                              = 0xa,
5337         END_OF_PIPE_INCR_DE                              = 0xb,
5338         END_OF_PIPE_IB_END                               = 0xc,
5339         RST_PIX_CNT                                      = 0xd,
5340         Reserved_0x0E                                    = 0xe,
5341         VS_PARTIAL_FLUSH                                 = 0xf,
5342         PS_PARTIAL_FLUSH                                 = 0x10,
5343         FLUSH_HS_OUTPUT                                  = 0x11,
5344         FLUSH_LS_OUTPUT                                  = 0x12,
5345         Reserved_0x13                                    = 0x13,
5346         CACHE_FLUSH_AND_INV_TS_EVENT                     = 0x14,
5347         ZPASS_DONE                                       = 0x15,
5348         CACHE_FLUSH_AND_INV_EVENT                        = 0x16,
5349         PERFCOUNTER_START                                = 0x17,
5350         PERFCOUNTER_STOP                                 = 0x18,
5351         PIPELINESTAT_START                               = 0x19,
5352         PIPELINESTAT_STOP                                = 0x1a,
5353         PERFCOUNTER_SAMPLE                               = 0x1b,
5354         FLUSH_ES_OUTPUT                                  = 0x1c,
5355         FLUSH_GS_OUTPUT                                  = 0x1d,
5356         SAMPLE_PIPELINESTAT                              = 0x1e,
5357         SO_VGTSTREAMOUT_FLUSH                            = 0x1f,
5358         SAMPLE_STREAMOUTSTATS                            = 0x20,
5359         RESET_VTX_CNT                                    = 0x21,
5360         BLOCK_CONTEXT_DONE                               = 0x22,
5361         CS_CONTEXT_DONE                                  = 0x23,
5362         VGT_FLUSH                                        = 0x24,
5363         TGID_ROLLOVER                                    = 0x25,
5364         SQ_NON_EVENT                                     = 0x26,
5365         SC_SEND_DB_VPZ                                   = 0x27,
5366         BOTTOM_OF_PIPE_TS                                = 0x28,
5367         FLUSH_SX_TS                                      = 0x29,
5368         DB_CACHE_FLUSH_AND_INV                           = 0x2a,
5369         FLUSH_AND_INV_DB_DATA_TS                         = 0x2b,
5370         FLUSH_AND_INV_DB_META                            = 0x2c,
5371         FLUSH_AND_INV_CB_DATA_TS                         = 0x2d,
5372         FLUSH_AND_INV_CB_META                            = 0x2e,
5373         CS_DONE                                          = 0x2f,
5374         PS_DONE                                          = 0x30,
5375         FLUSH_AND_INV_CB_PIXEL_DATA                      = 0x31,
5376         SX_CB_RAT_ACK_REQUEST                            = 0x32,
5377         THREAD_TRACE_START                               = 0x33,
5378         THREAD_TRACE_STOP                                = 0x34,
5379         THREAD_TRACE_MARKER                              = 0x35,
5380         THREAD_TRACE_FLUSH                               = 0x36,
5381         THREAD_TRACE_FINISH                              = 0x37,
5382         PIXEL_PIPE_STAT_CONTROL                          = 0x38,
5383         PIXEL_PIPE_STAT_DUMP                             = 0x39,
5384         PIXEL_PIPE_STAT_RESET                            = 0x3a,
5385         CONTEXT_SUSPEND                                  = 0x3b,
5386         OFFCHIP_HS_DEALLOC                               = 0x3c,
5387 } VGT_EVENT_TYPE;
5388 typedef enum VGT_DMA_SWAP_MODE {
5389         VGT_DMA_SWAP_NONE                                = 0x0,
5390         VGT_DMA_SWAP_16_BIT                              = 0x1,
5391         VGT_DMA_SWAP_32_BIT                              = 0x2,
5392         VGT_DMA_SWAP_WORD                                = 0x3,
5393 } VGT_DMA_SWAP_MODE;
5394 typedef enum VGT_INDEX_TYPE_MODE {
5395         VGT_INDEX_16                                     = 0x0,
5396         VGT_INDEX_32                                     = 0x1,
5397         VGT_INDEX_8                                      = 0x2,
5398 } VGT_INDEX_TYPE_MODE;
5399 typedef enum VGT_DMA_BUF_TYPE {
5400         VGT_DMA_BUF_MEM                                  = 0x0,
5401         VGT_DMA_BUF_RING                                 = 0x1,
5402         VGT_DMA_BUF_SETUP                                = 0x2,
5403         VGT_DMA_PTR_UPDATE                               = 0x3,
5404 } VGT_DMA_BUF_TYPE;
5405 typedef enum VGT_OUTPATH_SELECT {
5406         VGT_OUTPATH_VTX_REUSE                            = 0x0,
5407         VGT_OUTPATH_TESS_EN                              = 0x1,
5408         VGT_OUTPATH_PASSTHRU                             = 0x2,
5409         VGT_OUTPATH_GS_BLOCK                             = 0x3,
5410         VGT_OUTPATH_HS_BLOCK                             = 0x4,
5411 } VGT_OUTPATH_SELECT;
5412 typedef enum VGT_GRP_PRIM_TYPE {
5413         VGT_GRP_3D_POINT                                 = 0x0,
5414         VGT_GRP_3D_LINE                                  = 0x1,
5415         VGT_GRP_3D_TRI                                   = 0x2,
5416         VGT_GRP_3D_RECT                                  = 0x3,
5417         VGT_GRP_3D_QUAD                                  = 0x4,
5418         VGT_GRP_2D_COPY_RECT_V0                          = 0x5,
5419         VGT_GRP_2D_COPY_RECT_V1                          = 0x6,
5420         VGT_GRP_2D_COPY_RECT_V2                          = 0x7,
5421         VGT_GRP_2D_COPY_RECT_V3                          = 0x8,
5422         VGT_GRP_2D_FILL_RECT                             = 0x9,
5423         VGT_GRP_2D_LINE                                  = 0xa,
5424         VGT_GRP_2D_TRI                                   = 0xb,
5425         VGT_GRP_PRIM_INDEX_LINE                          = 0xc,
5426         VGT_GRP_PRIM_INDEX_TRI                           = 0xd,
5427         VGT_GRP_PRIM_INDEX_QUAD                          = 0xe,
5428         VGT_GRP_3D_LINE_ADJ                              = 0xf,
5429         VGT_GRP_3D_TRI_ADJ                               = 0x10,
5430         VGT_GRP_3D_PATCH                                 = 0x11,
5431 } VGT_GRP_PRIM_TYPE;
5432 typedef enum VGT_GRP_PRIM_ORDER {
5433         VGT_GRP_LIST                                     = 0x0,
5434         VGT_GRP_STRIP                                    = 0x1,
5435         VGT_GRP_FAN                                      = 0x2,
5436         VGT_GRP_LOOP                                     = 0x3,
5437         VGT_GRP_POLYGON                                  = 0x4,
5438 } VGT_GRP_PRIM_ORDER;
5439 typedef enum VGT_GROUP_CONV_SEL {
5440         VGT_GRP_INDEX_16                                 = 0x0,
5441         VGT_GRP_INDEX_32                                 = 0x1,
5442         VGT_GRP_UINT_16                                  = 0x2,
5443         VGT_GRP_UINT_32                                  = 0x3,
5444         VGT_GRP_SINT_16                                  = 0x4,
5445         VGT_GRP_SINT_32                                  = 0x5,
5446         VGT_GRP_FLOAT_32                                 = 0x6,
5447         VGT_GRP_AUTO_PRIM                                = 0x7,
5448         VGT_GRP_FIX_1_23_TO_FLOAT                        = 0x8,
5449 } VGT_GROUP_CONV_SEL;
5450 typedef enum VGT_GS_MODE_TYPE {
5451         GS_OFF                                           = 0x0,
5452         GS_SCENARIO_A                                    = 0x1,
5453         GS_SCENARIO_B                                    = 0x2,
5454         GS_SCENARIO_G                                    = 0x3,
5455         GS_SCENARIO_C                                    = 0x4,
5456         SPRITE_EN                                        = 0x5,
5457 } VGT_GS_MODE_TYPE;
5458 typedef enum VGT_GS_CUT_MODE {
5459         GS_CUT_1024                                      = 0x0,
5460         GS_CUT_512                                       = 0x1,
5461         GS_CUT_256                                       = 0x2,
5462         GS_CUT_128                                       = 0x3,
5463 } VGT_GS_CUT_MODE;
5464 typedef enum VGT_GS_OUTPRIM_TYPE {
5465         POINTLIST                                        = 0x0,
5466         LINESTRIP                                        = 0x1,
5467         TRISTRIP                                         = 0x2,
5468 } VGT_GS_OUTPRIM_TYPE;
5469 typedef enum VGT_CACHE_INVALID_MODE {
5470         VC_ONLY                                          = 0x0,
5471         TC_ONLY                                          = 0x1,
5472         VC_AND_TC                                        = 0x2,
5473 } VGT_CACHE_INVALID_MODE;
5474 typedef enum VGT_TESS_TYPE {
5475         TESS_ISOLINE                                     = 0x0,
5476         TESS_TRIANGLE                                    = 0x1,
5477         TESS_QUAD                                        = 0x2,
5478 } VGT_TESS_TYPE;
5479 typedef enum VGT_TESS_PARTITION {
5480         PART_INTEGER                                     = 0x0,
5481         PART_POW2                                        = 0x1,
5482         PART_FRAC_ODD                                    = 0x2,
5483         PART_FRAC_EVEN                                   = 0x3,
5484 } VGT_TESS_PARTITION;
5485 typedef enum VGT_TESS_TOPOLOGY {
5486         OUTPUT_POINT                                     = 0x0,
5487         OUTPUT_LINE                                      = 0x1,
5488         OUTPUT_TRIANGLE_CW                               = 0x2,
5489         OUTPUT_TRIANGLE_CCW                              = 0x3,
5490 } VGT_TESS_TOPOLOGY;
5491 typedef enum VGT_RDREQ_POLICY {
5492         VGT_POLICY_LRU                                   = 0x0,
5493         VGT_POLICY_STREAM                                = 0x1,
5494 } VGT_RDREQ_POLICY;
5495 typedef enum VGT_DIST_MODE {
5496         NO_DIST                                          = 0x0,
5497         PATCHES                                          = 0x1,
5498         DONUTS                                           = 0x2,
5499 } VGT_DIST_MODE;
5500 typedef enum VGT_STAGES_LS_EN {
5501         LS_STAGE_OFF                                     = 0x0,
5502         LS_STAGE_ON                                      = 0x1,
5503         CS_STAGE_ON                                      = 0x2,
5504         RESERVED_LS                                      = 0x3,
5505 } VGT_STAGES_LS_EN;
5506 typedef enum VGT_STAGES_HS_EN {
5507         HS_STAGE_OFF                                     = 0x0,
5508         HS_STAGE_ON                                      = 0x1,
5509 } VGT_STAGES_HS_EN;
5510 typedef enum VGT_STAGES_ES_EN {
5511         ES_STAGE_OFF                                     = 0x0,
5512         ES_STAGE_DS                                      = 0x1,
5513         ES_STAGE_REAL                                    = 0x2,
5514         RESERVED_ES                                      = 0x3,
5515 } VGT_STAGES_ES_EN;
5516 typedef enum VGT_STAGES_GS_EN {
5517         GS_STAGE_OFF                                     = 0x0,
5518         GS_STAGE_ON                                      = 0x1,
5519 } VGT_STAGES_GS_EN;
5520 typedef enum VGT_STAGES_VS_EN {
5521         VS_STAGE_REAL                                    = 0x0,
5522         VS_STAGE_DS                                      = 0x1,
5523         VS_STAGE_COPY_SHADER                             = 0x2,
5524         RESERVED_VS                                      = 0x3,
5525 } VGT_STAGES_VS_EN;
5526 typedef enum VGT_PERFCOUNT_SELECT {
5527         vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE    = 0x0,
5528         vgt_perf_VGT_SPI_ESVERT_VALID                    = 0x1,
5529         vgt_perf_VGT_SPI_ESVERT_EOV                      = 0x2,
5530         vgt_perf_VGT_SPI_ESVERT_STALLED                  = 0x3,
5531         vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY             = 0x4,
5532         vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE             = 0x5,
5533         vgt_perf_VGT_SPI_ESVERT_STATIC                   = 0x6,
5534         vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT               = 0x7,
5535         vgt_perf_VGT_SPI_ESTHREAD_SEND                   = 0x8,
5536         vgt_perf_VGT_SPI_GSPRIM_VALID                    = 0x9,
5537         vgt_perf_VGT_SPI_GSPRIM_EOV                      = 0xa,
5538         vgt_perf_VGT_SPI_GSPRIM_CONT                     = 0xb,
5539         vgt_perf_VGT_SPI_GSPRIM_STALLED                  = 0xc,
5540         vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY             = 0xd,
5541         vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE             = 0xe,
5542         vgt_perf_VGT_SPI_GSPRIM_STATIC                   = 0xf,
5543         vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE    = 0x10,
5544         vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT               = 0x11,
5545         vgt_perf_VGT_SPI_GSTHREAD_SEND                   = 0x12,
5546         vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE    = 0x13,
5547         vgt_perf_VGT_SPI_VSVERT_SEND                     = 0x14,
5548         vgt_perf_VGT_SPI_VSVERT_EOV                      = 0x15,
5549         vgt_perf_VGT_SPI_VSVERT_STALLED                  = 0x16,
5550         vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY             = 0x17,
5551         vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE             = 0x18,
5552         vgt_perf_VGT_SPI_VSVERT_STATIC                   = 0x19,
5553         vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT               = 0x1a,
5554         vgt_perf_VGT_SPI_VSTHREAD_SEND                   = 0x1b,
5555         vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE              = 0x1c,
5556         vgt_perf_VGT_PA_CLIPV_SEND                       = 0x1d,
5557         vgt_perf_VGT_PA_CLIPV_FIRSTVERT                  = 0x1e,
5558         vgt_perf_VGT_PA_CLIPV_STALLED                    = 0x1f,
5559         vgt_perf_VGT_PA_CLIPV_STARVED_BUSY               = 0x20,
5560         vgt_perf_VGT_PA_CLIPV_STARVED_IDLE               = 0x21,
5561         vgt_perf_VGT_PA_CLIPV_STATIC                     = 0x22,
5562         vgt_perf_VGT_PA_CLIPP_SEND                       = 0x23,
5563         vgt_perf_VGT_PA_CLIPP_EOP                        = 0x24,
5564         vgt_perf_VGT_PA_CLIPP_IS_EVENT                   = 0x25,
5565         vgt_perf_VGT_PA_CLIPP_NULL_PRIM                  = 0x26,
5566         vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT               = 0x27,
5567         vgt_perf_VGT_PA_CLIPP_STALLED                    = 0x28,
5568         vgt_perf_VGT_PA_CLIPP_STARVED_BUSY               = 0x29,
5569         vgt_perf_VGT_PA_CLIPP_STARVED_IDLE               = 0x2a,
5570         vgt_perf_VGT_PA_CLIPP_STATIC                     = 0x2b,
5571         vgt_perf_VGT_PA_CLIPS_SEND                       = 0x2c,
5572         vgt_perf_VGT_PA_CLIPS_STALLED                    = 0x2d,
5573         vgt_perf_VGT_PA_CLIPS_STARVED_BUSY               = 0x2e,
5574         vgt_perf_VGT_PA_CLIPS_STARVED_IDLE               = 0x2f,
5575         vgt_perf_VGT_PA_CLIPS_STATIC                     = 0x30,
5576         vgt_perf_vsvert_ds_send                          = 0x31,
5577         vgt_perf_vsvert_api_send                         = 0x32,
5578         vgt_perf_hs_tif_stall                            = 0x33,
5579         vgt_perf_hs_input_stall                          = 0x34,
5580         vgt_perf_hs_interface_stall                      = 0x35,
5581         vgt_perf_hs_tfm_stall                            = 0x36,
5582         vgt_perf_te11_starved                            = 0x37,
5583         vgt_perf_gs_event_stall                          = 0x38,
5584         vgt_perf_vgt_pa_clipp_send_not_event             = 0x39,
5585         vgt_perf_vgt_pa_clipp_valid_prim                 = 0x3a,
5586         vgt_perf_reused_es_indices                       = 0x3b,
5587         vgt_perf_vs_cache_hits                           = 0x3c,
5588         vgt_perf_gs_cache_hits                           = 0x3d,
5589         vgt_perf_ds_cache_hits                           = 0x3e,
5590         vgt_perf_total_cache_hits                        = 0x3f,
5591         vgt_perf_vgt_busy                                = 0x40,
5592         vgt_perf_vgt_gs_busy                             = 0x41,
5593         vgt_perf_esvert_stalled_es_tbl                   = 0x42,
5594         vgt_perf_esvert_stalled_gs_tbl                   = 0x43,
5595         vgt_perf_esvert_stalled_gs_event                 = 0x44,
5596         vgt_perf_esvert_stalled_gsprim                   = 0x45,
5597         vgt_perf_gsprim_stalled_es_tbl                   = 0x46,
5598         vgt_perf_gsprim_stalled_gs_tbl                   = 0x47,
5599         vgt_perf_gsprim_stalled_gs_event                 = 0x48,
5600         vgt_perf_gsprim_stalled_esvert                   = 0x49,
5601         vgt_perf_esthread_stalled_es_rb_full             = 0x4a,
5602         vgt_perf_esthread_stalled_spi_bp                 = 0x4b,
5603         vgt_perf_counters_avail_stalled                  = 0x4c,
5604         vgt_perf_gs_rb_space_avail_stalled               = 0x4d,
5605         vgt_perf_gs_issue_rtr_stalled                    = 0x4e,
5606         vgt_perf_gsthread_stalled                        = 0x4f,
5607         vgt_perf_strmout_stalled                         = 0x50,
5608         vgt_perf_wait_for_es_done_stalled                = 0x51,
5609         vgt_perf_cm_stalled_by_gog                       = 0x52,
5610         vgt_perf_cm_reading_stalled                      = 0x53,
5611         vgt_perf_cm_stalled_by_gsfetch_done              = 0x54,
5612         vgt_perf_gog_vs_tbl_stalled                      = 0x55,
5613         vgt_perf_gog_out_indx_stalled                    = 0x56,
5614         vgt_perf_gog_out_prim_stalled                    = 0x57,
5615         vgt_perf_waveid_stalled                          = 0x58,
5616         vgt_perf_gog_busy                                = 0x59,
5617         vgt_perf_reused_vs_indices                       = 0x5a,
5618         vgt_perf_sclk_reg_vld_event                      = 0x5b,
5619         vgt_perf_vs_conflicting_indices                  = 0x5c,
5620         vgt_perf_sclk_core_vld_event                     = 0x5d,
5621         vgt_perf_hswave_stalled                          = 0x5e,
5622         vgt_perf_sclk_gs_vld_event                       = 0x5f,
5623         vgt_perf_VGT_SPI_LSVERT_VALID                    = 0x60,
5624         vgt_perf_VGT_SPI_LSVERT_EOV                      = 0x61,
5625         vgt_perf_VGT_SPI_LSVERT_STALLED                  = 0x62,
5626         vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY             = 0x63,
5627         vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE             = 0x64,
5628         vgt_perf_VGT_SPI_LSVERT_STATIC                   = 0x65,
5629         vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE      = 0x66,
5630         vgt_perf_VGT_SPI_LSWAVE_IS_EVENT                 = 0x67,
5631         vgt_perf_VGT_SPI_LSWAVE_SEND                     = 0x68,
5632         vgt_perf_VGT_SPI_HSVERT_VALID                    = 0x69,
5633         vgt_perf_VGT_SPI_HSVERT_EOV                      = 0x6a,
5634         vgt_perf_VGT_SPI_HSVERT_STALLED                  = 0x6b,
5635         vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY             = 0x6c,
5636         vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE             = 0x6d,
5637         vgt_perf_VGT_SPI_HSVERT_STATIC                   = 0x6e,
5638         vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE      = 0x6f,
5639         vgt_perf_VGT_SPI_HSWAVE_IS_EVENT                 = 0x70,
5640         vgt_perf_VGT_SPI_HSWAVE_SEND                     = 0x71,
5641         vgt_perf_ds_prims                                = 0x72,
5642         vgt_perf_ls_thread_groups                        = 0x73,
5643         vgt_perf_hs_thread_groups                        = 0x74,
5644         vgt_perf_es_thread_groups                        = 0x75,
5645         vgt_perf_vs_thread_groups                        = 0x76,
5646         vgt_perf_ls_done_latency                         = 0x77,
5647         vgt_perf_hs_done_latency                         = 0x78,
5648         vgt_perf_es_done_latency                         = 0x79,
5649         vgt_perf_gs_done_latency                         = 0x7a,
5650         vgt_perf_vgt_hs_busy                             = 0x7b,
5651         vgt_perf_vgt_te11_busy                           = 0x7c,
5652         vgt_perf_ls_flush                                = 0x7d,
5653         vgt_perf_hs_flush                                = 0x7e,
5654         vgt_perf_es_flush                                = 0x7f,
5655         vgt_perf_vgt_pa_clipp_eopg                       = 0x80,
5656         vgt_perf_ls_done                                 = 0x81,
5657         vgt_perf_hs_done                                 = 0x82,
5658         vgt_perf_es_done                                 = 0x83,
5659         vgt_perf_gs_done                                 = 0x84,
5660         vgt_perf_vsfetch_done                            = 0x85,
5661         vgt_perf_gs_done_received                        = 0x86,
5662         vgt_perf_es_ring_high_water_mark                 = 0x87,
5663         vgt_perf_gs_ring_high_water_mark                 = 0x88,
5664         vgt_perf_vs_table_high_water_mark                = 0x89,
5665         vgt_perf_hs_tgs_active_high_water_mark           = 0x8a,
5666         vgt_perf_pa_clipp_dealloc                        = 0x8b,
5667         vgt_perf_cut_mem_flush_stalled                   = 0x8c,
5668         vgt_perf_vsvert_work_received                    = 0x8d,
5669         vgt_perf_vgt_pa_clipp_starved_after_work         = 0x8e,
5670         vgt_perf_te11_con_starved_after_work             = 0x8f,
5671         vgt_perf_hs_waiting_on_ls_done_stall             = 0x90,
5672         vgt_spi_vsvert_valid                             = 0x91,
5673 } VGT_PERFCOUNT_SELECT;
5674 typedef enum IA_PERFCOUNT_SELECT {
5675         ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE            = 0x0,
5676         ia_perf_dma_data_fifo_full                       = 0x1,
5677         ia_perf_RESERVED1                                = 0x2,
5678         ia_perf_RESERVED2                                = 0x3,
5679         ia_perf_RESERVED3                                = 0x4,
5680         ia_perf_RESERVED4                                = 0x5,
5681         ia_perf_RESERVED5                                = 0x6,
5682         ia_perf_MC_LAT_BIN_0                             = 0x7,
5683         ia_perf_MC_LAT_BIN_1                             = 0x8,
5684         ia_perf_MC_LAT_BIN_2                             = 0x9,
5685         ia_perf_MC_LAT_BIN_3                             = 0xa,
5686         ia_perf_MC_LAT_BIN_4                             = 0xb,
5687         ia_perf_MC_LAT_BIN_5                             = 0xc,
5688         ia_perf_MC_LAT_BIN_6                             = 0xd,
5689         ia_perf_MC_LAT_BIN_7                             = 0xe,
5690         ia_perf_ia_busy                                  = 0xf,
5691         ia_perf_ia_sclk_reg_vld_event                    = 0x10,
5692         ia_perf_RESERVED6                                = 0x11,
5693         ia_perf_ia_sclk_core_vld_event                   = 0x12,
5694         ia_perf_RESERVED7                                = 0x13,
5695         ia_perf_ia_dma_return                            = 0x14,
5696         ia_perf_ia_stalled                               = 0x15,
5697         ia_perf_shift_starved_pipe0_event                = 0x16,
5698         ia_perf_shift_starved_pipe1_event                = 0x17,
5699 } IA_PERFCOUNT_SELECT;
5700 typedef enum WD_PERFCOUNT_SELECT {
5701         wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE           = 0x0,
5702         wd_perf_RBIU_DR_FIFO_STARVED                     = 0x1,
5703         wd_perf_RBIU_DR_FIFO_STALLED                     = 0x2,
5704         wd_perf_RBIU_DI_FIFO_STARVED                     = 0x3,
5705         wd_perf_RBIU_DI_FIFO_STALLED                     = 0x4,
5706         wd_perf_wd_busy                                  = 0x5,
5707         wd_perf_wd_sclk_reg_vld_event                    = 0x6,
5708         wd_perf_wd_sclk_input_vld_event                  = 0x7,
5709         wd_perf_wd_sclk_core_vld_event                   = 0x8,
5710         wd_perf_wd_stalled                               = 0x9,
5711         wd_perf_inside_tf_bin_0                          = 0xa,
5712         wd_perf_inside_tf_bin_1                          = 0xb,
5713         wd_perf_inside_tf_bin_2                          = 0xc,
5714         wd_perf_inside_tf_bin_3                          = 0xd,
5715         wd_perf_inside_tf_bin_4                          = 0xe,
5716         wd_perf_inside_tf_bin_5                          = 0xf,
5717         wd_perf_inside_tf_bin_6                          = 0x10,
5718         wd_perf_inside_tf_bin_7                          = 0x11,
5719         wd_perf_inside_tf_bin_8                          = 0x12,
5720         wd_perf_tfreq_lat_bin_0                          = 0x13,
5721         wd_perf_tfreq_lat_bin_1                          = 0x14,
5722         wd_perf_tfreq_lat_bin_2                          = 0x15,
5723         wd_perf_tfreq_lat_bin_3                          = 0x16,
5724         wd_perf_tfreq_lat_bin_4                          = 0x17,
5725         wd_perf_tfreq_lat_bin_5                          = 0x18,
5726         wd_perf_tfreq_lat_bin_6                          = 0x19,
5727         wd_perf_tfreq_lat_bin_7                          = 0x1a,
5728         wd_starved_on_hs_done                            = 0x1b,
5729         wd_perf_se0_hs_done_latency                      = 0x1c,
5730         wd_perf_se1_hs_done_latency                      = 0x1d,
5731         wd_perf_se2_hs_done_latency                      = 0x1e,
5732         wd_perf_se3_hs_done_latency                      = 0x1f,
5733         wd_perf_hs_done_se0                              = 0x20,
5734         wd_perf_hs_done_se1                              = 0x21,
5735         wd_perf_hs_done_se2                              = 0x22,
5736         wd_perf_hs_done_se3                              = 0x23,
5737         wd_perf_null_patches                             = 0x24,
5738 } WD_PERFCOUNT_SELECT;
5739 typedef enum WD_IA_DRAW_TYPE {
5740         WD_IA_DRAW_TYPE_DI_MM0                           = 0x0,
5741         WD_IA_DRAW_TYPE_DI_MM1                           = 0x1,
5742         WD_IA_DRAW_TYPE_EVENT_INIT                       = 0x2,
5743         WD_IA_DRAW_TYPE_EVENT_ADDR                       = 0x3,
5744         WD_IA_DRAW_TYPE_MIN_INDX                         = 0x4,
5745         WD_IA_DRAW_TYPE_MAX_INDX                         = 0x5,
5746         WD_IA_DRAW_TYPE_INDX_OFF                         = 0x6,
5747         WD_IA_DRAW_TYPE_IMM_DATA                         = 0x7,
5748 } WD_IA_DRAW_TYPE;
5749 typedef enum WD_IA_DRAW_SOURCE {
5750         WD_IA_DRAW_SOURCE_DMA                            = 0x0,
5751         WD_IA_DRAW_SOURCE_IMMD                           = 0x1,
5752         WD_IA_DRAW_SOURCE_AUTO                           = 0x2,
5753         WD_IA_DRAW_SOURCE_OPAQ                           = 0x3,
5754 } WD_IA_DRAW_SOURCE;
5755 #define GSTHREADID_SIZE                           0x2
5756 typedef enum DebugBlockId {
5757         DBG_BLOCK_ID_RESERVED                            = 0x0,
5758         DBG_BLOCK_ID_DBG                                 = 0x1,
5759         DBG_BLOCK_ID_VMC                                 = 0x2,
5760         DBG_BLOCK_ID_PDMA                                = 0x3,
5761         DBG_BLOCK_ID_CG                                  = 0x4,
5762         DBG_BLOCK_ID_SRBM                                = 0x5,
5763         DBG_BLOCK_ID_GRBM                                = 0x6,
5764         DBG_BLOCK_ID_RLC                                 = 0x7,
5765         DBG_BLOCK_ID_CSC                                 = 0x8,
5766         DBG_BLOCK_ID_SEM                                 = 0x9,
5767         DBG_BLOCK_ID_IH                                  = 0xa,
5768         DBG_BLOCK_ID_SC                                  = 0xb,
5769         DBG_BLOCK_ID_SQ                                  = 0xc,
5770         DBG_BLOCK_ID_UVDU                                = 0xd,
5771         DBG_BLOCK_ID_SQA                                 = 0xe,
5772         DBG_BLOCK_ID_SDMA0                               = 0xf,
5773         DBG_BLOCK_ID_SDMA1                               = 0x10,
5774         DBG_BLOCK_ID_SPIM                                = 0x11,
5775         DBG_BLOCK_ID_GDS                                 = 0x12,
5776         DBG_BLOCK_ID_VC0                                 = 0x13,
5777         DBG_BLOCK_ID_VC1                                 = 0x14,
5778         DBG_BLOCK_ID_PA0                                 = 0x15,
5779         DBG_BLOCK_ID_PA1                                 = 0x16,
5780         DBG_BLOCK_ID_CP0                                 = 0x17,
5781         DBG_BLOCK_ID_CP1                                 = 0x18,
5782         DBG_BLOCK_ID_CP2                                 = 0x19,
5783         DBG_BLOCK_ID_XBR                                 = 0x1a,
5784         DBG_BLOCK_ID_UVDM                                = 0x1b,
5785         DBG_BLOCK_ID_VGT0                                = 0x1c,
5786         DBG_BLOCK_ID_VGT1                                = 0x1d,
5787         DBG_BLOCK_ID_IA                                  = 0x1e,
5788         DBG_BLOCK_ID_SXM0                                = 0x1f,
5789         DBG_BLOCK_ID_SXM1                                = 0x20,
5790         DBG_BLOCK_ID_SCT0                                = 0x21,
5791         DBG_BLOCK_ID_SCT1                                = 0x22,
5792         DBG_BLOCK_ID_SPM0                                = 0x23,
5793         DBG_BLOCK_ID_SPM1                                = 0x24,
5794         DBG_BLOCK_ID_UNUSED0                             = 0x25,
5795         DBG_BLOCK_ID_UNUSED1                             = 0x26,
5796         DBG_BLOCK_ID_TCAA                                = 0x27,
5797         DBG_BLOCK_ID_TCAB                                = 0x28,
5798         DBG_BLOCK_ID_TCCA                                = 0x29,
5799         DBG_BLOCK_ID_TCCB                                = 0x2a,
5800         DBG_BLOCK_ID_MCC0                                = 0x2b,
5801         DBG_BLOCK_ID_MCC1                                = 0x2c,
5802         DBG_BLOCK_ID_MCC2                                = 0x2d,
5803         DBG_BLOCK_ID_MCC3                                = 0x2e,
5804         DBG_BLOCK_ID_SXS0                                = 0x2f,
5805         DBG_BLOCK_ID_SXS1                                = 0x30,
5806         DBG_BLOCK_ID_SXS2                                = 0x31,
5807         DBG_BLOCK_ID_SXS3                                = 0x32,
5808         DBG_BLOCK_ID_SXS4                                = 0x33,
5809         DBG_BLOCK_ID_SXS5                                = 0x34,
5810         DBG_BLOCK_ID_SXS6                                = 0x35,
5811         DBG_BLOCK_ID_SXS7                                = 0x36,
5812         DBG_BLOCK_ID_SXS8                                = 0x37,
5813         DBG_BLOCK_ID_SXS9                                = 0x38,
5814         DBG_BLOCK_ID_BCI0                                = 0x39,
5815         DBG_BLOCK_ID_BCI1                                = 0x3a,
5816         DBG_BLOCK_ID_BCI2                                = 0x3b,
5817         DBG_BLOCK_ID_BCI3                                = 0x3c,
5818         DBG_BLOCK_ID_MCB                                 = 0x3d,
5819         DBG_BLOCK_ID_UNUSED6                             = 0x3e,
5820         DBG_BLOCK_ID_SQA00                               = 0x3f,
5821         DBG_BLOCK_ID_SQA01                               = 0x40,
5822         DBG_BLOCK_ID_SQA02                               = 0x41,
5823         DBG_BLOCK_ID_SQA10                               = 0x42,
5824         DBG_BLOCK_ID_SQA11                               = 0x43,
5825         DBG_BLOCK_ID_SQA12                               = 0x44,
5826         DBG_BLOCK_ID_UNUSED7                             = 0x45,
5827         DBG_BLOCK_ID_UNUSED8                             = 0x46,
5828         DBG_BLOCK_ID_SQB00                               = 0x47,
5829         DBG_BLOCK_ID_SQB01                               = 0x48,
5830         DBG_BLOCK_ID_SQB10                               = 0x49,
5831         DBG_BLOCK_ID_SQB11                               = 0x4a,
5832         DBG_BLOCK_ID_SQ00                                = 0x4b,
5833         DBG_BLOCK_ID_SQ01                                = 0x4c,
5834         DBG_BLOCK_ID_SQ10                                = 0x4d,
5835         DBG_BLOCK_ID_SQ11                                = 0x4e,
5836         DBG_BLOCK_ID_CB00                                = 0x4f,
5837         DBG_BLOCK_ID_CB01                                = 0x50,
5838         DBG_BLOCK_ID_CB02                                = 0x51,
5839         DBG_BLOCK_ID_CB03                                = 0x52,
5840         DBG_BLOCK_ID_CB04                                = 0x53,
5841         DBG_BLOCK_ID_UNUSED9                             = 0x54,
5842         DBG_BLOCK_ID_UNUSED10                            = 0x55,
5843         DBG_BLOCK_ID_UNUSED11                            = 0x56,
5844         DBG_BLOCK_ID_CB10                                = 0x57,
5845         DBG_BLOCK_ID_CB11                                = 0x58,
5846         DBG_BLOCK_ID_CB12                                = 0x59,
5847         DBG_BLOCK_ID_CB13                                = 0x5a,
5848         DBG_BLOCK_ID_CB14                                = 0x5b,
5849         DBG_BLOCK_ID_UNUSED12                            = 0x5c,
5850         DBG_BLOCK_ID_UNUSED13                            = 0x5d,
5851         DBG_BLOCK_ID_UNUSED14                            = 0x5e,
5852         DBG_BLOCK_ID_TCP0                                = 0x5f,
5853         DBG_BLOCK_ID_TCP1                                = 0x60,
5854         DBG_BLOCK_ID_TCP2                                = 0x61,
5855         DBG_BLOCK_ID_TCP3                                = 0x62,
5856         DBG_BLOCK_ID_TCP4                                = 0x63,
5857         DBG_BLOCK_ID_TCP5                                = 0x64,
5858         DBG_BLOCK_ID_TCP6                                = 0x65,
5859         DBG_BLOCK_ID_TCP7                                = 0x66,
5860         DBG_BLOCK_ID_TCP8                                = 0x67,
5861         DBG_BLOCK_ID_TCP9                                = 0x68,
5862         DBG_BLOCK_ID_TCP10                               = 0x69,
5863         DBG_BLOCK_ID_TCP11                               = 0x6a,
5864         DBG_BLOCK_ID_TCP12                               = 0x6b,
5865         DBG_BLOCK_ID_TCP13                               = 0x6c,
5866         DBG_BLOCK_ID_TCP14                               = 0x6d,
5867         DBG_BLOCK_ID_TCP15                               = 0x6e,
5868         DBG_BLOCK_ID_TCP16                               = 0x6f,
5869         DBG_BLOCK_ID_TCP17                               = 0x70,
5870         DBG_BLOCK_ID_TCP18                               = 0x71,
5871         DBG_BLOCK_ID_TCP19                               = 0x72,
5872         DBG_BLOCK_ID_TCP20                               = 0x73,
5873         DBG_BLOCK_ID_TCP21                               = 0x74,
5874         DBG_BLOCK_ID_TCP22                               = 0x75,
5875         DBG_BLOCK_ID_TCP23                               = 0x76,
5876         DBG_BLOCK_ID_TCP_RESERVED0                       = 0x77,
5877         DBG_BLOCK_ID_TCP_RESERVED1                       = 0x78,
5878         DBG_BLOCK_ID_TCP_RESERVED2                       = 0x79,
5879         DBG_BLOCK_ID_TCP_RESERVED3                       = 0x7a,
5880         DBG_BLOCK_ID_TCP_RESERVED4                       = 0x7b,
5881         DBG_BLOCK_ID_TCP_RESERVED5                       = 0x7c,
5882         DBG_BLOCK_ID_TCP_RESERVED6                       = 0x7d,
5883         DBG_BLOCK_ID_TCP_RESERVED7                       = 0x7e,
5884         DBG_BLOCK_ID_DB00                                = 0x7f,
5885         DBG_BLOCK_ID_DB01                                = 0x80,
5886         DBG_BLOCK_ID_DB02                                = 0x81,
5887         DBG_BLOCK_ID_DB03                                = 0x82,
5888         DBG_BLOCK_ID_DB04                                = 0x83,
5889         DBG_BLOCK_ID_UNUSED15                            = 0x84,
5890         DBG_BLOCK_ID_UNUSED16                            = 0x85,
5891         DBG_BLOCK_ID_UNUSED17                            = 0x86,
5892         DBG_BLOCK_ID_DB10                                = 0x87,
5893         DBG_BLOCK_ID_DB11                                = 0x88,
5894         DBG_BLOCK_ID_DB12                                = 0x89,
5895         DBG_BLOCK_ID_DB13                                = 0x8a,
5896         DBG_BLOCK_ID_DB14                                = 0x8b,
5897         DBG_BLOCK_ID_UNUSED18                            = 0x8c,
5898         DBG_BLOCK_ID_UNUSED19                            = 0x8d,
5899         DBG_BLOCK_ID_UNUSED20                            = 0x8e,
5900         DBG_BLOCK_ID_TCC0                                = 0x8f,
5901         DBG_BLOCK_ID_TCC1                                = 0x90,
5902         DBG_BLOCK_ID_TCC2                                = 0x91,
5903         DBG_BLOCK_ID_TCC3                                = 0x92,
5904         DBG_BLOCK_ID_TCC4                                = 0x93,
5905         DBG_BLOCK_ID_TCC5                                = 0x94,
5906         DBG_BLOCK_ID_TCC6                                = 0x95,
5907         DBG_BLOCK_ID_TCC7                                = 0x96,
5908         DBG_BLOCK_ID_SPS00                               = 0x97,
5909         DBG_BLOCK_ID_SPS01                               = 0x98,
5910         DBG_BLOCK_ID_SPS02                               = 0x99,
5911         DBG_BLOCK_ID_SPS10                               = 0x9a,
5912         DBG_BLOCK_ID_SPS11                               = 0x9b,
5913         DBG_BLOCK_ID_SPS12                               = 0x9c,
5914         DBG_BLOCK_ID_UNUSED21                            = 0x9d,
5915         DBG_BLOCK_ID_UNUSED22                            = 0x9e,
5916         DBG_BLOCK_ID_TA00                                = 0x9f,
5917         DBG_BLOCK_ID_TA01                                = 0xa0,
5918         DBG_BLOCK_ID_TA02                                = 0xa1,
5919         DBG_BLOCK_ID_TA03                                = 0xa2,
5920         DBG_BLOCK_ID_TA04                                = 0xa3,
5921         DBG_BLOCK_ID_TA05                                = 0xa4,
5922         DBG_BLOCK_ID_TA06                                = 0xa5,
5923         DBG_BLOCK_ID_TA07                                = 0xa6,
5924         DBG_BLOCK_ID_TA08                                = 0xa7,
5925         DBG_BLOCK_ID_TA09                                = 0xa8,
5926         DBG_BLOCK_ID_TA0A                                = 0xa9,
5927         DBG_BLOCK_ID_TA0B                                = 0xaa,
5928         DBG_BLOCK_ID_UNUSED23                            = 0xab,
5929         DBG_BLOCK_ID_UNUSED24                            = 0xac,
5930         DBG_BLOCK_ID_UNUSED25                            = 0xad,
5931         DBG_BLOCK_ID_UNUSED26                            = 0xae,
5932         DBG_BLOCK_ID_TA10                                = 0xaf,
5933         DBG_BLOCK_ID_TA11                                = 0xb0,
5934         DBG_BLOCK_ID_TA12                                = 0xb1,
5935         DBG_BLOCK_ID_TA13                                = 0xb2,
5936         DBG_BLOCK_ID_TA14                                = 0xb3,
5937         DBG_BLOCK_ID_TA15                                = 0xb4,
5938         DBG_BLOCK_ID_TA16                                = 0xb5,
5939         DBG_BLOCK_ID_TA17                                = 0xb6,
5940         DBG_BLOCK_ID_TA18                                = 0xb7,
5941         DBG_BLOCK_ID_TA19                                = 0xb8,
5942         DBG_BLOCK_ID_TA1A                                = 0xb9,
5943         DBG_BLOCK_ID_TA1B                                = 0xba,
5944         DBG_BLOCK_ID_UNUSED27                            = 0xbb,
5945         DBG_BLOCK_ID_UNUSED28                            = 0xbc,
5946         DBG_BLOCK_ID_UNUSED29                            = 0xbd,
5947         DBG_BLOCK_ID_UNUSED30                            = 0xbe,
5948         DBG_BLOCK_ID_TD00                                = 0xbf,
5949         DBG_BLOCK_ID_TD01                                = 0xc0,
5950         DBG_BLOCK_ID_TD02                                = 0xc1,
5951         DBG_BLOCK_ID_TD03                                = 0xc2,
5952         DBG_BLOCK_ID_TD04                                = 0xc3,
5953         DBG_BLOCK_ID_TD05                                = 0xc4,
5954         DBG_BLOCK_ID_TD06                                = 0xc5,
5955         DBG_BLOCK_ID_TD07                                = 0xc6,
5956         DBG_BLOCK_ID_TD08                                = 0xc7,
5957         DBG_BLOCK_ID_TD09                                = 0xc8,
5958         DBG_BLOCK_ID_TD0A                                = 0xc9,
5959         DBG_BLOCK_ID_TD0B                                = 0xca,
5960         DBG_BLOCK_ID_UNUSED31                            = 0xcb,
5961         DBG_BLOCK_ID_UNUSED32                            = 0xcc,
5962         DBG_BLOCK_ID_UNUSED33                            = 0xcd,
5963         DBG_BLOCK_ID_UNUSED34                            = 0xce,
5964         DBG_BLOCK_ID_TD10                                = 0xcf,
5965         DBG_BLOCK_ID_TD11                                = 0xd0,
5966         DBG_BLOCK_ID_TD12                                = 0xd1,
5967         DBG_BLOCK_ID_TD13                                = 0xd2,
5968         DBG_BLOCK_ID_TD14                                = 0xd3,
5969         DBG_BLOCK_ID_TD15                                = 0xd4,
5970         DBG_BLOCK_ID_TD16                                = 0xd5,
5971         DBG_BLOCK_ID_TD17                                = 0xd6,
5972         DBG_BLOCK_ID_TD18                                = 0xd7,
5973         DBG_BLOCK_ID_TD19                                = 0xd8,
5974         DBG_BLOCK_ID_TD1A                                = 0xd9,
5975         DBG_BLOCK_ID_TD1B                                = 0xda,
5976         DBG_BLOCK_ID_UNUSED35                            = 0xdb,
5977         DBG_BLOCK_ID_UNUSED36                            = 0xdc,
5978         DBG_BLOCK_ID_UNUSED37                            = 0xdd,
5979         DBG_BLOCK_ID_UNUSED38                            = 0xde,
5980         DBG_BLOCK_ID_LDS00                               = 0xdf,
5981         DBG_BLOCK_ID_LDS01                               = 0xe0,
5982         DBG_BLOCK_ID_LDS02                               = 0xe1,
5983         DBG_BLOCK_ID_LDS03                               = 0xe2,
5984         DBG_BLOCK_ID_LDS04                               = 0xe3,
5985         DBG_BLOCK_ID_LDS05                               = 0xe4,
5986         DBG_BLOCK_ID_LDS06                               = 0xe5,
5987         DBG_BLOCK_ID_LDS07                               = 0xe6,
5988         DBG_BLOCK_ID_LDS08                               = 0xe7,
5989         DBG_BLOCK_ID_LDS09                               = 0xe8,
5990         DBG_BLOCK_ID_LDS0A                               = 0xe9,
5991         DBG_BLOCK_ID_LDS0B                               = 0xea,
5992         DBG_BLOCK_ID_UNUSED39                            = 0xeb,
5993         DBG_BLOCK_ID_UNUSED40                            = 0xec,
5994         DBG_BLOCK_ID_UNUSED41                            = 0xed,
5995         DBG_BLOCK_ID_UNUSED42                            = 0xee,
5996         DBG_BLOCK_ID_LDS10                               = 0xef,
5997         DBG_BLOCK_ID_LDS11                               = 0xf0,
5998         DBG_BLOCK_ID_LDS12                               = 0xf1,
5999         DBG_BLOCK_ID_LDS13                               = 0xf2,
6000         DBG_BLOCK_ID_LDS14                               = 0xf3,
6001         DBG_BLOCK_ID_LDS15                               = 0xf4,
6002         DBG_BLOCK_ID_LDS16                               = 0xf5,
6003         DBG_BLOCK_ID_LDS17                               = 0xf6,
6004         DBG_BLOCK_ID_LDS18                               = 0xf7,
6005         DBG_BLOCK_ID_LDS19                               = 0xf8,
6006         DBG_BLOCK_ID_LDS1A                               = 0xf9,
6007         DBG_BLOCK_ID_LDS1B                               = 0xfa,
6008         DBG_BLOCK_ID_UNUSED43                            = 0xfb,
6009         DBG_BLOCK_ID_UNUSED44                            = 0xfc,
6010         DBG_BLOCK_ID_UNUSED45                            = 0xfd,
6011         DBG_BLOCK_ID_UNUSED46                            = 0xfe,
6012 } DebugBlockId;
6013 typedef enum DebugBlockId_BY2 {
6014         DBG_BLOCK_ID_RESERVED_BY2                        = 0x0,
6015         DBG_BLOCK_ID_VMC_BY2                             = 0x1,
6016         DBG_BLOCK_ID_UNUSED0_BY2                         = 0x2,
6017         DBG_BLOCK_ID_GRBM_BY2                            = 0x3,
6018         DBG_BLOCK_ID_CSC_BY2                             = 0x4,
6019         DBG_BLOCK_ID_IH_BY2                              = 0x5,
6020         DBG_BLOCK_ID_SQ_BY2                              = 0x6,
6021         DBG_BLOCK_ID_UVD_BY2                             = 0x7,
6022         DBG_BLOCK_ID_SDMA0_BY2                           = 0x8,
6023         DBG_BLOCK_ID_SPIM_BY2                            = 0x9,
6024         DBG_BLOCK_ID_VC0_BY2                             = 0xa,
6025         DBG_BLOCK_ID_PA_BY2                              = 0xb,
6026         DBG_BLOCK_ID_CP0_BY2                             = 0xc,
6027         DBG_BLOCK_ID_CP2_BY2                             = 0xd,
6028         DBG_BLOCK_ID_PC0_BY2                             = 0xe,
6029         DBG_BLOCK_ID_BCI0_BY2                            = 0xf,
6030         DBG_BLOCK_ID_SXM0_BY2                            = 0x10,
6031         DBG_BLOCK_ID_SCT0_BY2                            = 0x11,
6032         DBG_BLOCK_ID_SPM0_BY2                            = 0x12,
6033         DBG_BLOCK_ID_BCI2_BY2                            = 0x13,
6034         DBG_BLOCK_ID_TCA_BY2                             = 0x14,
6035         DBG_BLOCK_ID_TCCA_BY2                            = 0x15,
6036         DBG_BLOCK_ID_MCC_BY2                             = 0x16,
6037         DBG_BLOCK_ID_MCC2_BY2                            = 0x17,
6038         DBG_BLOCK_ID_MCD_BY2                             = 0x18,
6039         DBG_BLOCK_ID_MCD2_BY2                            = 0x19,
6040         DBG_BLOCK_ID_MCD4_BY2                            = 0x1a,
6041         DBG_BLOCK_ID_MCB_BY2                             = 0x1b,
6042         DBG_BLOCK_ID_SQA_BY2                             = 0x1c,
6043         DBG_BLOCK_ID_SQA02_BY2                           = 0x1d,
6044         DBG_BLOCK_ID_SQA11_BY2                           = 0x1e,
6045         DBG_BLOCK_ID_UNUSED8_BY2                         = 0x1f,
6046         DBG_BLOCK_ID_SQB_BY2                             = 0x20,
6047         DBG_BLOCK_ID_SQB10_BY2                           = 0x21,
6048         DBG_BLOCK_ID_UNUSED10_BY2                        = 0x22,
6049         DBG_BLOCK_ID_UNUSED12_BY2                        = 0x23,
6050         DBG_BLOCK_ID_CB_BY2                              = 0x24,
6051         DBG_BLOCK_ID_CB02_BY2                            = 0x25,
6052         DBG_BLOCK_ID_CB10_BY2                            = 0x26,
6053         DBG_BLOCK_ID_CB12_BY2                            = 0x27,
6054         DBG_BLOCK_ID_SXS_BY2                             = 0x28,
6055         DBG_BLOCK_ID_SXS2_BY2                            = 0x29,
6056         DBG_BLOCK_ID_SXS4_BY2                            = 0x2a,
6057         DBG_BLOCK_ID_SXS6_BY2                            = 0x2b,
6058         DBG_BLOCK_ID_DB_BY2                              = 0x2c,
6059         DBG_BLOCK_ID_DB02_BY2                            = 0x2d,
6060         DBG_BLOCK_ID_DB10_BY2                            = 0x2e,
6061         DBG_BLOCK_ID_DB12_BY2                            = 0x2f,
6062         DBG_BLOCK_ID_TCP_BY2                             = 0x30,
6063         DBG_BLOCK_ID_TCP2_BY2                            = 0x31,
6064         DBG_BLOCK_ID_TCP4_BY2                            = 0x32,
6065         DBG_BLOCK_ID_TCP6_BY2                            = 0x33,
6066         DBG_BLOCK_ID_TCP8_BY2                            = 0x34,
6067         DBG_BLOCK_ID_TCP10_BY2                           = 0x35,
6068         DBG_BLOCK_ID_TCP12_BY2                           = 0x36,
6069         DBG_BLOCK_ID_TCP14_BY2                           = 0x37,
6070         DBG_BLOCK_ID_TCP16_BY2                           = 0x38,
6071         DBG_BLOCK_ID_TCP18_BY2                           = 0x39,
6072         DBG_BLOCK_ID_TCP20_BY2                           = 0x3a,
6073         DBG_BLOCK_ID_TCP22_BY2                           = 0x3b,
6074         DBG_BLOCK_ID_TCP_RESERVED0_BY2                   = 0x3c,
6075         DBG_BLOCK_ID_TCP_RESERVED2_BY2                   = 0x3d,
6076         DBG_BLOCK_ID_TCP_RESERVED4_BY2                   = 0x3e,
6077         DBG_BLOCK_ID_TCP_RESERVED6_BY2                   = 0x3f,
6078         DBG_BLOCK_ID_TCC_BY2                             = 0x40,
6079         DBG_BLOCK_ID_TCC2_BY2                            = 0x41,
6080         DBG_BLOCK_ID_TCC4_BY2                            = 0x42,
6081         DBG_BLOCK_ID_TCC6_BY2                            = 0x43,
6082         DBG_BLOCK_ID_SPS_BY2                             = 0x44,
6083         DBG_BLOCK_ID_SPS02_BY2                           = 0x45,
6084         DBG_BLOCK_ID_SPS11_BY2                           = 0x46,
6085         DBG_BLOCK_ID_UNUSED14_BY2                        = 0x47,
6086         DBG_BLOCK_ID_TA_BY2                              = 0x48,
6087         DBG_BLOCK_ID_TA02_BY2                            = 0x49,
6088         DBG_BLOCK_ID_TA04_BY2                            = 0x4a,
6089         DBG_BLOCK_ID_TA06_BY2                            = 0x4b,
6090         DBG_BLOCK_ID_TA08_BY2                            = 0x4c,
6091         DBG_BLOCK_ID_TA0A_BY2                            = 0x4d,
6092         DBG_BLOCK_ID_UNUSED20_BY2                        = 0x4e,
6093         DBG_BLOCK_ID_UNUSED22_BY2                        = 0x4f,
6094         DBG_BLOCK_ID_TA10_BY2                            = 0x50,
6095         DBG_BLOCK_ID_TA12_BY2                            = 0x51,
6096         DBG_BLOCK_ID_TA14_BY2                            = 0x52,
6097         DBG_BLOCK_ID_TA16_BY2                            = 0x53,
6098         DBG_BLOCK_ID_TA18_BY2                            = 0x54,
6099         DBG_BLOCK_ID_TA1A_BY2                            = 0x55,
6100         DBG_BLOCK_ID_UNUSED24_BY2                        = 0x56,
6101         DBG_BLOCK_ID_UNUSED26_BY2                        = 0x57,
6102         DBG_BLOCK_ID_TD_BY2                              = 0x58,
6103         DBG_BLOCK_ID_TD02_BY2                            = 0x59,
6104         DBG_BLOCK_ID_TD04_BY2                            = 0x5a,
6105         DBG_BLOCK_ID_TD06_BY2                            = 0x5b,
6106         DBG_BLOCK_ID_TD08_BY2                            = 0x5c,
6107         DBG_BLOCK_ID_TD0A_BY2                            = 0x5d,
6108         DBG_BLOCK_ID_UNUSED28_BY2                        = 0x5e,
6109         DBG_BLOCK_ID_UNUSED30_BY2                        = 0x5f,
6110         DBG_BLOCK_ID_TD10_BY2                            = 0x60,
6111         DBG_BLOCK_ID_TD12_BY2                            = 0x61,
6112         DBG_BLOCK_ID_TD14_BY2                            = 0x62,
6113         DBG_BLOCK_ID_TD16_BY2                            = 0x63,
6114         DBG_BLOCK_ID_TD18_BY2                            = 0x64,
6115         DBG_BLOCK_ID_TD1A_BY2                            = 0x65,
6116         DBG_BLOCK_ID_UNUSED32_BY2                        = 0x66,
6117         DBG_BLOCK_ID_UNUSED34_BY2                        = 0x67,
6118         DBG_BLOCK_ID_LDS_BY2                             = 0x68,
6119         DBG_BLOCK_ID_LDS02_BY2                           = 0x69,
6120         DBG_BLOCK_ID_LDS04_BY2                           = 0x6a,
6121         DBG_BLOCK_ID_LDS06_BY2                           = 0x6b,
6122         DBG_BLOCK_ID_LDS08_BY2                           = 0x6c,
6123         DBG_BLOCK_ID_LDS0A_BY2                           = 0x6d,
6124         DBG_BLOCK_ID_UNUSED36_BY2                        = 0x6e,
6125         DBG_BLOCK_ID_UNUSED38_BY2                        = 0x6f,
6126         DBG_BLOCK_ID_LDS10_BY2                           = 0x70,
6127         DBG_BLOCK_ID_LDS12_BY2                           = 0x71,
6128         DBG_BLOCK_ID_LDS14_BY2                           = 0x72,
6129         DBG_BLOCK_ID_LDS16_BY2                           = 0x73,
6130         DBG_BLOCK_ID_LDS18_BY2                           = 0x74,
6131         DBG_BLOCK_ID_LDS1A_BY2                           = 0x75,
6132         DBG_BLOCK_ID_UNUSED40_BY2                        = 0x76,
6133         DBG_BLOCK_ID_UNUSED42_BY2                        = 0x77,
6134 } DebugBlockId_BY2;
6135 typedef enum DebugBlockId_BY4 {
6136         DBG_BLOCK_ID_RESERVED_BY4                        = 0x0,
6137         DBG_BLOCK_ID_UNUSED0_BY4                         = 0x1,
6138         DBG_BLOCK_ID_CSC_BY4                             = 0x2,
6139         DBG_BLOCK_ID_SQ_BY4                              = 0x3,
6140         DBG_BLOCK_ID_SDMA0_BY4                           = 0x4,
6141         DBG_BLOCK_ID_VC0_BY4                             = 0x5,
6142         DBG_BLOCK_ID_CP0_BY4                             = 0x6,
6143         DBG_BLOCK_ID_UNUSED1_BY4                         = 0x7,
6144         DBG_BLOCK_ID_SXM0_BY4                            = 0x8,
6145         DBG_BLOCK_ID_SPM0_BY4                            = 0x9,
6146         DBG_BLOCK_ID_TCAA_BY4                            = 0xa,
6147         DBG_BLOCK_ID_MCC_BY4                             = 0xb,
6148         DBG_BLOCK_ID_MCD_BY4                             = 0xc,
6149         DBG_BLOCK_ID_MCD4_BY4                            = 0xd,
6150         DBG_BLOCK_ID_SQA_BY4                             = 0xe,
6151         DBG_BLOCK_ID_SQA11_BY4                           = 0xf,
6152         DBG_BLOCK_ID_SQB_BY4                             = 0x10,
6153         DBG_BLOCK_ID_UNUSED10_BY4                        = 0x11,
6154         DBG_BLOCK_ID_CB_BY4                              = 0x12,
6155         DBG_BLOCK_ID_CB10_BY4                            = 0x13,
6156         DBG_BLOCK_ID_SXS_BY4                             = 0x14,
6157         DBG_BLOCK_ID_SXS4_BY4                            = 0x15,
6158         DBG_BLOCK_ID_DB_BY4                              = 0x16,
6159         DBG_BLOCK_ID_DB10_BY4                            = 0x17,
6160         DBG_BLOCK_ID_TCP_BY4                             = 0x18,
6161         DBG_BLOCK_ID_TCP4_BY4                            = 0x19,
6162         DBG_BLOCK_ID_TCP8_BY4                            = 0x1a,
6163         DBG_BLOCK_ID_TCP12_BY4                           = 0x1b,
6164         DBG_BLOCK_ID_TCP16_BY4                           = 0x1c,
6165         DBG_BLOCK_ID_TCP20_BY4                           = 0x1d,
6166         DBG_BLOCK_ID_TCP_RESERVED0_BY4                   = 0x1e,
6167         DBG_BLOCK_ID_TCP_RESERVED4_BY4                   = 0x1f,
6168         DBG_BLOCK_ID_TCC_BY4                             = 0x20,
6169         DBG_BLOCK_ID_TCC4_BY4                            = 0x21,
6170         DBG_BLOCK_ID_SPS_BY4                             = 0x22,
6171         DBG_BLOCK_ID_SPS11_BY4                           = 0x23,
6172         DBG_BLOCK_ID_TA_BY4                              = 0x24,
6173         DBG_BLOCK_ID_TA04_BY4                            = 0x25,
6174         DBG_BLOCK_ID_TA08_BY4                            = 0x26,
6175         DBG_BLOCK_ID_UNUSED20_BY4                        = 0x27,
6176         DBG_BLOCK_ID_TA10_BY4                            = 0x28,
6177         DBG_BLOCK_ID_TA14_BY4                            = 0x29,
6178         DBG_BLOCK_ID_TA18_BY4                            = 0x2a,
6179         DBG_BLOCK_ID_UNUSED24_BY4                        = 0x2b,
6180         DBG_BLOCK_ID_TD_BY4                              = 0x2c,
6181         DBG_BLOCK_ID_TD04_BY4                            = 0x2d,
6182         DBG_BLOCK_ID_TD08_BY4                            = 0x2e,
6183         DBG_BLOCK_ID_UNUSED28_BY4                        = 0x2f,
6184         DBG_BLOCK_ID_TD10_BY4                            = 0x30,
6185         DBG_BLOCK_ID_TD14_BY4                            = 0x31,
6186         DBG_BLOCK_ID_TD18_BY4                            = 0x32,
6187         DBG_BLOCK_ID_UNUSED32_BY4                        = 0x33,
6188         DBG_BLOCK_ID_LDS_BY4                             = 0x34,
6189         DBG_BLOCK_ID_LDS04_BY4                           = 0x35,
6190         DBG_BLOCK_ID_LDS08_BY4                           = 0x36,
6191         DBG_BLOCK_ID_UNUSED36_BY4                        = 0x37,
6192         DBG_BLOCK_ID_LDS10_BY4                           = 0x38,
6193         DBG_BLOCK_ID_LDS14_BY4                           = 0x39,
6194         DBG_BLOCK_ID_LDS18_BY4                           = 0x3a,
6195         DBG_BLOCK_ID_UNUSED40_BY4                        = 0x3b,
6196 } DebugBlockId_BY4;
6197 typedef enum DebugBlockId_BY8 {
6198         DBG_BLOCK_ID_RESERVED_BY8                        = 0x0,
6199         DBG_BLOCK_ID_CSC_BY8                             = 0x1,
6200         DBG_BLOCK_ID_SDMA0_BY8                           = 0x2,
6201         DBG_BLOCK_ID_CP0_BY8                             = 0x3,
6202         DBG_BLOCK_ID_SXM0_BY8                            = 0x4,
6203         DBG_BLOCK_ID_TCA_BY8                             = 0x5,
6204         DBG_BLOCK_ID_MCD_BY8                             = 0x6,
6205         DBG_BLOCK_ID_SQA_BY8                             = 0x7,
6206         DBG_BLOCK_ID_SQB_BY8                             = 0x8,
6207         DBG_BLOCK_ID_CB_BY8                              = 0x9,
6208         DBG_BLOCK_ID_SXS_BY8                             = 0xa,
6209         DBG_BLOCK_ID_DB_BY8                              = 0xb,
6210         DBG_BLOCK_ID_TCP_BY8                             = 0xc,
6211         DBG_BLOCK_ID_TCP8_BY8                            = 0xd,
6212         DBG_BLOCK_ID_TCP16_BY8                           = 0xe,
6213         DBG_BLOCK_ID_TCP_RESERVED0_BY8                   = 0xf,
6214         DBG_BLOCK_ID_TCC_BY8                             = 0x10,
6215         DBG_BLOCK_ID_SPS_BY8                             = 0x11,
6216         DBG_BLOCK_ID_TA_BY8                              = 0x12,
6217         DBG_BLOCK_ID_TA08_BY8                            = 0x13,
6218         DBG_BLOCK_ID_TA10_BY8                            = 0x14,
6219         DBG_BLOCK_ID_TA18_BY8                            = 0x15,
6220         DBG_BLOCK_ID_TD_BY8                              = 0x16,
6221         DBG_BLOCK_ID_TD08_BY8                            = 0x17,
6222         DBG_BLOCK_ID_TD10_BY8                            = 0x18,
6223         DBG_BLOCK_ID_TD18_BY8                            = 0x19,
6224         DBG_BLOCK_ID_LDS_BY8                             = 0x1a,
6225         DBG_BLOCK_ID_LDS08_BY8                           = 0x1b,
6226         DBG_BLOCK_ID_LDS10_BY8                           = 0x1c,
6227         DBG_BLOCK_ID_LDS18_BY8                           = 0x1d,
6228 } DebugBlockId_BY8;
6229 typedef enum DebugBlockId_BY16 {
6230         DBG_BLOCK_ID_RESERVED_BY16                       = 0x0,
6231         DBG_BLOCK_ID_SDMA0_BY16                          = 0x1,
6232         DBG_BLOCK_ID_SXM_BY16                            = 0x2,
6233         DBG_BLOCK_ID_MCD_BY16                            = 0x3,
6234         DBG_BLOCK_ID_SQB_BY16                            = 0x4,
6235         DBG_BLOCK_ID_SXS_BY16                            = 0x5,
6236         DBG_BLOCK_ID_TCP_BY16                            = 0x6,
6237         DBG_BLOCK_ID_TCP16_BY16                          = 0x7,
6238         DBG_BLOCK_ID_TCC_BY16                            = 0x8,
6239         DBG_BLOCK_ID_TA_BY16                             = 0x9,
6240         DBG_BLOCK_ID_TA10_BY16                           = 0xa,
6241         DBG_BLOCK_ID_TD_BY16                             = 0xb,
6242         DBG_BLOCK_ID_TD10_BY16                           = 0xc,
6243         DBG_BLOCK_ID_LDS_BY16                            = 0xd,
6244         DBG_BLOCK_ID_LDS10_BY16                          = 0xe,
6245 } DebugBlockId_BY16;
6246 typedef enum SurfaceEndian {
6247         ENDIAN_NONE                                      = 0x0,
6248         ENDIAN_8IN16                                     = 0x1,
6249         ENDIAN_8IN32                                     = 0x2,
6250         ENDIAN_8IN64                                     = 0x3,
6251 } SurfaceEndian;
6252 typedef enum ArrayMode {
6253         ARRAY_LINEAR_GENERAL                             = 0x0,
6254         ARRAY_LINEAR_ALIGNED                             = 0x1,
6255         ARRAY_1D_TILED_THIN1                             = 0x2,
6256         ARRAY_1D_TILED_THICK                             = 0x3,
6257         ARRAY_2D_TILED_THIN1                             = 0x4,
6258         ARRAY_PRT_TILED_THIN1                            = 0x5,
6259         ARRAY_PRT_2D_TILED_THIN1                         = 0x6,
6260         ARRAY_2D_TILED_THICK                             = 0x7,
6261         ARRAY_2D_TILED_XTHICK                            = 0x8,
6262         ARRAY_PRT_TILED_THICK                            = 0x9,
6263         ARRAY_PRT_2D_TILED_THICK                         = 0xa,
6264         ARRAY_PRT_3D_TILED_THIN1                         = 0xb,
6265         ARRAY_3D_TILED_THIN1                             = 0xc,
6266         ARRAY_3D_TILED_THICK                             = 0xd,
6267         ARRAY_3D_TILED_XTHICK                            = 0xe,
6268         ARRAY_PRT_3D_TILED_THICK                         = 0xf,
6269 } ArrayMode;
6270 typedef enum PipeTiling {
6271         CONFIG_1_PIPE                                    = 0x0,
6272         CONFIG_2_PIPE                                    = 0x1,
6273         CONFIG_4_PIPE                                    = 0x2,
6274         CONFIG_8_PIPE                                    = 0x3,
6275 } PipeTiling;
6276 typedef enum BankTiling {
6277         CONFIG_4_BANK                                    = 0x0,
6278         CONFIG_8_BANK                                    = 0x1,
6279 } BankTiling;
6280 typedef enum GroupInterleave {
6281         CONFIG_256B_GROUP                                = 0x0,
6282         CONFIG_512B_GROUP                                = 0x1,
6283 } GroupInterleave;
6284 typedef enum RowTiling {
6285         CONFIG_1KB_ROW                                   = 0x0,
6286         CONFIG_2KB_ROW                                   = 0x1,
6287         CONFIG_4KB_ROW                                   = 0x2,
6288         CONFIG_8KB_ROW                                   = 0x3,
6289         CONFIG_1KB_ROW_OPT                               = 0x4,
6290         CONFIG_2KB_ROW_OPT                               = 0x5,
6291         CONFIG_4KB_ROW_OPT                               = 0x6,
6292         CONFIG_8KB_ROW_OPT                               = 0x7,
6293 } RowTiling;
6294 typedef enum BankSwapBytes {
6295         CONFIG_128B_SWAPS                                = 0x0,
6296         CONFIG_256B_SWAPS                                = 0x1,
6297         CONFIG_512B_SWAPS                                = 0x2,
6298         CONFIG_1KB_SWAPS                                 = 0x3,
6299 } BankSwapBytes;
6300 typedef enum SampleSplitBytes {
6301         CONFIG_1KB_SPLIT                                 = 0x0,
6302         CONFIG_2KB_SPLIT                                 = 0x1,
6303         CONFIG_4KB_SPLIT                                 = 0x2,
6304         CONFIG_8KB_SPLIT                                 = 0x3,
6305 } SampleSplitBytes;
6306 typedef enum NumPipes {
6307         ADDR_CONFIG_1_PIPE                               = 0x0,
6308         ADDR_CONFIG_2_PIPE                               = 0x1,
6309         ADDR_CONFIG_4_PIPE                               = 0x2,
6310         ADDR_CONFIG_8_PIPE                               = 0x3,
6311 } NumPipes;
6312 typedef enum PipeInterleaveSize {
6313         ADDR_CONFIG_PIPE_INTERLEAVE_256B                 = 0x0,
6314         ADDR_CONFIG_PIPE_INTERLEAVE_512B                 = 0x1,
6315 } PipeInterleaveSize;
6316 typedef enum BankInterleaveSize {
6317         ADDR_CONFIG_BANK_INTERLEAVE_1                    = 0x0,
6318         ADDR_CONFIG_BANK_INTERLEAVE_2                    = 0x1,
6319         ADDR_CONFIG_BANK_INTERLEAVE_4                    = 0x2,
6320         ADDR_CONFIG_BANK_INTERLEAVE_8                    = 0x3,
6321 } BankInterleaveSize;
6322 typedef enum NumShaderEngines {
6323         ADDR_CONFIG_1_SHADER_ENGINE                      = 0x0,
6324         ADDR_CONFIG_2_SHADER_ENGINE                      = 0x1,
6325 } NumShaderEngines;
6326 typedef enum ShaderEngineTileSize {
6327         ADDR_CONFIG_SE_TILE_16                           = 0x0,
6328         ADDR_CONFIG_SE_TILE_32                           = 0x1,
6329 } ShaderEngineTileSize;
6330 typedef enum NumGPUs {
6331         ADDR_CONFIG_1_GPU                                = 0x0,
6332         ADDR_CONFIG_2_GPU                                = 0x1,
6333         ADDR_CONFIG_4_GPU                                = 0x2,
6334 } NumGPUs;
6335 typedef enum MultiGPUTileSize {
6336         ADDR_CONFIG_GPU_TILE_16                          = 0x0,
6337         ADDR_CONFIG_GPU_TILE_32                          = 0x1,
6338         ADDR_CONFIG_GPU_TILE_64                          = 0x2,
6339         ADDR_CONFIG_GPU_TILE_128                         = 0x3,
6340 } MultiGPUTileSize;
6341 typedef enum RowSize {
6342         ADDR_CONFIG_1KB_ROW                              = 0x0,
6343         ADDR_CONFIG_2KB_ROW                              = 0x1,
6344         ADDR_CONFIG_4KB_ROW                              = 0x2,
6345 } RowSize;
6346 typedef enum NumLowerPipes {
6347         ADDR_CONFIG_1_LOWER_PIPES                        = 0x0,
6348         ADDR_CONFIG_2_LOWER_PIPES                        = 0x1,
6349 } NumLowerPipes;
6350 typedef enum ColorTransform {
6351         DCC_CT_AUTO                                      = 0x0,
6352         DCC_CT_NONE                                      = 0x1,
6353         ABGR_TO_A_BG_G_RB                                = 0x2,
6354         BGRA_TO_BG_G_RB_A                                = 0x3,
6355 } ColorTransform;
6356 typedef enum CompareRef {
6357         REF_NEVER                                        = 0x0,
6358         REF_LESS                                         = 0x1,
6359         REF_EQUAL                                        = 0x2,
6360         REF_LEQUAL                                       = 0x3,
6361         REF_GREATER                                      = 0x4,
6362         REF_NOTEQUAL                                     = 0x5,
6363         REF_GEQUAL                                       = 0x6,
6364         REF_ALWAYS                                       = 0x7,
6365 } CompareRef;
6366 typedef enum ReadSize {
6367         READ_256_BITS                                    = 0x0,
6368         READ_512_BITS                                    = 0x1,
6369 } ReadSize;
6370 typedef enum DepthFormat {
6371         DEPTH_INVALID                                    = 0x0,
6372         DEPTH_16                                         = 0x1,
6373         DEPTH_X8_24                                      = 0x2,
6374         DEPTH_8_24                                       = 0x3,
6375         DEPTH_X8_24_FLOAT                                = 0x4,
6376         DEPTH_8_24_FLOAT                                 = 0x5,
6377         DEPTH_32_FLOAT                                   = 0x6,
6378         DEPTH_X24_8_32_FLOAT                             = 0x7,
6379 } DepthFormat;
6380 typedef enum ZFormat {
6381         Z_INVALID                                        = 0x0,
6382         Z_16                                             = 0x1,
6383         Z_24                                             = 0x2,
6384         Z_32_FLOAT                                       = 0x3,
6385 } ZFormat;
6386 typedef enum StencilFormat {
6387         STENCIL_INVALID                                  = 0x0,
6388         STENCIL_8                                        = 0x1,
6389 } StencilFormat;
6390 typedef enum CmaskMode {
6391         CMASK_CLEAR_NONE                                 = 0x0,
6392         CMASK_CLEAR_ONE                                  = 0x1,
6393         CMASK_CLEAR_ALL                                  = 0x2,
6394         CMASK_ANY_EXPANDED                               = 0x3,
6395         CMASK_ALPHA0_FRAG1                               = 0x4,
6396         CMASK_ALPHA0_FRAG2                               = 0x5,
6397         CMASK_ALPHA0_FRAG4                               = 0x6,
6398         CMASK_ALPHA0_FRAGS                               = 0x7,
6399         CMASK_ALPHA1_FRAG1                               = 0x8,
6400         CMASK_ALPHA1_FRAG2                               = 0x9,
6401         CMASK_ALPHA1_FRAG4                               = 0xa,
6402         CMASK_ALPHA1_FRAGS                               = 0xb,
6403         CMASK_ALPHAX_FRAG1                               = 0xc,
6404         CMASK_ALPHAX_FRAG2                               = 0xd,
6405         CMASK_ALPHAX_FRAG4                               = 0xe,
6406         CMASK_ALPHAX_FRAGS                               = 0xf,
6407 } CmaskMode;
6408 typedef enum QuadExportFormat {
6409         EXPORT_UNUSED                                    = 0x0,
6410         EXPORT_32_R                                      = 0x1,
6411         EXPORT_32_GR                                     = 0x2,
6412         EXPORT_32_AR                                     = 0x3,
6413         EXPORT_FP16_ABGR                                 = 0x4,
6414         EXPORT_UNSIGNED16_ABGR                           = 0x5,
6415         EXPORT_SIGNED16_ABGR                             = 0x6,
6416         EXPORT_32_ABGR                                   = 0x7,
6417         EXPORT_32BPP_8PIX                                = 0x8,
6418         EXPORT_16_16_UNSIGNED_8PIX                       = 0x9,
6419         EXPORT_16_16_SIGNED_8PIX                         = 0xa,
6420         EXPORT_16_16_FLOAT_8PIX                          = 0xb,
6421 } QuadExportFormat;
6422 typedef enum QuadExportFormatOld {
6423         EXPORT_4P_32BPC_ABGR                             = 0x0,
6424         EXPORT_4P_16BPC_ABGR                             = 0x1,
6425         EXPORT_4P_32BPC_GR                               = 0x2,
6426         EXPORT_4P_32BPC_AR                               = 0x3,
6427         EXPORT_2P_32BPC_ABGR                             = 0x4,
6428         EXPORT_8P_32BPC_R                                = 0x5,
6429 } QuadExportFormatOld;
6430 typedef enum ColorFormat {
6431         COLOR_INVALID                                    = 0x0,
6432         COLOR_8                                          = 0x1,
6433         COLOR_16                                         = 0x2,
6434         COLOR_8_8                                        = 0x3,
6435         COLOR_32                                         = 0x4,
6436         COLOR_16_16                                      = 0x5,
6437         COLOR_10_11_11                                   = 0x6,
6438         COLOR_11_11_10                                   = 0x7,
6439         COLOR_10_10_10_2                                 = 0x8,
6440         COLOR_2_10_10_10                                 = 0x9,
6441         COLOR_8_8_8_8                                    = 0xa,
6442         COLOR_32_32                                      = 0xb,
6443         COLOR_16_16_16_16                                = 0xc,
6444         COLOR_RESERVED_13                                = 0xd,
6445         COLOR_32_32_32_32                                = 0xe,
6446         COLOR_RESERVED_15                                = 0xf,
6447         COLOR_5_6_5                                      = 0x10,
6448         COLOR_1_5_5_5                                    = 0x11,
6449         COLOR_5_5_5_1                                    = 0x12,
6450         COLOR_4_4_4_4                                    = 0x13,
6451         COLOR_8_24                                       = 0x14,
6452         COLOR_24_8                                       = 0x15,
6453         COLOR_X24_8_32_FLOAT                             = 0x16,
6454         COLOR_RESERVED_23                                = 0x17,
6455         COLOR_RESERVED_24                                = 0x18,
6456         COLOR_RESERVED_25                                = 0x19,
6457         COLOR_RESERVED_26                                = 0x1a,
6458         COLOR_RESERVED_27                                = 0x1b,
6459         COLOR_RESERVED_28                                = 0x1c,
6460         COLOR_RESERVED_29                                = 0x1d,
6461         COLOR_RESERVED_30                                = 0x1e,
6462 } ColorFormat;
6463 typedef enum SurfaceFormat {
6464         FMT_INVALID                                      = 0x0,
6465         FMT_8                                            = 0x1,
6466         FMT_16                                           = 0x2,
6467         FMT_8_8                                          = 0x3,
6468         FMT_32                                           = 0x4,
6469         FMT_16_16                                        = 0x5,
6470         FMT_10_11_11                                     = 0x6,
6471         FMT_11_11_10                                     = 0x7,
6472         FMT_10_10_10_2                                   = 0x8,
6473         FMT_2_10_10_10                                   = 0x9,
6474         FMT_8_8_8_8                                      = 0xa,
6475         FMT_32_32                                        = 0xb,
6476         FMT_16_16_16_16                                  = 0xc,
6477         FMT_32_32_32                                     = 0xd,
6478         FMT_32_32_32_32                                  = 0xe,
6479         FMT_RESERVED_4                                   = 0xf,
6480         FMT_5_6_5                                        = 0x10,
6481         FMT_1_5_5_5                                      = 0x11,
6482         FMT_5_5_5_1                                      = 0x12,
6483         FMT_4_4_4_4                                      = 0x13,
6484         FMT_8_24                                         = 0x14,
6485         FMT_24_8                                         = 0x15,
6486         FMT_X24_8_32_FLOAT                               = 0x16,
6487         FMT_RESERVED_33                                  = 0x17,
6488         FMT_11_11_10_FLOAT                               = 0x18,
6489         FMT_16_FLOAT                                     = 0x19,
6490         FMT_32_FLOAT                                     = 0x1a,
6491         FMT_16_16_FLOAT                                  = 0x1b,
6492         FMT_8_24_FLOAT                                   = 0x1c,
6493         FMT_24_8_FLOAT                                   = 0x1d,
6494         FMT_32_32_FLOAT                                  = 0x1e,
6495         FMT_10_11_11_FLOAT                               = 0x1f,
6496         FMT_16_16_16_16_FLOAT                            = 0x20,
6497         FMT_3_3_2                                        = 0x21,
6498         FMT_6_5_5                                        = 0x22,
6499         FMT_32_32_32_32_FLOAT                            = 0x23,
6500         FMT_RESERVED_36                                  = 0x24,
6501         FMT_1                                            = 0x25,
6502         FMT_1_REVERSED                                   = 0x26,
6503         FMT_GB_GR                                        = 0x27,
6504         FMT_BG_RG                                        = 0x28,
6505         FMT_32_AS_8                                      = 0x29,
6506         FMT_32_AS_8_8                                    = 0x2a,
6507         FMT_5_9_9_9_SHAREDEXP                            = 0x2b,
6508         FMT_8_8_8                                        = 0x2c,
6509         FMT_16_16_16                                     = 0x2d,
6510         FMT_16_16_16_FLOAT                               = 0x2e,
6511         FMT_4_4                                          = 0x2f,
6512         FMT_32_32_32_FLOAT                               = 0x30,
6513         FMT_BC1                                          = 0x31,
6514         FMT_BC2                                          = 0x32,
6515         FMT_BC3                                          = 0x33,
6516         FMT_BC4                                          = 0x34,
6517         FMT_BC5                                          = 0x35,
6518         FMT_BC6                                          = 0x36,
6519         FMT_BC7                                          = 0x37,
6520         FMT_32_AS_32_32_32_32                            = 0x38,
6521         FMT_APC3                                         = 0x39,
6522         FMT_APC4                                         = 0x3a,
6523         FMT_APC5                                         = 0x3b,
6524         FMT_APC6                                         = 0x3c,
6525         FMT_APC7                                         = 0x3d,
6526         FMT_CTX1                                         = 0x3e,
6527         FMT_RESERVED_63                                  = 0x3f,
6528 } SurfaceFormat;
6529 typedef enum BUF_DATA_FORMAT {
6530         BUF_DATA_FORMAT_INVALID                          = 0x0,
6531         BUF_DATA_FORMAT_8                                = 0x1,
6532         BUF_DATA_FORMAT_16                               = 0x2,
6533         BUF_DATA_FORMAT_8_8                              = 0x3,
6534         BUF_DATA_FORMAT_32                               = 0x4,
6535         BUF_DATA_FORMAT_16_16                            = 0x5,
6536         BUF_DATA_FORMAT_10_11_11                         = 0x6,
6537         BUF_DATA_FORMAT_11_11_10                         = 0x7,
6538         BUF_DATA_FORMAT_10_10_10_2                       = 0x8,
6539         BUF_DATA_FORMAT_2_10_10_10                       = 0x9,
6540         BUF_DATA_FORMAT_8_8_8_8                          = 0xa,
6541         BUF_DATA_FORMAT_32_32                            = 0xb,
6542         BUF_DATA_FORMAT_16_16_16_16                      = 0xc,
6543         BUF_DATA_FORMAT_32_32_32                         = 0xd,
6544         BUF_DATA_FORMAT_32_32_32_32                      = 0xe,
6545         BUF_DATA_FORMAT_RESERVED_15                      = 0xf,
6546 } BUF_DATA_FORMAT;
6547 typedef enum IMG_DATA_FORMAT {
6548         IMG_DATA_FORMAT_INVALID                          = 0x0,
6549         IMG_DATA_FORMAT_8                                = 0x1,
6550         IMG_DATA_FORMAT_16                               = 0x2,
6551         IMG_DATA_FORMAT_8_8                              = 0x3,
6552         IMG_DATA_FORMAT_32                               = 0x4,
6553         IMG_DATA_FORMAT_16_16                            = 0x5,
6554         IMG_DATA_FORMAT_10_11_11                         = 0x6,
6555         IMG_DATA_FORMAT_11_11_10                         = 0x7,
6556         IMG_DATA_FORMAT_10_10_10_2                       = 0x8,
6557         IMG_DATA_FORMAT_2_10_10_10                       = 0x9,
6558         IMG_DATA_FORMAT_8_8_8_8                          = 0xa,
6559         IMG_DATA_FORMAT_32_32                            = 0xb,
6560         IMG_DATA_FORMAT_16_16_16_16                      = 0xc,
6561         IMG_DATA_FORMAT_32_32_32                         = 0xd,
6562         IMG_DATA_FORMAT_32_32_32_32                      = 0xe,
6563         IMG_DATA_FORMAT_16_AS_32_32                      = 0xf,
6564         IMG_DATA_FORMAT_5_6_5                            = 0x10,
6565         IMG_DATA_FORMAT_1_5_5_5                          = 0x11,
6566         IMG_DATA_FORMAT_5_5_5_1                          = 0x12,
6567         IMG_DATA_FORMAT_4_4_4_4                          = 0x13,
6568         IMG_DATA_FORMAT_8_24                             = 0x14,
6569         IMG_DATA_FORMAT_24_8                             = 0x15,
6570         IMG_DATA_FORMAT_X24_8_32                         = 0x16,
6571         IMG_DATA_FORMAT_8_AS_8_8_8_8                     = 0x17,
6572         IMG_DATA_FORMAT_ETC2_RGB                         = 0x18,
6573         IMG_DATA_FORMAT_ETC2_RGBA                        = 0x19,
6574         IMG_DATA_FORMAT_ETC2_R                           = 0x1a,
6575         IMG_DATA_FORMAT_ETC2_RG                          = 0x1b,
6576         IMG_DATA_FORMAT_ETC2_RGBA1                       = 0x1c,
6577         IMG_DATA_FORMAT_RESERVED_29                      = 0x1d,
6578         IMG_DATA_FORMAT_RESERVED_30                      = 0x1e,
6579         IMG_DATA_FORMAT_RESERVED_31                      = 0x1f,
6580         IMG_DATA_FORMAT_GB_GR                            = 0x20,
6581         IMG_DATA_FORMAT_BG_RG                            = 0x21,
6582         IMG_DATA_FORMAT_5_9_9_9                          = 0x22,
6583         IMG_DATA_FORMAT_BC1                              = 0x23,
6584         IMG_DATA_FORMAT_BC2                              = 0x24,
6585         IMG_DATA_FORMAT_BC3                              = 0x25,
6586         IMG_DATA_FORMAT_BC4                              = 0x26,
6587         IMG_DATA_FORMAT_BC5                              = 0x27,
6588         IMG_DATA_FORMAT_BC6                              = 0x28,
6589         IMG_DATA_FORMAT_BC7                              = 0x29,
6590         IMG_DATA_FORMAT_16_AS_16_16_16_16                = 0x2a,
6591         IMG_DATA_FORMAT_16_AS_32_32_32_32                = 0x2b,
6592         IMG_DATA_FORMAT_FMASK8_S2_F1                     = 0x2c,
6593         IMG_DATA_FORMAT_FMASK8_S4_F1                     = 0x2d,
6594         IMG_DATA_FORMAT_FMASK8_S8_F1                     = 0x2e,
6595         IMG_DATA_FORMAT_FMASK8_S2_F2                     = 0x2f,
6596         IMG_DATA_FORMAT_FMASK8_S4_F2                     = 0x30,
6597         IMG_DATA_FORMAT_FMASK8_S4_F4                     = 0x31,
6598         IMG_DATA_FORMAT_FMASK16_S16_F1                   = 0x32,
6599         IMG_DATA_FORMAT_FMASK16_S8_F2                    = 0x33,
6600         IMG_DATA_FORMAT_FMASK32_S16_F2                   = 0x34,
6601         IMG_DATA_FORMAT_FMASK32_S8_F4                    = 0x35,
6602         IMG_DATA_FORMAT_FMASK32_S8_F8                    = 0x36,
6603         IMG_DATA_FORMAT_FMASK64_S16_F4                   = 0x37,
6604         IMG_DATA_FORMAT_FMASK64_S16_F8                   = 0x38,
6605         IMG_DATA_FORMAT_4_4                              = 0x39,
6606         IMG_DATA_FORMAT_6_5_5                            = 0x3a,
6607         IMG_DATA_FORMAT_1                                = 0x3b,
6608         IMG_DATA_FORMAT_1_REVERSED                       = 0x3c,
6609         IMG_DATA_FORMAT_8_AS_32                          = 0x3d,
6610         IMG_DATA_FORMAT_8_AS_32_32                       = 0x3e,
6611         IMG_DATA_FORMAT_32_AS_32_32_32_32                = 0x3f,
6612 } IMG_DATA_FORMAT;
6613 typedef enum BUF_NUM_FORMAT {
6614         BUF_NUM_FORMAT_UNORM                             = 0x0,
6615         BUF_NUM_FORMAT_SNORM                             = 0x1,
6616         BUF_NUM_FORMAT_USCALED                           = 0x2,
6617         BUF_NUM_FORMAT_SSCALED                           = 0x3,
6618         BUF_NUM_FORMAT_UINT                              = 0x4,
6619         BUF_NUM_FORMAT_SINT                              = 0x5,
6620         BUF_NUM_FORMAT_RESERVED_6                        = 0x6,
6621         BUF_NUM_FORMAT_FLOAT                             = 0x7,
6622 } BUF_NUM_FORMAT;
6623 typedef enum IMG_NUM_FORMAT {
6624         IMG_NUM_FORMAT_UNORM                             = 0x0,
6625         IMG_NUM_FORMAT_SNORM                             = 0x1,
6626         IMG_NUM_FORMAT_USCALED                           = 0x2,
6627         IMG_NUM_FORMAT_SSCALED                           = 0x3,
6628         IMG_NUM_FORMAT_UINT                              = 0x4,
6629         IMG_NUM_FORMAT_SINT                              = 0x5,
6630         IMG_NUM_FORMAT_RESERVED_6                        = 0x6,
6631         IMG_NUM_FORMAT_FLOAT                             = 0x7,
6632         IMG_NUM_FORMAT_RESERVED_8                        = 0x8,
6633         IMG_NUM_FORMAT_SRGB                              = 0x9,
6634         IMG_NUM_FORMAT_RESERVED_10                       = 0xa,
6635         IMG_NUM_FORMAT_RESERVED_11                       = 0xb,
6636         IMG_NUM_FORMAT_RESERVED_12                       = 0xc,
6637         IMG_NUM_FORMAT_RESERVED_13                       = 0xd,
6638         IMG_NUM_FORMAT_RESERVED_14                       = 0xe,
6639         IMG_NUM_FORMAT_RESERVED_15                       = 0xf,
6640 } IMG_NUM_FORMAT;
6641 typedef enum TileType {
6642         ARRAY_COLOR_TILE                                 = 0x0,
6643         ARRAY_DEPTH_TILE                                 = 0x1,
6644 } TileType;
6645 typedef enum NonDispTilingOrder {
6646         ADDR_SURF_MICRO_TILING_DISPLAY                   = 0x0,
6647         ADDR_SURF_MICRO_TILING_NON_DISPLAY               = 0x1,
6648 } NonDispTilingOrder;
6649 typedef enum MicroTileMode {
6650         ADDR_SURF_DISPLAY_MICRO_TILING                   = 0x0,
6651         ADDR_SURF_THIN_MICRO_TILING                      = 0x1,
6652         ADDR_SURF_DEPTH_MICRO_TILING                     = 0x2,
6653         ADDR_SURF_ROTATED_MICRO_TILING                   = 0x3,
6654         ADDR_SURF_THICK_MICRO_TILING                     = 0x4,
6655 } MicroTileMode;
6656 typedef enum TileSplit {
6657         ADDR_SURF_TILE_SPLIT_64B                         = 0x0,
6658         ADDR_SURF_TILE_SPLIT_128B                        = 0x1,
6659         ADDR_SURF_TILE_SPLIT_256B                        = 0x2,
6660         ADDR_SURF_TILE_SPLIT_512B                        = 0x3,
6661         ADDR_SURF_TILE_SPLIT_1KB                         = 0x4,
6662         ADDR_SURF_TILE_SPLIT_2KB                         = 0x5,
6663         ADDR_SURF_TILE_SPLIT_4KB                         = 0x6,
6664 } TileSplit;
6665 typedef enum SampleSplit {
6666         ADDR_SURF_SAMPLE_SPLIT_1                         = 0x0,
6667         ADDR_SURF_SAMPLE_SPLIT_2                         = 0x1,
6668         ADDR_SURF_SAMPLE_SPLIT_4                         = 0x2,
6669         ADDR_SURF_SAMPLE_SPLIT_8                         = 0x3,
6670 } SampleSplit;
6671 typedef enum PipeConfig {
6672         ADDR_SURF_P2                                     = 0x0,
6673         ADDR_SURF_P2_RESERVED0                           = 0x1,
6674         ADDR_SURF_P2_RESERVED1                           = 0x2,
6675         ADDR_SURF_P2_RESERVED2                           = 0x3,
6676         ADDR_SURF_P4_8x16                                = 0x4,
6677         ADDR_SURF_P4_16x16                               = 0x5,
6678         ADDR_SURF_P4_16x32                               = 0x6,
6679         ADDR_SURF_P4_32x32                               = 0x7,
6680         ADDR_SURF_P8_16x16_8x16                          = 0x8,
6681         ADDR_SURF_P8_16x32_8x16                          = 0x9,
6682         ADDR_SURF_P8_32x32_8x16                          = 0xa,
6683         ADDR_SURF_P8_16x32_16x16                         = 0xb,
6684         ADDR_SURF_P8_32x32_16x16                         = 0xc,
6685         ADDR_SURF_P8_32x32_16x32                         = 0xd,
6686         ADDR_SURF_P8_32x64_32x32                         = 0xe,
6687         ADDR_SURF_P8_RESERVED0                           = 0xf,
6688         ADDR_SURF_P16_32x32_8x16                         = 0x10,
6689         ADDR_SURF_P16_32x32_16x16                        = 0x11,
6690 } PipeConfig;
6691 typedef enum NumBanks {
6692         ADDR_SURF_2_BANK                                 = 0x0,
6693         ADDR_SURF_4_BANK                                 = 0x1,
6694         ADDR_SURF_8_BANK                                 = 0x2,
6695         ADDR_SURF_16_BANK                                = 0x3,
6696 } NumBanks;
6697 typedef enum BankWidth {
6698         ADDR_SURF_BANK_WIDTH_1                           = 0x0,
6699         ADDR_SURF_BANK_WIDTH_2                           = 0x1,
6700         ADDR_SURF_BANK_WIDTH_4                           = 0x2,
6701         ADDR_SURF_BANK_WIDTH_8                           = 0x3,
6702 } BankWidth;
6703 typedef enum BankHeight {
6704         ADDR_SURF_BANK_HEIGHT_1                          = 0x0,
6705         ADDR_SURF_BANK_HEIGHT_2                          = 0x1,
6706         ADDR_SURF_BANK_HEIGHT_4                          = 0x2,
6707         ADDR_SURF_BANK_HEIGHT_8                          = 0x3,
6708 } BankHeight;
6709 typedef enum BankWidthHeight {
6710         ADDR_SURF_BANK_WH_1                              = 0x0,
6711         ADDR_SURF_BANK_WH_2                              = 0x1,
6712         ADDR_SURF_BANK_WH_4                              = 0x2,
6713         ADDR_SURF_BANK_WH_8                              = 0x3,
6714 } BankWidthHeight;
6715 typedef enum MacroTileAspect {
6716         ADDR_SURF_MACRO_ASPECT_1                         = 0x0,
6717         ADDR_SURF_MACRO_ASPECT_2                         = 0x1,
6718         ADDR_SURF_MACRO_ASPECT_4                         = 0x2,
6719         ADDR_SURF_MACRO_ASPECT_8                         = 0x3,
6720 } MacroTileAspect;
6721 typedef enum GATCL1RequestType {
6722         GATCL1_TYPE_NORMAL                               = 0x0,
6723         GATCL1_TYPE_SHOOTDOWN                            = 0x1,
6724         GATCL1_TYPE_BYPASS                               = 0x2,
6725 } GATCL1RequestType;
6726 typedef enum TCC_CACHE_POLICIES {
6727         TCC_CACHE_POLICY_LRU                             = 0x0,
6728         TCC_CACHE_POLICY_STREAM                          = 0x1,
6729 } TCC_CACHE_POLICIES;
6730 typedef enum MTYPE {
6731         MTYPE_NC_NV                                      = 0x0,
6732         MTYPE_NC                                         = 0x1,
6733         MTYPE_CC                                         = 0x2,
6734         MTYPE_UC                                         = 0x3,
6735 } MTYPE;
6736 typedef enum PERFMON_COUNTER_MODE {
6737         PERFMON_COUNTER_MODE_ACCUM                       = 0x0,
6738         PERFMON_COUNTER_MODE_ACTIVE_CYCLES               = 0x1,
6739         PERFMON_COUNTER_MODE_MAX                         = 0x2,
6740         PERFMON_COUNTER_MODE_DIRTY                       = 0x3,
6741         PERFMON_COUNTER_MODE_SAMPLE                      = 0x4,
6742         PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT    = 0x5,
6743         PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT     = 0x6,
6744         PERFMON_COUNTER_MODE_CYCLES_GE_HI                = 0x7,
6745         PERFMON_COUNTER_MODE_CYCLES_EQ_HI                = 0x8,
6746         PERFMON_COUNTER_MODE_INACTIVE_CYCLES             = 0x9,
6747         PERFMON_COUNTER_MODE_RESERVED                    = 0xf,
6748 } PERFMON_COUNTER_MODE;
6749 typedef enum PERFMON_SPM_MODE {
6750         PERFMON_SPM_MODE_OFF                             = 0x0,
6751         PERFMON_SPM_MODE_16BIT_CLAMP                     = 0x1,
6752         PERFMON_SPM_MODE_16BIT_NO_CLAMP                  = 0x2,
6753         PERFMON_SPM_MODE_32BIT_CLAMP                     = 0x3,
6754         PERFMON_SPM_MODE_32BIT_NO_CLAMP                  = 0x4,
6755         PERFMON_SPM_MODE_RESERVED_5                      = 0x5,
6756         PERFMON_SPM_MODE_RESERVED_6                      = 0x6,
6757         PERFMON_SPM_MODE_RESERVED_7                      = 0x7,
6758         PERFMON_SPM_MODE_TEST_MODE_0                     = 0x8,
6759         PERFMON_SPM_MODE_TEST_MODE_1                     = 0x9,
6760         PERFMON_SPM_MODE_TEST_MODE_2                     = 0xa,
6761 } PERFMON_SPM_MODE;
6762 typedef enum SurfaceTiling {
6763         ARRAY_LINEAR                                     = 0x0,
6764         ARRAY_TILED                                      = 0x1,
6765 } SurfaceTiling;
6766 typedef enum SurfaceArray {
6767         ARRAY_1D                                         = 0x0,
6768         ARRAY_2D                                         = 0x1,
6769         ARRAY_3D                                         = 0x2,
6770         ARRAY_3D_SLICE                                   = 0x3,
6771 } SurfaceArray;
6772 typedef enum ColorArray {
6773         ARRAY_2D_ALT_COLOR                               = 0x0,
6774         ARRAY_2D_COLOR                                   = 0x1,
6775         ARRAY_3D_SLICE_COLOR                             = 0x3,
6776 } ColorArray;
6777 typedef enum DepthArray {
6778         ARRAY_2D_ALT_DEPTH                               = 0x0,
6779         ARRAY_2D_DEPTH                                   = 0x1,
6780 } DepthArray;
6781 typedef enum ENUM_NUM_SIMD_PER_CU {
6782         NUM_SIMD_PER_CU                                  = 0x4,
6783 } ENUM_NUM_SIMD_PER_CU;
6784 typedef enum MEM_PWR_FORCE_CTRL {
6785         NO_FORCE_REQUEST                                 = 0x0,
6786         FORCE_LIGHT_SLEEP_REQUEST                        = 0x1,
6787         FORCE_DEEP_SLEEP_REQUEST                         = 0x2,
6788         FORCE_SHUT_DOWN_REQUEST                          = 0x3,
6789 } MEM_PWR_FORCE_CTRL;
6790 typedef enum MEM_PWR_FORCE_CTRL2 {
6791         NO_FORCE_REQ                                     = 0x0,
6792         FORCE_LIGHT_SLEEP_REQ                            = 0x1,
6793 } MEM_PWR_FORCE_CTRL2;
6794 typedef enum MEM_PWR_DIS_CTRL {
6795         ENABLE_MEM_PWR_CTRL                              = 0x0,
6796         DISABLE_MEM_PWR_CTRL                             = 0x1,
6797 } MEM_PWR_DIS_CTRL;
6798 typedef enum MEM_PWR_SEL_CTRL {
6799         DYNAMIC_SHUT_DOWN_ENABLE                         = 0x0,
6800         DYNAMIC_DEEP_SLEEP_ENABLE                        = 0x1,
6801         DYNAMIC_LIGHT_SLEEP_ENABLE                       = 0x2,
6802 } MEM_PWR_SEL_CTRL;
6803 typedef enum MEM_PWR_SEL_CTRL2 {
6804         DYNAMIC_DEEP_SLEEP_EN                            = 0x0,
6805         DYNAMIC_LIGHT_SLEEP_EN                           = 0x1,
6806 } MEM_PWR_SEL_CTRL2;
6807 
6808 #endif /* GFX_8_1_ENUM_H */