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24 #ifndef GFX_7_0_D_H
25 #define GFX_7_0_D_H
26
27 #define mmCB_BLEND_RED 0xa105
28 #define mmCB_BLEND_GREEN 0xa106
29 #define mmCB_BLEND_BLUE 0xa107
30 #define mmCB_BLEND_ALPHA 0xa108
31 #define mmCB_COLOR_CONTROL 0xa202
32 #define mmCB_BLEND0_CONTROL 0xa1e0
33 #define mmCB_BLEND1_CONTROL 0xa1e1
34 #define mmCB_BLEND2_CONTROL 0xa1e2
35 #define mmCB_BLEND3_CONTROL 0xa1e3
36 #define mmCB_BLEND4_CONTROL 0xa1e4
37 #define mmCB_BLEND5_CONTROL 0xa1e5
38 #define mmCB_BLEND6_CONTROL 0xa1e6
39 #define mmCB_BLEND7_CONTROL 0xa1e7
40 #define mmCB_COLOR0_BASE 0xa318
41 #define mmCB_COLOR1_BASE 0xa327
42 #define mmCB_COLOR2_BASE 0xa336
43 #define mmCB_COLOR3_BASE 0xa345
44 #define mmCB_COLOR4_BASE 0xa354
45 #define mmCB_COLOR5_BASE 0xa363
46 #define mmCB_COLOR6_BASE 0xa372
47 #define mmCB_COLOR7_BASE 0xa381
48 #define mmCB_COLOR0_PITCH 0xa319
49 #define mmCB_COLOR1_PITCH 0xa328
50 #define mmCB_COLOR2_PITCH 0xa337
51 #define mmCB_COLOR3_PITCH 0xa346
52 #define mmCB_COLOR4_PITCH 0xa355
53 #define mmCB_COLOR5_PITCH 0xa364
54 #define mmCB_COLOR6_PITCH 0xa373
55 #define mmCB_COLOR7_PITCH 0xa382
56 #define mmCB_COLOR0_SLICE 0xa31a
57 #define mmCB_COLOR1_SLICE 0xa329
58 #define mmCB_COLOR2_SLICE 0xa338
59 #define mmCB_COLOR3_SLICE 0xa347
60 #define mmCB_COLOR4_SLICE 0xa356
61 #define mmCB_COLOR5_SLICE 0xa365
62 #define mmCB_COLOR6_SLICE 0xa374
63 #define mmCB_COLOR7_SLICE 0xa383
64 #define mmCB_COLOR0_VIEW 0xa31b
65 #define mmCB_COLOR1_VIEW 0xa32a
66 #define mmCB_COLOR2_VIEW 0xa339
67 #define mmCB_COLOR3_VIEW 0xa348
68 #define mmCB_COLOR4_VIEW 0xa357
69 #define mmCB_COLOR5_VIEW 0xa366
70 #define mmCB_COLOR6_VIEW 0xa375
71 #define mmCB_COLOR7_VIEW 0xa384
72 #define mmCB_COLOR0_INFO 0xa31c
73 #define mmCB_COLOR1_INFO 0xa32b
74 #define mmCB_COLOR2_INFO 0xa33a
75 #define mmCB_COLOR3_INFO 0xa349
76 #define mmCB_COLOR4_INFO 0xa358
77 #define mmCB_COLOR5_INFO 0xa367
78 #define mmCB_COLOR6_INFO 0xa376
79 #define mmCB_COLOR7_INFO 0xa385
80 #define mmCB_COLOR0_ATTRIB 0xa31d
81 #define mmCB_COLOR1_ATTRIB 0xa32c
82 #define mmCB_COLOR2_ATTRIB 0xa33b
83 #define mmCB_COLOR3_ATTRIB 0xa34a
84 #define mmCB_COLOR4_ATTRIB 0xa359
85 #define mmCB_COLOR5_ATTRIB 0xa368
86 #define mmCB_COLOR6_ATTRIB 0xa377
87 #define mmCB_COLOR7_ATTRIB 0xa386
88 #define mmCB_COLOR0_CMASK 0xa31f
89 #define mmCB_COLOR1_CMASK 0xa32e
90 #define mmCB_COLOR2_CMASK 0xa33d
91 #define mmCB_COLOR3_CMASK 0xa34c
92 #define mmCB_COLOR4_CMASK 0xa35b
93 #define mmCB_COLOR5_CMASK 0xa36a
94 #define mmCB_COLOR6_CMASK 0xa379
95 #define mmCB_COLOR7_CMASK 0xa388
96 #define mmCB_COLOR0_CMASK_SLICE 0xa320
97 #define mmCB_COLOR1_CMASK_SLICE 0xa32f
98 #define mmCB_COLOR2_CMASK_SLICE 0xa33e
99 #define mmCB_COLOR3_CMASK_SLICE 0xa34d
100 #define mmCB_COLOR4_CMASK_SLICE 0xa35c
101 #define mmCB_COLOR5_CMASK_SLICE 0xa36b
102 #define mmCB_COLOR6_CMASK_SLICE 0xa37a
103 #define mmCB_COLOR7_CMASK_SLICE 0xa389
104 #define mmCB_COLOR0_FMASK 0xa321
105 #define mmCB_COLOR1_FMASK 0xa330
106 #define mmCB_COLOR2_FMASK 0xa33f
107 #define mmCB_COLOR3_FMASK 0xa34e
108 #define mmCB_COLOR4_FMASK 0xa35d
109 #define mmCB_COLOR5_FMASK 0xa36c
110 #define mmCB_COLOR6_FMASK 0xa37b
111 #define mmCB_COLOR7_FMASK 0xa38a
112 #define mmCB_COLOR0_FMASK_SLICE 0xa322
113 #define mmCB_COLOR1_FMASK_SLICE 0xa331
114 #define mmCB_COLOR2_FMASK_SLICE 0xa340
115 #define mmCB_COLOR3_FMASK_SLICE 0xa34f
116 #define mmCB_COLOR4_FMASK_SLICE 0xa35e
117 #define mmCB_COLOR5_FMASK_SLICE 0xa36d
118 #define mmCB_COLOR6_FMASK_SLICE 0xa37c
119 #define mmCB_COLOR7_FMASK_SLICE 0xa38b
120 #define mmCB_COLOR0_CLEAR_WORD0 0xa323
121 #define mmCB_COLOR1_CLEAR_WORD0 0xa332
122 #define mmCB_COLOR2_CLEAR_WORD0 0xa341
123 #define mmCB_COLOR3_CLEAR_WORD0 0xa350
124 #define mmCB_COLOR4_CLEAR_WORD0 0xa35f
125 #define mmCB_COLOR5_CLEAR_WORD0 0xa36e
126 #define mmCB_COLOR6_CLEAR_WORD0 0xa37d
127 #define mmCB_COLOR7_CLEAR_WORD0 0xa38c
128 #define mmCB_COLOR0_CLEAR_WORD1 0xa324
129 #define mmCB_COLOR1_CLEAR_WORD1 0xa333
130 #define mmCB_COLOR2_CLEAR_WORD1 0xa342
131 #define mmCB_COLOR3_CLEAR_WORD1 0xa351
132 #define mmCB_COLOR4_CLEAR_WORD1 0xa360
133 #define mmCB_COLOR5_CLEAR_WORD1 0xa36f
134 #define mmCB_COLOR6_CLEAR_WORD1 0xa37e
135 #define mmCB_COLOR7_CLEAR_WORD1 0xa38d
136 #define mmCB_TARGET_MASK 0xa08e
137 #define mmCB_SHADER_MASK 0xa08f
138 #define mmCB_HW_CONTROL 0x2684
139 #define mmCB_HW_CONTROL_1 0x2685
140 #define mmCB_HW_CONTROL_2 0x2686
141 #define mmCB_HW_CONTROL_3 0x2683
142 #define mmCB_PERFCOUNTER_FILTER 0xdc00
143 #define mmCB_PERFCOUNTER0_SELECT 0xdc01
144 #define mmCB_PERFCOUNTER0_SELECT1 0xdc02
145 #define mmCB_PERFCOUNTER1_SELECT 0xdc03
146 #define mmCB_PERFCOUNTER2_SELECT 0xdc04
147 #define mmCB_PERFCOUNTER3_SELECT 0xdc05
148 #define mmCB_PERFCOUNTER0_LO 0xd406
149 #define mmCB_PERFCOUNTER1_LO 0xd408
150 #define mmCB_PERFCOUNTER2_LO 0xd40a
151 #define mmCB_PERFCOUNTER3_LO 0xd40c
152 #define mmCB_PERFCOUNTER0_HI 0xd407
153 #define mmCB_PERFCOUNTER1_HI 0xd409
154 #define mmCB_PERFCOUNTER2_HI 0xd40b
155 #define mmCB_PERFCOUNTER3_HI 0xd40d
156 #define mmCB_CGTT_SCLK_CTRL 0xf0a8
157 #define mmCB_DEBUG_BUS_1 0x2699
158 #define mmCB_DEBUG_BUS_2 0x269a
159 #define mmCB_DEBUG_BUS_3 0x269b
160 #define mmCB_DEBUG_BUS_4 0x269c
161 #define mmCB_DEBUG_BUS_5 0x269d
162 #define mmCB_DEBUG_BUS_6 0x269e
163 #define mmCB_DEBUG_BUS_7 0x269f
164 #define mmCB_DEBUG_BUS_8 0x26a0
165 #define mmCB_DEBUG_BUS_9 0x26a1
166 #define mmCB_DEBUG_BUS_10 0x26a2
167 #define mmCB_DEBUG_BUS_11 0x26a3
168 #define mmCB_DEBUG_BUS_12 0x26a4
169 #define mmCB_DEBUG_BUS_13 0x26a5
170 #define mmCB_DEBUG_BUS_14 0x26a6
171 #define mmCB_DEBUG_BUS_15 0x26a7
172 #define mmCB_DEBUG_BUS_16 0x26a8
173 #define mmCB_DEBUG_BUS_17 0x26a9
174 #define mmCB_DEBUG_BUS_18 0x26aa
175 #define mmCP_DFY_CNTL 0x3020
176 #define mmCP_DFY_STAT 0x3021
177 #define mmCP_DFY_ADDR_HI 0x3022
178 #define mmCP_DFY_ADDR_LO 0x3023
179 #define mmCP_DFY_DATA_0 0x3024
180 #define mmCP_DFY_DATA_1 0x3025
181 #define mmCP_DFY_DATA_2 0x3026
182 #define mmCP_DFY_DATA_3 0x3027
183 #define mmCP_DFY_DATA_4 0x3028
184 #define mmCP_DFY_DATA_5 0x3029
185 #define mmCP_DFY_DATA_6 0x302a
186 #define mmCP_DFY_DATA_7 0x302b
187 #define mmCP_DFY_DATA_8 0x302c
188 #define mmCP_DFY_DATA_9 0x302d
189 #define mmCP_DFY_DATA_10 0x302e
190 #define mmCP_DFY_DATA_11 0x302f
191 #define mmCP_DFY_DATA_12 0x3030
192 #define mmCP_DFY_DATA_13 0x3031
193 #define mmCP_DFY_DATA_14 0x3032
194 #define mmCP_DFY_DATA_15 0x3033
195 #define mmCP_RB0_BASE 0x3040
196 #define mmCP_RB0_BASE_HI 0x30b1
197 #define mmCP_RB_BASE 0x3040
198 #define mmCP_RB1_BASE 0x3060
199 #define mmCP_RB1_BASE_HI 0x30b2
200 #define mmCP_RB2_BASE 0x3065
201 #define mmCP_RB0_CNTL 0x3041
202 #define mmCP_RB_CNTL 0x3041
203 #define mmCP_RB1_CNTL 0x3061
204 #define mmCP_RB2_CNTL 0x3066
205 #define mmCP_RB_RPTR_WR 0x3042
206 #define mmCP_RB0_RPTR_ADDR 0x3043
207 #define mmCP_RB_RPTR_ADDR 0x3043
208 #define mmCP_RB1_RPTR_ADDR 0x3062
209 #define mmCP_RB2_RPTR_ADDR 0x3067
210 #define mmCP_RB0_RPTR_ADDR_HI 0x3044
211 #define mmCP_RB_RPTR_ADDR_HI 0x3044
212 #define mmCP_RB1_RPTR_ADDR_HI 0x3063
213 #define mmCP_RB2_RPTR_ADDR_HI 0x3068
214 #define mmCP_RB0_WPTR 0x3045
215 #define mmCP_RB_WPTR 0x3045
216 #define mmCP_RB1_WPTR 0x3064
217 #define mmCP_RB2_WPTR 0x3069
218 #define mmCP_RB_WPTR_POLL_ADDR_LO 0x3046
219 #define mmCP_RB_WPTR_POLL_ADDR_HI 0x3047
220 #define mmGC_PRIV_MODE 0x3048
221 #define mmCP_INT_CNTL 0x3049
222 #define mmCP_INT_CNTL_RING0 0x306a
223 #define mmCP_INT_CNTL_RING1 0x306b
224 #define mmCP_INT_CNTL_RING2 0x306c
225 #define mmCP_INT_STATUS 0x304a
226 #define mmCP_INT_STATUS_RING0 0x306d
227 #define mmCP_INT_STATUS_RING1 0x306e
228 #define mmCP_INT_STATUS_RING2 0x306f
229 #define mmCP_DEVICE_ID 0x304b
230 #define mmCP_RING_PRIORITY_CNTS 0x304c
231 #define mmCP_ME0_PIPE_PRIORITY_CNTS 0x304c
232 #define mmCP_RING0_PRIORITY 0x304d
233 #define mmCP_ME0_PIPE0_PRIORITY 0x304d
234 #define mmCP_RING1_PRIORITY 0x304e
235 #define mmCP_ME0_PIPE1_PRIORITY 0x304e
236 #define mmCP_RING2_PRIORITY 0x304f
237 #define mmCP_ME0_PIPE2_PRIORITY 0x304f
238 #define mmCP_ENDIAN_SWAP 0x3050
239 #define mmCP_RB_VMID 0x3051
240 #define mmCP_PFP_UCODE_ADDR 0x3054
241 #define mmCP_PFP_UCODE_DATA 0x3055
242 #define mmCP_ME_RAM_RADDR 0x3056
243 #define mmCP_ME_RAM_WADDR 0x3057
244 #define mmCP_ME_RAM_DATA 0x3058
245 #define mmCGTT_CPC_CLK_CTRL 0xf0b2
246 #define mmCGTT_CPF_CLK_CTRL 0xf0b1
247 #define mmCGTT_CP_CLK_CTRL 0xf0b0
248 #define mmCP_CE_UCODE_ADDR 0x305a
249 #define mmCP_CE_UCODE_DATA 0x305b
250 #define mmCP_MEC_ME1_UCODE_ADDR 0x305c
251 #define mmCP_MEC_ME1_UCODE_DATA 0x305d
252 #define mmCP_MEC_ME2_UCODE_ADDR 0x305e
253 #define mmCP_MEC_ME2_UCODE_DATA 0x305f
254 #define mmCP_PWR_CNTL 0x3078
255 #define mmCP_MEM_SLP_CNTL 0x3079
256 #define mmCP_ECC_FIRSTOCCURRENCE 0x307a
257 #define mmCP_ECC_FIRSTOCCURRENCE_RING0 0x307b
258 #define mmCP_ECC_FIRSTOCCURRENCE_RING1 0x307c
259 #define mmCP_ECC_FIRSTOCCURRENCE_RING2 0x307d
260 #define mmCP_CPF_DEBUG 0x3080
261 #define mmCP_FETCHER_SOURCE 0x3082
262 #define mmCP_PQ_WPTR_POLL_CNTL 0x3083
263 #define mmCP_PQ_WPTR_POLL_CNTL1 0x3084
264 #define mmCPC_INT_CNTL 0x30b4
265 #define mmCP_ME1_PIPE0_INT_CNTL 0x3085
266 #define mmCP_ME1_PIPE1_INT_CNTL 0x3086
267 #define mmCP_ME1_PIPE2_INT_CNTL 0x3087
268 #define mmCP_ME1_PIPE3_INT_CNTL 0x3088
269 #define mmCP_ME2_PIPE0_INT_CNTL 0x3089
270 #define mmCP_ME2_PIPE1_INT_CNTL 0x308a
271 #define mmCP_ME2_PIPE2_INT_CNTL 0x308b
272 #define mmCP_ME2_PIPE3_INT_CNTL 0x308c
273 #define mmCPC_INT_STATUS 0x30b5
274 #define mmCP_ME1_PIPE0_INT_STATUS 0x308d
275 #define mmCP_ME1_PIPE1_INT_STATUS 0x308e
276 #define mmCP_ME1_PIPE2_INT_STATUS 0x308f
277 #define mmCP_ME1_PIPE3_INT_STATUS 0x3090
278 #define mmCP_ME2_PIPE0_INT_STATUS 0x3091
279 #define mmCP_ME2_PIPE1_INT_STATUS 0x3092
280 #define mmCP_ME2_PIPE2_INT_STATUS 0x3093
281 #define mmCP_ME2_PIPE3_INT_STATUS 0x3094
282 #define mmCP_ME1_INT_STAT_DEBUG 0x3095
283 #define mmCP_ME2_INT_STAT_DEBUG 0x3096
284 #define mmCP_ME1_PIPE_PRIORITY_CNTS 0x3099
285 #define mmCP_ME1_PIPE0_PRIORITY 0x309a
286 #define mmCP_ME1_PIPE1_PRIORITY 0x309b
287 #define mmCP_ME1_PIPE2_PRIORITY 0x309c
288 #define mmCP_ME1_PIPE3_PRIORITY 0x309d
289 #define mmCP_ME2_PIPE_PRIORITY_CNTS 0x309e
290 #define mmCP_ME2_PIPE0_PRIORITY 0x309f
291 #define mmCP_ME2_PIPE1_PRIORITY 0x30a0
292 #define mmCP_ME2_PIPE2_PRIORITY 0x30a1
293 #define mmCP_ME2_PIPE3_PRIORITY 0x30a2
294 #define mmCP_CE_PRGRM_CNTR_START 0x30a3
295 #define mmCP_PFP_PRGRM_CNTR_START 0x30a4
296 #define mmCP_ME_PRGRM_CNTR_START 0x30a5
297 #define mmCP_MEC1_PRGRM_CNTR_START 0x30a6
298 #define mmCP_MEC2_PRGRM_CNTR_START 0x30a7
299 #define mmCP_CE_INTR_ROUTINE_START 0x30a8
300 #define mmCP_PFP_INTR_ROUTINE_START 0x30a9
301 #define mmCP_ME_INTR_ROUTINE_START 0x30aa
302 #define mmCP_MEC1_INTR_ROUTINE_START 0x30ab
303 #define mmCP_MEC2_INTR_ROUTINE_START 0x30ac
304 #define mmCP_CONTEXT_CNTL 0x30ad
305 #define mmCP_MAX_CONTEXT 0x30ae
306 #define mmCP_IQ_WAIT_TIME1 0x30af
307 #define mmCP_IQ_WAIT_TIME2 0x30b0
308 #define mmCP_VMID_RESET 0x30b3
309 #define mmCP_VMID_PREEMPT 0x30b6
310 #define mmCP_PQ_STATUS 0x30b8
311 #define mmCP_CPC_STATUS 0x2084
312 #define mmCP_CPC_BUSY_STAT 0x2085
313 #define mmCP_CPC_STALLED_STAT1 0x2086
314 #define mmCP_CPF_STATUS 0x2087
315 #define mmCP_CPF_BUSY_STAT 0x2088
316 #define mmCP_CPF_STALLED_STAT1 0x2089
317 #define mmCP_CPC_MC_CNTL 0x208a
318 #define mmCP_CPC_GRBM_FREE_COUNT 0x208b
319 #define mmCP_MEC_CNTL 0x208d
320 #define mmCP_MEC_ME1_HEADER_DUMP 0x208e
321 #define mmCP_MEC_ME2_HEADER_DUMP 0x208f
322 #define mmCP_CPC_SCRATCH_INDEX 0x2090
323 #define mmCP_CPC_SCRATCH_DATA 0x2091
324 #define mmCPG_PERFCOUNTER1_SELECT 0xd800
325 #define mmCPG_PERFCOUNTER1_LO 0xd000
326 #define mmCPG_PERFCOUNTER1_HI 0xd001
327 #define mmCPG_PERFCOUNTER0_SELECT1 0xd801
328 #define mmCPG_PERFCOUNTER0_SELECT 0xd802
329 #define mmCPG_PERFCOUNTER0_LO 0xd002
330 #define mmCPG_PERFCOUNTER0_HI 0xd003
331 #define mmCPC_PERFCOUNTER1_SELECT 0xd803
332 #define mmCPC_PERFCOUNTER1_LO 0xd004
333 #define mmCPC_PERFCOUNTER1_HI 0xd005
334 #define mmCPC_PERFCOUNTER0_SELECT1 0xd804
335 #define mmCPC_PERFCOUNTER0_SELECT 0xd809
336 #define mmCPC_PERFCOUNTER0_LO 0xd006
337 #define mmCPC_PERFCOUNTER0_HI 0xd007
338 #define mmCPF_PERFCOUNTER1_SELECT 0xd805
339 #define mmCPF_PERFCOUNTER1_LO 0xd008
340 #define mmCPF_PERFCOUNTER1_HI 0xd009
341 #define mmCPF_PERFCOUNTER0_SELECT1 0xd806
342 #define mmCPF_PERFCOUNTER0_SELECT 0xd807
343 #define mmCPF_PERFCOUNTER0_LO 0xd00a
344 #define mmCPF_PERFCOUNTER0_HI 0xd00b
345 #define mmCP_CPC_HALT_HYST_COUNT 0x20a7
346 #define mmCP_CE_COMPARE_COUNT 0x20c0
347 #define mmCP_CE_DE_COUNT 0x20c1
348 #define mmCP_DE_CE_COUNT 0x20c2
349 #define mmCP_DE_LAST_INVAL_COUNT 0x20c3
350 #define mmCP_DE_DE_COUNT 0x20c4
351 #define mmCP_EOP_DONE_EVENT_CNTL 0xc0d5
352 #define mmCP_EOP_DONE_DATA_CNTL 0xc0d6
353 #define mmCP_EOP_DONE_ADDR_LO 0xc000
354 #define mmCP_EOP_DONE_ADDR_HI 0xc001
355 #define mmCP_EOP_DONE_DATA_LO 0xc002
356 #define mmCP_EOP_DONE_DATA_HI 0xc003
357 #define mmCP_EOP_LAST_FENCE_LO 0xc004
358 #define mmCP_EOP_LAST_FENCE_HI 0xc005
359 #define mmCP_STREAM_OUT_ADDR_LO 0xc006
360 #define mmCP_STREAM_OUT_ADDR_HI 0xc007
361 #define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO 0xc008
362 #define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI 0xc009
363 #define mmCP_NUM_PRIM_NEEDED_COUNT0_LO 0xc00a
364 #define mmCP_NUM_PRIM_NEEDED_COUNT0_HI 0xc00b
365 #define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO 0xc00c
366 #define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI 0xc00d
367 #define mmCP_NUM_PRIM_NEEDED_COUNT1_LO 0xc00e
368 #define mmCP_NUM_PRIM_NEEDED_COUNT1_HI 0xc00f
369 #define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO 0xc010
370 #define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI 0xc011
371 #define mmCP_NUM_PRIM_NEEDED_COUNT2_LO 0xc012
372 #define mmCP_NUM_PRIM_NEEDED_COUNT2_HI 0xc013
373 #define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO 0xc014
374 #define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI 0xc015
375 #define mmCP_NUM_PRIM_NEEDED_COUNT3_LO 0xc016
376 #define mmCP_NUM_PRIM_NEEDED_COUNT3_HI 0xc017
377 #define mmCP_PIPE_STATS_ADDR_LO 0xc018
378 #define mmCP_PIPE_STATS_ADDR_HI 0xc019
379 #define mmCP_VGT_IAVERT_COUNT_LO 0xc01a
380 #define mmCP_VGT_IAVERT_COUNT_HI 0xc01b
381 #define mmCP_VGT_IAPRIM_COUNT_LO 0xc01c
382 #define mmCP_VGT_IAPRIM_COUNT_HI 0xc01d
383 #define mmCP_VGT_GSPRIM_COUNT_LO 0xc01e
384 #define mmCP_VGT_GSPRIM_COUNT_HI 0xc01f
385 #define mmCP_VGT_VSINVOC_COUNT_LO 0xc020
386 #define mmCP_VGT_VSINVOC_COUNT_HI 0xc021
387 #define mmCP_VGT_GSINVOC_COUNT_LO 0xc022
388 #define mmCP_VGT_GSINVOC_COUNT_HI 0xc023
389 #define mmCP_VGT_HSINVOC_COUNT_LO 0xc024
390 #define mmCP_VGT_HSINVOC_COUNT_HI 0xc025
391 #define mmCP_VGT_DSINVOC_COUNT_LO 0xc026
392 #define mmCP_VGT_DSINVOC_COUNT_HI 0xc027
393 #define mmCP_PA_CINVOC_COUNT_LO 0xc028
394 #define mmCP_PA_CINVOC_COUNT_HI 0xc029
395 #define mmCP_PA_CPRIM_COUNT_LO 0xc02a
396 #define mmCP_PA_CPRIM_COUNT_HI 0xc02b
397 #define mmCP_SC_PSINVOC_COUNT0_LO 0xc02c
398 #define mmCP_SC_PSINVOC_COUNT0_HI 0xc02d
399 #define mmCP_SC_PSINVOC_COUNT1_LO 0xc02e
400 #define mmCP_SC_PSINVOC_COUNT1_HI 0xc02f
401 #define mmCP_VGT_CSINVOC_COUNT_LO 0xc030
402 #define mmCP_VGT_CSINVOC_COUNT_HI 0xc031
403 #define mmCP_STRMOUT_CNTL 0xc03f
404 #define mmSCRATCH_REG0 0xc040
405 #define mmSCRATCH_REG1 0xc041
406 #define mmSCRATCH_REG2 0xc042
407 #define mmSCRATCH_REG3 0xc043
408 #define mmSCRATCH_REG4 0xc044
409 #define mmSCRATCH_REG5 0xc045
410 #define mmSCRATCH_REG6 0xc046
411 #define mmSCRATCH_REG7 0xc047
412 #define mmSCRATCH_UMSK 0xc050
413 #define mmSCRATCH_ADDR 0xc051
414 #define mmCP_PFP_ATOMIC_PREOP_LO 0xc052
415 #define mmCP_PFP_ATOMIC_PREOP_HI 0xc053
416 #define mmCP_PFP_GDS_ATOMIC0_PREOP_LO 0xc054
417 #define mmCP_PFP_GDS_ATOMIC0_PREOP_HI 0xc055
418 #define mmCP_PFP_GDS_ATOMIC1_PREOP_LO 0xc056
419 #define mmCP_PFP_GDS_ATOMIC1_PREOP_HI 0xc057
420 #define mmCP_APPEND_ADDR_LO 0xc058
421 #define mmCP_APPEND_ADDR_HI 0xc059
422 #define mmCP_APPEND_DATA 0xc05a
423 #define mmCP_APPEND_LAST_CS_FENCE 0xc05b
424 #define mmCP_APPEND_LAST_PS_FENCE 0xc05c
425 #define mmCP_ATOMIC_PREOP_LO 0xc05d
426 #define mmCP_ME_ATOMIC_PREOP_LO 0xc05d
427 #define mmCP_ATOMIC_PREOP_HI 0xc05e
428 #define mmCP_ME_ATOMIC_PREOP_HI 0xc05e
429 #define mmCP_GDS_ATOMIC0_PREOP_LO 0xc05f
430 #define mmCP_ME_GDS_ATOMIC0_PREOP_LO 0xc05f
431 #define mmCP_GDS_ATOMIC0_PREOP_HI 0xc060
432 #define mmCP_ME_GDS_ATOMIC0_PREOP_HI 0xc060
433 #define mmCP_GDS_ATOMIC1_PREOP_LO 0xc061
434 #define mmCP_ME_GDS_ATOMIC1_PREOP_LO 0xc061
435 #define mmCP_GDS_ATOMIC1_PREOP_HI 0xc062
436 #define mmCP_ME_GDS_ATOMIC1_PREOP_HI 0xc062
437 #define mmCP_ME_MC_WADDR_LO 0xc069
438 #define mmCP_ME_MC_WADDR_HI 0xc06a
439 #define mmCP_ME_MC_WDATA_LO 0xc06b
440 #define mmCP_ME_MC_WDATA_HI 0xc06c
441 #define mmCP_ME_MC_RADDR_LO 0xc06d
442 #define mmCP_ME_MC_RADDR_HI 0xc06e
443 #define mmCP_SEM_WAIT_TIMER 0xc06f
444 #define mmCP_SIG_SEM_ADDR_LO 0xc070
445 #define mmCP_SIG_SEM_ADDR_HI 0xc071
446 #define mmCP_SEM_INCOMPLETE_TIMER_CNTL 0xc072
447 #define mmCP_WAIT_SEM_STATUS 0xc073
448 #define mmCP_WAIT_SEM_ADDR_LO 0xc075
449 #define mmCP_WAIT_SEM_ADDR_HI 0xc076
450 #define mmCP_WAIT_REG_MEM_TIMEOUT 0xc074
451 #define mmCP_COHER_START_DELAY 0xc07b
452 #define mmCP_COHER_CNTL 0xc07c
453 #define mmCP_COHER_SIZE 0xc07d
454 #define mmCP_COHER_SIZE_HI 0xc08c
455 #define mmCP_COHER_BASE 0xc07e
456 #define mmCP_COHER_BASE_HI 0xc079
457 #define mmCP_COHER_STATUS 0xc07f
458 #define mmCOHER_DEST_BASE_0 0xa092
459 #define mmCOHER_DEST_BASE_1 0xa093
460 #define mmCOHER_DEST_BASE_2 0xa07e
461 #define mmCOHER_DEST_BASE_3 0xa07f
462 #define mmCOHER_DEST_BASE_HI_0 0xa07a
463 #define mmCOHER_DEST_BASE_HI_1 0xa07b
464 #define mmCOHER_DEST_BASE_HI_2 0xa07c
465 #define mmCOHER_DEST_BASE_HI_3 0xa07d
466 #define mmCP_DMA_ME_SRC_ADDR 0xc080
467 #define mmCP_DMA_ME_SRC_ADDR_HI 0xc081
468 #define mmCP_DMA_ME_DST_ADDR 0xc082
469 #define mmCP_DMA_ME_DST_ADDR_HI 0xc083
470 #define mmCP_DMA_ME_CONTROL 0xc078
471 #define mmCP_DMA_ME_COMMAND 0xc084
472 #define mmCP_DMA_PFP_SRC_ADDR 0xc085
473 #define mmCP_DMA_PFP_SRC_ADDR_HI 0xc086
474 #define mmCP_DMA_PFP_DST_ADDR 0xc087
475 #define mmCP_DMA_PFP_DST_ADDR_HI 0xc088
476 #define mmCP_DMA_PFP_CONTROL 0xc077
477 #define mmCP_DMA_PFP_COMMAND 0xc089
478 #define mmCP_DMA_CNTL 0xc08a
479 #define mmCP_DMA_READ_TAGS 0xc08b
480 #define mmCP_PFP_IB_CONTROL 0xc08d
481 #define mmCP_PFP_LOAD_CONTROL 0xc08e
482 #define mmCP_SCRATCH_INDEX 0xc08f
483 #define mmCP_SCRATCH_DATA 0xc090
484 #define mmCP_RB_OFFSET 0xc091
485 #define mmCP_IB1_OFFSET 0xc092
486 #define mmCP_IB2_OFFSET 0xc093
487 #define mmCP_IB1_PREAMBLE_BEGIN 0xc094
488 #define mmCP_IB1_PREAMBLE_END 0xc095
489 #define mmCP_IB2_PREAMBLE_BEGIN 0xc096
490 #define mmCP_IB2_PREAMBLE_END 0xc097
491 #define mmCP_STALLED_STAT1 0x219d
492 #define mmCP_STALLED_STAT2 0x219e
493 #define mmCP_STALLED_STAT3 0x219c
494 #define mmCP_BUSY_STAT 0x219f
495 #define mmCP_STAT 0x21a0
496 #define mmCP_ME_HEADER_DUMP 0x21a1
497 #define mmCP_PFP_HEADER_DUMP 0x21a2
498 #define mmCP_GRBM_FREE_COUNT 0x21a3
499 #define mmCP_CE_HEADER_DUMP 0x21a4
500 #define mmCP_MC_PACK_DELAY_CNT 0x21a7
501 #define mmCP_MC_TAG_CNTL 0x21a8
502 #define mmCP_MC_TAG_DATA 0x21a9
503 #define mmCP_CSF_STAT 0x21b4
504 #define mmCP_CSF_CNTL 0x21b5
505 #define mmCP_ME_CNTL 0x21b6
506 #define mmCP_CNTX_STAT 0x21b8
507 #define mmCP_ME_PREEMPTION 0x21b9
508 #define mmCP_RB0_RPTR 0x21c0
509 #define mmCP_RB_RPTR 0x21c0
510 #define mmCP_RB1_RPTR 0x21bf
511 #define mmCP_RB2_RPTR 0x21be
512 #define mmCP_RB_WPTR_DELAY 0x21c1
513 #define mmCP_RB_WPTR_POLL_CNTL 0x21c2
514 #define mmCP_CE_INIT_BASE_LO 0xc0c3
515 #define mmCP_CE_INIT_BASE_HI 0xc0c4
516 #define mmCP_CE_INIT_BUFSZ 0xc0c5
517 #define mmCP_CE_IB1_BASE_LO 0xc0c6
518 #define mmCP_CE_IB1_BASE_HI 0xc0c7
519 #define mmCP_CE_IB1_BUFSZ 0xc0c8
520 #define mmCP_CE_IB2_BASE_LO 0xc0c9
521 #define mmCP_CE_IB2_BASE_HI 0xc0ca
522 #define mmCP_CE_IB2_BUFSZ 0xc0cb
523 #define mmCP_IB1_BASE_LO 0xc0cc
524 #define mmCP_IB1_BASE_HI 0xc0cd
525 #define mmCP_IB1_BUFSZ 0xc0ce
526 #define mmCP_IB2_BASE_LO 0xc0cf
527 #define mmCP_IB2_BASE_HI 0xc0d0
528 #define mmCP_IB2_BUFSZ 0xc0d1
529 #define mmCP_ST_BASE_LO 0xc0d2
530 #define mmCP_ST_BASE_HI 0xc0d3
531 #define mmCP_ST_BUFSZ 0xc0d4
532 #define mmCP_ROQ_THRESHOLDS 0x21bc
533 #define mmCP_MEQ_STQ_THRESHOLD 0x21bd
534 #define mmCP_ROQ1_THRESHOLDS 0x21d5
535 #define mmCP_ROQ2_THRESHOLDS 0x21d6
536 #define mmCP_STQ_THRESHOLDS 0x21d7
537 #define mmCP_QUEUE_THRESHOLDS 0x21d8
538 #define mmCP_MEQ_THRESHOLDS 0x21d9
539 #define mmCP_ROQ_AVAIL 0x21da
540 #define mmCP_STQ_AVAIL 0x21db
541 #define mmCP_ROQ2_AVAIL 0x21dc
542 #define mmCP_MEQ_AVAIL 0x21dd
543 #define mmCP_CMD_INDEX 0x21de
544 #define mmCP_CMD_DATA 0x21df
545 #define mmCP_ROQ_RB_STAT 0x21e0
546 #define mmCP_ROQ_IB1_STAT 0x21e1
547 #define mmCP_ROQ_IB2_STAT 0x21e2
548 #define mmCP_STQ_STAT 0x21e3
549 #define mmCP_STQ_WR_STAT 0x21e4
550 #define mmCP_MEQ_STAT 0x21e5
551 #define mmCP_CEQ1_AVAIL 0x21e6
552 #define mmCP_CEQ2_AVAIL 0x21e7
553 #define mmCP_CE_ROQ_RB_STAT 0x21e8
554 #define mmCP_CE_ROQ_IB1_STAT 0x21e9
555 #define mmCP_CE_ROQ_IB2_STAT 0x21ea
556 #define mmCP_INT_STAT_DEBUG 0x21f7
557 #define mmCP_PERFMON_CNTL 0xd808
558 #define mmCP_PERFMON_CNTX_CNTL 0xa0d8
559 #define mmCP_RINGID 0xa0d9
560 #define mmCP_PIPEID 0xa0d9
561 #define mmCP_VMID 0xa0da
562 #define mmCP_HPD_ROQ_OFFSETS 0x3240
563 #define mmCP_HPD_EOP_BASE_ADDR 0x3241
564 #define mmCP_HPD_EOP_BASE_ADDR_HI 0x3242
565 #define mmCP_HPD_EOP_VMID 0x3243
566 #define mmCP_HPD_EOP_CONTROL 0x3244
567 #define mmCP_MQD_BASE_ADDR 0x3245
568 #define mmCP_MQD_BASE_ADDR_HI 0x3246
569 #define mmCP_HQD_ACTIVE 0x3247
570 #define mmCP_HQD_VMID 0x3248
571 #define mmCP_HQD_PERSISTENT_STATE 0x3249
572 #define mmCP_HQD_PIPE_PRIORITY 0x324a
573 #define mmCP_HQD_QUEUE_PRIORITY 0x324b
574 #define mmCP_HQD_QUANTUM 0x324c
575 #define mmCP_HQD_PQ_BASE 0x324d
576 #define mmCP_HQD_PQ_BASE_HI 0x324e
577 #define mmCP_HQD_PQ_RPTR 0x324f
578 #define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x3250
579 #define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x3251
580 #define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x3252
581 #define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x3253
582 #define mmCP_HQD_PQ_DOORBELL_CONTROL 0x3254
583 #define mmCP_HQD_PQ_WPTR 0x3255
584 #define mmCP_HQD_PQ_CONTROL 0x3256
585 #define mmCP_HQD_IB_BASE_ADDR 0x3257
586 #define mmCP_HQD_IB_BASE_ADDR_HI 0x3258
587 #define mmCP_HQD_IB_RPTR 0x3259
588 #define mmCP_HQD_IB_CONTROL 0x325a
589 #define mmCP_HQD_IQ_TIMER 0x325b
590 #define mmCP_HQD_IQ_RPTR 0x325c
591 #define mmCP_HQD_DEQUEUE_REQUEST 0x325d
592 #define mmCP_HQD_DMA_OFFLOAD 0x325e
593 #define mmCP_HQD_SEMA_CMD 0x325f
594 #define mmCP_HQD_MSG_TYPE 0x3260
595 #define mmCP_HQD_ATOMIC0_PREOP_LO 0x3261
596 #define mmCP_HQD_ATOMIC0_PREOP_HI 0x3262
597 #define mmCP_HQD_ATOMIC1_PREOP_LO 0x3263
598 #define mmCP_HQD_ATOMIC1_PREOP_HI 0x3264
599 #define mmCP_HQD_HQ_SCHEDULER0 0x3265
600 #define mmCP_HQD_HQ_SCHEDULER1 0x3266
601 #define mmCP_MQD_CONTROL 0x3267
602 #define mmDB_Z_READ_BASE 0xa012
603 #define mmDB_STENCIL_READ_BASE 0xa013
604 #define mmDB_Z_WRITE_BASE 0xa014
605 #define mmDB_STENCIL_WRITE_BASE 0xa015
606 #define mmDB_DEPTH_INFO 0xa00f
607 #define mmDB_Z_INFO 0xa010
608 #define mmDB_STENCIL_INFO 0xa011
609 #define mmDB_DEPTH_SIZE 0xa016
610 #define mmDB_DEPTH_SLICE 0xa017
611 #define mmDB_DEPTH_VIEW 0xa002
612 #define mmDB_RENDER_CONTROL 0xa000
613 #define mmDB_COUNT_CONTROL 0xa001
614 #define mmDB_RENDER_OVERRIDE 0xa003
615 #define mmDB_RENDER_OVERRIDE2 0xa004
616 #define mmDB_EQAA 0xa201
617 #define mmDB_SHADER_CONTROL 0xa203
618 #define mmDB_DEPTH_BOUNDS_MIN 0xa008
619 #define mmDB_DEPTH_BOUNDS_MAX 0xa009
620 #define mmDB_STENCIL_CLEAR 0xa00a
621 #define mmDB_DEPTH_CLEAR 0xa00b
622 #define mmDB_HTILE_DATA_BASE 0xa005
623 #define mmDB_HTILE_SURFACE 0xa2af
624 #define mmDB_PRELOAD_CONTROL 0xa2b2
625 #define mmDB_STENCILREFMASK 0xa10c
626 #define mmDB_STENCILREFMASK_BF 0xa10d
627 #define mmDB_SRESULTS_COMPARE_STATE0 0xa2b0
628 #define mmDB_SRESULTS_COMPARE_STATE1 0xa2b1
629 #define mmDB_DEPTH_CONTROL 0xa200
630 #define mmDB_STENCIL_CONTROL 0xa10b
631 #define mmDB_ALPHA_TO_MASK 0xa2dc
632 #define mmDB_PERFCOUNTER0_SELECT 0xdc40
633 #define mmDB_PERFCOUNTER1_SELECT 0xdc42
634 #define mmDB_PERFCOUNTER2_SELECT 0xdc44
635 #define mmDB_PERFCOUNTER3_SELECT 0xdc46
636 #define mmDB_PERFCOUNTER0_SELECT1 0xdc41
637 #define mmDB_PERFCOUNTER1_SELECT1 0xdc43
638 #define mmDB_PERFCOUNTER0_LO 0xd440
639 #define mmDB_PERFCOUNTER1_LO 0xd442
640 #define mmDB_PERFCOUNTER2_LO 0xd444
641 #define mmDB_PERFCOUNTER3_LO 0xd446
642 #define mmDB_PERFCOUNTER0_HI 0xd441
643 #define mmDB_PERFCOUNTER1_HI 0xd443
644 #define mmDB_PERFCOUNTER2_HI 0xd445
645 #define mmDB_PERFCOUNTER3_HI 0xd447
646 #define mmDB_DEBUG 0x260c
647 #define mmDB_DEBUG2 0x260d
648 #define mmDB_DEBUG3 0x260e
649 #define mmDB_DEBUG4 0x260f
650 #define mmDB_CREDIT_LIMIT 0x2614
651 #define mmDB_WATERMARKS 0x2615
652 #define mmDB_SUBTILE_CONTROL 0x2616
653 #define mmDB_FREE_CACHELINES 0x2617
654 #define mmDB_FIFO_DEPTH1 0x2618
655 #define mmDB_FIFO_DEPTH2 0x2619
656 #define mmDB_CGTT_CLK_CTRL_0 0xf0a4
657 #define mmDB_ZPASS_COUNT_LOW 0xc3fe
658 #define mmDB_ZPASS_COUNT_HI 0xc3ff
659 #define mmDB_RING_CONTROL 0x261b
660 #define mmDB_READ_DEBUG_0 0x2620
661 #define mmDB_READ_DEBUG_1 0x2621
662 #define mmDB_READ_DEBUG_2 0x2622
663 #define mmDB_READ_DEBUG_3 0x2623
664 #define mmDB_READ_DEBUG_4 0x2624
665 #define mmDB_READ_DEBUG_5 0x2625
666 #define mmDB_READ_DEBUG_6 0x2626
667 #define mmDB_READ_DEBUG_7 0x2627
668 #define mmDB_READ_DEBUG_8 0x2628
669 #define mmDB_READ_DEBUG_9 0x2629
670 #define mmDB_READ_DEBUG_A 0x262a
671 #define mmDB_READ_DEBUG_B 0x262b
672 #define mmDB_READ_DEBUG_C 0x262c
673 #define mmDB_READ_DEBUG_D 0x262d
674 #define mmDB_READ_DEBUG_E 0x262e
675 #define mmDB_READ_DEBUG_F 0x262f
676 #define mmDB_OCCLUSION_COUNT0_LOW 0xc3c0
677 #define mmDB_OCCLUSION_COUNT0_HI 0xc3c1
678 #define mmDB_OCCLUSION_COUNT1_LOW 0xc3c2
679 #define mmDB_OCCLUSION_COUNT1_HI 0xc3c3
680 #define mmDB_OCCLUSION_COUNT2_LOW 0xc3c4
681 #define mmDB_OCCLUSION_COUNT2_HI 0xc3c5
682 #define mmDB_OCCLUSION_COUNT3_LOW 0xc3c6
683 #define mmDB_OCCLUSION_COUNT3_HI 0xc3c7
684 #define mmCC_RB_REDUNDANCY 0x263c
685 #define mmCC_RB_BACKEND_DISABLE 0x263d
686 #define mmGC_USER_RB_REDUNDANCY 0x26de
687 #define mmGC_USER_RB_BACKEND_DISABLE 0x26df
688 #define mmGB_ADDR_CONFIG 0x263e
689 #define mmGB_BACKEND_MAP 0x263f
690 #define mmGB_GPU_ID 0x2640
691 #define mmCC_RB_DAISY_CHAIN 0x2641
692 #define mmGB_TILE_MODE0 0x2644
693 #define mmGB_TILE_MODE1 0x2645
694 #define mmGB_TILE_MODE2 0x2646
695 #define mmGB_TILE_MODE3 0x2647
696 #define mmGB_TILE_MODE4 0x2648
697 #define mmGB_TILE_MODE5 0x2649
698 #define mmGB_TILE_MODE6 0x264a
699 #define mmGB_TILE_MODE7 0x264b
700 #define mmGB_TILE_MODE8 0x264c
701 #define mmGB_TILE_MODE9 0x264d
702 #define mmGB_TILE_MODE10 0x264e
703 #define mmGB_TILE_MODE11 0x264f
704 #define mmGB_TILE_MODE12 0x2650
705 #define mmGB_TILE_MODE13 0x2651
706 #define mmGB_TILE_MODE14 0x2652
707 #define mmGB_TILE_MODE15 0x2653
708 #define mmGB_TILE_MODE16 0x2654
709 #define mmGB_TILE_MODE17 0x2655
710 #define mmGB_TILE_MODE18 0x2656
711 #define mmGB_TILE_MODE19 0x2657
712 #define mmGB_TILE_MODE20 0x2658
713 #define mmGB_TILE_MODE21 0x2659
714 #define mmGB_TILE_MODE22 0x265a
715 #define mmGB_TILE_MODE23 0x265b
716 #define mmGB_TILE_MODE24 0x265c
717 #define mmGB_TILE_MODE25 0x265d
718 #define mmGB_TILE_MODE26 0x265e
719 #define mmGB_TILE_MODE27 0x265f
720 #define mmGB_TILE_MODE28 0x2660
721 #define mmGB_TILE_MODE29 0x2661
722 #define mmGB_TILE_MODE30 0x2662
723 #define mmGB_TILE_MODE31 0x2663
724 #define mmGB_MACROTILE_MODE0 0x2664
725 #define mmGB_MACROTILE_MODE1 0x2665
726 #define mmGB_MACROTILE_MODE2 0x2666
727 #define mmGB_MACROTILE_MODE3 0x2667
728 #define mmGB_MACROTILE_MODE4 0x2668
729 #define mmGB_MACROTILE_MODE5 0x2669
730 #define mmGB_MACROTILE_MODE6 0x266a
731 #define mmGB_MACROTILE_MODE7 0x266b
732 #define mmGB_MACROTILE_MODE8 0x266c
733 #define mmGB_MACROTILE_MODE9 0x266d
734 #define mmGB_MACROTILE_MODE10 0x266e
735 #define mmGB_MACROTILE_MODE11 0x266f
736 #define mmGB_MACROTILE_MODE12 0x2670
737 #define mmGB_MACROTILE_MODE13 0x2671
738 #define mmGB_MACROTILE_MODE14 0x2672
739 #define mmGB_MACROTILE_MODE15 0x2673
740 #define mmGB_EDC_MODE 0x307e
741 #define mmCC_GC_EDC_CONFIG 0x3098
742 #define mmRAS_SIGNATURE_CONTROL 0x3380
743 #define mmRAS_SIGNATURE_MASK 0x3381
744 #define mmRAS_SX_SIGNATURE0 0x3382
745 #define mmRAS_SX_SIGNATURE1 0x3383
746 #define mmRAS_SX_SIGNATURE2 0x3384
747 #define mmRAS_SX_SIGNATURE3 0x3385
748 #define mmRAS_DB_SIGNATURE0 0x338b
749 #define mmRAS_PA_SIGNATURE0 0x338c
750 #define mmRAS_VGT_SIGNATURE0 0x338d
751 #define mmRAS_SQ_SIGNATURE0 0x338e
752 #define mmRAS_SC_SIGNATURE0 0x338f
753 #define mmRAS_SC_SIGNATURE1 0x3390
754 #define mmRAS_SC_SIGNATURE2 0x3391
755 #define mmRAS_SC_SIGNATURE3 0x3392
756 #define mmRAS_SC_SIGNATURE4 0x3393
757 #define mmRAS_SC_SIGNATURE5 0x3394
758 #define mmRAS_SC_SIGNATURE6 0x3395
759 #define mmRAS_SC_SIGNATURE7 0x3396
760 #define mmRAS_IA_SIGNATURE0 0x3397
761 #define mmRAS_IA_SIGNATURE1 0x3398
762 #define mmRAS_SPI_SIGNATURE0 0x3399
763 #define mmRAS_SPI_SIGNATURE1 0x339a
764 #define mmRAS_TA_SIGNATURE0 0x339b
765 #define mmRAS_TD_SIGNATURE0 0x339c
766 #define mmRAS_CB_SIGNATURE0 0x339d
767 #define mmRAS_BCI_SIGNATURE0 0x339e
768 #define mmRAS_BCI_SIGNATURE1 0x339f
769 #define mmGRBM_CAM_INDEX 0x3000
770 #define mmGRBM_CAM_DATA 0x3001
771 #define mmGRBM_CNTL 0x2000
772 #define mmGRBM_SKEW_CNTL 0x2001
773 #define mmGRBM_PWR_CNTL 0x2003
774 #define mmGRBM_STATUS 0x2004
775 #define mmGRBM_STATUS2 0x2002
776 #define mmGRBM_STATUS_SE0 0x2005
777 #define mmGRBM_STATUS_SE1 0x2006
778 #define mmGRBM_STATUS_SE2 0x200e
779 #define mmGRBM_STATUS_SE3 0x200f
780 #define mmGRBM_SOFT_RESET 0x2008
781 #define mmGRBM_DEBUG_CNTL 0x2009
782 #define mmGRBM_DEBUG_DATA 0x200a
783 #define mmGRBM_GFX_INDEX 0xc200
784 #define mmGRBM_GFX_CLKEN_CNTL 0x200c
785 #define mmGRBM_WAIT_IDLE_CLOCKS 0x200d
786 #define mmGRBM_DEBUG 0x2014
787 #define mmGRBM_DEBUG_SNAPSHOT 0x2015
788 #define mmGRBM_READ_ERROR 0x2016
789 #define mmGRBM_READ_ERROR2 0x2017
790 #define mmGRBM_INT_CNTL 0x2018
791 #define mmGRBM_PERFCOUNTER0_SELECT 0xd840
792 #define mmGRBM_PERFCOUNTER1_SELECT 0xd841
793 #define mmGRBM_SE0_PERFCOUNTER_SELECT 0xd842
794 #define mmGRBM_SE1_PERFCOUNTER_SELECT 0xd843
795 #define mmGRBM_SE2_PERFCOUNTER_SELECT 0xd844
796 #define mmGRBM_SE3_PERFCOUNTER_SELECT 0xd845
797 #define mmGRBM_PERFCOUNTER0_LO 0xd040
798 #define mmGRBM_PERFCOUNTER0_HI 0xd041
799 #define mmGRBM_PERFCOUNTER1_LO 0xd043
800 #define mmGRBM_PERFCOUNTER1_HI 0xd044
801 #define mmGRBM_SE0_PERFCOUNTER_LO 0xd045
802 #define mmGRBM_SE0_PERFCOUNTER_HI 0xd046
803 #define mmGRBM_SE1_PERFCOUNTER_LO 0xd047
804 #define mmGRBM_SE1_PERFCOUNTER_HI 0xd048
805 #define mmGRBM_SE2_PERFCOUNTER_LO 0xd049
806 #define mmGRBM_SE2_PERFCOUNTER_HI 0xd04a
807 #define mmGRBM_SE3_PERFCOUNTER_LO 0xd04b
808 #define mmGRBM_SE3_PERFCOUNTER_HI 0xd04c
809 #define mmGRBM_SCRATCH_REG0 0x2040
810 #define mmGRBM_SCRATCH_REG1 0x2041
811 #define mmGRBM_SCRATCH_REG2 0x2042
812 #define mmGRBM_SCRATCH_REG3 0x2043
813 #define mmGRBM_SCRATCH_REG4 0x2044
814 #define mmGRBM_SCRATCH_REG5 0x2045
815 #define mmGRBM_SCRATCH_REG6 0x2046
816 #define mmGRBM_SCRATCH_REG7 0x2047
817 #define mmDEBUG_INDEX 0x203c
818 #define mmDEBUG_DATA 0x203d
819 #define mmGRBM_NOWHERE 0x203f
820 #define mmPA_CL_VPORT_XSCALE 0xa10f
821 #define mmPA_CL_VPORT_XOFFSET 0xa110
822 #define mmPA_CL_VPORT_YSCALE 0xa111
823 #define mmPA_CL_VPORT_YOFFSET 0xa112
824 #define mmPA_CL_VPORT_ZSCALE 0xa113
825 #define mmPA_CL_VPORT_ZOFFSET 0xa114
826 #define mmPA_CL_VPORT_XSCALE_1 0xa115
827 #define mmPA_CL_VPORT_XSCALE_2 0xa11b
828 #define mmPA_CL_VPORT_XSCALE_3 0xa121
829 #define mmPA_CL_VPORT_XSCALE_4 0xa127
830 #define mmPA_CL_VPORT_XSCALE_5 0xa12d
831 #define mmPA_CL_VPORT_XSCALE_6 0xa133
832 #define mmPA_CL_VPORT_XSCALE_7 0xa139
833 #define mmPA_CL_VPORT_XSCALE_8 0xa13f
834 #define mmPA_CL_VPORT_XSCALE_9 0xa145
835 #define mmPA_CL_VPORT_XSCALE_10 0xa14b
836 #define mmPA_CL_VPORT_XSCALE_11 0xa151
837 #define mmPA_CL_VPORT_XSCALE_12 0xa157
838 #define mmPA_CL_VPORT_XSCALE_13 0xa15d
839 #define mmPA_CL_VPORT_XSCALE_14 0xa163
840 #define mmPA_CL_VPORT_XSCALE_15 0xa169
841 #define mmPA_CL_VPORT_XOFFSET_1 0xa116
842 #define mmPA_CL_VPORT_XOFFSET_2 0xa11c
843 #define mmPA_CL_VPORT_XOFFSET_3 0xa122
844 #define mmPA_CL_VPORT_XOFFSET_4 0xa128
845 #define mmPA_CL_VPORT_XOFFSET_5 0xa12e
846 #define mmPA_CL_VPORT_XOFFSET_6 0xa134
847 #define mmPA_CL_VPORT_XOFFSET_7 0xa13a
848 #define mmPA_CL_VPORT_XOFFSET_8 0xa140
849 #define mmPA_CL_VPORT_XOFFSET_9 0xa146
850 #define mmPA_CL_VPORT_XOFFSET_10 0xa14c
851 #define mmPA_CL_VPORT_XOFFSET_11 0xa152
852 #define mmPA_CL_VPORT_XOFFSET_12 0xa158
853 #define mmPA_CL_VPORT_XOFFSET_13 0xa15e
854 #define mmPA_CL_VPORT_XOFFSET_14 0xa164
855 #define mmPA_CL_VPORT_XOFFSET_15 0xa16a
856 #define mmPA_CL_VPORT_YSCALE_1 0xa117
857 #define mmPA_CL_VPORT_YSCALE_2 0xa11d
858 #define mmPA_CL_VPORT_YSCALE_3 0xa123
859 #define mmPA_CL_VPORT_YSCALE_4 0xa129
860 #define mmPA_CL_VPORT_YSCALE_5 0xa12f
861 #define mmPA_CL_VPORT_YSCALE_6 0xa135
862 #define mmPA_CL_VPORT_YSCALE_7 0xa13b
863 #define mmPA_CL_VPORT_YSCALE_8 0xa141
864 #define mmPA_CL_VPORT_YSCALE_9 0xa147
865 #define mmPA_CL_VPORT_YSCALE_10 0xa14d
866 #define mmPA_CL_VPORT_YSCALE_11 0xa153
867 #define mmPA_CL_VPORT_YSCALE_12 0xa159
868 #define mmPA_CL_VPORT_YSCALE_13 0xa15f
869 #define mmPA_CL_VPORT_YSCALE_14 0xa165
870 #define mmPA_CL_VPORT_YSCALE_15 0xa16b
871 #define mmPA_CL_VPORT_YOFFSET_1 0xa118
872 #define mmPA_CL_VPORT_YOFFSET_2 0xa11e
873 #define mmPA_CL_VPORT_YOFFSET_3 0xa124
874 #define mmPA_CL_VPORT_YOFFSET_4 0xa12a
875 #define mmPA_CL_VPORT_YOFFSET_5 0xa130
876 #define mmPA_CL_VPORT_YOFFSET_6 0xa136
877 #define mmPA_CL_VPORT_YOFFSET_7 0xa13c
878 #define mmPA_CL_VPORT_YOFFSET_8 0xa142
879 #define mmPA_CL_VPORT_YOFFSET_9 0xa148
880 #define mmPA_CL_VPORT_YOFFSET_10 0xa14e
881 #define mmPA_CL_VPORT_YOFFSET_11 0xa154
882 #define mmPA_CL_VPORT_YOFFSET_12 0xa15a
883 #define mmPA_CL_VPORT_YOFFSET_13 0xa160
884 #define mmPA_CL_VPORT_YOFFSET_14 0xa166
885 #define mmPA_CL_VPORT_YOFFSET_15 0xa16c
886 #define mmPA_CL_VPORT_ZSCALE_1 0xa119
887 #define mmPA_CL_VPORT_ZSCALE_2 0xa11f
888 #define mmPA_CL_VPORT_ZSCALE_3 0xa125
889 #define mmPA_CL_VPORT_ZSCALE_4 0xa12b
890 #define mmPA_CL_VPORT_ZSCALE_5 0xa131
891 #define mmPA_CL_VPORT_ZSCALE_6 0xa137
892 #define mmPA_CL_VPORT_ZSCALE_7 0xa13d
893 #define mmPA_CL_VPORT_ZSCALE_8 0xa143
894 #define mmPA_CL_VPORT_ZSCALE_9 0xa149
895 #define mmPA_CL_VPORT_ZSCALE_10 0xa14f
896 #define mmPA_CL_VPORT_ZSCALE_11 0xa155
897 #define mmPA_CL_VPORT_ZSCALE_12 0xa15b
898 #define mmPA_CL_VPORT_ZSCALE_13 0xa161
899 #define mmPA_CL_VPORT_ZSCALE_14 0xa167
900 #define mmPA_CL_VPORT_ZSCALE_15 0xa16d
901 #define mmPA_CL_VPORT_ZOFFSET_1 0xa11a
902 #define mmPA_CL_VPORT_ZOFFSET_2 0xa120
903 #define mmPA_CL_VPORT_ZOFFSET_3 0xa126
904 #define mmPA_CL_VPORT_ZOFFSET_4 0xa12c
905 #define mmPA_CL_VPORT_ZOFFSET_5 0xa132
906 #define mmPA_CL_VPORT_ZOFFSET_6 0xa138
907 #define mmPA_CL_VPORT_ZOFFSET_7 0xa13e
908 #define mmPA_CL_VPORT_ZOFFSET_8 0xa144
909 #define mmPA_CL_VPORT_ZOFFSET_9 0xa14a
910 #define mmPA_CL_VPORT_ZOFFSET_10 0xa150
911 #define mmPA_CL_VPORT_ZOFFSET_11 0xa156
912 #define mmPA_CL_VPORT_ZOFFSET_12 0xa15c
913 #define mmPA_CL_VPORT_ZOFFSET_13 0xa162
914 #define mmPA_CL_VPORT_ZOFFSET_14 0xa168
915 #define mmPA_CL_VPORT_ZOFFSET_15 0xa16e
916 #define mmPA_CL_VTE_CNTL 0xa206
917 #define mmPA_CL_VS_OUT_CNTL 0xa207
918 #define mmPA_CL_NANINF_CNTL 0xa208
919 #define mmPA_CL_CLIP_CNTL 0xa204
920 #define mmPA_CL_GB_VERT_CLIP_ADJ 0xa2fa
921 #define mmPA_CL_GB_VERT_DISC_ADJ 0xa2fb
922 #define mmPA_CL_GB_HORZ_CLIP_ADJ 0xa2fc
923 #define mmPA_CL_GB_HORZ_DISC_ADJ 0xa2fd
924 #define mmPA_CL_UCP_0_X 0xa16f
925 #define mmPA_CL_UCP_0_Y 0xa170
926 #define mmPA_CL_UCP_0_Z 0xa171
927 #define mmPA_CL_UCP_0_W 0xa172
928 #define mmPA_CL_UCP_1_X 0xa173
929 #define mmPA_CL_UCP_1_Y 0xa174
930 #define mmPA_CL_UCP_1_Z 0xa175
931 #define mmPA_CL_UCP_1_W 0xa176
932 #define mmPA_CL_UCP_2_X 0xa177
933 #define mmPA_CL_UCP_2_Y 0xa178
934 #define mmPA_CL_UCP_2_Z 0xa179
935 #define mmPA_CL_UCP_2_W 0xa17a
936 #define mmPA_CL_UCP_3_X 0xa17b
937 #define mmPA_CL_UCP_3_Y 0xa17c
938 #define mmPA_CL_UCP_3_Z 0xa17d
939 #define mmPA_CL_UCP_3_W 0xa17e
940 #define mmPA_CL_UCP_4_X 0xa17f
941 #define mmPA_CL_UCP_4_Y 0xa180
942 #define mmPA_CL_UCP_4_Z 0xa181
943 #define mmPA_CL_UCP_4_W 0xa182
944 #define mmPA_CL_UCP_5_X 0xa183
945 #define mmPA_CL_UCP_5_Y 0xa184
946 #define mmPA_CL_UCP_5_Z 0xa185
947 #define mmPA_CL_UCP_5_W 0xa186
948 #define mmPA_CL_POINT_X_RAD 0xa1f5
949 #define mmPA_CL_POINT_Y_RAD 0xa1f6
950 #define mmPA_CL_POINT_SIZE 0xa1f7
951 #define mmPA_CL_POINT_CULL_RAD 0xa1f8
952 #define mmPA_CL_ENHANCE 0x2285
953 #define mmPA_CL_RESET_DEBUG 0x2286
954 #define mmPA_SU_VTX_CNTL 0xa2f9
955 #define mmPA_SU_POINT_SIZE 0xa280
956 #define mmPA_SU_POINT_MINMAX 0xa281
957 #define mmPA_SU_LINE_CNTL 0xa282
958 #define mmPA_SU_LINE_STIPPLE_CNTL 0xa209
959 #define mmPA_SU_LINE_STIPPLE_SCALE 0xa20a
960 #define mmPA_SU_PRIM_FILTER_CNTL 0xa20b
961 #define mmPA_SU_SC_MODE_CNTL 0xa205
962 #define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL 0xa2de
963 #define mmPA_SU_POLY_OFFSET_CLAMP 0xa2df
964 #define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0xa2e0
965 #define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0xa2e1
966 #define mmPA_SU_POLY_OFFSET_BACK_SCALE 0xa2e2
967 #define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0xa2e3
968 #define mmPA_SU_HARDWARE_SCREEN_OFFSET 0xa08d
969 #define mmPA_SU_LINE_STIPPLE_VALUE 0xc280
970 #define mmPA_SU_PERFCOUNTER0_SELECT 0xd900
971 #define mmPA_SU_PERFCOUNTER0_SELECT1 0xd901
972 #define mmPA_SU_PERFCOUNTER1_SELECT 0xd902
973 #define mmPA_SU_PERFCOUNTER1_SELECT1 0xd903
974 #define mmPA_SU_PERFCOUNTER2_SELECT 0xd904
975 #define mmPA_SU_PERFCOUNTER3_SELECT 0xd905
976 #define mmPA_SU_PERFCOUNTER0_LO 0xd100
977 #define mmPA_SU_PERFCOUNTER0_HI 0xd101
978 #define mmPA_SU_PERFCOUNTER1_LO 0xd102
979 #define mmPA_SU_PERFCOUNTER1_HI 0xd103
980 #define mmPA_SU_PERFCOUNTER2_LO 0xd104
981 #define mmPA_SU_PERFCOUNTER2_HI 0xd105
982 #define mmPA_SU_PERFCOUNTER3_LO 0xd106
983 #define mmPA_SU_PERFCOUNTER3_HI 0xd107
984 #define mmPA_SC_AA_CONFIG 0xa2f8
985 #define mmPA_SC_AA_MASK_X0Y0_X1Y0 0xa30e
986 #define mmPA_SC_AA_MASK_X0Y1_X1Y1 0xa30f
987 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0xa2fe
988 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0xa2ff
989 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0xa300
990 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0xa301
991 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0xa302
992 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0xa303
993 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0xa304
994 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0xa305
995 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0xa306
996 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0xa307
997 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0xa308
998 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0xa309
999 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0xa30a
1000 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0xa30b
1001 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0xa30c
1002 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0xa30d
1003 #define mmPA_SC_CENTROID_PRIORITY_0 0xa2f5
1004 #define mmPA_SC_CENTROID_PRIORITY_1 0xa2f6
1005 #define mmPA_SC_CLIPRECT_0_TL 0xa084
1006 #define mmPA_SC_CLIPRECT_0_BR 0xa085
1007 #define mmPA_SC_CLIPRECT_1_TL 0xa086
1008 #define mmPA_SC_CLIPRECT_1_BR 0xa087
1009 #define mmPA_SC_CLIPRECT_2_TL 0xa088
1010 #define mmPA_SC_CLIPRECT_2_BR 0xa089
1011 #define mmPA_SC_CLIPRECT_3_TL 0xa08a
1012 #define mmPA_SC_CLIPRECT_3_BR 0xa08b
1013 #define mmPA_SC_CLIPRECT_RULE 0xa083
1014 #define mmPA_SC_EDGERULE 0xa08c
1015 #define mmPA_SC_LINE_CNTL 0xa2f7
1016 #define mmPA_SC_LINE_STIPPLE 0xa283
1017 #define mmPA_SC_MODE_CNTL_0 0xa292
1018 #define mmPA_SC_MODE_CNTL_1 0xa293
1019 #define mmPA_SC_RASTER_CONFIG 0xa0d4
1020 #define mmPA_SC_RASTER_CONFIG_1 0xa0d5
1021 #define mmPA_SC_SCREEN_EXTENT_CONTROL 0xa0d6
1022 #define mmPA_SC_GENERIC_SCISSOR_TL 0xa090
1023 #define mmPA_SC_GENERIC_SCISSOR_BR 0xa091
1024 #define mmPA_SC_SCREEN_SCISSOR_TL 0xa00c
1025 #define mmPA_SC_SCREEN_SCISSOR_BR 0xa00d
1026 #define mmPA_SC_WINDOW_OFFSET 0xa080
1027 #define mmPA_SC_WINDOW_SCISSOR_TL 0xa081
1028 #define mmPA_SC_WINDOW_SCISSOR_BR 0xa082
1029 #define mmPA_SC_VPORT_SCISSOR_0_TL 0xa094
1030 #define mmPA_SC_VPORT_SCISSOR_1_TL 0xa096
1031 #define mmPA_SC_VPORT_SCISSOR_2_TL 0xa098
1032 #define mmPA_SC_VPORT_SCISSOR_3_TL 0xa09a
1033 #define mmPA_SC_VPORT_SCISSOR_4_TL 0xa09c
1034 #define mmPA_SC_VPORT_SCISSOR_5_TL 0xa09e
1035 #define mmPA_SC_VPORT_SCISSOR_6_TL 0xa0a0
1036 #define mmPA_SC_VPORT_SCISSOR_7_TL 0xa0a2
1037 #define mmPA_SC_VPORT_SCISSOR_8_TL 0xa0a4
1038 #define mmPA_SC_VPORT_SCISSOR_9_TL 0xa0a6
1039 #define mmPA_SC_VPORT_SCISSOR_10_TL 0xa0a8
1040 #define mmPA_SC_VPORT_SCISSOR_11_TL 0xa0aa
1041 #define mmPA_SC_VPORT_SCISSOR_12_TL 0xa0ac
1042 #define mmPA_SC_VPORT_SCISSOR_13_TL 0xa0ae
1043 #define mmPA_SC_VPORT_SCISSOR_14_TL 0xa0b0
1044 #define mmPA_SC_VPORT_SCISSOR_15_TL 0xa0b2
1045 #define mmPA_SC_VPORT_SCISSOR_0_BR 0xa095
1046 #define mmPA_SC_VPORT_SCISSOR_1_BR 0xa097
1047 #define mmPA_SC_VPORT_SCISSOR_2_BR 0xa099
1048 #define mmPA_SC_VPORT_SCISSOR_3_BR 0xa09b
1049 #define mmPA_SC_VPORT_SCISSOR_4_BR 0xa09d
1050 #define mmPA_SC_VPORT_SCISSOR_5_BR 0xa09f
1051 #define mmPA_SC_VPORT_SCISSOR_6_BR 0xa0a1
1052 #define mmPA_SC_VPORT_SCISSOR_7_BR 0xa0a3
1053 #define mmPA_SC_VPORT_SCISSOR_8_BR 0xa0a5
1054 #define mmPA_SC_VPORT_SCISSOR_9_BR 0xa0a7
1055 #define mmPA_SC_VPORT_SCISSOR_10_BR 0xa0a9
1056 #define mmPA_SC_VPORT_SCISSOR_11_BR 0xa0ab
1057 #define mmPA_SC_VPORT_SCISSOR_12_BR 0xa0ad
1058 #define mmPA_SC_VPORT_SCISSOR_13_BR 0xa0af
1059 #define mmPA_SC_VPORT_SCISSOR_14_BR 0xa0b1
1060 #define mmPA_SC_VPORT_SCISSOR_15_BR 0xa0b3
1061 #define mmPA_SC_VPORT_ZMIN_0 0xa0b4
1062 #define mmPA_SC_VPORT_ZMIN_1 0xa0b6
1063 #define mmPA_SC_VPORT_ZMIN_2 0xa0b8
1064 #define mmPA_SC_VPORT_ZMIN_3 0xa0ba
1065 #define mmPA_SC_VPORT_ZMIN_4 0xa0bc
1066 #define mmPA_SC_VPORT_ZMIN_5 0xa0be
1067 #define mmPA_SC_VPORT_ZMIN_6 0xa0c0
1068 #define mmPA_SC_VPORT_ZMIN_7 0xa0c2
1069 #define mmPA_SC_VPORT_ZMIN_8 0xa0c4
1070 #define mmPA_SC_VPORT_ZMIN_9 0xa0c6
1071 #define mmPA_SC_VPORT_ZMIN_10 0xa0c8
1072 #define mmPA_SC_VPORT_ZMIN_11 0xa0ca
1073 #define mmPA_SC_VPORT_ZMIN_12 0xa0cc
1074 #define mmPA_SC_VPORT_ZMIN_13 0xa0ce
1075 #define mmPA_SC_VPORT_ZMIN_14 0xa0d0
1076 #define mmPA_SC_VPORT_ZMIN_15 0xa0d2
1077 #define mmPA_SC_VPORT_ZMAX_0 0xa0b5
1078 #define mmPA_SC_VPORT_ZMAX_1 0xa0b7
1079 #define mmPA_SC_VPORT_ZMAX_2 0xa0b9
1080 #define mmPA_SC_VPORT_ZMAX_3 0xa0bb
1081 #define mmPA_SC_VPORT_ZMAX_4 0xa0bd
1082 #define mmPA_SC_VPORT_ZMAX_5 0xa0bf
1083 #define mmPA_SC_VPORT_ZMAX_6 0xa0c1
1084 #define mmPA_SC_VPORT_ZMAX_7 0xa0c3
1085 #define mmPA_SC_VPORT_ZMAX_8 0xa0c5
1086 #define mmPA_SC_VPORT_ZMAX_9 0xa0c7
1087 #define mmPA_SC_VPORT_ZMAX_10 0xa0c9
1088 #define mmPA_SC_VPORT_ZMAX_11 0xa0cb
1089 #define mmPA_SC_VPORT_ZMAX_12 0xa0cd
1090 #define mmPA_SC_VPORT_ZMAX_13 0xa0cf
1091 #define mmPA_SC_VPORT_ZMAX_14 0xa0d1
1092 #define mmPA_SC_VPORT_ZMAX_15 0xa0d3
1093 #define mmPA_SC_ENHANCE 0x22fc
1094 #define mmPA_SC_FIFO_SIZE 0x22f3
1095 #define mmPA_SC_IF_FIFO_SIZE 0x22f5
1096 #define mmPA_SC_FORCE_EOV_MAX_CNTS 0x22c9
1097 #define mmPA_SC_LINE_STIPPLE_STATE 0xc281
1098 #define mmPA_SC_SCREEN_EXTENT_MIN_0 0xc284
1099 #define mmPA_SC_SCREEN_EXTENT_MAX_0 0xc285
1100 #define mmPA_SC_SCREEN_EXTENT_MIN_1 0xc286
1101 #define mmPA_SC_SCREEN_EXTENT_MAX_1 0xc28b
1102 #define mmPA_SC_PERFCOUNTER0_SELECT 0xd940
1103 #define mmPA_SC_PERFCOUNTER0_SELECT1 0xd941
1104 #define mmPA_SC_PERFCOUNTER1_SELECT 0xd942
1105 #define mmPA_SC_PERFCOUNTER2_SELECT 0xd943
1106 #define mmPA_SC_PERFCOUNTER3_SELECT 0xd944
1107 #define mmPA_SC_PERFCOUNTER4_SELECT 0xd945
1108 #define mmPA_SC_PERFCOUNTER5_SELECT 0xd946
1109 #define mmPA_SC_PERFCOUNTER6_SELECT 0xd947
1110 #define mmPA_SC_PERFCOUNTER7_SELECT 0xd948
1111 #define mmPA_SC_PERFCOUNTER0_LO 0xd140
1112 #define mmPA_SC_PERFCOUNTER0_HI 0xd141
1113 #define mmPA_SC_PERFCOUNTER1_LO 0xd142
1114 #define mmPA_SC_PERFCOUNTER1_HI 0xd143
1115 #define mmPA_SC_PERFCOUNTER2_LO 0xd144
1116 #define mmPA_SC_PERFCOUNTER2_HI 0xd145
1117 #define mmPA_SC_PERFCOUNTER3_LO 0xd146
1118 #define mmPA_SC_PERFCOUNTER3_HI 0xd147
1119 #define mmPA_SC_PERFCOUNTER4_LO 0xd148
1120 #define mmPA_SC_PERFCOUNTER4_HI 0xd149
1121 #define mmPA_SC_PERFCOUNTER5_LO 0xd14a
1122 #define mmPA_SC_PERFCOUNTER5_HI 0xd14b
1123 #define mmPA_SC_PERFCOUNTER6_LO 0xd14c
1124 #define mmPA_SC_PERFCOUNTER6_HI 0xd14d
1125 #define mmPA_SC_PERFCOUNTER7_LO 0xd14e
1126 #define mmPA_SC_PERFCOUNTER7_HI 0xd14f
1127 #define mmPA_SC_P3D_TRAP_SCREEN_HV_EN 0xc2a0
1128 #define mmPA_SC_P3D_TRAP_SCREEN_H 0xc2a1
1129 #define mmPA_SC_P3D_TRAP_SCREEN_V 0xc2a2
1130 #define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0xc2a3
1131 #define mmPA_SC_P3D_TRAP_SCREEN_COUNT 0xc2a4
1132 #define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN 0xc2a8
1133 #define mmPA_SC_HP3D_TRAP_SCREEN_H 0xc2a9
1134 #define mmPA_SC_HP3D_TRAP_SCREEN_V 0xc2aa
1135 #define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0xc2ab
1136 #define mmPA_SC_HP3D_TRAP_SCREEN_COUNT 0xc2ac
1137 #define mmPA_SC_TRAP_SCREEN_HV_EN 0xc2b0
1138 #define mmPA_SC_TRAP_SCREEN_H 0xc2b1
1139 #define mmPA_SC_TRAP_SCREEN_V 0xc2b2
1140 #define mmPA_SC_TRAP_SCREEN_OCCURRENCE 0xc2b3
1141 #define mmPA_SC_TRAP_SCREEN_COUNT 0xc2b4
1142 #define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0x22c0
1143 #define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0x22c1
1144 #define mmPA_SC_TRAP_SCREEN_HV_LOCK 0x22c2
1145 #define mmPA_CL_CNTL_STATUS 0x2284
1146 #define mmPA_SU_CNTL_STATUS 0x2294
1147 #define mmPA_SC_FIFO_DEPTH_CNTL 0x2295
1148 #define mmCGTT_PA_CLK_CTRL 0xf088
1149 #define mmCGTT_SC_CLK_CTRL 0xf089
1150 #define mmPA_SU_DEBUG_CNTL 0x2280
1151 #define mmPA_SU_DEBUG_DATA 0x2281
1152 #define mmPA_SC_DEBUG_CNTL 0x22f6
1153 #define mmPA_SC_DEBUG_DATA 0x22f7
1154 #define ixCLIPPER_DEBUG_REG00 0x0
1155 #define ixCLIPPER_DEBUG_REG01 0x1
1156 #define ixCLIPPER_DEBUG_REG02 0x2
1157 #define ixCLIPPER_DEBUG_REG03 0x3
1158 #define ixCLIPPER_DEBUG_REG04 0x4
1159 #define ixCLIPPER_DEBUG_REG05 0x5
1160 #define ixCLIPPER_DEBUG_REG06 0x6
1161 #define ixCLIPPER_DEBUG_REG07 0x7
1162 #define ixCLIPPER_DEBUG_REG08 0x8
1163 #define ixCLIPPER_DEBUG_REG09 0x9
1164 #define ixCLIPPER_DEBUG_REG10 0xa
1165 #define ixCLIPPER_DEBUG_REG11 0xb
1166 #define ixCLIPPER_DEBUG_REG12 0xc
1167 #define ixCLIPPER_DEBUG_REG13 0xd
1168 #define ixCLIPPER_DEBUG_REG14 0xe
1169 #define ixCLIPPER_DEBUG_REG15 0xf
1170 #define ixCLIPPER_DEBUG_REG16 0x10
1171 #define ixCLIPPER_DEBUG_REG17 0x11
1172 #define ixCLIPPER_DEBUG_REG18 0x12
1173 #define ixCLIPPER_DEBUG_REG19 0x13
1174 #define ixSXIFCCG_DEBUG_REG0 0x14
1175 #define ixSXIFCCG_DEBUG_REG1 0x15
1176 #define ixSXIFCCG_DEBUG_REG2 0x16
1177 #define ixSXIFCCG_DEBUG_REG3 0x17
1178 #define ixSETUP_DEBUG_REG0 0x18
1179 #define ixSETUP_DEBUG_REG1 0x19
1180 #define ixSETUP_DEBUG_REG2 0x1a
1181 #define ixSETUP_DEBUG_REG3 0x1b
1182 #define ixSETUP_DEBUG_REG4 0x1c
1183 #define ixSETUP_DEBUG_REG5 0x1d
1184 #define ixPA_SC_DEBUG_REG0 0x0
1185 #define ixPA_SC_DEBUG_REG1 0x1
1186 #define mmCOMPUTE_DISPATCH_INITIATOR 0x2e00
1187 #define mmCOMPUTE_DIM_X 0x2e01
1188 #define mmCOMPUTE_DIM_Y 0x2e02
1189 #define mmCOMPUTE_DIM_Z 0x2e03
1190 #define mmCOMPUTE_START_X 0x2e04
1191 #define mmCOMPUTE_START_Y 0x2e05
1192 #define mmCOMPUTE_START_Z 0x2e06
1193 #define mmCOMPUTE_NUM_THREAD_X 0x2e07
1194 #define mmCOMPUTE_NUM_THREAD_Y 0x2e08
1195 #define mmCOMPUTE_NUM_THREAD_Z 0x2e09
1196 #define mmCOMPUTE_PIPELINESTAT_ENABLE 0x2e0a
1197 #define mmCOMPUTE_PERFCOUNT_ENABLE 0x2e0b
1198 #define mmCOMPUTE_PGM_LO 0x2e0c
1199 #define mmCOMPUTE_PGM_HI 0x2e0d
1200 #define mmCOMPUTE_TBA_LO 0x2e0e
1201 #define mmCOMPUTE_TBA_HI 0x2e0f
1202 #define mmCOMPUTE_TMA_LO 0x2e10
1203 #define mmCOMPUTE_TMA_HI 0x2e11
1204 #define mmCOMPUTE_PGM_RSRC1 0x2e12
1205 #define mmCOMPUTE_PGM_RSRC2 0x2e13
1206 #define mmCOMPUTE_VMID 0x2e14
1207 #define mmCOMPUTE_RESOURCE_LIMITS 0x2e15
1208 #define mmCOMPUTE_STATIC_THREAD_MGMT_SE0 0x2e16
1209 #define mmCOMPUTE_STATIC_THREAD_MGMT_SE1 0x2e17
1210 #define mmCOMPUTE_TMPRING_SIZE 0x2e18
1211 #define mmCOMPUTE_STATIC_THREAD_MGMT_SE2 0x2e19
1212 #define mmCOMPUTE_STATIC_THREAD_MGMT_SE3 0x2e1a
1213 #define mmCOMPUTE_RESTART_X 0x2e1b
1214 #define mmCOMPUTE_RESTART_Y 0x2e1c
1215 #define mmCOMPUTE_RESTART_Z 0x2e1d
1216 #define mmCOMPUTE_THREAD_TRACE_ENABLE 0x2e1e
1217 #define mmCOMPUTE_MISC_RESERVED 0x2e1f
1218 #define mmCOMPUTE_USER_DATA_0 0x2e40
1219 #define mmCOMPUTE_USER_DATA_1 0x2e41
1220 #define mmCOMPUTE_USER_DATA_2 0x2e42
1221 #define mmCOMPUTE_USER_DATA_3 0x2e43
1222 #define mmCOMPUTE_USER_DATA_4 0x2e44
1223 #define mmCOMPUTE_USER_DATA_5 0x2e45
1224 #define mmCOMPUTE_USER_DATA_6 0x2e46
1225 #define mmCOMPUTE_USER_DATA_7 0x2e47
1226 #define mmCOMPUTE_USER_DATA_8 0x2e48
1227 #define mmCOMPUTE_USER_DATA_9 0x2e49
1228 #define mmCOMPUTE_USER_DATA_10 0x2e4a
1229 #define mmCOMPUTE_USER_DATA_11 0x2e4b
1230 #define mmCOMPUTE_USER_DATA_12 0x2e4c
1231 #define mmCOMPUTE_USER_DATA_13 0x2e4d
1232 #define mmCOMPUTE_USER_DATA_14 0x2e4e
1233 #define mmCOMPUTE_USER_DATA_15 0x2e4f
1234 #define mmCSPRIV_CONNECT 0x0
1235 #define mmCSPRIV_THREAD_TRACE_TG0 0x1e
1236 #define mmCSPRIV_THREAD_TRACE_TG1 0x1e
1237 #define mmCSPRIV_THREAD_TRACE_TG2 0x1e
1238 #define mmCSPRIV_THREAD_TRACE_TG3 0x1e
1239 #define mmCSPRIV_THREAD_TRACE_EVENT 0x1f
1240 #define mmRLC_CNTL 0x30c0
1241 #define mmRLC_DEBUG_SELECT 0x30c1
1242 #define mmRLC_DEBUG 0x30c2
1243 #define mmRLC_MC_CNTL 0x30c3
1244 #define mmRLC_STAT 0x30c4
1245 #define mmRLC_SAFE_MODE 0x313a
1246 #define mmRLC_SOFT_RESET_GPU 0x30c5
1247 #define mmRLC_MEM_SLP_CNTL 0x30c6
1248 #define mmRLC_PERFMON_CNTL 0xdcc0
1249 #define mmRLC_PERFCOUNTER0_SELECT 0xdcc1
1250 #define mmRLC_PERFCOUNTER1_SELECT 0xdcc2
1251 #define mmRLC_PERFCOUNTER0_LO 0xd480
1252 #define mmRLC_PERFCOUNTER1_LO 0xd482
1253 #define mmRLC_PERFCOUNTER0_HI 0xd481
1254 #define mmRLC_PERFCOUNTER1_HI 0xd483
1255 #define mmCGTT_RLC_CLK_CTRL 0xf0b8
1256 #define mmRLC_LB_CNTL 0x30d9
1257 #define mmRLC_LB_CNTR_MAX 0x30d2
1258 #define mmRLC_LB_CNTR_INIT 0x30db
1259 #define mmRLC_LOAD_BALANCE_CNTR 0x30dc
1260 #define mmRLC_SAVE_AND_RESTORE_BASE 0x30dd
1261 #define mmRLC_JUMP_TABLE_RESTORE 0x30de
1262 #define mmRLC_DRIVER_CPDMA_STATUS 0x30de
1263 #define mmRLC_PG_DELAY_2 0x30df
1264 #define mmRLC_GPM_DEBUG_SELECT 0x30e0
1265 #define mmRLC_GPM_DEBUG 0x30e1
1266 #define mmRLC_GPM_UCODE_ADDR 0x30e2
1267 #define mmRLC_GPM_UCODE_DATA 0x30e3
1268 #define mmRLC_GPU_CLOCK_COUNT_LSB 0x30e4
1269 #define mmRLC_GPU_CLOCK_COUNT_MSB 0x30e5
1270 #define mmRLC_CAPTURE_GPU_CLOCK_COUNT 0x30e6
1271 #define mmRLC_UCODE_CNTL 0x30e7
1272 #define mmRLC_GPM_STAT 0x3100
1273 #define mmRLC_GPU_CLOCK_32_RES_SEL 0x3101
1274 #define mmRLC_GPU_CLOCK_32 0x3102
1275 #define mmRLC_PG_CNTL 0x3103
1276 #define mmRLC_GPM_THREAD_PRIORITY 0x3104
1277 #define mmRLC_GPM_THREAD_ENABLE 0x3105
1278 #define mmRLC_GPM_VMID_THREAD0 0x3106
1279 #define mmRLC_GPM_VMID_THREAD1 0x3107
1280 #define mmRLC_CGTT_MGCG_OVERRIDE 0x3108
1281 #define mmRLC_CGCG_CGLS_CTRL 0x3109
1282 #define mmRLC_CGCG_RAMP_CTRL 0x310a
1283 #define mmRLC_DYN_PG_STATUS 0x310b
1284 #define mmRLC_DYN_PG_REQUEST 0x310c
1285 #define mmRLC_PG_DELAY 0x310d
1286 #define mmRLC_CU_STATUS 0x310e
1287 #define mmRLC_LB_INIT_CU_MASK 0x310f
1288 #define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK 0x3110
1289 #define mmRLC_LB_PARAMS 0x3111
1290 #define mmRLC_THREAD1_DELAY 0x3112
1291 #define mmRLC_PG_ALWAYS_ON_CU_MASK 0x3113
1292 #define mmRLC_MAX_PG_CU 0x3114
1293 #define mmRLC_AUTO_PG_CTRL 0x3115
1294 #define mmRLC_SMU_GRBM_REG_SAVE_CTRL 0x3116
1295 #define mmRLC_SMU_PG_CTRL 0x3117
1296 #define mmRLC_SMU_PG_WAKE_UP_CTRL 0x3118
1297 #define mmRLC_SERDES_RD_MASTER_INDEX 0x3119
1298 #define mmRLC_SERDES_RD_DATA_0 0x311a
1299 #define mmRLC_SERDES_RD_DATA_1 0x311b
1300 #define mmRLC_SERDES_RD_DATA_2 0x311c
1301 #define mmRLC_SERDES_WR_CU_MASTER_MASK 0x311d
1302 #define mmRLC_SERDES_WR_NONCU_MASTER_MASK 0x311e
1303 #define mmRLC_SERDES_WR_CTRL 0x311f
1304 #define mmRLC_SERDES_WR_DATA 0x3120
1305 #define mmRLC_SERDES_CU_MASTER_BUSY 0x3121
1306 #define mmRLC_SERDES_NONCU_MASTER_BUSY 0x3122
1307 #define mmRLC_GPM_GENERAL_0 0x3123
1308 #define mmRLC_GPM_GENERAL_1 0x3124
1309 #define mmRLC_GPM_GENERAL_2 0x3125
1310 #define mmRLC_GPM_GENERAL_3 0x3126
1311 #define mmRLC_GPM_GENERAL_4 0x3127
1312 #define mmRLC_GPM_GENERAL_5 0x3128
1313 #define mmRLC_GPM_GENERAL_6 0x3129
1314 #define mmRLC_GPM_GENERAL_7 0x312a
1315 #define mmRLC_GPM_CU_PD_TIMEOUT 0x312b
1316 #define mmRLC_GPM_SCRATCH_ADDR 0x312c
1317 #define mmRLC_GPM_SCRATCH_DATA 0x312d
1318 #define mmRLC_STATIC_PG_STATUS 0x312e
1319 #define mmRLC_GPM_PERF_COUNT_0 0x312f
1320 #define mmRLC_GPM_PERF_COUNT_1 0x3130
1321 #define mmRLC_GPR_REG1 0x3139
1322 #define mmRLC_GPR_REG2 0x313a
1323 #define mmRLC_SPM_VMID 0x3131
1324 #define mmRLC_SPM_INT_CNTL 0x3132
1325 #define mmRLC_SPM_INT_STATUS 0x3133
1326 #define mmRLC_SPM_DEBUG_SELECT 0x3134
1327 #define mmRLC_SPM_DEBUG 0x3135
1328 #define mmRLC_GPM_LOG_ADDR 0x3136
1329 #define mmRLC_GPM_LOG_SIZE 0x3137
1330 #define mmRLC_GPM_LOG_CONT 0x3138
1331 #define mmRLC_SPM_PERFMON_CNTL 0xdc80
1332 #define mmRLC_SPM_PERFMON_RING_BASE_LO 0xdc81
1333 #define mmRLC_SPM_PERFMON_RING_BASE_HI 0xdc82
1334 #define mmRLC_SPM_PERFMON_RING_SIZE 0xdc83
1335 #define mmRLC_SPM_PERFMON_SEGMENT_SIZE 0xdc84
1336 #define mmRLC_SPM_SE_MUXSEL_ADDR 0xdc85
1337 #define mmRLC_SPM_SE_MUXSEL_DATA 0xdc86
1338 #define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY 0xdc87
1339 #define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY 0xdc88
1340 #define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY 0xdc89
1341 #define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY 0xdc8a
1342 #define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY 0xdc8b
1343 #define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY 0xdc8c
1344 #define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY 0xdc8d
1345 #define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY 0xdc8e
1346 #define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY 0xdc90
1347 #define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY 0xdc91
1348 #define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY 0xdc92
1349 #define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY 0xdc93
1350 #define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY 0xdc94
1351 #define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY 0xdc95
1352 #define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY 0xdc96
1353 #define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY 0xdc97
1354 #define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY 0xdc98
1355 #define mmRLC_SPM_TCS_PERFMON_SAMPLE_DELAY 0xdc99
1356 #define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY 0xdc9a
1357 #define mmRLC_SPM_GLOBAL_MUXSEL_ADDR 0xdc9b
1358 #define mmRLC_SPM_GLOBAL_MUXSEL_DATA 0xdc9c
1359 #define mmRLC_SPM_RING_RDPTR 0xdc9d
1360 #define mmRLC_SPM_SEGMENT_THRESHOLD 0xdc9e
1361 #define mmSPI_PS_INPUT_CNTL_0 0xa191
1362 #define mmSPI_PS_INPUT_CNTL_1 0xa192
1363 #define mmSPI_PS_INPUT_CNTL_2 0xa193
1364 #define mmSPI_PS_INPUT_CNTL_3 0xa194
1365 #define mmSPI_PS_INPUT_CNTL_4 0xa195
1366 #define mmSPI_PS_INPUT_CNTL_5 0xa196
1367 #define mmSPI_PS_INPUT_CNTL_6 0xa197
1368 #define mmSPI_PS_INPUT_CNTL_7 0xa198
1369 #define mmSPI_PS_INPUT_CNTL_8 0xa199
1370 #define mmSPI_PS_INPUT_CNTL_9 0xa19a
1371 #define mmSPI_PS_INPUT_CNTL_10 0xa19b
1372 #define mmSPI_PS_INPUT_CNTL_11 0xa19c
1373 #define mmSPI_PS_INPUT_CNTL_12 0xa19d
1374 #define mmSPI_PS_INPUT_CNTL_13 0xa19e
1375 #define mmSPI_PS_INPUT_CNTL_14 0xa19f
1376 #define mmSPI_PS_INPUT_CNTL_15 0xa1a0
1377 #define mmSPI_PS_INPUT_CNTL_16 0xa1a1
1378 #define mmSPI_PS_INPUT_CNTL_17 0xa1a2
1379 #define mmSPI_PS_INPUT_CNTL_18 0xa1a3
1380 #define mmSPI_PS_INPUT_CNTL_19 0xa1a4
1381 #define mmSPI_PS_INPUT_CNTL_20 0xa1a5
1382 #define mmSPI_PS_INPUT_CNTL_21 0xa1a6
1383 #define mmSPI_PS_INPUT_CNTL_22 0xa1a7
1384 #define mmSPI_PS_INPUT_CNTL_23 0xa1a8
1385 #define mmSPI_PS_INPUT_CNTL_24 0xa1a9
1386 #define mmSPI_PS_INPUT_CNTL_25 0xa1aa
1387 #define mmSPI_PS_INPUT_CNTL_26 0xa1ab
1388 #define mmSPI_PS_INPUT_CNTL_27 0xa1ac
1389 #define mmSPI_PS_INPUT_CNTL_28 0xa1ad
1390 #define mmSPI_PS_INPUT_CNTL_29 0xa1ae
1391 #define mmSPI_PS_INPUT_CNTL_30 0xa1af
1392 #define mmSPI_PS_INPUT_CNTL_31 0xa1b0
1393 #define mmSPI_VS_OUT_CONFIG 0xa1b1
1394 #define mmSPI_PS_INPUT_ENA 0xa1b3
1395 #define mmSPI_PS_INPUT_ADDR 0xa1b4
1396 #define mmSPI_INTERP_CONTROL_0 0xa1b5
1397 #define mmSPI_PS_IN_CONTROL 0xa1b6
1398 #define mmSPI_BARYC_CNTL 0xa1b8
1399 #define mmSPI_TMPRING_SIZE 0xa1ba
1400 #define mmSPI_SHADER_POS_FORMAT 0xa1c3
1401 #define mmSPI_SHADER_Z_FORMAT 0xa1c4
1402 #define mmSPI_SHADER_COL_FORMAT 0xa1c5
1403 #define mmSPI_ARB_PRIORITY 0x31c0
1404 #define mmSPI_ARB_CYCLES_0 0x31c1
1405 #define mmSPI_ARB_CYCLES_1 0x31c2
1406 #define mmSPI_CDBG_SYS_GFX 0x31c3
1407 #define mmSPI_CDBG_SYS_HP3D 0x31c4
1408 #define mmSPI_CDBG_SYS_CS0 0x31c5
1409 #define mmSPI_CDBG_SYS_CS1 0x31c6
1410 #define mmSPI_WCL_PIPE_PERCENT_GFX 0x31c7
1411 #define mmSPI_WCL_PIPE_PERCENT_HP3D 0x31c8
1412 #define mmSPI_WCL_PIPE_PERCENT_CS0 0x31c9
1413 #define mmSPI_WCL_PIPE_PERCENT_CS1 0x31ca
1414 #define mmSPI_WCL_PIPE_PERCENT_CS2 0x31cb
1415 #define mmSPI_WCL_PIPE_PERCENT_CS3 0x31cc
1416 #define mmSPI_WCL_PIPE_PERCENT_CS4 0x31cd
1417 #define mmSPI_WCL_PIPE_PERCENT_CS5 0x31ce
1418 #define mmSPI_WCL_PIPE_PERCENT_CS6 0x31cf
1419 #define mmSPI_WCL_PIPE_PERCENT_CS7 0x31d0
1420 #define mmSPI_GDBG_WAVE_CNTL 0x31d1
1421 #define mmSPI_GDBG_TRAP_CONFIG 0x31d2
1422 #define mmSPI_GDBG_TRAP_MASK 0x31d3
1423 #define mmSPI_GDBG_TBA_LO 0x31d4
1424 #define mmSPI_GDBG_TBA_HI 0x31d5
1425 #define mmSPI_GDBG_TMA_LO 0x31d6
1426 #define mmSPI_GDBG_TMA_HI 0x31d7
1427 #define mmSPI_GDBG_TRAP_DATA0 0x31d8
1428 #define mmSPI_GDBG_TRAP_DATA1 0x31d9
1429 #define mmSPI_RESET_DEBUG 0x31da
1430 #define mmSPI_COMPUTE_QUEUE_RESET 0x31db
1431 #define mmSPI_RESOURCE_RESERVE_CU_0 0x31dc
1432 #define mmSPI_RESOURCE_RESERVE_CU_1 0x31dd
1433 #define mmSPI_RESOURCE_RESERVE_CU_2 0x31de
1434 #define mmSPI_RESOURCE_RESERVE_CU_3 0x31df
1435 #define mmSPI_RESOURCE_RESERVE_CU_4 0x31e0
1436 #define mmSPI_RESOURCE_RESERVE_CU_5 0x31e1
1437 #define mmSPI_RESOURCE_RESERVE_CU_6 0x31e2
1438 #define mmSPI_RESOURCE_RESERVE_CU_7 0x31e3
1439 #define mmSPI_RESOURCE_RESERVE_CU_8 0x31e4
1440 #define mmSPI_RESOURCE_RESERVE_CU_9 0x31e5
1441 #define mmSPI_RESOURCE_RESERVE_EN_CU_0 0x31e6
1442 #define mmSPI_RESOURCE_RESERVE_EN_CU_1 0x31e7
1443 #define mmSPI_RESOURCE_RESERVE_EN_CU_2 0x31e8
1444 #define mmSPI_RESOURCE_RESERVE_EN_CU_3 0x31e9
1445 #define mmSPI_RESOURCE_RESERVE_EN_CU_4 0x31ea
1446 #define mmSPI_RESOURCE_RESERVE_EN_CU_5 0x31eb
1447 #define mmSPI_RESOURCE_RESERVE_EN_CU_6 0x31ec
1448 #define mmSPI_RESOURCE_RESERVE_EN_CU_7 0x31ed
1449 #define mmSPI_RESOURCE_RESERVE_EN_CU_8 0x31ee
1450 #define mmSPI_RESOURCE_RESERVE_EN_CU_9 0x31ef
1451 #define mmSPI_PS_MAX_WAVE_ID 0x243a
1452 #define mmSPI_CONFIG_CNTL 0x2440
1453 #define mmSPI_DEBUG_CNTL 0x2441
1454 #define mmSPI_DEBUG_READ 0x2442
1455 #define mmSPI_PERFCOUNTER0_SELECT 0xd980
1456 #define mmSPI_PERFCOUNTER1_SELECT 0xd981
1457 #define mmSPI_PERFCOUNTER2_SELECT 0xd982
1458 #define mmSPI_PERFCOUNTER3_SELECT 0xd983
1459 #define mmSPI_PERFCOUNTER0_SELECT1 0xd984
1460 #define mmSPI_PERFCOUNTER1_SELECT1 0xd985
1461 #define mmSPI_PERFCOUNTER2_SELECT1 0xd986
1462 #define mmSPI_PERFCOUNTER3_SELECT1 0xd987
1463 #define mmSPI_PERFCOUNTER4_SELECT 0xd988
1464 #define mmSPI_PERFCOUNTER5_SELECT 0xd989
1465 #define mmSPI_PERFCOUNTER_BINS 0xd98a
1466 #define mmSPI_PERFCOUNTER0_HI 0xd180
1467 #define mmSPI_PERFCOUNTER0_LO 0xd181
1468 #define mmSPI_PERFCOUNTER1_HI 0xd182
1469 #define mmSPI_PERFCOUNTER1_LO 0xd183
1470 #define mmSPI_PERFCOUNTER2_HI 0xd184
1471 #define mmSPI_PERFCOUNTER2_LO 0xd185
1472 #define mmSPI_PERFCOUNTER3_HI 0xd186
1473 #define mmSPI_PERFCOUNTER3_LO 0xd187
1474 #define mmSPI_PERFCOUNTER4_HI 0xd188
1475 #define mmSPI_PERFCOUNTER4_LO 0xd189
1476 #define mmSPI_PERFCOUNTER5_HI 0xd18a
1477 #define mmSPI_PERFCOUNTER5_LO 0xd18b
1478 #define mmSPI_CONFIG_CNTL_1 0x244f
1479 #define mmSPI_DEBUG_BUSY 0x2450
1480 #define mmCGTS_SM_CTRL_REG 0xf000
1481 #define mmCGTS_RD_CTRL_REG 0xf001
1482 #define mmCGTS_RD_REG 0xf002
1483 #define mmCGTS_TCC_DISABLE 0xf003
1484 #define mmCGTS_USER_TCC_DISABLE 0xf004
1485 #define mmCGTS_CU0_SP0_CTRL_REG 0xf008
1486 #define mmCGTS_CU0_LDS_SQ_CTRL_REG 0xf009
1487 #define mmCGTS_CU0_TA_SQC_CTRL_REG 0xf00a
1488 #define mmCGTS_CU0_SP1_CTRL_REG 0xf00b
1489 #define mmCGTS_CU0_TD_TCP_CTRL_REG 0xf00c
1490 #define mmCGTS_CU1_SP0_CTRL_REG 0xf00d
1491 #define mmCGTS_CU1_LDS_SQ_CTRL_REG 0xf00e
1492 #define mmCGTS_CU1_TA_CTRL_REG 0xf00f
1493 #define mmCGTS_CU1_SP1_CTRL_REG 0xf010
1494 #define mmCGTS_CU1_TD_TCP_CTRL_REG 0xf011
1495 #define mmCGTS_CU2_SP0_CTRL_REG 0xf012
1496 #define mmCGTS_CU2_LDS_SQ_CTRL_REG 0xf013
1497 #define mmCGTS_CU2_TA_CTRL_REG 0xf014
1498 #define mmCGTS_CU2_SP1_CTRL_REG 0xf015
1499 #define mmCGTS_CU2_TD_TCP_CTRL_REG 0xf016
1500 #define mmCGTS_CU3_SP0_CTRL_REG 0xf017
1501 #define mmCGTS_CU3_LDS_SQ_CTRL_REG 0xf018
1502 #define mmCGTS_CU3_TA_CTRL_REG 0xf019
1503 #define mmCGTS_CU3_SP1_CTRL_REG 0xf01a
1504 #define mmCGTS_CU3_TD_TCP_CTRL_REG 0xf01b
1505 #define mmCGTS_CU4_SP0_CTRL_REG 0xf01c
1506 #define mmCGTS_CU4_LDS_SQ_CTRL_REG 0xf01d
1507 #define mmCGTS_CU4_TA_SQC_CTRL_REG 0xf01e
1508 #define mmCGTS_CU4_SP1_CTRL_REG 0xf01f
1509 #define mmCGTS_CU4_TD_TCP_CTRL_REG 0xf020
1510 #define mmCGTS_CU5_SP0_CTRL_REG 0xf021
1511 #define mmCGTS_CU5_LDS_SQ_CTRL_REG 0xf022
1512 #define mmCGTS_CU5_TA_CTRL_REG 0xf023
1513 #define mmCGTS_CU5_SP1_CTRL_REG 0xf024
1514 #define mmCGTS_CU5_TD_TCP_CTRL_REG 0xf025
1515 #define mmCGTS_CU6_SP0_CTRL_REG 0xf026
1516 #define mmCGTS_CU6_LDS_SQ_CTRL_REG 0xf027
1517 #define mmCGTS_CU6_TA_CTRL_REG 0xf028
1518 #define mmCGTS_CU6_SP1_CTRL_REG 0xf029
1519 #define mmCGTS_CU6_TD_TCP_CTRL_REG 0xf02a
1520 #define mmCGTS_CU7_SP0_CTRL_REG 0xf02b
1521 #define mmCGTS_CU7_LDS_SQ_CTRL_REG 0xf02c
1522 #define mmCGTS_CU7_TA_CTRL_REG 0xf02d
1523 #define mmCGTS_CU7_SP1_CTRL_REG 0xf02e
1524 #define mmCGTS_CU7_TD_TCP_CTRL_REG 0xf02f
1525 #define mmCGTS_CU8_SP0_CTRL_REG 0xf030
1526 #define mmCGTS_CU8_LDS_SQ_CTRL_REG 0xf031
1527 #define mmCGTS_CU8_TA_SQC_CTRL_REG 0xf032
1528 #define mmCGTS_CU8_SP1_CTRL_REG 0xf033
1529 #define mmCGTS_CU8_TD_TCP_CTRL_REG 0xf034
1530 #define mmCGTS_CU9_SP0_CTRL_REG 0xf035
1531 #define mmCGTS_CU9_LDS_SQ_CTRL_REG 0xf036
1532 #define mmCGTS_CU9_TA_CTRL_REG 0xf037
1533 #define mmCGTS_CU9_SP1_CTRL_REG 0xf038
1534 #define mmCGTS_CU9_TD_TCP_CTRL_REG 0xf039
1535 #define mmCGTS_CU10_SP0_CTRL_REG 0xf03a
1536 #define mmCGTS_CU10_LDS_SQ_CTRL_REG 0xf03b
1537 #define mmCGTS_CU10_TA_CTRL_REG 0xf03c
1538 #define mmCGTS_CU10_SP1_CTRL_REG 0xf03d
1539 #define mmCGTS_CU10_TD_TCP_CTRL_REG 0xf03e
1540 #define mmCGTS_CU11_SP0_CTRL_REG 0xf03f
1541 #define mmCGTS_CU11_LDS_SQ_CTRL_REG 0xf040
1542 #define mmCGTS_CU11_TA_CTRL_REG 0xf041
1543 #define mmCGTS_CU11_SP1_CTRL_REG 0xf042
1544 #define mmCGTS_CU11_TD_TCP_CTRL_REG 0xf043
1545 #define mmCGTS_CU12_SP0_CTRL_REG 0xf044
1546 #define mmCGTS_CU12_LDS_SQ_CTRL_REG 0xf045
1547 #define mmCGTS_CU12_TA_SQC_CTRL_REG 0xf046
1548 #define mmCGTS_CU12_SP1_CTRL_REG 0xf047
1549 #define mmCGTS_CU12_TD_TCP_CTRL_REG 0xf048
1550 #define mmCGTS_CU13_SP0_CTRL_REG 0xf049
1551 #define mmCGTS_CU13_LDS_SQ_CTRL_REG 0xf04a
1552 #define mmCGTS_CU13_TA_CTRL_REG 0xf04b
1553 #define mmCGTS_CU13_SP1_CTRL_REG 0xf04c
1554 #define mmCGTS_CU13_TD_TCP_CTRL_REG 0xf04d
1555 #define mmCGTS_CU14_SP0_CTRL_REG 0xf04e
1556 #define mmCGTS_CU14_LDS_SQ_CTRL_REG 0xf04f
1557 #define mmCGTS_CU14_TA_CTRL_REG 0xf050
1558 #define mmCGTS_CU14_SP1_CTRL_REG 0xf051
1559 #define mmCGTS_CU14_TD_TCP_CTRL_REG 0xf052
1560 #define mmCGTS_CU15_SP0_CTRL_REG 0xf053
1561 #define mmCGTS_CU15_LDS_SQ_CTRL_REG 0xf054
1562 #define mmCGTS_CU15_TA_CTRL_REG 0xf055
1563 #define mmCGTS_CU15_SP1_CTRL_REG 0xf056
1564 #define mmCGTS_CU15_TD_TCP_CTRL_REG 0xf057
1565 #define mmCGTT_SPI_CLK_CTRL 0xf080
1566 #define mmCGTT_PC_CLK_CTRL 0xf081
1567 #define mmCGTT_BCI_CLK_CTRL 0xf082
1568 #define mmSPI_WF_LIFETIME_CNTL 0x24aa
1569 #define mmSPI_WF_LIFETIME_LIMIT_0 0x24ab
1570 #define mmSPI_WF_LIFETIME_LIMIT_1 0x24ac
1571 #define mmSPI_WF_LIFETIME_LIMIT_2 0x24ad
1572 #define mmSPI_WF_LIFETIME_LIMIT_3 0x24ae
1573 #define mmSPI_WF_LIFETIME_LIMIT_4 0x24af
1574 #define mmSPI_WF_LIFETIME_LIMIT_5 0x24b0
1575 #define mmSPI_WF_LIFETIME_LIMIT_6 0x24b1
1576 #define mmSPI_WF_LIFETIME_LIMIT_7 0x24b2
1577 #define mmSPI_WF_LIFETIME_LIMIT_8 0x24b3
1578 #define mmSPI_WF_LIFETIME_LIMIT_9 0x24b4
1579 #define mmSPI_WF_LIFETIME_STATUS_0 0x24b5
1580 #define mmSPI_WF_LIFETIME_STATUS_1 0x24b6
1581 #define mmSPI_WF_LIFETIME_STATUS_2 0x24b7
1582 #define mmSPI_WF_LIFETIME_STATUS_3 0x24b8
1583 #define mmSPI_WF_LIFETIME_STATUS_4 0x24b9
1584 #define mmSPI_WF_LIFETIME_STATUS_5 0x24ba
1585 #define mmSPI_WF_LIFETIME_STATUS_6 0x24bb
1586 #define mmSPI_WF_LIFETIME_STATUS_7 0x24bc
1587 #define mmSPI_WF_LIFETIME_STATUS_8 0x24bd
1588 #define mmSPI_WF_LIFETIME_STATUS_9 0x24be
1589 #define mmSPI_WF_LIFETIME_STATUS_10 0x24bf
1590 #define mmSPI_WF_LIFETIME_STATUS_11 0x24c0
1591 #define mmSPI_WF_LIFETIME_STATUS_12 0x24c1
1592 #define mmSPI_WF_LIFETIME_STATUS_13 0x24c2
1593 #define mmSPI_WF_LIFETIME_STATUS_14 0x24c3
1594 #define mmSPI_WF_LIFETIME_STATUS_15 0x24c4
1595 #define mmSPI_WF_LIFETIME_STATUS_16 0x24c5
1596 #define mmSPI_WF_LIFETIME_STATUS_17 0x24c6
1597 #define mmSPI_WF_LIFETIME_STATUS_18 0x24c7
1598 #define mmSPI_WF_LIFETIME_STATUS_19 0x24c8
1599 #define mmSPI_WF_LIFETIME_STATUS_20 0x24c9
1600 #define mmSPI_WF_LIFETIME_DEBUG 0x24ca
1601 #define mmSPI_SLAVE_DEBUG_BUSY 0x24d3
1602 #define mmSPI_LB_CTR_CTRL 0x24d4
1603 #define mmSPI_LB_CU_MASK 0x24d5
1604 #define mmSPI_LB_DATA_REG 0x24d6
1605 #define mmSPI_PG_ENABLE_STATIC_CU_MASK 0x24d7
1606 #define mmSPI_GDS_CREDITS 0x24d8
1607 #define mmSPI_SX_EXPORT_BUFFER_SIZES 0x24d9
1608 #define mmSPI_SX_SCOREBOARD_BUFFER_SIZES 0x24da
1609 #define mmSPI_CSQ_WF_ACTIVE_STATUS 0x24db
1610 #define mmSPI_CSQ_WF_ACTIVE_COUNT_0 0x24dc
1611 #define mmSPI_CSQ_WF_ACTIVE_COUNT_1 0x24dd
1612 #define mmSPI_CSQ_WF_ACTIVE_COUNT_2 0x24de
1613 #define mmSPI_CSQ_WF_ACTIVE_COUNT_3 0x24df
1614 #define mmSPI_CSQ_WF_ACTIVE_COUNT_4 0x24e0
1615 #define mmSPI_CSQ_WF_ACTIVE_COUNT_5 0x24e1
1616 #define mmSPI_CSQ_WF_ACTIVE_COUNT_6 0x24e2
1617 #define mmSPI_CSQ_WF_ACTIVE_COUNT_7 0x24e3
1618 #define mmBCI_DEBUG_READ 0x24eb
1619 #define mmSPI_P0_TRAP_SCREEN_PSBA_LO 0x24ec
1620 #define mmSPI_P0_TRAP_SCREEN_PSBA_HI 0x24ed
1621 #define mmSPI_P0_TRAP_SCREEN_PSMA_LO 0x24ee
1622 #define mmSPI_P0_TRAP_SCREEN_PSMA_HI 0x24ef
1623 #define mmSPI_P0_TRAP_SCREEN_GPR_MIN 0x24f0
1624 #define mmSPI_P1_TRAP_SCREEN_PSBA_LO 0x24f1
1625 #define mmSPI_P1_TRAP_SCREEN_PSBA_HI 0x24f2
1626 #define mmSPI_P1_TRAP_SCREEN_PSMA_LO 0x24f3
1627 #define mmSPI_P1_TRAP_SCREEN_PSMA_HI 0x24f4
1628 #define mmSPI_P1_TRAP_SCREEN_GPR_MIN 0x24f5
1629 #define mmSPI_SHADER_TBA_LO_PS 0x2c00
1630 #define mmSPI_SHADER_TBA_HI_PS 0x2c01
1631 #define mmSPI_SHADER_TMA_LO_PS 0x2c02
1632 #define mmSPI_SHADER_TMA_HI_PS 0x2c03
1633 #define mmSPI_SHADER_PGM_LO_PS 0x2c08
1634 #define mmSPI_SHADER_PGM_HI_PS 0x2c09
1635 #define mmSPI_SHADER_PGM_RSRC1_PS 0x2c0a
1636 #define mmSPI_SHADER_PGM_RSRC2_PS 0x2c0b
1637 #define mmSPI_SHADER_PGM_RSRC3_PS 0x2c07
1638 #define mmSPI_SHADER_USER_DATA_PS_0 0x2c0c
1639 #define mmSPI_SHADER_USER_DATA_PS_1 0x2c0d
1640 #define mmSPI_SHADER_USER_DATA_PS_2 0x2c0e
1641 #define mmSPI_SHADER_USER_DATA_PS_3 0x2c0f
1642 #define mmSPI_SHADER_USER_DATA_PS_4 0x2c10
1643 #define mmSPI_SHADER_USER_DATA_PS_5 0x2c11
1644 #define mmSPI_SHADER_USER_DATA_PS_6 0x2c12
1645 #define mmSPI_SHADER_USER_DATA_PS_7 0x2c13
1646 #define mmSPI_SHADER_USER_DATA_PS_8 0x2c14
1647 #define mmSPI_SHADER_USER_DATA_PS_9 0x2c15
1648 #define mmSPI_SHADER_USER_DATA_PS_10 0x2c16
1649 #define mmSPI_SHADER_USER_DATA_PS_11 0x2c17
1650 #define mmSPI_SHADER_USER_DATA_PS_12 0x2c18
1651 #define mmSPI_SHADER_USER_DATA_PS_13 0x2c19
1652 #define mmSPI_SHADER_USER_DATA_PS_14 0x2c1a
1653 #define mmSPI_SHADER_USER_DATA_PS_15 0x2c1b
1654 #define mmSPI_SHADER_TBA_LO_VS 0x2c40
1655 #define mmSPI_SHADER_TBA_HI_VS 0x2c41
1656 #define mmSPI_SHADER_TMA_LO_VS 0x2c42
1657 #define mmSPI_SHADER_TMA_HI_VS 0x2c43
1658 #define mmSPI_SHADER_PGM_LO_VS 0x2c48
1659 #define mmSPI_SHADER_PGM_HI_VS 0x2c49
1660 #define mmSPI_SHADER_PGM_RSRC1_VS 0x2c4a
1661 #define mmSPI_SHADER_PGM_RSRC2_VS 0x2c4b
1662 #define mmSPI_SHADER_PGM_RSRC3_VS 0x2c46
1663 #define mmSPI_SHADER_LATE_ALLOC_VS 0x2c47
1664 #define mmSPI_SHADER_USER_DATA_VS_0 0x2c4c
1665 #define mmSPI_SHADER_USER_DATA_VS_1 0x2c4d
1666 #define mmSPI_SHADER_USER_DATA_VS_2 0x2c4e
1667 #define mmSPI_SHADER_USER_DATA_VS_3 0x2c4f
1668 #define mmSPI_SHADER_USER_DATA_VS_4 0x2c50
1669 #define mmSPI_SHADER_USER_DATA_VS_5 0x2c51
1670 #define mmSPI_SHADER_USER_DATA_VS_6 0x2c52
1671 #define mmSPI_SHADER_USER_DATA_VS_7 0x2c53
1672 #define mmSPI_SHADER_USER_DATA_VS_8 0x2c54
1673 #define mmSPI_SHADER_USER_DATA_VS_9 0x2c55
1674 #define mmSPI_SHADER_USER_DATA_VS_10 0x2c56
1675 #define mmSPI_SHADER_USER_DATA_VS_11 0x2c57
1676 #define mmSPI_SHADER_USER_DATA_VS_12 0x2c58
1677 #define mmSPI_SHADER_USER_DATA_VS_13 0x2c59
1678 #define mmSPI_SHADER_USER_DATA_VS_14 0x2c5a
1679 #define mmSPI_SHADER_USER_DATA_VS_15 0x2c5b
1680 #define mmSPI_SHADER_PGM_RSRC2_ES_VS 0x2c7c
1681 #define mmSPI_SHADER_PGM_RSRC2_LS_VS 0x2c7d
1682 #define mmSPI_SHADER_TBA_LO_GS 0x2c80
1683 #define mmSPI_SHADER_TBA_HI_GS 0x2c81
1684 #define mmSPI_SHADER_TMA_LO_GS 0x2c82
1685 #define mmSPI_SHADER_TMA_HI_GS 0x2c83
1686 #define mmSPI_SHADER_PGM_LO_GS 0x2c88
1687 #define mmSPI_SHADER_PGM_HI_GS 0x2c89
1688 #define mmSPI_SHADER_PGM_RSRC1_GS 0x2c8a
1689 #define mmSPI_SHADER_PGM_RSRC2_GS 0x2c8b
1690 #define mmSPI_SHADER_PGM_RSRC3_GS 0x2c87
1691 #define mmSPI_SHADER_USER_DATA_GS_0 0x2c8c
1692 #define mmSPI_SHADER_USER_DATA_GS_1 0x2c8d
1693 #define mmSPI_SHADER_USER_DATA_GS_2 0x2c8e
1694 #define mmSPI_SHADER_USER_DATA_GS_3 0x2c8f
1695 #define mmSPI_SHADER_USER_DATA_GS_4 0x2c90
1696 #define mmSPI_SHADER_USER_DATA_GS_5 0x2c91
1697 #define mmSPI_SHADER_USER_DATA_GS_6 0x2c92
1698 #define mmSPI_SHADER_USER_DATA_GS_7 0x2c93
1699 #define mmSPI_SHADER_USER_DATA_GS_8 0x2c94
1700 #define mmSPI_SHADER_USER_DATA_GS_9 0x2c95
1701 #define mmSPI_SHADER_USER_DATA_GS_10 0x2c96
1702 #define mmSPI_SHADER_USER_DATA_GS_11 0x2c97
1703 #define mmSPI_SHADER_USER_DATA_GS_12 0x2c98
1704 #define mmSPI_SHADER_USER_DATA_GS_13 0x2c99
1705 #define mmSPI_SHADER_USER_DATA_GS_14 0x2c9a
1706 #define mmSPI_SHADER_USER_DATA_GS_15 0x2c9b
1707 #define mmSPI_SHADER_PGM_RSRC2_ES_GS 0x2cbc
1708 #define mmSPI_SHADER_TBA_LO_ES 0x2cc0
1709 #define mmSPI_SHADER_TBA_HI_ES 0x2cc1
1710 #define mmSPI_SHADER_TMA_LO_ES 0x2cc2
1711 #define mmSPI_SHADER_TMA_HI_ES 0x2cc3
1712 #define mmSPI_SHADER_PGM_LO_ES 0x2cc8
1713 #define mmSPI_SHADER_PGM_HI_ES 0x2cc9
1714 #define mmSPI_SHADER_PGM_RSRC1_ES 0x2cca
1715 #define mmSPI_SHADER_PGM_RSRC2_ES 0x2ccb
1716 #define mmSPI_SHADER_PGM_RSRC3_ES 0x2cc7
1717 #define mmSPI_SHADER_USER_DATA_ES_0 0x2ccc
1718 #define mmSPI_SHADER_USER_DATA_ES_1 0x2ccd
1719 #define mmSPI_SHADER_USER_DATA_ES_2 0x2cce
1720 #define mmSPI_SHADER_USER_DATA_ES_3 0x2ccf
1721 #define mmSPI_SHADER_USER_DATA_ES_4 0x2cd0
1722 #define mmSPI_SHADER_USER_DATA_ES_5 0x2cd1
1723 #define mmSPI_SHADER_USER_DATA_ES_6 0x2cd2
1724 #define mmSPI_SHADER_USER_DATA_ES_7 0x2cd3
1725 #define mmSPI_SHADER_USER_DATA_ES_8 0x2cd4
1726 #define mmSPI_SHADER_USER_DATA_ES_9 0x2cd5
1727 #define mmSPI_SHADER_USER_DATA_ES_10 0x2cd6
1728 #define mmSPI_SHADER_USER_DATA_ES_11 0x2cd7
1729 #define mmSPI_SHADER_USER_DATA_ES_12 0x2cd8
1730 #define mmSPI_SHADER_USER_DATA_ES_13 0x2cd9
1731 #define mmSPI_SHADER_USER_DATA_ES_14 0x2cda
1732 #define mmSPI_SHADER_USER_DATA_ES_15 0x2cdb
1733 #define mmSPI_SHADER_PGM_RSRC2_LS_ES 0x2cfd
1734 #define mmSPI_SHADER_TBA_LO_HS 0x2d00
1735 #define mmSPI_SHADER_TBA_HI_HS 0x2d01
1736 #define mmSPI_SHADER_TMA_LO_HS 0x2d02
1737 #define mmSPI_SHADER_TMA_HI_HS 0x2d03
1738 #define mmSPI_SHADER_PGM_LO_HS 0x2d08
1739 #define mmSPI_SHADER_PGM_HI_HS 0x2d09
1740 #define mmSPI_SHADER_PGM_RSRC1_HS 0x2d0a
1741 #define mmSPI_SHADER_PGM_RSRC2_HS 0x2d0b
1742 #define mmSPI_SHADER_PGM_RSRC3_HS 0x2d07
1743 #define mmSPI_SHADER_USER_DATA_HS_0 0x2d0c
1744 #define mmSPI_SHADER_USER_DATA_HS_1 0x2d0d
1745 #define mmSPI_SHADER_USER_DATA_HS_2 0x2d0e
1746 #define mmSPI_SHADER_USER_DATA_HS_3 0x2d0f
1747 #define mmSPI_SHADER_USER_DATA_HS_4 0x2d10
1748 #define mmSPI_SHADER_USER_DATA_HS_5 0x2d11
1749 #define mmSPI_SHADER_USER_DATA_HS_6 0x2d12
1750 #define mmSPI_SHADER_USER_DATA_HS_7 0x2d13
1751 #define mmSPI_SHADER_USER_DATA_HS_8 0x2d14
1752 #define mmSPI_SHADER_USER_DATA_HS_9 0x2d15
1753 #define mmSPI_SHADER_USER_DATA_HS_10 0x2d16
1754 #define mmSPI_SHADER_USER_DATA_HS_11 0x2d17
1755 #define mmSPI_SHADER_USER_DATA_HS_12 0x2d18
1756 #define mmSPI_SHADER_USER_DATA_HS_13 0x2d19
1757 #define mmSPI_SHADER_USER_DATA_HS_14 0x2d1a
1758 #define mmSPI_SHADER_USER_DATA_HS_15 0x2d1b
1759 #define mmSPI_SHADER_PGM_RSRC2_LS_HS 0x2d3d
1760 #define mmSPI_SHADER_TBA_LO_LS 0x2d40
1761 #define mmSPI_SHADER_TBA_HI_LS 0x2d41
1762 #define mmSPI_SHADER_TMA_LO_LS 0x2d42
1763 #define mmSPI_SHADER_TMA_HI_LS 0x2d43
1764 #define mmSPI_SHADER_PGM_LO_LS 0x2d48
1765 #define mmSPI_SHADER_PGM_HI_LS 0x2d49
1766 #define mmSPI_SHADER_PGM_RSRC1_LS 0x2d4a
1767 #define mmSPI_SHADER_PGM_RSRC2_LS 0x2d4b
1768 #define mmSPI_SHADER_PGM_RSRC3_LS 0x2d47
1769 #define mmSPI_SHADER_USER_DATA_LS_0 0x2d4c
1770 #define mmSPI_SHADER_USER_DATA_LS_1 0x2d4d
1771 #define mmSPI_SHADER_USER_DATA_LS_2 0x2d4e
1772 #define mmSPI_SHADER_USER_DATA_LS_3 0x2d4f
1773 #define mmSPI_SHADER_USER_DATA_LS_4 0x2d50
1774 #define mmSPI_SHADER_USER_DATA_LS_5 0x2d51
1775 #define mmSPI_SHADER_USER_DATA_LS_6 0x2d52
1776 #define mmSPI_SHADER_USER_DATA_LS_7 0x2d53
1777 #define mmSPI_SHADER_USER_DATA_LS_8 0x2d54
1778 #define mmSPI_SHADER_USER_DATA_LS_9 0x2d55
1779 #define mmSPI_SHADER_USER_DATA_LS_10 0x2d56
1780 #define mmSPI_SHADER_USER_DATA_LS_11 0x2d57
1781 #define mmSPI_SHADER_USER_DATA_LS_12 0x2d58
1782 #define mmSPI_SHADER_USER_DATA_LS_13 0x2d59
1783 #define mmSPI_SHADER_USER_DATA_LS_14 0x2d5a
1784 #define mmSPI_SHADER_USER_DATA_LS_15 0x2d5b
1785 #define mmSQ_CONFIG 0x2300
1786 #define mmSQC_CONFIG 0x2301
1787 #define mmSQC_CACHES 0xc348
1788 #define mmSQ_RANDOM_WAVE_PRI 0x2303
1789 #define mmSQ_REG_CREDITS 0x2304
1790 #define mmSQ_FIFO_SIZES 0x2305
1791 #define mmSQ_INTERRUPT_AUTO_MASK 0x2314
1792 #define mmSQ_INTERRUPT_MSG_CTRL 0x2315
1793 #define mmSQ_PERFCOUNTER_CTRL 0xd9e0
1794 #define mmSQ_PERFCOUNTER_MASK 0xd9e1
1795 #define mmSQ_PERFCOUNTER_CTRL2 0xd9e2
1796 #define mmCC_SQC_BANK_DISABLE 0x2307
1797 #define mmUSER_SQC_BANK_DISABLE 0x2308
1798 #define mmSQ_PERFCOUNTER0_LO 0xd1c0
1799 #define mmSQ_PERFCOUNTER1_LO 0xd1c2
1800 #define mmSQ_PERFCOUNTER2_LO 0xd1c4
1801 #define mmSQ_PERFCOUNTER3_LO 0xd1c6
1802 #define mmSQ_PERFCOUNTER4_LO 0xd1c8
1803 #define mmSQ_PERFCOUNTER5_LO 0xd1ca
1804 #define mmSQ_PERFCOUNTER6_LO 0xd1cc
1805 #define mmSQ_PERFCOUNTER7_LO 0xd1ce
1806 #define mmSQ_PERFCOUNTER8_LO 0xd1d0
1807 #define mmSQ_PERFCOUNTER9_LO 0xd1d2
1808 #define mmSQ_PERFCOUNTER10_LO 0xd1d4
1809 #define mmSQ_PERFCOUNTER11_LO 0xd1d6
1810 #define mmSQ_PERFCOUNTER12_LO 0xd1d8
1811 #define mmSQ_PERFCOUNTER13_LO 0xd1da
1812 #define mmSQ_PERFCOUNTER14_LO 0xd1dc
1813 #define mmSQ_PERFCOUNTER15_LO 0xd1de
1814 #define mmSQ_PERFCOUNTER0_HI 0xd1c1
1815 #define mmSQ_PERFCOUNTER1_HI 0xd1c3
1816 #define mmSQ_PERFCOUNTER2_HI 0xd1c5
1817 #define mmSQ_PERFCOUNTER3_HI 0xd1c7
1818 #define mmSQ_PERFCOUNTER4_HI 0xd1c9
1819 #define mmSQ_PERFCOUNTER5_HI 0xd1cb
1820 #define mmSQ_PERFCOUNTER6_HI 0xd1cd
1821 #define mmSQ_PERFCOUNTER7_HI 0xd1cf
1822 #define mmSQ_PERFCOUNTER8_HI 0xd1d1
1823 #define mmSQ_PERFCOUNTER9_HI 0xd1d3
1824 #define mmSQ_PERFCOUNTER10_HI 0xd1d5
1825 #define mmSQ_PERFCOUNTER11_HI 0xd1d7
1826 #define mmSQ_PERFCOUNTER12_HI 0xd1d9
1827 #define mmSQ_PERFCOUNTER13_HI 0xd1db
1828 #define mmSQ_PERFCOUNTER14_HI 0xd1dd
1829 #define mmSQ_PERFCOUNTER15_HI 0xd1df
1830 #define mmSQ_PERFCOUNTER0_SELECT 0xd9c0
1831 #define mmSQ_PERFCOUNTER1_SELECT 0xd9c1
1832 #define mmSQ_PERFCOUNTER2_SELECT 0xd9c2
1833 #define mmSQ_PERFCOUNTER3_SELECT 0xd9c3
1834 #define mmSQ_PERFCOUNTER4_SELECT 0xd9c4
1835 #define mmSQ_PERFCOUNTER5_SELECT 0xd9c5
1836 #define mmSQ_PERFCOUNTER6_SELECT 0xd9c6
1837 #define mmSQ_PERFCOUNTER7_SELECT 0xd9c7
1838 #define mmSQ_PERFCOUNTER8_SELECT 0xd9c8
1839 #define mmSQ_PERFCOUNTER9_SELECT 0xd9c9
1840 #define mmSQ_PERFCOUNTER10_SELECT 0xd9ca
1841 #define mmSQ_PERFCOUNTER11_SELECT 0xd9cb
1842 #define mmSQ_PERFCOUNTER12_SELECT 0xd9cc
1843 #define mmSQ_PERFCOUNTER13_SELECT 0xd9cd
1844 #define mmSQ_PERFCOUNTER14_SELECT 0xd9ce
1845 #define mmSQ_PERFCOUNTER15_SELECT 0xd9cf
1846 #define mmCGTT_SQ_CLK_CTRL 0xf08c
1847 #define mmCGTT_SQG_CLK_CTRL 0xf08d
1848 #define mmSQ_ALU_CLK_CTRL 0xf08e
1849 #define mmSQ_TEX_CLK_CTRL 0xf08f
1850 #define mmSQ_LDS_CLK_CTRL 0xf090
1851 #define mmSQ_POWER_THROTTLE 0xf091
1852 #define mmSQ_POWER_THROTTLE2 0xf092
1853 #define mmSQ_TIME_HI 0x237c
1854 #define mmSQ_TIME_LO 0x237d
1855 #define mmSQ_THREAD_TRACE_BASE 0x2380
1856 #define mmSQ_THREAD_TRACE_BASE2 0x2385
1857 #define mmSQ_THREAD_TRACE_SIZE 0x2381
1858 #define mmSQ_THREAD_TRACE_MASK 0x2382
1859 #define mmSQ_THREAD_TRACE_USERDATA_0 0xc340
1860 #define mmSQ_THREAD_TRACE_USERDATA_1 0xc341
1861 #define mmSQ_THREAD_TRACE_USERDATA_2 0xc342
1862 #define mmSQ_THREAD_TRACE_USERDATA_3 0xc343
1863 #define mmSQ_THREAD_TRACE_MODE 0x238e
1864 #define mmSQ_THREAD_TRACE_CTRL 0x238f
1865 #define mmSQ_THREAD_TRACE_TOKEN_MASK 0x2383
1866 #define mmSQ_THREAD_TRACE_TOKEN_MASK2 0x2386
1867 #define mmSQ_THREAD_TRACE_PERF_MASK 0x2384
1868 #define mmSQ_THREAD_TRACE_WPTR 0x238c
1869 #define mmSQ_THREAD_TRACE_STATUS 0x238d
1870 #define mmSQ_THREAD_TRACE_CNTR 0x2390
1871 #define mmSQ_THREAD_TRACE_HIWATER 0x2392
1872 #define mmSQ_LB_CTR_CTRL 0x2398
1873 #define mmSQ_LB_DATA_ALU_CYCLES 0x2399
1874 #define mmSQ_LB_DATA_TEX_CYCLES 0x239a
1875 #define mmSQ_LB_DATA_ALU_STALLS 0x239b
1876 #define mmSQ_LB_DATA_TEX_STALLS 0x239c
1877 #define mmSQC_SECDED_CNT 0x23a0
1878 #define mmSQ_SEC_CNT 0x23a1
1879 #define mmSQ_DED_CNT 0x23a2
1880 #define mmSQ_DED_INFO 0x23a3
1881 #define mmSQ_BUF_RSRC_WORD0 0x23c0
1882 #define mmSQ_BUF_RSRC_WORD1 0x23c1
1883 #define mmSQ_BUF_RSRC_WORD2 0x23c2
1884 #define mmSQ_BUF_RSRC_WORD3 0x23c3
1885 #define mmSQ_IMG_RSRC_WORD0 0x23c4
1886 #define mmSQ_IMG_RSRC_WORD1 0x23c5
1887 #define mmSQ_IMG_RSRC_WORD2 0x23c6
1888 #define mmSQ_IMG_RSRC_WORD3 0x23c7
1889 #define mmSQ_IMG_RSRC_WORD4 0x23c8
1890 #define mmSQ_IMG_RSRC_WORD5 0x23c9
1891 #define mmSQ_IMG_RSRC_WORD6 0x23ca
1892 #define mmSQ_IMG_RSRC_WORD7 0x23cb
1893 #define mmSQ_IMG_SAMP_WORD0 0x23cc
1894 #define mmSQ_IMG_SAMP_WORD1 0x23cd
1895 #define mmSQ_IMG_SAMP_WORD2 0x23ce
1896 #define mmSQ_IMG_SAMP_WORD3 0x23cf
1897 #define mmSQ_FLAT_SCRATCH_WORD0 0x23d0
1898 #define mmSQ_FLAT_SCRATCH_WORD1 0x23d1
1899 #define mmSQ_IND_INDEX 0x2378
1900 #define mmSQ_IND_CMD 0x237a
1901 #define mmSQ_CMD 0x237b
1902 #define mmSQ_IND_DATA 0x2379
1903 #define mmSQ_REG_TIMESTAMP 0x2374
1904 #define mmSQ_CMD_TIMESTAMP 0x2375
1905 #define mmSQ_HV_VMID_CTRL 0xf840
1906 #define ixSQ_WAVE_INST_DW0 0x1a
1907 #define ixSQ_WAVE_INST_DW1 0x1b
1908 #define ixSQ_WAVE_PC_LO 0x18
1909 #define ixSQ_WAVE_PC_HI 0x19
1910 #define ixSQ_WAVE_IB_DBG0 0x1c
1911 #define ixSQ_WAVE_EXEC_LO 0x27e
1912 #define ixSQ_WAVE_EXEC_HI 0x27f
1913 #define ixSQ_WAVE_STATUS 0x12
1914 #define ixSQ_WAVE_MODE 0x11
1915 #define ixSQ_WAVE_TRAPSTS 0x13
1916 #define ixSQ_WAVE_HW_ID 0x14
1917 #define ixSQ_WAVE_GPR_ALLOC 0x15
1918 #define ixSQ_WAVE_LDS_ALLOC 0x16
1919 #define ixSQ_WAVE_IB_STS 0x17
1920 #define ixSQ_WAVE_M0 0x27c
1921 #define ixSQ_WAVE_TBA_LO 0x26c
1922 #define ixSQ_WAVE_TBA_HI 0x26d
1923 #define ixSQ_WAVE_TMA_LO 0x26e
1924 #define ixSQ_WAVE_TMA_HI 0x26f
1925 #define ixSQ_WAVE_TTMP0 0x270
1926 #define ixSQ_WAVE_TTMP1 0x271
1927 #define ixSQ_WAVE_TTMP2 0x272
1928 #define ixSQ_WAVE_TTMP3 0x273
1929 #define ixSQ_WAVE_TTMP4 0x274
1930 #define ixSQ_WAVE_TTMP5 0x275
1931 #define ixSQ_WAVE_TTMP6 0x276
1932 #define ixSQ_WAVE_TTMP7 0x277
1933 #define ixSQ_WAVE_TTMP8 0x278
1934 #define ixSQ_WAVE_TTMP9 0x279
1935 #define ixSQ_WAVE_TTMP10 0x27a
1936 #define ixSQ_WAVE_TTMP11 0x27b
1937 #define mmSQ_DEBUG_STS_GLOBAL 0x2309
1938 #define mmSQ_DEBUG_STS_GLOBAL2 0x2310
1939 #define mmSQ_DEBUG_STS_GLOBAL3 0x2311
1940 #define ixSQ_DEBUG_STS_LOCAL 0x8
1941 #define ixSQ_DEBUG_CTRL_LOCAL 0x9
1942 #define mmSH_MEM_BASES 0x230a
1943 #define mmSH_MEM_APE1_BASE 0x230b
1944 #define mmSH_MEM_APE1_LIMIT 0x230c
1945 #define mmSH_MEM_CONFIG 0x230d
1946 #define mmSQC_POLICY 0x230e
1947 #define mmSQC_VOLATILE 0x230f
1948 #define mmSQ_THREAD_TRACE_WORD_CMN 0x23b0
1949 #define mmSQ_THREAD_TRACE_WORD_INST 0x23b0
1950 #define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 0x23b0
1951 #define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 0x23b1
1952 #define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 0x23b0
1953 #define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 0x23b1
1954 #define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 0x23b0
1955 #define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 0x23b1
1956 #define mmSQ_THREAD_TRACE_WORD_WAVE 0x23b0
1957 #define mmSQ_THREAD_TRACE_WORD_MISC 0x23b0
1958 #define mmSQ_THREAD_TRACE_WORD_WAVE_START 0x23b0
1959 #define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2 0x23b0
1960 #define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2 0x23b0
1961 #define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 0x23b0
1962 #define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 0x23b0
1963 #define mmSQ_THREAD_TRACE_WORD_EVENT 0x23b0
1964 #define mmSQ_THREAD_TRACE_WORD_ISSUE 0x23b0
1965 #define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2 0x23b0
1966 #define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2 0x23b1
1967 #define ixSQ_INTERRUPT_WORD_CMN 0x20c0
1968 #define ixSQ_INTERRUPT_WORD_AUTO 0x20c0
1969 #define ixSQ_INTERRUPT_WORD_WAVE 0x20c0
1970 #define mmSQ_SOP2 0x237f
1971 #define mmSQ_VOP1 0x237f
1972 #define mmSQ_MTBUF_1 0x237f
1973 #define mmSQ_EXP_1 0x237f
1974 #define mmSQ_MUBUF_1 0x237f
1975 #define mmSQ_INST 0x237f
1976 #define mmSQ_EXP_0 0x237f
1977 #define mmSQ_MUBUF_0 0x237f
1978 #define mmSQ_VOP3_0 0x237f
1979 #define mmSQ_VOP2 0x237f
1980 #define mmSQ_MTBUF_0 0x237f
1981 #define mmSQ_SOPP 0x237f
1982 #define mmSQ_FLAT_0 0x237f
1983 #define mmSQ_VOP3_0_SDST_ENC 0x237f
1984 #define mmSQ_MIMG_1 0x237f
1985 #define mmSQ_SMRD 0x237f
1986 #define mmSQ_SOP1 0x237f
1987 #define mmSQ_SOPC 0x237f
1988 #define mmSQ_FLAT_1 0x237f
1989 #define mmSQ_DS_1 0x237f
1990 #define mmSQ_VOP3_1 0x237f
1991 #define mmSQ_MIMG_0 0x237f
1992 #define mmSQ_SOPK 0x237f
1993 #define mmSQ_DS_0 0x237f
1994 #define mmSQ_VOPC 0x237f
1995 #define mmSQ_VINTRP 0x237f
1996 #define mmCGTT_SX_CLK_CTRL0 0xf094
1997 #define mmCGTT_SX_CLK_CTRL1 0xf095
1998 #define mmCGTT_SX_CLK_CTRL2 0xf096
1999 #define mmCGTT_SX_CLK_CTRL3 0xf097
2000 #define mmCGTT_SX_CLK_CTRL4 0xf098
2001 #define mmSX_DEBUG_BUSY 0x2414
2002 #define mmSX_DEBUG_BUSY_2 0x2415
2003 #define mmSX_DEBUG_BUSY_3 0x2416
2004 #define mmSX_DEBUG_BUSY_4 0x2417
2005 #define mmSX_DEBUG_1 0x2418
2006 #define mmSX_PERFCOUNTER0_SELECT 0xda40
2007 #define mmSX_PERFCOUNTER1_SELECT 0xda41
2008 #define mmSX_PERFCOUNTER2_SELECT 0xda42
2009 #define mmSX_PERFCOUNTER3_SELECT 0xda43
2010 #define mmSX_PERFCOUNTER0_SELECT1 0xda44
2011 #define mmSX_PERFCOUNTER1_SELECT1 0xda45
2012 #define mmSX_PERFCOUNTER0_LO 0xd240
2013 #define mmSX_PERFCOUNTER0_HI 0xd241
2014 #define mmSX_PERFCOUNTER1_LO 0xd242
2015 #define mmSX_PERFCOUNTER1_HI 0xd243
2016 #define mmSX_PERFCOUNTER2_LO 0xd244
2017 #define mmSX_PERFCOUNTER2_HI 0xd245
2018 #define mmSX_PERFCOUNTER3_LO 0xd246
2019 #define mmSX_PERFCOUNTER3_HI 0xd247
2020 #define mmTCC_CTRL 0x2b80
2021 #define mmTCC_EDC_COUNTER 0x2b82
2022 #define mmTCC_REDUNDANCY 0x2b83
2023 #define mmTCC_CGTT_SCLK_CTRL 0xf0ac
2024 #define mmTCA_CGTT_SCLK_CTRL 0xf0ad
2025 #define mmTCS_CGTT_SCLK_CTRL 0xf0ae
2026 #define mmTCC_PERFCOUNTER0_SELECT 0xdb80
2027 #define mmTCC_PERFCOUNTER1_SELECT 0xdb82
2028 #define mmTCC_PERFCOUNTER0_SELECT1 0xdb81
2029 #define mmTCC_PERFCOUNTER1_SELECT1 0xdb83
2030 #define mmTCC_PERFCOUNTER2_SELECT 0xdb84
2031 #define mmTCC_PERFCOUNTER3_SELECT 0xdb85
2032 #define mmTCC_PERFCOUNTER0_LO 0xd380
2033 #define mmTCC_PERFCOUNTER1_LO 0xd382
2034 #define mmTCC_PERFCOUNTER2_LO 0xd384
2035 #define mmTCC_PERFCOUNTER3_LO 0xd386
2036 #define mmTCC_PERFCOUNTER0_HI 0xd381
2037 #define mmTCC_PERFCOUNTER1_HI 0xd383
2038 #define mmTCC_PERFCOUNTER2_HI 0xd385
2039 #define mmTCC_PERFCOUNTER3_HI 0xd387
2040 #define mmTCA_CTRL 0x2bc0
2041 #define mmTCA_PERFCOUNTER0_SELECT 0xdb90
2042 #define mmTCA_PERFCOUNTER1_SELECT 0xdb92
2043 #define mmTCA_PERFCOUNTER0_SELECT1 0xdb91
2044 #define mmTCA_PERFCOUNTER1_SELECT1 0xdb93
2045 #define mmTCA_PERFCOUNTER2_SELECT 0xdb94
2046 #define mmTCA_PERFCOUNTER3_SELECT 0xdb95
2047 #define mmTCA_PERFCOUNTER0_LO 0xd390
2048 #define mmTCA_PERFCOUNTER1_LO 0xd392
2049 #define mmTCA_PERFCOUNTER2_LO 0xd394
2050 #define mmTCA_PERFCOUNTER3_LO 0xd396
2051 #define mmTCA_PERFCOUNTER0_HI 0xd391
2052 #define mmTCA_PERFCOUNTER1_HI 0xd393
2053 #define mmTCA_PERFCOUNTER2_HI 0xd395
2054 #define mmTCA_PERFCOUNTER3_HI 0xd397
2055 #define mmTCS_CTRL 0x2be0
2056 #define mmTCS_PERFCOUNTER0_SELECT 0xdba0
2057 #define mmTCS_PERFCOUNTER0_SELECT1 0xdba1
2058 #define mmTCS_PERFCOUNTER1_SELECT 0xdba2
2059 #define mmTCS_PERFCOUNTER2_SELECT 0xdba3
2060 #define mmTCS_PERFCOUNTER3_SELECT 0xdba4
2061 #define mmTCS_PERFCOUNTER0_LO 0xd3a0
2062 #define mmTCS_PERFCOUNTER1_LO 0xd3a2
2063 #define mmTCS_PERFCOUNTER2_LO 0xd3a4
2064 #define mmTCS_PERFCOUNTER3_LO 0xd3a6
2065 #define mmTCS_PERFCOUNTER0_HI 0xd3a1
2066 #define mmTCS_PERFCOUNTER1_HI 0xd3a3
2067 #define mmTCS_PERFCOUNTER2_HI 0xd3a5
2068 #define mmTCS_PERFCOUNTER3_HI 0xd3a7
2069 #define mmTA_BC_BASE_ADDR 0xa020
2070 #define mmTA_BC_BASE_ADDR_HI 0xa021
2071 #define mmTD_CNTL 0x2525
2072 #define mmTD_STATUS 0x2526
2073 #define mmTD_DEBUG_INDEX 0x2528
2074 #define mmTD_DEBUG_DATA 0x2529
2075 #define mmTD_PERFCOUNTER0_SELECT 0xdb00
2076 #define mmTD_PERFCOUNTER1_SELECT 0xdb02
2077 #define mmTD_PERFCOUNTER0_SELECT1 0xdb01
2078 #define mmTD_PERFCOUNTER0_LO 0xd300
2079 #define mmTD_PERFCOUNTER1_LO 0xd302
2080 #define mmTD_PERFCOUNTER0_HI 0xd301
2081 #define mmTD_PERFCOUNTER1_HI 0xd303
2082 #define mmTD_SCRATCH 0x2533
2083 #define mmTA_CNTL 0x2541
2084 #define mmTA_CNTL_AUX 0x2542
2085 #define mmTA_RESERVED_010C 0x2543
2086 #define mmTA_CS_BC_BASE_ADDR 0xc380
2087 #define mmTA_CS_BC_BASE_ADDR_HI 0xc381
2088 #define mmTA_STATUS 0x2548
2089 #define mmTA_DEBUG_INDEX 0x254c
2090 #define mmTA_DEBUG_DATA 0x254d
2091 #define mmTA_PERFCOUNTER0_SELECT 0xdac0
2092 #define mmTA_PERFCOUNTER1_SELECT 0xdac2
2093 #define mmTA_PERFCOUNTER0_SELECT1 0xdac1
2094 #define mmTA_PERFCOUNTER0_LO 0xd2c0
2095 #define mmTA_PERFCOUNTER1_LO 0xd2c2
2096 #define mmTA_PERFCOUNTER0_HI 0xd2c1
2097 #define mmTA_PERFCOUNTER1_HI 0xd2c3
2098 #define mmTA_SCRATCH 0x2564
2099 #define mmSH_HIDDEN_PRIVATE_BASE_VMID 0x2580
2100 #define mmSH_STATIC_MEM_CONFIG 0x2581
2101 #define mmTCP_INVALIDATE 0x2b00
2102 #define mmTCP_STATUS 0x2b01
2103 #define mmTCP_CNTL 0x2b02
2104 #define mmTCP_CHAN_STEER_LO 0x2b03
2105 #define mmTCP_CHAN_STEER_HI 0x2b04
2106 #define mmTCP_ADDR_CONFIG 0x2b05
2107 #define mmTCP_CREDIT 0x2b06
2108 #define mmTCP_PERFCOUNTER0_SELECT 0xdb40
2109 #define mmTCP_PERFCOUNTER1_SELECT 0xdb42
2110 #define mmTCP_PERFCOUNTER0_SELECT1 0xdb41
2111 #define mmTCP_PERFCOUNTER1_SELECT1 0xdb43
2112 #define mmTCP_PERFCOUNTER2_SELECT 0xdb44
2113 #define mmTCP_PERFCOUNTER3_SELECT 0xdb45
2114 #define mmTCP_PERFCOUNTER0_LO 0xd340
2115 #define mmTCP_PERFCOUNTER1_LO 0xd342
2116 #define mmTCP_PERFCOUNTER2_LO 0xd344
2117 #define mmTCP_PERFCOUNTER3_LO 0xd346
2118 #define mmTCP_PERFCOUNTER0_HI 0xd341
2119 #define mmTCP_PERFCOUNTER1_HI 0xd343
2120 #define mmTCP_PERFCOUNTER2_HI 0xd345
2121 #define mmTCP_PERFCOUNTER3_HI 0xd347
2122 #define mmTCP_BUFFER_ADDR_HASH_CNTL 0x2b16
2123 #define mmTCP_EDC_COUNTER 0x2b17
2124 #define mmTC_CFG_L1_LOAD_POLICY0 0x2b1a
2125 #define mmTC_CFG_L1_LOAD_POLICY1 0x2b1b
2126 #define mmTC_CFG_L1_STORE_POLICY 0x2b1c
2127 #define mmTC_CFG_L2_LOAD_POLICY0 0x2b1d
2128 #define mmTC_CFG_L2_LOAD_POLICY1 0x2b1e
2129 #define mmTC_CFG_L2_STORE_POLICY0 0x2b1f
2130 #define mmTC_CFG_L2_STORE_POLICY1 0x2b20
2131 #define mmTC_CFG_L2_ATOMIC_POLICY 0x2b21
2132 #define mmTC_CFG_L1_VOLATILE 0x2b22
2133 #define mmTC_CFG_L2_VOLATILE 0x2b23
2134 #define mmTCP_WATCH0_ADDR_H 0x32a0
2135 #define mmTCP_WATCH1_ADDR_H 0x32a3
2136 #define mmTCP_WATCH2_ADDR_H 0x32a6
2137 #define mmTCP_WATCH3_ADDR_H 0x32a9
2138 #define mmTCP_WATCH0_ADDR_L 0x32a1
2139 #define mmTCP_WATCH1_ADDR_L 0x32a4
2140 #define mmTCP_WATCH2_ADDR_L 0x32a7
2141 #define mmTCP_WATCH3_ADDR_L 0x32aa
2142 #define mmTCP_WATCH0_CNTL 0x32a2
2143 #define mmTCP_WATCH1_CNTL 0x32a5
2144 #define mmTCP_WATCH2_CNTL 0x32a8
2145 #define mmTCP_WATCH3_CNTL 0x32ab
2146 #define mmTD_CGTT_CTRL 0xf09c
2147 #define mmTA_CGTT_CTRL 0xf09d
2148 #define mmCGTT_TCP_CLK_CTRL 0xf09e
2149 #define mmCGTT_TCI_CLK_CTRL 0xf09f
2150 #define mmTCI_STATUS 0x2b61
2151 #define mmTCI_CNTL_1 0x2b62
2152 #define mmTCI_CNTL_2 0x2b63
2153 #define mmGDS_CONFIG 0x25c0
2154 #define mmGDS_CNTL_STATUS 0x25c1
2155 #define mmGDS_ENHANCE 0x25c2
2156 #define mmGDS_PROTECTION_FAULT 0x25c3
2157 #define mmGDS_VM_PROTECTION_FAULT 0x25c4
2158 #define mmGDS_SECDED_CNT 0x25c5
2159 #define mmGDS_GRBM_SECDED_CNT 0x25c6
2160 #define mmGDS_OA_DED 0x25c7
2161 #define mmGDS_DEBUG_CNTL 0x25c8
2162 #define mmGDS_DEBUG_DATA 0x25c9
2163 #define mmCGTT_GDS_CLK_CTRL 0xf0a0
2164 #define mmGDS_RD_ADDR 0xc400
2165 #define mmGDS_RD_DATA 0xc401
2166 #define mmGDS_RD_BURST_ADDR 0xc402
2167 #define mmGDS_RD_BURST_COUNT 0xc403
2168 #define mmGDS_RD_BURST_DATA 0xc404
2169 #define mmGDS_WR_ADDR 0xc405
2170 #define mmGDS_WR_DATA 0xc406
2171 #define mmGDS_WR_BURST_ADDR 0xc407
2172 #define mmGDS_WR_BURST_DATA 0xc408
2173 #define mmGDS_WRITE_COMPLETE 0xc409
2174 #define mmGDS_ATOM_CNTL 0xc40a
2175 #define mmGDS_ATOM_COMPLETE 0xc40b
2176 #define mmGDS_ATOM_BASE 0xc40c
2177 #define mmGDS_ATOM_SIZE 0xc40d
2178 #define mmGDS_ATOM_OFFSET0 0xc40e
2179 #define mmGDS_ATOM_OFFSET1 0xc40f
2180 #define mmGDS_ATOM_DST 0xc410
2181 #define mmGDS_ATOM_OP 0xc411
2182 #define mmGDS_ATOM_SRC0 0xc412
2183 #define mmGDS_ATOM_SRC0_U 0xc413
2184 #define mmGDS_ATOM_SRC1 0xc414
2185 #define mmGDS_ATOM_SRC1_U 0xc415
2186 #define mmGDS_ATOM_READ0 0xc416
2187 #define mmGDS_ATOM_READ0_U 0xc417
2188 #define mmGDS_ATOM_READ1 0xc418
2189 #define mmGDS_ATOM_READ1_U 0xc419
2190 #define mmGDS_GWS_RESOURCE_CNTL 0xc41a
2191 #define mmGDS_GWS_RESOURCE 0xc41b
2192 #define mmGDS_GWS_RESOURCE_CNT 0xc41c
2193 #define mmGDS_OA_CNTL 0xc41d
2194 #define mmGDS_OA_COUNTER 0xc41e
2195 #define mmGDS_OA_ADDRESS 0xc41f
2196 #define mmGDS_OA_INCDEC 0xc420
2197 #define ixGDS_DEBUG_REG0 0x0
2198 #define ixGDS_DEBUG_REG1 0x1
2199 #define ixGDS_DEBUG_REG2 0x2
2200 #define ixGDS_DEBUG_REG3 0x3
2201 #define ixGDS_DEBUG_REG4 0x4
2202 #define ixGDS_DEBUG_REG5 0x5
2203 #define ixGDS_DEBUG_REG6 0x6
2204 #define mmGDS_PERFCOUNTER0_SELECT 0xda80
2205 #define mmGDS_PERFCOUNTER1_SELECT 0xda81
2206 #define mmGDS_PERFCOUNTER2_SELECT 0xda82
2207 #define mmGDS_PERFCOUNTER3_SELECT 0xda83
2208 #define mmGDS_PERFCOUNTER0_LO 0xd280
2209 #define mmGDS_PERFCOUNTER1_LO 0xd282
2210 #define mmGDS_PERFCOUNTER2_LO 0xd284
2211 #define mmGDS_PERFCOUNTER3_LO 0xd286
2212 #define mmGDS_PERFCOUNTER0_HI 0xd281
2213 #define mmGDS_PERFCOUNTER1_HI 0xd283
2214 #define mmGDS_PERFCOUNTER2_HI 0xd285
2215 #define mmGDS_PERFCOUNTER3_HI 0xd287
2216 #define mmGDS_PERFCOUNTER0_SELECT1 0xda84
2217 #define mmGDS_VMID0_BASE 0x3300
2218 #define mmGDS_VMID1_BASE 0x3302
2219 #define mmGDS_VMID2_BASE 0x3304
2220 #define mmGDS_VMID3_BASE 0x3306
2221 #define mmGDS_VMID4_BASE 0x3308
2222 #define mmGDS_VMID5_BASE 0x330a
2223 #define mmGDS_VMID6_BASE 0x330c
2224 #define mmGDS_VMID7_BASE 0x330e
2225 #define mmGDS_VMID8_BASE 0x3310
2226 #define mmGDS_VMID9_BASE 0x3312
2227 #define mmGDS_VMID10_BASE 0x3314
2228 #define mmGDS_VMID11_BASE 0x3316
2229 #define mmGDS_VMID12_BASE 0x3318
2230 #define mmGDS_VMID13_BASE 0x331a
2231 #define mmGDS_VMID14_BASE 0x331c
2232 #define mmGDS_VMID15_BASE 0x331e
2233 #define mmGDS_VMID0_SIZE 0x3301
2234 #define mmGDS_VMID1_SIZE 0x3303
2235 #define mmGDS_VMID2_SIZE 0x3305
2236 #define mmGDS_VMID3_SIZE 0x3307
2237 #define mmGDS_VMID4_SIZE 0x3309
2238 #define mmGDS_VMID5_SIZE 0x330b
2239 #define mmGDS_VMID6_SIZE 0x330d
2240 #define mmGDS_VMID7_SIZE 0x330f
2241 #define mmGDS_VMID8_SIZE 0x3311
2242 #define mmGDS_VMID9_SIZE 0x3313
2243 #define mmGDS_VMID10_SIZE 0x3315
2244 #define mmGDS_VMID11_SIZE 0x3317
2245 #define mmGDS_VMID12_SIZE 0x3319
2246 #define mmGDS_VMID13_SIZE 0x331b
2247 #define mmGDS_VMID14_SIZE 0x331d
2248 #define mmGDS_VMID15_SIZE 0x331f
2249 #define mmGDS_GWS_VMID0 0x3320
2250 #define mmGDS_GWS_VMID1 0x3321
2251 #define mmGDS_GWS_VMID2 0x3322
2252 #define mmGDS_GWS_VMID3 0x3323
2253 #define mmGDS_GWS_VMID4 0x3324
2254 #define mmGDS_GWS_VMID5 0x3325
2255 #define mmGDS_GWS_VMID6 0x3326
2256 #define mmGDS_GWS_VMID7 0x3327
2257 #define mmGDS_GWS_VMID8 0x3328
2258 #define mmGDS_GWS_VMID9 0x3329
2259 #define mmGDS_GWS_VMID10 0x332a
2260 #define mmGDS_GWS_VMID11 0x332b
2261 #define mmGDS_GWS_VMID12 0x332c
2262 #define mmGDS_GWS_VMID13 0x332d
2263 #define mmGDS_GWS_VMID14 0x332e
2264 #define mmGDS_GWS_VMID15 0x332f
2265 #define mmGDS_OA_VMID0 0x3330
2266 #define mmGDS_OA_VMID1 0x3331
2267 #define mmGDS_OA_VMID2 0x3332
2268 #define mmGDS_OA_VMID3 0x3333
2269 #define mmGDS_OA_VMID4 0x3334
2270 #define mmGDS_OA_VMID5 0x3335
2271 #define mmGDS_OA_VMID6 0x3336
2272 #define mmGDS_OA_VMID7 0x3337
2273 #define mmGDS_OA_VMID8 0x3338
2274 #define mmGDS_OA_VMID9 0x3339
2275 #define mmGDS_OA_VMID10 0x333a
2276 #define mmGDS_OA_VMID11 0x333b
2277 #define mmGDS_OA_VMID12 0x333c
2278 #define mmGDS_OA_VMID13 0x333d
2279 #define mmGDS_OA_VMID14 0x333e
2280 #define mmGDS_OA_VMID15 0x333f
2281 #define mmGDS_GWS_RESET0 0x3344
2282 #define mmGDS_GWS_RESET1 0x3345
2283 #define mmGDS_GWS_RESOURCE_RESET 0x3346
2284 #define mmGDS_COMPUTE_MAX_WAVE_ID 0x3348
2285 #define mmGDS_OA_RESET_MASK 0x3349
2286 #define mmGDS_OA_RESET 0x334a
2287 #define mmCS_COPY_STATE 0xa1f3
2288 #define mmGFX_COPY_STATE 0xa1f4
2289 #define mmVGT_DRAW_INITIATOR 0xa1fc
2290 #define mmVGT_EVENT_INITIATOR 0xa2a4
2291 #define mmVGT_EVENT_ADDRESS_REG 0xa1fe
2292 #define mmVGT_DMA_BASE_HI 0xa1f9
2293 #define mmVGT_DMA_BASE 0xa1fa
2294 #define mmVGT_DMA_INDEX_TYPE 0xa29f
2295 #define mmVGT_DMA_NUM_INSTANCES 0xa2a2
2296 #define mmIA_ENHANCE 0xa29c
2297 #define mmVGT_DMA_SIZE 0xa29d
2298 #define mmVGT_DMA_MAX_SIZE 0xa29e
2299 #define mmVGT_DMA_PRIMITIVE_TYPE 0x2271
2300 #define mmVGT_DMA_CONTROL 0x2272
2301 #define mmVGT_IMMED_DATA 0xa1fd
2302 #define mmVGT_INDEX_TYPE 0xc243
2303 #define mmVGT_NUM_INDICES 0xc24c
2304 #define mmVGT_NUM_INSTANCES 0xc24d
2305 #define mmVGT_PRIMITIVE_TYPE 0xc242
2306 #define mmVGT_PRIMITIVEID_EN 0xa2a1
2307 #define mmVGT_PRIMITIVEID_RESET 0xa2a3
2308 #define mmVGT_VTX_CNT_EN 0xa2ae
2309 #define mmVGT_REUSE_OFF 0xa2ad
2310 #define mmVGT_INSTANCE_STEP_RATE_0 0xa2a8
2311 #define mmVGT_INSTANCE_STEP_RATE_1 0xa2a9
2312 #define mmVGT_MAX_VTX_INDX 0xa100
2313 #define mmVGT_MIN_VTX_INDX 0xa101
2314 #define mmVGT_INDX_OFFSET 0xa102
2315 #define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0xa316
2316 #define mmVGT_OUT_DEALLOC_CNTL 0xa317
2317 #define mmVGT_MULTI_PRIM_IB_RESET_INDX 0xa103
2318 #define mmVGT_MULTI_PRIM_IB_RESET_EN 0xa2a5
2319 #define mmVGT_ENHANCE 0xa294
2320 #define mmVGT_OUTPUT_PATH_CNTL 0xa284
2321 #define mmVGT_HOS_CNTL 0xa285
2322 #define mmVGT_HOS_MAX_TESS_LEVEL 0xa286
2323 #define mmVGT_HOS_MIN_TESS_LEVEL 0xa287
2324 #define mmVGT_HOS_REUSE_DEPTH 0xa288
2325 #define mmVGT_GROUP_PRIM_TYPE 0xa289
2326 #define mmVGT_GROUP_FIRST_DECR 0xa28a
2327 #define mmVGT_GROUP_DECR 0xa28b
2328 #define mmVGT_GROUP_VECT_0_CNTL 0xa28c
2329 #define mmVGT_GROUP_VECT_1_CNTL 0xa28d
2330 #define mmVGT_GROUP_VECT_0_FMT_CNTL 0xa28e
2331 #define mmVGT_GROUP_VECT_1_FMT_CNTL 0xa28f
2332 #define mmVGT_VTX_VECT_EJECT_REG 0x222c
2333 #define mmVGT_DMA_DATA_FIFO_DEPTH 0x222d
2334 #define mmVGT_DMA_REQ_FIFO_DEPTH 0x222e
2335 #define mmVGT_DRAW_INIT_FIFO_DEPTH 0x222f
2336 #define mmVGT_LAST_COPY_STATE 0x2230
2337 #define mmCC_GC_SHADER_ARRAY_CONFIG 0x226f
2338 #define mmGC_USER_SHADER_ARRAY_CONFIG 0x2270
2339 #define mmVGT_GS_MODE 0xa290
2340 #define mmVGT_GS_ONCHIP_CNTL 0xa291
2341 #define mmVGT_GS_OUT_PRIM_TYPE 0xa29b
2342 #define mmVGT_CACHE_INVALIDATION 0x2231
2343 #define mmVGT_RESET_DEBUG 0x2232
2344 #define mmVGT_STRMOUT_DELAY 0x2233
2345 #define mmVGT_FIFO_DEPTHS 0x2234
2346 #define mmVGT_GS_PER_ES 0xa295
2347 #define mmVGT_ES_PER_GS 0xa296
2348 #define mmVGT_GS_PER_VS 0xa297
2349 #define mmVGT_GS_VERTEX_REUSE 0x2235
2350 #define mmVGT_MC_LAT_CNTL 0x2236
2351 #define mmIA_CNTL_STATUS 0x2237
2352 #define mmVGT_STRMOUT_CONFIG 0xa2e5
2353 #define mmVGT_STRMOUT_BUFFER_SIZE_0 0xa2b4
2354 #define mmVGT_STRMOUT_BUFFER_SIZE_1 0xa2b8
2355 #define mmVGT_STRMOUT_BUFFER_SIZE_2 0xa2bc
2356 #define mmVGT_STRMOUT_BUFFER_SIZE_3 0xa2c0
2357 #define mmVGT_STRMOUT_BUFFER_OFFSET_0 0xa2b7
2358 #define mmVGT_STRMOUT_BUFFER_OFFSET_1 0xa2bb
2359 #define mmVGT_STRMOUT_BUFFER_OFFSET_2 0xa2bf
2360 #define mmVGT_STRMOUT_BUFFER_OFFSET_3 0xa2c3
2361 #define mmVGT_STRMOUT_VTX_STRIDE_0 0xa2b5
2362 #define mmVGT_STRMOUT_VTX_STRIDE_1 0xa2b9
2363 #define mmVGT_STRMOUT_VTX_STRIDE_2 0xa2bd
2364 #define mmVGT_STRMOUT_VTX_STRIDE_3 0xa2c1
2365 #define mmVGT_STRMOUT_BUFFER_CONFIG 0xa2e6
2366 #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0 0xc244
2367 #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1 0xc245
2368 #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2 0xc246
2369 #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3 0xc247
2370 #define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0xa2ca
2371 #define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0xa2cb
2372 #define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0xa2cc
2373 #define mmVGT_GS_MAX_VERT_OUT 0xa2ce
2374 #define mmIA_VMID_OVERRIDE 0x2260
2375 #define mmVGT_SHADER_STAGES_EN 0xa2d5
2376 #define mmVGT_LS_HS_CONFIG 0xa2d6
2377 #define mmVGT_DMA_LS_HS_CONFIG 0x2273
2378 #define mmVGT_TF_PARAM 0xa2db
2379 #define mmVGT_TF_RING_SIZE 0xc24e
2380 #define mmVGT_SYS_CONFIG 0x2263
2381 #define mmVGT_HS_OFFCHIP_PARAM 0xc24f
2382 #define mmVGT_TF_MEMORY_BASE 0xc250
2383 #define mmVGT_GS_INSTANCE_CNT 0xa2e4
2384 #define mmIA_MULTI_VGT_PARAM 0xa2aa
2385 #define mmVGT_VS_MAX_WAVE_ID 0x2268
2386 #define mmVGT_ESGS_RING_SIZE 0xc240
2387 #define mmVGT_GSVS_RING_SIZE 0xc241
2388 #define mmVGT_GSVS_RING_OFFSET_1 0xa298
2389 #define mmVGT_GSVS_RING_OFFSET_2 0xa299
2390 #define mmVGT_GSVS_RING_OFFSET_3 0xa29a
2391 #define mmVGT_ESGS_RING_ITEMSIZE 0xa2ab
2392 #define mmVGT_GSVS_RING_ITEMSIZE 0xa2ac
2393 #define mmVGT_GS_VERT_ITEMSIZE 0xa2d7
2394 #define mmVGT_GS_VERT_ITEMSIZE_1 0xa2d8
2395 #define mmVGT_GS_VERT_ITEMSIZE_2 0xa2d9
2396 #define mmVGT_GS_VERT_ITEMSIZE_3 0xa2da
2397 #define mmWD_CNTL_STATUS 0x223f
2398 #define mmWD_ENHANCE 0xa2a0
2399 #define mmGFX_PIPE_CONTROL 0x226d
2400 #define mmGFX_PIPE_PRIORITY 0xf87f
2401 #define mmCGTT_VGT_CLK_CTRL 0xf084
2402 #define mmCGTT_IA_CLK_CTRL 0xf085
2403 #define mmCGTT_WD_CLK_CTRL 0xf086
2404 #define mmVGT_DEBUG_CNTL 0x2238
2405 #define mmVGT_DEBUG_DATA 0x2239
2406 #define mmIA_DEBUG_CNTL 0x223a
2407 #define mmIA_DEBUG_DATA 0x223b
2408 #define mmVGT_CNTL_STATUS 0x223c
2409 #define mmWD_DEBUG_CNTL 0x223d
2410 #define mmWD_DEBUG_DATA 0x223e
2411 #define mmCC_GC_PRIM_CONFIG 0x2240
2412 #define mmGC_USER_PRIM_CONFIG 0x2241
2413 #define ixWD_DEBUG_REG0 0x0
2414 #define ixWD_DEBUG_REG1 0x1
2415 #define ixWD_DEBUG_REG2 0x2
2416 #define ixWD_DEBUG_REG3 0x3
2417 #define ixWD_DEBUG_REG4 0x4
2418 #define ixWD_DEBUG_REG5 0x5
2419 #define ixIA_DEBUG_REG0 0x0
2420 #define ixIA_DEBUG_REG1 0x1
2421 #define ixIA_DEBUG_REG2 0x2
2422 #define ixIA_DEBUG_REG3 0x3
2423 #define ixIA_DEBUG_REG4 0x4
2424 #define ixIA_DEBUG_REG5 0x5
2425 #define ixIA_DEBUG_REG6 0x6
2426 #define ixIA_DEBUG_REG7 0x7
2427 #define ixIA_DEBUG_REG8 0x8
2428 #define ixIA_DEBUG_REG9 0x9
2429 #define ixVGT_DEBUG_REG0 0x0
2430 #define ixVGT_DEBUG_REG1 0x1
2431 #define ixVGT_DEBUG_REG2 0x1e
2432 #define ixVGT_DEBUG_REG3 0x1f
2433 #define ixVGT_DEBUG_REG4 0x20
2434 #define ixVGT_DEBUG_REG5 0x21
2435 #define ixVGT_DEBUG_REG6 0x22
2436 #define ixVGT_DEBUG_REG7 0x23
2437 #define ixVGT_DEBUG_REG8 0x8
2438 #define ixVGT_DEBUG_REG9 0x9
2439 #define ixVGT_DEBUG_REG10 0xa
2440 #define ixVGT_DEBUG_REG11 0xb
2441 #define ixVGT_DEBUG_REG12 0xc
2442 #define ixVGT_DEBUG_REG13 0xd
2443 #define ixVGT_DEBUG_REG14 0xe
2444 #define ixVGT_DEBUG_REG15 0xf
2445 #define ixVGT_DEBUG_REG16 0x10
2446 #define ixVGT_DEBUG_REG17 0x11
2447 #define ixVGT_DEBUG_REG18 0x7
2448 #define ixVGT_DEBUG_REG19 0x13
2449 #define ixVGT_DEBUG_REG20 0x14
2450 #define ixVGT_DEBUG_REG21 0x15
2451 #define ixVGT_DEBUG_REG22 0x16
2452 #define ixVGT_DEBUG_REG23 0x17
2453 #define ixVGT_DEBUG_REG24 0x18
2454 #define ixVGT_DEBUG_REG25 0x19
2455 #define ixVGT_DEBUG_REG26 0x24
2456 #define ixVGT_DEBUG_REG27 0x1b
2457 #define ixVGT_DEBUG_REG28 0x1c
2458 #define ixVGT_DEBUG_REG29 0x1d
2459 #define ixVGT_DEBUG_REG30 0x25
2460 #define ixVGT_DEBUG_REG31 0x26
2461 #define ixVGT_DEBUG_REG32 0x27
2462 #define ixVGT_DEBUG_REG33 0x28
2463 #define ixVGT_DEBUG_REG34 0x29
2464 #define ixVGT_DEBUG_REG35 0x2a
2465 #define mmVGT_PERFCOUNTER_SEID_MASK 0xd894
2466 #define mmVGT_PERFCOUNTER0_SELECT 0xd88c
2467 #define mmVGT_PERFCOUNTER1_SELECT 0xd88d
2468 #define mmVGT_PERFCOUNTER2_SELECT 0xd88e
2469 #define mmVGT_PERFCOUNTER3_SELECT 0xd88f
2470 #define mmVGT_PERFCOUNTER0_SELECT1 0xd890
2471 #define mmVGT_PERFCOUNTER1_SELECT1 0xd891
2472 #define mmVGT_PERFCOUNTER0_LO 0xd090
2473 #define mmVGT_PERFCOUNTER1_LO 0xd092
2474 #define mmVGT_PERFCOUNTER2_LO 0xd094
2475 #define mmVGT_PERFCOUNTER3_LO 0xd096
2476 #define mmVGT_PERFCOUNTER0_HI 0xd091
2477 #define mmVGT_PERFCOUNTER1_HI 0xd093
2478 #define mmVGT_PERFCOUNTER2_HI 0xd095
2479 #define mmVGT_PERFCOUNTER3_HI 0xd097
2480 #define mmIA_PERFCOUNTER0_SELECT 0xd884
2481 #define mmIA_PERFCOUNTER1_SELECT 0xd885
2482 #define mmIA_PERFCOUNTER2_SELECT 0xd886
2483 #define mmIA_PERFCOUNTER3_SELECT 0xd887
2484 #define mmIA_PERFCOUNTER0_SELECT1 0xd888
2485 #define mmIA_PERFCOUNTER0_LO 0xd088
2486 #define mmIA_PERFCOUNTER1_LO 0xd08a
2487 #define mmIA_PERFCOUNTER2_LO 0xd08c
2488 #define mmIA_PERFCOUNTER3_LO 0xd08e
2489 #define mmIA_PERFCOUNTER0_HI 0xd089
2490 #define mmIA_PERFCOUNTER1_HI 0xd08b
2491 #define mmIA_PERFCOUNTER2_HI 0xd08d
2492 #define mmIA_PERFCOUNTER3_HI 0xd08f
2493 #define mmWD_PERFCOUNTER0_SELECT 0xd880
2494 #define mmWD_PERFCOUNTER1_SELECT 0xd881
2495 #define mmWD_PERFCOUNTER2_SELECT 0xd882
2496 #define mmWD_PERFCOUNTER3_SELECT 0xd883
2497 #define mmWD_PERFCOUNTER0_LO 0xd080
2498 #define mmWD_PERFCOUNTER1_LO 0xd082
2499 #define mmWD_PERFCOUNTER2_LO 0xd084
2500 #define mmWD_PERFCOUNTER3_LO 0xd086
2501 #define mmWD_PERFCOUNTER0_HI 0xd081
2502 #define mmWD_PERFCOUNTER1_HI 0xd083
2503 #define mmWD_PERFCOUNTER2_HI 0xd085
2504 #define mmWD_PERFCOUNTER3_HI 0xd087
2505 #define mmDIDT_IND_INDEX 0x3280
2506 #define mmDIDT_IND_DATA 0x3281
2507 #define ixDIDT_SQ_CTRL0 0x0
2508 #define ixDIDT_SQ_CTRL1 0x1
2509 #define ixDIDT_SQ_CTRL2 0x2
2510 #define ixDIDT_SQ_WEIGHT0_3 0x10
2511 #define ixDIDT_SQ_WEIGHT4_7 0x11
2512 #define ixDIDT_SQ_WEIGHT8_11 0x12
2513 #define ixDIDT_DB_CTRL0 0x20
2514 #define ixDIDT_DB_CTRL1 0x21
2515 #define ixDIDT_DB_CTRL2 0x22
2516 #define ixDIDT_DB_WEIGHT0_3 0x30
2517 #define ixDIDT_DB_WEIGHT4_7 0x31
2518 #define ixDIDT_DB_WEIGHT8_11 0x32
2519 #define ixDIDT_TD_CTRL0 0x40
2520 #define ixDIDT_TD_CTRL1 0x41
2521 #define ixDIDT_TD_CTRL2 0x42
2522 #define ixDIDT_TD_WEIGHT0_3 0x50
2523 #define ixDIDT_TD_WEIGHT4_7 0x51
2524 #define ixDIDT_TD_WEIGHT8_11 0x52
2525 #define ixDIDT_TCP_CTRL0 0x60
2526 #define ixDIDT_TCP_CTRL1 0x61
2527 #define ixDIDT_TCP_CTRL2 0x62
2528 #define ixDIDT_TCP_WEIGHT0_3 0x70
2529 #define ixDIDT_TCP_WEIGHT4_7 0x71
2530 #define ixDIDT_TCP_WEIGHT8_11 0x72
2531
2532 #endif