drivers/gpu/drm/amd/include/asic_reg/athub/athub_1_0

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   1 /*
   2  * Copyright (C) 2017  Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  */
  21 #ifndef _athub_1_0_OFFSET_HEADER
  22 #define _athub_1_0_OFFSET_HEADER
  23 
  24 
  25 
  26 // addressBlock: athub_atsdec
  27 // base address:        0x3080
  28 #define mmATC_ATS_CNTL  0x0000
  29 #define mmATC_ATS_CNTL_BASE_IDX 0
  30 #define mmATC_ATS_STATUS        0x0003
  31 #define mmATC_ATS_STATUS_BASE_IDX       0
  32 #define mmATC_ATS_FAULT_CNTL    0x0004
  33 #define mmATC_ATS_FAULT_CNTL_BASE_IDX   0
  34 #define mmATC_ATS_FAULT_STATUS_INFO     0x0005
  35 #define mmATC_ATS_FAULT_STATUS_INFO_BASE_IDX    0
  36 #define mmATC_ATS_FAULT_STATUS_ADDR     0x0006
  37 #define mmATC_ATS_FAULT_STATUS_ADDR_BASE_IDX    0
  38 #define mmATC_ATS_DEFAULT_PAGE_LOW      0x0007
  39 #define mmATC_ATS_DEFAULT_PAGE_LOW_BASE_IDX     0
  40 #define mmATC_TRANS_FAULT_RSPCNTRL      0x0008
  41 #define mmATC_TRANS_FAULT_RSPCNTRL_BASE_IDX     0
  42 #define mmATC_ATS_FAULT_STATUS_INFO2    0x0009
  43 #define mmATC_ATS_FAULT_STATUS_INFO2_BASE_IDX   0
  44 #define mmATHUB_MISC_CNTL       0x000a
  45 #define mmATHUB_MISC_CNTL_BASE_IDX      0
  46 #define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS  0x000b
  47 #define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS_BASE_IDX 0
  48 #define mmATC_VMID0_PASID_MAPPING       0x000c
  49 #define mmATC_VMID0_PASID_MAPPING_BASE_IDX      0
  50 #define mmATC_VMID1_PASID_MAPPING       0x000d
  51 #define mmATC_VMID1_PASID_MAPPING_BASE_IDX      0
  52 #define mmATC_VMID2_PASID_MAPPING       0x000e
  53 #define mmATC_VMID2_PASID_MAPPING_BASE_IDX      0
  54 #define mmATC_VMID3_PASID_MAPPING       0x000f
  55 #define mmATC_VMID3_PASID_MAPPING_BASE_IDX      0
  56 #define mmATC_VMID4_PASID_MAPPING       0x0010
  57 #define mmATC_VMID4_PASID_MAPPING_BASE_IDX      0
  58 #define mmATC_VMID5_PASID_MAPPING       0x0011
  59 #define mmATC_VMID5_PASID_MAPPING_BASE_IDX      0
  60 #define mmATC_VMID6_PASID_MAPPING       0x0012
  61 #define mmATC_VMID6_PASID_MAPPING_BASE_IDX      0
  62 #define mmATC_VMID7_PASID_MAPPING       0x0013
  63 #define mmATC_VMID7_PASID_MAPPING_BASE_IDX      0
  64 #define mmATC_VMID8_PASID_MAPPING       0x0014
  65 #define mmATC_VMID8_PASID_MAPPING_BASE_IDX      0
  66 #define mmATC_VMID9_PASID_MAPPING       0x0015
  67 #define mmATC_VMID9_PASID_MAPPING_BASE_IDX      0
  68 #define mmATC_VMID10_PASID_MAPPING      0x0016
  69 #define mmATC_VMID10_PASID_MAPPING_BASE_IDX     0
  70 #define mmATC_VMID11_PASID_MAPPING      0x0017
  71 #define mmATC_VMID11_PASID_MAPPING_BASE_IDX     0
  72 #define mmATC_VMID12_PASID_MAPPING      0x0018
  73 #define mmATC_VMID12_PASID_MAPPING_BASE_IDX     0
  74 #define mmATC_VMID13_PASID_MAPPING      0x0019
  75 #define mmATC_VMID13_PASID_MAPPING_BASE_IDX     0
  76 #define mmATC_VMID14_PASID_MAPPING      0x001a
  77 #define mmATC_VMID14_PASID_MAPPING_BASE_IDX     0
  78 #define mmATC_VMID15_PASID_MAPPING      0x001b
  79 #define mmATC_VMID15_PASID_MAPPING_BASE_IDX     0
  80 #define mmATC_ATS_VMID_STATUS   0x001c
  81 #define mmATC_ATS_VMID_STATUS_BASE_IDX  0
  82 #define mmATC_ATS_GFX_ATCL2_STATUS      0x001d
  83 #define mmATC_ATS_GFX_ATCL2_STATUS_BASE_IDX     0
  84 #define mmATC_PERFCOUNTER0_CFG  0x001e
  85 #define mmATC_PERFCOUNTER0_CFG_BASE_IDX 0
  86 #define mmATC_PERFCOUNTER1_CFG  0x001f
  87 #define mmATC_PERFCOUNTER1_CFG_BASE_IDX 0
  88 #define mmATC_PERFCOUNTER2_CFG  0x0020
  89 #define mmATC_PERFCOUNTER2_CFG_BASE_IDX 0
  90 #define mmATC_PERFCOUNTER3_CFG  0x0021
  91 #define mmATC_PERFCOUNTER3_CFG_BASE_IDX 0
  92 #define mmATC_PERFCOUNTER_RSLT_CNTL     0x0022
  93 #define mmATC_PERFCOUNTER_RSLT_CNTL_BASE_IDX    0
  94 #define mmATC_PERFCOUNTER_LO    0x0023
  95 #define mmATC_PERFCOUNTER_LO_BASE_IDX   0
  96 #define mmATC_PERFCOUNTER_HI    0x0024
  97 #define mmATC_PERFCOUNTER_HI_BASE_IDX   0
  98 #define mmATHUB_PCIE_ATS_CNTL   0x0025
  99 #define mmATHUB_PCIE_ATS_CNTL_BASE_IDX  0
 100 #define mmATHUB_PCIE_PASID_CNTL 0x0026
 101 #define mmATHUB_PCIE_PASID_CNTL_BASE_IDX        0
 102 #define mmATHUB_PCIE_PAGE_REQ_CNTL      0x0027
 103 #define mmATHUB_PCIE_PAGE_REQ_CNTL_BASE_IDX     0
 104 #define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC    0x0028
 105 #define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC_BASE_IDX   0
 106 #define mmATHUB_COMMAND 0x0029
 107 #define mmATHUB_COMMAND_BASE_IDX        0
 108 #define mmATHUB_PCIE_ATS_CNTL_VF_0      0x002a
 109 #define mmATHUB_PCIE_ATS_CNTL_VF_0_BASE_IDX     0
 110 #define mmATHUB_PCIE_ATS_CNTL_VF_1      0x002b
 111 #define mmATHUB_PCIE_ATS_CNTL_VF_1_BASE_IDX     0
 112 #define mmATHUB_PCIE_ATS_CNTL_VF_2      0x002c
 113 #define mmATHUB_PCIE_ATS_CNTL_VF_2_BASE_IDX     0
 114 #define mmATHUB_PCIE_ATS_CNTL_VF_3      0x002d
 115 #define mmATHUB_PCIE_ATS_CNTL_VF_3_BASE_IDX     0
 116 #define mmATHUB_PCIE_ATS_CNTL_VF_4      0x002e
 117 #define mmATHUB_PCIE_ATS_CNTL_VF_4_BASE_IDX     0
 118 #define mmATHUB_PCIE_ATS_CNTL_VF_5      0x002f
 119 #define mmATHUB_PCIE_ATS_CNTL_VF_5_BASE_IDX     0
 120 #define mmATHUB_PCIE_ATS_CNTL_VF_6      0x0030
 121 #define mmATHUB_PCIE_ATS_CNTL_VF_6_BASE_IDX     0
 122 #define mmATHUB_PCIE_ATS_CNTL_VF_7      0x0031
 123 #define mmATHUB_PCIE_ATS_CNTL_VF_7_BASE_IDX     0
 124 #define mmATHUB_PCIE_ATS_CNTL_VF_8      0x0032
 125 #define mmATHUB_PCIE_ATS_CNTL_VF_8_BASE_IDX     0
 126 #define mmATHUB_PCIE_ATS_CNTL_VF_9      0x0033
 127 #define mmATHUB_PCIE_ATS_CNTL_VF_9_BASE_IDX     0
 128 #define mmATHUB_PCIE_ATS_CNTL_VF_10     0x0034
 129 #define mmATHUB_PCIE_ATS_CNTL_VF_10_BASE_IDX    0
 130 #define mmATHUB_PCIE_ATS_CNTL_VF_11     0x0035
 131 #define mmATHUB_PCIE_ATS_CNTL_VF_11_BASE_IDX    0
 132 #define mmATHUB_PCIE_ATS_CNTL_VF_12     0x0036
 133 #define mmATHUB_PCIE_ATS_CNTL_VF_12_BASE_IDX    0
 134 #define mmATHUB_PCIE_ATS_CNTL_VF_13     0x0037
 135 #define mmATHUB_PCIE_ATS_CNTL_VF_13_BASE_IDX    0
 136 #define mmATHUB_PCIE_ATS_CNTL_VF_14     0x0038
 137 #define mmATHUB_PCIE_ATS_CNTL_VF_14_BASE_IDX    0
 138 #define mmATHUB_PCIE_ATS_CNTL_VF_15     0x0039
 139 #define mmATHUB_PCIE_ATS_CNTL_VF_15_BASE_IDX    0
 140 #define mmATHUB_MEM_POWER_LS    0x003a
 141 #define mmATHUB_MEM_POWER_LS_BASE_IDX   0
 142 #define mmATS_IH_CREDIT 0x003b
 143 #define mmATS_IH_CREDIT_BASE_IDX        0
 144 #define mmATHUB_IH_CREDIT       0x003c
 145 #define mmATHUB_IH_CREDIT_BASE_IDX      0
 146 #define mmATC_VMID16_PASID_MAPPING      0x003d
 147 #define mmATC_VMID16_PASID_MAPPING_BASE_IDX     0
 148 #define mmATC_VMID17_PASID_MAPPING      0x003e
 149 #define mmATC_VMID17_PASID_MAPPING_BASE_IDX     0
 150 #define mmATC_VMID18_PASID_MAPPING      0x003f
 151 #define mmATC_VMID18_PASID_MAPPING_BASE_IDX     0
 152 #define mmATC_VMID19_PASID_MAPPING      0x0040
 153 #define mmATC_VMID19_PASID_MAPPING_BASE_IDX     0
 154 #define mmATC_VMID20_PASID_MAPPING      0x0041
 155 #define mmATC_VMID20_PASID_MAPPING_BASE_IDX     0
 156 #define mmATC_VMID21_PASID_MAPPING      0x0042
 157 #define mmATC_VMID21_PASID_MAPPING_BASE_IDX     0
 158 #define mmATC_VMID22_PASID_MAPPING      0x0043
 159 #define mmATC_VMID22_PASID_MAPPING_BASE_IDX     0
 160 #define mmATC_VMID23_PASID_MAPPING      0x0044
 161 #define mmATC_VMID23_PASID_MAPPING_BASE_IDX     0
 162 #define mmATC_VMID24_PASID_MAPPING      0x0045
 163 #define mmATC_VMID24_PASID_MAPPING_BASE_IDX     0
 164 #define mmATC_VMID25_PASID_MAPPING      0x0046
 165 #define mmATC_VMID25_PASID_MAPPING_BASE_IDX     0
 166 #define mmATC_VMID26_PASID_MAPPING      0x0047
 167 #define mmATC_VMID26_PASID_MAPPING_BASE_IDX     0
 168 #define mmATC_VMID27_PASID_MAPPING      0x0048
 169 #define mmATC_VMID27_PASID_MAPPING_BASE_IDX     0
 170 #define mmATC_VMID28_PASID_MAPPING      0x0049
 171 #define mmATC_VMID28_PASID_MAPPING_BASE_IDX     0
 172 #define mmATC_VMID29_PASID_MAPPING      0x004a
 173 #define mmATC_VMID29_PASID_MAPPING_BASE_IDX     0
 174 #define mmATC_VMID30_PASID_MAPPING      0x004b
 175 #define mmATC_VMID30_PASID_MAPPING_BASE_IDX     0
 176 #define mmATC_VMID31_PASID_MAPPING      0x004c
 177 #define mmATC_VMID31_PASID_MAPPING_BASE_IDX     0
 178 #define mmATC_ATS_MMHUB_ATCL2_STATUS    0x004d
 179 #define mmATC_ATS_MMHUB_ATCL2_STATUS_BASE_IDX   0
 180 #define mmATHUB_SHARED_VIRT_RESET_REQ   0x004e
 181 #define mmATHUB_SHARED_VIRT_RESET_REQ_BASE_IDX  0
 182 #define mmATHUB_SHARED_ACTIVE_FCN_ID    0x004f
 183 #define mmATHUB_SHARED_ACTIVE_FCN_ID_BASE_IDX   0
 184 #define mmATC_ATS_SDPPORT_CNTL  0x0050
 185 #define mmATC_ATS_SDPPORT_CNTL_BASE_IDX 0
 186 #define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT        0x0052
 187 #define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT_BASE_IDX       0
 188 #define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT      0x0053
 189 #define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT_BASE_IDX     0
 190 
 191 
 192 // addressBlock: athub_xpbdec
 193 // base address:        0x31f0
 194 #define mmXPB_RTR_SRC_APRTR0    0x005c
 195 #define mmXPB_RTR_SRC_APRTR0_BASE_IDX   0
 196 #define mmXPB_RTR_SRC_APRTR1    0x005d
 197 #define mmXPB_RTR_SRC_APRTR1_BASE_IDX   0
 198 #define mmXPB_RTR_SRC_APRTR2    0x005e
 199 #define mmXPB_RTR_SRC_APRTR2_BASE_IDX   0
 200 #define mmXPB_RTR_SRC_APRTR3    0x005f
 201 #define mmXPB_RTR_SRC_APRTR3_BASE_IDX   0
 202 #define mmXPB_RTR_SRC_APRTR4    0x0060
 203 #define mmXPB_RTR_SRC_APRTR4_BASE_IDX   0
 204 #define mmXPB_RTR_SRC_APRTR5    0x0061
 205 #define mmXPB_RTR_SRC_APRTR5_BASE_IDX   0
 206 #define mmXPB_RTR_SRC_APRTR6    0x0062
 207 #define mmXPB_RTR_SRC_APRTR6_BASE_IDX   0
 208 #define mmXPB_RTR_SRC_APRTR7    0x0063
 209 #define mmXPB_RTR_SRC_APRTR7_BASE_IDX   0
 210 #define mmXPB_RTR_SRC_APRTR8    0x0064
 211 #define mmXPB_RTR_SRC_APRTR8_BASE_IDX   0
 212 #define mmXPB_RTR_SRC_APRTR9    0x0065
 213 #define mmXPB_RTR_SRC_APRTR9_BASE_IDX   0
 214 #define mmXPB_XDMA_RTR_SRC_APRTR0       0x0066
 215 #define mmXPB_XDMA_RTR_SRC_APRTR0_BASE_IDX      0
 216 #define mmXPB_XDMA_RTR_SRC_APRTR1       0x0067
 217 #define mmXPB_XDMA_RTR_SRC_APRTR1_BASE_IDX      0
 218 #define mmXPB_XDMA_RTR_SRC_APRTR2       0x0068
 219 #define mmXPB_XDMA_RTR_SRC_APRTR2_BASE_IDX      0
 220 #define mmXPB_XDMA_RTR_SRC_APRTR3       0x0069
 221 #define mmXPB_XDMA_RTR_SRC_APRTR3_BASE_IDX      0
 222 #define mmXPB_RTR_DEST_MAP0     0x006a
 223 #define mmXPB_RTR_DEST_MAP0_BASE_IDX    0
 224 #define mmXPB_RTR_DEST_MAP1     0x006b
 225 #define mmXPB_RTR_DEST_MAP1_BASE_IDX    0
 226 #define mmXPB_RTR_DEST_MAP2     0x006c
 227 #define mmXPB_RTR_DEST_MAP2_BASE_IDX    0
 228 #define mmXPB_RTR_DEST_MAP3     0x006d
 229 #define mmXPB_RTR_DEST_MAP3_BASE_IDX    0
 230 #define mmXPB_RTR_DEST_MAP4     0x006e
 231 #define mmXPB_RTR_DEST_MAP4_BASE_IDX    0
 232 #define mmXPB_RTR_DEST_MAP5     0x006f
 233 #define mmXPB_RTR_DEST_MAP5_BASE_IDX    0
 234 #define mmXPB_RTR_DEST_MAP6     0x0070
 235 #define mmXPB_RTR_DEST_MAP6_BASE_IDX    0
 236 #define mmXPB_RTR_DEST_MAP7     0x0071
 237 #define mmXPB_RTR_DEST_MAP7_BASE_IDX    0
 238 #define mmXPB_RTR_DEST_MAP8     0x0072
 239 #define mmXPB_RTR_DEST_MAP8_BASE_IDX    0
 240 #define mmXPB_RTR_DEST_MAP9     0x0073
 241 #define mmXPB_RTR_DEST_MAP9_BASE_IDX    0
 242 #define mmXPB_XDMA_RTR_DEST_MAP0        0x0074
 243 #define mmXPB_XDMA_RTR_DEST_MAP0_BASE_IDX       0
 244 #define mmXPB_XDMA_RTR_DEST_MAP1        0x0075
 245 #define mmXPB_XDMA_RTR_DEST_MAP1_BASE_IDX       0
 246 #define mmXPB_XDMA_RTR_DEST_MAP2        0x0076
 247 #define mmXPB_XDMA_RTR_DEST_MAP2_BASE_IDX       0
 248 #define mmXPB_XDMA_RTR_DEST_MAP3        0x0077
 249 #define mmXPB_XDMA_RTR_DEST_MAP3_BASE_IDX       0
 250 #define mmXPB_CLG_CFG0  0x0078
 251 #define mmXPB_CLG_CFG0_BASE_IDX 0
 252 #define mmXPB_CLG_CFG1  0x0079
 253 #define mmXPB_CLG_CFG1_BASE_IDX 0
 254 #define mmXPB_CLG_CFG2  0x007a
 255 #define mmXPB_CLG_CFG2_BASE_IDX 0
 256 #define mmXPB_CLG_CFG3  0x007b
 257 #define mmXPB_CLG_CFG3_BASE_IDX 0
 258 #define mmXPB_CLG_CFG4  0x007c
 259 #define mmXPB_CLG_CFG4_BASE_IDX 0
 260 #define mmXPB_CLG_CFG5  0x007d
 261 #define mmXPB_CLG_CFG5_BASE_IDX 0
 262 #define mmXPB_CLG_CFG6  0x007e
 263 #define mmXPB_CLG_CFG6_BASE_IDX 0
 264 #define mmXPB_CLG_CFG7  0x007f
 265 #define mmXPB_CLG_CFG7_BASE_IDX 0
 266 #define mmXPB_CLG_EXTRA 0x0080
 267 #define mmXPB_CLG_EXTRA_BASE_IDX        0
 268 #define mmXPB_CLG_EXTRA_MSK     0x0081
 269 #define mmXPB_CLG_EXTRA_MSK_BASE_IDX    0
 270 #define mmXPB_LB_ADDR   0x0082
 271 #define mmXPB_LB_ADDR_BASE_IDX  0
 272 #define mmXPB_WCB_STS   0x0083
 273 #define mmXPB_WCB_STS_BASE_IDX  0
 274 #define mmXPB_HST_CFG   0x0084
 275 #define mmXPB_HST_CFG_BASE_IDX  0
 276 #define mmXPB_P2P_BAR_CFG       0x0085
 277 #define mmXPB_P2P_BAR_CFG_BASE_IDX      0
 278 #define mmXPB_P2P_BAR0  0x0086
 279 #define mmXPB_P2P_BAR0_BASE_IDX 0
 280 #define mmXPB_P2P_BAR1  0x0087
 281 #define mmXPB_P2P_BAR1_BASE_IDX 0
 282 #define mmXPB_P2P_BAR2  0x0088
 283 #define mmXPB_P2P_BAR2_BASE_IDX 0
 284 #define mmXPB_P2P_BAR3  0x0089
 285 #define mmXPB_P2P_BAR3_BASE_IDX 0
 286 #define mmXPB_P2P_BAR4  0x008a
 287 #define mmXPB_P2P_BAR4_BASE_IDX 0
 288 #define mmXPB_P2P_BAR5  0x008b
 289 #define mmXPB_P2P_BAR5_BASE_IDX 0
 290 #define mmXPB_P2P_BAR6  0x008c
 291 #define mmXPB_P2P_BAR6_BASE_IDX 0
 292 #define mmXPB_P2P_BAR7  0x008d
 293 #define mmXPB_P2P_BAR7_BASE_IDX 0
 294 #define mmXPB_P2P_BAR_SETUP     0x008e
 295 #define mmXPB_P2P_BAR_SETUP_BASE_IDX    0
 296 #define mmXPB_P2P_BAR_DELTA_ABOVE       0x0090
 297 #define mmXPB_P2P_BAR_DELTA_ABOVE_BASE_IDX      0
 298 #define mmXPB_P2P_BAR_DELTA_BELOW       0x0091
 299 #define mmXPB_P2P_BAR_DELTA_BELOW_BASE_IDX      0
 300 #define mmXPB_PEER_SYS_BAR0     0x0092
 301 #define mmXPB_PEER_SYS_BAR0_BASE_IDX    0
 302 #define mmXPB_PEER_SYS_BAR1     0x0093
 303 #define mmXPB_PEER_SYS_BAR1_BASE_IDX    0
 304 #define mmXPB_PEER_SYS_BAR2     0x0094
 305 #define mmXPB_PEER_SYS_BAR2_BASE_IDX    0
 306 #define mmXPB_PEER_SYS_BAR3     0x0095
 307 #define mmXPB_PEER_SYS_BAR3_BASE_IDX    0
 308 #define mmXPB_PEER_SYS_BAR4     0x0096
 309 #define mmXPB_PEER_SYS_BAR4_BASE_IDX    0
 310 #define mmXPB_PEER_SYS_BAR5     0x0097
 311 #define mmXPB_PEER_SYS_BAR5_BASE_IDX    0
 312 #define mmXPB_PEER_SYS_BAR6     0x0098
 313 #define mmXPB_PEER_SYS_BAR6_BASE_IDX    0
 314 #define mmXPB_PEER_SYS_BAR7     0x0099
 315 #define mmXPB_PEER_SYS_BAR7_BASE_IDX    0
 316 #define mmXPB_PEER_SYS_BAR8     0x009a
 317 #define mmXPB_PEER_SYS_BAR8_BASE_IDX    0
 318 #define mmXPB_PEER_SYS_BAR9     0x009b
 319 #define mmXPB_PEER_SYS_BAR9_BASE_IDX    0
 320 #define mmXPB_XDMA_PEER_SYS_BAR0        0x009c
 321 #define mmXPB_XDMA_PEER_SYS_BAR0_BASE_IDX       0
 322 #define mmXPB_XDMA_PEER_SYS_BAR1        0x009d
 323 #define mmXPB_XDMA_PEER_SYS_BAR1_BASE_IDX       0
 324 #define mmXPB_XDMA_PEER_SYS_BAR2        0x009e
 325 #define mmXPB_XDMA_PEER_SYS_BAR2_BASE_IDX       0
 326 #define mmXPB_XDMA_PEER_SYS_BAR3        0x009f
 327 #define mmXPB_XDMA_PEER_SYS_BAR3_BASE_IDX       0
 328 #define mmXPB_CLK_GAT   0x00a0
 329 #define mmXPB_CLK_GAT_BASE_IDX  0
 330 #define mmXPB_INTF_CFG  0x00a1
 331 #define mmXPB_INTF_CFG_BASE_IDX 0
 332 #define mmXPB_INTF_STS  0x00a2
 333 #define mmXPB_INTF_STS_BASE_IDX 0
 334 #define mmXPB_PIPE_STS  0x00a3
 335 #define mmXPB_PIPE_STS_BASE_IDX 0
 336 #define mmXPB_SUB_CTRL  0x00a4
 337 #define mmXPB_SUB_CTRL_BASE_IDX 0
 338 #define mmXPB_MAP_INVERT_FLUSH_NUM_LSB  0x00a5
 339 #define mmXPB_MAP_INVERT_FLUSH_NUM_LSB_BASE_IDX 0
 340 #define mmXPB_PERF_KNOBS        0x00a6
 341 #define mmXPB_PERF_KNOBS_BASE_IDX       0
 342 #define mmXPB_STICKY    0x00a7
 343 #define mmXPB_STICKY_BASE_IDX   0
 344 #define mmXPB_STICKY_W1C        0x00a8
 345 #define mmXPB_STICKY_W1C_BASE_IDX       0
 346 #define mmXPB_MISC_CFG  0x00a9
 347 #define mmXPB_MISC_CFG_BASE_IDX 0
 348 #define mmXPB_INTF_CFG2 0x00aa
 349 #define mmXPB_INTF_CFG2_BASE_IDX        0
 350 #define mmXPB_CLG_EXTRA_RD      0x00ab
 351 #define mmXPB_CLG_EXTRA_RD_BASE_IDX     0
 352 #define mmXPB_CLG_EXTRA_MSK_RD  0x00ac
 353 #define mmXPB_CLG_EXTRA_MSK_RD_BASE_IDX 0
 354 #define mmXPB_CLG_GFX_MATCH     0x00ad
 355 #define mmXPB_CLG_GFX_MATCH_BASE_IDX    0
 356 #define mmXPB_CLG_GFX_MATCH_MSK 0x00ae
 357 #define mmXPB_CLG_GFX_MATCH_MSK_BASE_IDX        0
 358 #define mmXPB_CLG_MM_MATCH      0x00af
 359 #define mmXPB_CLG_MM_MATCH_BASE_IDX     0
 360 #define mmXPB_CLG_MM_MATCH_MSK  0x00b0
 361 #define mmXPB_CLG_MM_MATCH_MSK_BASE_IDX 0
 362 #define mmXPB_CLG_GFX_UNITID_MAPPING0   0x00b1
 363 #define mmXPB_CLG_GFX_UNITID_MAPPING0_BASE_IDX  0
 364 #define mmXPB_CLG_GFX_UNITID_MAPPING1   0x00b2
 365 #define mmXPB_CLG_GFX_UNITID_MAPPING1_BASE_IDX  0
 366 #define mmXPB_CLG_GFX_UNITID_MAPPING2   0x00b3
 367 #define mmXPB_CLG_GFX_UNITID_MAPPING2_BASE_IDX  0
 368 #define mmXPB_CLG_GFX_UNITID_MAPPING3   0x00b4
 369 #define mmXPB_CLG_GFX_UNITID_MAPPING3_BASE_IDX  0
 370 #define mmXPB_CLG_GFX_UNITID_MAPPING4   0x00b5
 371 #define mmXPB_CLG_GFX_UNITID_MAPPING4_BASE_IDX  0
 372 #define mmXPB_CLG_GFX_UNITID_MAPPING5   0x00b6
 373 #define mmXPB_CLG_GFX_UNITID_MAPPING5_BASE_IDX  0
 374 #define mmXPB_CLG_GFX_UNITID_MAPPING6   0x00b7
 375 #define mmXPB_CLG_GFX_UNITID_MAPPING6_BASE_IDX  0
 376 #define mmXPB_CLG_GFX_UNITID_MAPPING7   0x00b8
 377 #define mmXPB_CLG_GFX_UNITID_MAPPING7_BASE_IDX  0
 378 #define mmXPB_CLG_MM_UNITID_MAPPING0    0x00b9
 379 #define mmXPB_CLG_MM_UNITID_MAPPING0_BASE_IDX   0
 380 #define mmXPB_CLG_MM_UNITID_MAPPING1    0x00ba
 381 #define mmXPB_CLG_MM_UNITID_MAPPING1_BASE_IDX   0
 382 #define mmXPB_CLG_MM_UNITID_MAPPING2    0x00bb
 383 #define mmXPB_CLG_MM_UNITID_MAPPING2_BASE_IDX   0
 384 #define mmXPB_CLG_MM_UNITID_MAPPING3    0x00bc
 385 #define mmXPB_CLG_MM_UNITID_MAPPING3_BASE_IDX   0
 386 
 387 
 388 // addressBlock: athub_rpbdec
 389 // base address:        0x33b0
 390 #define mmRPB_PASSPW_CONF       0x00cc
 391 #define mmRPB_PASSPW_CONF_BASE_IDX      0
 392 #define mmRPB_BLOCKLEVEL_CONF   0x00cd
 393 #define mmRPB_BLOCKLEVEL_CONF_BASE_IDX  0
 394 #define mmRPB_TAG_CONF  0x00cf
 395 #define mmRPB_TAG_CONF_BASE_IDX 0
 396 #define mmRPB_EFF_CNTL  0x00d1
 397 #define mmRPB_EFF_CNTL_BASE_IDX 0
 398 #define mmRPB_ARB_CNTL  0x00d2
 399 #define mmRPB_ARB_CNTL_BASE_IDX 0
 400 #define mmRPB_ARB_CNTL2 0x00d3
 401 #define mmRPB_ARB_CNTL2_BASE_IDX        0
 402 #define mmRPB_BIF_CNTL  0x00d4
 403 #define mmRPB_BIF_CNTL_BASE_IDX 0
 404 #define mmRPB_WR_SWITCH_CNTL    0x00d5
 405 #define mmRPB_WR_SWITCH_CNTL_BASE_IDX   0
 406 #define mmRPB_RD_SWITCH_CNTL    0x00d7
 407 #define mmRPB_RD_SWITCH_CNTL_BASE_IDX   0
 408 #define mmRPB_CID_QUEUE_WR      0x00d8
 409 #define mmRPB_CID_QUEUE_WR_BASE_IDX     0
 410 #define mmRPB_CID_QUEUE_RD      0x00d9
 411 #define mmRPB_CID_QUEUE_RD_BASE_IDX     0
 412 #define mmRPB_CID_QUEUE_EX      0x00dc
 413 #define mmRPB_CID_QUEUE_EX_BASE_IDX     0
 414 #define mmRPB_CID_QUEUE_EX_DATA 0x00dd
 415 #define mmRPB_CID_QUEUE_EX_DATA_BASE_IDX        0
 416 #define mmRPB_SWITCH_CNTL2      0x00de
 417 #define mmRPB_SWITCH_CNTL2_BASE_IDX     0
 418 #define mmRPB_DEINTRLV_COMBINE_CNTL     0x00df
 419 #define mmRPB_DEINTRLV_COMBINE_CNTL_BASE_IDX    0
 420 #define mmRPB_VC_SWITCH_RDWR    0x00e0
 421 #define mmRPB_VC_SWITCH_RDWR_BASE_IDX   0
 422 #define mmRPB_PERFCOUNTER_LO    0x00e1
 423 #define mmRPB_PERFCOUNTER_LO_BASE_IDX   0
 424 #define mmRPB_PERFCOUNTER_HI    0x00e2
 425 #define mmRPB_PERFCOUNTER_HI_BASE_IDX   0
 426 #define mmRPB_PERFCOUNTER0_CFG  0x00e3
 427 #define mmRPB_PERFCOUNTER0_CFG_BASE_IDX 0
 428 #define mmRPB_PERFCOUNTER1_CFG  0x00e4
 429 #define mmRPB_PERFCOUNTER1_CFG_BASE_IDX 0
 430 #define mmRPB_PERFCOUNTER2_CFG  0x00e5
 431 #define mmRPB_PERFCOUNTER2_CFG_BASE_IDX 0
 432 #define mmRPB_PERFCOUNTER3_CFG  0x00e6
 433 #define mmRPB_PERFCOUNTER3_CFG_BASE_IDX 0
 434 #define mmRPB_PERFCOUNTER_RSLT_CNTL     0x00e7
 435 #define mmRPB_PERFCOUNTER_RSLT_CNTL_BASE_IDX    0
 436 #define mmRPB_RD_QUEUE_CNTL     0x00e9
 437 #define mmRPB_RD_QUEUE_CNTL_BASE_IDX    0
 438 #define mmRPB_RD_QUEUE_CNTL2    0x00ea
 439 #define mmRPB_RD_QUEUE_CNTL2_BASE_IDX   0
 440 #define mmRPB_WR_QUEUE_CNTL     0x00eb
 441 #define mmRPB_WR_QUEUE_CNTL_BASE_IDX    0
 442 #define mmRPB_WR_QUEUE_CNTL2    0x00ec
 443 #define mmRPB_WR_QUEUE_CNTL2_BASE_IDX   0
 444 #define mmRPB_EA_QUEUE_WR       0x00ed
 445 #define mmRPB_EA_QUEUE_WR_BASE_IDX      0
 446 #define mmRPB_ATS_CNTL  0x00ee
 447 #define mmRPB_ATS_CNTL_BASE_IDX 0
 448 #define mmRPB_ATS_CNTL2 0x00ef
 449 #define mmRPB_ATS_CNTL2_BASE_IDX        0
 450 #define mmRPB_SDPPORT_CNTL      0x00f0
 451 #define mmRPB_SDPPORT_CNTL_BASE_IDX     0
 452 
 453 #endif
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/amd/include/asic_reg/athub/athub_1_0_offset.h

INCLUDED FROM
