root/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_offset.h

INCLUDED FROM

   1 /*
   2  * Copyright (C) 2019  Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  */
  21 #ifndef _nbio_2_3_OFFSET_HEADER
  22 #define _nbio_2_3_OFFSET_HEADER
  23 
  24 
  25 
  26 // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC
  27 // base address: 0x0
  28 #define mmBIF_BX_PF_MM_INDEX                                                                           0x0000
  29 #define mmBIF_BX_PF_MM_INDEX_BASE_IDX                                                                  0
  30 #define mmBIF_BX_PF_MM_DATA                                                                            0x0001
  31 #define mmBIF_BX_PF_MM_DATA_BASE_IDX                                                                   0
  32 #define mmBIF_BX_PF_MM_INDEX_HI                                                                        0x0006
  33 #define mmBIF_BX_PF_MM_INDEX_HI_BASE_IDX                                                               0
  34 
  35 
  36 // addressBlock: nbio_nbif0_bif_bx_SYSDEC
  37 // base address: 0x0
  38 #define mmSYSHUB_INDEX_OVLP                                                                            0x0008
  39 #define mmSYSHUB_INDEX_OVLP_BASE_IDX                                                                   0
  40 #define mmSYSHUB_DATA_OVLP                                                                             0x0009
  41 #define mmSYSHUB_DATA_OVLP_BASE_IDX                                                                    0
  42 #define mmPCIE_INDEX                                                                                   0x000c
  43 #define mmPCIE_INDEX_BASE_IDX                                                                          0
  44 #define mmPCIE_DATA                                                                                    0x000d
  45 #define mmPCIE_DATA_BASE_IDX                                                                           0
  46 #define mmPCIE_INDEX2                                                                                  0x000e
  47 #define mmPCIE_INDEX2_BASE_IDX                                                                         0
  48 #define mmPCIE_DATA2                                                                                   0x000f
  49 #define mmPCIE_DATA2_BASE_IDX                                                                          0
  50 #define mmSBIOS_SCRATCH_0                                                                              0x0034
  51 #define mmSBIOS_SCRATCH_0_BASE_IDX                                                                     1
  52 #define mmSBIOS_SCRATCH_1                                                                              0x0035
  53 #define mmSBIOS_SCRATCH_1_BASE_IDX                                                                     1
  54 #define mmSBIOS_SCRATCH_2                                                                              0x0036
  55 #define mmSBIOS_SCRATCH_2_BASE_IDX                                                                     1
  56 #define mmSBIOS_SCRATCH_3                                                                              0x0037
  57 #define mmSBIOS_SCRATCH_3_BASE_IDX                                                                     1
  58 #define mmBIOS_SCRATCH_0                                                                               0x0038
  59 #define mmBIOS_SCRATCH_0_BASE_IDX                                                                      1
  60 #define mmBIOS_SCRATCH_1                                                                               0x0039
  61 #define mmBIOS_SCRATCH_1_BASE_IDX                                                                      1
  62 #define mmBIOS_SCRATCH_2                                                                               0x003a
  63 #define mmBIOS_SCRATCH_2_BASE_IDX                                                                      1
  64 #define mmBIOS_SCRATCH_3                                                                               0x003b
  65 #define mmBIOS_SCRATCH_3_BASE_IDX                                                                      1
  66 #define mmBIOS_SCRATCH_4                                                                               0x003c
  67 #define mmBIOS_SCRATCH_4_BASE_IDX                                                                      1
  68 #define mmBIOS_SCRATCH_5                                                                               0x003d
  69 #define mmBIOS_SCRATCH_5_BASE_IDX                                                                      1
  70 #define mmBIOS_SCRATCH_6                                                                               0x003e
  71 #define mmBIOS_SCRATCH_6_BASE_IDX                                                                      1
  72 #define mmBIOS_SCRATCH_7                                                                               0x003f
  73 #define mmBIOS_SCRATCH_7_BASE_IDX                                                                      1
  74 #define mmBIOS_SCRATCH_8                                                                               0x0040
  75 #define mmBIOS_SCRATCH_8_BASE_IDX                                                                      1
  76 #define mmBIOS_SCRATCH_9                                                                               0x0041
  77 #define mmBIOS_SCRATCH_9_BASE_IDX                                                                      1
  78 #define mmBIOS_SCRATCH_10                                                                              0x0042
  79 #define mmBIOS_SCRATCH_10_BASE_IDX                                                                     1
  80 #define mmBIOS_SCRATCH_11                                                                              0x0043
  81 #define mmBIOS_SCRATCH_11_BASE_IDX                                                                     1
  82 #define mmBIOS_SCRATCH_12                                                                              0x0044
  83 #define mmBIOS_SCRATCH_12_BASE_IDX                                                                     1
  84 #define mmBIOS_SCRATCH_13                                                                              0x0045
  85 #define mmBIOS_SCRATCH_13_BASE_IDX                                                                     1
  86 #define mmBIOS_SCRATCH_14                                                                              0x0046
  87 #define mmBIOS_SCRATCH_14_BASE_IDX                                                                     1
  88 #define mmBIOS_SCRATCH_15                                                                              0x0047
  89 #define mmBIOS_SCRATCH_15_BASE_IDX                                                                     1
  90 #define mmBIF_RLC_INTR_CNTL                                                                            0x004c
  91 #define mmBIF_RLC_INTR_CNTL_BASE_IDX                                                                   1
  92 #define mmBIF_VCE_INTR_CNTL                                                                            0x004d
  93 #define mmBIF_VCE_INTR_CNTL_BASE_IDX                                                                   1
  94 #define mmBIF_UVD_INTR_CNTL                                                                            0x004e
  95 #define mmBIF_UVD_INTR_CNTL_BASE_IDX                                                                   1
  96 #define mmGFX_MMIOREG_CAM_ADDR0                                                                        0x006c
  97 #define mmGFX_MMIOREG_CAM_ADDR0_BASE_IDX                                                               1
  98 #define mmGFX_MMIOREG_CAM_REMAP_ADDR0                                                                  0x006d
  99 #define mmGFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX                                                         1
 100 #define mmGFX_MMIOREG_CAM_ADDR1                                                                        0x006e
 101 #define mmGFX_MMIOREG_CAM_ADDR1_BASE_IDX                                                               1
 102 #define mmGFX_MMIOREG_CAM_REMAP_ADDR1                                                                  0x006f
 103 #define mmGFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX                                                         1
 104 #define mmGFX_MMIOREG_CAM_ADDR2                                                                        0x0070
 105 #define mmGFX_MMIOREG_CAM_ADDR2_BASE_IDX                                                               1
 106 #define mmGFX_MMIOREG_CAM_REMAP_ADDR2                                                                  0x0071
 107 #define mmGFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX                                                         1
 108 #define mmGFX_MMIOREG_CAM_ADDR3                                                                        0x0072
 109 #define mmGFX_MMIOREG_CAM_ADDR3_BASE_IDX                                                               1
 110 #define mmGFX_MMIOREG_CAM_REMAP_ADDR3                                                                  0x0073
 111 #define mmGFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX                                                         1
 112 #define mmGFX_MMIOREG_CAM_ADDR4                                                                        0x0074
 113 #define mmGFX_MMIOREG_CAM_ADDR4_BASE_IDX                                                               1
 114 #define mmGFX_MMIOREG_CAM_REMAP_ADDR4                                                                  0x0075
 115 #define mmGFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX                                                         1
 116 #define mmGFX_MMIOREG_CAM_ADDR5                                                                        0x0076
 117 #define mmGFX_MMIOREG_CAM_ADDR5_BASE_IDX                                                               1
 118 #define mmGFX_MMIOREG_CAM_REMAP_ADDR5                                                                  0x0077
 119 #define mmGFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX                                                         1
 120 #define mmGFX_MMIOREG_CAM_ADDR6                                                                        0x0078
 121 #define mmGFX_MMIOREG_CAM_ADDR6_BASE_IDX                                                               1
 122 #define mmGFX_MMIOREG_CAM_REMAP_ADDR6                                                                  0x0079
 123 #define mmGFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX                                                         1
 124 #define mmGFX_MMIOREG_CAM_ADDR7                                                                        0x007a
 125 #define mmGFX_MMIOREG_CAM_ADDR7_BASE_IDX                                                               1
 126 #define mmGFX_MMIOREG_CAM_REMAP_ADDR7                                                                  0x007b
 127 #define mmGFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX                                                         1
 128 #define mmGFX_MMIOREG_CAM_CNTL                                                                         0x007c
 129 #define mmGFX_MMIOREG_CAM_CNTL_BASE_IDX                                                                1
 130 #define mmGFX_MMIOREG_CAM_ZERO_CPL                                                                     0x007d
 131 #define mmGFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX                                                            1
 132 #define mmGFX_MMIOREG_CAM_ONE_CPL                                                                      0x007e
 133 #define mmGFX_MMIOREG_CAM_ONE_CPL_BASE_IDX                                                             1
 134 #define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL                                                             0x007f
 135 #define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX                                                    1
 136 
 137 
 138 // addressBlock: nbio_nbif0_syshub_mmreg_syshubdec
 139 // base address: 0x0
 140 #define mmSYSHUB_INDEX                                                                                 0x0008
 141 #define mmSYSHUB_INDEX_BASE_IDX                                                                        0
 142 #define mmSYSHUB_DATA                                                                                  0x0009
 143 #define mmSYSHUB_DATA_BASE_IDX                                                                         0
 144 
 145 
 146 // addressBlock: nbio_nbif0_rcc_strap_BIFDEC1
 147 // base address: 0x0
 148 #define mmRCC_BIF_STRAP0                                                                               0x0000
 149 #define mmRCC_BIF_STRAP0_BASE_IDX                                                                      2
 150 #define mmRCC_BIF_STRAP1                                                                               0x0001
 151 #define mmRCC_BIF_STRAP1_BASE_IDX                                                                      2
 152 #define mmRCC_BIF_STRAP2                                                                               0x0002
 153 #define mmRCC_BIF_STRAP2_BASE_IDX                                                                      2
 154 #define mmRCC_BIF_STRAP3                                                                               0x0003
 155 #define mmRCC_BIF_STRAP3_BASE_IDX                                                                      2
 156 #define mmRCC_BIF_STRAP4                                                                               0x0004
 157 #define mmRCC_BIF_STRAP4_BASE_IDX                                                                      2
 158 #define mmRCC_BIF_STRAP5                                                                               0x0005
 159 #define mmRCC_BIF_STRAP5_BASE_IDX                                                                      2
 160 #define mmRCC_BIF_STRAP6                                                                               0x0006
 161 #define mmRCC_BIF_STRAP6_BASE_IDX                                                                      2
 162 #define mmRCC_DEV0_PORT_STRAP0                                                                         0x0007
 163 #define mmRCC_DEV0_PORT_STRAP0_BASE_IDX                                                                2
 164 #define mmRCC_DEV0_PORT_STRAP1                                                                         0x0008
 165 #define mmRCC_DEV0_PORT_STRAP1_BASE_IDX                                                                2
 166 #define mmRCC_DEV0_PORT_STRAP2                                                                         0x0009
 167 #define mmRCC_DEV0_PORT_STRAP2_BASE_IDX                                                                2
 168 #define mmRCC_DEV0_PORT_STRAP3                                                                         0x000a
 169 #define mmRCC_DEV0_PORT_STRAP3_BASE_IDX                                                                2
 170 #define mmRCC_DEV0_PORT_STRAP4                                                                         0x000b
 171 #define mmRCC_DEV0_PORT_STRAP4_BASE_IDX                                                                2
 172 #define mmRCC_DEV0_PORT_STRAP5                                                                         0x000c
 173 #define mmRCC_DEV0_PORT_STRAP5_BASE_IDX                                                                2
 174 #define mmRCC_DEV0_PORT_STRAP6                                                                         0x000d
 175 #define mmRCC_DEV0_PORT_STRAP6_BASE_IDX                                                                2
 176 #define mmRCC_DEV0_PORT_STRAP7                                                                         0x000e
 177 #define mmRCC_DEV0_PORT_STRAP7_BASE_IDX                                                                2
 178 #define mmRCC_DEV0_PORT_STRAP8                                                                         0x000f
 179 #define mmRCC_DEV0_PORT_STRAP8_BASE_IDX                                                                2
 180 #define mmRCC_DEV0_PORT_STRAP9                                                                         0x0010
 181 #define mmRCC_DEV0_PORT_STRAP9_BASE_IDX                                                                2
 182 #define mmRCC_DEV0_EPF0_STRAP0                                                                         0x0011
 183 #define mmRCC_DEV0_EPF0_STRAP0_BASE_IDX                                                                2
 184 #define mmRCC_DEV0_EPF0_STRAP1                                                                         0x0012
 185 #define mmRCC_DEV0_EPF0_STRAP1_BASE_IDX                                                                2
 186 #define mmRCC_DEV0_EPF0_STRAP13                                                                        0x0013
 187 #define mmRCC_DEV0_EPF0_STRAP13_BASE_IDX                                                               2
 188 #define mmRCC_DEV0_EPF0_STRAP2                                                                         0x0014
 189 #define mmRCC_DEV0_EPF0_STRAP2_BASE_IDX                                                                2
 190 #define mmRCC_DEV0_EPF0_STRAP3                                                                         0x0015
 191 #define mmRCC_DEV0_EPF0_STRAP3_BASE_IDX                                                                2
 192 #define mmRCC_DEV0_EPF0_STRAP4                                                                         0x0016
 193 #define mmRCC_DEV0_EPF0_STRAP4_BASE_IDX                                                                2
 194 #define mmRCC_DEV0_EPF0_STRAP5                                                                         0x0017
 195 #define mmRCC_DEV0_EPF0_STRAP5_BASE_IDX                                                                2
 196 #define mmRCC_DEV0_EPF0_STRAP8                                                                         0x0018
 197 #define mmRCC_DEV0_EPF0_STRAP8_BASE_IDX                                                                2
 198 #define mmRCC_DEV0_EPF0_STRAP9                                                                         0x0019
 199 #define mmRCC_DEV0_EPF0_STRAP9_BASE_IDX                                                                2
 200 #define mmRCC_DEV0_EPF1_STRAP0                                                                         0x001a
 201 #define mmRCC_DEV0_EPF1_STRAP0_BASE_IDX                                                                2
 202 #define mmRCC_DEV0_EPF1_STRAP10                                                                        0x001b
 203 #define mmRCC_DEV0_EPF1_STRAP10_BASE_IDX                                                               2
 204 #define mmRCC_DEV0_EPF1_STRAP11                                                                        0x001c
 205 #define mmRCC_DEV0_EPF1_STRAP11_BASE_IDX                                                               2
 206 #define mmRCC_DEV0_EPF1_STRAP12                                                                        0x001d
 207 #define mmRCC_DEV0_EPF1_STRAP12_BASE_IDX                                                               2
 208 #define mmRCC_DEV0_EPF1_STRAP13                                                                        0x001e
 209 #define mmRCC_DEV0_EPF1_STRAP13_BASE_IDX                                                               2
 210 #define mmRCC_DEV0_EPF1_STRAP2                                                                         0x001f
 211 #define mmRCC_DEV0_EPF1_STRAP2_BASE_IDX                                                                2
 212 #define mmRCC_DEV0_EPF1_STRAP3                                                                         0x0020
 213 #define mmRCC_DEV0_EPF1_STRAP3_BASE_IDX                                                                2
 214 #define mmRCC_DEV0_EPF1_STRAP4                                                                         0x0021
 215 #define mmRCC_DEV0_EPF1_STRAP4_BASE_IDX                                                                2
 216 #define mmRCC_DEV0_EPF1_STRAP5                                                                         0x0022
 217 #define mmRCC_DEV0_EPF1_STRAP5_BASE_IDX                                                                2
 218 #define mmRCC_DEV0_EPF1_STRAP6                                                                         0x0023
 219 #define mmRCC_DEV0_EPF1_STRAP6_BASE_IDX                                                                2
 220 #define mmRCC_DEV0_EPF1_STRAP7                                                                         0x0024
 221 #define mmRCC_DEV0_EPF1_STRAP7_BASE_IDX                                                                2
 222 
 223 
 224 // addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1
 225 // base address: 0x0
 226 #define mmEP_PCIE_SCRATCH                                                                              0x0025
 227 #define mmEP_PCIE_SCRATCH_BASE_IDX                                                                     2
 228 #define mmEP_PCIE_CNTL                                                                                 0x0027
 229 #define mmEP_PCIE_CNTL_BASE_IDX                                                                        2
 230 #define mmEP_PCIE_INT_CNTL                                                                             0x0028
 231 #define mmEP_PCIE_INT_CNTL_BASE_IDX                                                                    2
 232 #define mmEP_PCIE_INT_STATUS                                                                           0x0029
 233 #define mmEP_PCIE_INT_STATUS_BASE_IDX                                                                  2
 234 #define mmEP_PCIE_RX_CNTL2                                                                             0x002a
 235 #define mmEP_PCIE_RX_CNTL2_BASE_IDX                                                                    2
 236 #define mmEP_PCIE_BUS_CNTL                                                                             0x002b
 237 #define mmEP_PCIE_BUS_CNTL_BASE_IDX                                                                    2
 238 #define mmEP_PCIE_CFG_CNTL                                                                             0x002c
 239 #define mmEP_PCIE_CFG_CNTL_BASE_IDX                                                                    2
 240 #define mmEP_PCIE_TX_LTR_CNTL                                                                          0x002e
 241 #define mmEP_PCIE_TX_LTR_CNTL_BASE_IDX                                                                 2
 242 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0                                                             0x002f
 243 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                                    2
 244 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1                                                             0x002f
 245 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                                    2
 246 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2                                                             0x002f
 247 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                                    2
 248 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3                                                             0x002f
 249 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                                    2
 250 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4                                                             0x0030
 251 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                                    2
 252 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5                                                             0x0030
 253 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                                    2
 254 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6                                                             0x0030
 255 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                                    2
 256 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7                                                             0x0030
 257 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                                    2
 258 #define mmEP_PCIE_STRAP_MISC                                                                           0x0031
 259 #define mmEP_PCIE_STRAP_MISC_BASE_IDX                                                                  2
 260 #define mmEP_PCIE_STRAP_MISC2                                                                          0x0032
 261 #define mmEP_PCIE_STRAP_MISC2_BASE_IDX                                                                 2
 262 #define mmEP_PCIE_F0_DPA_CAP                                                                           0x0034
 263 #define mmEP_PCIE_F0_DPA_CAP_BASE_IDX                                                                  2
 264 #define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR                                                             0x0035
 265 #define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX                                                    2
 266 #define mmEP_PCIE_F0_DPA_CNTL                                                                          0x0035
 267 #define mmEP_PCIE_F0_DPA_CNTL_BASE_IDX                                                                 2
 268 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0                                                             0x0035
 269 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                                    2
 270 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1                                                             0x0036
 271 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                                    2
 272 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2                                                             0x0036
 273 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                                    2
 274 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3                                                             0x0036
 275 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                                    2
 276 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4                                                             0x0036
 277 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                                    2
 278 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5                                                             0x0037
 279 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                                    2
 280 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6                                                             0x0037
 281 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                                    2
 282 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7                                                             0x0037
 283 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                                    2
 284 #define mmEP_PCIE_PME_CONTROL                                                                          0x0037
 285 #define mmEP_PCIE_PME_CONTROL_BASE_IDX                                                                 2
 286 #define mmEP_PCIEP_RESERVED                                                                            0x0038
 287 #define mmEP_PCIEP_RESERVED_BASE_IDX                                                                   2
 288 #define mmEP_PCIE_TX_CNTL                                                                              0x003a
 289 #define mmEP_PCIE_TX_CNTL_BASE_IDX                                                                     2
 290 #define mmEP_PCIE_TX_REQUESTER_ID                                                                      0x003b
 291 #define mmEP_PCIE_TX_REQUESTER_ID_BASE_IDX                                                             2
 292 #define mmEP_PCIE_ERR_CNTL                                                                             0x003c
 293 #define mmEP_PCIE_ERR_CNTL_BASE_IDX                                                                    2
 294 #define mmEP_PCIE_RX_CNTL                                                                              0x003d
 295 #define mmEP_PCIE_RX_CNTL_BASE_IDX                                                                     2
 296 #define mmEP_PCIE_LC_SPEED_CNTL                                                                        0x003e
 297 #define mmEP_PCIE_LC_SPEED_CNTL_BASE_IDX                                                               2
 298 
 299 
 300 // addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1
 301 // base address: 0x0
 302 #define mmDN_PCIE_RESERVED                                                                             0x0040
 303 #define mmDN_PCIE_RESERVED_BASE_IDX                                                                    2
 304 #define mmDN_PCIE_SCRATCH                                                                              0x0041
 305 #define mmDN_PCIE_SCRATCH_BASE_IDX                                                                     2
 306 #define mmDN_PCIE_CNTL                                                                                 0x0043
 307 #define mmDN_PCIE_CNTL_BASE_IDX                                                                        2
 308 #define mmDN_PCIE_CONFIG_CNTL                                                                          0x0044
 309 #define mmDN_PCIE_CONFIG_CNTL_BASE_IDX                                                                 2
 310 #define mmDN_PCIE_RX_CNTL2                                                                             0x0045
 311 #define mmDN_PCIE_RX_CNTL2_BASE_IDX                                                                    2
 312 #define mmDN_PCIE_BUS_CNTL                                                                             0x0046
 313 #define mmDN_PCIE_BUS_CNTL_BASE_IDX                                                                    2
 314 #define mmDN_PCIE_CFG_CNTL                                                                             0x0047
 315 #define mmDN_PCIE_CFG_CNTL_BASE_IDX                                                                    2
 316 #define mmDN_PCIE_STRAP_F0                                                                             0x0048
 317 #define mmDN_PCIE_STRAP_F0_BASE_IDX                                                                    2
 318 #define mmDN_PCIE_STRAP_MISC                                                                           0x0049
 319 #define mmDN_PCIE_STRAP_MISC_BASE_IDX                                                                  2
 320 #define mmDN_PCIE_STRAP_MISC2                                                                          0x004a
 321 #define mmDN_PCIE_STRAP_MISC2_BASE_IDX                                                                 2
 322 
 323 
 324 // addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1
 325 // base address: 0x0
 326 #define mmPCIE_ERR_CNTL                                                                                0x004f
 327 #define mmPCIE_ERR_CNTL_BASE_IDX                                                                       2
 328 #define mmPCIE_RX_CNTL                                                                                 0x0050
 329 #define mmPCIE_RX_CNTL_BASE_IDX                                                                        2
 330 #define mmPCIE_LC_SPEED_CNTL                                                                           0x0051
 331 #define mmPCIE_LC_SPEED_CNTL_BASE_IDX                                                                  2
 332 #define mmPCIE_LC_CNTL2                                                                                0x0052
 333 #define mmPCIE_LC_CNTL2_BASE_IDX                                                                       2
 334 #define mmPCIEP_STRAP_MISC                                                                             0x0053
 335 #define mmPCIEP_STRAP_MISC_BASE_IDX                                                                    2
 336 #define mmLTR_MSG_INFO_FROM_EP                                                                         0x0054
 337 #define mmLTR_MSG_INFO_FROM_EP_BASE_IDX                                                                2
 338 
 339 
 340 // addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1[13440..14975]
 341 // base address: 0x3480
 342 #define mmRCC_DEV0_EPF0_RCC_ERR_LOG                                                                    0x0085
 343 #define mmRCC_DEV0_EPF0_RCC_ERR_LOG_BASE_IDX                                                           2
 344 #define mmRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN                                                           0x00c0
 345 #define mmRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN_BASE_IDX                                                  2
 346 #define mmRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE                                                             0x00c3
 347 #define mmRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE_BASE_IDX                                                    2
 348 #define mmRCC_DEV0_EPF0_RCC_CONFIG_RESERVED                                                            0x00c4
 349 #define mmRCC_DEV0_EPF0_RCC_CONFIG_RESERVED_BASE_IDX                                                   2
 350 #define mmRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER                                                        0x00c5
 351 #define mmRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                               2
 352 
 353 
 354 // addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1
 355 // base address: 0x0
 356 #define mmRCC_ERR_INT_CNTL                                                                             0x0086
 357 #define mmRCC_ERR_INT_CNTL_BASE_IDX                                                                    2
 358 #define mmRCC_BACO_CNTL_MISC                                                                           0x0087
 359 #define mmRCC_BACO_CNTL_MISC_BASE_IDX                                                                  2
 360 #define mmRCC_RESET_EN                                                                                 0x0088
 361 #define mmRCC_RESET_EN_BASE_IDX                                                                        2
 362 #define mmRCC_VDM_SUPPORT                                                                              0x0089
 363 #define mmRCC_VDM_SUPPORT_BASE_IDX                                                                     2
 364 #define mmRCC_MARGIN_PARAM_CNTL0                                                                       0x008a
 365 #define mmRCC_MARGIN_PARAM_CNTL0_BASE_IDX                                                              2
 366 #define mmRCC_MARGIN_PARAM_CNTL1                                                                       0x008b
 367 #define mmRCC_MARGIN_PARAM_CNTL1_BASE_IDX                                                              2
 368 #define mmRCC_GPUIOV_REGION                                                                            0x008c
 369 #define mmRCC_GPUIOV_REGION_BASE_IDX                                                                   2
 370 #define mmRCC_PEER_REG_RANGE0                                                                          0x00be
 371 #define mmRCC_PEER_REG_RANGE0_BASE_IDX                                                                 2
 372 #define mmRCC_PEER_REG_RANGE1                                                                          0x00bf
 373 #define mmRCC_PEER_REG_RANGE1_BASE_IDX                                                                 2
 374 #define mmRCC_BUS_CNTL                                                                                 0x00c1
 375 #define mmRCC_BUS_CNTL_BASE_IDX                                                                        2
 376 #define mmRCC_CONFIG_CNTL                                                                              0x00c2
 377 #define mmRCC_CONFIG_CNTL_BASE_IDX                                                                     2
 378 #define mmRCC_CONFIG_F0_BASE                                                                           0x00c6
 379 #define mmRCC_CONFIG_F0_BASE_BASE_IDX                                                                  2
 380 #define mmRCC_CONFIG_APER_SIZE                                                                         0x00c7
 381 #define mmRCC_CONFIG_APER_SIZE_BASE_IDX                                                                2
 382 #define mmRCC_CONFIG_REG_APER_SIZE                                                                     0x00c8
 383 #define mmRCC_CONFIG_REG_APER_SIZE_BASE_IDX                                                            2
 384 #define mmRCC_XDMA_LO                                                                                  0x00c9
 385 #define mmRCC_XDMA_LO_BASE_IDX                                                                         2
 386 #define mmRCC_XDMA_HI                                                                                  0x00ca
 387 #define mmRCC_XDMA_HI_BASE_IDX                                                                         2
 388 #define mmRCC_FEATURES_CONTROL_MISC                                                                    0x00cb
 389 #define mmRCC_FEATURES_CONTROL_MISC_BASE_IDX                                                           2
 390 #define mmRCC_BUSNUM_CNTL1                                                                             0x00cc
 391 #define mmRCC_BUSNUM_CNTL1_BASE_IDX                                                                    2
 392 #define mmRCC_BUSNUM_LIST0                                                                             0x00cd
 393 #define mmRCC_BUSNUM_LIST0_BASE_IDX                                                                    2
 394 #define mmRCC_BUSNUM_LIST1                                                                             0x00ce
 395 #define mmRCC_BUSNUM_LIST1_BASE_IDX                                                                    2
 396 #define mmRCC_BUSNUM_CNTL2                                                                             0x00cf
 397 #define mmRCC_BUSNUM_CNTL2_BASE_IDX                                                                    2
 398 #define mmRCC_CAPTURE_HOST_BUSNUM                                                                      0x00d0
 399 #define mmRCC_CAPTURE_HOST_BUSNUM_BASE_IDX                                                             2
 400 #define mmRCC_HOST_BUSNUM                                                                              0x00d1
 401 #define mmRCC_HOST_BUSNUM_BASE_IDX                                                                     2
 402 #define mmRCC_PEER0_FB_OFFSET_HI                                                                       0x00d2
 403 #define mmRCC_PEER0_FB_OFFSET_HI_BASE_IDX                                                              2
 404 #define mmRCC_PEER0_FB_OFFSET_LO                                                                       0x00d3
 405 #define mmRCC_PEER0_FB_OFFSET_LO_BASE_IDX                                                              2
 406 #define mmRCC_PEER1_FB_OFFSET_HI                                                                       0x00d4
 407 #define mmRCC_PEER1_FB_OFFSET_HI_BASE_IDX                                                              2
 408 #define mmRCC_PEER1_FB_OFFSET_LO                                                                       0x00d5
 409 #define mmRCC_PEER1_FB_OFFSET_LO_BASE_IDX                                                              2
 410 #define mmRCC_PEER2_FB_OFFSET_HI                                                                       0x00d6
 411 #define mmRCC_PEER2_FB_OFFSET_HI_BASE_IDX                                                              2
 412 #define mmRCC_PEER2_FB_OFFSET_LO                                                                       0x00d7
 413 #define mmRCC_PEER2_FB_OFFSET_LO_BASE_IDX                                                              2
 414 #define mmRCC_PEER3_FB_OFFSET_HI                                                                       0x00d8
 415 #define mmRCC_PEER3_FB_OFFSET_HI_BASE_IDX                                                              2
 416 #define mmRCC_PEER3_FB_OFFSET_LO                                                                       0x00d9
 417 #define mmRCC_PEER3_FB_OFFSET_LO_BASE_IDX                                                              2
 418 #define mmRCC_DEVFUNCNUM_LIST0                                                                         0x00da
 419 #define mmRCC_DEVFUNCNUM_LIST0_BASE_IDX                                                                2
 420 #define mmRCC_DEVFUNCNUM_LIST1                                                                         0x00db
 421 #define mmRCC_DEVFUNCNUM_LIST1_BASE_IDX                                                                2
 422 #define mmRCC_DEV0_LINK_CNTL                                                                           0x00dd
 423 #define mmRCC_DEV0_LINK_CNTL_BASE_IDX                                                                  2
 424 #define mmRCC_CMN_LINK_CNTL                                                                            0x00de
 425 #define mmRCC_CMN_LINK_CNTL_BASE_IDX                                                                   2
 426 #define mmRCC_EP_REQUESTERID_RESTORE                                                                   0x00df
 427 #define mmRCC_EP_REQUESTERID_RESTORE_BASE_IDX                                                          2
 428 #define mmRCC_LTR_LSWITCH_CNTL                                                                         0x00e0
 429 #define mmRCC_LTR_LSWITCH_CNTL_BASE_IDX                                                                2
 430 #define mmRCC_MH_ARB_CNTL                                                                              0x00e1
 431 #define mmRCC_MH_ARB_CNTL_BASE_IDX                                                                     2
 432 
 433 
 434 // addressBlock: nbio_nbif0_bif_bx_BIFDEC1
 435 // base address: 0x0
 436 #define mmCC_BIF_BX_STRAP0                                                                             0x00e2
 437 #define mmCC_BIF_BX_STRAP0_BASE_IDX                                                                    2
 438 #define mmCC_BIF_BX_PINSTRAP0                                                                          0x00e4
 439 #define mmCC_BIF_BX_PINSTRAP0_BASE_IDX                                                                 2
 440 #define mmBIF_MM_INDACCESS_CNTL                                                                        0x00e6
 441 #define mmBIF_MM_INDACCESS_CNTL_BASE_IDX                                                               2
 442 #define mmBUS_CNTL                                                                                     0x00e7
 443 #define mmBUS_CNTL_BASE_IDX                                                                            2
 444 #define mmBIF_SCRATCH0                                                                                 0x00e8
 445 #define mmBIF_SCRATCH0_BASE_IDX                                                                        2
 446 #define mmBIF_SCRATCH1                                                                                 0x00e9
 447 #define mmBIF_SCRATCH1_BASE_IDX                                                                        2
 448 #define mmBX_RESET_EN                                                                                  0x00ed
 449 #define mmBX_RESET_EN_BASE_IDX                                                                         2
 450 #define mmMM_CFGREGS_CNTL                                                                              0x00ee
 451 #define mmMM_CFGREGS_CNTL_BASE_IDX                                                                     2
 452 #define mmBX_RESET_CNTL                                                                                0x00f0
 453 #define mmBX_RESET_CNTL_BASE_IDX                                                                       2
 454 #define mmINTERRUPT_CNTL                                                                               0x00f1
 455 #define mmINTERRUPT_CNTL_BASE_IDX                                                                      2
 456 #define mmINTERRUPT_CNTL2                                                                              0x00f2
 457 #define mmINTERRUPT_CNTL2_BASE_IDX                                                                     2
 458 #define mmCLKREQB_PAD_CNTL                                                                             0x00f8
 459 #define mmCLKREQB_PAD_CNTL_BASE_IDX                                                                    2
 460 #define mmBIF_FEATURES_CONTROL_MISC                                                                    0x00fb
 461 #define mmBIF_FEATURES_CONTROL_MISC_BASE_IDX                                                           2
 462 #define mmBIF_DOORBELL_CNTL                                                                            0x00fc
 463 #define mmBIF_DOORBELL_CNTL_BASE_IDX                                                                   2
 464 #define mmBIF_DOORBELL_INT_CNTL                                                                        0x00fd
 465 #define mmBIF_DOORBELL_INT_CNTL_BASE_IDX                                                               2
 466 #define mmBIF_FB_EN                                                                                    0x00ff
 467 #define mmBIF_FB_EN_BASE_IDX                                                                           2
 468 #define mmBIF_INTR_CNTL                                                                                0x0100
 469 #define mmBIF_INTR_CNTL_BASE_IDX                                                                       2
 470 #define mmBIF_MST_TRANS_PENDING_VF                                                                     0x0109
 471 #define mmBIF_MST_TRANS_PENDING_VF_BASE_IDX                                                            2
 472 #define mmBIF_SLV_TRANS_PENDING_VF                                                                     0x010a
 473 #define mmBIF_SLV_TRANS_PENDING_VF_BASE_IDX                                                            2
 474 #define mmBACO_CNTL                                                                                    0x010b
 475 #define mmBACO_CNTL_BASE_IDX                                                                           2
 476 #define mmBIF_BACO_EXIT_TIME0                                                                          0x010c
 477 #define mmBIF_BACO_EXIT_TIME0_BASE_IDX                                                                 2
 478 #define mmBIF_BACO_EXIT_TIMER1                                                                         0x010d
 479 #define mmBIF_BACO_EXIT_TIMER1_BASE_IDX                                                                2
 480 #define mmBIF_BACO_EXIT_TIMER2                                                                         0x010e
 481 #define mmBIF_BACO_EXIT_TIMER2_BASE_IDX                                                                2
 482 #define mmBIF_BACO_EXIT_TIMER3                                                                         0x010f
 483 #define mmBIF_BACO_EXIT_TIMER3_BASE_IDX                                                                2
 484 #define mmBIF_BACO_EXIT_TIMER4                                                                         0x0110
 485 #define mmBIF_BACO_EXIT_TIMER4_BASE_IDX                                                                2
 486 #define mmMEM_TYPE_CNTL                                                                                0x0111
 487 #define mmMEM_TYPE_CNTL_BASE_IDX                                                                       2
 488 #define mmNBIF_GFX_ADDR_LUT_CNTL                                                                       0x0113
 489 #define mmNBIF_GFX_ADDR_LUT_CNTL_BASE_IDX                                                              2
 490 #define mmNBIF_GFX_ADDR_LUT_0                                                                          0x0114
 491 #define mmNBIF_GFX_ADDR_LUT_0_BASE_IDX                                                                 2
 492 #define mmNBIF_GFX_ADDR_LUT_1                                                                          0x0115
 493 #define mmNBIF_GFX_ADDR_LUT_1_BASE_IDX                                                                 2
 494 #define mmNBIF_GFX_ADDR_LUT_2                                                                          0x0116
 495 #define mmNBIF_GFX_ADDR_LUT_2_BASE_IDX                                                                 2
 496 #define mmNBIF_GFX_ADDR_LUT_3                                                                          0x0117
 497 #define mmNBIF_GFX_ADDR_LUT_3_BASE_IDX                                                                 2
 498 #define mmNBIF_GFX_ADDR_LUT_4                                                                          0x0118
 499 #define mmNBIF_GFX_ADDR_LUT_4_BASE_IDX                                                                 2
 500 #define mmNBIF_GFX_ADDR_LUT_5                                                                          0x0119
 501 #define mmNBIF_GFX_ADDR_LUT_5_BASE_IDX                                                                 2
 502 #define mmNBIF_GFX_ADDR_LUT_6                                                                          0x011a
 503 #define mmNBIF_GFX_ADDR_LUT_6_BASE_IDX                                                                 2
 504 #define mmNBIF_GFX_ADDR_LUT_7                                                                          0x011b
 505 #define mmNBIF_GFX_ADDR_LUT_7_BASE_IDX                                                                 2
 506 #define mmNBIF_GFX_ADDR_LUT_8                                                                          0x011c
 507 #define mmNBIF_GFX_ADDR_LUT_8_BASE_IDX                                                                 2
 508 #define mmNBIF_GFX_ADDR_LUT_9                                                                          0x011d
 509 #define mmNBIF_GFX_ADDR_LUT_9_BASE_IDX                                                                 2
 510 #define mmNBIF_GFX_ADDR_LUT_10                                                                         0x011e
 511 #define mmNBIF_GFX_ADDR_LUT_10_BASE_IDX                                                                2
 512 #define mmNBIF_GFX_ADDR_LUT_11                                                                         0x011f
 513 #define mmNBIF_GFX_ADDR_LUT_11_BASE_IDX                                                                2
 514 #define mmNBIF_GFX_ADDR_LUT_12                                                                         0x0120
 515 #define mmNBIF_GFX_ADDR_LUT_12_BASE_IDX                                                                2
 516 #define mmNBIF_GFX_ADDR_LUT_13                                                                         0x0121
 517 #define mmNBIF_GFX_ADDR_LUT_13_BASE_IDX                                                                2
 518 #define mmNBIF_GFX_ADDR_LUT_14                                                                         0x0122
 519 #define mmNBIF_GFX_ADDR_LUT_14_BASE_IDX                                                                2
 520 #define mmNBIF_GFX_ADDR_LUT_15                                                                         0x0123
 521 #define mmNBIF_GFX_ADDR_LUT_15_BASE_IDX                                                                2
 522 #define mmREMAP_HDP_MEM_FLUSH_CNTL                                                                     0x012d
 523 #define mmREMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX                                                            2
 524 #define mmREMAP_HDP_REG_FLUSH_CNTL                                                                     0x012e
 525 #define mmREMAP_HDP_REG_FLUSH_CNTL_BASE_IDX                                                            2
 526 #define mmBIF_RB_CNTL                                                                                  0x012f
 527 #define mmBIF_RB_CNTL_BASE_IDX                                                                         2
 528 #define mmBIF_RB_BASE                                                                                  0x0130
 529 #define mmBIF_RB_BASE_BASE_IDX                                                                         2
 530 #define mmBIF_RB_RPTR                                                                                  0x0131
 531 #define mmBIF_RB_RPTR_BASE_IDX                                                                         2
 532 #define mmBIF_RB_WPTR                                                                                  0x0132
 533 #define mmBIF_RB_WPTR_BASE_IDX                                                                         2
 534 #define mmBIF_RB_WPTR_ADDR_HI                                                                          0x0133
 535 #define mmBIF_RB_WPTR_ADDR_HI_BASE_IDX                                                                 2
 536 #define mmBIF_RB_WPTR_ADDR_LO                                                                          0x0134
 537 #define mmBIF_RB_WPTR_ADDR_LO_BASE_IDX                                                                 2
 538 #define mmMAILBOX_INDEX                                                                                0x0135
 539 #define mmMAILBOX_INDEX_BASE_IDX                                                                       2
 540 #define mmBIF_MP1_INTR_CTRL                                                                            0x0142
 541 #define mmBIF_MP1_INTR_CTRL_BASE_IDX                                                                   2
 542 #define mmBIF_UVD_GPUIOV_CFG_SIZE                                                                      0x0143
 543 #define mmBIF_UVD_GPUIOV_CFG_SIZE_BASE_IDX                                                             2
 544 #define mmBIF_VCE_GPUIOV_CFG_SIZE                                                                      0x0144
 545 #define mmBIF_VCE_GPUIOV_CFG_SIZE_BASE_IDX                                                             2
 546 #define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE                                                                 0x0145
 547 #define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE_BASE_IDX                                                        2
 548 #define mmBIF_PERSTB_PAD_CNTL                                                                          0x0148
 549 #define mmBIF_PERSTB_PAD_CNTL_BASE_IDX                                                                 2
 550 #define mmBIF_PX_EN_PAD_CNTL                                                                           0x0149
 551 #define mmBIF_PX_EN_PAD_CNTL_BASE_IDX                                                                  2
 552 #define mmBIF_REFPADKIN_PAD_CNTL                                                                       0x014a
 553 #define mmBIF_REFPADKIN_PAD_CNTL_BASE_IDX                                                              2
 554 #define mmBIF_CLKREQB_PAD_CNTL                                                                         0x014b
 555 #define mmBIF_CLKREQB_PAD_CNTL_BASE_IDX                                                                2
 556 #define mmBIF_PWRBRK_PAD_CNTL                                                                          0x014c
 557 #define mmBIF_PWRBRK_PAD_CNTL_BASE_IDX                                                                 2
 558 #define mmBIF_WAKEB_PAD_CNTL                                                                           0x014d
 559 #define mmBIF_WAKEB_PAD_CNTL_BASE_IDX                                                                  2
 560 #define mmBIF_VAUX_PRESENT_PAD_CNTL                                                                    0x014e
 561 #define mmBIF_VAUX_PRESENT_PAD_CNTL_BASE_IDX                                                           2
 562 
 563 
 564 // addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1
 565 // base address: 0x0
 566 #define mmBIF_BX_PF_BIF_BME_STATUS                                                                     0x00eb
 567 #define mmBIF_BX_PF_BIF_BME_STATUS_BASE_IDX                                                            2
 568 #define mmBIF_BX_PF_BIF_ATOMIC_ERR_LOG                                                                 0x00ec
 569 #define mmBIF_BX_PF_BIF_ATOMIC_ERR_LOG_BASE_IDX                                                        2
 570 #define mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                               0x00f3
 571 #define mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                                      2
 572 #define mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                                0x00f4
 573 #define mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                                       2
 574 #define mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL                                                    0x00f5
 575 #define mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                                           2
 576 #define mmBIF_BX_PF_HDP_REG_COHERENCY_FLUSH_CNTL                                                       0x00f6
 577 #define mmBIF_BX_PF_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                              2
 578 #define mmBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL                                                       0x00f7
 579 #define mmBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                              2
 580 #define mmBIF_BX_PF_GPU_HDP_FLUSH_REQ                                                                  0x0106
 581 #define mmBIF_BX_PF_GPU_HDP_FLUSH_REQ_BASE_IDX                                                         2
 582 #define mmBIF_BX_PF_GPU_HDP_FLUSH_DONE                                                                 0x0107
 583 #define mmBIF_BX_PF_GPU_HDP_FLUSH_DONE_BASE_IDX                                                        2
 584 #define mmBIF_BX_PF_BIF_TRANS_PENDING                                                                  0x0108
 585 #define mmBIF_BX_PF_BIF_TRANS_PENDING_BASE_IDX                                                         2
 586 #define mmBIF_BX_PF_NBIF_GFX_ADDR_LUT_BYPASS                                                           0x0112
 587 #define mmBIF_BX_PF_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                                  2
 588 #define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0                                                             0x0136
 589 #define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                                    2
 590 #define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1                                                             0x0137
 591 #define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                                    2
 592 #define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2                                                             0x0138
 593 #define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                                    2
 594 #define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3                                                             0x0139
 595 #define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                                    2
 596 #define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0                                                             0x013a
 597 #define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                                    2
 598 #define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW1                                                             0x013b
 599 #define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                                    2
 600 #define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2                                                             0x013c
 601 #define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                                    2
 602 #define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW3                                                             0x013d
 603 #define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                                    2
 604 #define mmBIF_BX_PF_MAILBOX_CONTROL                                                                    0x013e
 605 #define mmBIF_BX_PF_MAILBOX_CONTROL_BASE_IDX                                                           2
 606 #define mmBIF_BX_PF_MAILBOX_INT_CNTL                                                                   0x013f
 607 #define mmBIF_BX_PF_MAILBOX_INT_CNTL_BASE_IDX                                                          2
 608 #define mmBIF_BX_PF_BIF_VMHV_MAILBOX                                                                   0x0140
 609 #define mmBIF_BX_PF_BIF_VMHV_MAILBOX_BASE_IDX                                                          2
 610 
 611 
 612 // addressBlock: nbio_nbif0_gdc_GDCDEC
 613 // base address: 0x0
 614 #define mmA2S_CNTL_CL0                                                                                 0x0190
 615 #define mmA2S_CNTL_CL0_BASE_IDX                                                                        2
 616 #define mmA2S_CNTL_CL1                                                                                 0x0191
 617 #define mmA2S_CNTL_CL1_BASE_IDX                                                                        2
 618 #define mmA2S_CNTL3_CL0                                                                                0x01a0
 619 #define mmA2S_CNTL3_CL0_BASE_IDX                                                                       2
 620 #define mmA2S_CNTL3_CL1                                                                                0x01a1
 621 #define mmA2S_CNTL3_CL1_BASE_IDX                                                                       2
 622 #define mmA2S_CNTL_SW0                                                                                 0x01b0
 623 #define mmA2S_CNTL_SW0_BASE_IDX                                                                        2
 624 #define mmA2S_CNTL_SW1                                                                                 0x01b1
 625 #define mmA2S_CNTL_SW1_BASE_IDX                                                                        2
 626 #define mmA2S_CNTL_SW2                                                                                 0x01b2
 627 #define mmA2S_CNTL_SW2_BASE_IDX                                                                        2
 628 #define mmA2S_CPLBUF_ALLOC_CNTL                                                                        0x01bc
 629 #define mmA2S_CPLBUF_ALLOC_CNTL_BASE_IDX                                                               2
 630 #define mmA2S_TAG_ALLOC_0                                                                              0x01bd
 631 #define mmA2S_TAG_ALLOC_0_BASE_IDX                                                                     2
 632 #define mmA2S_TAG_ALLOC_1                                                                              0x01be
 633 #define mmA2S_TAG_ALLOC_1_BASE_IDX                                                                     2
 634 #define mmA2S_MISC_CNTL                                                                                0x01c1
 635 #define mmA2S_MISC_CNTL_BASE_IDX                                                                       2
 636 #define mmNGDC_SDP_PORT_CTRL                                                                           0x01c2
 637 #define mmNGDC_SDP_PORT_CTRL_BASE_IDX                                                                  2
 638 #define mmSHUB_REGS_IF_CTL                                                                             0x01c3
 639 #define mmSHUB_REGS_IF_CTL_BASE_IDX                                                                    2
 640 #define mmNGDC_MGCG_CTRL                                                                               0x01ca
 641 #define mmNGDC_MGCG_CTRL_BASE_IDX                                                                      2
 642 #define mmNGDC_RESERVED_0                                                                              0x01cb
 643 #define mmNGDC_RESERVED_0_BASE_IDX                                                                     2
 644 #define mmNGDC_RESERVED_1                                                                              0x01cc
 645 #define mmNGDC_RESERVED_1_BASE_IDX                                                                     2
 646 #define mmNGDC_SDP_PORT_CTRL_SOCCLK                                                                    0x01cd
 647 #define mmNGDC_SDP_PORT_CTRL_SOCCLK_BASE_IDX                                                           2
 648 #define mmBIF_SDMA0_DOORBELL_RANGE                                                                     0x01d0
 649 #define mmBIF_SDMA0_DOORBELL_RANGE_BASE_IDX                                                            2
 650 #define mmBIF_SDMA1_DOORBELL_RANGE                                                                     0x01d1
 651 #define mmBIF_SDMA1_DOORBELL_RANGE_BASE_IDX                                                            2
 652 #define mmBIF_IH_DOORBELL_RANGE                                                                        0x01d2
 653 #define mmBIF_IH_DOORBELL_RANGE_BASE_IDX                                                               2
 654 #define mmBIF_MMSCH0_DOORBELL_RANGE                                                                    0x01d3
 655 #define mmBIF_MMSCH0_DOORBELL_RANGE_BASE_IDX                                                           2
 656 #define mmBIF_ACV_DOORBELL_RANGE                                                                       0x01d4
 657 #define mmBIF_ACV_DOORBELL_RANGE_BASE_IDX                                                              2
 658 #define mmBIF_DOORBELL_FENCE_CNTL                                                                      0x01de
 659 #define mmBIF_DOORBELL_FENCE_CNTL_BASE_IDX                                                             2
 660 #define mmS2A_MISC_CNTL                                                                                0x01df
 661 #define mmS2A_MISC_CNTL_BASE_IDX                                                                       2
 662 #define mmNGDC_PG_MISC_CTRL                                                                            0x01f0
 663 #define mmNGDC_PG_MISC_CTRL_BASE_IDX                                                                   2
 664 #define mmNGDC_PGMST_CTRL                                                                              0x01f1
 665 #define mmNGDC_PGMST_CTRL_BASE_IDX                                                                     2
 666 #define mmNGDC_PGSLV_CTRL                                                                              0x01f2
 667 #define mmNGDC_PGSLV_CTRL_BASE_IDX                                                                     2
 668 
 669 
 670 // addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFDEC2
 671 // base address: 0x0
 672 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO                                                          0x0400
 673 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                                 3
 674 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI                                                          0x0401
 675 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                                 3
 676 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA                                                         0x0402
 677 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                                3
 678 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL                                                          0x0403
 679 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL_BASE_IDX                                                 3
 680 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO                                                          0x0404
 681 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                                 3
 682 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI                                                          0x0405
 683 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                                 3
 684 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA                                                         0x0406
 685 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                                3
 686 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL                                                          0x0407
 687 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL_BASE_IDX                                                 3
 688 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO                                                          0x0408
 689 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                                 3
 690 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI                                                          0x0409
 691 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                                 3
 692 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA                                                         0x040a
 693 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                                3
 694 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL                                                          0x040b
 695 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL_BASE_IDX                                                 3
 696 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO                                                          0x040c
 697 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                                 3
 698 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI                                                          0x040d
 699 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                                 3
 700 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA                                                         0x040e
 701 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                                3
 702 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL                                                          0x040f
 703 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL_BASE_IDX                                                 3
 704 #define mmRCC_DEV0_EPF0_GFXMSIX_PBA                                                                    0x0800
 705 #define mmRCC_DEV0_EPF0_GFXMSIX_PBA_BASE_IDX                                                           3
 706 
 707 
 708 // addressBlock: nbio_pcie0_pswuscfg0_cfgdecp
 709 // base address: 0x0
 710 #define cfgPSWUSCFG0_0_VENDOR_ID                                                                        0x0000
 711 #define cfgPSWUSCFG0_0_DEVICE_ID                                                                        0x0002
 712 #define cfgPSWUSCFG0_0_COMMAND                                                                          0x0004
 713 #define cfgPSWUSCFG0_0_STATUS                                                                           0x0006
 714 #define cfgPSWUSCFG0_0_REVISION_ID                                                                      0x0008
 715 #define cfgPSWUSCFG0_0_PROG_INTERFACE                                                                   0x0009
 716 #define cfgPSWUSCFG0_0_SUB_CLASS                                                                        0x000a
 717 #define cfgPSWUSCFG0_0_BASE_CLASS                                                                       0x000b
 718 #define cfgPSWUSCFG0_0_CACHE_LINE                                                                       0x000c
 719 #define cfgPSWUSCFG0_0_LATENCY                                                                          0x000d
 720 #define cfgPSWUSCFG0_0_HEADER                                                                           0x000e
 721 #define cfgPSWUSCFG0_0_BIST                                                                             0x000f
 722 #define cfgPSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY                                                           0x0018
 723 #define cfgPSWUSCFG0_0_IO_BASE_LIMIT                                                                    0x001c
 724 #define cfgPSWUSCFG0_0_SECONDARY_STATUS                                                                 0x001e
 725 #define cfgPSWUSCFG0_0_MEM_BASE_LIMIT                                                                   0x0020
 726 #define cfgPSWUSCFG0_0_PREF_BASE_LIMIT                                                                  0x0024
 727 #define cfgPSWUSCFG0_0_PREF_BASE_UPPER                                                                  0x0028
 728 #define cfgPSWUSCFG0_0_PREF_LIMIT_UPPER                                                                 0x002c
 729 #define cfgPSWUSCFG0_0_IO_BASE_LIMIT_HI                                                                 0x0030
 730 #define cfgPSWUSCFG0_0_CAP_PTR                                                                          0x0034
 731 #define cfgPSWUSCFG0_0_ROM_BASE_ADDR                                                                    0x0038
 732 #define cfgPSWUSCFG0_0_INTERRUPT_LINE                                                                   0x003c
 733 #define cfgPSWUSCFG0_0_INTERRUPT_PIN                                                                    0x003d
 734 #define cfgPSWUSCFG0_0_IRQ_BRIDGE_CNTL                                                                  0x003e
 735 #define cfgPSWUSCFG0_0_EXT_BRIDGE_CNTL                                                                  0x0040
 736 #define cfgPSWUSCFG0_0_VENDOR_CAP_LIST                                                                  0x0048
 737 #define cfgPSWUSCFG0_0_ADAPTER_ID_W                                                                     0x004c
 738 #define cfgPSWUSCFG0_0_PMI_CAP_LIST                                                                     0x0050
 739 #define cfgPSWUSCFG0_0_PMI_CAP                                                                          0x0052
 740 #define cfgPSWUSCFG0_0_PMI_STATUS_CNTL                                                                  0x0054
 741 #define cfgPSWUSCFG0_0_PCIE_CAP_LIST                                                                    0x0058
 742 #define cfgPSWUSCFG0_0_PCIE_CAP                                                                         0x005a
 743 #define cfgPSWUSCFG0_0_DEVICE_CAP                                                                       0x005c
 744 #define cfgPSWUSCFG0_0_DEVICE_CNTL                                                                      0x0060
 745 #define cfgPSWUSCFG0_0_DEVICE_STATUS                                                                    0x0062
 746 #define cfgPSWUSCFG0_0_LINK_CAP                                                                         0x0064
 747 #define cfgPSWUSCFG0_0_LINK_CNTL                                                                        0x0068
 748 #define cfgPSWUSCFG0_0_LINK_STATUS                                                                      0x006a
 749 #define cfgPSWUSCFG0_0_DEVICE_CAP2                                                                      0x007c
 750 #define cfgPSWUSCFG0_0_DEVICE_CNTL2                                                                     0x0080
 751 #define cfgPSWUSCFG0_0_DEVICE_STATUS2                                                                   0x0082
 752 #define cfgPSWUSCFG0_0_LINK_CAP2                                                                        0x0084
 753 #define cfgPSWUSCFG0_0_LINK_CNTL2                                                                       0x0088
 754 #define cfgPSWUSCFG0_0_LINK_STATUS2                                                                     0x008a
 755 #define cfgPSWUSCFG0_0_MSI_CAP_LIST                                                                     0x00a0
 756 #define cfgPSWUSCFG0_0_MSI_MSG_CNTL                                                                     0x00a2
 757 #define cfgPSWUSCFG0_0_MSI_MSG_ADDR_LO                                                                  0x00a4
 758 #define cfgPSWUSCFG0_0_MSI_MSG_ADDR_HI                                                                  0x00a8
 759 #define cfgPSWUSCFG0_0_MSI_MSG_DATA                                                                     0x00a8
 760 #define cfgPSWUSCFG0_0_MSI_MSG_DATA_64                                                                  0x00ac
 761 #define cfgPSWUSCFG0_0_SSID_CAP_LIST                                                                    0x00c0
 762 #define cfgPSWUSCFG0_0_SSID_CAP                                                                         0x00c4
 763 #define cfgPSWUSCFG0_0_MSI_MAP_CAP_LIST                                                                 0x00c8
 764 #define cfgPSWUSCFG0_0_MSI_MAP_CAP                                                                      0x00ca
 765 #define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                                0x0100
 766 #define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR                                                         0x0104
 767 #define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC1                                                            0x0108
 768 #define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC2                                                            0x010c
 769 #define cfgPSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST                                                             0x0110
 770 #define cfgPSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1                                                            0x0114
 771 #define cfgPSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2                                                            0x0118
 772 #define cfgPSWUSCFG0_0_PCIE_PORT_VC_CNTL                                                                0x011c
 773 #define cfgPSWUSCFG0_0_PCIE_PORT_VC_STATUS                                                              0x011e
 774 #define cfgPSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP                                                            0x0120
 775 #define cfgPSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL                                                           0x0124
 776 #define cfgPSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS                                                         0x012a
 777 #define cfgPSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP                                                            0x012c
 778 #define cfgPSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL                                                           0x0130
 779 #define cfgPSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS                                                         0x0136
 780 #define cfgPSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                                 0x0140
 781 #define cfgPSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW1                                                          0x0144
 782 #define cfgPSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW2                                                          0x0148
 783 #define cfgPSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                                    0x0150
 784 #define cfgPSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS                                                           0x0154
 785 #define cfgPSWUSCFG0_0_PCIE_UNCORR_ERR_MASK                                                             0x0158
 786 #define cfgPSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY                                                         0x015c
 787 #define cfgPSWUSCFG0_0_PCIE_CORR_ERR_STATUS                                                             0x0160
 788 #define cfgPSWUSCFG0_0_PCIE_CORR_ERR_MASK                                                               0x0164
 789 #define cfgPSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL                                                            0x0168
 790 #define cfgPSWUSCFG0_0_PCIE_HDR_LOG0                                                                    0x016c
 791 #define cfgPSWUSCFG0_0_PCIE_HDR_LOG1                                                                    0x0170
 792 #define cfgPSWUSCFG0_0_PCIE_HDR_LOG2                                                                    0x0174
 793 #define cfgPSWUSCFG0_0_PCIE_HDR_LOG3                                                                    0x0178
 794 #define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG0                                                             0x0188
 795 #define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG1                                                             0x018c
 796 #define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG2                                                             0x0190
 797 #define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG3                                                             0x0194
 798 #define cfgPSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST                                                      0x0270
 799 #define cfgPSWUSCFG0_0_PCIE_LINK_CNTL3                                                                  0x0274
 800 #define cfgPSWUSCFG0_0_PCIE_LANE_ERROR_STATUS                                                           0x0278
 801 #define cfgPSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL                                                    0x027c
 802 #define cfgPSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL                                                    0x027e
 803 #define cfgPSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL                                                    0x0280
 804 #define cfgPSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL                                                    0x0282
 805 #define cfgPSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL                                                    0x0284
 806 #define cfgPSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL                                                    0x0286
 807 #define cfgPSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL                                                    0x0288
 808 #define cfgPSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL                                                    0x028a
 809 #define cfgPSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL                                                    0x028c
 810 #define cfgPSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL                                                    0x028e
 811 #define cfgPSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL                                                   0x0290
 812 #define cfgPSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL                                                   0x0292
 813 #define cfgPSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL                                                   0x0294
 814 #define cfgPSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL                                                   0x0296
 815 #define cfgPSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL                                                   0x0298
 816 #define cfgPSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL                                                   0x029a
 817 #define cfgPSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST                                                            0x02a0
 818 #define cfgPSWUSCFG0_0_PCIE_ACS_CAP                                                                     0x02a4
 819 #define cfgPSWUSCFG0_0_PCIE_ACS_CNTL                                                                    0x02a6
 820 #define cfgPSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST                                                             0x02f0
 821 #define cfgPSWUSCFG0_0_PCIE_MC_CAP                                                                      0x02f4
 822 #define cfgPSWUSCFG0_0_PCIE_MC_CNTL                                                                     0x02f6
 823 #define cfgPSWUSCFG0_0_PCIE_MC_ADDR0                                                                    0x02f8
 824 #define cfgPSWUSCFG0_0_PCIE_MC_ADDR1                                                                    0x02fc
 825 #define cfgPSWUSCFG0_0_PCIE_MC_RCV0                                                                     0x0300
 826 #define cfgPSWUSCFG0_0_PCIE_MC_RCV1                                                                     0x0304
 827 #define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_ALL0                                                               0x0308
 828 #define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_ALL1                                                               0x030c
 829 #define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_0                                                     0x0310
 830 #define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_1                                                     0x0314
 831 #define cfgPSWUSCFG0_0_PCIE_MC_OVERLAY_BAR0                                                             0x0318
 832 #define cfgPSWUSCFG0_0_PCIE_MC_OVERLAY_BAR1                                                             0x031c
 833 #define cfgPSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST                                                            0x0320
 834 #define cfgPSWUSCFG0_0_PCIE_LTR_CAP                                                                     0x0324
 835 #define cfgPSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST                                                            0x0328
 836 #define cfgPSWUSCFG0_0_PCIE_ARI_CAP                                                                     0x032c
 837 #define cfgPSWUSCFG0_0_PCIE_ARI_CNTL                                                                    0x032e
 838 #define cfgPSWUSCFG0_0_PCIE_L1_PM_SUB_CAP_LIST                                                          0x0370
 839 #define cfgPSWUSCFG0_0_PCIE_L1_PM_SUB_CAP                                                               0x0374
 840 #define cfgPSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL                                                              0x0378
 841 #define cfgPSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL2                                                             0x037c
 842 #define cfgPSWUSCFG0_0_PCIE_ESM_CAP_LIST                                                                0x03c4
 843 #define cfgPSWUSCFG0_0_PCIE_ESM_HEADER_1                                                                0x03c8
 844 #define cfgPSWUSCFG0_0_PCIE_ESM_HEADER_2                                                                0x03cc
 845 #define cfgPSWUSCFG0_0_PCIE_ESM_STATUS                                                                  0x03ce
 846 #define cfgPSWUSCFG0_0_PCIE_ESM_CTRL                                                                    0x03d0
 847 #define cfgPSWUSCFG0_0_PCIE_ESM_CAP_1                                                                   0x03d4
 848 #define cfgPSWUSCFG0_0_PCIE_ESM_CAP_2                                                                   0x03d8
 849 #define cfgPSWUSCFG0_0_PCIE_ESM_CAP_3                                                                   0x03dc
 850 #define cfgPSWUSCFG0_0_PCIE_ESM_CAP_4                                                                   0x03e0
 851 #define cfgPSWUSCFG0_0_PCIE_ESM_CAP_5                                                                   0x03e4
 852 #define cfgPSWUSCFG0_0_PCIE_ESM_CAP_6                                                                   0x03e8
 853 #define cfgPSWUSCFG0_0_PCIE_ESM_CAP_7                                                                   0x03ec
 854 #define cfgPSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST                                                            0x0400
 855 #define cfgPSWUSCFG0_0_DATA_LINK_FEATURE_CAP                                                            0x0404
 856 #define cfgPSWUSCFG0_0_DATA_LINK_FEATURE_STATUS                                                         0x0408
 857 #define cfgPSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST                                                       0x0410
 858 #define cfgPSWUSCFG0_0_LINK_CAP_16GT                                                                    0x0414
 859 #define cfgPSWUSCFG0_0_LINK_CNTL_16GT                                                                   0x0418
 860 #define cfgPSWUSCFG0_0_LINK_STATUS_16GT                                                                 0x041c
 861 #define cfgPSWUSCFG0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT                                                0x0420
 862 #define cfgPSWUSCFG0_0_RTM1_PARITY_MISMATCH_STATUS_16GT                                                 0x0424
 863 #define cfgPSWUSCFG0_0_RTM2_PARITY_MISMATCH_STATUS_16GT                                                 0x0428
 864 #define cfgPSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT                                                    0x0430
 865 #define cfgPSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT                                                    0x0431
 866 #define cfgPSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT                                                    0x0432
 867 #define cfgPSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT                                                    0x0433
 868 #define cfgPSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT                                                    0x0434
 869 #define cfgPSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT                                                    0x0435
 870 #define cfgPSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT                                                    0x0436
 871 #define cfgPSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT                                                    0x0437
 872 #define cfgPSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT                                                    0x0438
 873 #define cfgPSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT                                                    0x0439
 874 #define cfgPSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT                                                   0x043a
 875 #define cfgPSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT                                                   0x043b
 876 #define cfgPSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT                                                   0x043c
 877 #define cfgPSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT                                                   0x043d
 878 #define cfgPSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT                                                   0x043e
 879 #define cfgPSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT                                                   0x043f
 880 #define cfgPSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST                                                      0x0440
 881 #define cfgPSWUSCFG0_0_MARGINING_PORT_CAP                                                               0x0444
 882 #define cfgPSWUSCFG0_0_MARGINING_PORT_STATUS                                                            0x0446
 883 #define cfgPSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL                                                       0x0448
 884 #define cfgPSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS                                                     0x044a
 885 #define cfgPSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL                                                       0x044c
 886 #define cfgPSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS                                                     0x044e
 887 #define cfgPSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL                                                       0x0450
 888 #define cfgPSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS                                                     0x0452
 889 #define cfgPSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL                                                       0x0454
 890 #define cfgPSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS                                                     0x0456
 891 #define cfgPSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL                                                       0x0458
 892 #define cfgPSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS                                                     0x045a
 893 #define cfgPSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL                                                       0x045c
 894 #define cfgPSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS                                                     0x045e
 895 #define cfgPSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL                                                       0x0460
 896 #define cfgPSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS                                                     0x0462
 897 #define cfgPSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL                                                       0x0464
 898 #define cfgPSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS                                                     0x0466
 899 #define cfgPSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL                                                       0x0468
 900 #define cfgPSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS                                                     0x046a
 901 #define cfgPSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL                                                       0x046c
 902 #define cfgPSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS                                                     0x046e
 903 #define cfgPSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL                                                      0x0470
 904 #define cfgPSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS                                                    0x0472
 905 #define cfgPSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL                                                      0x0474
 906 #define cfgPSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS                                                    0x0476
 907 #define cfgPSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL                                                      0x0478
 908 #define cfgPSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS                                                    0x047a
 909 #define cfgPSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL                                                      0x047c
 910 #define cfgPSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS                                                    0x047e
 911 #define cfgPSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL                                                      0x0480
 912 #define cfgPSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS                                                    0x0482
 913 #define cfgPSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL                                                      0x0484
 914 #define cfgPSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS                                                    0x0486
 915 #define cfgPSWUSCFG0_0_PCIE_CCIX_CAP_LIST                                                               0x0488
 916 #define cfgPSWUSCFG0_0_PCIE_CCIX_HEADER_1                                                               0x048c
 917 #define cfgPSWUSCFG0_0_PCIE_CCIX_HEADER_2                                                               0x0490
 918 #define cfgPSWUSCFG0_0_PCIE_CCIX_CAP                                                                    0x0492
 919 #define cfgPSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP                                                           0x0494
 920 #define cfgPSWUSCFG0_0_PCIE_CCIX_ESM_OPTL_CAP                                                           0x0498
 921 #define cfgPSWUSCFG0_0_PCIE_CCIX_ESM_STATUS                                                             0x049c
 922 #define cfgPSWUSCFG0_0_PCIE_CCIX_ESM_CNTL                                                               0x04a0
 923 #define cfgPSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT                                                0x04a4
 924 #define cfgPSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT                                                0x04a5
 925 #define cfgPSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT                                                0x04a6
 926 #define cfgPSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT                                                0x04a7
 927 #define cfgPSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT                                                0x04a8
 928 #define cfgPSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT                                                0x04a9
 929 #define cfgPSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT                                                0x04aa
 930 #define cfgPSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT                                                0x04ab
 931 #define cfgPSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT                                                0x04ac
 932 #define cfgPSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT                                                0x04ad
 933 #define cfgPSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT                                               0x04ae
 934 #define cfgPSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT                                               0x04af
 935 #define cfgPSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT                                               0x04b0
 936 #define cfgPSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT                                               0x04b1
 937 #define cfgPSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT                                               0x04b2
 938 #define cfgPSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT                                               0x04b3
 939 #define cfgPSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT                                                0x04b4
 940 #define cfgPSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT                                                0x04b5
 941 #define cfgPSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT                                                0x04b6
 942 #define cfgPSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT                                                0x04b7
 943 #define cfgPSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT                                                0x04b8
 944 #define cfgPSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT                                                0x04b9
 945 #define cfgPSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT                                                0x04ba
 946 #define cfgPSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT                                                0x04bb
 947 #define cfgPSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT                                                0x04bc
 948 #define cfgPSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT                                                0x04bd
 949 #define cfgPSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT                                               0x04be
 950 #define cfgPSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT                                               0x04bf
 951 #define cfgPSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT                                               0x04c0
 952 #define cfgPSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT                                               0x04c1
 953 #define cfgPSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT                                               0x04c2
 954 #define cfgPSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT                                               0x04c3
 955 #define cfgPSWUSCFG0_0_PCIE_CCIX_TRANS_CAP                                                              0x04c4
 956 #define cfgPSWUSCFG0_0_PCIE_CCIX_TRANS_CNTL                                                             0x04c8
 957 
 958 
 959 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp
 960 // base address: 0x0
 961 #define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_ID                                                                0x0000
 962 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_ID                                                                0x0002
 963 #define cfgBIF_CFG_DEV0_EPF0_0_COMMAND                                                                  0x0004
 964 #define cfgBIF_CFG_DEV0_EPF0_0_STATUS                                                                   0x0006
 965 #define cfgBIF_CFG_DEV0_EPF0_0_REVISION_ID                                                              0x0008
 966 #define cfgBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE                                                           0x0009
 967 #define cfgBIF_CFG_DEV0_EPF0_0_SUB_CLASS                                                                0x000a
 968 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_CLASS                                                               0x000b
 969 #define cfgBIF_CFG_DEV0_EPF0_0_CACHE_LINE                                                               0x000c
 970 #define cfgBIF_CFG_DEV0_EPF0_0_LATENCY                                                                  0x000d
 971 #define cfgBIF_CFG_DEV0_EPF0_0_HEADER                                                                   0x000e
 972 #define cfgBIF_CFG_DEV0_EPF0_0_BIST                                                                     0x000f
 973 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1                                                              0x0010
 974 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2                                                              0x0014
 975 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3                                                              0x0018
 976 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4                                                              0x001c
 977 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5                                                              0x0020
 978 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6                                                              0x0024
 979 #define cfgBIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR                                                          0x0028
 980 #define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID                                                               0x002c
 981 #define cfgBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR                                                            0x0030
 982 #define cfgBIF_CFG_DEV0_EPF0_0_CAP_PTR                                                                  0x0034
 983 #define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE                                                           0x003c
 984 #define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN                                                            0x003d
 985 #define cfgBIF_CFG_DEV0_EPF0_0_MIN_GRANT                                                                0x003e
 986 #define cfgBIF_CFG_DEV0_EPF0_0_MAX_LATENCY                                                              0x003f
 987 #define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST                                                          0x0048
 988 #define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W                                                             0x004c
 989 #define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST                                                             0x0050
 990 #define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP                                                                  0x0052
 991 #define cfgBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL                                                          0x0054
 992 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST                                                            0x0064
 993 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP                                                                 0x0066
 994 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP                                                               0x0068
 995 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL                                                              0x006c
 996 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS                                                            0x006e
 997 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP                                                                 0x0070
 998 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL                                                                0x0074
 999 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS                                                              0x0076
1000 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2                                                              0x0088
1001 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2                                                             0x008c
1002 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2                                                           0x008e
1003 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP2                                                                0x0090
1004 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL2                                                               0x0094
1005 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS2                                                             0x0096
1006 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST                                                             0x00a0
1007 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL                                                             0x00a2
1008 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO                                                          0x00a4
1009 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI                                                          0x00a8
1010 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA                                                             0x00a8
1011 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK                                                                 0x00ac
1012 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64                                                          0x00ac
1013 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK_64                                                              0x00b0
1014 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING                                                              0x00b0
1015 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64                                                           0x00b4
1016 #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST                                                            0x00c0
1017 #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL                                                            0x00c2
1018 #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_TABLE                                                               0x00c4
1019 #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_PBA                                                                 0x00c8
1020 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                        0x0100
1021 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR                                                 0x0104
1022 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1                                                    0x0108
1023 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2                                                    0x010c
1024 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST                                                     0x0110
1025 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1                                                    0x0114
1026 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2                                                    0x0118
1027 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL                                                        0x011c
1028 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS                                                      0x011e
1029 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP                                                    0x0120
1030 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL                                                   0x0124
1031 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS                                                 0x012a
1032 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP                                                    0x012c
1033 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL                                                   0x0130
1034 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS                                                 0x0136
1035 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                         0x0140
1036 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1                                                  0x0144
1037 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2                                                  0x0148
1038 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                            0x0150
1039 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS                                                   0x0154
1040 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK                                                     0x0158
1041 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY                                                 0x015c
1042 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS                                                     0x0160
1043 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK                                                       0x0164
1044 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL                                                    0x0168
1045 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0                                                            0x016c
1046 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1                                                            0x0170
1047 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2                                                            0x0174
1048 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3                                                            0x0178
1049 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0                                                     0x0188
1050 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1                                                     0x018c
1051 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2                                                     0x0190
1052 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3                                                     0x0194
1053 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST                                                    0x0200
1054 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP                                                            0x0204
1055 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL                                                           0x0208
1056 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP                                                            0x020c
1057 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL                                                           0x0210
1058 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP                                                            0x0214
1059 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL                                                           0x0218
1060 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP                                                            0x021c
1061 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL                                                           0x0220
1062 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP                                                            0x0224
1063 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL                                                           0x0228
1064 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP                                                            0x022c
1065 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL                                                           0x0230
1066 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST                                             0x0240
1067 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT                                              0x0244
1068 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA                                                     0x0248
1069 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP                                                      0x024c
1070 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST                                                    0x0250
1071 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP                                                             0x0254
1072 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR                                               0x0258
1073 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS                                                          0x025c
1074 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL                                                            0x025e
1075 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                            0x0260
1076 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                            0x0261
1077 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                            0x0262
1078 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                            0x0263
1079 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                            0x0264
1080 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                            0x0265
1081 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                            0x0266
1082 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                            0x0267
1083 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST                                              0x0270
1084 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3                                                          0x0274
1085 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS                                                   0x0278
1086 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL                                            0x027c
1087 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL                                            0x027e
1088 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL                                            0x0280
1089 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL                                            0x0282
1090 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL                                            0x0284
1091 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL                                            0x0286
1092 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL                                            0x0288
1093 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL                                            0x028a
1094 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL                                            0x028c
1095 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL                                            0x028e
1096 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL                                           0x0290
1097 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL                                           0x0292
1098 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL                                           0x0294
1099 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL                                           0x0296
1100 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL                                           0x0298
1101 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL                                           0x029a
1102 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST                                                    0x02a0
1103 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP                                                             0x02a4
1104 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL                                                            0x02a6
1105 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST                                                    0x02b0
1106 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP                                                             0x02b4
1107 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL                                                            0x02b6
1108 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST                                               0x02c0
1109 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL                                                       0x02c4
1110 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS                                                     0x02c6
1111 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY                                          0x02c8
1112 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC                                             0x02cc
1113 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST                                                  0x02d0
1114 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP                                                           0x02d4
1115 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL                                                          0x02d6
1116 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST                                                     0x02f0
1117 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP                                                              0x02f4
1118 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL                                                             0x02f6
1119 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0                                                            0x02f8
1120 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1                                                            0x02fc
1121 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0                                                             0x0300
1122 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1                                                             0x0304
1123 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0                                                       0x0308
1124 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1                                                       0x030c
1125 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0                                             0x0310
1126 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1                                             0x0314
1127 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST                                                    0x0320
1128 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP                                                             0x0324
1129 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST                                                    0x0328
1130 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP                                                             0x032c
1131 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL                                                            0x032e
1132 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST                                                  0x0330
1133 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP                                                           0x0334
1134 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL                                                       0x0338
1135 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS                                                        0x033a
1136 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS                                                   0x033c
1137 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS                                                     0x033e
1138 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS                                                       0x0340
1139 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK                                                 0x0342
1140 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET                                               0x0344
1141 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE                                                     0x0346
1142 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID                                                  0x034a
1143 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE                                           0x034c
1144 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE                                              0x0350
1145 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0                                                0x0354
1146 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1                                                0x0358
1147 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2                                                0x035c
1148 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3                                                0x0360
1149 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4                                                0x0364
1150 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5                                                0x0368
1151 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET                               0x036c
1152 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST                                               0x0370
1153 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP                                                        0x0374
1154 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL                                                       0x0378
1155 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST                                                    0x0400
1156 #define cfgBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP                                                    0x0404
1157 #define cfgBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS                                                 0x0408
1158 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST                                               0x0410
1159 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT                                                            0x0414
1160 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT                                                           0x0418
1161 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT                                                         0x041c
1162 #define cfgBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT                                        0x0420
1163 #define cfgBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT                                         0x0424
1164 #define cfgBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT                                         0x0428
1165 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT                                            0x0430
1166 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT                                            0x0431
1167 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT                                            0x0432
1168 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT                                            0x0433
1169 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT                                            0x0434
1170 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT                                            0x0435
1171 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT                                            0x0436
1172 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT                                            0x0437
1173 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT                                            0x0438
1174 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT                                            0x0439
1175 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT                                           0x043a
1176 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT                                           0x043b
1177 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT                                           0x043c
1178 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT                                           0x043d
1179 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT                                           0x043e
1180 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT                                           0x043f
1181 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST                                              0x0440
1182 #define cfgBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP                                                       0x0444
1183 #define cfgBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS                                                    0x0446
1184 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL                                               0x0448
1185 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS                                             0x044a
1186 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL                                               0x044c
1187 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS                                             0x044e
1188 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL                                               0x0450
1189 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS                                             0x0452
1190 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL                                               0x0454
1191 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS                                             0x0456
1192 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL                                               0x0458
1193 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS                                             0x045a
1194 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL                                               0x045c
1195 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS                                             0x045e
1196 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL                                               0x0460
1197 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS                                             0x0462
1198 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL                                               0x0464
1199 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS                                             0x0466
1200 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL                                               0x0468
1201 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS                                             0x046a
1202 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL                                               0x046c
1203 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS                                             0x046e
1204 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL                                              0x0470
1205 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS                                            0x0472
1206 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL                                              0x0474
1207 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS                                            0x0476
1208 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL                                              0x0478
1209 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS                                            0x047a
1210 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL                                              0x047c
1211 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS                                            0x047e
1212 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL                                              0x0480
1213 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS                                            0x0482
1214 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL                                              0x0484
1215 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS                                            0x0486
1216 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST                                          0x04c0
1217 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP                                                  0x04c4
1218 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL                                                 0x04c8
1219 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP                                                  0x04cc
1220 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL                                                 0x04d0
1221 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP                                                  0x04d4
1222 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL                                                 0x04d8
1223 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP                                                  0x04dc
1224 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL                                                 0x04e0
1225 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP                                                  0x04e4
1226 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL                                                 0x04e8
1227 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP                                                  0x04ec
1228 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL                                                 0x04f0
1229 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV                                 0x0500
1230 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV                                          0x0504
1231 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW                             0x0508
1232 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE                              0x050c
1233 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS                              0x0510
1234 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL                            0x0514
1235 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0                            0x0518
1236 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1                            0x051c
1237 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2                            0x0520
1238 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT                                  0x0524
1239 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB                                 0x0528
1240 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS                                  0x052c
1241 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION                                   0x0530
1242 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE                     0x0534
1243 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB                                   0x0538
1244 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB                                   0x053c
1245 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB                                   0x0540
1246 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB                                   0x0544
1247 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB                                   0x0548
1248 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB                                   0x054c
1249 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB                                   0x0550
1250 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB                                   0x0554
1251 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB                                   0x0558
1252 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB                                   0x055c
1253 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB                                  0x0560
1254 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB                                  0x0564
1255 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB                                  0x0568
1256 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB                                  0x056c
1257 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB                                  0x0570
1258 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB                                  0x0574
1259 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB                                  0x0578
1260 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB                                  0x057c
1261 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB                                  0x0580
1262 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB                                  0x0584
1263 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB                                  0x0588
1264 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB                                  0x058c
1265 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB                                  0x0590
1266 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB                                  0x0594
1267 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB                                  0x0598
1268 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB                                  0x059c
1269 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB                                  0x05a0
1270 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB                                  0x05a4
1271 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB                                  0x05a8
1272 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB                                  0x05ac
1273 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB                                  0x05b0
1274 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0                               0x05c0
1275 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1                               0x05c4
1276 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2                               0x05c8
1277 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3                               0x05cc
1278 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4                               0x05d0
1279 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5                               0x05d4
1280 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6                               0x05d8
1281 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7                               0x05dc
1282 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8                               0x05e0
1283 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0                               0x05f0
1284 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1                               0x05f4
1285 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2                               0x05f8
1286 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3                               0x05fc
1287 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4                               0x0600
1288 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5                               0x0604
1289 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6                               0x0608
1290 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7                               0x060c
1291 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8                               0x0610
1292 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0                               0x0620
1293 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1                               0x0624
1294 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2                               0x0628
1295 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3                               0x062c
1296 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4                               0x0630
1297 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5                               0x0634
1298 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6                               0x0638
1299 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7                               0x063c
1300 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8                               0x0640
1301 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0                              0x0650
1302 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1                              0x0654
1303 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2                              0x0658
1304 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3                              0x065c
1305 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4                              0x0660
1306 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5                              0x0664
1307 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6                              0x0668
1308 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7                              0x066c
1309 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8                              0x0670
1310 
1311 
1312 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp
1313 // base address: 0x0
1314 #define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_ID                                                                0x0000
1315 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_ID                                                                0x0002
1316 #define cfgBIF_CFG_DEV0_EPF1_0_COMMAND                                                                  0x0004
1317 #define cfgBIF_CFG_DEV0_EPF1_0_STATUS                                                                   0x0006
1318 #define cfgBIF_CFG_DEV0_EPF1_0_REVISION_ID                                                              0x0008
1319 #define cfgBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE                                                           0x0009
1320 #define cfgBIF_CFG_DEV0_EPF1_0_SUB_CLASS                                                                0x000a
1321 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_CLASS                                                               0x000b
1322 #define cfgBIF_CFG_DEV0_EPF1_0_CACHE_LINE                                                               0x000c
1323 #define cfgBIF_CFG_DEV0_EPF1_0_LATENCY                                                                  0x000d
1324 #define cfgBIF_CFG_DEV0_EPF1_0_HEADER                                                                   0x000e
1325 #define cfgBIF_CFG_DEV0_EPF1_0_BIST                                                                     0x000f
1326 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1                                                              0x0010
1327 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2                                                              0x0014
1328 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3                                                              0x0018
1329 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4                                                              0x001c
1330 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5                                                              0x0020
1331 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6                                                              0x0024
1332 #define cfgBIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR                                                          0x0028
1333 #define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID                                                               0x002c
1334 #define cfgBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR                                                            0x0030
1335 #define cfgBIF_CFG_DEV0_EPF1_0_CAP_PTR                                                                  0x0034
1336 #define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE                                                           0x003c
1337 #define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN                                                            0x003d
1338 #define cfgBIF_CFG_DEV0_EPF1_0_MIN_GRANT                                                                0x003e
1339 #define cfgBIF_CFG_DEV0_EPF1_0_MAX_LATENCY                                                              0x003f
1340 #define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST                                                          0x0048
1341 #define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W                                                             0x004c
1342 #define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST                                                             0x0050
1343 #define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP                                                                  0x0052
1344 #define cfgBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL                                                          0x0054
1345 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST                                                            0x0064
1346 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP                                                                 0x0066
1347 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP                                                               0x0068
1348 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL                                                              0x006c
1349 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS                                                            0x006e
1350 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP                                                                 0x0070
1351 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL                                                                0x0074
1352 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS                                                              0x0076
1353 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2                                                              0x0088
1354 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2                                                             0x008c
1355 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2                                                           0x008e
1356 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP2                                                                0x0090
1357 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL2                                                               0x0094
1358 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS2                                                             0x0096
1359 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST                                                             0x00a0
1360 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL                                                             0x00a2
1361 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO                                                          0x00a4
1362 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI                                                          0x00a8
1363 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA                                                             0x00a8
1364 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK                                                                 0x00ac
1365 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64                                                          0x00ac
1366 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK_64                                                              0x00b0
1367 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING                                                              0x00b0
1368 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64                                                           0x00b4
1369 #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST                                                            0x00c0
1370 #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL                                                            0x00c2
1371 #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_TABLE                                                               0x00c4
1372 #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_PBA                                                                 0x00c8
1373 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                        0x0100
1374 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR                                                 0x0104
1375 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1                                                    0x0108
1376 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2                                                    0x010c
1377 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST                                                     0x0110
1378 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1                                                    0x0114
1379 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2                                                    0x0118
1380 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL                                                        0x011c
1381 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS                                                      0x011e
1382 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP                                                    0x0120
1383 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL                                                   0x0124
1384 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS                                                 0x012a
1385 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP                                                    0x012c
1386 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL                                                   0x0130
1387 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS                                                 0x0136
1388 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                         0x0140
1389 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1                                                  0x0144
1390 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2                                                  0x0148
1391 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                            0x0150
1392 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS                                                   0x0154
1393 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK                                                     0x0158
1394 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY                                                 0x015c
1395 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS                                                     0x0160
1396 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK                                                       0x0164
1397 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL                                                    0x0168
1398 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0                                                            0x016c
1399 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1                                                            0x0170
1400 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2                                                            0x0174
1401 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3                                                            0x0178
1402 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0                                                     0x0188
1403 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1                                                     0x018c
1404 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2                                                     0x0190
1405 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3                                                     0x0194
1406 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST                                                    0x0200
1407 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP                                                            0x0204
1408 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL                                                           0x0208
1409 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP                                                            0x020c
1410 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL                                                           0x0210
1411 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP                                                            0x0214
1412 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL                                                           0x0218
1413 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP                                                            0x021c
1414 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL                                                           0x0220
1415 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP                                                            0x0224
1416 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL                                                           0x0228
1417 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP                                                            0x022c
1418 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL                                                           0x0230
1419 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST                                             0x0240
1420 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT                                              0x0244
1421 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA                                                     0x0248
1422 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP                                                      0x024c
1423 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST                                                    0x0250
1424 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP                                                             0x0254
1425 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR                                               0x0258
1426 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS                                                          0x025c
1427 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL                                                            0x025e
1428 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                            0x0260
1429 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                            0x0261
1430 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                            0x0262
1431 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                            0x0263
1432 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                            0x0264
1433 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                            0x0265
1434 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                            0x0266
1435 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                            0x0267
1436 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST                                              0x0270
1437 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3                                                          0x0274
1438 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS                                                   0x0278
1439 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL                                            0x027c
1440 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL                                            0x027e
1441 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL                                            0x0280
1442 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL                                            0x0282
1443 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL                                            0x0284
1444 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL                                            0x0286
1445 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL                                            0x0288
1446 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL                                            0x028a
1447 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL                                            0x028c
1448 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL                                            0x028e
1449 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL                                           0x0290
1450 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL                                           0x0292
1451 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL                                           0x0294
1452 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL                                           0x0296
1453 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL                                           0x0298
1454 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL                                           0x029a
1455 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST                                                    0x02a0
1456 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP                                                             0x02a4
1457 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL                                                            0x02a6
1458 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST                                                    0x02b0
1459 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP                                                             0x02b4
1460 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL                                                            0x02b6
1461 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST                                               0x02c0
1462 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL                                                       0x02c4
1463 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS                                                     0x02c6
1464 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY                                          0x02c8
1465 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC                                             0x02cc
1466 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST                                                  0x02d0
1467 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP                                                           0x02d4
1468 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL                                                          0x02d6
1469 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST                                                     0x02f0
1470 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP                                                              0x02f4
1471 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL                                                             0x02f6
1472 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0                                                            0x02f8
1473 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1                                                            0x02fc
1474 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0                                                             0x0300
1475 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1                                                             0x0304
1476 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0                                                       0x0308
1477 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1                                                       0x030c
1478 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0                                             0x0310
1479 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1                                             0x0314
1480 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST                                                    0x0320
1481 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP                                                             0x0324
1482 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST                                                    0x0328
1483 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP                                                             0x032c
1484 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL                                                            0x032e
1485 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST                                                  0x0330
1486 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP                                                           0x0334
1487 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL                                                       0x0338
1488 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS                                                        0x033a
1489 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS                                                   0x033c
1490 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS                                                     0x033e
1491 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS                                                       0x0340
1492 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK                                                 0x0342
1493 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET                                               0x0344
1494 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE                                                     0x0346
1495 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID                                                  0x034a
1496 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE                                           0x034c
1497 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE                                              0x0350
1498 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0                                                0x0354
1499 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1                                                0x0358
1500 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2                                                0x035c
1501 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3                                                0x0360
1502 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4                                                0x0364
1503 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5                                                0x0368
1504 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET                               0x036c
1505 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST                                               0x0370
1506 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP                                                        0x0374
1507 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL                                                       0x0378
1508 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST                                                    0x0400
1509 #define cfgBIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP                                                    0x0404
1510 #define cfgBIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS                                                 0x0408
1511 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST                                               0x0410
1512 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP_16GT                                                            0x0414
1513 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL_16GT                                                           0x0418
1514 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT                                                         0x041c
1515 #define cfgBIF_CFG_DEV0_EPF1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT                                        0x0420
1516 #define cfgBIF_CFG_DEV0_EPF1_0_RTM1_PARITY_MISMATCH_STATUS_16GT                                         0x0424
1517 #define cfgBIF_CFG_DEV0_EPF1_0_RTM2_PARITY_MISMATCH_STATUS_16GT                                         0x0428
1518 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT                                            0x0430
1519 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT                                            0x0431
1520 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT                                            0x0432
1521 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT                                            0x0433
1522 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT                                            0x0434
1523 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT                                            0x0435
1524 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT                                            0x0436
1525 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT                                            0x0437
1526 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT                                            0x0438
1527 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT                                            0x0439
1528 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT                                           0x043a
1529 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT                                           0x043b
1530 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT                                           0x043c
1531 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT                                           0x043d
1532 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT                                           0x043e
1533 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT                                           0x043f
1534 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST                                              0x0440
1535 #define cfgBIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP                                                       0x0444
1536 #define cfgBIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS                                                    0x0446
1537 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL                                               0x0448
1538 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS                                             0x044a
1539 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL                                               0x044c
1540 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS                                             0x044e
1541 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL                                               0x0450
1542 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS                                             0x0452
1543 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL                                               0x0454
1544 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS                                             0x0456
1545 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL                                               0x0458
1546 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS                                             0x045a
1547 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL                                               0x045c
1548 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS                                             0x045e
1549 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL                                               0x0460
1550 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS                                             0x0462
1551 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL                                               0x0464
1552 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS                                             0x0466
1553 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL                                               0x0468
1554 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS                                             0x046a
1555 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL                                               0x046c
1556 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS                                             0x046e
1557 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL                                              0x0470
1558 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS                                            0x0472
1559 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL                                              0x0474
1560 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS                                            0x0476
1561 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL                                              0x0478
1562 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS                                            0x047a
1563 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL                                              0x047c
1564 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS                                            0x047e
1565 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL                                              0x0480
1566 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS                                            0x0482
1567 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL                                              0x0484
1568 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS                                            0x0486
1569 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST                                          0x04c0
1570 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP                                                  0x04c4
1571 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL                                                 0x04c8
1572 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP                                                  0x04cc
1573 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL                                                 0x04d0
1574 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP                                                  0x04d4
1575 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL                                                 0x04d8
1576 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP                                                  0x04dc
1577 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL                                                 0x04e0
1578 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP                                                  0x04e4
1579 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL                                                 0x04e8
1580 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP                                                  0x04ec
1581 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL                                                 0x04f0
1582 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV                                 0x0500
1583 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV                                          0x0504
1584 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW                             0x0508
1585 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE                              0x050c
1586 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS                              0x0510
1587 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL                            0x0514
1588 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0                            0x0518
1589 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1                            0x051c
1590 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2                            0x0520
1591 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT                                  0x0524
1592 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB                                 0x0528
1593 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS                                  0x052c
1594 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION                                   0x0530
1595 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE                     0x0534
1596 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB                                   0x0538
1597 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB                                   0x053c
1598 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB                                   0x0540
1599 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB                                   0x0544
1600 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB                                   0x0548
1601 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB                                   0x054c
1602 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB                                   0x0550
1603 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB                                   0x0554
1604 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB                                   0x0558
1605 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB                                   0x055c
1606 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB                                  0x0560
1607 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB                                  0x0564
1608 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB                                  0x0568
1609 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB                                  0x056c
1610 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB                                  0x0570
1611 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB                                  0x0574
1612 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB                                  0x0578
1613 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB                                  0x057c
1614 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB                                  0x0580
1615 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB                                  0x0584
1616 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB                                  0x0588
1617 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB                                  0x058c
1618 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB                                  0x0590
1619 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB                                  0x0594
1620 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB                                  0x0598
1621 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB                                  0x059c
1622 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB                                  0x05a0
1623 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB                                  0x05a4
1624 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB                                  0x05a8
1625 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB                                  0x05ac
1626 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB                                  0x05b0
1627 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0                               0x05c0
1628 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1                               0x05c4
1629 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2                               0x05c8
1630 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3                               0x05cc
1631 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4                               0x05d0
1632 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5                               0x05d4
1633 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6                               0x05d8
1634 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7                               0x05dc
1635 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8                               0x05e0
1636 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0                               0x05f0
1637 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1                               0x05f4
1638 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2                               0x05f8
1639 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3                               0x05fc
1640 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4                               0x0600
1641 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5                               0x0604
1642 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6                               0x0608
1643 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7                               0x060c
1644 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8                               0x0610
1645 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0                               0x0620
1646 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1                               0x0624
1647 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2                               0x0628
1648 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3                               0x062c
1649 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4                               0x0630
1650 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5                               0x0634
1651 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6                               0x0638
1652 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7                               0x063c
1653 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8                               0x0640
1654 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0                              0x0650
1655 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1                              0x0654
1656 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2                              0x0658
1657 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3                              0x065c
1658 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4                              0x0660
1659 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5                              0x0664
1660 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6                              0x0668
1661 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7                              0x066c
1662 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8                              0x0670
1663 
1664 
1665 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp
1666 // base address: 0x0
1667 #define cfgBIF_CFG_DEV0_EPF2_0_VENDOR_ID                                                                0x0000
1668 #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_ID                                                                0x0002
1669 #define cfgBIF_CFG_DEV0_EPF2_0_COMMAND                                                                  0x0004
1670 #define cfgBIF_CFG_DEV0_EPF2_0_STATUS                                                                   0x0006
1671 #define cfgBIF_CFG_DEV0_EPF2_0_REVISION_ID                                                              0x0008
1672 #define cfgBIF_CFG_DEV0_EPF2_0_PROG_INTERFACE                                                           0x0009
1673 #define cfgBIF_CFG_DEV0_EPF2_0_SUB_CLASS                                                                0x000a
1674 #define cfgBIF_CFG_DEV0_EPF2_0_BASE_CLASS                                                               0x000b
1675 #define cfgBIF_CFG_DEV0_EPF2_0_CACHE_LINE                                                               0x000c
1676 #define cfgBIF_CFG_DEV0_EPF2_0_LATENCY                                                                  0x000d
1677 #define cfgBIF_CFG_DEV0_EPF2_0_HEADER                                                                   0x000e
1678 #define cfgBIF_CFG_DEV0_EPF2_0_BIST                                                                     0x000f
1679 #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_1                                                              0x0010
1680 #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_2                                                              0x0014
1681 #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_3                                                              0x0018
1682 #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_4                                                              0x001c
1683 #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_5                                                              0x0020
1684 #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_6                                                              0x0024
1685 #define cfgBIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR                                                          0x0028
1686 #define cfgBIF_CFG_DEV0_EPF2_0_ADAPTER_ID                                                               0x002c
1687 #define cfgBIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR                                                            0x0030
1688 #define cfgBIF_CFG_DEV0_EPF2_0_CAP_PTR                                                                  0x0034
1689 #define cfgBIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE                                                           0x003c
1690 #define cfgBIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN                                                            0x003d
1691 #define cfgBIF_CFG_DEV0_EPF2_0_MIN_GRANT                                                                0x003e
1692 #define cfgBIF_CFG_DEV0_EPF2_0_MAX_LATENCY                                                              0x003f
1693 #define cfgBIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST                                                          0x0048
1694 #define cfgBIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W                                                             0x004c
1695 #define cfgBIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST                                                             0x0050
1696 #define cfgBIF_CFG_DEV0_EPF2_0_PMI_CAP                                                                  0x0052
1697 #define cfgBIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL                                                          0x0054
1698 #define cfgBIF_CFG_DEV0_EPF2_0_SBRN                                                                     0x0060
1699 #define cfgBIF_CFG_DEV0_EPF2_0_FLADJ                                                                    0x0061
1700 #define cfgBIF_CFG_DEV0_EPF2_0_DBESL_DBESLD                                                             0x0062
1701 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST                                                            0x0064
1702 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CAP                                                                 0x0066
1703 #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CAP                                                               0x0068
1704 #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL                                                              0x006c
1705 #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS                                                            0x006e
1706 #define cfgBIF_CFG_DEV0_EPF2_0_LINK_CAP                                                                 0x0070
1707 #define cfgBIF_CFG_DEV0_EPF2_0_LINK_CNTL                                                                0x0074
1708 #define cfgBIF_CFG_DEV0_EPF2_0_LINK_STATUS                                                              0x0076
1709 #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CAP2                                                              0x0088
1710 #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2                                                             0x008c
1711 #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2                                                           0x008e
1712 #define cfgBIF_CFG_DEV0_EPF2_0_LINK_CAP2                                                                0x0090
1713 #define cfgBIF_CFG_DEV0_EPF2_0_LINK_CNTL2                                                               0x0094
1714 #define cfgBIF_CFG_DEV0_EPF2_0_LINK_STATUS2                                                             0x0096
1715 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST                                                             0x00a0
1716 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL                                                             0x00a2
1717 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO                                                          0x00a4
1718 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI                                                          0x00a8
1719 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA                                                             0x00a8
1720 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MASK                                                                 0x00ac
1721 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64                                                          0x00ac
1722 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MASK_64                                                              0x00b0
1723 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_PENDING                                                              0x00b0
1724 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_PENDING_64                                                           0x00b4
1725 #define cfgBIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST                                                            0x00c0
1726 #define cfgBIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL                                                            0x00c2
1727 #define cfgBIF_CFG_DEV0_EPF2_0_MSIX_TABLE                                                               0x00c4
1728 #define cfgBIF_CFG_DEV0_EPF2_0_MSIX_PBA                                                                 0x00c8
1729 #define cfgBIF_CFG_DEV0_EPF2_0_SATA_CAP_0                                                               0x00d0
1730 #define cfgBIF_CFG_DEV0_EPF2_0_SATA_CAP_1                                                               0x00d4
1731 #define cfgBIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX                                                           0x00d8
1732 #define cfgBIF_CFG_DEV0_EPF2_0_SATA_IDP_DATA                                                            0x00dc
1733 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                        0x0100
1734 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR                                                 0x0104
1735 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1                                                    0x0108
1736 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2                                                    0x010c
1737 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                            0x0150
1738 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS                                                   0x0154
1739 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK                                                     0x0158
1740 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY                                                 0x015c
1741 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS                                                     0x0160
1742 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK                                                       0x0164
1743 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL                                                    0x0168
1744 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0                                                            0x016c
1745 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1                                                            0x0170
1746 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2                                                            0x0174
1747 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3                                                            0x0178
1748 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0                                                     0x0188
1749 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1                                                     0x018c
1750 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2                                                     0x0190
1751 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3                                                     0x0194
1752 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST                                                    0x0200
1753 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP                                                            0x0204
1754 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL                                                           0x0208
1755 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP                                                            0x020c
1756 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL                                                           0x0210
1757 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP                                                            0x0214
1758 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL                                                           0x0218
1759 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP                                                            0x021c
1760 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL                                                           0x0220
1761 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP                                                            0x0224
1762 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL                                                           0x0228
1763 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP                                                            0x022c
1764 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL                                                           0x0230
1765 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST                                             0x0240
1766 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT                                              0x0244
1767 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA                                                     0x0248
1768 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP                                                      0x024c
1769 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST                                                    0x0250
1770 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP                                                             0x0254
1771 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR                                               0x0258
1772 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS                                                          0x025c
1773 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL                                                            0x025e
1774 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                            0x0260
1775 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                            0x0261
1776 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                            0x0262
1777 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                            0x0263
1778 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                            0x0264
1779 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                            0x0265
1780 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                            0x0266
1781 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                            0x0267
1782 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST                                                    0x02a0
1783 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP                                                             0x02a4
1784 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL                                                            0x02a6
1785 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST                                                  0x02d0
1786 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP                                                           0x02d4
1787 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL                                                          0x02d6
1788 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST                                                    0x0328
1789 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP                                                             0x032c
1790 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL                                                            0x032e
1791 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST                                               0x0370
1792 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP                                                        0x0374
1793 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CNTL                                                       0x0378
1794 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_0                                                      0x037c
1795 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_1                                                      0x037e
1796 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_2                                                      0x0380
1797 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_3                                                      0x0382
1798 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_4                                                      0x0384
1799 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_5                                                      0x0386
1800 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_6                                                      0x0388
1801 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_7                                                      0x038a
1802 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_8                                                      0x038c
1803 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_9                                                      0x038e
1804 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_10                                                     0x0390
1805 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_11                                                     0x0392
1806 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_12                                                     0x0394
1807 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_13                                                     0x0396
1808 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_14                                                     0x0398
1809 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_15                                                     0x039a
1810 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_16                                                     0x039c
1811 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_17                                                     0x039e
1812 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_18                                                     0x03a0
1813 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_19                                                     0x03a2
1814 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_20                                                     0x03a4
1815 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_21                                                     0x03a6
1816 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_22                                                     0x03a8
1817 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_23                                                     0x03aa
1818 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_24                                                     0x03ac
1819 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_25                                                     0x03ae
1820 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_26                                                     0x03b0
1821 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_27                                                     0x03b2
1822 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_28                                                     0x03b4
1823 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_29                                                     0x03b6
1824 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_30                                                     0x03b8
1825 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_31                                                     0x03ba
1826 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_32                                                     0x03bc
1827 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_33                                                     0x03be
1828 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_34                                                     0x03c0
1829 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_35                                                     0x03c2
1830 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_36                                                     0x03c4
1831 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_37                                                     0x03c6
1832 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_38                                                     0x03c8
1833 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_39                                                     0x03ca
1834 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_40                                                     0x03cc
1835 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_41                                                     0x03ce
1836 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_42                                                     0x03d0
1837 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_43                                                     0x03d2
1838 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_44                                                     0x03d4
1839 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_45                                                     0x03d6
1840 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_46                                                     0x03d8
1841 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_47                                                     0x03da
1842 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_48                                                     0x03dc
1843 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_49                                                     0x03de
1844 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_50                                                     0x03e0
1845 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_51                                                     0x03e2
1846 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_52                                                     0x03e4
1847 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_53                                                     0x03e6
1848 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_54                                                     0x03e8
1849 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_55                                                     0x03ea
1850 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_56                                                     0x03ec
1851 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_57                                                     0x03ee
1852 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_58                                                     0x03f0
1853 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_59                                                     0x03f2
1854 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_60                                                     0x03f4
1855 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_61                                                     0x03f6
1856 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_62                                                     0x03f8
1857 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_63                                                     0x03fa
1858 
1859 
1860 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp
1861 // base address: 0x0
1862 #define cfgBIF_CFG_DEV0_EPF3_0_VENDOR_ID                                                                0x0000
1863 #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_ID                                                                0x0002
1864 #define cfgBIF_CFG_DEV0_EPF3_0_COMMAND                                                                  0x0004
1865 #define cfgBIF_CFG_DEV0_EPF3_0_STATUS                                                                   0x0006
1866 #define cfgBIF_CFG_DEV0_EPF3_0_REVISION_ID                                                              0x0008
1867 #define cfgBIF_CFG_DEV0_EPF3_0_PROG_INTERFACE                                                           0x0009
1868 #define cfgBIF_CFG_DEV0_EPF3_0_SUB_CLASS                                                                0x000a
1869 #define cfgBIF_CFG_DEV0_EPF3_0_BASE_CLASS                                                               0x000b
1870 #define cfgBIF_CFG_DEV0_EPF3_0_CACHE_LINE                                                               0x000c
1871 #define cfgBIF_CFG_DEV0_EPF3_0_LATENCY                                                                  0x000d
1872 #define cfgBIF_CFG_DEV0_EPF3_0_HEADER                                                                   0x000e
1873 #define cfgBIF_CFG_DEV0_EPF3_0_BIST                                                                     0x000f
1874 #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_1                                                              0x0010
1875 #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_2                                                              0x0014
1876 #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_3                                                              0x0018
1877 #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_4                                                              0x001c
1878 #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_5                                                              0x0020
1879 #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_6                                                              0x0024
1880 #define cfgBIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR                                                          0x0028
1881 #define cfgBIF_CFG_DEV0_EPF3_0_ADAPTER_ID                                                               0x002c
1882 #define cfgBIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR                                                            0x0030
1883 #define cfgBIF_CFG_DEV0_EPF3_0_CAP_PTR                                                                  0x0034
1884 #define cfgBIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE                                                           0x003c
1885 #define cfgBIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN                                                            0x003d
1886 #define cfgBIF_CFG_DEV0_EPF3_0_MIN_GRANT                                                                0x003e
1887 #define cfgBIF_CFG_DEV0_EPF3_0_MAX_LATENCY                                                              0x003f
1888 #define cfgBIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST                                                          0x0048
1889 #define cfgBIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W                                                             0x004c
1890 #define cfgBIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST                                                             0x0050
1891 #define cfgBIF_CFG_DEV0_EPF3_0_PMI_CAP                                                                  0x0052
1892 #define cfgBIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL                                                          0x0054
1893 #define cfgBIF_CFG_DEV0_EPF3_0_SBRN                                                                     0x0060
1894 #define cfgBIF_CFG_DEV0_EPF3_0_FLADJ                                                                    0x0061
1895 #define cfgBIF_CFG_DEV0_EPF3_0_DBESL_DBESLD                                                             0x0062
1896 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST                                                            0x0064
1897 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CAP                                                                 0x0066
1898 #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CAP                                                               0x0068
1899 #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL                                                              0x006c
1900 #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS                                                            0x006e
1901 #define cfgBIF_CFG_DEV0_EPF3_0_LINK_CAP                                                                 0x0070
1902 #define cfgBIF_CFG_DEV0_EPF3_0_LINK_CNTL                                                                0x0074
1903 #define cfgBIF_CFG_DEV0_EPF3_0_LINK_STATUS                                                              0x0076
1904 #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CAP2                                                              0x0088
1905 #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2                                                             0x008c
1906 #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2                                                           0x008e
1907 #define cfgBIF_CFG_DEV0_EPF3_0_LINK_CAP2                                                                0x0090
1908 #define cfgBIF_CFG_DEV0_EPF3_0_LINK_CNTL2                                                               0x0094
1909 #define cfgBIF_CFG_DEV0_EPF3_0_LINK_STATUS2                                                             0x0096
1910 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST                                                             0x00a0
1911 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL                                                             0x00a2
1912 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO                                                          0x00a4
1913 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI                                                          0x00a8
1914 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA                                                             0x00a8
1915 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MASK                                                                 0x00ac
1916 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64                                                          0x00ac
1917 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MASK_64                                                              0x00b0
1918 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_PENDING                                                              0x00b0
1919 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_PENDING_64                                                           0x00b4
1920 #define cfgBIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST                                                            0x00c0
1921 #define cfgBIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL                                                            0x00c2
1922 #define cfgBIF_CFG_DEV0_EPF3_0_MSIX_TABLE                                                               0x00c4
1923 #define cfgBIF_CFG_DEV0_EPF3_0_MSIX_PBA                                                                 0x00c8
1924 #define cfgBIF_CFG_DEV0_EPF3_0_SATA_CAP_0                                                               0x00d0
1925 #define cfgBIF_CFG_DEV0_EPF3_0_SATA_CAP_1                                                               0x00d4
1926 #define cfgBIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX                                                           0x00d8
1927 #define cfgBIF_CFG_DEV0_EPF3_0_SATA_IDP_DATA                                                            0x00dc
1928 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                        0x0100
1929 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR                                                 0x0104
1930 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1                                                    0x0108
1931 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2                                                    0x010c
1932 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                            0x0150
1933 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS                                                   0x0154
1934 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK                                                     0x0158
1935 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY                                                 0x015c
1936 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS                                                     0x0160
1937 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK                                                       0x0164
1938 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL                                                    0x0168
1939 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0                                                            0x016c
1940 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1                                                            0x0170
1941 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2                                                            0x0174
1942 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3                                                            0x0178
1943 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0                                                     0x0188
1944 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1                                                     0x018c
1945 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2                                                     0x0190
1946 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3                                                     0x0194
1947 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST                                                    0x0200
1948 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP                                                            0x0204
1949 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL                                                           0x0208
1950 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP                                                            0x020c
1951 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL                                                           0x0210
1952 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP                                                            0x0214
1953 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL                                                           0x0218
1954 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP                                                            0x021c
1955 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL                                                           0x0220
1956 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP                                                            0x0224
1957 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL                                                           0x0228
1958 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP                                                            0x022c
1959 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL                                                           0x0230
1960 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST                                             0x0240
1961 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT                                              0x0244
1962 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA                                                     0x0248
1963 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP                                                      0x024c
1964 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST                                                    0x0250
1965 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP                                                             0x0254
1966 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR                                               0x0258
1967 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS                                                          0x025c
1968 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL                                                            0x025e
1969 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                            0x0260
1970 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                            0x0261
1971 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                            0x0262
1972 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                            0x0263
1973 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                            0x0264
1974 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                            0x0265
1975 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                            0x0266
1976 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                            0x0267
1977 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST                                                    0x02a0
1978 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP                                                             0x02a4
1979 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL                                                            0x02a6
1980 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST                                                  0x02d0
1981 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP                                                           0x02d4
1982 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL                                                          0x02d6
1983 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST                                                    0x0328
1984 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP                                                             0x032c
1985 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL                                                            0x032e
1986 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST                                               0x0370
1987 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP                                                        0x0374
1988 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CNTL                                                       0x0378
1989 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_0                                                      0x037c
1990 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_1                                                      0x037e
1991 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_2                                                      0x0380
1992 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_3                                                      0x0382
1993 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_4                                                      0x0384
1994 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_5                                                      0x0386
1995 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_6                                                      0x0388
1996 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_7                                                      0x038a
1997 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_8                                                      0x038c
1998 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_9                                                      0x038e
1999 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_10                                                     0x0390
2000 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_11                                                     0x0392
2001 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_12                                                     0x0394
2002 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_13                                                     0x0396
2003 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_14                                                     0x0398
2004 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_15                                                     0x039a
2005 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_16                                                     0x039c
2006 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_17                                                     0x039e
2007 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_18                                                     0x03a0
2008 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_19                                                     0x03a2
2009 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_20                                                     0x03a4
2010 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_21                                                     0x03a6
2011 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_22                                                     0x03a8
2012 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_23                                                     0x03aa
2013 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_24                                                     0x03ac
2014 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_25                                                     0x03ae
2015 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_26                                                     0x03b0
2016 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_27                                                     0x03b2
2017 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_28                                                     0x03b4
2018 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_29                                                     0x03b6
2019 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_30                                                     0x03b8
2020 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_31                                                     0x03ba
2021 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_32                                                     0x03bc
2022 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_33                                                     0x03be
2023 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_34                                                     0x03c0
2024 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_35                                                     0x03c2
2025 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_36                                                     0x03c4
2026 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_37                                                     0x03c6
2027 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_38                                                     0x03c8
2028 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_39                                                     0x03ca
2029 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_40                                                     0x03cc
2030 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_41                                                     0x03ce
2031 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_42                                                     0x03d0
2032 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_43                                                     0x03d2
2033 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_44                                                     0x03d4
2034 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_45                                                     0x03d6
2035 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_46                                                     0x03d8
2036 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_47                                                     0x03da
2037 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_48                                                     0x03dc
2038 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_49                                                     0x03de
2039 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_50                                                     0x03e0
2040 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_51                                                     0x03e2
2041 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_52                                                     0x03e4
2042 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_53                                                     0x03e6
2043 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_54                                                     0x03e8
2044 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_55                                                     0x03ea
2045 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_56                                                     0x03ec
2046 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_57                                                     0x03ee
2047 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_58                                                     0x03f0
2048 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_59                                                     0x03f2
2049 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_60                                                     0x03f4
2050 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_61                                                     0x03f6
2051 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_62                                                     0x03f8
2052 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_63                                                     0x03fa
2053 
2054 
2055 // addressBlock: nbio_nbif0_bif_cfg_dev0_swds_bifcfgdecp
2056 // base address: 0x0
2057 #define cfgBIF_CFG_DEV0_SWDS0_VENDOR_ID                                                                 0x0000
2058 #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_ID                                                                 0x0002
2059 #define cfgBIF_CFG_DEV0_SWDS0_COMMAND                                                                   0x0004
2060 #define cfgBIF_CFG_DEV0_SWDS0_STATUS                                                                    0x0006
2061 #define cfgBIF_CFG_DEV0_SWDS0_REVISION_ID                                                               0x0008
2062 #define cfgBIF_CFG_DEV0_SWDS0_PROG_INTERFACE                                                            0x0009
2063 #define cfgBIF_CFG_DEV0_SWDS0_SUB_CLASS                                                                 0x000a
2064 #define cfgBIF_CFG_DEV0_SWDS0_BASE_CLASS                                                                0x000b
2065 #define cfgBIF_CFG_DEV0_SWDS0_CACHE_LINE                                                                0x000c
2066 #define cfgBIF_CFG_DEV0_SWDS0_LATENCY                                                                   0x000d
2067 #define cfgBIF_CFG_DEV0_SWDS0_HEADER                                                                    0x000e
2068 #define cfgBIF_CFG_DEV0_SWDS0_BIST                                                                      0x000f
2069 #define cfgBIF_CFG_DEV0_SWDS0_BASE_ADDR_1                                                               0x0010
2070 #define cfgBIF_CFG_DEV0_SWDS0_BASE_ADDR_2                                                               0x0014
2071 #define cfgBIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY                                                    0x0018
2072 #define cfgBIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT                                                             0x001c
2073 #define cfgBIF_CFG_DEV0_SWDS0_SECONDARY_STATUS                                                          0x001e
2074 #define cfgBIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT                                                            0x0020
2075 #define cfgBIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT                                                           0x0024
2076 #define cfgBIF_CFG_DEV0_SWDS0_PREF_BASE_UPPER                                                           0x0028
2077 #define cfgBIF_CFG_DEV0_SWDS0_PREF_LIMIT_UPPER                                                          0x002c
2078 #define cfgBIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI                                                          0x0030
2079 #define cfgBIF_CFG_DEV0_SWDS0_CAP_PTR                                                                   0x0034
2080 #define cfgBIF_CFG_DEV0_SWDS0_ROM_BASE_ADDR                                                             0x0038
2081 #define cfgBIF_CFG_DEV0_SWDS0_INTERRUPT_LINE                                                            0x003c
2082 #define cfgBIF_CFG_DEV0_SWDS0_INTERRUPT_PIN                                                             0x003d
2083 #define cfgBIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL                                                           0x003e
2084 #define cfgBIF_CFG_DEV0_SWDS0_PMI_CAP_LIST                                                              0x0050
2085 #define cfgBIF_CFG_DEV0_SWDS0_PMI_CAP                                                                   0x0052
2086 #define cfgBIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL                                                           0x0054
2087 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST                                                             0x0058
2088 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_CAP                                                                  0x005a
2089 #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CAP                                                                0x005c
2090 #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CNTL                                                               0x0060
2091 #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_STATUS                                                             0x0062
2092 #define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP                                                                  0x0064
2093 #define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL                                                                 0x0068
2094 #define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS                                                               0x006a
2095 #define cfgBIF_CFG_DEV0_SWDS0_SLOT_CAP                                                                  0x006c
2096 #define cfgBIF_CFG_DEV0_SWDS0_SLOT_CNTL                                                                 0x0070
2097 #define cfgBIF_CFG_DEV0_SWDS0_SLOT_STATUS                                                               0x0072
2098 #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CAP2                                                               0x007c
2099 #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CNTL2                                                              0x0080
2100 #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_STATUS2                                                            0x0082
2101 #define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP2                                                                 0x0084
2102 #define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL2                                                                0x0088
2103 #define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS2                                                              0x008a
2104 #define cfgBIF_CFG_DEV0_SWDS0_SLOT_CAP2                                                                 0x008c
2105 #define cfgBIF_CFG_DEV0_SWDS0_SLOT_CNTL2                                                                0x0090
2106 #define cfgBIF_CFG_DEV0_SWDS0_SLOT_STATUS2                                                              0x0092
2107 #define cfgBIF_CFG_DEV0_SWDS0_MSI_CAP_LIST                                                              0x00a0
2108 #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL                                                              0x00a2
2109 #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_LO                                                           0x00a4
2110 #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_HI                                                           0x00a8
2111 #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_DATA                                                              0x00a8
2112 #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_DATA_64                                                           0x00ac
2113 #define cfgBIF_CFG_DEV0_SWDS0_SSID_CAP_LIST                                                             0x00c0
2114 #define cfgBIF_CFG_DEV0_SWDS0_SSID_CAP                                                                  0x00c4
2115 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                         0x0100
2116 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR                                                  0x0104
2117 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC1                                                     0x0108
2118 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC2                                                     0x010c
2119 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST                                                      0x0110
2120 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1                                                     0x0114
2121 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2                                                     0x0118
2122 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL                                                         0x011c
2123 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_STATUS                                                       0x011e
2124 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP                                                     0x0120
2125 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL                                                    0x0124
2126 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS                                                  0x012a
2127 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP                                                     0x012c
2128 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL                                                    0x0130
2129 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS                                                  0x0136
2130 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                          0x0140
2131 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW1                                                   0x0144
2132 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW2                                                   0x0148
2133 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                             0x0150
2134 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS                                                    0x0154
2135 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK                                                      0x0158
2136 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY                                                  0x015c
2137 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS                                                      0x0160
2138 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK                                                        0x0164
2139 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL                                                     0x0168
2140 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG0                                                             0x016c
2141 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG1                                                             0x0170
2142 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG2                                                             0x0174
2143 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG3                                                             0x0178
2144 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG0                                                      0x0188
2145 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG1                                                      0x018c
2146 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG2                                                      0x0190
2147 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG3                                                      0x0194
2148 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST                                               0x0270
2149 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3                                                           0x0274
2150 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS                                                    0x0278
2151 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL                                             0x027c
2152 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL                                             0x027e
2153 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL                                             0x0280
2154 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL                                             0x0282
2155 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL                                             0x0284
2156 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL                                             0x0286
2157 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL                                             0x0288
2158 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL                                             0x028a
2159 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL                                             0x028c
2160 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL                                             0x028e
2161 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL                                            0x0290
2162 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL                                            0x0292
2163 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL                                            0x0294
2164 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL                                            0x0296
2165 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL                                            0x0298
2166 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL                                            0x029a
2167 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST                                                     0x02a0
2168 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP                                                              0x02a4
2169 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL                                                             0x02a6
2170 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_DLF_ENH_CAP_LIST                                                     0x0400
2171 #define cfgBIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_CAP                                                     0x0404
2172 #define cfgBIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_STATUS                                                  0x0408
2173 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PHY_16GT_ENH_CAP_LIST                                                0x0410
2174 #define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP_16GT                                                             0x0414
2175 #define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL_16GT                                                            0x0418
2176 #define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT                                                          0x041c
2177 #define cfgBIF_CFG_DEV0_SWDS0_LOCAL_PARITY_MISMATCH_STATUS_16GT                                         0x0420
2178 #define cfgBIF_CFG_DEV0_SWDS0_RTM1_PARITY_MISMATCH_STATUS_16GT                                          0x0424
2179 #define cfgBIF_CFG_DEV0_SWDS0_RTM2_PARITY_MISMATCH_STATUS_16GT                                          0x0428
2180 #define cfgBIF_CFG_DEV0_SWDS0_LANE_0_EQUALIZATION_CNTL_16GT                                             0x0430
2181 #define cfgBIF_CFG_DEV0_SWDS0_LANE_1_EQUALIZATION_CNTL_16GT                                             0x0431
2182 #define cfgBIF_CFG_DEV0_SWDS0_LANE_2_EQUALIZATION_CNTL_16GT                                             0x0432
2183 #define cfgBIF_CFG_DEV0_SWDS0_LANE_3_EQUALIZATION_CNTL_16GT                                             0x0433
2184 #define cfgBIF_CFG_DEV0_SWDS0_LANE_4_EQUALIZATION_CNTL_16GT                                             0x0434
2185 #define cfgBIF_CFG_DEV0_SWDS0_LANE_5_EQUALIZATION_CNTL_16GT                                             0x0435
2186 #define cfgBIF_CFG_DEV0_SWDS0_LANE_6_EQUALIZATION_CNTL_16GT                                             0x0436
2187 #define cfgBIF_CFG_DEV0_SWDS0_LANE_7_EQUALIZATION_CNTL_16GT                                             0x0437
2188 #define cfgBIF_CFG_DEV0_SWDS0_LANE_8_EQUALIZATION_CNTL_16GT                                             0x0438
2189 #define cfgBIF_CFG_DEV0_SWDS0_LANE_9_EQUALIZATION_CNTL_16GT                                             0x0439
2190 #define cfgBIF_CFG_DEV0_SWDS0_LANE_10_EQUALIZATION_CNTL_16GT                                            0x043a
2191 #define cfgBIF_CFG_DEV0_SWDS0_LANE_11_EQUALIZATION_CNTL_16GT                                            0x043b
2192 #define cfgBIF_CFG_DEV0_SWDS0_LANE_12_EQUALIZATION_CNTL_16GT                                            0x043c
2193 #define cfgBIF_CFG_DEV0_SWDS0_LANE_13_EQUALIZATION_CNTL_16GT                                            0x043d
2194 #define cfgBIF_CFG_DEV0_SWDS0_LANE_14_EQUALIZATION_CNTL_16GT                                            0x043e
2195 #define cfgBIF_CFG_DEV0_SWDS0_LANE_15_EQUALIZATION_CNTL_16GT                                            0x043f
2196 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_MARGINING_ENH_CAP_LIST                                               0x0440
2197 #define cfgBIF_CFG_DEV0_SWDS0_MARGINING_PORT_CAP                                                        0x0444
2198 #define cfgBIF_CFG_DEV0_SWDS0_MARGINING_PORT_STATUS                                                     0x0446
2199 #define cfgBIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_CNTL                                                0x0448
2200 #define cfgBIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_STATUS                                              0x044a
2201 #define cfgBIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_CNTL                                                0x044c
2202 #define cfgBIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_STATUS                                              0x044e
2203 #define cfgBIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_CNTL                                                0x0450
2204 #define cfgBIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_STATUS                                              0x0452
2205 #define cfgBIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_CNTL                                                0x0454
2206 #define cfgBIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_STATUS                                              0x0456
2207 #define cfgBIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_CNTL                                                0x0458
2208 #define cfgBIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_STATUS                                              0x045a
2209 #define cfgBIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_CNTL                                                0x045c
2210 #define cfgBIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_STATUS                                              0x045e
2211 #define cfgBIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_CNTL                                                0x0460
2212 #define cfgBIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_STATUS                                              0x0462
2213 #define cfgBIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_CNTL                                                0x0464
2214 #define cfgBIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_STATUS                                              0x0466
2215 #define cfgBIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_CNTL                                                0x0468
2216 #define cfgBIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_STATUS                                              0x046a
2217 #define cfgBIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_CNTL                                                0x046c
2218 #define cfgBIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_STATUS                                              0x046e
2219 #define cfgBIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_CNTL                                               0x0470
2220 #define cfgBIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_STATUS                                             0x0472
2221 #define cfgBIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL                                               0x0474
2222 #define cfgBIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_STATUS                                             0x0476
2223 #define cfgBIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_CNTL                                               0x0478
2224 #define cfgBIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_STATUS                                             0x047a
2225 #define cfgBIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_CNTL                                               0x047c
2226 #define cfgBIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_STATUS                                             0x047e
2227 #define cfgBIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_CNTL                                               0x0480
2228 #define cfgBIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_STATUS                                             0x0482
2229 #define cfgBIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_CNTL                                               0x0484
2230 #define cfgBIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_STATUS                                             0x0486
2231 
2232 
2233 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp
2234 // base address: 0x0
2235 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID                                                            0x0000
2236 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID                                                            0x0002
2237 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_COMMAND                                                              0x0004
2238 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_STATUS                                                               0x0006
2239 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID                                                          0x0008
2240 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE                                                       0x0009
2241 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS                                                            0x000a
2242 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS                                                           0x000b
2243 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE                                                           0x000c
2244 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LATENCY                                                              0x000d
2245 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_HEADER                                                               0x000e
2246 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BIST                                                                 0x000f
2247 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1                                                          0x0010
2248 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2                                                          0x0014
2249 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3                                                          0x0018
2250 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4                                                          0x001c
2251 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5                                                          0x0020
2252 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6                                                          0x0024
2253 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_CARDBUS_CIS_PTR                                                      0x0028
2254 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID                                                           0x002c
2255 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR                                                        0x0030
2256 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR                                                              0x0034
2257 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE                                                       0x003c
2258 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN                                                        0x003d
2259 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MIN_GRANT                                                            0x003e
2260 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MAX_LATENCY                                                          0x003f
2261 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST                                                        0x0064
2262 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP                                                             0x0066
2263 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP                                                           0x0068
2264 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL                                                          0x006c
2265 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS                                                        0x006e
2266 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP                                                             0x0070
2267 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL                                                            0x0074
2268 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS                                                          0x0076
2269 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2                                                          0x0088
2270 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2                                                         0x008c
2271 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2                                                       0x008e
2272 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2                                                            0x0090
2273 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2                                                           0x0094
2274 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2                                                         0x0096
2275 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST                                                         0x00a0
2276 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL                                                         0x00a2
2277 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO                                                      0x00a4
2278 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI                                                      0x00a8
2279 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA                                                         0x00a8
2280 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK                                                             0x00ac
2281 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64                                                      0x00ac
2282 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64                                                          0x00b0
2283 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING                                                          0x00b0
2284 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64                                                       0x00b4
2285 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST                                                        0x00c0
2286 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL                                                        0x00c2
2287 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE                                                           0x00c4
2288 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA                                                             0x00c8
2289 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                    0x0100
2290 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR                                             0x0104
2291 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1                                                0x0108
2292 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2                                                0x010c
2293 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                        0x0150
2294 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS                                               0x0154
2295 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK                                                 0x0158
2296 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY                                             0x015c
2297 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS                                                 0x0160
2298 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK                                                   0x0164
2299 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL                                                0x0168
2300 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0                                                        0x016c
2301 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1                                                        0x0170
2302 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2                                                        0x0174
2303 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3                                                        0x0178
2304 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0                                                 0x0188
2305 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1                                                 0x018c
2306 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2                                                 0x0190
2307 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3                                                 0x0194
2308 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST                                                0x02b0
2309 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP                                                         0x02b4
2310 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL                                                        0x02b6
2311 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST                                                0x0328
2312 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP                                                         0x032c
2313 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL                                                        0x032e
2314 
2315 
2316 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp
2317 // base address: 0x0
2318 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID                                                            0x0000
2319 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID                                                            0x0002
2320 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_COMMAND                                                              0x0004
2321 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_STATUS                                                               0x0006
2322 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID                                                          0x0008
2323 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE                                                       0x0009
2324 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS                                                            0x000a
2325 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS                                                           0x000b
2326 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE                                                           0x000c
2327 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LATENCY                                                              0x000d
2328 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_HEADER                                                               0x000e
2329 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BIST                                                                 0x000f
2330 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1                                                          0x0010
2331 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2                                                          0x0014
2332 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3                                                          0x0018
2333 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4                                                          0x001c
2334 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5                                                          0x0020
2335 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6                                                          0x0024
2336 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_CARDBUS_CIS_PTR                                                      0x0028
2337 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID                                                           0x002c
2338 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR                                                        0x0030
2339 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR                                                              0x0034
2340 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE                                                       0x003c
2341 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN                                                        0x003d
2342 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MIN_GRANT                                                            0x003e
2343 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MAX_LATENCY                                                          0x003f
2344 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST                                                        0x0064
2345 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP                                                             0x0066
2346 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP                                                           0x0068
2347 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL                                                          0x006c
2348 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS                                                        0x006e
2349 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP                                                             0x0070
2350 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL                                                            0x0074
2351 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS                                                          0x0076
2352 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2                                                          0x0088
2353 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2                                                         0x008c
2354 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2                                                       0x008e
2355 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2                                                            0x0090
2356 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2                                                           0x0094
2357 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2                                                         0x0096
2358 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST                                                         0x00a0
2359 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL                                                         0x00a2
2360 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO                                                      0x00a4
2361 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI                                                      0x00a8
2362 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA                                                         0x00a8
2363 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK                                                             0x00ac
2364 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64                                                      0x00ac
2365 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64                                                          0x00b0
2366 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING                                                          0x00b0
2367 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64                                                       0x00b4
2368 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST                                                        0x00c0
2369 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL                                                        0x00c2
2370 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE                                                           0x00c4
2371 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA                                                             0x00c8
2372 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                    0x0100
2373 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR                                             0x0104
2374 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1                                                0x0108
2375 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2                                                0x010c
2376 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                        0x0150
2377 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS                                               0x0154
2378 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK                                                 0x0158
2379 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY                                             0x015c
2380 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS                                                 0x0160
2381 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK                                                   0x0164
2382 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL                                                0x0168
2383 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0                                                        0x016c
2384 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1                                                        0x0170
2385 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2                                                        0x0174
2386 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3                                                        0x0178
2387 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0                                                 0x0188
2388 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1                                                 0x018c
2389 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2                                                 0x0190
2390 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3                                                 0x0194
2391 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST                                                0x02b0
2392 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP                                                         0x02b4
2393 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL                                                        0x02b6
2394 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST                                                0x0328
2395 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP                                                         0x032c
2396 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL                                                        0x032e
2397 
2398 
2399 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp
2400 // base address: 0x0
2401 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID                                                            0x0000
2402 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID                                                            0x0002
2403 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_COMMAND                                                              0x0004
2404 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_STATUS                                                               0x0006
2405 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID                                                          0x0008
2406 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE                                                       0x0009
2407 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS                                                            0x000a
2408 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS                                                           0x000b
2409 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE                                                           0x000c
2410 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LATENCY                                                              0x000d
2411 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_HEADER                                                               0x000e
2412 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BIST                                                                 0x000f
2413 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1                                                          0x0010
2414 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2                                                          0x0014
2415 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3                                                          0x0018
2416 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4                                                          0x001c
2417 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5                                                          0x0020
2418 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6                                                          0x0024
2419 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_CARDBUS_CIS_PTR                                                      0x0028
2420 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID                                                           0x002c
2421 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR                                                        0x0030
2422 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR                                                              0x0034
2423 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE                                                       0x003c
2424 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN                                                        0x003d
2425 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MIN_GRANT                                                            0x003e
2426 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MAX_LATENCY                                                          0x003f
2427 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST                                                        0x0064
2428 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP                                                             0x0066
2429 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP                                                           0x0068
2430 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL                                                          0x006c
2431 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS                                                        0x006e
2432 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP                                                             0x0070
2433 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL                                                            0x0074
2434 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS                                                          0x0076
2435 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2                                                          0x0088
2436 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2                                                         0x008c
2437 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2                                                       0x008e
2438 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2                                                            0x0090
2439 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2                                                           0x0094
2440 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2                                                         0x0096
2441 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST                                                         0x00a0
2442 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL                                                         0x00a2
2443 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO                                                      0x00a4
2444 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI                                                      0x00a8
2445 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA                                                         0x00a8
2446 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK                                                             0x00ac
2447 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64                                                      0x00ac
2448 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64                                                          0x00b0
2449 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING                                                          0x00b0
2450 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64                                                       0x00b4
2451 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST                                                        0x00c0
2452 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL                                                        0x00c2
2453 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE                                                           0x00c4
2454 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA                                                             0x00c8
2455 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                    0x0100
2456 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR                                             0x0104
2457 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1                                                0x0108
2458 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2                                                0x010c
2459 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                        0x0150
2460 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS                                               0x0154
2461 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK                                                 0x0158
2462 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY                                             0x015c
2463 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS                                                 0x0160
2464 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK                                                   0x0164
2465 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL                                                0x0168
2466 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0                                                        0x016c
2467 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1                                                        0x0170
2468 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2                                                        0x0174
2469 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3                                                        0x0178
2470 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0                                                 0x0188
2471 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1                                                 0x018c
2472 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2                                                 0x0190
2473 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3                                                 0x0194
2474 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST                                                0x02b0
2475 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP                                                         0x02b4
2476 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL                                                        0x02b6
2477 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST                                                0x0328
2478 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP                                                         0x032c
2479 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL                                                        0x032e
2480 
2481 
2482 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp
2483 // base address: 0x0
2484 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID                                                            0x0000
2485 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID                                                            0x0002
2486 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_COMMAND                                                              0x0004
2487 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_STATUS                                                               0x0006
2488 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID                                                          0x0008
2489 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE                                                       0x0009
2490 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS                                                            0x000a
2491 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS                                                           0x000b
2492 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE                                                           0x000c
2493 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LATENCY                                                              0x000d
2494 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_HEADER                                                               0x000e
2495 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BIST                                                                 0x000f
2496 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1                                                          0x0010
2497 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2                                                          0x0014
2498 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3                                                          0x0018
2499 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4                                                          0x001c
2500 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5                                                          0x0020
2501 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6                                                          0x0024
2502 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_CARDBUS_CIS_PTR                                                      0x0028
2503 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID                                                           0x002c
2504 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR                                                        0x0030
2505 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR                                                              0x0034
2506 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE                                                       0x003c
2507 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN                                                        0x003d
2508 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MIN_GRANT                                                            0x003e
2509 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MAX_LATENCY                                                          0x003f
2510 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST                                                        0x0064
2511 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP                                                             0x0066
2512 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP                                                           0x0068
2513 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL                                                          0x006c
2514 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS                                                        0x006e
2515 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP                                                             0x0070
2516 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL                                                            0x0074
2517 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS                                                          0x0076
2518 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2                                                          0x0088
2519 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2                                                         0x008c
2520 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2                                                       0x008e
2521 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2                                                            0x0090
2522 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2                                                           0x0094
2523 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2                                                         0x0096
2524 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST                                                         0x00a0
2525 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL                                                         0x00a2
2526 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO                                                      0x00a4
2527 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI                                                      0x00a8
2528 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA                                                         0x00a8
2529 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK                                                             0x00ac
2530 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64                                                      0x00ac
2531 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64                                                          0x00b0
2532 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING                                                          0x00b0
2533 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64                                                       0x00b4
2534 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST                                                        0x00c0
2535 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL                                                        0x00c2
2536 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE                                                           0x00c4
2537 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA                                                             0x00c8
2538 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                    0x0100
2539 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR                                             0x0104
2540 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1                                                0x0108
2541 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2                                                0x010c
2542 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                        0x0150
2543 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS                                               0x0154
2544 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK                                                 0x0158
2545 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY                                             0x015c
2546 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS                                                 0x0160
2547 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK                                                   0x0164
2548 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL                                                0x0168
2549 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0                                                        0x016c
2550 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1                                                        0x0170
2551 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2                                                        0x0174
2552 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3                                                        0x0178
2553 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0                                                 0x0188
2554 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1                                                 0x018c
2555 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2                                                 0x0190
2556 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3                                                 0x0194
2557 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST                                                0x02b0
2558 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP                                                         0x02b4
2559 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL                                                        0x02b6
2560 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST                                                0x0328
2561 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP                                                         0x032c
2562 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL                                                        0x032e
2563 
2564 
2565 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp
2566 // base address: 0x0
2567 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID                                                            0x0000
2568 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID                                                            0x0002
2569 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_COMMAND                                                              0x0004
2570 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_STATUS                                                               0x0006
2571 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID                                                          0x0008
2572 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE                                                       0x0009
2573 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS                                                            0x000a
2574 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS                                                           0x000b
2575 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE                                                           0x000c
2576 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LATENCY                                                              0x000d
2577 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_HEADER                                                               0x000e
2578 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BIST                                                                 0x000f
2579 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1                                                          0x0010
2580 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2                                                          0x0014
2581 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3                                                          0x0018
2582 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4                                                          0x001c
2583 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5                                                          0x0020
2584 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6                                                          0x0024
2585 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_CARDBUS_CIS_PTR                                                      0x0028
2586 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID                                                           0x002c
2587 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR                                                        0x0030
2588 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR                                                              0x0034
2589 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE                                                       0x003c
2590 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN                                                        0x003d
2591 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MIN_GRANT                                                            0x003e
2592 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MAX_LATENCY                                                          0x003f
2593 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST                                                        0x0064
2594 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP                                                             0x0066
2595 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP                                                           0x0068
2596 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL                                                          0x006c
2597 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS                                                        0x006e
2598 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP                                                             0x0070
2599 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL                                                            0x0074
2600 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS                                                          0x0076
2601 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2                                                          0x0088
2602 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2                                                         0x008c
2603 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2                                                       0x008e
2604 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2                                                            0x0090
2605 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2                                                           0x0094
2606 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2                                                         0x0096
2607 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST                                                         0x00a0
2608 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL                                                         0x00a2
2609 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO                                                      0x00a4
2610 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI                                                      0x00a8
2611 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA                                                         0x00a8
2612 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK                                                             0x00ac
2613 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64                                                      0x00ac
2614 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64                                                          0x00b0
2615 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING                                                          0x00b0
2616 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64                                                       0x00b4
2617 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST                                                        0x00c0
2618 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL                                                        0x00c2
2619 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE                                                           0x00c4
2620 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA                                                             0x00c8
2621 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                    0x0100
2622 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR                                             0x0104
2623 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1                                                0x0108
2624 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2                                                0x010c
2625 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                        0x0150
2626 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS                                               0x0154
2627 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK                                                 0x0158
2628 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY                                             0x015c
2629 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS                                                 0x0160
2630 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK                                                   0x0164
2631 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL                                                0x0168
2632 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0                                                        0x016c
2633 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1                                                        0x0170
2634 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2                                                        0x0174
2635 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3                                                        0x0178
2636 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0                                                 0x0188
2637 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1                                                 0x018c
2638 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2                                                 0x0190
2639 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3                                                 0x0194
2640 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST                                                0x02b0
2641 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP                                                         0x02b4
2642 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL                                                        0x02b6
2643 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST                                                0x0328
2644 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP                                                         0x032c
2645 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL                                                        0x032e
2646 
2647 
2648 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp
2649 // base address: 0x0
2650 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID                                                            0x0000
2651 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID                                                            0x0002
2652 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_COMMAND                                                              0x0004
2653 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_STATUS                                                               0x0006
2654 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID                                                          0x0008
2655 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE                                                       0x0009
2656 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS                                                            0x000a
2657 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS                                                           0x000b
2658 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE                                                           0x000c
2659 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LATENCY                                                              0x000d
2660 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_HEADER                                                               0x000e
2661 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BIST                                                                 0x000f
2662 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1                                                          0x0010
2663 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2                                                          0x0014
2664 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3                                                          0x0018
2665 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4                                                          0x001c
2666 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5                                                          0x0020
2667 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6                                                          0x0024
2668 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_CARDBUS_CIS_PTR                                                      0x0028
2669 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID                                                           0x002c
2670 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR                                                        0x0030
2671 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR                                                              0x0034
2672 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE                                                       0x003c
2673 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN                                                        0x003d
2674 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MIN_GRANT                                                            0x003e
2675 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MAX_LATENCY                                                          0x003f
2676 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST                                                        0x0064
2677 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP                                                             0x0066
2678 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP                                                           0x0068
2679 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL                                                          0x006c
2680 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS                                                        0x006e
2681 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP                                                             0x0070
2682 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL                                                            0x0074
2683 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS                                                          0x0076
2684 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2                                                          0x0088
2685 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2                                                         0x008c
2686 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2                                                       0x008e
2687 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2                                                            0x0090
2688 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2                                                           0x0094
2689 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2                                                         0x0096
2690 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST                                                         0x00a0
2691 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL                                                         0x00a2
2692 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO                                                      0x00a4
2693 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI                                                      0x00a8
2694 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA                                                         0x00a8
2695 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK                                                             0x00ac
2696 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64                                                      0x00ac
2697 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64                                                          0x00b0
2698 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING                                                          0x00b0
2699 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64                                                       0x00b4
2700 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST                                                        0x00c0
2701 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL                                                        0x00c2
2702 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE                                                           0x00c4
2703 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA                                                             0x00c8
2704 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                    0x0100
2705 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR                                             0x0104
2706 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1                                                0x0108
2707 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2                                                0x010c
2708 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                        0x0150
2709 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS                                               0x0154
2710 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK                                                 0x0158
2711 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY                                             0x015c
2712 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS                                                 0x0160
2713 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK                                                   0x0164
2714 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL                                                0x0168
2715 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0                                                        0x016c
2716 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1                                                        0x0170
2717 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2                                                        0x0174
2718 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3                                                        0x0178
2719 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0                                                 0x0188
2720 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1                                                 0x018c
2721 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2                                                 0x0190
2722 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3                                                 0x0194
2723 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST                                                0x02b0
2724 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP                                                         0x02b4
2725 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL                                                        0x02b6
2726 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST                                                0x0328
2727 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP                                                         0x032c
2728 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL                                                        0x032e
2729 
2730 
2731 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp
2732 // base address: 0x0
2733 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID                                                            0x0000
2734 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID                                                            0x0002
2735 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_COMMAND                                                              0x0004
2736 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_STATUS                                                               0x0006
2737 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID                                                          0x0008
2738 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE                                                       0x0009
2739 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS                                                            0x000a
2740 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS                                                           0x000b
2741 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE                                                           0x000c
2742 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LATENCY                                                              0x000d
2743 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_HEADER                                                               0x000e
2744 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BIST                                                                 0x000f
2745 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1                                                          0x0010
2746 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2                                                          0x0014
2747 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3                                                          0x0018
2748 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4                                                          0x001c
2749 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5                                                          0x0020
2750 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6                                                          0x0024
2751 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_CARDBUS_CIS_PTR                                                      0x0028
2752 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID                                                           0x002c
2753 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR                                                        0x0030
2754 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR                                                              0x0034
2755 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE                                                       0x003c
2756 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN                                                        0x003d
2757 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MIN_GRANT                                                            0x003e
2758 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MAX_LATENCY                                                          0x003f
2759 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST                                                        0x0064
2760 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP                                                             0x0066
2761 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP                                                           0x0068
2762 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL                                                          0x006c
2763 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS                                                        0x006e
2764 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP                                                             0x0070
2765 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL                                                            0x0074
2766 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS                                                          0x0076
2767 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2                                                          0x0088
2768 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2                                                         0x008c
2769 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2                                                       0x008e
2770 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2                                                            0x0090
2771 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2                                                           0x0094
2772 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2                                                         0x0096
2773 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST                                                         0x00a0
2774 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL                                                         0x00a2
2775 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO                                                      0x00a4
2776 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI                                                      0x00a8
2777 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA                                                         0x00a8
2778 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK                                                             0x00ac
2779 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64                                                      0x00ac
2780 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64                                                          0x00b0
2781 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING                                                          0x00b0
2782 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64                                                       0x00b4
2783 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST                                                        0x00c0
2784 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL                                                        0x00c2
2785 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE                                                           0x00c4
2786 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA                                                             0x00c8
2787 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                    0x0100
2788 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR                                             0x0104
2789 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1                                                0x0108
2790 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2                                                0x010c
2791 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                        0x0150
2792 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS                                               0x0154
2793 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK                                                 0x0158
2794 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY                                             0x015c
2795 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS                                                 0x0160
2796 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK                                                   0x0164
2797 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL                                                0x0168
2798 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0                                                        0x016c
2799 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1                                                        0x0170
2800 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2                                                        0x0174
2801 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3                                                        0x0178
2802 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0                                                 0x0188
2803 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1                                                 0x018c
2804 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2                                                 0x0190
2805 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3                                                 0x0194
2806 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST                                                0x02b0
2807 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP                                                         0x02b4
2808 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL                                                        0x02b6
2809 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST                                                0x0328
2810 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP                                                         0x032c
2811 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL                                                        0x032e
2812 
2813 
2814 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp
2815 // base address: 0x0
2816 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID                                                            0x0000
2817 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID                                                            0x0002
2818 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_COMMAND                                                              0x0004
2819 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_STATUS                                                               0x0006
2820 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID                                                          0x0008
2821 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE                                                       0x0009
2822 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS                                                            0x000a
2823 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS                                                           0x000b
2824 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE                                                           0x000c
2825 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LATENCY                                                              0x000d
2826 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_HEADER                                                               0x000e
2827 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BIST                                                                 0x000f
2828 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1                                                          0x0010
2829 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2                                                          0x0014
2830 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3                                                          0x0018
2831 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4                                                          0x001c
2832 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5                                                          0x0020
2833 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6                                                          0x0024
2834 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_CARDBUS_CIS_PTR                                                      0x0028
2835 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID                                                           0x002c
2836 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR                                                        0x0030
2837 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR                                                              0x0034
2838 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE                                                       0x003c
2839 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN                                                        0x003d
2840 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MIN_GRANT                                                            0x003e
2841 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MAX_LATENCY                                                          0x003f
2842 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST                                                        0x0064
2843 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP                                                             0x0066
2844 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP                                                           0x0068
2845 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL                                                          0x006c
2846 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS                                                        0x006e
2847 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP                                                             0x0070
2848 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL                                                            0x0074
2849 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS                                                          0x0076
2850 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2                                                          0x0088
2851 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2                                                         0x008c
2852 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2                                                       0x008e
2853 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2                                                            0x0090
2854 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2                                                           0x0094
2855 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2                                                         0x0096
2856 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST                                                         0x00a0
2857 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL                                                         0x00a2
2858 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO                                                      0x00a4
2859 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI                                                      0x00a8
2860 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA                                                         0x00a8
2861 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK                                                             0x00ac
2862 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64                                                      0x00ac
2863 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64                                                          0x00b0
2864 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING                                                          0x00b0
2865 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64                                                       0x00b4
2866 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST                                                        0x00c0
2867 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL                                                        0x00c2
2868 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE                                                           0x00c4
2869 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA                                                             0x00c8
2870 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                    0x0100
2871 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR                                             0x0104
2872 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1                                                0x0108
2873 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2                                                0x010c
2874 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                        0x0150
2875 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS                                               0x0154
2876 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK                                                 0x0158
2877 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY                                             0x015c
2878 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS                                                 0x0160
2879 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK                                                   0x0164
2880 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL                                                0x0168
2881 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0                                                        0x016c
2882 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1                                                        0x0170
2883 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2                                                        0x0174
2884 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3                                                        0x0178
2885 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0                                                 0x0188
2886 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1                                                 0x018c
2887 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2                                                 0x0190
2888 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3                                                 0x0194
2889 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST                                                0x02b0
2890 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP                                                         0x02b4
2891 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL                                                        0x02b6
2892 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST                                                0x0328
2893 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP                                                         0x032c
2894 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL                                                        0x032e
2895 
2896 
2897 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf8_bifcfgdecp
2898 // base address: 0x0
2899 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID                                                            0x0000
2900 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID                                                            0x0002
2901 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_COMMAND                                                              0x0004
2902 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_STATUS                                                               0x0006
2903 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID                                                          0x0008
2904 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE                                                       0x0009
2905 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS                                                            0x000a
2906 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS                                                           0x000b
2907 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE                                                           0x000c
2908 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LATENCY                                                              0x000d
2909 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_HEADER                                                               0x000e
2910 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BIST                                                                 0x000f
2911 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1                                                          0x0010
2912 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2                                                          0x0014
2913 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3                                                          0x0018
2914 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4                                                          0x001c
2915 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5                                                          0x0020
2916 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6                                                          0x0024
2917 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_CARDBUS_CIS_PTR                                                      0x0028
2918 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID                                                           0x002c
2919 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR                                                        0x0030
2920 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR                                                              0x0034
2921 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE                                                       0x003c
2922 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN                                                        0x003d
2923 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MIN_GRANT                                                            0x003e
2924 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MAX_LATENCY                                                          0x003f
2925 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST                                                        0x0064
2926 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP                                                             0x0066
2927 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP                                                           0x0068
2928 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL                                                          0x006c
2929 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS                                                        0x006e
2930 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP                                                             0x0070
2931 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL                                                            0x0074
2932 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS                                                          0x0076
2933 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2                                                          0x0088
2934 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2                                                         0x008c
2935 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2                                                       0x008e
2936 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2                                                            0x0090
2937 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2                                                           0x0094
2938 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2                                                         0x0096
2939 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST                                                         0x00a0
2940 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL                                                         0x00a2
2941 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO                                                      0x00a4
2942 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI                                                      0x00a8
2943 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA                                                         0x00a8
2944 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK                                                             0x00ac
2945 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64                                                      0x00ac
2946 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64                                                          0x00b0
2947 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING                                                          0x00b0
2948 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64                                                       0x00b4
2949 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST                                                        0x00c0
2950 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL                                                        0x00c2
2951 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE                                                           0x00c4
2952 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA                                                             0x00c8
2953 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                    0x0100
2954 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR                                             0x0104
2955 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1                                                0x0108
2956 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2                                                0x010c
2957 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                        0x0150
2958 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS                                               0x0154
2959 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK                                                 0x0158
2960 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY                                             0x015c
2961 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS                                                 0x0160
2962 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK                                                   0x0164
2963 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL                                                0x0168
2964 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0                                                        0x016c
2965 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1                                                        0x0170
2966 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2                                                        0x0174
2967 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3                                                        0x0178
2968 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0                                                 0x0188
2969 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1                                                 0x018c
2970 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2                                                 0x0190
2971 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3                                                 0x0194
2972 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST                                                0x02b0
2973 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP                                                         0x02b4
2974 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL                                                        0x02b6
2975 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST                                                0x0328
2976 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP                                                         0x032c
2977 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL                                                        0x032e
2978 
2979 
2980 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf9_bifcfgdecp
2981 // base address: 0x0
2982 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID                                                            0x0000
2983 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID                                                            0x0002
2984 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_COMMAND                                                              0x0004
2985 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_STATUS                                                               0x0006
2986 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID                                                          0x0008
2987 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE                                                       0x0009
2988 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS                                                            0x000a
2989 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS                                                           0x000b
2990 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE                                                           0x000c
2991 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LATENCY                                                              0x000d
2992 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_HEADER                                                               0x000e
2993 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BIST                                                                 0x000f
2994 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1                                                          0x0010
2995 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2                                                          0x0014
2996 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3                                                          0x0018
2997 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4                                                          0x001c
2998 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5                                                          0x0020
2999 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6                                                          0x0024
3000 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_CARDBUS_CIS_PTR                                                      0x0028
3001 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID                                                           0x002c
3002 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR                                                        0x0030
3003 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR                                                              0x0034
3004 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE                                                       0x003c
3005 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN                                                        0x003d
3006 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MIN_GRANT                                                            0x003e
3007 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MAX_LATENCY                                                          0x003f
3008 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST                                                        0x0064
3009 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP                                                             0x0066
3010 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP                                                           0x0068
3011 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL                                                          0x006c
3012 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS                                                        0x006e
3013 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP                                                             0x0070
3014 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL                                                            0x0074
3015 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS                                                          0x0076
3016 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2                                                          0x0088
3017 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2                                                         0x008c
3018 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2                                                       0x008e
3019 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2                                                            0x0090
3020 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2                                                           0x0094
3021 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2                                                         0x0096
3022 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST                                                         0x00a0
3023 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL                                                         0x00a2
3024 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO                                                      0x00a4
3025 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI                                                      0x00a8
3026 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA                                                         0x00a8
3027 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK                                                             0x00ac
3028 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64                                                      0x00ac
3029 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64                                                          0x00b0
3030 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING                                                          0x00b0
3031 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64                                                       0x00b4
3032 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST                                                        0x00c0
3033 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL                                                        0x00c2
3034 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE                                                           0x00c4
3035 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA                                                             0x00c8
3036 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                    0x0100
3037 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR                                             0x0104
3038 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1                                                0x0108
3039 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2                                                0x010c
3040 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                        0x0150
3041 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS                                               0x0154
3042 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK                                                 0x0158
3043 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY                                             0x015c
3044 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS                                                 0x0160
3045 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK                                                   0x0164
3046 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL                                                0x0168
3047 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0                                                        0x016c
3048 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1                                                        0x0170
3049 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2                                                        0x0174
3050 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3                                                        0x0178
3051 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0                                                 0x0188
3052 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1                                                 0x018c
3053 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2                                                 0x0190
3054 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3                                                 0x0194
3055 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST                                                0x02b0
3056 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP                                                         0x02b4
3057 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL                                                        0x02b6
3058 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST                                                0x0328
3059 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP                                                         0x032c
3060 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL                                                        0x032e
3061 
3062 
3063 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf10_bifcfgdecp
3064 // base address: 0x0
3065 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID                                                           0x0000
3066 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID                                                           0x0002
3067 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_COMMAND                                                             0x0004
3068 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_STATUS                                                              0x0006
3069 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID                                                         0x0008
3070 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE                                                      0x0009
3071 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS                                                           0x000a
3072 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS                                                          0x000b
3073 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE                                                          0x000c
3074 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LATENCY                                                             0x000d
3075 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_HEADER                                                              0x000e
3076 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BIST                                                                0x000f
3077 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1                                                         0x0010
3078 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2                                                         0x0014
3079 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3                                                         0x0018
3080 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4                                                         0x001c
3081 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5                                                         0x0020
3082 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6                                                         0x0024
3083 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_CARDBUS_CIS_PTR                                                     0x0028
3084 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID                                                          0x002c
3085 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR                                                       0x0030
3086 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR                                                             0x0034
3087 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE                                                      0x003c
3088 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN                                                       0x003d
3089 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MIN_GRANT                                                           0x003e
3090 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MAX_LATENCY                                                         0x003f
3091 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST                                                       0x0064
3092 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP                                                            0x0066
3093 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP                                                          0x0068
3094 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL                                                         0x006c
3095 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS                                                       0x006e
3096 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP                                                            0x0070
3097 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL                                                           0x0074
3098 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS                                                         0x0076
3099 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2                                                         0x0088
3100 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2                                                        0x008c
3101 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2                                                      0x008e
3102 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2                                                           0x0090
3103 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2                                                          0x0094
3104 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2                                                        0x0096
3105 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST                                                        0x00a0
3106 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL                                                        0x00a2
3107 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO                                                     0x00a4
3108 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI                                                     0x00a8
3109 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA                                                        0x00a8
3110 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK                                                            0x00ac
3111 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64                                                     0x00ac
3112 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64                                                         0x00b0
3113 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING                                                         0x00b0
3114 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64                                                      0x00b4
3115 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST                                                       0x00c0
3116 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL                                                       0x00c2
3117 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE                                                          0x00c4
3118 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA                                                            0x00c8
3119 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0x0100
3120 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR                                            0x0104
3121 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1                                               0x0108
3122 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2                                               0x010c
3123 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0x0150
3124 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS                                              0x0154
3125 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK                                                0x0158
3126 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY                                            0x015c
3127 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS                                                0x0160
3128 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK                                                  0x0164
3129 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL                                               0x0168
3130 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0                                                       0x016c
3131 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1                                                       0x0170
3132 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2                                                       0x0174
3133 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3                                                       0x0178
3134 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0                                                0x0188
3135 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1                                                0x018c
3136 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2                                                0x0190
3137 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3                                                0x0194
3138 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST                                               0x02b0
3139 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP                                                        0x02b4
3140 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL                                                       0x02b6
3141 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST                                               0x0328
3142 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP                                                        0x032c
3143 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL                                                       0x032e
3144 
3145 
3146 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf11_bifcfgdecp
3147 // base address: 0x0
3148 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID                                                           0x0000
3149 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID                                                           0x0002
3150 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_COMMAND                                                             0x0004
3151 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_STATUS                                                              0x0006
3152 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID                                                         0x0008
3153 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE                                                      0x0009
3154 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS                                                           0x000a
3155 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS                                                          0x000b
3156 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE                                                          0x000c
3157 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LATENCY                                                             0x000d
3158 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_HEADER                                                              0x000e
3159 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BIST                                                                0x000f
3160 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1                                                         0x0010
3161 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2                                                         0x0014
3162 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3                                                         0x0018
3163 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4                                                         0x001c
3164 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5                                                         0x0020
3165 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6                                                         0x0024
3166 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_CARDBUS_CIS_PTR                                                     0x0028
3167 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID                                                          0x002c
3168 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR                                                       0x0030
3169 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR                                                             0x0034
3170 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE                                                      0x003c
3171 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN                                                       0x003d
3172 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MIN_GRANT                                                           0x003e
3173 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MAX_LATENCY                                                         0x003f
3174 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST                                                       0x0064
3175 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP                                                            0x0066
3176 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP                                                          0x0068
3177 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL                                                         0x006c
3178 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS                                                       0x006e
3179 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP                                                            0x0070
3180 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL                                                           0x0074
3181 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS                                                         0x0076
3182 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2                                                         0x0088
3183 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2                                                        0x008c
3184 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2                                                      0x008e
3185 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2                                                           0x0090
3186 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2                                                          0x0094
3187 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2                                                        0x0096
3188 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST                                                        0x00a0
3189 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL                                                        0x00a2
3190 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO                                                     0x00a4
3191 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI                                                     0x00a8
3192 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA                                                        0x00a8
3193 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK                                                            0x00ac
3194 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64                                                     0x00ac
3195 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64                                                         0x00b0
3196 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING                                                         0x00b0
3197 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64                                                      0x00b4
3198 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST                                                       0x00c0
3199 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL                                                       0x00c2
3200 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE                                                          0x00c4
3201 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA                                                            0x00c8
3202 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0x0100
3203 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR                                            0x0104
3204 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1                                               0x0108
3205 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2                                               0x010c
3206 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0x0150
3207 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS                                              0x0154
3208 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK                                                0x0158
3209 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY                                            0x015c
3210 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS                                                0x0160
3211 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK                                                  0x0164
3212 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL                                               0x0168
3213 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0                                                       0x016c
3214 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1                                                       0x0170
3215 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2                                                       0x0174
3216 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3                                                       0x0178
3217 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0                                                0x0188
3218 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1                                                0x018c
3219 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2                                                0x0190
3220 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3                                                0x0194
3221 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST                                               0x02b0
3222 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP                                                        0x02b4
3223 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL                                                       0x02b6
3224 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST                                               0x0328
3225 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP                                                        0x032c
3226 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL                                                       0x032e
3227 
3228 
3229 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf12_bifcfgdecp
3230 // base address: 0x0
3231 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID                                                           0x0000
3232 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID                                                           0x0002
3233 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_COMMAND                                                             0x0004
3234 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_STATUS                                                              0x0006
3235 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID                                                         0x0008
3236 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE                                                      0x0009
3237 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS                                                           0x000a
3238 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS                                                          0x000b
3239 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE                                                          0x000c
3240 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LATENCY                                                             0x000d
3241 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_HEADER                                                              0x000e
3242 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BIST                                                                0x000f
3243 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1                                                         0x0010
3244 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2                                                         0x0014
3245 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3                                                         0x0018
3246 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4                                                         0x001c
3247 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5                                                         0x0020
3248 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6                                                         0x0024
3249 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_CARDBUS_CIS_PTR                                                     0x0028
3250 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID                                                          0x002c
3251 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR                                                       0x0030
3252 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR                                                             0x0034
3253 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE                                                      0x003c
3254 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN                                                       0x003d
3255 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MIN_GRANT                                                           0x003e
3256 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MAX_LATENCY                                                         0x003f
3257 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST                                                       0x0064
3258 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP                                                            0x0066
3259 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP                                                          0x0068
3260 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL                                                         0x006c
3261 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS                                                       0x006e
3262 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP                                                            0x0070
3263 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL                                                           0x0074
3264 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS                                                         0x0076
3265 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2                                                         0x0088
3266 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2                                                        0x008c
3267 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2                                                      0x008e
3268 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2                                                           0x0090
3269 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2                                                          0x0094
3270 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2                                                        0x0096
3271 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST                                                        0x00a0
3272 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL                                                        0x00a2
3273 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO                                                     0x00a4
3274 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI                                                     0x00a8
3275 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA                                                        0x00a8
3276 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK                                                            0x00ac
3277 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64                                                     0x00ac
3278 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64                                                         0x00b0
3279 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING                                                         0x00b0
3280 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64                                                      0x00b4
3281 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST                                                       0x00c0
3282 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL                                                       0x00c2
3283 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE                                                          0x00c4
3284 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA                                                            0x00c8
3285 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0x0100
3286 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR                                            0x0104
3287 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1                                               0x0108
3288 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2                                               0x010c
3289 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0x0150
3290 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS                                              0x0154
3291 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK                                                0x0158
3292 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY                                            0x015c
3293 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS                                                0x0160
3294 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK                                                  0x0164
3295 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL                                               0x0168
3296 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0                                                       0x016c
3297 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1                                                       0x0170
3298 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2                                                       0x0174
3299 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3                                                       0x0178
3300 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0                                                0x0188
3301 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1                                                0x018c
3302 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2                                                0x0190
3303 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3                                                0x0194
3304 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST                                               0x02b0
3305 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP                                                        0x02b4
3306 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL                                                       0x02b6
3307 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST                                               0x0328
3308 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP                                                        0x032c
3309 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL                                                       0x032e
3310 
3311 
3312 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf13_bifcfgdecp
3313 // base address: 0x0
3314 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID                                                           0x0000
3315 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID                                                           0x0002
3316 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_COMMAND                                                             0x0004
3317 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_STATUS                                                              0x0006
3318 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID                                                         0x0008
3319 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE                                                      0x0009
3320 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS                                                           0x000a
3321 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS                                                          0x000b
3322 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE                                                          0x000c
3323 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LATENCY                                                             0x000d
3324 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_HEADER                                                              0x000e
3325 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BIST                                                                0x000f
3326 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1                                                         0x0010
3327 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2                                                         0x0014
3328 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3                                                         0x0018
3329 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4                                                         0x001c
3330 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5                                                         0x0020
3331 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6                                                         0x0024
3332 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_CARDBUS_CIS_PTR                                                     0x0028
3333 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID                                                          0x002c
3334 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR                                                       0x0030
3335 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR                                                             0x0034
3336 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE                                                      0x003c
3337 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN                                                       0x003d
3338 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MIN_GRANT                                                           0x003e
3339 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MAX_LATENCY                                                         0x003f
3340 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST                                                       0x0064
3341 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP                                                            0x0066
3342 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP                                                          0x0068
3343 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL                                                         0x006c
3344 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS                                                       0x006e
3345 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP                                                            0x0070
3346 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL                                                           0x0074
3347 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS                                                         0x0076
3348 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2                                                         0x0088
3349 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2                                                        0x008c
3350 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2                                                      0x008e
3351 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2                                                           0x0090
3352 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2                                                          0x0094
3353 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2                                                        0x0096
3354 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST                                                        0x00a0
3355 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL                                                        0x00a2
3356 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO                                                     0x00a4
3357 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI                                                     0x00a8
3358 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA                                                        0x00a8
3359 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK                                                            0x00ac
3360 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64                                                     0x00ac
3361 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64                                                         0x00b0
3362 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING                                                         0x00b0
3363 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64                                                      0x00b4
3364 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST                                                       0x00c0
3365 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL                                                       0x00c2
3366 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE                                                          0x00c4
3367 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA                                                            0x00c8
3368 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0x0100
3369 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR                                            0x0104
3370 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1                                               0x0108
3371 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2                                               0x010c
3372 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0x0150
3373 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS                                              0x0154
3374 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK                                                0x0158
3375 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY                                            0x015c
3376 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS                                                0x0160
3377 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK                                                  0x0164
3378 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL                                               0x0168
3379 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0                                                       0x016c
3380 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1                                                       0x0170
3381 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2                                                       0x0174
3382 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3                                                       0x0178
3383 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0                                                0x0188
3384 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1                                                0x018c
3385 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2                                                0x0190
3386 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3                                                0x0194
3387 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST                                               0x02b0
3388 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP                                                        0x02b4
3389 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL                                                       0x02b6
3390 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST                                               0x0328
3391 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP                                                        0x032c
3392 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL                                                       0x032e
3393 
3394 
3395 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf14_bifcfgdecp
3396 // base address: 0x0
3397 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID                                                           0x0000
3398 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID                                                           0x0002
3399 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_COMMAND                                                             0x0004
3400 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_STATUS                                                              0x0006
3401 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID                                                         0x0008
3402 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE                                                      0x0009
3403 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS                                                           0x000a
3404 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS                                                          0x000b
3405 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE                                                          0x000c
3406 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LATENCY                                                             0x000d
3407 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_HEADER                                                              0x000e
3408 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BIST                                                                0x000f
3409 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1                                                         0x0010
3410 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2                                                         0x0014
3411 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3                                                         0x0018
3412 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4                                                         0x001c
3413 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5                                                         0x0020
3414 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6                                                         0x0024
3415 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_CARDBUS_CIS_PTR                                                     0x0028
3416 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID                                                          0x002c
3417 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR                                                       0x0030
3418 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR                                                             0x0034
3419 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE                                                      0x003c
3420 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN                                                       0x003d
3421 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MIN_GRANT                                                           0x003e
3422 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MAX_LATENCY                                                         0x003f
3423 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST                                                       0x0064
3424 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP                                                            0x0066
3425 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP                                                          0x0068
3426 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL                                                         0x006c
3427 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS                                                       0x006e
3428 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP                                                            0x0070
3429 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL                                                           0x0074
3430 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS                                                         0x0076
3431 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2                                                         0x0088
3432 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2                                                        0x008c
3433 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2                                                      0x008e
3434 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2                                                           0x0090
3435 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2                                                          0x0094
3436 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2                                                        0x0096
3437 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST                                                        0x00a0
3438 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL                                                        0x00a2
3439 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO                                                     0x00a4
3440 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI                                                     0x00a8
3441 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA                                                        0x00a8
3442 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK                                                            0x00ac
3443 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64                                                     0x00ac
3444 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64                                                         0x00b0
3445 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING                                                         0x00b0
3446 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64                                                      0x00b4
3447 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST                                                       0x00c0
3448 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL                                                       0x00c2
3449 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE                                                          0x00c4
3450 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA                                                            0x00c8
3451 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0x0100
3452 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR                                            0x0104
3453 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1                                               0x0108
3454 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2                                               0x010c
3455 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0x0150
3456 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS                                              0x0154
3457 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK                                                0x0158
3458 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY                                            0x015c
3459 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS                                                0x0160
3460 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK                                                  0x0164
3461 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL                                               0x0168
3462 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0                                                       0x016c
3463 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1                                                       0x0170
3464 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2                                                       0x0174
3465 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3                                                       0x0178
3466 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0                                                0x0188
3467 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1                                                0x018c
3468 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2                                                0x0190
3469 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3                                                0x0194
3470 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST                                               0x02b0
3471 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP                                                        0x02b4
3472 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL                                                       0x02b6
3473 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST                                               0x0328
3474 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP                                                        0x032c
3475 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL                                                       0x032e
3476 
3477 
3478 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf15_bifcfgdecp
3479 // base address: 0x0
3480 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID                                                           0x0000
3481 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID                                                           0x0002
3482 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_COMMAND                                                             0x0004
3483 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_STATUS                                                              0x0006
3484 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID                                                         0x0008
3485 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE                                                      0x0009
3486 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS                                                           0x000a
3487 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS                                                          0x000b
3488 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE                                                          0x000c
3489 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LATENCY                                                             0x000d
3490 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_HEADER                                                              0x000e
3491 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BIST                                                                0x000f
3492 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1                                                         0x0010
3493 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2                                                         0x0014
3494 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3                                                         0x0018
3495 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4                                                         0x001c
3496 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5                                                         0x0020
3497 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6                                                         0x0024
3498 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_CARDBUS_CIS_PTR                                                     0x0028
3499 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID                                                          0x002c
3500 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR                                                       0x0030
3501 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR                                                             0x0034
3502 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE                                                      0x003c
3503 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN                                                       0x003d
3504 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MIN_GRANT                                                           0x003e
3505 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MAX_LATENCY                                                         0x003f
3506 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST                                                       0x0064
3507 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP                                                            0x0066
3508 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP                                                          0x0068
3509 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL                                                         0x006c
3510 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS                                                       0x006e
3511 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP                                                            0x0070
3512 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL                                                           0x0074
3513 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS                                                         0x0076
3514 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2                                                         0x0088
3515 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2                                                        0x008c
3516 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2                                                      0x008e
3517 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2                                                           0x0090
3518 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2                                                          0x0094
3519 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2                                                        0x0096
3520 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST                                                        0x00a0
3521 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL                                                        0x00a2
3522 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO                                                     0x00a4
3523 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI                                                     0x00a8
3524 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA                                                        0x00a8
3525 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK                                                            0x00ac
3526 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64                                                     0x00ac
3527 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64                                                         0x00b0
3528 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING                                                         0x00b0
3529 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64                                                      0x00b4
3530 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST                                                       0x00c0
3531 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL                                                       0x00c2
3532 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE                                                          0x00c4
3533 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA                                                            0x00c8
3534 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0x0100
3535 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR                                            0x0104
3536 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1                                               0x0108
3537 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2                                               0x010c
3538 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0x0150
3539 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS                                              0x0154
3540 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK                                                0x0158
3541 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY                                            0x015c
3542 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS                                                0x0160
3543 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK                                                  0x0164
3544 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL                                               0x0168
3545 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0                                                       0x016c
3546 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1                                                       0x0170
3547 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2                                                       0x0174
3548 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3                                                       0x0178
3549 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0                                                0x0188
3550 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1                                                0x018c
3551 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2                                                0x0190
3552 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3                                                0x0194
3553 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST                                               0x02b0
3554 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP                                                        0x02b4
3555 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL                                                       0x02b6
3556 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST                                               0x0328
3557 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP                                                        0x032c
3558 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL                                                       0x032e
3559 
3560 
3561 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf16_bifcfgdecp
3562 // base address: 0x0
3563 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_VENDOR_ID                                                           0x0000
3564 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_ID                                                           0x0002
3565 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_COMMAND                                                             0x0004
3566 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_STATUS                                                              0x0006
3567 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_REVISION_ID                                                         0x0008
3568 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PROG_INTERFACE                                                      0x0009
3569 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_SUB_CLASS                                                           0x000a
3570 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_CLASS                                                          0x000b
3571 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_CACHE_LINE                                                          0x000c
3572 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_LATENCY                                                             0x000d
3573 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_HEADER                                                              0x000e
3574 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_BIST                                                                0x000f
3575 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_1                                                         0x0010
3576 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_2                                                         0x0014
3577 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_3                                                         0x0018
3578 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_4                                                         0x001c
3579 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_5                                                         0x0020
3580 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_6                                                         0x0024
3581 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_CARDBUS_CIS_PTR                                                     0x0028
3582 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_ADAPTER_ID                                                          0x002c
3583 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_ROM_BASE_ADDR                                                       0x0030
3584 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_CAP_PTR                                                             0x0034
3585 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_INTERRUPT_LINE                                                      0x003c
3586 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_INTERRUPT_PIN                                                       0x003d
3587 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MIN_GRANT                                                           0x003e
3588 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MAX_LATENCY                                                         0x003f
3589 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP_LIST                                                       0x0064
3590 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP                                                            0x0066
3591 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP                                                          0x0068
3592 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL                                                         0x006c
3593 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS                                                       0x006e
3594 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP                                                            0x0070
3595 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL                                                           0x0074
3596 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS                                                         0x0076
3597 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2                                                         0x0088
3598 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2                                                        0x008c
3599 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS2                                                      0x008e
3600 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2                                                           0x0090
3601 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2                                                          0x0094
3602 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2                                                        0x0096
3603 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_CAP_LIST                                                        0x00a0
3604 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL                                                        0x00a2
3605 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_ADDR_LO                                                     0x00a4
3606 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_ADDR_HI                                                     0x00a8
3607 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_DATA                                                        0x00a8
3608 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MASK                                                            0x00ac
3609 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_DATA_64                                                     0x00ac
3610 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MASK_64                                                         0x00b0
3611 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_PENDING                                                         0x00b0
3612 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_PENDING_64                                                      0x00b4
3613 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSIX_CAP_LIST                                                       0x00c0
3614 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSIX_MSG_CNTL                                                       0x00c2
3615 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSIX_TABLE                                                          0x00c4
3616 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSIX_PBA                                                            0x00c8
3617 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0x0100
3618 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_HDR                                            0x0104
3619 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC1                                               0x0108
3620 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC2                                               0x010c
3621 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0x0150
3622 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS                                              0x0154
3623 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK                                                0x0158
3624 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY                                            0x015c
3625 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS                                                0x0160
3626 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK                                                  0x0164
3627 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL                                               0x0168
3628 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG0                                                       0x016c
3629 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG1                                                       0x0170
3630 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG2                                                       0x0174
3631 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG3                                                       0x0178
3632 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG0                                                0x0188
3633 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG1                                                0x018c
3634 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG2                                                0x0190
3635 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG3                                                0x0194
3636 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_ENH_CAP_LIST                                               0x02b0
3637 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CAP                                                        0x02b4
3638 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CNTL                                                       0x02b6
3639 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_ENH_CAP_LIST                                               0x0328
3640 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CAP                                                        0x032c
3641 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CNTL                                                       0x032e
3642 
3643 
3644 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf17_bifcfgdecp
3645 // base address: 0x0
3646 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_VENDOR_ID                                                           0x0000
3647 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_ID                                                           0x0002
3648 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_COMMAND                                                             0x0004
3649 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_STATUS                                                              0x0006
3650 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_REVISION_ID                                                         0x0008
3651 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PROG_INTERFACE                                                      0x0009
3652 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_SUB_CLASS                                                           0x000a
3653 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_CLASS                                                          0x000b
3654 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_CACHE_LINE                                                          0x000c
3655 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_LATENCY                                                             0x000d
3656 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_HEADER                                                              0x000e
3657 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_BIST                                                                0x000f
3658 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_1                                                         0x0010
3659 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_2                                                         0x0014
3660 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_3                                                         0x0018
3661 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_4                                                         0x001c
3662 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_5                                                         0x0020
3663 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_6                                                         0x0024
3664 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_CARDBUS_CIS_PTR                                                     0x0028
3665 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_ADAPTER_ID                                                          0x002c
3666 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_ROM_BASE_ADDR                                                       0x0030
3667 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_CAP_PTR                                                             0x0034
3668 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_INTERRUPT_LINE                                                      0x003c
3669 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_INTERRUPT_PIN                                                       0x003d
3670 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MIN_GRANT                                                           0x003e
3671 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MAX_LATENCY                                                         0x003f
3672 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP_LIST                                                       0x0064
3673 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP                                                            0x0066
3674 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP                                                          0x0068
3675 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL                                                         0x006c
3676 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS                                                       0x006e
3677 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP                                                            0x0070
3678 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL                                                           0x0074
3679 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS                                                         0x0076
3680 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2                                                         0x0088
3681 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2                                                        0x008c
3682 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS2                                                      0x008e
3683 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2                                                           0x0090
3684 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2                                                          0x0094
3685 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2                                                        0x0096
3686 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_CAP_LIST                                                        0x00a0
3687 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL                                                        0x00a2
3688 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_ADDR_LO                                                     0x00a4
3689 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_ADDR_HI                                                     0x00a8
3690 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_DATA                                                        0x00a8
3691 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MASK                                                            0x00ac
3692 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_DATA_64                                                     0x00ac
3693 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MASK_64                                                         0x00b0
3694 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_PENDING                                                         0x00b0
3695 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_PENDING_64                                                      0x00b4
3696 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSIX_CAP_LIST                                                       0x00c0
3697 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSIX_MSG_CNTL                                                       0x00c2
3698 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSIX_TABLE                                                          0x00c4
3699 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSIX_PBA                                                            0x00c8
3700 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0x0100
3701 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_HDR                                            0x0104
3702 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC1                                               0x0108
3703 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC2                                               0x010c
3704 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0x0150
3705 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS                                              0x0154
3706 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK                                                0x0158
3707 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY                                            0x015c
3708 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS                                                0x0160
3709 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK                                                  0x0164
3710 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL                                               0x0168
3711 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG0                                                       0x016c
3712 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG1                                                       0x0170
3713 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG2                                                       0x0174
3714 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG3                                                       0x0178
3715 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG0                                                0x0188
3716 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG1                                                0x018c
3717 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG2                                                0x0190
3718 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG3                                                0x0194
3719 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_ENH_CAP_LIST                                               0x02b0
3720 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CAP                                                        0x02b4
3721 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CNTL                                                       0x02b6
3722 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_ENH_CAP_LIST                                               0x0328
3723 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CAP                                                        0x032c
3724 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CNTL                                                       0x032e
3725 
3726 
3727 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf18_bifcfgdecp
3728 // base address: 0x0
3729 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_VENDOR_ID                                                           0x0000
3730 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_ID                                                           0x0002
3731 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_COMMAND                                                             0x0004
3732 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_STATUS                                                              0x0006
3733 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_REVISION_ID                                                         0x0008
3734 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PROG_INTERFACE                                                      0x0009
3735 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_SUB_CLASS                                                           0x000a
3736 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_CLASS                                                          0x000b
3737 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_CACHE_LINE                                                          0x000c
3738 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_LATENCY                                                             0x000d
3739 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_HEADER                                                              0x000e
3740 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_BIST                                                                0x000f
3741 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_1                                                         0x0010
3742 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_2                                                         0x0014
3743 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_3                                                         0x0018
3744 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_4                                                         0x001c
3745 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_5                                                         0x0020
3746 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_6                                                         0x0024
3747 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_CARDBUS_CIS_PTR                                                     0x0028
3748 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_ADAPTER_ID                                                          0x002c
3749 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_ROM_BASE_ADDR                                                       0x0030
3750 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_CAP_PTR                                                             0x0034
3751 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_INTERRUPT_LINE                                                      0x003c
3752 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_INTERRUPT_PIN                                                       0x003d
3753 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MIN_GRANT                                                           0x003e
3754 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MAX_LATENCY                                                         0x003f
3755 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP_LIST                                                       0x0064
3756 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP                                                            0x0066
3757 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP                                                          0x0068
3758 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL                                                         0x006c
3759 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS                                                       0x006e
3760 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP                                                            0x0070
3761 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL                                                           0x0074
3762 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS                                                         0x0076
3763 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2                                                         0x0088
3764 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2                                                        0x008c
3765 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS2                                                      0x008e
3766 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2                                                           0x0090
3767 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2                                                          0x0094
3768 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2                                                        0x0096
3769 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_CAP_LIST                                                        0x00a0
3770 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL                                                        0x00a2
3771 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_ADDR_LO                                                     0x00a4
3772 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_ADDR_HI                                                     0x00a8
3773 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_DATA                                                        0x00a8
3774 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MASK                                                            0x00ac
3775 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_DATA_64                                                     0x00ac
3776 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MASK_64                                                         0x00b0
3777 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_PENDING                                                         0x00b0
3778 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_PENDING_64                                                      0x00b4
3779 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSIX_CAP_LIST                                                       0x00c0
3780 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSIX_MSG_CNTL                                                       0x00c2
3781 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSIX_TABLE                                                          0x00c4
3782 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSIX_PBA                                                            0x00c8
3783 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0x0100
3784 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_HDR                                            0x0104
3785 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC1                                               0x0108
3786 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC2                                               0x010c
3787 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0x0150
3788 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS                                              0x0154
3789 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK                                                0x0158
3790 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY                                            0x015c
3791 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS                                                0x0160
3792 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK                                                  0x0164
3793 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL                                               0x0168
3794 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG0                                                       0x016c
3795 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG1                                                       0x0170
3796 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG2                                                       0x0174
3797 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG3                                                       0x0178
3798 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG0                                                0x0188
3799 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG1                                                0x018c
3800 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG2                                                0x0190
3801 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG3                                                0x0194
3802 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_ENH_CAP_LIST                                               0x02b0
3803 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CAP                                                        0x02b4
3804 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CNTL                                                       0x02b6
3805 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_ENH_CAP_LIST                                               0x0328
3806 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CAP                                                        0x032c
3807 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CNTL                                                       0x032e
3808 
3809 
3810 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf19_bifcfgdecp
3811 // base address: 0x0
3812 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_VENDOR_ID                                                           0x0000
3813 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_ID                                                           0x0002
3814 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_COMMAND                                                             0x0004
3815 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_STATUS                                                              0x0006
3816 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_REVISION_ID                                                         0x0008
3817 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PROG_INTERFACE                                                      0x0009
3818 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_SUB_CLASS                                                           0x000a
3819 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_CLASS                                                          0x000b
3820 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_CACHE_LINE                                                          0x000c
3821 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_LATENCY                                                             0x000d
3822 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_HEADER                                                              0x000e
3823 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_BIST                                                                0x000f
3824 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_1                                                         0x0010
3825 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_2                                                         0x0014
3826 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_3                                                         0x0018
3827 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_4                                                         0x001c
3828 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_5                                                         0x0020
3829 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_6                                                         0x0024
3830 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_CARDBUS_CIS_PTR                                                     0x0028
3831 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_ADAPTER_ID                                                          0x002c
3832 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_ROM_BASE_ADDR                                                       0x0030
3833 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_CAP_PTR                                                             0x0034
3834 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_INTERRUPT_LINE                                                      0x003c
3835 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_INTERRUPT_PIN                                                       0x003d
3836 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MIN_GRANT                                                           0x003e
3837 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MAX_LATENCY                                                         0x003f
3838 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP_LIST                                                       0x0064
3839 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP                                                            0x0066
3840 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP                                                          0x0068
3841 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL                                                         0x006c
3842 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS                                                       0x006e
3843 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP                                                            0x0070
3844 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL                                                           0x0074
3845 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS                                                         0x0076
3846 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2                                                         0x0088
3847 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2                                                        0x008c
3848 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS2                                                      0x008e
3849 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2                                                           0x0090
3850 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2                                                          0x0094
3851 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2                                                        0x0096
3852 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_CAP_LIST                                                        0x00a0
3853 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL                                                        0x00a2
3854 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_ADDR_LO                                                     0x00a4
3855 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_ADDR_HI                                                     0x00a8
3856 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_DATA                                                        0x00a8
3857 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MASK                                                            0x00ac
3858 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_DATA_64                                                     0x00ac
3859 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MASK_64                                                         0x00b0
3860 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_PENDING                                                         0x00b0
3861 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_PENDING_64                                                      0x00b4
3862 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSIX_CAP_LIST                                                       0x00c0
3863 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSIX_MSG_CNTL                                                       0x00c2
3864 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSIX_TABLE                                                          0x00c4
3865 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSIX_PBA                                                            0x00c8
3866 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0x0100
3867 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_HDR                                            0x0104
3868 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC1                                               0x0108
3869 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC2                                               0x010c
3870 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0x0150
3871 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS                                              0x0154
3872 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK                                                0x0158
3873 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY                                            0x015c
3874 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS                                                0x0160
3875 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK                                                  0x0164
3876 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL                                               0x0168
3877 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG0                                                       0x016c
3878 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG1                                                       0x0170
3879 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG2                                                       0x0174
3880 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG3                                                       0x0178
3881 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG0                                                0x0188
3882 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG1                                                0x018c
3883 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG2                                                0x0190
3884 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG3                                                0x0194
3885 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_ENH_CAP_LIST                                               0x02b0
3886 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CAP                                                        0x02b4
3887 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CNTL                                                       0x02b6
3888 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_ENH_CAP_LIST                                               0x0328
3889 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CAP                                                        0x032c
3890 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CNTL                                                       0x032e
3891 
3892 
3893 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf20_bifcfgdecp
3894 // base address: 0x0
3895 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_VENDOR_ID                                                           0x0000
3896 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_ID                                                           0x0002
3897 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_COMMAND                                                             0x0004
3898 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_STATUS                                                              0x0006
3899 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_REVISION_ID                                                         0x0008
3900 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PROG_INTERFACE                                                      0x0009
3901 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_SUB_CLASS                                                           0x000a
3902 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_CLASS                                                          0x000b
3903 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_CACHE_LINE                                                          0x000c
3904 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_LATENCY                                                             0x000d
3905 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_HEADER                                                              0x000e
3906 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_BIST                                                                0x000f
3907 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_1                                                         0x0010
3908 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_2                                                         0x0014
3909 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_3                                                         0x0018
3910 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_4                                                         0x001c
3911 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_5                                                         0x0020
3912 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_6                                                         0x0024
3913 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_CARDBUS_CIS_PTR                                                     0x0028
3914 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_ADAPTER_ID                                                          0x002c
3915 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_ROM_BASE_ADDR                                                       0x0030
3916 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_CAP_PTR                                                             0x0034
3917 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_INTERRUPT_LINE                                                      0x003c
3918 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_INTERRUPT_PIN                                                       0x003d
3919 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MIN_GRANT                                                           0x003e
3920 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MAX_LATENCY                                                         0x003f
3921 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP_LIST                                                       0x0064
3922 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP                                                            0x0066
3923 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP                                                          0x0068
3924 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL                                                         0x006c
3925 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS                                                       0x006e
3926 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP                                                            0x0070
3927 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL                                                           0x0074
3928 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS                                                         0x0076
3929 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2                                                         0x0088
3930 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2                                                        0x008c
3931 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS2                                                      0x008e
3932 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2                                                           0x0090
3933 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2                                                          0x0094
3934 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2                                                        0x0096
3935 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_CAP_LIST                                                        0x00a0
3936 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL                                                        0x00a2
3937 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_ADDR_LO                                                     0x00a4
3938 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_ADDR_HI                                                     0x00a8
3939 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_DATA                                                        0x00a8
3940 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MASK                                                            0x00ac
3941 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_DATA_64                                                     0x00ac
3942 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MASK_64                                                         0x00b0
3943 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_PENDING                                                         0x00b0
3944 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_PENDING_64                                                      0x00b4
3945 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSIX_CAP_LIST                                                       0x00c0
3946 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSIX_MSG_CNTL                                                       0x00c2
3947 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSIX_TABLE                                                          0x00c4
3948 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSIX_PBA                                                            0x00c8
3949 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0x0100
3950 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_HDR                                            0x0104
3951 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC1                                               0x0108
3952 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC2                                               0x010c
3953 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0x0150
3954 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS                                              0x0154
3955 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK                                                0x0158
3956 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY                                            0x015c
3957 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS                                                0x0160
3958 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK                                                  0x0164
3959 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL                                               0x0168
3960 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG0                                                       0x016c
3961 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG1                                                       0x0170
3962 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG2                                                       0x0174
3963 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG3                                                       0x0178
3964 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG0                                                0x0188
3965 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG1                                                0x018c
3966 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG2                                                0x0190
3967 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG3                                                0x0194
3968 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_ENH_CAP_LIST                                               0x02b0
3969 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CAP                                                        0x02b4
3970 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CNTL                                                       0x02b6
3971 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_ENH_CAP_LIST                                               0x0328
3972 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CAP                                                        0x032c
3973 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CNTL                                                       0x032e
3974 
3975 
3976 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf21_bifcfgdecp
3977 // base address: 0x0
3978 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_VENDOR_ID                                                           0x0000
3979 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_ID                                                           0x0002
3980 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_COMMAND                                                             0x0004
3981 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_STATUS                                                              0x0006
3982 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_REVISION_ID                                                         0x0008
3983 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PROG_INTERFACE                                                      0x0009
3984 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_SUB_CLASS                                                           0x000a
3985 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_CLASS                                                          0x000b
3986 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_CACHE_LINE                                                          0x000c
3987 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_LATENCY                                                             0x000d
3988 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_HEADER                                                              0x000e
3989 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_BIST                                                                0x000f
3990 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_1                                                         0x0010
3991 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_2                                                         0x0014
3992 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_3                                                         0x0018
3993 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_4                                                         0x001c
3994 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_5                                                         0x0020
3995 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_6                                                         0x0024
3996 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_CARDBUS_CIS_PTR                                                     0x0028
3997 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_ADAPTER_ID                                                          0x002c
3998 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_ROM_BASE_ADDR                                                       0x0030
3999 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_CAP_PTR                                                             0x0034
4000 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_INTERRUPT_LINE                                                      0x003c
4001 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_INTERRUPT_PIN                                                       0x003d
4002 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MIN_GRANT                                                           0x003e
4003 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MAX_LATENCY                                                         0x003f
4004 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP_LIST                                                       0x0064
4005 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP                                                            0x0066
4006 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP                                                          0x0068
4007 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL                                                         0x006c
4008 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS                                                       0x006e
4009 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP                                                            0x0070
4010 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL                                                           0x0074
4011 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS                                                         0x0076
4012 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2                                                         0x0088
4013 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2                                                        0x008c
4014 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS2                                                      0x008e
4015 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2                                                           0x0090
4016 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2                                                          0x0094
4017 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2                                                        0x0096
4018 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_CAP_LIST                                                        0x00a0
4019 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL                                                        0x00a2
4020 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_ADDR_LO                                                     0x00a4
4021 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_ADDR_HI                                                     0x00a8
4022 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_DATA                                                        0x00a8
4023 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MASK                                                            0x00ac
4024 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_DATA_64                                                     0x00ac
4025 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MASK_64                                                         0x00b0
4026 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_PENDING                                                         0x00b0
4027 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_PENDING_64                                                      0x00b4
4028 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSIX_CAP_LIST                                                       0x00c0
4029 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSIX_MSG_CNTL                                                       0x00c2
4030 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSIX_TABLE                                                          0x00c4
4031 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSIX_PBA                                                            0x00c8
4032 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0x0100
4033 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_HDR                                            0x0104
4034 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC1                                               0x0108
4035 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC2                                               0x010c
4036 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0x0150
4037 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS                                              0x0154
4038 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK                                                0x0158
4039 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY                                            0x015c
4040 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS                                                0x0160
4041 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK                                                  0x0164
4042 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL                                               0x0168
4043 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG0                                                       0x016c
4044 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG1                                                       0x0170
4045 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG2                                                       0x0174
4046 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG3                                                       0x0178
4047 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG0                                                0x0188
4048 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG1                                                0x018c
4049 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG2                                                0x0190
4050 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG3                                                0x0194
4051 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_ENH_CAP_LIST                                               0x02b0
4052 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CAP                                                        0x02b4
4053 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CNTL                                                       0x02b6
4054 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_ENH_CAP_LIST                                               0x0328
4055 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CAP                                                        0x032c
4056 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CNTL                                                       0x032e
4057 
4058 
4059 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf22_bifcfgdecp
4060 // base address: 0x0
4061 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_VENDOR_ID                                                           0x0000
4062 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_ID                                                           0x0002
4063 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_COMMAND                                                             0x0004
4064 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_STATUS                                                              0x0006
4065 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_REVISION_ID                                                         0x0008
4066 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PROG_INTERFACE                                                      0x0009
4067 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_SUB_CLASS                                                           0x000a
4068 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_CLASS                                                          0x000b
4069 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_CACHE_LINE                                                          0x000c
4070 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_LATENCY                                                             0x000d
4071 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_HEADER                                                              0x000e
4072 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_BIST                                                                0x000f
4073 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_1                                                         0x0010
4074 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_2                                                         0x0014
4075 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_3                                                         0x0018
4076 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_4                                                         0x001c
4077 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_5                                                         0x0020
4078 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_6                                                         0x0024
4079 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_CARDBUS_CIS_PTR                                                     0x0028
4080 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_ADAPTER_ID                                                          0x002c
4081 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_ROM_BASE_ADDR                                                       0x0030
4082 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_CAP_PTR                                                             0x0034
4083 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_INTERRUPT_LINE                                                      0x003c
4084 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_INTERRUPT_PIN                                                       0x003d
4085 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MIN_GRANT                                                           0x003e
4086 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MAX_LATENCY                                                         0x003f
4087 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP_LIST                                                       0x0064
4088 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP                                                            0x0066
4089 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP                                                          0x0068
4090 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL                                                         0x006c
4091 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS                                                       0x006e
4092 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP                                                            0x0070
4093 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL                                                           0x0074
4094 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS                                                         0x0076
4095 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2                                                         0x0088
4096 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2                                                        0x008c
4097 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS2                                                      0x008e
4098 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2                                                           0x0090
4099 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2                                                          0x0094
4100 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2                                                        0x0096
4101 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_CAP_LIST                                                        0x00a0
4102 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL                                                        0x00a2
4103 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_ADDR_LO                                                     0x00a4
4104 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_ADDR_HI                                                     0x00a8
4105 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_DATA                                                        0x00a8
4106 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MASK                                                            0x00ac
4107 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_DATA_64                                                     0x00ac
4108 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MASK_64                                                         0x00b0
4109 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_PENDING                                                         0x00b0
4110 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_PENDING_64                                                      0x00b4
4111 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSIX_CAP_LIST                                                       0x00c0
4112 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSIX_MSG_CNTL                                                       0x00c2
4113 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSIX_TABLE                                                          0x00c4
4114 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSIX_PBA                                                            0x00c8
4115 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0x0100
4116 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_HDR                                            0x0104
4117 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC1                                               0x0108
4118 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC2                                               0x010c
4119 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0x0150
4120 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS                                              0x0154
4121 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK                                                0x0158
4122 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY                                            0x015c
4123 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS                                                0x0160
4124 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK                                                  0x0164
4125 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL                                               0x0168
4126 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG0                                                       0x016c
4127 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG1                                                       0x0170
4128 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG2                                                       0x0174
4129 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG3                                                       0x0178
4130 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG0                                                0x0188
4131 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG1                                                0x018c
4132 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG2                                                0x0190
4133 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG3                                                0x0194
4134 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_ENH_CAP_LIST                                               0x02b0
4135 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CAP                                                        0x02b4
4136 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CNTL                                                       0x02b6
4137 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_ENH_CAP_LIST                                               0x0328
4138 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CAP                                                        0x032c
4139 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CNTL                                                       0x032e
4140 
4141 
4142 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf23_bifcfgdecp
4143 // base address: 0x0
4144 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_VENDOR_ID                                                           0x0000
4145 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_ID                                                           0x0002
4146 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_COMMAND                                                             0x0004
4147 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_STATUS                                                              0x0006
4148 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_REVISION_ID                                                         0x0008
4149 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PROG_INTERFACE                                                      0x0009
4150 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_SUB_CLASS                                                           0x000a
4151 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_CLASS                                                          0x000b
4152 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_CACHE_LINE                                                          0x000c
4153 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_LATENCY                                                             0x000d
4154 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_HEADER                                                              0x000e
4155 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_BIST                                                                0x000f
4156 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_1                                                         0x0010
4157 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_2                                                         0x0014
4158 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_3                                                         0x0018
4159 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_4                                                         0x001c
4160 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_5                                                         0x0020
4161 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_6                                                         0x0024
4162 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_CARDBUS_CIS_PTR                                                     0x0028
4163 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_ADAPTER_ID                                                          0x002c
4164 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_ROM_BASE_ADDR                                                       0x0030
4165 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_CAP_PTR                                                             0x0034
4166 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_INTERRUPT_LINE                                                      0x003c
4167 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_INTERRUPT_PIN                                                       0x003d
4168 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MIN_GRANT                                                           0x003e
4169 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MAX_LATENCY                                                         0x003f
4170 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP_LIST                                                       0x0064
4171 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP                                                            0x0066
4172 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP                                                          0x0068
4173 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL                                                         0x006c
4174 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS                                                       0x006e
4175 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP                                                            0x0070
4176 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL                                                           0x0074
4177 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS                                                         0x0076
4178 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2                                                         0x0088
4179 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2                                                        0x008c
4180 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS2                                                      0x008e
4181 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2                                                           0x0090
4182 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2                                                          0x0094
4183 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2                                                        0x0096
4184 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_CAP_LIST                                                        0x00a0
4185 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL                                                        0x00a2
4186 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_ADDR_LO                                                     0x00a4
4187 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_ADDR_HI                                                     0x00a8
4188 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_DATA                                                        0x00a8
4189 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MASK                                                            0x00ac
4190 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_DATA_64                                                     0x00ac
4191 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MASK_64                                                         0x00b0
4192 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_PENDING                                                         0x00b0
4193 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_PENDING_64                                                      0x00b4
4194 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSIX_CAP_LIST                                                       0x00c0
4195 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSIX_MSG_CNTL                                                       0x00c2
4196 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSIX_TABLE                                                          0x00c4
4197 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSIX_PBA                                                            0x00c8
4198 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0x0100
4199 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_HDR                                            0x0104
4200 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC1                                               0x0108
4201 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC2                                               0x010c
4202 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0x0150
4203 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS                                              0x0154
4204 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK                                                0x0158
4205 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY                                            0x015c
4206 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS                                                0x0160
4207 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK                                                  0x0164
4208 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL                                               0x0168
4209 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG0                                                       0x016c
4210 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG1                                                       0x0170
4211 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG2                                                       0x0174
4212 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG3                                                       0x0178
4213 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG0                                                0x0188
4214 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG1                                                0x018c
4215 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG2                                                0x0190
4216 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG3                                                0x0194
4217 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_ENH_CAP_LIST                                               0x02b0
4218 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CAP                                                        0x02b4
4219 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CNTL                                                       0x02b6
4220 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_ENH_CAP_LIST                                               0x0328
4221 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CAP                                                        0x032c
4222 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CNTL                                                       0x032e
4223 
4224 
4225 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf24_bifcfgdecp
4226 // base address: 0x0
4227 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_VENDOR_ID                                                           0x0000
4228 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_ID                                                           0x0002
4229 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_COMMAND                                                             0x0004
4230 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_STATUS                                                              0x0006
4231 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_REVISION_ID                                                         0x0008
4232 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PROG_INTERFACE                                                      0x0009
4233 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_SUB_CLASS                                                           0x000a
4234 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_CLASS                                                          0x000b
4235 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_CACHE_LINE                                                          0x000c
4236 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_LATENCY                                                             0x000d
4237 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_HEADER                                                              0x000e
4238 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_BIST                                                                0x000f
4239 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_1                                                         0x0010
4240 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_2                                                         0x0014
4241 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_3                                                         0x0018
4242 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_4                                                         0x001c
4243 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_5                                                         0x0020
4244 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_6                                                         0x0024
4245 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_CARDBUS_CIS_PTR                                                     0x0028
4246 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_ADAPTER_ID                                                          0x002c
4247 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_ROM_BASE_ADDR                                                       0x0030
4248 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_CAP_PTR                                                             0x0034
4249 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_INTERRUPT_LINE                                                      0x003c
4250 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_INTERRUPT_PIN                                                       0x003d
4251 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MIN_GRANT                                                           0x003e
4252 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MAX_LATENCY                                                         0x003f
4253 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP_LIST                                                       0x0064
4254 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP                                                            0x0066
4255 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP                                                          0x0068
4256 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL                                                         0x006c
4257 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS                                                       0x006e
4258 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP                                                            0x0070
4259 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL                                                           0x0074
4260 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS                                                         0x0076
4261 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2                                                         0x0088
4262 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2                                                        0x008c
4263 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS2                                                      0x008e
4264 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2                                                           0x0090
4265 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2                                                          0x0094
4266 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2                                                        0x0096
4267 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_CAP_LIST                                                        0x00a0
4268 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL                                                        0x00a2
4269 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_ADDR_LO                                                     0x00a4
4270 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_ADDR_HI                                                     0x00a8
4271 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_DATA                                                        0x00a8
4272 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MASK                                                            0x00ac
4273 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_DATA_64                                                     0x00ac
4274 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MASK_64                                                         0x00b0
4275 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_PENDING                                                         0x00b0
4276 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_PENDING_64                                                      0x00b4
4277 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSIX_CAP_LIST                                                       0x00c0
4278 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSIX_MSG_CNTL                                                       0x00c2
4279 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSIX_TABLE                                                          0x00c4
4280 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSIX_PBA                                                            0x00c8
4281 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0x0100
4282 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_HDR                                            0x0104
4283 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC1                                               0x0108
4284 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC2                                               0x010c
4285 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0x0150
4286 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS                                              0x0154
4287 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK                                                0x0158
4288 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY                                            0x015c
4289 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS                                                0x0160
4290 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK                                                  0x0164
4291 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL                                               0x0168
4292 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG0                                                       0x016c
4293 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG1                                                       0x0170
4294 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG2                                                       0x0174
4295 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG3                                                       0x0178
4296 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG0                                                0x0188
4297 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG1                                                0x018c
4298 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG2                                                0x0190
4299 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG3                                                0x0194
4300 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_ENH_CAP_LIST                                               0x02b0
4301 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CAP                                                        0x02b4
4302 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CNTL                                                       0x02b6
4303 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_ENH_CAP_LIST                                               0x0328
4304 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CAP                                                        0x032c
4305 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CNTL                                                       0x032e
4306 
4307 
4308 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf25_bifcfgdecp
4309 // base address: 0x0
4310 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_VENDOR_ID                                                           0x0000
4311 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_ID                                                           0x0002
4312 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_COMMAND                                                             0x0004
4313 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_STATUS                                                              0x0006
4314 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_REVISION_ID                                                         0x0008
4315 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PROG_INTERFACE                                                      0x0009
4316 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_SUB_CLASS                                                           0x000a
4317 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_CLASS                                                          0x000b
4318 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_CACHE_LINE                                                          0x000c
4319 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_LATENCY                                                             0x000d
4320 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_HEADER                                                              0x000e
4321 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_BIST                                                                0x000f
4322 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_1                                                         0x0010
4323 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_2                                                         0x0014
4324 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_3                                                         0x0018
4325 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_4                                                         0x001c
4326 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_5                                                         0x0020
4327 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_6                                                         0x0024
4328 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_CARDBUS_CIS_PTR                                                     0x0028
4329 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_ADAPTER_ID                                                          0x002c
4330 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_ROM_BASE_ADDR                                                       0x0030
4331 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_CAP_PTR                                                             0x0034
4332 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_INTERRUPT_LINE                                                      0x003c
4333 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_INTERRUPT_PIN                                                       0x003d
4334 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MIN_GRANT                                                           0x003e
4335 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MAX_LATENCY                                                         0x003f
4336 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP_LIST                                                       0x0064
4337 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP                                                            0x0066
4338 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP                                                          0x0068
4339 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL                                                         0x006c
4340 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS                                                       0x006e
4341 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP                                                            0x0070
4342 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL                                                           0x0074
4343 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS                                                         0x0076
4344 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2                                                         0x0088
4345 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2                                                        0x008c
4346 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS2                                                      0x008e
4347 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2                                                           0x0090
4348 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2                                                          0x0094
4349 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2                                                        0x0096
4350 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_CAP_LIST                                                        0x00a0
4351 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL                                                        0x00a2
4352 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_ADDR_LO                                                     0x00a4
4353 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_ADDR_HI                                                     0x00a8
4354 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_DATA                                                        0x00a8
4355 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MASK                                                            0x00ac
4356 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_DATA_64                                                     0x00ac
4357 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MASK_64                                                         0x00b0
4358 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_PENDING                                                         0x00b0
4359 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_PENDING_64                                                      0x00b4
4360 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSIX_CAP_LIST                                                       0x00c0
4361 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSIX_MSG_CNTL                                                       0x00c2
4362 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSIX_TABLE                                                          0x00c4
4363 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSIX_PBA                                                            0x00c8
4364 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0x0100
4365 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_HDR                                            0x0104
4366 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC1                                               0x0108
4367 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC2                                               0x010c
4368 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0x0150
4369 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS                                              0x0154
4370 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK                                                0x0158
4371 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY                                            0x015c
4372 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS                                                0x0160
4373 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK                                                  0x0164
4374 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL                                               0x0168
4375 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG0                                                       0x016c
4376 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG1                                                       0x0170
4377 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG2                                                       0x0174
4378 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG3                                                       0x0178
4379 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG0                                                0x0188
4380 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG1                                                0x018c
4381 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG2                                                0x0190
4382 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG3                                                0x0194
4383 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_ENH_CAP_LIST                                               0x02b0
4384 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CAP                                                        0x02b4
4385 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CNTL                                                       0x02b6
4386 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_ENH_CAP_LIST                                               0x0328
4387 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CAP                                                        0x032c
4388 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CNTL                                                       0x032e
4389 
4390 
4391 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf26_bifcfgdecp
4392 // base address: 0x0
4393 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_VENDOR_ID                                                           0x0000
4394 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_ID                                                           0x0002
4395 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_COMMAND                                                             0x0004
4396 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_STATUS                                                              0x0006
4397 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_REVISION_ID                                                         0x0008
4398 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PROG_INTERFACE                                                      0x0009
4399 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_SUB_CLASS                                                           0x000a
4400 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_CLASS                                                          0x000b
4401 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_CACHE_LINE                                                          0x000c
4402 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_LATENCY                                                             0x000d
4403 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_HEADER                                                              0x000e
4404 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_BIST                                                                0x000f
4405 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_1                                                         0x0010
4406 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_2                                                         0x0014
4407 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_3                                                         0x0018
4408 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_4                                                         0x001c
4409 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_5                                                         0x0020
4410 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_6                                                         0x0024
4411 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_CARDBUS_CIS_PTR                                                     0x0028
4412 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_ADAPTER_ID                                                          0x002c
4413 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_ROM_BASE_ADDR                                                       0x0030
4414 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_CAP_PTR                                                             0x0034
4415 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_INTERRUPT_LINE                                                      0x003c
4416 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_INTERRUPT_PIN                                                       0x003d
4417 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MIN_GRANT                                                           0x003e
4418 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MAX_LATENCY                                                         0x003f
4419 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP_LIST                                                       0x0064
4420 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP                                                            0x0066
4421 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP                                                          0x0068
4422 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL                                                         0x006c
4423 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS                                                       0x006e
4424 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP                                                            0x0070
4425 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL                                                           0x0074
4426 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS                                                         0x0076
4427 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2                                                         0x0088
4428 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2                                                        0x008c
4429 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS2                                                      0x008e
4430 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2                                                           0x0090
4431 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2                                                          0x0094
4432 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2                                                        0x0096
4433 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_CAP_LIST                                                        0x00a0
4434 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL                                                        0x00a2
4435 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_ADDR_LO                                                     0x00a4
4436 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_ADDR_HI                                                     0x00a8
4437 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_DATA                                                        0x00a8
4438 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MASK                                                            0x00ac
4439 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_DATA_64                                                     0x00ac
4440 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MASK_64                                                         0x00b0
4441 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_PENDING                                                         0x00b0
4442 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_PENDING_64                                                      0x00b4
4443 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSIX_CAP_LIST                                                       0x00c0
4444 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSIX_MSG_CNTL                                                       0x00c2
4445 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSIX_TABLE                                                          0x00c4
4446 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSIX_PBA                                                            0x00c8
4447 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0x0100
4448 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_HDR                                            0x0104
4449 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC1                                               0x0108
4450 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC2                                               0x010c
4451 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0x0150
4452 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS                                              0x0154
4453 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK                                                0x0158
4454 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY                                            0x015c
4455 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS                                                0x0160
4456 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK                                                  0x0164
4457 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL                                               0x0168
4458 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG0                                                       0x016c
4459 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG1                                                       0x0170
4460 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG2                                                       0x0174
4461 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG3                                                       0x0178
4462 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG0                                                0x0188
4463 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG1                                                0x018c
4464 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG2                                                0x0190
4465 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG3                                                0x0194
4466 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_ENH_CAP_LIST                                               0x02b0
4467 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CAP                                                        0x02b4
4468 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CNTL                                                       0x02b6
4469 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_ENH_CAP_LIST                                               0x0328
4470 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CAP                                                        0x032c
4471 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CNTL                                                       0x032e
4472 
4473 
4474 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf27_bifcfgdecp
4475 // base address: 0x0
4476 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_VENDOR_ID                                                           0x0000
4477 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_ID                                                           0x0002
4478 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_COMMAND                                                             0x0004
4479 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_STATUS                                                              0x0006
4480 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_REVISION_ID                                                         0x0008
4481 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PROG_INTERFACE                                                      0x0009
4482 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_SUB_CLASS                                                           0x000a
4483 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_CLASS                                                          0x000b
4484 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_CACHE_LINE                                                          0x000c
4485 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_LATENCY                                                             0x000d
4486 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_HEADER                                                              0x000e
4487 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_BIST                                                                0x000f
4488 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_1                                                         0x0010
4489 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_2                                                         0x0014
4490 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_3                                                         0x0018
4491 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_4                                                         0x001c
4492 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_5                                                         0x0020
4493 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_6                                                         0x0024
4494 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_CARDBUS_CIS_PTR                                                     0x0028
4495 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_ADAPTER_ID                                                          0x002c
4496 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_ROM_BASE_ADDR                                                       0x0030
4497 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_CAP_PTR                                                             0x0034
4498 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_INTERRUPT_LINE                                                      0x003c
4499 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_INTERRUPT_PIN                                                       0x003d
4500 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MIN_GRANT                                                           0x003e
4501 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MAX_LATENCY                                                         0x003f
4502 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP_LIST                                                       0x0064
4503 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP                                                            0x0066
4504 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP                                                          0x0068
4505 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL                                                         0x006c
4506 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS                                                       0x006e
4507 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP                                                            0x0070
4508 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL                                                           0x0074
4509 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS                                                         0x0076
4510 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2                                                         0x0088
4511 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2                                                        0x008c
4512 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS2                                                      0x008e
4513 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2                                                           0x0090
4514 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2                                                          0x0094
4515 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2                                                        0x0096
4516 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_CAP_LIST                                                        0x00a0
4517 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL                                                        0x00a2
4518 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_ADDR_LO                                                     0x00a4
4519 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_ADDR_HI                                                     0x00a8
4520 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_DATA                                                        0x00a8
4521 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MASK                                                            0x00ac
4522 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_DATA_64                                                     0x00ac
4523 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MASK_64                                                         0x00b0
4524 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_PENDING                                                         0x00b0
4525 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_PENDING_64                                                      0x00b4
4526 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSIX_CAP_LIST                                                       0x00c0
4527 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSIX_MSG_CNTL                                                       0x00c2
4528 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSIX_TABLE                                                          0x00c4
4529 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSIX_PBA                                                            0x00c8
4530 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0x0100
4531 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_HDR                                            0x0104
4532 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC1                                               0x0108
4533 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC2                                               0x010c
4534 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0x0150
4535 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS                                              0x0154
4536 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK                                                0x0158
4537 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY                                            0x015c
4538 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS                                                0x0160
4539 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK                                                  0x0164
4540 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL                                               0x0168
4541 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG0                                                       0x016c
4542 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG1                                                       0x0170
4543 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG2                                                       0x0174
4544 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG3                                                       0x0178
4545 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG0                                                0x0188
4546 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG1                                                0x018c
4547 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG2                                                0x0190
4548 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG3                                                0x0194
4549 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_ENH_CAP_LIST                                               0x02b0
4550 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CAP                                                        0x02b4
4551 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CNTL                                                       0x02b6
4552 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_ENH_CAP_LIST                                               0x0328
4553 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CAP                                                        0x032c
4554 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CNTL                                                       0x032e
4555 
4556 
4557 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf28_bifcfgdecp
4558 // base address: 0x0
4559 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_VENDOR_ID                                                           0x0000
4560 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_ID                                                           0x0002
4561 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_COMMAND                                                             0x0004
4562 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_STATUS                                                              0x0006
4563 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_REVISION_ID                                                         0x0008
4564 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PROG_INTERFACE                                                      0x0009
4565 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_SUB_CLASS                                                           0x000a
4566 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_CLASS                                                          0x000b
4567 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_CACHE_LINE                                                          0x000c
4568 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_LATENCY                                                             0x000d
4569 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_HEADER                                                              0x000e
4570 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_BIST                                                                0x000f
4571 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_1                                                         0x0010
4572 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_2                                                         0x0014
4573 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_3                                                         0x0018
4574 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_4                                                         0x001c
4575 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_5                                                         0x0020
4576 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_6                                                         0x0024
4577 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_CARDBUS_CIS_PTR                                                     0x0028
4578 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_ADAPTER_ID                                                          0x002c
4579 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_ROM_BASE_ADDR                                                       0x0030
4580 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_CAP_PTR                                                             0x0034
4581 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_INTERRUPT_LINE                                                      0x003c
4582 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_INTERRUPT_PIN                                                       0x003d
4583 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MIN_GRANT                                                           0x003e
4584 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MAX_LATENCY                                                         0x003f
4585 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP_LIST                                                       0x0064
4586 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP                                                            0x0066
4587 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP                                                          0x0068
4588 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL                                                         0x006c
4589 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS                                                       0x006e
4590 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP                                                            0x0070
4591 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL                                                           0x0074
4592 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS                                                         0x0076
4593 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2                                                         0x0088
4594 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2                                                        0x008c
4595 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS2                                                      0x008e
4596 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2                                                           0x0090
4597 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2                                                          0x0094
4598 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2                                                        0x0096
4599 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_CAP_LIST                                                        0x00a0
4600 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL                                                        0x00a2
4601 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_ADDR_LO                                                     0x00a4
4602 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_ADDR_HI                                                     0x00a8
4603 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_DATA                                                        0x00a8
4604 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MASK                                                            0x00ac
4605 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_DATA_64                                                     0x00ac
4606 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MASK_64                                                         0x00b0
4607 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_PENDING                                                         0x00b0
4608 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_PENDING_64                                                      0x00b4
4609 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSIX_CAP_LIST                                                       0x00c0
4610 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSIX_MSG_CNTL                                                       0x00c2
4611 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSIX_TABLE                                                          0x00c4
4612 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSIX_PBA                                                            0x00c8
4613 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0x0100
4614 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_HDR                                            0x0104
4615 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC1                                               0x0108
4616 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC2                                               0x010c
4617 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0x0150
4618 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS                                              0x0154
4619 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK                                                0x0158
4620 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY                                            0x015c
4621 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS                                                0x0160
4622 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK                                                  0x0164
4623 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL                                               0x0168
4624 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG0                                                       0x016c
4625 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG1                                                       0x0170
4626 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG2                                                       0x0174
4627 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG3                                                       0x0178
4628 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG0                                                0x0188
4629 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG1                                                0x018c
4630 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG2                                                0x0190
4631 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG3                                                0x0194
4632 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_ENH_CAP_LIST                                               0x02b0
4633 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CAP                                                        0x02b4
4634 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CNTL                                                       0x02b6
4635 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_ENH_CAP_LIST                                               0x0328
4636 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CAP                                                        0x032c
4637 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CNTL                                                       0x032e
4638 
4639 
4640 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf29_bifcfgdecp
4641 // base address: 0x0
4642 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_VENDOR_ID                                                           0x0000
4643 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_ID                                                           0x0002
4644 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_COMMAND                                                             0x0004
4645 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_STATUS                                                              0x0006
4646 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_REVISION_ID                                                         0x0008
4647 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PROG_INTERFACE                                                      0x0009
4648 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_SUB_CLASS                                                           0x000a
4649 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_CLASS                                                          0x000b
4650 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_CACHE_LINE                                                          0x000c
4651 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_LATENCY                                                             0x000d
4652 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_HEADER                                                              0x000e
4653 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_BIST                                                                0x000f
4654 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_1                                                         0x0010
4655 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_2                                                         0x0014
4656 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_3                                                         0x0018
4657 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_4                                                         0x001c
4658 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_5                                                         0x0020
4659 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_6                                                         0x0024
4660 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_CARDBUS_CIS_PTR                                                     0x0028
4661 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_ADAPTER_ID                                                          0x002c
4662 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_ROM_BASE_ADDR                                                       0x0030
4663 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_CAP_PTR                                                             0x0034
4664 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_INTERRUPT_LINE                                                      0x003c
4665 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_INTERRUPT_PIN                                                       0x003d
4666 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MIN_GRANT                                                           0x003e
4667 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MAX_LATENCY                                                         0x003f
4668 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP_LIST                                                       0x0064
4669 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP                                                            0x0066
4670 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP                                                          0x0068
4671 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL                                                         0x006c
4672 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS                                                       0x006e
4673 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP                                                            0x0070
4674 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL                                                           0x0074
4675 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS                                                         0x0076
4676 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2                                                         0x0088
4677 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2                                                        0x008c
4678 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS2                                                      0x008e
4679 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2                                                           0x0090
4680 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2                                                          0x0094
4681 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2                                                        0x0096
4682 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_CAP_LIST                                                        0x00a0
4683 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL                                                        0x00a2
4684 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_ADDR_LO                                                     0x00a4
4685 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_ADDR_HI                                                     0x00a8
4686 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_DATA                                                        0x00a8
4687 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MASK                                                            0x00ac
4688 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_DATA_64                                                     0x00ac
4689 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MASK_64                                                         0x00b0
4690 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_PENDING                                                         0x00b0
4691 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_PENDING_64                                                      0x00b4
4692 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSIX_CAP_LIST                                                       0x00c0
4693 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSIX_MSG_CNTL                                                       0x00c2
4694 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSIX_TABLE                                                          0x00c4
4695 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSIX_PBA                                                            0x00c8
4696 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0x0100
4697 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_HDR                                            0x0104
4698 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC1                                               0x0108
4699 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC2                                               0x010c
4700 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0x0150
4701 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS                                              0x0154
4702 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK                                                0x0158
4703 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY                                            0x015c
4704 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS                                                0x0160
4705 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK                                                  0x0164
4706 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL                                               0x0168
4707 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG0                                                       0x016c
4708 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG1                                                       0x0170
4709 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG2                                                       0x0174
4710 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG3                                                       0x0178
4711 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG0                                                0x0188
4712 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG1                                                0x018c
4713 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG2                                                0x0190
4714 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG3                                                0x0194
4715 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_ENH_CAP_LIST                                               0x02b0
4716 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CAP                                                        0x02b4
4717 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CNTL                                                       0x02b6
4718 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_ENH_CAP_LIST                                               0x0328
4719 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CAP                                                        0x032c
4720 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CNTL                                                       0x032e
4721 
4722 
4723 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf30_bifcfgdecp
4724 // base address: 0x0
4725 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_VENDOR_ID                                                           0x0000
4726 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_ID                                                           0x0002
4727 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_COMMAND                                                             0x0004
4728 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_STATUS                                                              0x0006
4729 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_REVISION_ID                                                         0x0008
4730 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PROG_INTERFACE                                                      0x0009
4731 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_SUB_CLASS                                                           0x000a
4732 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_CLASS                                                          0x000b
4733 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_CACHE_LINE                                                          0x000c
4734 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_LATENCY                                                             0x000d
4735 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_HEADER                                                              0x000e
4736 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_BIST                                                                0x000f
4737 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_1                                                         0x0010
4738 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_2                                                         0x0014
4739 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_3                                                         0x0018
4740 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_4                                                         0x001c
4741 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_5                                                         0x0020
4742 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_6                                                         0x0024
4743 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_CARDBUS_CIS_PTR                                                     0x0028
4744 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_ADAPTER_ID                                                          0x002c
4745 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_ROM_BASE_ADDR                                                       0x0030
4746 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_CAP_PTR                                                             0x0034
4747 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_INTERRUPT_LINE                                                      0x003c
4748 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_INTERRUPT_PIN                                                       0x003d
4749 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MIN_GRANT                                                           0x003e
4750 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MAX_LATENCY                                                         0x003f
4751 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP_LIST                                                       0x0064
4752 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP                                                            0x0066
4753 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP                                                          0x0068
4754 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL                                                         0x006c
4755 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS                                                       0x006e
4756 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP                                                            0x0070
4757 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL                                                           0x0074
4758 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS                                                         0x0076
4759 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2                                                         0x0088
4760 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2                                                        0x008c
4761 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS2                                                      0x008e
4762 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2                                                           0x0090
4763 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2                                                          0x0094
4764 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2                                                        0x0096
4765 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_CAP_LIST                                                        0x00a0
4766 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL                                                        0x00a2
4767 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_ADDR_LO                                                     0x00a4
4768 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_ADDR_HI                                                     0x00a8
4769 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_DATA                                                        0x00a8
4770 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MASK                                                            0x00ac
4771 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_DATA_64                                                     0x00ac
4772 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MASK_64                                                         0x00b0
4773 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_PENDING                                                         0x00b0
4774 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_PENDING_64                                                      0x00b4
4775 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSIX_CAP_LIST                                                       0x00c0
4776 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSIX_MSG_CNTL                                                       0x00c2
4777 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSIX_TABLE                                                          0x00c4
4778 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSIX_PBA                                                            0x00c8
4779 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0x0100
4780 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_HDR                                            0x0104
4781 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC1                                               0x0108
4782 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC2                                               0x010c
4783 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0x0150
4784 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS                                              0x0154
4785 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK                                                0x0158
4786 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY                                            0x015c
4787 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS                                                0x0160
4788 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK                                                  0x0164
4789 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL                                               0x0168
4790 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG0                                                       0x016c
4791 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG1                                                       0x0170
4792 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG2                                                       0x0174
4793 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG3                                                       0x0178
4794 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG0                                                0x0188
4795 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG1                                                0x018c
4796 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG2                                                0x0190
4797 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG3                                                0x0194
4798 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_ENH_CAP_LIST                                               0x02b0
4799 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CAP                                                        0x02b4
4800 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CNTL                                                       0x02b6
4801 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_ENH_CAP_LIST                                               0x0328
4802 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CAP                                                        0x032c
4803 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CNTL                                                       0x032e
4804 
4805 
4806 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC
4807 // base address: 0x0
4808 #define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX                                                                0x0000
4809 #define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_BASE_IDX                                                       0
4810 #define mmBIF_BX_DEV0_EPF0_VF0_MM_DATA                                                                 0x0001
4811 #define mmBIF_BX_DEV0_EPF0_VF0_MM_DATA_BASE_IDX                                                        0
4812 #define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI                                                             0x0006
4813 #define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI_BASE_IDX                                                    0
4814 
4815 
4816 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFPFVFDEC1
4817 // base address: 0x0
4818 #define mmRCC_DEV0_EPF0_VF0_RCC_ERR_LOG                                                                0x0085
4819 #define mmRCC_DEV0_EPF0_VF0_RCC_ERR_LOG_BASE_IDX                                                       2
4820 #define mmRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN                                                       0x00c0
4821 #define mmRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN_BASE_IDX                                              2
4822 #define mmRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE                                                         0x00c3
4823 #define mmRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE_BASE_IDX                                                2
4824 #define mmRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED                                                        0x00c4
4825 #define mmRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED_BASE_IDX                                               2
4826 #define mmRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER                                                    0x00c5
4827 #define mmRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                           2
4828 
4829 
4830 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1
4831 // base address: 0x0
4832 #define mmBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS                                                          0x00eb
4833 #define mmBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS_BASE_IDX                                                 2
4834 #define mmBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG                                                      0x00ec
4835 #define mmBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG_BASE_IDX                                             2
4836 #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                    0x00f3
4837 #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                           2
4838 #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                     0x00f4
4839 #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                            2
4840 #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL                                         0x00f5
4841 #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                                2
4842 #define mmBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL                                            0x00f6
4843 #define mmBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                   2
4844 #define mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL                                            0x00f7
4845 #define mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                   2
4846 #define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ                                                       0x0106
4847 #define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ_BASE_IDX                                              2
4848 #define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE                                                      0x0107
4849 #define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE_BASE_IDX                                             2
4850 #define mmBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING                                                       0x0108
4851 #define mmBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING_BASE_IDX                                              2
4852 #define mmBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS                                                0x0112
4853 #define mmBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                       2
4854 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0                                                  0x0136
4855 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                         2
4856 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1                                                  0x0137
4857 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                         2
4858 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2                                                  0x0138
4859 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                         2
4860 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3                                                  0x0139
4861 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                         2
4862 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0                                                  0x013a
4863 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                         2
4864 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1                                                  0x013b
4865 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                         2
4866 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2                                                  0x013c
4867 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                         2
4868 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3                                                  0x013d
4869 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                         2
4870 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL                                                         0x013e
4871 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL_BASE_IDX                                                2
4872 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL                                                        0x013f
4873 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL_BASE_IDX                                               2
4874 #define mmBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX                                                        0x0140
4875 #define mmBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX_BASE_IDX                                               2
4876 
4877 
4878 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFDEC2
4879 // base address: 0x0
4880 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO                                                      0x0400
4881 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                             3
4882 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI                                                      0x0401
4883 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                             3
4884 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA                                                     0x0402
4885 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                            3
4886 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL                                                      0x0403
4887 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL_BASE_IDX                                             3
4888 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO                                                      0x0404
4889 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                             3
4890 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI                                                      0x0405
4891 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                             3
4892 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA                                                     0x0406
4893 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                            3
4894 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL                                                      0x0407
4895 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL_BASE_IDX                                             3
4896 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO                                                      0x0408
4897 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                             3
4898 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI                                                      0x0409
4899 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                             3
4900 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA                                                     0x040a
4901 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                            3
4902 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL                                                      0x040b
4903 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL_BASE_IDX                                             3
4904 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO                                                      0x040c
4905 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                             3
4906 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI                                                      0x040d
4907 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                             3
4908 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA                                                     0x040e
4909 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                            3
4910 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL                                                      0x040f
4911 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL_BASE_IDX                                             3
4912 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_PBA                                                                0x0800
4913 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_PBA_BASE_IDX                                                       3
4914 
4915 
4916 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC
4917 // base address: 0x0
4918 #define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX                                                                0x0000
4919 #define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_BASE_IDX                                                       0
4920 #define mmBIF_BX_DEV0_EPF0_VF1_MM_DATA                                                                 0x0001
4921 #define mmBIF_BX_DEV0_EPF0_VF1_MM_DATA_BASE_IDX                                                        0
4922 #define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI                                                             0x0006
4923 #define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI_BASE_IDX                                                    0
4924 
4925 
4926 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFPFVFDEC1
4927 // base address: 0x0
4928 #define mmRCC_DEV0_EPF0_VF1_RCC_ERR_LOG                                                                0x0085
4929 #define mmRCC_DEV0_EPF0_VF1_RCC_ERR_LOG_BASE_IDX                                                       2
4930 #define mmRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN                                                       0x00c0
4931 #define mmRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN_BASE_IDX                                              2
4932 #define mmRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE                                                         0x00c3
4933 #define mmRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE_BASE_IDX                                                2
4934 #define mmRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED                                                        0x00c4
4935 #define mmRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED_BASE_IDX                                               2
4936 #define mmRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER                                                    0x00c5
4937 #define mmRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                           2
4938 
4939 
4940 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1
4941 // base address: 0x0
4942 #define mmBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS                                                          0x00eb
4943 #define mmBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS_BASE_IDX                                                 2
4944 #define mmBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG                                                      0x00ec
4945 #define mmBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG_BASE_IDX                                             2
4946 #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                    0x00f3
4947 #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                           2
4948 #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                     0x00f4
4949 #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                            2
4950 #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL                                         0x00f5
4951 #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                                2
4952 #define mmBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL                                            0x00f6
4953 #define mmBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                   2
4954 #define mmBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL                                            0x00f7
4955 #define mmBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                   2
4956 #define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ                                                       0x0106
4957 #define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ_BASE_IDX                                              2
4958 #define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE                                                      0x0107
4959 #define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE_BASE_IDX                                             2
4960 #define mmBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING                                                       0x0108
4961 #define mmBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING_BASE_IDX                                              2
4962 #define mmBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS                                                0x0112
4963 #define mmBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                       2
4964 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0                                                  0x0136
4965 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                         2
4966 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1                                                  0x0137
4967 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                         2
4968 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2                                                  0x0138
4969 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                         2
4970 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3                                                  0x0139
4971 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                         2
4972 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0                                                  0x013a
4973 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                         2
4974 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1                                                  0x013b
4975 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                         2
4976 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2                                                  0x013c
4977 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                         2
4978 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3                                                  0x013d
4979 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                         2
4980 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL                                                         0x013e
4981 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL_BASE_IDX                                                2
4982 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL                                                        0x013f
4983 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL_BASE_IDX                                               2
4984 #define mmBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX                                                        0x0140
4985 #define mmBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX_BASE_IDX                                               2
4986 
4987 
4988 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFDEC2
4989 // base address: 0x0
4990 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO                                                      0x0400
4991 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                             3
4992 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI                                                      0x0401
4993 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                             3
4994 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA                                                     0x0402
4995 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                            3
4996 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL                                                      0x0403
4997 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL_BASE_IDX                                             3
4998 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO                                                      0x0404
4999 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                             3
5000 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI                                                      0x0405
5001 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                             3
5002 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA                                                     0x0406
5003 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                            3
5004 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL                                                      0x0407
5005 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL_BASE_IDX                                             3
5006 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO                                                      0x0408
5007 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                             3
5008 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI                                                      0x0409
5009 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                             3
5010 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA                                                     0x040a
5011 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                            3
5012 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL                                                      0x040b
5013 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL_BASE_IDX                                             3
5014 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO                                                      0x040c
5015 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                             3
5016 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI                                                      0x040d
5017 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                             3
5018 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA                                                     0x040e
5019 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                            3
5020 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL                                                      0x040f
5021 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL_BASE_IDX                                             3
5022 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_PBA                                                                0x0800
5023 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_PBA_BASE_IDX                                                       3
5024 
5025 
5026 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC
5027 // base address: 0x0
5028 #define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX                                                                0x0000
5029 #define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_BASE_IDX                                                       0
5030 #define mmBIF_BX_DEV0_EPF0_VF2_MM_DATA                                                                 0x0001
5031 #define mmBIF_BX_DEV0_EPF0_VF2_MM_DATA_BASE_IDX                                                        0
5032 #define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI                                                             0x0006
5033 #define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI_BASE_IDX                                                    0
5034 
5035 
5036 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFPFVFDEC1
5037 // base address: 0x0
5038 #define mmRCC_DEV0_EPF0_VF2_RCC_ERR_LOG                                                                0x0085
5039 #define mmRCC_DEV0_EPF0_VF2_RCC_ERR_LOG_BASE_IDX                                                       2
5040 #define mmRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN                                                       0x00c0
5041 #define mmRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN_BASE_IDX                                              2
5042 #define mmRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE                                                         0x00c3
5043 #define mmRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE_BASE_IDX                                                2
5044 #define mmRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED                                                        0x00c4
5045 #define mmRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED_BASE_IDX                                               2
5046 #define mmRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER                                                    0x00c5
5047 #define mmRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                           2
5048 
5049 
5050 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1
5051 // base address: 0x0
5052 #define mmBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS                                                          0x00eb
5053 #define mmBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS_BASE_IDX                                                 2
5054 #define mmBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG                                                      0x00ec
5055 #define mmBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG_BASE_IDX                                             2
5056 #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                    0x00f3
5057 #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                           2
5058 #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                     0x00f4
5059 #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                            2
5060 #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL                                         0x00f5
5061 #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                                2
5062 #define mmBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL                                            0x00f6
5063 #define mmBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                   2
5064 #define mmBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL                                            0x00f7
5065 #define mmBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                   2
5066 #define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ                                                       0x0106
5067 #define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ_BASE_IDX                                              2
5068 #define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE                                                      0x0107
5069 #define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE_BASE_IDX                                             2
5070 #define mmBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING                                                       0x0108
5071 #define mmBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING_BASE_IDX                                              2
5072 #define mmBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS                                                0x0112
5073 #define mmBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                       2
5074 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0                                                  0x0136
5075 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                         2
5076 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1                                                  0x0137
5077 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                         2
5078 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2                                                  0x0138
5079 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                         2
5080 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3                                                  0x0139
5081 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                         2
5082 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0                                                  0x013a
5083 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                         2
5084 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1                                                  0x013b
5085 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                         2
5086 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2                                                  0x013c
5087 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                         2
5088 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3                                                  0x013d
5089 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                         2
5090 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL                                                         0x013e
5091 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL_BASE_IDX                                                2
5092 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL                                                        0x013f
5093 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL_BASE_IDX                                               2
5094 #define mmBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX                                                        0x0140
5095 #define mmBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX_BASE_IDX                                               2
5096 
5097 
5098 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFDEC2
5099 // base address: 0x0
5100 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO                                                      0x0400
5101 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                             3
5102 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI                                                      0x0401
5103 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                             3
5104 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA                                                     0x0402
5105 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                            3
5106 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL                                                      0x0403
5107 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL_BASE_IDX                                             3
5108 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO                                                      0x0404
5109 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                             3
5110 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI                                                      0x0405
5111 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                             3
5112 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA                                                     0x0406
5113 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                            3
5114 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL                                                      0x0407
5115 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL_BASE_IDX                                             3
5116 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO                                                      0x0408
5117 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                             3
5118 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI                                                      0x0409
5119 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                             3
5120 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA                                                     0x040a
5121 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                            3
5122 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL                                                      0x040b
5123 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL_BASE_IDX                                             3
5124 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO                                                      0x040c
5125 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                             3
5126 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI                                                      0x040d
5127 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                             3
5128 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA                                                     0x040e
5129 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                            3
5130 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL                                                      0x040f
5131 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL_BASE_IDX                                             3
5132 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_PBA                                                                0x0800
5133 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_PBA_BASE_IDX                                                       3
5134 
5135 
5136 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC
5137 // base address: 0x0
5138 #define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX                                                                0x0000
5139 #define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_BASE_IDX                                                       0
5140 #define mmBIF_BX_DEV0_EPF0_VF3_MM_DATA                                                                 0x0001
5141 #define mmBIF_BX_DEV0_EPF0_VF3_MM_DATA_BASE_IDX                                                        0
5142 #define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI                                                             0x0006
5143 #define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI_BASE_IDX                                                    0
5144 
5145 
5146 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFPFVFDEC1
5147 // base address: 0x0
5148 #define mmRCC_DEV0_EPF0_VF3_RCC_ERR_LOG                                                                0x0085
5149 #define mmRCC_DEV0_EPF0_VF3_RCC_ERR_LOG_BASE_IDX                                                       2
5150 #define mmRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN                                                       0x00c0
5151 #define mmRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN_BASE_IDX                                              2
5152 #define mmRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE                                                         0x00c3
5153 #define mmRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE_BASE_IDX                                                2
5154 #define mmRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED                                                        0x00c4
5155 #define mmRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED_BASE_IDX                                               2
5156 #define mmRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER                                                    0x00c5
5157 #define mmRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                           2
5158 
5159 
5160 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1
5161 // base address: 0x0
5162 #define mmBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS                                                          0x00eb
5163 #define mmBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS_BASE_IDX                                                 2
5164 #define mmBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG                                                      0x00ec
5165 #define mmBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG_BASE_IDX                                             2
5166 #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                    0x00f3
5167 #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                           2
5168 #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                     0x00f4
5169 #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                            2
5170 #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL                                         0x00f5
5171 #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                                2
5172 #define mmBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL                                            0x00f6
5173 #define mmBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                   2
5174 #define mmBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL                                            0x00f7
5175 #define mmBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                   2
5176 #define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ                                                       0x0106
5177 #define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ_BASE_IDX                                              2
5178 #define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE                                                      0x0107
5179 #define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE_BASE_IDX                                             2
5180 #define mmBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING                                                       0x0108
5181 #define mmBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING_BASE_IDX                                              2
5182 #define mmBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS                                                0x0112
5183 #define mmBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                       2
5184 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0                                                  0x0136
5185 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                         2
5186 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1                                                  0x0137
5187 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                         2
5188 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2                                                  0x0138
5189 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                         2
5190 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3                                                  0x0139
5191 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                         2
5192 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0                                                  0x013a
5193 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                         2
5194 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1                                                  0x013b
5195 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                         2
5196 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2                                                  0x013c
5197 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                         2
5198 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3                                                  0x013d
5199 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                         2
5200 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL                                                         0x013e
5201 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL_BASE_IDX                                                2
5202 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL                                                        0x013f
5203 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL_BASE_IDX                                               2
5204 #define mmBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX                                                        0x0140
5205 #define mmBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX_BASE_IDX                                               2
5206 
5207 
5208 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFDEC2
5209 // base address: 0x0
5210 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO                                                      0x0400
5211 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                             3
5212 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI                                                      0x0401
5213 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                             3
5214 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA                                                     0x0402
5215 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                            3
5216 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL                                                      0x0403
5217 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL_BASE_IDX                                             3
5218 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO                                                      0x0404
5219 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                             3
5220 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI                                                      0x0405
5221 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                             3
5222 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA                                                     0x0406
5223 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                            3
5224 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL                                                      0x0407
5225 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL_BASE_IDX                                             3
5226 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO                                                      0x0408
5227 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                             3
5228 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI                                                      0x0409
5229 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                             3
5230 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA                                                     0x040a
5231 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                            3
5232 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL                                                      0x040b
5233 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL_BASE_IDX                                             3
5234 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO                                                      0x040c
5235 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                             3
5236 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI                                                      0x040d
5237 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                             3
5238 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA                                                     0x040e
5239 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                            3
5240 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL                                                      0x040f
5241 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL_BASE_IDX                                             3
5242 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_PBA                                                                0x0800
5243 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_PBA_BASE_IDX                                                       3
5244 
5245 
5246 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC
5247 // base address: 0x0
5248 #define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX                                                                0x0000
5249 #define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_BASE_IDX                                                       0
5250 #define mmBIF_BX_DEV0_EPF0_VF4_MM_DATA                                                                 0x0001
5251 #define mmBIF_BX_DEV0_EPF0_VF4_MM_DATA_BASE_IDX                                                        0
5252 #define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI                                                             0x0006
5253 #define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI_BASE_IDX                                                    0
5254 
5255 
5256 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFPFVFDEC1
5257 // base address: 0x0
5258 #define mmRCC_DEV0_EPF0_VF4_RCC_ERR_LOG                                                                0x0085
5259 #define mmRCC_DEV0_EPF0_VF4_RCC_ERR_LOG_BASE_IDX                                                       2
5260 #define mmRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN                                                       0x00c0
5261 #define mmRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN_BASE_IDX                                              2
5262 #define mmRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE                                                         0x00c3
5263 #define mmRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE_BASE_IDX                                                2
5264 #define mmRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED                                                        0x00c4
5265 #define mmRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED_BASE_IDX                                               2
5266 #define mmRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER                                                    0x00c5
5267 #define mmRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                           2
5268 
5269 
5270 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1
5271 // base address: 0x0
5272 #define mmBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS                                                          0x00eb
5273 #define mmBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS_BASE_IDX                                                 2
5274 #define mmBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG                                                      0x00ec
5275 #define mmBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG_BASE_IDX                                             2
5276 #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                    0x00f3
5277 #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                           2
5278 #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                     0x00f4
5279 #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                            2
5280 #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL                                         0x00f5
5281 #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                                2
5282 #define mmBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL                                            0x00f6
5283 #define mmBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                   2
5284 #define mmBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL                                            0x00f7
5285 #define mmBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                   2
5286 #define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ                                                       0x0106
5287 #define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ_BASE_IDX                                              2
5288 #define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE                                                      0x0107
5289 #define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE_BASE_IDX                                             2
5290 #define mmBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING                                                       0x0108
5291 #define mmBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING_BASE_IDX                                              2
5292 #define mmBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS                                                0x0112
5293 #define mmBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                       2
5294 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0                                                  0x0136
5295 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                         2
5296 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1                                                  0x0137
5297 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                         2
5298 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2                                                  0x0138
5299 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                         2
5300 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3                                                  0x0139
5301 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                         2
5302 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0                                                  0x013a
5303 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                         2
5304 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1                                                  0x013b
5305 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                         2
5306 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2                                                  0x013c
5307 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                         2
5308 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3                                                  0x013d
5309 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                         2
5310 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL                                                         0x013e
5311 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL_BASE_IDX                                                2
5312 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL                                                        0x013f
5313 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL_BASE_IDX                                               2
5314 #define mmBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX                                                        0x0140
5315 #define mmBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX_BASE_IDX                                               2
5316 
5317 
5318 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFDEC2
5319 // base address: 0x0
5320 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO                                                      0x0400
5321 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                             3
5322 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI                                                      0x0401
5323 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                             3
5324 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA                                                     0x0402
5325 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                            3
5326 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL                                                      0x0403
5327 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL_BASE_IDX                                             3
5328 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO                                                      0x0404
5329 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                             3
5330 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI                                                      0x0405
5331 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                             3
5332 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA                                                     0x0406
5333 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                            3
5334 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL                                                      0x0407
5335 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL_BASE_IDX                                             3
5336 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO                                                      0x0408
5337 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                             3
5338 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI                                                      0x0409
5339 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                             3
5340 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA                                                     0x040a
5341 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                            3
5342 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL                                                      0x040b
5343 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL_BASE_IDX                                             3
5344 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO                                                      0x040c
5345 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                             3
5346 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI                                                      0x040d
5347 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                             3
5348 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA                                                     0x040e
5349 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                            3
5350 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL                                                      0x040f
5351 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL_BASE_IDX                                             3
5352 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_PBA                                                                0x0800
5353 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_PBA_BASE_IDX                                                       3
5354 
5355 
5356 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC
5357 // base address: 0x0
5358 #define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX                                                                0x0000
5359 #define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_BASE_IDX                                                       0
5360 #define mmBIF_BX_DEV0_EPF0_VF5_MM_DATA                                                                 0x0001
5361 #define mmBIF_BX_DEV0_EPF0_VF5_MM_DATA_BASE_IDX                                                        0
5362 #define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI                                                             0x0006
5363 #define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI_BASE_IDX                                                    0
5364 
5365 
5366 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFPFVFDEC1
5367 // base address: 0x0
5368 #define mmRCC_DEV0_EPF0_VF5_RCC_ERR_LOG                                                                0x0085
5369 #define mmRCC_DEV0_EPF0_VF5_RCC_ERR_LOG_BASE_IDX                                                       2
5370 #define mmRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN                                                       0x00c0
5371 #define mmRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN_BASE_IDX                                              2
5372 #define mmRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE                                                         0x00c3
5373 #define mmRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE_BASE_IDX                                                2
5374 #define mmRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED                                                        0x00c4
5375 #define mmRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED_BASE_IDX                                               2
5376 #define mmRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER                                                    0x00c5
5377 #define mmRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                           2
5378 
5379 
5380 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1
5381 // base address: 0x0
5382 #define mmBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS                                                          0x00eb
5383 #define mmBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS_BASE_IDX                                                 2
5384 #define mmBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG                                                      0x00ec
5385 #define mmBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG_BASE_IDX                                             2
5386 #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                    0x00f3
5387 #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                           2
5388 #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                     0x00f4
5389 #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                            2
5390 #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL                                         0x00f5
5391 #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                                2
5392 #define mmBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL                                            0x00f6
5393 #define mmBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                   2
5394 #define mmBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL                                            0x00f7
5395 #define mmBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                   2
5396 #define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ                                                       0x0106
5397 #define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ_BASE_IDX                                              2
5398 #define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE                                                      0x0107
5399 #define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE_BASE_IDX                                             2
5400 #define mmBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING                                                       0x0108
5401 #define mmBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING_BASE_IDX                                              2
5402 #define mmBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS                                                0x0112
5403 #define mmBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                       2
5404 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0                                                  0x0136
5405 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                         2
5406 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1                                                  0x0137
5407 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                         2
5408 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2                                                  0x0138
5409 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                         2
5410 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3                                                  0x0139
5411 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                         2
5412 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0                                                  0x013a
5413 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                         2
5414 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1                                                  0x013b
5415 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                         2
5416 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2                                                  0x013c
5417 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                         2
5418 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3                                                  0x013d
5419 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                         2
5420 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL                                                         0x013e
5421 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL_BASE_IDX                                                2
5422 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL                                                        0x013f
5423 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL_BASE_IDX                                               2
5424 #define mmBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX                                                        0x0140
5425 #define mmBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX_BASE_IDX                                               2
5426 
5427 
5428 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFDEC2
5429 // base address: 0x0
5430 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO                                                      0x0400
5431 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                             3
5432 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI                                                      0x0401
5433 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                             3
5434 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA                                                     0x0402
5435 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                            3
5436 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL                                                      0x0403
5437 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL_BASE_IDX                                             3
5438 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO                                                      0x0404
5439 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                             3
5440 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI                                                      0x0405
5441 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                             3
5442 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA                                                     0x0406
5443 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                            3
5444 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL                                                      0x0407
5445 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL_BASE_IDX                                             3
5446 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO                                                      0x0408
5447 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                             3
5448 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI                                                      0x0409
5449 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                             3
5450 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA                                                     0x040a
5451 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                            3
5452 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL                                                      0x040b
5453 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL_BASE_IDX                                             3
5454 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO                                                      0x040c
5455 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                             3
5456 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI                                                      0x040d
5457 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                             3
5458 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA                                                     0x040e
5459 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                            3
5460 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL                                                      0x040f
5461 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL_BASE_IDX                                             3
5462 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_PBA                                                                0x0800
5463 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_PBA_BASE_IDX                                                       3
5464 
5465 
5466 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC
5467 // base address: 0x0
5468 #define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX                                                                0x0000
5469 #define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_BASE_IDX                                                       0
5470 #define mmBIF_BX_DEV0_EPF0_VF6_MM_DATA                                                                 0x0001
5471 #define mmBIF_BX_DEV0_EPF0_VF6_MM_DATA_BASE_IDX                                                        0
5472 #define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI                                                             0x0006
5473 #define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI_BASE_IDX                                                    0
5474 
5475 
5476 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFPFVFDEC1
5477 // base address: 0x0
5478 #define mmRCC_DEV0_EPF0_VF6_RCC_ERR_LOG                                                                0x0085
5479 #define mmRCC_DEV0_EPF0_VF6_RCC_ERR_LOG_BASE_IDX                                                       2
5480 #define mmRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN                                                       0x00c0
5481 #define mmRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN_BASE_IDX                                              2
5482 #define mmRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE                                                         0x00c3
5483 #define mmRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE_BASE_IDX                                                2
5484 #define mmRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED                                                        0x00c4
5485 #define mmRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED_BASE_IDX                                               2
5486 #define mmRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER                                                    0x00c5
5487 #define mmRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                           2
5488 
5489 
5490 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1
5491 // base address: 0x0
5492 #define mmBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS                                                          0x00eb
5493 #define mmBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS_BASE_IDX                                                 2
5494 #define mmBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG                                                      0x00ec
5495 #define mmBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG_BASE_IDX                                             2
5496 #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                    0x00f3
5497 #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                           2
5498 #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                     0x00f4
5499 #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                            2
5500 #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL                                         0x00f5
5501 #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                                2
5502 #define mmBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL                                            0x00f6
5503 #define mmBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                   2
5504 #define mmBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL                                            0x00f7
5505 #define mmBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                   2
5506 #define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ                                                       0x0106
5507 #define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ_BASE_IDX                                              2
5508 #define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE                                                      0x0107
5509 #define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE_BASE_IDX                                             2
5510 #define mmBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING                                                       0x0108
5511 #define mmBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING_BASE_IDX                                              2
5512 #define mmBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS                                                0x0112
5513 #define mmBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                       2
5514 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0                                                  0x0136
5515 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                         2
5516 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1                                                  0x0137
5517 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                         2
5518 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2                                                  0x0138
5519 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                         2
5520 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3                                                  0x0139
5521 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                         2
5522 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0                                                  0x013a
5523 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                         2
5524 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1                                                  0x013b
5525 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                         2
5526 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2                                                  0x013c
5527 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                         2
5528 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3                                                  0x013d
5529 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                         2
5530 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL                                                         0x013e
5531 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL_BASE_IDX                                                2
5532 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL                                                        0x013f
5533 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL_BASE_IDX                                               2
5534 #define mmBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX                                                        0x0140
5535 #define mmBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX_BASE_IDX                                               2
5536 
5537 
5538 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFDEC2
5539 // base address: 0x0
5540 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO                                                      0x0400
5541 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                             3
5542 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI                                                      0x0401
5543 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                             3
5544 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA                                                     0x0402
5545 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                            3
5546 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL                                                      0x0403
5547 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL_BASE_IDX                                             3
5548 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO                                                      0x0404
5549 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                             3
5550 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI                                                      0x0405
5551 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                             3
5552 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA                                                     0x0406
5553 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                            3
5554 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL                                                      0x0407
5555 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL_BASE_IDX                                             3
5556 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO                                                      0x0408
5557 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                             3
5558 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI                                                      0x0409
5559 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                             3
5560 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA                                                     0x040a
5561 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                            3
5562 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL                                                      0x040b
5563 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL_BASE_IDX                                             3
5564 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO                                                      0x040c
5565 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                             3
5566 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI                                                      0x040d
5567 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                             3
5568 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA                                                     0x040e
5569 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                            3
5570 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL                                                      0x040f
5571 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL_BASE_IDX                                             3
5572 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_PBA                                                                0x0800
5573 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_PBA_BASE_IDX                                                       3
5574 
5575 
5576 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC
5577 // base address: 0x0
5578 #define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX                                                                0x0000
5579 #define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_BASE_IDX                                                       0
5580 #define mmBIF_BX_DEV0_EPF0_VF7_MM_DATA                                                                 0x0001
5581 #define mmBIF_BX_DEV0_EPF0_VF7_MM_DATA_BASE_IDX                                                        0
5582 #define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI                                                             0x0006
5583 #define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI_BASE_IDX                                                    0
5584 
5585 
5586 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFPFVFDEC1
5587 // base address: 0x0
5588 #define mmRCC_DEV0_EPF0_VF7_RCC_ERR_LOG                                                                0x0085
5589 #define mmRCC_DEV0_EPF0_VF7_RCC_ERR_LOG_BASE_IDX                                                       2
5590 #define mmRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN                                                       0x00c0
5591 #define mmRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN_BASE_IDX                                              2
5592 #define mmRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE                                                         0x00c3
5593 #define mmRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE_BASE_IDX                                                2
5594 #define mmRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED                                                        0x00c4
5595 #define mmRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED_BASE_IDX                                               2
5596 #define mmRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER                                                    0x00c5
5597 #define mmRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                           2
5598 
5599 
5600 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1
5601 // base address: 0x0
5602 #define mmBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS                                                          0x00eb
5603 #define mmBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS_BASE_IDX                                                 2
5604 #define mmBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG                                                      0x00ec
5605 #define mmBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG_BASE_IDX                                             2
5606 #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                    0x00f3
5607 #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                           2
5608 #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                     0x00f4
5609 #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                            2
5610 #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL                                         0x00f5
5611 #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                                2
5612 #define mmBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL                                            0x00f6
5613 #define mmBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                   2
5614 #define mmBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL                                            0x00f7
5615 #define mmBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                   2
5616 #define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ                                                       0x0106
5617 #define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ_BASE_IDX                                              2
5618 #define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE                                                      0x0107
5619 #define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE_BASE_IDX                                             2
5620 #define mmBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING                                                       0x0108
5621 #define mmBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING_BASE_IDX                                              2
5622 #define mmBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS                                                0x0112
5623 #define mmBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                       2
5624 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0                                                  0x0136
5625 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                         2
5626 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1                                                  0x0137
5627 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                         2
5628 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2                                                  0x0138
5629 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                         2
5630 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3                                                  0x0139
5631 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                         2
5632 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0                                                  0x013a
5633 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                         2
5634 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1                                                  0x013b
5635 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                         2
5636 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2                                                  0x013c
5637 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                         2
5638 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3                                                  0x013d
5639 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                         2
5640 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL                                                         0x013e
5641 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL_BASE_IDX                                                2
5642 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL                                                        0x013f
5643 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL_BASE_IDX                                               2
5644 #define mmBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX                                                        0x0140
5645 #define mmBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX_BASE_IDX                                               2
5646 
5647 
5648 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFDEC2
5649 // base address: 0x0
5650 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO                                                      0x0400
5651 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                             3
5652 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI                                                      0x0401
5653 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                             3
5654 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA                                                     0x0402
5655 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                            3
5656 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL                                                      0x0403
5657 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL_BASE_IDX                                             3
5658 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO                                                      0x0404
5659 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                             3
5660 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI                                                      0x0405
5661 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                             3
5662 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA                                                     0x0406
5663 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                            3
5664 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL                                                      0x0407
5665 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL_BASE_IDX                                             3
5666 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO                                                      0x0408
5667 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                             3
5668 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI                                                      0x0409
5669 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                             3
5670 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA                                                     0x040a
5671 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                            3
5672 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL                                                      0x040b
5673 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL_BASE_IDX                                             3
5674 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO                                                      0x040c
5675 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                             3
5676 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI                                                      0x040d
5677 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                             3
5678 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA                                                     0x040e
5679 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                            3
5680 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL                                                      0x040f
5681 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL_BASE_IDX                                             3
5682 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_PBA                                                                0x0800
5683 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_PBA_BASE_IDX                                                       3
5684 
5685 
5686 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_SYSPFVFDEC
5687 // base address: 0x0
5688 #define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX                                                                0x0000
5689 #define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_BASE_IDX                                                       0
5690 #define mmBIF_BX_DEV0_EPF0_VF8_MM_DATA                                                                 0x0001
5691 #define mmBIF_BX_DEV0_EPF0_VF8_MM_DATA_BASE_IDX                                                        0
5692 #define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI                                                             0x0006
5693 #define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI_BASE_IDX                                                    0
5694 
5695 
5696 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFPFVFDEC1
5697 // base address: 0x0
5698 #define mmRCC_DEV0_EPF0_VF8_RCC_ERR_LOG                                                                0x0085
5699 #define mmRCC_DEV0_EPF0_VF8_RCC_ERR_LOG_BASE_IDX                                                       2
5700 #define mmRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN                                                       0x00c0
5701 #define mmRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN_BASE_IDX                                              2
5702 #define mmRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE                                                         0x00c3
5703 #define mmRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE_BASE_IDX                                                2
5704 #define mmRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED                                                        0x00c4
5705 #define mmRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED_BASE_IDX                                               2
5706 #define mmRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER                                                    0x00c5
5707 #define mmRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                           2
5708 
5709 
5710 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_BIFPFVFDEC1
5711 // base address: 0x0
5712 #define mmBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS                                                          0x00eb
5713 #define mmBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS_BASE_IDX                                                 2
5714 #define mmBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG                                                      0x00ec
5715 #define mmBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG_BASE_IDX                                             2
5716 #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                    0x00f3
5717 #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                           2
5718 #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                     0x00f4
5719 #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                            2
5720 #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL                                         0x00f5
5721 #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                                2
5722 #define mmBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL                                            0x00f6
5723 #define mmBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                   2
5724 #define mmBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL                                            0x00f7
5725 #define mmBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                   2
5726 #define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ                                                       0x0106
5727 #define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ_BASE_IDX                                              2
5728 #define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE                                                      0x0107
5729 #define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE_BASE_IDX                                             2
5730 #define mmBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING                                                       0x0108
5731 #define mmBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING_BASE_IDX                                              2
5732 #define mmBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS                                                0x0112
5733 #define mmBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                       2
5734 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0                                                  0x0136
5735 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                         2
5736 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1                                                  0x0137
5737 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                         2
5738 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2                                                  0x0138
5739 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                         2
5740 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3                                                  0x0139
5741 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                         2
5742 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0                                                  0x013a
5743 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                         2
5744 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1                                                  0x013b
5745 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                         2
5746 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2                                                  0x013c
5747 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                         2
5748 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3                                                  0x013d
5749 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                         2
5750 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL                                                         0x013e
5751 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL_BASE_IDX                                                2
5752 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL                                                        0x013f
5753 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL_BASE_IDX                                               2
5754 #define mmBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX                                                        0x0140
5755 #define mmBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX_BASE_IDX                                               2
5756 
5757 
5758 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFDEC2
5759 // base address: 0x0
5760 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO                                                      0x0400
5761 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                             3
5762 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI                                                      0x0401
5763 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                             3
5764 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA                                                     0x0402
5765 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                            3
5766 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL                                                      0x0403
5767 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL_BASE_IDX                                             3
5768 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO                                                      0x0404
5769 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                             3
5770 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI                                                      0x0405
5771 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                             3
5772 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA                                                     0x0406
5773 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                            3
5774 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL                                                      0x0407
5775 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL_BASE_IDX                                             3
5776 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO                                                      0x0408
5777 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                             3
5778 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI                                                      0x0409
5779 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                             3
5780 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA                                                     0x040a
5781 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                            3
5782 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL                                                      0x040b
5783 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL_BASE_IDX                                             3
5784 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO                                                      0x040c
5785 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                             3
5786 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI                                                      0x040d
5787 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                             3
5788 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA                                                     0x040e
5789 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                            3
5790 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL                                                      0x040f
5791 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL_BASE_IDX                                             3
5792 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_PBA                                                                0x0800
5793 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_PBA_BASE_IDX                                                       3
5794 
5795 
5796 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_SYSPFVFDEC
5797 // base address: 0x0
5798 #define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX                                                                0x0000
5799 #define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_BASE_IDX                                                       0
5800 #define mmBIF_BX_DEV0_EPF0_VF9_MM_DATA                                                                 0x0001
5801 #define mmBIF_BX_DEV0_EPF0_VF9_MM_DATA_BASE_IDX                                                        0
5802 #define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI                                                             0x0006
5803 #define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI_BASE_IDX                                                    0
5804 
5805 
5806 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFPFVFDEC1
5807 // base address: 0x0
5808 #define mmRCC_DEV0_EPF0_VF9_RCC_ERR_LOG                                                                0x0085
5809 #define mmRCC_DEV0_EPF0_VF9_RCC_ERR_LOG_BASE_IDX                                                       2
5810 #define mmRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN                                                       0x00c0
5811 #define mmRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN_BASE_IDX                                              2
5812 #define mmRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE                                                         0x00c3
5813 #define mmRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE_BASE_IDX                                                2
5814 #define mmRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED                                                        0x00c4
5815 #define mmRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED_BASE_IDX                                               2
5816 #define mmRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER                                                    0x00c5
5817 #define mmRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                           2
5818 
5819 
5820 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_BIFPFVFDEC1
5821 // base address: 0x0
5822 #define mmBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS                                                          0x00eb
5823 #define mmBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS_BASE_IDX                                                 2
5824 #define mmBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG                                                      0x00ec
5825 #define mmBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG_BASE_IDX                                             2
5826 #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                    0x00f3
5827 #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                           2
5828 #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                     0x00f4
5829 #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                            2
5830 #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL                                         0x00f5
5831 #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                                2
5832 #define mmBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL                                            0x00f6
5833 #define mmBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                   2
5834 #define mmBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL                                            0x00f7
5835 #define mmBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                   2
5836 #define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ                                                       0x0106
5837 #define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ_BASE_IDX                                              2
5838 #define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE                                                      0x0107
5839 #define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE_BASE_IDX                                             2
5840 #define mmBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING                                                       0x0108
5841 #define mmBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING_BASE_IDX                                              2
5842 #define mmBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS                                                0x0112
5843 #define mmBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                       2
5844 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0                                                  0x0136
5845 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                         2
5846 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1                                                  0x0137
5847 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                         2
5848 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2                                                  0x0138
5849 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                         2
5850 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3                                                  0x0139
5851 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                         2
5852 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0                                                  0x013a
5853 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                         2
5854 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1                                                  0x013b
5855 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                         2
5856 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2                                                  0x013c
5857 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                         2
5858 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3                                                  0x013d
5859 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                         2
5860 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL                                                         0x013e
5861 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL_BASE_IDX                                                2
5862 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL                                                        0x013f
5863 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL_BASE_IDX                                               2
5864 #define mmBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX                                                        0x0140
5865 #define mmBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX_BASE_IDX                                               2
5866 
5867 
5868 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFDEC2
5869 // base address: 0x0
5870 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO                                                      0x0400
5871 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                             3
5872 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI                                                      0x0401
5873 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                             3
5874 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA                                                     0x0402
5875 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                            3
5876 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL                                                      0x0403
5877 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL_BASE_IDX                                             3
5878 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO                                                      0x0404
5879 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                             3
5880 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI                                                      0x0405
5881 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                             3
5882 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA                                                     0x0406
5883 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                            3
5884 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL                                                      0x0407
5885 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL_BASE_IDX                                             3
5886 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO                                                      0x0408
5887 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                             3
5888 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI                                                      0x0409
5889 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                             3
5890 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA                                                     0x040a
5891 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                            3
5892 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL                                                      0x040b
5893 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL_BASE_IDX                                             3
5894 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO                                                      0x040c
5895 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                             3
5896 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI                                                      0x040d
5897 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                             3
5898 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA                                                     0x040e
5899 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                            3
5900 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL                                                      0x040f
5901 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL_BASE_IDX                                             3
5902 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_PBA                                                                0x0800
5903 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_PBA_BASE_IDX                                                       3
5904 
5905 
5906 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_SYSPFVFDEC
5907 // base address: 0x0
5908 #define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX                                                               0x0000
5909 #define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_BASE_IDX                                                      0
5910 #define mmBIF_BX_DEV0_EPF0_VF10_MM_DATA                                                                0x0001
5911 #define mmBIF_BX_DEV0_EPF0_VF10_MM_DATA_BASE_IDX                                                       0
5912 #define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI                                                            0x0006
5913 #define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI_BASE_IDX                                                   0
5914 
5915 
5916 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFPFVFDEC1
5917 // base address: 0x0
5918 #define mmRCC_DEV0_EPF0_VF10_RCC_ERR_LOG                                                               0x0085
5919 #define mmRCC_DEV0_EPF0_VF10_RCC_ERR_LOG_BASE_IDX                                                      2
5920 #define mmRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN                                                      0x00c0
5921 #define mmRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN_BASE_IDX                                             2
5922 #define mmRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE                                                        0x00c3
5923 #define mmRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE_BASE_IDX                                               2
5924 #define mmRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED                                                       0x00c4
5925 #define mmRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED_BASE_IDX                                              2
5926 #define mmRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER                                                   0x00c5
5927 #define mmRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                          2
5928 
5929 
5930 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_BIFPFVFDEC1
5931 // base address: 0x0
5932 #define mmBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS                                                         0x00eb
5933 #define mmBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS_BASE_IDX                                                2
5934 #define mmBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG                                                     0x00ec
5935 #define mmBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG_BASE_IDX                                            2
5936 #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0x00f3
5937 #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                          2
5938 #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0x00f4
5939 #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                           2
5940 #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL                                        0x00f5
5941 #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                               2
5942 #define mmBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL                                           0x00f6
5943 #define mmBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
5944 #define mmBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0x00f7
5945 #define mmBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
5946 #define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ                                                      0x0106
5947 #define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ_BASE_IDX                                             2
5948 #define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE                                                     0x0107
5949 #define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE_BASE_IDX                                            2
5950 #define mmBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING                                                      0x0108
5951 #define mmBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING_BASE_IDX                                             2
5952 #define mmBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS                                               0x0112
5953 #define mmBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                      2
5954 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0                                                 0x0136
5955 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                        2
5956 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1                                                 0x0137
5957 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                        2
5958 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2                                                 0x0138
5959 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                        2
5960 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3                                                 0x0139
5961 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                        2
5962 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0                                                 0x013a
5963 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                        2
5964 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1                                                 0x013b
5965 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                        2
5966 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2                                                 0x013c
5967 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                        2
5968 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3                                                 0x013d
5969 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                        2
5970 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL                                                        0x013e
5971 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL_BASE_IDX                                               2
5972 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL                                                       0x013f
5973 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL_BASE_IDX                                              2
5974 #define mmBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX                                                       0x0140
5975 #define mmBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX_BASE_IDX                                              2
5976 
5977 
5978 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFDEC2
5979 // base address: 0x0
5980 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO                                                     0x0400
5981 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                            3
5982 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI                                                     0x0401
5983 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                            3
5984 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA                                                    0x0402
5985 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                           3
5986 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL                                                     0x0403
5987 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL_BASE_IDX                                            3
5988 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO                                                     0x0404
5989 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                            3
5990 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI                                                     0x0405
5991 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                            3
5992 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA                                                    0x0406
5993 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                           3
5994 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL                                                     0x0407
5995 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL_BASE_IDX                                            3
5996 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO                                                     0x0408
5997 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                            3
5998 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI                                                     0x0409
5999 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                            3
6000 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA                                                    0x040a
6001 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                           3
6002 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL                                                     0x040b
6003 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL_BASE_IDX                                            3
6004 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO                                                     0x040c
6005 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                            3
6006 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI                                                     0x040d
6007 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                            3
6008 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA                                                    0x040e
6009 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                           3
6010 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL                                                     0x040f
6011 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL_BASE_IDX                                            3
6012 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_PBA                                                               0x0800
6013 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_PBA_BASE_IDX                                                      3
6014 
6015 
6016 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_SYSPFVFDEC
6017 // base address: 0x0
6018 #define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX                                                               0x0000
6019 #define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_BASE_IDX                                                      0
6020 #define mmBIF_BX_DEV0_EPF0_VF11_MM_DATA                                                                0x0001
6021 #define mmBIF_BX_DEV0_EPF0_VF11_MM_DATA_BASE_IDX                                                       0
6022 #define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI                                                            0x0006
6023 #define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI_BASE_IDX                                                   0
6024 
6025 
6026 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFPFVFDEC1
6027 // base address: 0x0
6028 #define mmRCC_DEV0_EPF0_VF11_RCC_ERR_LOG                                                               0x0085
6029 #define mmRCC_DEV0_EPF0_VF11_RCC_ERR_LOG_BASE_IDX                                                      2
6030 #define mmRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN                                                      0x00c0
6031 #define mmRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN_BASE_IDX                                             2
6032 #define mmRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE                                                        0x00c3
6033 #define mmRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE_BASE_IDX                                               2
6034 #define mmRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED                                                       0x00c4
6035 #define mmRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED_BASE_IDX                                              2
6036 #define mmRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER                                                   0x00c5
6037 #define mmRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                          2
6038 
6039 
6040 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_BIFPFVFDEC1
6041 // base address: 0x0
6042 #define mmBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS                                                         0x00eb
6043 #define mmBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS_BASE_IDX                                                2
6044 #define mmBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG                                                     0x00ec
6045 #define mmBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG_BASE_IDX                                            2
6046 #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0x00f3
6047 #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                          2
6048 #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0x00f4
6049 #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                           2
6050 #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL                                        0x00f5
6051 #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                               2
6052 #define mmBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL                                           0x00f6
6053 #define mmBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
6054 #define mmBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0x00f7
6055 #define mmBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
6056 #define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ                                                      0x0106
6057 #define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ_BASE_IDX                                             2
6058 #define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE                                                     0x0107
6059 #define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE_BASE_IDX                                            2
6060 #define mmBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING                                                      0x0108
6061 #define mmBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING_BASE_IDX                                             2
6062 #define mmBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS                                               0x0112
6063 #define mmBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                      2
6064 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0                                                 0x0136
6065 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                        2
6066 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1                                                 0x0137
6067 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                        2
6068 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2                                                 0x0138
6069 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                        2
6070 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3                                                 0x0139
6071 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                        2
6072 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0                                                 0x013a
6073 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                        2
6074 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1                                                 0x013b
6075 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                        2
6076 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2                                                 0x013c
6077 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                        2
6078 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3                                                 0x013d
6079 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                        2
6080 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL                                                        0x013e
6081 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL_BASE_IDX                                               2
6082 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL                                                       0x013f
6083 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL_BASE_IDX                                              2
6084 #define mmBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX                                                       0x0140
6085 #define mmBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX_BASE_IDX                                              2
6086 
6087 
6088 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFDEC2
6089 // base address: 0x0
6090 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO                                                     0x0400
6091 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                            3
6092 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI                                                     0x0401
6093 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                            3
6094 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA                                                    0x0402
6095 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                           3
6096 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL                                                     0x0403
6097 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL_BASE_IDX                                            3
6098 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO                                                     0x0404
6099 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                            3
6100 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI                                                     0x0405
6101 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                            3
6102 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA                                                    0x0406
6103 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                           3
6104 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL                                                     0x0407
6105 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL_BASE_IDX                                            3
6106 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO                                                     0x0408
6107 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                            3
6108 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI                                                     0x0409
6109 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                            3
6110 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA                                                    0x040a
6111 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                           3
6112 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL                                                     0x040b
6113 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL_BASE_IDX                                            3
6114 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO                                                     0x040c
6115 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                            3
6116 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI                                                     0x040d
6117 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                            3
6118 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA                                                    0x040e
6119 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                           3
6120 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL                                                     0x040f
6121 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL_BASE_IDX                                            3
6122 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_PBA                                                               0x0800
6123 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_PBA_BASE_IDX                                                      3
6124 
6125 
6126 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_SYSPFVFDEC
6127 // base address: 0x0
6128 #define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX                                                               0x0000
6129 #define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_BASE_IDX                                                      0
6130 #define mmBIF_BX_DEV0_EPF0_VF12_MM_DATA                                                                0x0001
6131 #define mmBIF_BX_DEV0_EPF0_VF12_MM_DATA_BASE_IDX                                                       0
6132 #define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI                                                            0x0006
6133 #define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI_BASE_IDX                                                   0
6134 
6135 
6136 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFPFVFDEC1
6137 // base address: 0x0
6138 #define mmRCC_DEV0_EPF0_VF12_RCC_ERR_LOG                                                               0x0085
6139 #define mmRCC_DEV0_EPF0_VF12_RCC_ERR_LOG_BASE_IDX                                                      2
6140 #define mmRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN                                                      0x00c0
6141 #define mmRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN_BASE_IDX                                             2
6142 #define mmRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE                                                        0x00c3
6143 #define mmRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE_BASE_IDX                                               2
6144 #define mmRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED                                                       0x00c4
6145 #define mmRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED_BASE_IDX                                              2
6146 #define mmRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER                                                   0x00c5
6147 #define mmRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                          2
6148 
6149 
6150 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_BIFPFVFDEC1
6151 // base address: 0x0
6152 #define mmBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS                                                         0x00eb
6153 #define mmBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS_BASE_IDX                                                2
6154 #define mmBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG                                                     0x00ec
6155 #define mmBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG_BASE_IDX                                            2
6156 #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0x00f3
6157 #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                          2
6158 #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0x00f4
6159 #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                           2
6160 #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL                                        0x00f5
6161 #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                               2
6162 #define mmBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL                                           0x00f6
6163 #define mmBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
6164 #define mmBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0x00f7
6165 #define mmBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
6166 #define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ                                                      0x0106
6167 #define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ_BASE_IDX                                             2
6168 #define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE                                                     0x0107
6169 #define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE_BASE_IDX                                            2
6170 #define mmBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING                                                      0x0108
6171 #define mmBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING_BASE_IDX                                             2
6172 #define mmBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS                                               0x0112
6173 #define mmBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                      2
6174 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0                                                 0x0136
6175 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                        2
6176 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1                                                 0x0137
6177 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                        2
6178 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2                                                 0x0138
6179 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                        2
6180 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3                                                 0x0139
6181 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                        2
6182 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0                                                 0x013a
6183 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                        2
6184 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1                                                 0x013b
6185 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                        2
6186 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2                                                 0x013c
6187 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                        2
6188 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3                                                 0x013d
6189 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                        2
6190 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL                                                        0x013e
6191 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL_BASE_IDX                                               2
6192 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL                                                       0x013f
6193 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL_BASE_IDX                                              2
6194 #define mmBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX                                                       0x0140
6195 #define mmBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX_BASE_IDX                                              2
6196 
6197 
6198 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFDEC2
6199 // base address: 0x0
6200 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO                                                     0x0400
6201 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                            3
6202 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI                                                     0x0401
6203 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                            3
6204 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA                                                    0x0402
6205 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                           3
6206 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL                                                     0x0403
6207 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL_BASE_IDX                                            3
6208 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO                                                     0x0404
6209 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                            3
6210 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI                                                     0x0405
6211 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                            3
6212 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA                                                    0x0406
6213 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                           3
6214 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL                                                     0x0407
6215 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL_BASE_IDX                                            3
6216 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO                                                     0x0408
6217 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                            3
6218 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI                                                     0x0409
6219 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                            3
6220 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA                                                    0x040a
6221 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                           3
6222 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL                                                     0x040b
6223 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL_BASE_IDX                                            3
6224 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO                                                     0x040c
6225 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                            3
6226 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI                                                     0x040d
6227 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                            3
6228 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA                                                    0x040e
6229 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                           3
6230 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL                                                     0x040f
6231 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL_BASE_IDX                                            3
6232 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_PBA                                                               0x0800
6233 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_PBA_BASE_IDX                                                      3
6234 
6235 
6236 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_SYSPFVFDEC
6237 // base address: 0x0
6238 #define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX                                                               0x0000
6239 #define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_BASE_IDX                                                      0
6240 #define mmBIF_BX_DEV0_EPF0_VF13_MM_DATA                                                                0x0001
6241 #define mmBIF_BX_DEV0_EPF0_VF13_MM_DATA_BASE_IDX                                                       0
6242 #define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI                                                            0x0006
6243 #define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI_BASE_IDX                                                   0
6244 
6245 
6246 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFPFVFDEC1
6247 // base address: 0x0
6248 #define mmRCC_DEV0_EPF0_VF13_RCC_ERR_LOG                                                               0x0085
6249 #define mmRCC_DEV0_EPF0_VF13_RCC_ERR_LOG_BASE_IDX                                                      2
6250 #define mmRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN                                                      0x00c0
6251 #define mmRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN_BASE_IDX                                             2
6252 #define mmRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE                                                        0x00c3
6253 #define mmRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE_BASE_IDX                                               2
6254 #define mmRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED                                                       0x00c4
6255 #define mmRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED_BASE_IDX                                              2
6256 #define mmRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER                                                   0x00c5
6257 #define mmRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                          2
6258 
6259 
6260 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_BIFPFVFDEC1
6261 // base address: 0x0
6262 #define mmBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS                                                         0x00eb
6263 #define mmBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS_BASE_IDX                                                2
6264 #define mmBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG                                                     0x00ec
6265 #define mmBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG_BASE_IDX                                            2
6266 #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0x00f3
6267 #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                          2
6268 #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0x00f4
6269 #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                           2
6270 #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL                                        0x00f5
6271 #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                               2
6272 #define mmBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL                                           0x00f6
6273 #define mmBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
6274 #define mmBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0x00f7
6275 #define mmBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
6276 #define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ                                                      0x0106
6277 #define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ_BASE_IDX                                             2
6278 #define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE                                                     0x0107
6279 #define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE_BASE_IDX                                            2
6280 #define mmBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING                                                      0x0108
6281 #define mmBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING_BASE_IDX                                             2
6282 #define mmBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS                                               0x0112
6283 #define mmBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                      2
6284 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0                                                 0x0136
6285 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                        2
6286 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1                                                 0x0137
6287 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                        2
6288 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2                                                 0x0138
6289 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                        2
6290 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3                                                 0x0139
6291 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                        2
6292 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0                                                 0x013a
6293 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                        2
6294 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1                                                 0x013b
6295 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                        2
6296 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2                                                 0x013c
6297 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                        2
6298 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3                                                 0x013d
6299 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                        2
6300 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL                                                        0x013e
6301 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL_BASE_IDX                                               2
6302 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL                                                       0x013f
6303 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL_BASE_IDX                                              2
6304 #define mmBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX                                                       0x0140
6305 #define mmBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX_BASE_IDX                                              2
6306 
6307 
6308 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFDEC2
6309 // base address: 0x0
6310 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO                                                     0x0400
6311 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                            3
6312 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI                                                     0x0401
6313 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                            3
6314 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA                                                    0x0402
6315 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                           3
6316 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL                                                     0x0403
6317 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL_BASE_IDX                                            3
6318 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO                                                     0x0404
6319 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                            3
6320 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI                                                     0x0405
6321 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                            3
6322 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA                                                    0x0406
6323 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                           3
6324 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL                                                     0x0407
6325 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL_BASE_IDX                                            3
6326 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO                                                     0x0408
6327 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                            3
6328 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI                                                     0x0409
6329 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                            3
6330 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA                                                    0x040a
6331 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                           3
6332 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL                                                     0x040b
6333 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL_BASE_IDX                                            3
6334 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO                                                     0x040c
6335 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                            3
6336 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI                                                     0x040d
6337 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                            3
6338 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA                                                    0x040e
6339 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                           3
6340 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL                                                     0x040f
6341 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL_BASE_IDX                                            3
6342 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_PBA                                                               0x0800
6343 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_PBA_BASE_IDX                                                      3
6344 
6345 
6346 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_SYSPFVFDEC
6347 // base address: 0x0
6348 #define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX                                                               0x0000
6349 #define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_BASE_IDX                                                      0
6350 #define mmBIF_BX_DEV0_EPF0_VF14_MM_DATA                                                                0x0001
6351 #define mmBIF_BX_DEV0_EPF0_VF14_MM_DATA_BASE_IDX                                                       0
6352 #define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI                                                            0x0006
6353 #define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI_BASE_IDX                                                   0
6354 
6355 
6356 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFPFVFDEC1
6357 // base address: 0x0
6358 #define mmRCC_DEV0_EPF0_VF14_RCC_ERR_LOG                                                               0x0085
6359 #define mmRCC_DEV0_EPF0_VF14_RCC_ERR_LOG_BASE_IDX                                                      2
6360 #define mmRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN                                                      0x00c0
6361 #define mmRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN_BASE_IDX                                             2
6362 #define mmRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE                                                        0x00c3
6363 #define mmRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE_BASE_IDX                                               2
6364 #define mmRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED                                                       0x00c4
6365 #define mmRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED_BASE_IDX                                              2
6366 #define mmRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER                                                   0x00c5
6367 #define mmRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                          2
6368 
6369 
6370 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_BIFPFVFDEC1
6371 // base address: 0x0
6372 #define mmBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS                                                         0x00eb
6373 #define mmBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS_BASE_IDX                                                2
6374 #define mmBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG                                                     0x00ec
6375 #define mmBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG_BASE_IDX                                            2
6376 #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0x00f3
6377 #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                          2
6378 #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0x00f4
6379 #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                           2
6380 #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL                                        0x00f5
6381 #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                               2
6382 #define mmBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL                                           0x00f6
6383 #define mmBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
6384 #define mmBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0x00f7
6385 #define mmBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
6386 #define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ                                                      0x0106
6387 #define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ_BASE_IDX                                             2
6388 #define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE                                                     0x0107
6389 #define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE_BASE_IDX                                            2
6390 #define mmBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING                                                      0x0108
6391 #define mmBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING_BASE_IDX                                             2
6392 #define mmBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS                                               0x0112
6393 #define mmBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                      2
6394 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0                                                 0x0136
6395 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                        2
6396 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1                                                 0x0137
6397 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                        2
6398 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2                                                 0x0138
6399 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                        2
6400 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3                                                 0x0139
6401 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                        2
6402 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0                                                 0x013a
6403 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                        2
6404 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1                                                 0x013b
6405 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                        2
6406 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2                                                 0x013c
6407 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                        2
6408 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3                                                 0x013d
6409 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                        2
6410 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL                                                        0x013e
6411 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL_BASE_IDX                                               2
6412 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL                                                       0x013f
6413 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL_BASE_IDX                                              2
6414 #define mmBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX                                                       0x0140
6415 #define mmBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX_BASE_IDX                                              2
6416 
6417 
6418 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFDEC2
6419 // base address: 0x0
6420 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO                                                     0x0400
6421 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                            3
6422 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI                                                     0x0401
6423 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                            3
6424 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA                                                    0x0402
6425 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                           3
6426 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL                                                     0x0403
6427 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL_BASE_IDX                                            3
6428 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO                                                     0x0404
6429 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                            3
6430 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI                                                     0x0405
6431 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                            3
6432 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA                                                    0x0406
6433 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                           3
6434 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL                                                     0x0407
6435 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL_BASE_IDX                                            3
6436 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO                                                     0x0408
6437 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                            3
6438 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI                                                     0x0409
6439 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                            3
6440 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA                                                    0x040a
6441 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                           3
6442 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL                                                     0x040b
6443 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL_BASE_IDX                                            3
6444 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO                                                     0x040c
6445 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                            3
6446 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI                                                     0x040d
6447 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                            3
6448 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA                                                    0x040e
6449 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                           3
6450 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL                                                     0x040f
6451 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL_BASE_IDX                                            3
6452 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_PBA                                                               0x0800
6453 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_PBA_BASE_IDX                                                      3
6454 
6455 
6456 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_SYSPFVFDEC
6457 // base address: 0x0
6458 #define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX                                                               0x0000
6459 #define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_BASE_IDX                                                      0
6460 #define mmBIF_BX_DEV0_EPF0_VF15_MM_DATA                                                                0x0001
6461 #define mmBIF_BX_DEV0_EPF0_VF15_MM_DATA_BASE_IDX                                                       0
6462 #define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI                                                            0x0006
6463 #define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI_BASE_IDX                                                   0
6464 
6465 
6466 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFPFVFDEC1
6467 // base address: 0x0
6468 #define mmRCC_DEV0_EPF0_VF15_RCC_ERR_LOG                                                               0x0085
6469 #define mmRCC_DEV0_EPF0_VF15_RCC_ERR_LOG_BASE_IDX                                                      2
6470 #define mmRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN                                                      0x00c0
6471 #define mmRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN_BASE_IDX                                             2
6472 #define mmRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE                                                        0x00c3
6473 #define mmRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE_BASE_IDX                                               2
6474 #define mmRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED                                                       0x00c4
6475 #define mmRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED_BASE_IDX                                              2
6476 #define mmRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER                                                   0x00c5
6477 #define mmRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                          2
6478 
6479 
6480 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_BIFPFVFDEC1
6481 // base address: 0x0
6482 #define mmBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS                                                         0x00eb
6483 #define mmBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS_BASE_IDX                                                2
6484 #define mmBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG                                                     0x00ec
6485 #define mmBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG_BASE_IDX                                            2
6486 #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0x00f3
6487 #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                          2
6488 #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0x00f4
6489 #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                           2
6490 #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL                                        0x00f5
6491 #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                               2
6492 #define mmBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL                                           0x00f6
6493 #define mmBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
6494 #define mmBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0x00f7
6495 #define mmBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
6496 #define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ                                                      0x0106
6497 #define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ_BASE_IDX                                             2
6498 #define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE                                                     0x0107
6499 #define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE_BASE_IDX                                            2
6500 #define mmBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING                                                      0x0108
6501 #define mmBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING_BASE_IDX                                             2
6502 #define mmBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS                                               0x0112
6503 #define mmBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                      2
6504 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0                                                 0x0136
6505 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                        2
6506 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1                                                 0x0137
6507 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                        2
6508 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2                                                 0x0138
6509 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                        2
6510 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3                                                 0x0139
6511 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                        2
6512 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0                                                 0x013a
6513 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                        2
6514 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1                                                 0x013b
6515 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                        2
6516 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2                                                 0x013c
6517 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                        2
6518 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3                                                 0x013d
6519 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                        2
6520 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL                                                        0x013e
6521 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL_BASE_IDX                                               2
6522 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL                                                       0x013f
6523 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL_BASE_IDX                                              2
6524 #define mmBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX                                                       0x0140
6525 #define mmBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX_BASE_IDX                                              2
6526 
6527 
6528 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFDEC2
6529 // base address: 0x0
6530 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO                                                     0x0400
6531 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                            3
6532 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI                                                     0x0401
6533 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                            3
6534 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA                                                    0x0402
6535 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                           3
6536 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL                                                     0x0403
6537 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL_BASE_IDX                                            3
6538 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO                                                     0x0404
6539 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                            3
6540 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI                                                     0x0405
6541 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                            3
6542 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA                                                    0x0406
6543 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                           3
6544 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL                                                     0x0407
6545 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL_BASE_IDX                                            3
6546 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO                                                     0x0408
6547 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                            3
6548 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI                                                     0x0409
6549 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                            3
6550 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA                                                    0x040a
6551 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                           3
6552 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL                                                     0x040b
6553 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL_BASE_IDX                                            3
6554 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO                                                     0x040c
6555 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                            3
6556 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI                                                     0x040d
6557 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                            3
6558 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA                                                    0x040e
6559 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                           3
6560 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL                                                     0x040f
6561 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL_BASE_IDX                                            3
6562 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_PBA                                                               0x0800
6563 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_PBA_BASE_IDX                                                      3
6564 
6565 
6566 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf16_SYSPFVFDEC
6567 // base address: 0x0
6568 #define mmBIF_BX_DEV0_EPF0_VF16_MM_INDEX                                                               0x0000
6569 #define mmBIF_BX_DEV0_EPF0_VF16_MM_INDEX_BASE_IDX                                                      0
6570 #define mmBIF_BX_DEV0_EPF0_VF16_MM_DATA                                                                0x0001
6571 #define mmBIF_BX_DEV0_EPF0_VF16_MM_DATA_BASE_IDX                                                       0
6572 #define mmBIF_BX_DEV0_EPF0_VF16_MM_INDEX_HI                                                            0x0006
6573 #define mmBIF_BX_DEV0_EPF0_VF16_MM_INDEX_HI_BASE_IDX                                                   0
6574 
6575 
6576 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf16_BIFPFVFDEC1
6577 // base address: 0x0
6578 #define mmRCC_DEV0_EPF0_VF16_RCC_ERR_LOG                                                               0x0085
6579 #define mmRCC_DEV0_EPF0_VF16_RCC_ERR_LOG_BASE_IDX                                                      2
6580 #define mmRCC_DEV0_EPF0_VF16_RCC_DOORBELL_APER_EN                                                      0x00c0
6581 #define mmRCC_DEV0_EPF0_VF16_RCC_DOORBELL_APER_EN_BASE_IDX                                             2
6582 #define mmRCC_DEV0_EPF0_VF16_RCC_CONFIG_MEMSIZE                                                        0x00c3
6583 #define mmRCC_DEV0_EPF0_VF16_RCC_CONFIG_MEMSIZE_BASE_IDX                                               2
6584 #define mmRCC_DEV0_EPF0_VF16_RCC_CONFIG_RESERVED                                                       0x00c4
6585 #define mmRCC_DEV0_EPF0_VF16_RCC_CONFIG_RESERVED_BASE_IDX                                              2
6586 #define mmRCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER                                                   0x00c5
6587 #define mmRCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                          2
6588 
6589 
6590 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf16_BIFPFVFDEC1
6591 // base address: 0x0
6592 #define mmBIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS                                                         0x00eb
6593 #define mmBIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS_BASE_IDX                                                2
6594 #define mmBIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG                                                     0x00ec
6595 #define mmBIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG_BASE_IDX                                            2
6596 #define mmBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0x00f3
6597 #define mmBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                          2
6598 #define mmBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0x00f4
6599 #define mmBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                           2
6600 #define mmBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL                                        0x00f5
6601 #define mmBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                               2
6602 #define mmBIF_BX_DEV0_EPF0_VF16_HDP_REG_COHERENCY_FLUSH_CNTL                                           0x00f6
6603 #define mmBIF_BX_DEV0_EPF0_VF16_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
6604 #define mmBIF_BX_DEV0_EPF0_VF16_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0x00f7
6605 #define mmBIF_BX_DEV0_EPF0_VF16_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
6606 #define mmBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ                                                      0x0106
6607 #define mmBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ_BASE_IDX                                             2
6608 #define mmBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE                                                     0x0107
6609 #define mmBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE_BASE_IDX                                            2
6610 #define mmBIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING                                                      0x0108
6611 #define mmBIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING_BASE_IDX                                             2
6612 #define mmBIF_BX_DEV0_EPF0_VF16_NBIF_GFX_ADDR_LUT_BYPASS                                               0x0112
6613 #define mmBIF_BX_DEV0_EPF0_VF16_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                      2
6614 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW0                                                 0x0136
6615 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                        2
6616 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW1                                                 0x0137
6617 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                        2
6618 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW2                                                 0x0138
6619 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                        2
6620 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW3                                                 0x0139
6621 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                        2
6622 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW0                                                 0x013a
6623 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                        2
6624 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW1                                                 0x013b
6625 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                        2
6626 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW2                                                 0x013c
6627 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                        2
6628 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW3                                                 0x013d
6629 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                        2
6630 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL                                                        0x013e
6631 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL_BASE_IDX                                               2
6632 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL                                                       0x013f
6633 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL_BASE_IDX                                              2
6634 #define mmBIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX                                                       0x0140
6635 #define mmBIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX_BASE_IDX                                              2
6636 
6637 
6638 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf16_BIFDEC2
6639 // base address: 0x0
6640 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_LO                                                     0x0400
6641 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                            3
6642 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_HI                                                     0x0401
6643 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                            3
6644 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_MSG_DATA                                                    0x0402
6645 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                           3
6646 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_CONTROL                                                     0x0403
6647 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_CONTROL_BASE_IDX                                            3
6648 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_LO                                                     0x0404
6649 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                            3
6650 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_HI                                                     0x0405
6651 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                            3
6652 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_MSG_DATA                                                    0x0406
6653 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                           3
6654 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_CONTROL                                                     0x0407
6655 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_CONTROL_BASE_IDX                                            3
6656 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_LO                                                     0x0408
6657 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                            3
6658 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_HI                                                     0x0409
6659 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                            3
6660 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_MSG_DATA                                                    0x040a
6661 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                           3
6662 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_CONTROL                                                     0x040b
6663 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_CONTROL_BASE_IDX                                            3
6664 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_LO                                                     0x040c
6665 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                            3
6666 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_HI                                                     0x040d
6667 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                            3
6668 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_MSG_DATA                                                    0x040e
6669 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                           3
6670 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_CONTROL                                                     0x040f
6671 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_CONTROL_BASE_IDX                                            3
6672 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_PBA                                                               0x0800
6673 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_PBA_BASE_IDX                                                      3
6674 
6675 
6676 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf17_SYSPFVFDEC
6677 // base address: 0x0
6678 #define mmBIF_BX_DEV0_EPF0_VF17_MM_INDEX                                                               0x0000
6679 #define mmBIF_BX_DEV0_EPF0_VF17_MM_INDEX_BASE_IDX                                                      0
6680 #define mmBIF_BX_DEV0_EPF0_VF17_MM_DATA                                                                0x0001
6681 #define mmBIF_BX_DEV0_EPF0_VF17_MM_DATA_BASE_IDX                                                       0
6682 #define mmBIF_BX_DEV0_EPF0_VF17_MM_INDEX_HI                                                            0x0006
6683 #define mmBIF_BX_DEV0_EPF0_VF17_MM_INDEX_HI_BASE_IDX                                                   0
6684 
6685 
6686 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf17_BIFPFVFDEC1
6687 // base address: 0x0
6688 #define mmRCC_DEV0_EPF0_VF17_RCC_ERR_LOG                                                               0x0085
6689 #define mmRCC_DEV0_EPF0_VF17_RCC_ERR_LOG_BASE_IDX                                                      2
6690 #define mmRCC_DEV0_EPF0_VF17_RCC_DOORBELL_APER_EN                                                      0x00c0
6691 #define mmRCC_DEV0_EPF0_VF17_RCC_DOORBELL_APER_EN_BASE_IDX                                             2
6692 #define mmRCC_DEV0_EPF0_VF17_RCC_CONFIG_MEMSIZE                                                        0x00c3
6693 #define mmRCC_DEV0_EPF0_VF17_RCC_CONFIG_MEMSIZE_BASE_IDX                                               2
6694 #define mmRCC_DEV0_EPF0_VF17_RCC_CONFIG_RESERVED                                                       0x00c4
6695 #define mmRCC_DEV0_EPF0_VF17_RCC_CONFIG_RESERVED_BASE_IDX                                              2
6696 #define mmRCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER                                                   0x00c5
6697 #define mmRCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                          2
6698 
6699 
6700 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf17_BIFPFVFDEC1
6701 // base address: 0x0
6702 #define mmBIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS                                                         0x00eb
6703 #define mmBIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS_BASE_IDX                                                2
6704 #define mmBIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG                                                     0x00ec
6705 #define mmBIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG_BASE_IDX                                            2
6706 #define mmBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0x00f3
6707 #define mmBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                          2
6708 #define mmBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0x00f4
6709 #define mmBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                           2
6710 #define mmBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL                                        0x00f5
6711 #define mmBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                               2
6712 #define mmBIF_BX_DEV0_EPF0_VF17_HDP_REG_COHERENCY_FLUSH_CNTL                                           0x00f6
6713 #define mmBIF_BX_DEV0_EPF0_VF17_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
6714 #define mmBIF_BX_DEV0_EPF0_VF17_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0x00f7
6715 #define mmBIF_BX_DEV0_EPF0_VF17_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
6716 #define mmBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ                                                      0x0106
6717 #define mmBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ_BASE_IDX                                             2
6718 #define mmBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE                                                     0x0107
6719 #define mmBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE_BASE_IDX                                            2
6720 #define mmBIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING                                                      0x0108
6721 #define mmBIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING_BASE_IDX                                             2
6722 #define mmBIF_BX_DEV0_EPF0_VF17_NBIF_GFX_ADDR_LUT_BYPASS                                               0x0112
6723 #define mmBIF_BX_DEV0_EPF0_VF17_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                      2
6724 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW0                                                 0x0136
6725 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                        2
6726 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW1                                                 0x0137
6727 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                        2
6728 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW2                                                 0x0138
6729 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                        2
6730 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW3                                                 0x0139
6731 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                        2
6732 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW0                                                 0x013a
6733 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                        2
6734 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW1                                                 0x013b
6735 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                        2
6736 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW2                                                 0x013c
6737 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                        2
6738 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW3                                                 0x013d
6739 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                        2
6740 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL                                                        0x013e
6741 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL_BASE_IDX                                               2
6742 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL                                                       0x013f
6743 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL_BASE_IDX                                              2
6744 #define mmBIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX                                                       0x0140
6745 #define mmBIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX_BASE_IDX                                              2
6746 
6747 
6748 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf17_BIFDEC2
6749 // base address: 0x0
6750 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_LO                                                     0x0400
6751 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                            3
6752 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_HI                                                     0x0401
6753 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                            3
6754 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_MSG_DATA                                                    0x0402
6755 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                           3
6756 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_CONTROL                                                     0x0403
6757 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_CONTROL_BASE_IDX                                            3
6758 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_LO                                                     0x0404
6759 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                            3
6760 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_HI                                                     0x0405
6761 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                            3
6762 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_MSG_DATA                                                    0x0406
6763 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                           3
6764 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_CONTROL                                                     0x0407
6765 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_CONTROL_BASE_IDX                                            3
6766 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_LO                                                     0x0408
6767 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                            3
6768 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_HI                                                     0x0409
6769 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                            3
6770 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_MSG_DATA                                                    0x040a
6771 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                           3
6772 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_CONTROL                                                     0x040b
6773 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_CONTROL_BASE_IDX                                            3
6774 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_LO                                                     0x040c
6775 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                            3
6776 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_HI                                                     0x040d
6777 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                            3
6778 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_MSG_DATA                                                    0x040e
6779 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                           3
6780 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_CONTROL                                                     0x040f
6781 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_CONTROL_BASE_IDX                                            3
6782 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_PBA                                                               0x0800
6783 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_PBA_BASE_IDX                                                      3
6784 
6785 
6786 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf18_SYSPFVFDEC
6787 // base address: 0x0
6788 #define mmBIF_BX_DEV0_EPF0_VF18_MM_INDEX                                                               0x0000
6789 #define mmBIF_BX_DEV0_EPF0_VF18_MM_INDEX_BASE_IDX                                                      0
6790 #define mmBIF_BX_DEV0_EPF0_VF18_MM_DATA                                                                0x0001
6791 #define mmBIF_BX_DEV0_EPF0_VF18_MM_DATA_BASE_IDX                                                       0
6792 #define mmBIF_BX_DEV0_EPF0_VF18_MM_INDEX_HI                                                            0x0006
6793 #define mmBIF_BX_DEV0_EPF0_VF18_MM_INDEX_HI_BASE_IDX                                                   0
6794 
6795 
6796 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf18_BIFPFVFDEC1
6797 // base address: 0x0
6798 #define mmRCC_DEV0_EPF0_VF18_RCC_ERR_LOG                                                               0x0085
6799 #define mmRCC_DEV0_EPF0_VF18_RCC_ERR_LOG_BASE_IDX                                                      2
6800 #define mmRCC_DEV0_EPF0_VF18_RCC_DOORBELL_APER_EN                                                      0x00c0
6801 #define mmRCC_DEV0_EPF0_VF18_RCC_DOORBELL_APER_EN_BASE_IDX                                             2
6802 #define mmRCC_DEV0_EPF0_VF18_RCC_CONFIG_MEMSIZE                                                        0x00c3
6803 #define mmRCC_DEV0_EPF0_VF18_RCC_CONFIG_MEMSIZE_BASE_IDX                                               2
6804 #define mmRCC_DEV0_EPF0_VF18_RCC_CONFIG_RESERVED                                                       0x00c4
6805 #define mmRCC_DEV0_EPF0_VF18_RCC_CONFIG_RESERVED_BASE_IDX                                              2
6806 #define mmRCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER                                                   0x00c5
6807 #define mmRCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                          2
6808 
6809 
6810 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf18_BIFPFVFDEC1
6811 // base address: 0x0
6812 #define mmBIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS                                                         0x00eb
6813 #define mmBIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS_BASE_IDX                                                2
6814 #define mmBIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG                                                     0x00ec
6815 #define mmBIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG_BASE_IDX                                            2
6816 #define mmBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0x00f3
6817 #define mmBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                          2
6818 #define mmBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0x00f4
6819 #define mmBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                           2
6820 #define mmBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL                                        0x00f5
6821 #define mmBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                               2
6822 #define mmBIF_BX_DEV0_EPF0_VF18_HDP_REG_COHERENCY_FLUSH_CNTL                                           0x00f6
6823 #define mmBIF_BX_DEV0_EPF0_VF18_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
6824 #define mmBIF_BX_DEV0_EPF0_VF18_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0x00f7
6825 #define mmBIF_BX_DEV0_EPF0_VF18_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
6826 #define mmBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ                                                      0x0106
6827 #define mmBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ_BASE_IDX                                             2
6828 #define mmBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE                                                     0x0107
6829 #define mmBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE_BASE_IDX                                            2
6830 #define mmBIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING                                                      0x0108
6831 #define mmBIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING_BASE_IDX                                             2
6832 #define mmBIF_BX_DEV0_EPF0_VF18_NBIF_GFX_ADDR_LUT_BYPASS                                               0x0112
6833 #define mmBIF_BX_DEV0_EPF0_VF18_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                      2
6834 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW0                                                 0x0136
6835 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                        2
6836 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW1                                                 0x0137
6837 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                        2
6838 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW2                                                 0x0138
6839 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                        2
6840 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW3                                                 0x0139
6841 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                        2
6842 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW0                                                 0x013a
6843 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                        2
6844 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW1                                                 0x013b
6845 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                        2
6846 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW2                                                 0x013c
6847 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                        2
6848 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW3                                                 0x013d
6849 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                        2
6850 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL                                                        0x013e
6851 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL_BASE_IDX                                               2
6852 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL                                                       0x013f
6853 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL_BASE_IDX                                              2
6854 #define mmBIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX                                                       0x0140
6855 #define mmBIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX_BASE_IDX                                              2
6856 
6857 
6858 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf18_BIFDEC2
6859 // base address: 0x0
6860 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_LO                                                     0x0400
6861 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                            3
6862 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_HI                                                     0x0401
6863 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                            3
6864 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_MSG_DATA                                                    0x0402
6865 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                           3
6866 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_CONTROL                                                     0x0403
6867 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_CONTROL_BASE_IDX                                            3
6868 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_LO                                                     0x0404
6869 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                            3
6870 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_HI                                                     0x0405
6871 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                            3
6872 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_MSG_DATA                                                    0x0406
6873 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                           3
6874 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_CONTROL                                                     0x0407
6875 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_CONTROL_BASE_IDX                                            3
6876 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_LO                                                     0x0408
6877 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                            3
6878 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_HI                                                     0x0409
6879 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                            3
6880 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_MSG_DATA                                                    0x040a
6881 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                           3
6882 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_CONTROL                                                     0x040b
6883 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_CONTROL_BASE_IDX                                            3
6884 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_LO                                                     0x040c
6885 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                            3
6886 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_HI                                                     0x040d
6887 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                            3
6888 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_MSG_DATA                                                    0x040e
6889 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                           3
6890 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_CONTROL                                                     0x040f
6891 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_CONTROL_BASE_IDX                                            3
6892 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_PBA                                                               0x0800
6893 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_PBA_BASE_IDX                                                      3
6894 
6895 
6896 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf19_SYSPFVFDEC
6897 // base address: 0x0
6898 #define mmBIF_BX_DEV0_EPF0_VF19_MM_INDEX                                                               0x0000
6899 #define mmBIF_BX_DEV0_EPF0_VF19_MM_INDEX_BASE_IDX                                                      0
6900 #define mmBIF_BX_DEV0_EPF0_VF19_MM_DATA                                                                0x0001
6901 #define mmBIF_BX_DEV0_EPF0_VF19_MM_DATA_BASE_IDX                                                       0
6902 #define mmBIF_BX_DEV0_EPF0_VF19_MM_INDEX_HI                                                            0x0006
6903 #define mmBIF_BX_DEV0_EPF0_VF19_MM_INDEX_HI_BASE_IDX                                                   0
6904 
6905 
6906 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf19_BIFPFVFDEC1
6907 // base address: 0x0
6908 #define mmRCC_DEV0_EPF0_VF19_RCC_ERR_LOG                                                               0x0085
6909 #define mmRCC_DEV0_EPF0_VF19_RCC_ERR_LOG_BASE_IDX                                                      2
6910 #define mmRCC_DEV0_EPF0_VF19_RCC_DOORBELL_APER_EN                                                      0x00c0
6911 #define mmRCC_DEV0_EPF0_VF19_RCC_DOORBELL_APER_EN_BASE_IDX                                             2
6912 #define mmRCC_DEV0_EPF0_VF19_RCC_CONFIG_MEMSIZE                                                        0x00c3
6913 #define mmRCC_DEV0_EPF0_VF19_RCC_CONFIG_MEMSIZE_BASE_IDX                                               2
6914 #define mmRCC_DEV0_EPF0_VF19_RCC_CONFIG_RESERVED                                                       0x00c4
6915 #define mmRCC_DEV0_EPF0_VF19_RCC_CONFIG_RESERVED_BASE_IDX                                              2
6916 #define mmRCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER                                                   0x00c5
6917 #define mmRCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                          2
6918 
6919 
6920 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf19_BIFPFVFDEC1
6921 // base address: 0x0
6922 #define mmBIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS                                                         0x00eb
6923 #define mmBIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS_BASE_IDX                                                2
6924 #define mmBIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG                                                     0x00ec
6925 #define mmBIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG_BASE_IDX                                            2
6926 #define mmBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0x00f3
6927 #define mmBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                          2
6928 #define mmBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0x00f4
6929 #define mmBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                           2
6930 #define mmBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL                                        0x00f5
6931 #define mmBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                               2
6932 #define mmBIF_BX_DEV0_EPF0_VF19_HDP_REG_COHERENCY_FLUSH_CNTL                                           0x00f6
6933 #define mmBIF_BX_DEV0_EPF0_VF19_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
6934 #define mmBIF_BX_DEV0_EPF0_VF19_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0x00f7
6935 #define mmBIF_BX_DEV0_EPF0_VF19_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
6936 #define mmBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ                                                      0x0106
6937 #define mmBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ_BASE_IDX                                             2
6938 #define mmBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE                                                     0x0107
6939 #define mmBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE_BASE_IDX                                            2
6940 #define mmBIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING                                                      0x0108
6941 #define mmBIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING_BASE_IDX                                             2
6942 #define mmBIF_BX_DEV0_EPF0_VF19_NBIF_GFX_ADDR_LUT_BYPASS                                               0x0112
6943 #define mmBIF_BX_DEV0_EPF0_VF19_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                      2
6944 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW0                                                 0x0136
6945 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                        2
6946 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW1                                                 0x0137
6947 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                        2
6948 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW2                                                 0x0138
6949 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                        2
6950 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW3                                                 0x0139
6951 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                        2
6952 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW0                                                 0x013a
6953 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                        2
6954 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW1                                                 0x013b
6955 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                        2
6956 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW2                                                 0x013c
6957 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                        2
6958 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW3                                                 0x013d
6959 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                        2
6960 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL                                                        0x013e
6961 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL_BASE_IDX                                               2
6962 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL                                                       0x013f
6963 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL_BASE_IDX                                              2
6964 #define mmBIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX                                                       0x0140
6965 #define mmBIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX_BASE_IDX                                              2
6966 
6967 
6968 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf19_BIFDEC2
6969 // base address: 0x0
6970 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_LO                                                     0x0400
6971 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                            3
6972 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_HI                                                     0x0401
6973 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                            3
6974 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_MSG_DATA                                                    0x0402
6975 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                           3
6976 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_CONTROL                                                     0x0403
6977 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_CONTROL_BASE_IDX                                            3
6978 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_LO                                                     0x0404
6979 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                            3
6980 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_HI                                                     0x0405
6981 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                            3
6982 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_MSG_DATA                                                    0x0406
6983 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                           3
6984 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_CONTROL                                                     0x0407
6985 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_CONTROL_BASE_IDX                                            3
6986 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_LO                                                     0x0408
6987 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                            3
6988 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_HI                                                     0x0409
6989 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                            3
6990 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_MSG_DATA                                                    0x040a
6991 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                           3
6992 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_CONTROL                                                     0x040b
6993 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_CONTROL_BASE_IDX                                            3
6994 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_LO                                                     0x040c
6995 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                            3
6996 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_HI                                                     0x040d
6997 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                            3
6998 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_MSG_DATA                                                    0x040e
6999 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                           3
7000 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_CONTROL                                                     0x040f
7001 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_CONTROL_BASE_IDX                                            3
7002 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_PBA                                                               0x0800
7003 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_PBA_BASE_IDX                                                      3
7004 
7005 
7006 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf20_SYSPFVFDEC
7007 // base address: 0x0
7008 #define mmBIF_BX_DEV0_EPF0_VF20_MM_INDEX                                                               0x0000
7009 #define mmBIF_BX_DEV0_EPF0_VF20_MM_INDEX_BASE_IDX                                                      0
7010 #define mmBIF_BX_DEV0_EPF0_VF20_MM_DATA                                                                0x0001
7011 #define mmBIF_BX_DEV0_EPF0_VF20_MM_DATA_BASE_IDX                                                       0
7012 #define mmBIF_BX_DEV0_EPF0_VF20_MM_INDEX_HI                                                            0x0006
7013 #define mmBIF_BX_DEV0_EPF0_VF20_MM_INDEX_HI_BASE_IDX                                                   0
7014 
7015 
7016 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf20_BIFPFVFDEC1
7017 // base address: 0x0
7018 #define mmRCC_DEV0_EPF0_VF20_RCC_ERR_LOG                                                               0x0085
7019 #define mmRCC_DEV0_EPF0_VF20_RCC_ERR_LOG_BASE_IDX                                                      2
7020 #define mmRCC_DEV0_EPF0_VF20_RCC_DOORBELL_APER_EN                                                      0x00c0
7021 #define mmRCC_DEV0_EPF0_VF20_RCC_DOORBELL_APER_EN_BASE_IDX                                             2
7022 #define mmRCC_DEV0_EPF0_VF20_RCC_CONFIG_MEMSIZE                                                        0x00c3
7023 #define mmRCC_DEV0_EPF0_VF20_RCC_CONFIG_MEMSIZE_BASE_IDX                                               2
7024 #define mmRCC_DEV0_EPF0_VF20_RCC_CONFIG_RESERVED                                                       0x00c4
7025 #define mmRCC_DEV0_EPF0_VF20_RCC_CONFIG_RESERVED_BASE_IDX                                              2
7026 #define mmRCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER                                                   0x00c5
7027 #define mmRCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                          2
7028 
7029 
7030 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf20_BIFPFVFDEC1
7031 // base address: 0x0
7032 #define mmBIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS                                                         0x00eb
7033 #define mmBIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS_BASE_IDX                                                2
7034 #define mmBIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG                                                     0x00ec
7035 #define mmBIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG_BASE_IDX                                            2
7036 #define mmBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0x00f3
7037 #define mmBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                          2
7038 #define mmBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0x00f4
7039 #define mmBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                           2
7040 #define mmBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL                                        0x00f5
7041 #define mmBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                               2
7042 #define mmBIF_BX_DEV0_EPF0_VF20_HDP_REG_COHERENCY_FLUSH_CNTL                                           0x00f6
7043 #define mmBIF_BX_DEV0_EPF0_VF20_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
7044 #define mmBIF_BX_DEV0_EPF0_VF20_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0x00f7
7045 #define mmBIF_BX_DEV0_EPF0_VF20_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
7046 #define mmBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ                                                      0x0106
7047 #define mmBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ_BASE_IDX                                             2
7048 #define mmBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE                                                     0x0107
7049 #define mmBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE_BASE_IDX                                            2
7050 #define mmBIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING                                                      0x0108
7051 #define mmBIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING_BASE_IDX                                             2
7052 #define mmBIF_BX_DEV0_EPF0_VF20_NBIF_GFX_ADDR_LUT_BYPASS                                               0x0112
7053 #define mmBIF_BX_DEV0_EPF0_VF20_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                      2
7054 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW0                                                 0x0136
7055 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                        2
7056 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW1                                                 0x0137
7057 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                        2
7058 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW2                                                 0x0138
7059 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                        2
7060 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW3                                                 0x0139
7061 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                        2
7062 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW0                                                 0x013a
7063 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                        2
7064 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW1                                                 0x013b
7065 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                        2
7066 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW2                                                 0x013c
7067 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                        2
7068 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW3                                                 0x013d
7069 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                        2
7070 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL                                                        0x013e
7071 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL_BASE_IDX                                               2
7072 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL                                                       0x013f
7073 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL_BASE_IDX                                              2
7074 #define mmBIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX                                                       0x0140
7075 #define mmBIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX_BASE_IDX                                              2
7076 
7077 
7078 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf20_BIFDEC2
7079 // base address: 0x0
7080 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_LO                                                     0x0400
7081 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                            3
7082 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_HI                                                     0x0401
7083 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                            3
7084 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_MSG_DATA                                                    0x0402
7085 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                           3
7086 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_CONTROL                                                     0x0403
7087 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_CONTROL_BASE_IDX                                            3
7088 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_LO                                                     0x0404
7089 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                            3
7090 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_HI                                                     0x0405
7091 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                            3
7092 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_MSG_DATA                                                    0x0406
7093 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                           3
7094 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_CONTROL                                                     0x0407
7095 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_CONTROL_BASE_IDX                                            3
7096 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_LO                                                     0x0408
7097 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                            3
7098 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_HI                                                     0x0409
7099 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                            3
7100 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_MSG_DATA                                                    0x040a
7101 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                           3
7102 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_CONTROL                                                     0x040b
7103 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_CONTROL_BASE_IDX                                            3
7104 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_LO                                                     0x040c
7105 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                            3
7106 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_HI                                                     0x040d
7107 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                            3
7108 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_MSG_DATA                                                    0x040e
7109 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                           3
7110 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_CONTROL                                                     0x040f
7111 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_CONTROL_BASE_IDX                                            3
7112 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_PBA                                                               0x0800
7113 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_PBA_BASE_IDX                                                      3
7114 
7115 
7116 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf21_SYSPFVFDEC
7117 // base address: 0x0
7118 #define mmBIF_BX_DEV0_EPF0_VF21_MM_INDEX                                                               0x0000
7119 #define mmBIF_BX_DEV0_EPF0_VF21_MM_INDEX_BASE_IDX                                                      0
7120 #define mmBIF_BX_DEV0_EPF0_VF21_MM_DATA                                                                0x0001
7121 #define mmBIF_BX_DEV0_EPF0_VF21_MM_DATA_BASE_IDX                                                       0
7122 #define mmBIF_BX_DEV0_EPF0_VF21_MM_INDEX_HI                                                            0x0006
7123 #define mmBIF_BX_DEV0_EPF0_VF21_MM_INDEX_HI_BASE_IDX                                                   0
7124 
7125 
7126 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf21_BIFPFVFDEC1
7127 // base address: 0x0
7128 #define mmRCC_DEV0_EPF0_VF21_RCC_ERR_LOG                                                               0x0085
7129 #define mmRCC_DEV0_EPF0_VF21_RCC_ERR_LOG_BASE_IDX                                                      2
7130 #define mmRCC_DEV0_EPF0_VF21_RCC_DOORBELL_APER_EN                                                      0x00c0
7131 #define mmRCC_DEV0_EPF0_VF21_RCC_DOORBELL_APER_EN_BASE_IDX                                             2
7132 #define mmRCC_DEV0_EPF0_VF21_RCC_CONFIG_MEMSIZE                                                        0x00c3
7133 #define mmRCC_DEV0_EPF0_VF21_RCC_CONFIG_MEMSIZE_BASE_IDX                                               2
7134 #define mmRCC_DEV0_EPF0_VF21_RCC_CONFIG_RESERVED                                                       0x00c4
7135 #define mmRCC_DEV0_EPF0_VF21_RCC_CONFIG_RESERVED_BASE_IDX                                              2
7136 #define mmRCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER                                                   0x00c5
7137 #define mmRCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                          2
7138 
7139 
7140 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf21_BIFPFVFDEC1
7141 // base address: 0x0
7142 #define mmBIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS                                                         0x00eb
7143 #define mmBIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS_BASE_IDX                                                2
7144 #define mmBIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG                                                     0x00ec
7145 #define mmBIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG_BASE_IDX                                            2
7146 #define mmBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0x00f3
7147 #define mmBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                          2
7148 #define mmBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0x00f4
7149 #define mmBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                           2
7150 #define mmBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL                                        0x00f5
7151 #define mmBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                               2
7152 #define mmBIF_BX_DEV0_EPF0_VF21_HDP_REG_COHERENCY_FLUSH_CNTL                                           0x00f6
7153 #define mmBIF_BX_DEV0_EPF0_VF21_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
7154 #define mmBIF_BX_DEV0_EPF0_VF21_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0x00f7
7155 #define mmBIF_BX_DEV0_EPF0_VF21_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
7156 #define mmBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ                                                      0x0106
7157 #define mmBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ_BASE_IDX                                             2
7158 #define mmBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE                                                     0x0107
7159 #define mmBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE_BASE_IDX                                            2
7160 #define mmBIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING                                                      0x0108
7161 #define mmBIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING_BASE_IDX                                             2
7162 #define mmBIF_BX_DEV0_EPF0_VF21_NBIF_GFX_ADDR_LUT_BYPASS                                               0x0112
7163 #define mmBIF_BX_DEV0_EPF0_VF21_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                      2
7164 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW0                                                 0x0136
7165 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                        2
7166 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW1                                                 0x0137
7167 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                        2
7168 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW2                                                 0x0138
7169 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                        2
7170 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW3                                                 0x0139
7171 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                        2
7172 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW0                                                 0x013a
7173 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                        2
7174 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW1                                                 0x013b
7175 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                        2
7176 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW2                                                 0x013c
7177 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                        2
7178 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW3                                                 0x013d
7179 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                        2
7180 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL                                                        0x013e
7181 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL_BASE_IDX                                               2
7182 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL                                                       0x013f
7183 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL_BASE_IDX                                              2
7184 #define mmBIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX                                                       0x0140
7185 #define mmBIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX_BASE_IDX                                              2
7186 
7187 
7188 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf21_BIFDEC2
7189 // base address: 0x0
7190 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_LO                                                     0x0400
7191 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                            3
7192 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_HI                                                     0x0401
7193 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                            3
7194 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_MSG_DATA                                                    0x0402
7195 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                           3
7196 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_CONTROL                                                     0x0403
7197 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_CONTROL_BASE_IDX                                            3
7198 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_LO                                                     0x0404
7199 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                            3
7200 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_HI                                                     0x0405
7201 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                            3
7202 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_MSG_DATA                                                    0x0406
7203 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                           3
7204 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_CONTROL                                                     0x0407
7205 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_CONTROL_BASE_IDX                                            3
7206 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_LO                                                     0x0408
7207 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                            3
7208 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_HI                                                     0x0409
7209 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                            3
7210 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_MSG_DATA                                                    0x040a
7211 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                           3
7212 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_CONTROL                                                     0x040b
7213 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_CONTROL_BASE_IDX                                            3
7214 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_LO                                                     0x040c
7215 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                            3
7216 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_HI                                                     0x040d
7217 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                            3
7218 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_MSG_DATA                                                    0x040e
7219 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                           3
7220 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_CONTROL                                                     0x040f
7221 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_CONTROL_BASE_IDX                                            3
7222 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_PBA                                                               0x0800
7223 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_PBA_BASE_IDX                                                      3
7224 
7225 
7226 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf22_SYSPFVFDEC
7227 // base address: 0x0
7228 #define mmBIF_BX_DEV0_EPF0_VF22_MM_INDEX                                                               0x0000
7229 #define mmBIF_BX_DEV0_EPF0_VF22_MM_INDEX_BASE_IDX                                                      0
7230 #define mmBIF_BX_DEV0_EPF0_VF22_MM_DATA                                                                0x0001
7231 #define mmBIF_BX_DEV0_EPF0_VF22_MM_DATA_BASE_IDX                                                       0
7232 #define mmBIF_BX_DEV0_EPF0_VF22_MM_INDEX_HI                                                            0x0006
7233 #define mmBIF_BX_DEV0_EPF0_VF22_MM_INDEX_HI_BASE_IDX                                                   0
7234 
7235 
7236 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf22_BIFPFVFDEC1
7237 // base address: 0x0
7238 #define mmRCC_DEV0_EPF0_VF22_RCC_ERR_LOG                                                               0x0085
7239 #define mmRCC_DEV0_EPF0_VF22_RCC_ERR_LOG_BASE_IDX                                                      2
7240 #define mmRCC_DEV0_EPF0_VF22_RCC_DOORBELL_APER_EN                                                      0x00c0
7241 #define mmRCC_DEV0_EPF0_VF22_RCC_DOORBELL_APER_EN_BASE_IDX                                             2
7242 #define mmRCC_DEV0_EPF0_VF22_RCC_CONFIG_MEMSIZE                                                        0x00c3
7243 #define mmRCC_DEV0_EPF0_VF22_RCC_CONFIG_MEMSIZE_BASE_IDX                                               2
7244 #define mmRCC_DEV0_EPF0_VF22_RCC_CONFIG_RESERVED                                                       0x00c4
7245 #define mmRCC_DEV0_EPF0_VF22_RCC_CONFIG_RESERVED_BASE_IDX                                              2
7246 #define mmRCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER                                                   0x00c5
7247 #define mmRCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                          2
7248 
7249 
7250 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf22_BIFPFVFDEC1
7251 // base address: 0x0
7252 #define mmBIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS                                                         0x00eb
7253 #define mmBIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS_BASE_IDX                                                2
7254 #define mmBIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG                                                     0x00ec
7255 #define mmBIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG_BASE_IDX                                            2
7256 #define mmBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0x00f3
7257 #define mmBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                          2
7258 #define mmBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0x00f4
7259 #define mmBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                           2
7260 #define mmBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL                                        0x00f5
7261 #define mmBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                               2
7262 #define mmBIF_BX_DEV0_EPF0_VF22_HDP_REG_COHERENCY_FLUSH_CNTL                                           0x00f6
7263 #define mmBIF_BX_DEV0_EPF0_VF22_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
7264 #define mmBIF_BX_DEV0_EPF0_VF22_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0x00f7
7265 #define mmBIF_BX_DEV0_EPF0_VF22_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
7266 #define mmBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ                                                      0x0106
7267 #define mmBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ_BASE_IDX                                             2
7268 #define mmBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE                                                     0x0107
7269 #define mmBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE_BASE_IDX                                            2
7270 #define mmBIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING                                                      0x0108
7271 #define mmBIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING_BASE_IDX                                             2
7272 #define mmBIF_BX_DEV0_EPF0_VF22_NBIF_GFX_ADDR_LUT_BYPASS                                               0x0112
7273 #define mmBIF_BX_DEV0_EPF0_VF22_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                      2
7274 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW0                                                 0x0136
7275 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                        2
7276 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW1                                                 0x0137
7277 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                        2
7278 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW2                                                 0x0138
7279 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                        2
7280 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW3                                                 0x0139
7281 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                        2
7282 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW0                                                 0x013a
7283 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                        2
7284 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW1                                                 0x013b
7285 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                        2
7286 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW2                                                 0x013c
7287 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                        2
7288 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW3                                                 0x013d
7289 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                        2
7290 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL                                                        0x013e
7291 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL_BASE_IDX                                               2
7292 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL                                                       0x013f
7293 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL_BASE_IDX                                              2
7294 #define mmBIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX                                                       0x0140
7295 #define mmBIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX_BASE_IDX                                              2
7296 
7297 
7298 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf22_BIFDEC2
7299 // base address: 0x0
7300 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_LO                                                     0x0400
7301 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                            3
7302 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_HI                                                     0x0401
7303 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                            3
7304 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_MSG_DATA                                                    0x0402
7305 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                           3
7306 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_CONTROL                                                     0x0403
7307 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_CONTROL_BASE_IDX                                            3
7308 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_LO                                                     0x0404
7309 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                            3
7310 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_HI                                                     0x0405
7311 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                            3
7312 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_MSG_DATA                                                    0x0406
7313 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                           3
7314 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_CONTROL                                                     0x0407
7315 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_CONTROL_BASE_IDX                                            3
7316 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_LO                                                     0x0408
7317 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                            3
7318 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_HI                                                     0x0409
7319 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                            3
7320 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_MSG_DATA                                                    0x040a
7321 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                           3
7322 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_CONTROL                                                     0x040b
7323 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_CONTROL_BASE_IDX                                            3
7324 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_LO                                                     0x040c
7325 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                            3
7326 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_HI                                                     0x040d
7327 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                            3
7328 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_MSG_DATA                                                    0x040e
7329 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                           3
7330 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_CONTROL                                                     0x040f
7331 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_CONTROL_BASE_IDX                                            3
7332 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_PBA                                                               0x0800
7333 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_PBA_BASE_IDX                                                      3
7334 
7335 
7336 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf23_SYSPFVFDEC
7337 // base address: 0x0
7338 #define mmBIF_BX_DEV0_EPF0_VF23_MM_INDEX                                                               0x0000
7339 #define mmBIF_BX_DEV0_EPF0_VF23_MM_INDEX_BASE_IDX                                                      0
7340 #define mmBIF_BX_DEV0_EPF0_VF23_MM_DATA                                                                0x0001
7341 #define mmBIF_BX_DEV0_EPF0_VF23_MM_DATA_BASE_IDX                                                       0
7342 #define mmBIF_BX_DEV0_EPF0_VF23_MM_INDEX_HI                                                            0x0006
7343 #define mmBIF_BX_DEV0_EPF0_VF23_MM_INDEX_HI_BASE_IDX                                                   0
7344 
7345 
7346 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf23_BIFPFVFDEC1
7347 // base address: 0x0
7348 #define mmRCC_DEV0_EPF0_VF23_RCC_ERR_LOG                                                               0x0085
7349 #define mmRCC_DEV0_EPF0_VF23_RCC_ERR_LOG_BASE_IDX                                                      2
7350 #define mmRCC_DEV0_EPF0_VF23_RCC_DOORBELL_APER_EN                                                      0x00c0
7351 #define mmRCC_DEV0_EPF0_VF23_RCC_DOORBELL_APER_EN_BASE_IDX                                             2
7352 #define mmRCC_DEV0_EPF0_VF23_RCC_CONFIG_MEMSIZE                                                        0x00c3
7353 #define mmRCC_DEV0_EPF0_VF23_RCC_CONFIG_MEMSIZE_BASE_IDX                                               2
7354 #define mmRCC_DEV0_EPF0_VF23_RCC_CONFIG_RESERVED                                                       0x00c4
7355 #define mmRCC_DEV0_EPF0_VF23_RCC_CONFIG_RESERVED_BASE_IDX                                              2
7356 #define mmRCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER                                                   0x00c5
7357 #define mmRCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                          2
7358 
7359 
7360 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf23_BIFPFVFDEC1
7361 // base address: 0x0
7362 #define mmBIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS                                                         0x00eb
7363 #define mmBIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS_BASE_IDX                                                2
7364 #define mmBIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG                                                     0x00ec
7365 #define mmBIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG_BASE_IDX                                            2
7366 #define mmBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0x00f3
7367 #define mmBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                          2
7368 #define mmBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0x00f4
7369 #define mmBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                           2
7370 #define mmBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL                                        0x00f5
7371 #define mmBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                               2
7372 #define mmBIF_BX_DEV0_EPF0_VF23_HDP_REG_COHERENCY_FLUSH_CNTL                                           0x00f6
7373 #define mmBIF_BX_DEV0_EPF0_VF23_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
7374 #define mmBIF_BX_DEV0_EPF0_VF23_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0x00f7
7375 #define mmBIF_BX_DEV0_EPF0_VF23_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
7376 #define mmBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ                                                      0x0106
7377 #define mmBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ_BASE_IDX                                             2
7378 #define mmBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE                                                     0x0107
7379 #define mmBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE_BASE_IDX                                            2
7380 #define mmBIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING                                                      0x0108
7381 #define mmBIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING_BASE_IDX                                             2
7382 #define mmBIF_BX_DEV0_EPF0_VF23_NBIF_GFX_ADDR_LUT_BYPASS                                               0x0112
7383 #define mmBIF_BX_DEV0_EPF0_VF23_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                      2
7384 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW0                                                 0x0136
7385 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                        2
7386 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW1                                                 0x0137
7387 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                        2
7388 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW2                                                 0x0138
7389 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                        2
7390 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW3                                                 0x0139
7391 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                        2
7392 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW0                                                 0x013a
7393 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                        2
7394 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW1                                                 0x013b
7395 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                        2
7396 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW2                                                 0x013c
7397 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                        2
7398 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW3                                                 0x013d
7399 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                        2
7400 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL                                                        0x013e
7401 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL_BASE_IDX                                               2
7402 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL                                                       0x013f
7403 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL_BASE_IDX                                              2
7404 #define mmBIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX                                                       0x0140
7405 #define mmBIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX_BASE_IDX                                              2
7406 
7407 
7408 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf23_BIFDEC2
7409 // base address: 0x0
7410 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_LO                                                     0x0400
7411 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                            3
7412 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_HI                                                     0x0401
7413 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                            3
7414 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_MSG_DATA                                                    0x0402
7415 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                           3
7416 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_CONTROL                                                     0x0403
7417 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_CONTROL_BASE_IDX                                            3
7418 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_LO                                                     0x0404
7419 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                            3
7420 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_HI                                                     0x0405
7421 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                            3
7422 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_MSG_DATA                                                    0x0406
7423 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                           3
7424 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_CONTROL                                                     0x0407
7425 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_CONTROL_BASE_IDX                                            3
7426 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_LO                                                     0x0408
7427 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                            3
7428 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_HI                                                     0x0409
7429 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                            3
7430 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_MSG_DATA                                                    0x040a
7431 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                           3
7432 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_CONTROL                                                     0x040b
7433 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_CONTROL_BASE_IDX                                            3
7434 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_LO                                                     0x040c
7435 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                            3
7436 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_HI                                                     0x040d
7437 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                            3
7438 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_MSG_DATA                                                    0x040e
7439 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                           3
7440 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_CONTROL                                                     0x040f
7441 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_CONTROL_BASE_IDX                                            3
7442 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_PBA                                                               0x0800
7443 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_PBA_BASE_IDX                                                      3
7444 
7445 
7446 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf24_SYSPFVFDEC
7447 // base address: 0x0
7448 #define mmBIF_BX_DEV0_EPF0_VF24_MM_INDEX                                                               0x0000
7449 #define mmBIF_BX_DEV0_EPF0_VF24_MM_INDEX_BASE_IDX                                                      0
7450 #define mmBIF_BX_DEV0_EPF0_VF24_MM_DATA                                                                0x0001
7451 #define mmBIF_BX_DEV0_EPF0_VF24_MM_DATA_BASE_IDX                                                       0
7452 #define mmBIF_BX_DEV0_EPF0_VF24_MM_INDEX_HI                                                            0x0006
7453 #define mmBIF_BX_DEV0_EPF0_VF24_MM_INDEX_HI_BASE_IDX                                                   0
7454 
7455 
7456 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf24_BIFPFVFDEC1
7457 // base address: 0x0
7458 #define mmRCC_DEV0_EPF0_VF24_RCC_ERR_LOG                                                               0x0085
7459 #define mmRCC_DEV0_EPF0_VF24_RCC_ERR_LOG_BASE_IDX                                                      2
7460 #define mmRCC_DEV0_EPF0_VF24_RCC_DOORBELL_APER_EN                                                      0x00c0
7461 #define mmRCC_DEV0_EPF0_VF24_RCC_DOORBELL_APER_EN_BASE_IDX                                             2
7462 #define mmRCC_DEV0_EPF0_VF24_RCC_CONFIG_MEMSIZE                                                        0x00c3
7463 #define mmRCC_DEV0_EPF0_VF24_RCC_CONFIG_MEMSIZE_BASE_IDX                                               2
7464 #define mmRCC_DEV0_EPF0_VF24_RCC_CONFIG_RESERVED                                                       0x00c4
7465 #define mmRCC_DEV0_EPF0_VF24_RCC_CONFIG_RESERVED_BASE_IDX                                              2
7466 #define mmRCC_DEV0_EPF0_VF24_RCC_IOV_FUNC_IDENTIFIER                                                   0x00c5
7467 #define mmRCC_DEV0_EPF0_VF24_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                          2
7468 
7469 
7470 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf24_BIFPFVFDEC1
7471 // base address: 0x0
7472 #define mmBIF_BX_DEV0_EPF0_VF24_BIF_BME_STATUS                                                         0x00eb
7473 #define mmBIF_BX_DEV0_EPF0_VF24_BIF_BME_STATUS_BASE_IDX                                                2
7474 #define mmBIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG                                                     0x00ec
7475 #define mmBIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG_BASE_IDX                                            2
7476 #define mmBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0x00f3
7477 #define mmBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                          2
7478 #define mmBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0x00f4
7479 #define mmBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                           2
7480 #define mmBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_CNTL                                        0x00f5
7481 #define mmBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                               2
7482 #define mmBIF_BX_DEV0_EPF0_VF24_HDP_REG_COHERENCY_FLUSH_CNTL                                           0x00f6
7483 #define mmBIF_BX_DEV0_EPF0_VF24_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
7484 #define mmBIF_BX_DEV0_EPF0_VF24_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0x00f7
7485 #define mmBIF_BX_DEV0_EPF0_VF24_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
7486 #define mmBIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ                                                      0x0106
7487 #define mmBIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ_BASE_IDX                                             2
7488 #define mmBIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE                                                     0x0107
7489 #define mmBIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE_BASE_IDX                                            2
7490 #define mmBIF_BX_DEV0_EPF0_VF24_BIF_TRANS_PENDING                                                      0x0108
7491 #define mmBIF_BX_DEV0_EPF0_VF24_BIF_TRANS_PENDING_BASE_IDX                                             2
7492 #define mmBIF_BX_DEV0_EPF0_VF24_NBIF_GFX_ADDR_LUT_BYPASS                                               0x0112
7493 #define mmBIF_BX_DEV0_EPF0_VF24_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                      2
7494 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW0                                                 0x0136
7495 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                        2
7496 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW1                                                 0x0137
7497 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                        2
7498 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW2                                                 0x0138
7499 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                        2
7500 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW3                                                 0x0139
7501 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                        2
7502 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW0                                                 0x013a
7503 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                        2
7504 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW1                                                 0x013b
7505 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                        2
7506 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW2                                                 0x013c
7507 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                        2
7508 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW3                                                 0x013d
7509 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                        2
7510 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL                                                        0x013e
7511 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL_BASE_IDX                                               2
7512 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_INT_CNTL                                                       0x013f
7513 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_INT_CNTL_BASE_IDX                                              2
7514 #define mmBIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX                                                       0x0140
7515 #define mmBIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX_BASE_IDX                                              2
7516 
7517 
7518 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf24_BIFDEC2
7519 // base address: 0x0
7520 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_LO                                                     0x0400
7521 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                            3
7522 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_HI                                                     0x0401
7523 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                            3
7524 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_MSG_DATA                                                    0x0402
7525 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                           3
7526 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_CONTROL                                                     0x0403
7527 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_CONTROL_BASE_IDX                                            3
7528 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_LO                                                     0x0404
7529 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                            3
7530 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_HI                                                     0x0405
7531 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                            3
7532 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_MSG_DATA                                                    0x0406
7533 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                           3
7534 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_CONTROL                                                     0x0407
7535 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_CONTROL_BASE_IDX                                            3
7536 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_LO                                                     0x0408
7537 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                            3
7538 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_HI                                                     0x0409
7539 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                            3
7540 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_MSG_DATA                                                    0x040a
7541 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                           3
7542 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_CONTROL                                                     0x040b
7543 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_CONTROL_BASE_IDX                                            3
7544 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_LO                                                     0x040c
7545 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                            3
7546 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_HI                                                     0x040d
7547 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                            3
7548 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_MSG_DATA                                                    0x040e
7549 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                           3
7550 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_CONTROL                                                     0x040f
7551 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_CONTROL_BASE_IDX                                            3
7552 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_PBA                                                               0x0800
7553 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_PBA_BASE_IDX                                                      3
7554 
7555 
7556 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf25_SYSPFVFDEC
7557 // base address: 0x0
7558 #define mmBIF_BX_DEV0_EPF0_VF25_MM_INDEX                                                               0x0000
7559 #define mmBIF_BX_DEV0_EPF0_VF25_MM_INDEX_BASE_IDX                                                      0
7560 #define mmBIF_BX_DEV0_EPF0_VF25_MM_DATA                                                                0x0001
7561 #define mmBIF_BX_DEV0_EPF0_VF25_MM_DATA_BASE_IDX                                                       0
7562 #define mmBIF_BX_DEV0_EPF0_VF25_MM_INDEX_HI                                                            0x0006
7563 #define mmBIF_BX_DEV0_EPF0_VF25_MM_INDEX_HI_BASE_IDX                                                   0
7564 
7565 
7566 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf25_BIFPFVFDEC1
7567 // base address: 0x0
7568 #define mmRCC_DEV0_EPF0_VF25_RCC_ERR_LOG                                                               0x0085
7569 #define mmRCC_DEV0_EPF0_VF25_RCC_ERR_LOG_BASE_IDX                                                      2
7570 #define mmRCC_DEV0_EPF0_VF25_RCC_DOORBELL_APER_EN                                                      0x00c0
7571 #define mmRCC_DEV0_EPF0_VF25_RCC_DOORBELL_APER_EN_BASE_IDX                                             2
7572 #define mmRCC_DEV0_EPF0_VF25_RCC_CONFIG_MEMSIZE                                                        0x00c3
7573 #define mmRCC_DEV0_EPF0_VF25_RCC_CONFIG_MEMSIZE_BASE_IDX                                               2
7574 #define mmRCC_DEV0_EPF0_VF25_RCC_CONFIG_RESERVED                                                       0x00c4
7575 #define mmRCC_DEV0_EPF0_VF25_RCC_CONFIG_RESERVED_BASE_IDX                                              2
7576 #define mmRCC_DEV0_EPF0_VF25_RCC_IOV_FUNC_IDENTIFIER                                                   0x00c5
7577 #define mmRCC_DEV0_EPF0_VF25_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                          2
7578 
7579 
7580 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf25_BIFPFVFDEC1
7581 // base address: 0x0
7582 #define mmBIF_BX_DEV0_EPF0_VF25_BIF_BME_STATUS                                                         0x00eb
7583 #define mmBIF_BX_DEV0_EPF0_VF25_BIF_BME_STATUS_BASE_IDX                                                2
7584 #define mmBIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG                                                     0x00ec
7585 #define mmBIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG_BASE_IDX                                            2
7586 #define mmBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0x00f3
7587 #define mmBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                          2
7588 #define mmBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0x00f4
7589 #define mmBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                           2
7590 #define mmBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_CNTL                                        0x00f5
7591 #define mmBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                               2
7592 #define mmBIF_BX_DEV0_EPF0_VF25_HDP_REG_COHERENCY_FLUSH_CNTL                                           0x00f6
7593 #define mmBIF_BX_DEV0_EPF0_VF25_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
7594 #define mmBIF_BX_DEV0_EPF0_VF25_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0x00f7
7595 #define mmBIF_BX_DEV0_EPF0_VF25_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
7596 #define mmBIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ                                                      0x0106
7597 #define mmBIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ_BASE_IDX                                             2
7598 #define mmBIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE                                                     0x0107
7599 #define mmBIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE_BASE_IDX                                            2
7600 #define mmBIF_BX_DEV0_EPF0_VF25_BIF_TRANS_PENDING                                                      0x0108
7601 #define mmBIF_BX_DEV0_EPF0_VF25_BIF_TRANS_PENDING_BASE_IDX                                             2
7602 #define mmBIF_BX_DEV0_EPF0_VF25_NBIF_GFX_ADDR_LUT_BYPASS                                               0x0112
7603 #define mmBIF_BX_DEV0_EPF0_VF25_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                      2
7604 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW0                                                 0x0136
7605 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                        2
7606 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW1                                                 0x0137
7607 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                        2
7608 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW2                                                 0x0138
7609 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                        2
7610 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW3                                                 0x0139
7611 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                        2
7612 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW0                                                 0x013a
7613 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                        2
7614 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW1                                                 0x013b
7615 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                        2
7616 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW2                                                 0x013c
7617 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                        2
7618 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW3                                                 0x013d
7619 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                        2
7620 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL                                                        0x013e
7621 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL_BASE_IDX                                               2
7622 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_INT_CNTL                                                       0x013f
7623 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_INT_CNTL_BASE_IDX                                              2
7624 #define mmBIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX                                                       0x0140
7625 #define mmBIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX_BASE_IDX                                              2
7626 
7627 
7628 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf25_BIFDEC2
7629 // base address: 0x0
7630 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_LO                                                     0x0400
7631 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                            3
7632 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_HI                                                     0x0401
7633 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                            3
7634 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_MSG_DATA                                                    0x0402
7635 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                           3
7636 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_CONTROL                                                     0x0403
7637 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_CONTROL_BASE_IDX                                            3
7638 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_LO                                                     0x0404
7639 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                            3
7640 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_HI                                                     0x0405
7641 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                            3
7642 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_MSG_DATA                                                    0x0406
7643 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                           3
7644 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_CONTROL                                                     0x0407
7645 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_CONTROL_BASE_IDX                                            3
7646 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_LO                                                     0x0408
7647 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                            3
7648 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_HI                                                     0x0409
7649 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                            3
7650 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_MSG_DATA                                                    0x040a
7651 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                           3
7652 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_CONTROL                                                     0x040b
7653 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_CONTROL_BASE_IDX                                            3
7654 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_LO                                                     0x040c
7655 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                            3
7656 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_HI                                                     0x040d
7657 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                            3
7658 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_MSG_DATA                                                    0x040e
7659 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                           3
7660 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_CONTROL                                                     0x040f
7661 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_CONTROL_BASE_IDX                                            3
7662 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_PBA                                                               0x0800
7663 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_PBA_BASE_IDX                                                      3
7664 
7665 
7666 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf26_SYSPFVFDEC
7667 // base address: 0x0
7668 #define mmBIF_BX_DEV0_EPF0_VF26_MM_INDEX                                                               0x0000
7669 #define mmBIF_BX_DEV0_EPF0_VF26_MM_INDEX_BASE_IDX                                                      0
7670 #define mmBIF_BX_DEV0_EPF0_VF26_MM_DATA                                                                0x0001
7671 #define mmBIF_BX_DEV0_EPF0_VF26_MM_DATA_BASE_IDX                                                       0
7672 #define mmBIF_BX_DEV0_EPF0_VF26_MM_INDEX_HI                                                            0x0006
7673 #define mmBIF_BX_DEV0_EPF0_VF26_MM_INDEX_HI_BASE_IDX                                                   0
7674 
7675 
7676 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf26_BIFPFVFDEC1
7677 // base address: 0x0
7678 #define mmRCC_DEV0_EPF0_VF26_RCC_ERR_LOG                                                               0x0085
7679 #define mmRCC_DEV0_EPF0_VF26_RCC_ERR_LOG_BASE_IDX                                                      2
7680 #define mmRCC_DEV0_EPF0_VF26_RCC_DOORBELL_APER_EN                                                      0x00c0
7681 #define mmRCC_DEV0_EPF0_VF26_RCC_DOORBELL_APER_EN_BASE_IDX                                             2
7682 #define mmRCC_DEV0_EPF0_VF26_RCC_CONFIG_MEMSIZE                                                        0x00c3
7683 #define mmRCC_DEV0_EPF0_VF26_RCC_CONFIG_MEMSIZE_BASE_IDX                                               2
7684 #define mmRCC_DEV0_EPF0_VF26_RCC_CONFIG_RESERVED                                                       0x00c4
7685 #define mmRCC_DEV0_EPF0_VF26_RCC_CONFIG_RESERVED_BASE_IDX                                              2
7686 #define mmRCC_DEV0_EPF0_VF26_RCC_IOV_FUNC_IDENTIFIER                                                   0x00c5
7687 #define mmRCC_DEV0_EPF0_VF26_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                          2
7688 
7689 
7690 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf26_BIFPFVFDEC1
7691 // base address: 0x0
7692 #define mmBIF_BX_DEV0_EPF0_VF26_BIF_BME_STATUS                                                         0x00eb
7693 #define mmBIF_BX_DEV0_EPF0_VF26_BIF_BME_STATUS_BASE_IDX                                                2
7694 #define mmBIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG                                                     0x00ec
7695 #define mmBIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG_BASE_IDX                                            2
7696 #define mmBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0x00f3
7697 #define mmBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                          2
7698 #define mmBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0x00f4
7699 #define mmBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                           2
7700 #define mmBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_CNTL                                        0x00f5
7701 #define mmBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                               2
7702 #define mmBIF_BX_DEV0_EPF0_VF26_HDP_REG_COHERENCY_FLUSH_CNTL                                           0x00f6
7703 #define mmBIF_BX_DEV0_EPF0_VF26_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
7704 #define mmBIF_BX_DEV0_EPF0_VF26_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0x00f7
7705 #define mmBIF_BX_DEV0_EPF0_VF26_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
7706 #define mmBIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ                                                      0x0106
7707 #define mmBIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ_BASE_IDX                                             2
7708 #define mmBIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE                                                     0x0107
7709 #define mmBIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE_BASE_IDX                                            2
7710 #define mmBIF_BX_DEV0_EPF0_VF26_BIF_TRANS_PENDING                                                      0x0108
7711 #define mmBIF_BX_DEV0_EPF0_VF26_BIF_TRANS_PENDING_BASE_IDX                                             2
7712 #define mmBIF_BX_DEV0_EPF0_VF26_NBIF_GFX_ADDR_LUT_BYPASS                                               0x0112
7713 #define mmBIF_BX_DEV0_EPF0_VF26_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                      2
7714 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW0                                                 0x0136
7715 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                        2
7716 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW1                                                 0x0137
7717 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                        2
7718 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW2                                                 0x0138
7719 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                        2
7720 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW3                                                 0x0139
7721 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                        2
7722 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW0                                                 0x013a
7723 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                        2
7724 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW1                                                 0x013b
7725 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                        2
7726 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW2                                                 0x013c
7727 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                        2
7728 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW3                                                 0x013d
7729 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                        2
7730 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL                                                        0x013e
7731 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL_BASE_IDX                                               2
7732 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_INT_CNTL                                                       0x013f
7733 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_INT_CNTL_BASE_IDX                                              2
7734 #define mmBIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX                                                       0x0140
7735 #define mmBIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX_BASE_IDX                                              2
7736 
7737 
7738 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf26_BIFDEC2
7739 // base address: 0x0
7740 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_LO                                                     0x0400
7741 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                            3
7742 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_HI                                                     0x0401
7743 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                            3
7744 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_MSG_DATA                                                    0x0402
7745 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                           3
7746 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_CONTROL                                                     0x0403
7747 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_CONTROL_BASE_IDX                                            3
7748 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_LO                                                     0x0404
7749 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                            3
7750 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_HI                                                     0x0405
7751 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                            3
7752 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_MSG_DATA                                                    0x0406
7753 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                           3
7754 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_CONTROL                                                     0x0407
7755 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_CONTROL_BASE_IDX                                            3
7756 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_LO                                                     0x0408
7757 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                            3
7758 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_HI                                                     0x0409
7759 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                            3
7760 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_MSG_DATA                                                    0x040a
7761 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                           3
7762 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_CONTROL                                                     0x040b
7763 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_CONTROL_BASE_IDX                                            3
7764 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_LO                                                     0x040c
7765 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                            3
7766 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_HI                                                     0x040d
7767 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                            3
7768 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_MSG_DATA                                                    0x040e
7769 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                           3
7770 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_CONTROL                                                     0x040f
7771 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_CONTROL_BASE_IDX                                            3
7772 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_PBA                                                               0x0800
7773 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_PBA_BASE_IDX                                                      3
7774 
7775 
7776 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf27_SYSPFVFDEC
7777 // base address: 0x0
7778 #define mmBIF_BX_DEV0_EPF0_VF27_MM_INDEX                                                               0x0000
7779 #define mmBIF_BX_DEV0_EPF0_VF27_MM_INDEX_BASE_IDX                                                      0
7780 #define mmBIF_BX_DEV0_EPF0_VF27_MM_DATA                                                                0x0001
7781 #define mmBIF_BX_DEV0_EPF0_VF27_MM_DATA_BASE_IDX                                                       0
7782 #define mmBIF_BX_DEV0_EPF0_VF27_MM_INDEX_HI                                                            0x0006
7783 #define mmBIF_BX_DEV0_EPF0_VF27_MM_INDEX_HI_BASE_IDX                                                   0
7784 
7785 
7786 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf27_BIFPFVFDEC1
7787 // base address: 0x0
7788 #define mmRCC_DEV0_EPF0_VF27_RCC_ERR_LOG                                                               0x0085
7789 #define mmRCC_DEV0_EPF0_VF27_RCC_ERR_LOG_BASE_IDX                                                      2
7790 #define mmRCC_DEV0_EPF0_VF27_RCC_DOORBELL_APER_EN                                                      0x00c0
7791 #define mmRCC_DEV0_EPF0_VF27_RCC_DOORBELL_APER_EN_BASE_IDX                                             2
7792 #define mmRCC_DEV0_EPF0_VF27_RCC_CONFIG_MEMSIZE                                                        0x00c3
7793 #define mmRCC_DEV0_EPF0_VF27_RCC_CONFIG_MEMSIZE_BASE_IDX                                               2
7794 #define mmRCC_DEV0_EPF0_VF27_RCC_CONFIG_RESERVED                                                       0x00c4
7795 #define mmRCC_DEV0_EPF0_VF27_RCC_CONFIG_RESERVED_BASE_IDX                                              2
7796 #define mmRCC_DEV0_EPF0_VF27_RCC_IOV_FUNC_IDENTIFIER                                                   0x00c5
7797 #define mmRCC_DEV0_EPF0_VF27_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                          2
7798 
7799 
7800 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf27_BIFPFVFDEC1
7801 // base address: 0x0
7802 #define mmBIF_BX_DEV0_EPF0_VF27_BIF_BME_STATUS                                                         0x00eb
7803 #define mmBIF_BX_DEV0_EPF0_VF27_BIF_BME_STATUS_BASE_IDX                                                2
7804 #define mmBIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG                                                     0x00ec
7805 #define mmBIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG_BASE_IDX                                            2
7806 #define mmBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0x00f3
7807 #define mmBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                          2
7808 #define mmBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0x00f4
7809 #define mmBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                           2
7810 #define mmBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_CNTL                                        0x00f5
7811 #define mmBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                               2
7812 #define mmBIF_BX_DEV0_EPF0_VF27_HDP_REG_COHERENCY_FLUSH_CNTL                                           0x00f6
7813 #define mmBIF_BX_DEV0_EPF0_VF27_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
7814 #define mmBIF_BX_DEV0_EPF0_VF27_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0x00f7
7815 #define mmBIF_BX_DEV0_EPF0_VF27_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
7816 #define mmBIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ                                                      0x0106
7817 #define mmBIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ_BASE_IDX                                             2
7818 #define mmBIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE                                                     0x0107
7819 #define mmBIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE_BASE_IDX                                            2
7820 #define mmBIF_BX_DEV0_EPF0_VF27_BIF_TRANS_PENDING                                                      0x0108
7821 #define mmBIF_BX_DEV0_EPF0_VF27_BIF_TRANS_PENDING_BASE_IDX                                             2
7822 #define mmBIF_BX_DEV0_EPF0_VF27_NBIF_GFX_ADDR_LUT_BYPASS                                               0x0112
7823 #define mmBIF_BX_DEV0_EPF0_VF27_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                      2
7824 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW0                                                 0x0136
7825 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                        2
7826 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW1                                                 0x0137
7827 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                        2
7828 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW2                                                 0x0138
7829 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                        2
7830 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW3                                                 0x0139
7831 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                        2
7832 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW0                                                 0x013a
7833 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                        2
7834 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW1                                                 0x013b
7835 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                        2
7836 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW2                                                 0x013c
7837 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                        2
7838 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW3                                                 0x013d
7839 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                        2
7840 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL                                                        0x013e
7841 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL_BASE_IDX                                               2
7842 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_INT_CNTL                                                       0x013f
7843 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_INT_CNTL_BASE_IDX                                              2
7844 #define mmBIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX                                                       0x0140
7845 #define mmBIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX_BASE_IDX                                              2
7846 
7847 
7848 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf27_BIFDEC2
7849 // base address: 0x0
7850 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_LO                                                     0x0400
7851 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                            3
7852 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_HI                                                     0x0401
7853 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                            3
7854 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_MSG_DATA                                                    0x0402
7855 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                           3
7856 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_CONTROL                                                     0x0403
7857 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_CONTROL_BASE_IDX                                            3
7858 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_LO                                                     0x0404
7859 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                            3
7860 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_HI                                                     0x0405
7861 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                            3
7862 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_MSG_DATA                                                    0x0406
7863 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                           3
7864 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_CONTROL                                                     0x0407
7865 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_CONTROL_BASE_IDX                                            3
7866 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_LO                                                     0x0408
7867 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                            3
7868 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_HI                                                     0x0409
7869 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                            3
7870 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_MSG_DATA                                                    0x040a
7871 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                           3
7872 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_CONTROL                                                     0x040b
7873 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_CONTROL_BASE_IDX                                            3
7874 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_LO                                                     0x040c
7875 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                            3
7876 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_HI                                                     0x040d
7877 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                            3
7878 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_MSG_DATA                                                    0x040e
7879 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                           3
7880 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_CONTROL                                                     0x040f
7881 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_CONTROL_BASE_IDX                                            3
7882 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_PBA                                                               0x0800
7883 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_PBA_BASE_IDX                                                      3
7884 
7885 
7886 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf28_SYSPFVFDEC
7887 // base address: 0x0
7888 #define mmBIF_BX_DEV0_EPF0_VF28_MM_INDEX                                                               0x0000
7889 #define mmBIF_BX_DEV0_EPF0_VF28_MM_INDEX_BASE_IDX                                                      0
7890 #define mmBIF_BX_DEV0_EPF0_VF28_MM_DATA                                                                0x0001
7891 #define mmBIF_BX_DEV0_EPF0_VF28_MM_DATA_BASE_IDX                                                       0
7892 #define mmBIF_BX_DEV0_EPF0_VF28_MM_INDEX_HI                                                            0x0006
7893 #define mmBIF_BX_DEV0_EPF0_VF28_MM_INDEX_HI_BASE_IDX                                                   0
7894 
7895 
7896 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf28_BIFPFVFDEC1
7897 // base address: 0x0
7898 #define mmRCC_DEV0_EPF0_VF28_RCC_ERR_LOG                                                               0x0085
7899 #define mmRCC_DEV0_EPF0_VF28_RCC_ERR_LOG_BASE_IDX                                                      2
7900 #define mmRCC_DEV0_EPF0_VF28_RCC_DOORBELL_APER_EN                                                      0x00c0
7901 #define mmRCC_DEV0_EPF0_VF28_RCC_DOORBELL_APER_EN_BASE_IDX                                             2
7902 #define mmRCC_DEV0_EPF0_VF28_RCC_CONFIG_MEMSIZE                                                        0x00c3
7903 #define mmRCC_DEV0_EPF0_VF28_RCC_CONFIG_MEMSIZE_BASE_IDX                                               2
7904 #define mmRCC_DEV0_EPF0_VF28_RCC_CONFIG_RESERVED                                                       0x00c4
7905 #define mmRCC_DEV0_EPF0_VF28_RCC_CONFIG_RESERVED_BASE_IDX                                              2
7906 #define mmRCC_DEV0_EPF0_VF28_RCC_IOV_FUNC_IDENTIFIER                                                   0x00c5
7907 #define mmRCC_DEV0_EPF0_VF28_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                          2
7908 
7909 
7910 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf28_BIFPFVFDEC1
7911 // base address: 0x0
7912 #define mmBIF_BX_DEV0_EPF0_VF28_BIF_BME_STATUS                                                         0x00eb
7913 #define mmBIF_BX_DEV0_EPF0_VF28_BIF_BME_STATUS_BASE_IDX                                                2
7914 #define mmBIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG                                                     0x00ec
7915 #define mmBIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG_BASE_IDX                                            2
7916 #define mmBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0x00f3
7917 #define mmBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                          2
7918 #define mmBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0x00f4
7919 #define mmBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                           2
7920 #define mmBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_CNTL                                        0x00f5
7921 #define mmBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                               2
7922 #define mmBIF_BX_DEV0_EPF0_VF28_HDP_REG_COHERENCY_FLUSH_CNTL                                           0x00f6
7923 #define mmBIF_BX_DEV0_EPF0_VF28_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
7924 #define mmBIF_BX_DEV0_EPF0_VF28_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0x00f7
7925 #define mmBIF_BX_DEV0_EPF0_VF28_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
7926 #define mmBIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ                                                      0x0106
7927 #define mmBIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ_BASE_IDX                                             2
7928 #define mmBIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE                                                     0x0107
7929 #define mmBIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE_BASE_IDX                                            2
7930 #define mmBIF_BX_DEV0_EPF0_VF28_BIF_TRANS_PENDING                                                      0x0108
7931 #define mmBIF_BX_DEV0_EPF0_VF28_BIF_TRANS_PENDING_BASE_IDX                                             2
7932 #define mmBIF_BX_DEV0_EPF0_VF28_NBIF_GFX_ADDR_LUT_BYPASS                                               0x0112
7933 #define mmBIF_BX_DEV0_EPF0_VF28_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                      2
7934 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW0                                                 0x0136
7935 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                        2
7936 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW1                                                 0x0137
7937 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                        2
7938 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW2                                                 0x0138
7939 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                        2
7940 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW3                                                 0x0139
7941 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                        2
7942 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW0                                                 0x013a
7943 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                        2
7944 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW1                                                 0x013b
7945 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                        2
7946 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW2                                                 0x013c
7947 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                        2
7948 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW3                                                 0x013d
7949 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                        2
7950 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL                                                        0x013e
7951 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL_BASE_IDX                                               2
7952 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_INT_CNTL                                                       0x013f
7953 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_INT_CNTL_BASE_IDX                                              2
7954 #define mmBIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX                                                       0x0140
7955 #define mmBIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX_BASE_IDX                                              2
7956 
7957 
7958 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf28_BIFDEC2
7959 // base address: 0x0
7960 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_LO                                                     0x0400
7961 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                            3
7962 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_HI                                                     0x0401
7963 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                            3
7964 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_MSG_DATA                                                    0x0402
7965 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                           3
7966 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_CONTROL                                                     0x0403
7967 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_CONTROL_BASE_IDX                                            3
7968 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_LO                                                     0x0404
7969 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                            3
7970 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_HI                                                     0x0405
7971 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                            3
7972 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_MSG_DATA                                                    0x0406
7973 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                           3
7974 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_CONTROL                                                     0x0407
7975 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_CONTROL_BASE_IDX                                            3
7976 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_LO                                                     0x0408
7977 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                            3
7978 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_HI                                                     0x0409
7979 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                            3
7980 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_MSG_DATA                                                    0x040a
7981 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                           3
7982 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_CONTROL                                                     0x040b
7983 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_CONTROL_BASE_IDX                                            3
7984 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_LO                                                     0x040c
7985 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                            3
7986 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_HI                                                     0x040d
7987 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                            3
7988 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_MSG_DATA                                                    0x040e
7989 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                           3
7990 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_CONTROL                                                     0x040f
7991 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_CONTROL_BASE_IDX                                            3
7992 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_PBA                                                               0x0800
7993 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_PBA_BASE_IDX                                                      3
7994 
7995 
7996 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf29_SYSPFVFDEC
7997 // base address: 0x0
7998 #define mmBIF_BX_DEV0_EPF0_VF29_MM_INDEX                                                               0x0000
7999 #define mmBIF_BX_DEV0_EPF0_VF29_MM_INDEX_BASE_IDX                                                      0
8000 #define mmBIF_BX_DEV0_EPF0_VF29_MM_DATA                                                                0x0001
8001 #define mmBIF_BX_DEV0_EPF0_VF29_MM_DATA_BASE_IDX                                                       0
8002 #define mmBIF_BX_DEV0_EPF0_VF29_MM_INDEX_HI                                                            0x0006
8003 #define mmBIF_BX_DEV0_EPF0_VF29_MM_INDEX_HI_BASE_IDX                                                   0
8004 
8005 
8006 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf29_BIFPFVFDEC1
8007 // base address: 0x0
8008 #define mmRCC_DEV0_EPF0_VF29_RCC_ERR_LOG                                                               0x0085
8009 #define mmRCC_DEV0_EPF0_VF29_RCC_ERR_LOG_BASE_IDX                                                      2
8010 #define mmRCC_DEV0_EPF0_VF29_RCC_DOORBELL_APER_EN                                                      0x00c0
8011 #define mmRCC_DEV0_EPF0_VF29_RCC_DOORBELL_APER_EN_BASE_IDX                                             2
8012 #define mmRCC_DEV0_EPF0_VF29_RCC_CONFIG_MEMSIZE                                                        0x00c3
8013 #define mmRCC_DEV0_EPF0_VF29_RCC_CONFIG_MEMSIZE_BASE_IDX                                               2
8014 #define mmRCC_DEV0_EPF0_VF29_RCC_CONFIG_RESERVED                                                       0x00c4
8015 #define mmRCC_DEV0_EPF0_VF29_RCC_CONFIG_RESERVED_BASE_IDX                                              2
8016 #define mmRCC_DEV0_EPF0_VF29_RCC_IOV_FUNC_IDENTIFIER                                                   0x00c5
8017 #define mmRCC_DEV0_EPF0_VF29_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                          2
8018 
8019 
8020 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf29_BIFPFVFDEC1
8021 // base address: 0x0
8022 #define mmBIF_BX_DEV0_EPF0_VF29_BIF_BME_STATUS                                                         0x00eb
8023 #define mmBIF_BX_DEV0_EPF0_VF29_BIF_BME_STATUS_BASE_IDX                                                2
8024 #define mmBIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG                                                     0x00ec
8025 #define mmBIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG_BASE_IDX                                            2
8026 #define mmBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0x00f3
8027 #define mmBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                          2
8028 #define mmBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0x00f4
8029 #define mmBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                           2
8030 #define mmBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_CNTL                                        0x00f5
8031 #define mmBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                               2
8032 #define mmBIF_BX_DEV0_EPF0_VF29_HDP_REG_COHERENCY_FLUSH_CNTL                                           0x00f6
8033 #define mmBIF_BX_DEV0_EPF0_VF29_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
8034 #define mmBIF_BX_DEV0_EPF0_VF29_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0x00f7
8035 #define mmBIF_BX_DEV0_EPF0_VF29_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
8036 #define mmBIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ                                                      0x0106
8037 #define mmBIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ_BASE_IDX                                             2
8038 #define mmBIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE                                                     0x0107
8039 #define mmBIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE_BASE_IDX                                            2
8040 #define mmBIF_BX_DEV0_EPF0_VF29_BIF_TRANS_PENDING                                                      0x0108
8041 #define mmBIF_BX_DEV0_EPF0_VF29_BIF_TRANS_PENDING_BASE_IDX                                             2
8042 #define mmBIF_BX_DEV0_EPF0_VF29_NBIF_GFX_ADDR_LUT_BYPASS                                               0x0112
8043 #define mmBIF_BX_DEV0_EPF0_VF29_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                      2
8044 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW0                                                 0x0136
8045 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                        2
8046 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW1                                                 0x0137
8047 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                        2
8048 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW2                                                 0x0138
8049 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                        2
8050 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW3                                                 0x0139
8051 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                        2
8052 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW0                                                 0x013a
8053 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                        2
8054 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW1                                                 0x013b
8055 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                        2
8056 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW2                                                 0x013c
8057 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                        2
8058 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW3                                                 0x013d
8059 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                        2
8060 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL                                                        0x013e
8061 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL_BASE_IDX                                               2
8062 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_INT_CNTL                                                       0x013f
8063 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_INT_CNTL_BASE_IDX                                              2
8064 #define mmBIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX                                                       0x0140
8065 #define mmBIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX_BASE_IDX                                              2
8066 
8067 
8068 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf29_BIFDEC2
8069 // base address: 0x0
8070 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_LO                                                     0x0400
8071 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                            3
8072 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_HI                                                     0x0401
8073 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                            3
8074 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_MSG_DATA                                                    0x0402
8075 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                           3
8076 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_CONTROL                                                     0x0403
8077 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_CONTROL_BASE_IDX                                            3
8078 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_LO                                                     0x0404
8079 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                            3
8080 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_HI                                                     0x0405
8081 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                            3
8082 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_MSG_DATA                                                    0x0406
8083 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                           3
8084 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_CONTROL                                                     0x0407
8085 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_CONTROL_BASE_IDX                                            3
8086 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_LO                                                     0x0408
8087 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                            3
8088 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_HI                                                     0x0409
8089 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                            3
8090 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_MSG_DATA                                                    0x040a
8091 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                           3
8092 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_CONTROL                                                     0x040b
8093 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_CONTROL_BASE_IDX                                            3
8094 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_LO                                                     0x040c
8095 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                            3
8096 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_HI                                                     0x040d
8097 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                            3
8098 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_MSG_DATA                                                    0x040e
8099 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                           3
8100 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_CONTROL                                                     0x040f
8101 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_CONTROL_BASE_IDX                                            3
8102 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_PBA                                                               0x0800
8103 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_PBA_BASE_IDX                                                      3
8104 
8105 
8106 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf30_SYSPFVFDEC
8107 // base address: 0x0
8108 #define mmBIF_BX_DEV0_EPF0_VF30_MM_INDEX                                                               0x0000
8109 #define mmBIF_BX_DEV0_EPF0_VF30_MM_INDEX_BASE_IDX                                                      0
8110 #define mmBIF_BX_DEV0_EPF0_VF30_MM_DATA                                                                0x0001
8111 #define mmBIF_BX_DEV0_EPF0_VF30_MM_DATA_BASE_IDX                                                       0
8112 #define mmBIF_BX_DEV0_EPF0_VF30_MM_INDEX_HI                                                            0x0006
8113 #define mmBIF_BX_DEV0_EPF0_VF30_MM_INDEX_HI_BASE_IDX                                                   0
8114 
8115 
8116 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf30_BIFPFVFDEC1
8117 // base address: 0x0
8118 #define mmRCC_DEV0_EPF0_VF30_RCC_ERR_LOG                                                               0x0085
8119 #define mmRCC_DEV0_EPF0_VF30_RCC_ERR_LOG_BASE_IDX                                                      2
8120 #define mmRCC_DEV0_EPF0_VF30_RCC_DOORBELL_APER_EN                                                      0x00c0
8121 #define mmRCC_DEV0_EPF0_VF30_RCC_DOORBELL_APER_EN_BASE_IDX                                             2
8122 #define mmRCC_DEV0_EPF0_VF30_RCC_CONFIG_MEMSIZE                                                        0x00c3
8123 #define mmRCC_DEV0_EPF0_VF30_RCC_CONFIG_MEMSIZE_BASE_IDX                                               2
8124 #define mmRCC_DEV0_EPF0_VF30_RCC_CONFIG_RESERVED                                                       0x00c4
8125 #define mmRCC_DEV0_EPF0_VF30_RCC_CONFIG_RESERVED_BASE_IDX                                              2
8126 #define mmRCC_DEV0_EPF0_VF30_RCC_IOV_FUNC_IDENTIFIER                                                   0x00c5
8127 #define mmRCC_DEV0_EPF0_VF30_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                          2
8128 
8129 
8130 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf30_BIFPFVFDEC1
8131 // base address: 0x0
8132 #define mmBIF_BX_DEV0_EPF0_VF30_BIF_BME_STATUS                                                         0x00eb
8133 #define mmBIF_BX_DEV0_EPF0_VF30_BIF_BME_STATUS_BASE_IDX                                                2
8134 #define mmBIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG                                                     0x00ec
8135 #define mmBIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG_BASE_IDX                                            2
8136 #define mmBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0x00f3
8137 #define mmBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                          2
8138 #define mmBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0x00f4
8139 #define mmBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                           2
8140 #define mmBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_CNTL                                        0x00f5
8141 #define mmBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                               2
8142 #define mmBIF_BX_DEV0_EPF0_VF30_HDP_REG_COHERENCY_FLUSH_CNTL                                           0x00f6
8143 #define mmBIF_BX_DEV0_EPF0_VF30_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
8144 #define mmBIF_BX_DEV0_EPF0_VF30_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0x00f7
8145 #define mmBIF_BX_DEV0_EPF0_VF30_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                  2
8146 #define mmBIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ                                                      0x0106
8147 #define mmBIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ_BASE_IDX                                             2
8148 #define mmBIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE                                                     0x0107
8149 #define mmBIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE_BASE_IDX                                            2
8150 #define mmBIF_BX_DEV0_EPF0_VF30_BIF_TRANS_PENDING                                                      0x0108
8151 #define mmBIF_BX_DEV0_EPF0_VF30_BIF_TRANS_PENDING_BASE_IDX                                             2
8152 #define mmBIF_BX_DEV0_EPF0_VF30_NBIF_GFX_ADDR_LUT_BYPASS                                               0x0112
8153 #define mmBIF_BX_DEV0_EPF0_VF30_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                      2
8154 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW0                                                 0x0136
8155 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                        2
8156 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW1                                                 0x0137
8157 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                        2
8158 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW2                                                 0x0138
8159 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                        2
8160 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW3                                                 0x0139
8161 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                        2
8162 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW0                                                 0x013a
8163 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                        2
8164 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW1                                                 0x013b
8165 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                        2
8166 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW2                                                 0x013c
8167 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                        2
8168 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW3                                                 0x013d
8169 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                        2
8170 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL                                                        0x013e
8171 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL_BASE_IDX                                               2
8172 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_INT_CNTL                                                       0x013f
8173 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_INT_CNTL_BASE_IDX                                              2
8174 #define mmBIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX                                                       0x0140
8175 #define mmBIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX_BASE_IDX                                              2
8176 
8177 
8178 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf30_BIFDEC2
8179 // base address: 0x0
8180 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_LO                                                     0x0400
8181 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                            3
8182 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_HI                                                     0x0401
8183 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                            3
8184 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_MSG_DATA                                                    0x0402
8185 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                           3
8186 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_CONTROL                                                     0x0403
8187 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_CONTROL_BASE_IDX                                            3
8188 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_LO                                                     0x0404
8189 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                            3
8190 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_HI                                                     0x0405
8191 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                            3
8192 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_MSG_DATA                                                    0x0406
8193 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                           3
8194 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_CONTROL                                                     0x0407
8195 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_CONTROL_BASE_IDX                                            3
8196 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_LO                                                     0x0408
8197 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                            3
8198 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_HI                                                     0x0409
8199 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                            3
8200 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_MSG_DATA                                                    0x040a
8201 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                           3
8202 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_CONTROL                                                     0x040b
8203 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_CONTROL_BASE_IDX                                            3
8204 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_LO                                                     0x040c
8205 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                            3
8206 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_HI                                                     0x040d
8207 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                            3
8208 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_MSG_DATA                                                    0x040e
8209 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                           3
8210 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_CONTROL                                                     0x040f
8211 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_CONTROL_BASE_IDX                                            3
8212 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_PBA                                                               0x0800
8213 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_PBA_BASE_IDX                                                      3
8214 
8215 
8216 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC
8217 // base address: 0xd0000000
8218 #define cfgBIF_BX_DEV0_EPF0_VF0_MM_INDEX                                                                0xd0000000
8219 #define cfgBIF_BX_DEV0_EPF0_VF0_MM_DATA                                                                 0xd0000004
8220 #define cfgBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI                                                             0xd0000018
8221 
8222 
8223 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFPFVFDEC1
8224 // base address: 0xd0000000
8225 #define cfgRCC_DEV0_EPF0_VF0_RCC_ERR_LOG                                                                0xd0003694
8226 #define cfgRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN                                                       0xd0003780
8227 #define cfgRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE                                                         0xd000378c
8228 #define cfgRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED                                                        0xd0003790
8229 #define cfgRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER                                                    0xd0003794
8230 
8231 
8232 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1
8233 // base address: 0xd0000000
8234 #define cfgBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS                                                          0xd000382c
8235 #define cfgBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG                                                      0xd0003830
8236 #define cfgBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                    0xd000384c
8237 #define cfgBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                     0xd0003850
8238 #define cfgBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL                                         0xd0003854
8239 #define cfgBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL                                            0xd0003858
8240 #define cfgBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL                                            0xd000385c
8241 #define cfgBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ                                                       0xd0003898
8242 #define cfgBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE                                                      0xd000389c
8243 #define cfgBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING                                                       0xd00038a0
8244 #define cfgBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS                                                0xd00038c8
8245 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0                                                  0xd0003958
8246 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1                                                  0xd000395c
8247 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2                                                  0xd0003960
8248 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3                                                  0xd0003964
8249 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0                                                  0xd0003968
8250 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1                                                  0xd000396c
8251 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2                                                  0xd0003970
8252 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3                                                  0xd0003974
8253 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL                                                         0xd0003978
8254 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL                                                        0xd000397c
8255 #define cfgBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX                                                        0xd0003980
8256 
8257 
8258 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFDEC2
8259 // base address: 0xd0000000
8260 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO                                                      0xd0042000
8261 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI                                                      0xd0042004
8262 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA                                                     0xd0042008
8263 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL                                                      0xd004200c
8264 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO                                                      0xd0042010
8265 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI                                                      0xd0042014
8266 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA                                                     0xd0042018
8267 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL                                                      0xd004201c
8268 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO                                                      0xd0042020
8269 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI                                                      0xd0042024
8270 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA                                                     0xd0042028
8271 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL                                                      0xd004202c
8272 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO                                                      0xd0042030
8273 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI                                                      0xd0042034
8274 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA                                                     0xd0042038
8275 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL                                                      0xd004203c
8276 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_PBA                                                                0xd0043000
8277 
8278 
8279 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC
8280 // base address: 0xd0080000
8281 #define cfgBIF_BX_DEV0_EPF0_VF1_MM_INDEX                                                                0xd0080000
8282 #define cfgBIF_BX_DEV0_EPF0_VF1_MM_DATA                                                                 0xd0080004
8283 #define cfgBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI                                                             0xd0080018
8284 
8285 
8286 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFPFVFDEC1
8287 // base address: 0xd0080000
8288 #define cfgRCC_DEV0_EPF0_VF1_RCC_ERR_LOG                                                                0xd0083694
8289 #define cfgRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN                                                       0xd0083780
8290 #define cfgRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE                                                         0xd008378c
8291 #define cfgRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED                                                        0xd0083790
8292 #define cfgRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER                                                    0xd0083794
8293 
8294 
8295 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1
8296 // base address: 0xd0080000
8297 #define cfgBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS                                                          0xd008382c
8298 #define cfgBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG                                                      0xd0083830
8299 #define cfgBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                    0xd008384c
8300 #define cfgBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                     0xd0083850
8301 #define cfgBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL                                         0xd0083854
8302 #define cfgBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL                                            0xd0083858
8303 #define cfgBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL                                            0xd008385c
8304 #define cfgBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ                                                       0xd0083898
8305 #define cfgBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE                                                      0xd008389c
8306 #define cfgBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING                                                       0xd00838a0
8307 #define cfgBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS                                                0xd00838c8
8308 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0                                                  0xd0083958
8309 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1                                                  0xd008395c
8310 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2                                                  0xd0083960
8311 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3                                                  0xd0083964
8312 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0                                                  0xd0083968
8313 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1                                                  0xd008396c
8314 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2                                                  0xd0083970
8315 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3                                                  0xd0083974
8316 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL                                                         0xd0083978
8317 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL                                                        0xd008397c
8318 #define cfgBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX                                                        0xd0083980
8319 
8320 
8321 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFDEC2
8322 // base address: 0xd0080000
8323 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO                                                      0xd00c2000
8324 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI                                                      0xd00c2004
8325 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA                                                     0xd00c2008
8326 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL                                                      0xd00c200c
8327 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO                                                      0xd00c2010
8328 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI                                                      0xd00c2014
8329 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA                                                     0xd00c2018
8330 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL                                                      0xd00c201c
8331 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO                                                      0xd00c2020
8332 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI                                                      0xd00c2024
8333 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA                                                     0xd00c2028
8334 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL                                                      0xd00c202c
8335 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO                                                      0xd00c2030
8336 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI                                                      0xd00c2034
8337 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA                                                     0xd00c2038
8338 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL                                                      0xd00c203c
8339 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_PBA                                                                0xd00c3000
8340 
8341 
8342 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC
8343 // base address: 0xd0100000
8344 #define cfgBIF_BX_DEV0_EPF0_VF2_MM_INDEX                                                                0xd0100000
8345 #define cfgBIF_BX_DEV0_EPF0_VF2_MM_DATA                                                                 0xd0100004
8346 #define cfgBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI                                                             0xd0100018
8347 
8348 
8349 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFPFVFDEC1
8350 // base address: 0xd0100000
8351 #define cfgRCC_DEV0_EPF0_VF2_RCC_ERR_LOG                                                                0xd0103694
8352 #define cfgRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN                                                       0xd0103780
8353 #define cfgRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE                                                         0xd010378c
8354 #define cfgRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED                                                        0xd0103790
8355 #define cfgRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER                                                    0xd0103794
8356 
8357 
8358 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1
8359 // base address: 0xd0100000
8360 #define cfgBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS                                                          0xd010382c
8361 #define cfgBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG                                                      0xd0103830
8362 #define cfgBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                    0xd010384c
8363 #define cfgBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                     0xd0103850
8364 #define cfgBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL                                         0xd0103854
8365 #define cfgBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL                                            0xd0103858
8366 #define cfgBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL                                            0xd010385c
8367 #define cfgBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ                                                       0xd0103898
8368 #define cfgBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE                                                      0xd010389c
8369 #define cfgBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING                                                       0xd01038a0
8370 #define cfgBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS                                                0xd01038c8
8371 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0                                                  0xd0103958
8372 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1                                                  0xd010395c
8373 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2                                                  0xd0103960
8374 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3                                                  0xd0103964
8375 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0                                                  0xd0103968
8376 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1                                                  0xd010396c
8377 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2                                                  0xd0103970
8378 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3                                                  0xd0103974
8379 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL                                                         0xd0103978
8380 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL                                                        0xd010397c
8381 #define cfgBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX                                                        0xd0103980
8382 
8383 
8384 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFDEC2
8385 // base address: 0xd0100000
8386 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO                                                      0xd0142000
8387 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI                                                      0xd0142004
8388 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA                                                     0xd0142008
8389 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL                                                      0xd014200c
8390 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO                                                      0xd0142010
8391 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI                                                      0xd0142014
8392 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA                                                     0xd0142018
8393 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL                                                      0xd014201c
8394 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO                                                      0xd0142020
8395 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI                                                      0xd0142024
8396 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA                                                     0xd0142028
8397 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL                                                      0xd014202c
8398 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO                                                      0xd0142030
8399 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI                                                      0xd0142034
8400 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA                                                     0xd0142038
8401 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL                                                      0xd014203c
8402 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_PBA                                                                0xd0143000
8403 
8404 
8405 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC
8406 // base address: 0xd0180000
8407 #define cfgBIF_BX_DEV0_EPF0_VF3_MM_INDEX                                                                0xd0180000
8408 #define cfgBIF_BX_DEV0_EPF0_VF3_MM_DATA                                                                 0xd0180004
8409 #define cfgBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI                                                             0xd0180018
8410 
8411 
8412 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFPFVFDEC1
8413 // base address: 0xd0180000
8414 #define cfgRCC_DEV0_EPF0_VF3_RCC_ERR_LOG                                                                0xd0183694
8415 #define cfgRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN                                                       0xd0183780
8416 #define cfgRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE                                                         0xd018378c
8417 #define cfgRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED                                                        0xd0183790
8418 #define cfgRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER                                                    0xd0183794
8419 
8420 
8421 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1
8422 // base address: 0xd0180000
8423 #define cfgBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS                                                          0xd018382c
8424 #define cfgBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG                                                      0xd0183830
8425 #define cfgBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                    0xd018384c
8426 #define cfgBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                     0xd0183850
8427 #define cfgBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL                                         0xd0183854
8428 #define cfgBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL                                            0xd0183858
8429 #define cfgBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL                                            0xd018385c
8430 #define cfgBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ                                                       0xd0183898
8431 #define cfgBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE                                                      0xd018389c
8432 #define cfgBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING                                                       0xd01838a0
8433 #define cfgBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS                                                0xd01838c8
8434 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0                                                  0xd0183958
8435 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1                                                  0xd018395c
8436 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2                                                  0xd0183960
8437 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3                                                  0xd0183964
8438 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0                                                  0xd0183968
8439 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1                                                  0xd018396c
8440 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2                                                  0xd0183970
8441 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3                                                  0xd0183974
8442 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL                                                         0xd0183978
8443 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL                                                        0xd018397c
8444 #define cfgBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX                                                        0xd0183980
8445 
8446 
8447 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFDEC2
8448 // base address: 0xd0180000
8449 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO                                                      0xd01c2000
8450 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI                                                      0xd01c2004
8451 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA                                                     0xd01c2008
8452 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL                                                      0xd01c200c
8453 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO                                                      0xd01c2010
8454 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI                                                      0xd01c2014
8455 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA                                                     0xd01c2018
8456 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL                                                      0xd01c201c
8457 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO                                                      0xd01c2020
8458 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI                                                      0xd01c2024
8459 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA                                                     0xd01c2028
8460 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL                                                      0xd01c202c
8461 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO                                                      0xd01c2030
8462 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI                                                      0xd01c2034
8463 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA                                                     0xd01c2038
8464 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL                                                      0xd01c203c
8465 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_PBA                                                                0xd01c3000
8466 
8467 
8468 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC
8469 // base address: 0xd0200000
8470 #define cfgBIF_BX_DEV0_EPF0_VF4_MM_INDEX                                                                0xd0200000
8471 #define cfgBIF_BX_DEV0_EPF0_VF4_MM_DATA                                                                 0xd0200004
8472 #define cfgBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI                                                             0xd0200018
8473 
8474 
8475 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFPFVFDEC1
8476 // base address: 0xd0200000
8477 #define cfgRCC_DEV0_EPF0_VF4_RCC_ERR_LOG                                                                0xd0203694
8478 #define cfgRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN                                                       0xd0203780
8479 #define cfgRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE                                                         0xd020378c
8480 #define cfgRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED                                                        0xd0203790
8481 #define cfgRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER                                                    0xd0203794
8482 
8483 
8484 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1
8485 // base address: 0xd0200000
8486 #define cfgBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS                                                          0xd020382c
8487 #define cfgBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG                                                      0xd0203830
8488 #define cfgBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                    0xd020384c
8489 #define cfgBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                     0xd0203850
8490 #define cfgBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL                                         0xd0203854
8491 #define cfgBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL                                            0xd0203858
8492 #define cfgBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL                                            0xd020385c
8493 #define cfgBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ                                                       0xd0203898
8494 #define cfgBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE                                                      0xd020389c
8495 #define cfgBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING                                                       0xd02038a0
8496 #define cfgBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS                                                0xd02038c8
8497 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0                                                  0xd0203958
8498 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1                                                  0xd020395c
8499 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2                                                  0xd0203960
8500 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3                                                  0xd0203964
8501 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0                                                  0xd0203968
8502 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1                                                  0xd020396c
8503 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2                                                  0xd0203970
8504 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3                                                  0xd0203974
8505 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL                                                         0xd0203978
8506 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL                                                        0xd020397c
8507 #define cfgBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX                                                        0xd0203980
8508 
8509 
8510 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFDEC2
8511 // base address: 0xd0200000
8512 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO                                                      0xd0242000
8513 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI                                                      0xd0242004
8514 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA                                                     0xd0242008
8515 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL                                                      0xd024200c
8516 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO                                                      0xd0242010
8517 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI                                                      0xd0242014
8518 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA                                                     0xd0242018
8519 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL                                                      0xd024201c
8520 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO                                                      0xd0242020
8521 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI                                                      0xd0242024
8522 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA                                                     0xd0242028
8523 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL                                                      0xd024202c
8524 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO                                                      0xd0242030
8525 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI                                                      0xd0242034
8526 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA                                                     0xd0242038
8527 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL                                                      0xd024203c
8528 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_PBA                                                                0xd0243000
8529 
8530 
8531 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC
8532 // base address: 0xd0280000
8533 #define cfgBIF_BX_DEV0_EPF0_VF5_MM_INDEX                                                                0xd0280000
8534 #define cfgBIF_BX_DEV0_EPF0_VF5_MM_DATA                                                                 0xd0280004
8535 #define cfgBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI                                                             0xd0280018
8536 
8537 
8538 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFPFVFDEC1
8539 // base address: 0xd0280000
8540 #define cfgRCC_DEV0_EPF0_VF5_RCC_ERR_LOG                                                                0xd0283694
8541 #define cfgRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN                                                       0xd0283780
8542 #define cfgRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE                                                         0xd028378c
8543 #define cfgRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED                                                        0xd0283790
8544 #define cfgRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER                                                    0xd0283794
8545 
8546 
8547 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1
8548 // base address: 0xd0280000
8549 #define cfgBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS                                                          0xd028382c
8550 #define cfgBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG                                                      0xd0283830
8551 #define cfgBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                    0xd028384c
8552 #define cfgBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                     0xd0283850
8553 #define cfgBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL                                         0xd0283854
8554 #define cfgBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL                                            0xd0283858
8555 #define cfgBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL                                            0xd028385c
8556 #define cfgBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ                                                       0xd0283898
8557 #define cfgBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE                                                      0xd028389c
8558 #define cfgBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING                                                       0xd02838a0
8559 #define cfgBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS                                                0xd02838c8
8560 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0                                                  0xd0283958
8561 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1                                                  0xd028395c
8562 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2                                                  0xd0283960
8563 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3                                                  0xd0283964
8564 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0                                                  0xd0283968
8565 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1                                                  0xd028396c
8566 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2                                                  0xd0283970
8567 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3                                                  0xd0283974
8568 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL                                                         0xd0283978
8569 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL                                                        0xd028397c
8570 #define cfgBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX                                                        0xd0283980
8571 
8572 
8573 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFDEC2
8574 // base address: 0xd0280000
8575 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO                                                      0xd02c2000
8576 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI                                                      0xd02c2004
8577 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA                                                     0xd02c2008
8578 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL                                                      0xd02c200c
8579 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO                                                      0xd02c2010
8580 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI                                                      0xd02c2014
8581 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA                                                     0xd02c2018
8582 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL                                                      0xd02c201c
8583 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO                                                      0xd02c2020
8584 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI                                                      0xd02c2024
8585 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA                                                     0xd02c2028
8586 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL                                                      0xd02c202c
8587 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO                                                      0xd02c2030
8588 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI                                                      0xd02c2034
8589 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA                                                     0xd02c2038
8590 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL                                                      0xd02c203c
8591 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_PBA                                                                0xd02c3000
8592 
8593 
8594 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC
8595 // base address: 0xd0300000
8596 #define cfgBIF_BX_DEV0_EPF0_VF6_MM_INDEX                                                                0xd0300000
8597 #define cfgBIF_BX_DEV0_EPF0_VF6_MM_DATA                                                                 0xd0300004
8598 #define cfgBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI                                                             0xd0300018
8599 
8600 
8601 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFPFVFDEC1
8602 // base address: 0xd0300000
8603 #define cfgRCC_DEV0_EPF0_VF6_RCC_ERR_LOG                                                                0xd0303694
8604 #define cfgRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN                                                       0xd0303780
8605 #define cfgRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE                                                         0xd030378c
8606 #define cfgRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED                                                        0xd0303790
8607 #define cfgRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER                                                    0xd0303794
8608 
8609 
8610 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1
8611 // base address: 0xd0300000
8612 #define cfgBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS                                                          0xd030382c
8613 #define cfgBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG                                                      0xd0303830
8614 #define cfgBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                    0xd030384c
8615 #define cfgBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                     0xd0303850
8616 #define cfgBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL                                         0xd0303854
8617 #define cfgBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL                                            0xd0303858
8618 #define cfgBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL                                            0xd030385c
8619 #define cfgBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ                                                       0xd0303898
8620 #define cfgBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE                                                      0xd030389c
8621 #define cfgBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING                                                       0xd03038a0
8622 #define cfgBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS                                                0xd03038c8
8623 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0                                                  0xd0303958
8624 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1                                                  0xd030395c
8625 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2                                                  0xd0303960
8626 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3                                                  0xd0303964
8627 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0                                                  0xd0303968
8628 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1                                                  0xd030396c
8629 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2                                                  0xd0303970
8630 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3                                                  0xd0303974
8631 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL                                                         0xd0303978
8632 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL                                                        0xd030397c
8633 #define cfgBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX                                                        0xd0303980
8634 
8635 
8636 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFDEC2
8637 // base address: 0xd0300000
8638 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO                                                      0xd0342000
8639 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI                                                      0xd0342004
8640 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA                                                     0xd0342008
8641 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL                                                      0xd034200c
8642 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO                                                      0xd0342010
8643 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI                                                      0xd0342014
8644 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA                                                     0xd0342018
8645 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL                                                      0xd034201c
8646 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO                                                      0xd0342020
8647 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI                                                      0xd0342024
8648 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA                                                     0xd0342028
8649 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL                                                      0xd034202c
8650 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO                                                      0xd0342030
8651 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI                                                      0xd0342034
8652 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA                                                     0xd0342038
8653 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL                                                      0xd034203c
8654 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_PBA                                                                0xd0343000
8655 
8656 
8657 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC
8658 // base address: 0xd0380000
8659 #define cfgBIF_BX_DEV0_EPF0_VF7_MM_INDEX                                                                0xd0380000
8660 #define cfgBIF_BX_DEV0_EPF0_VF7_MM_DATA                                                                 0xd0380004
8661 #define cfgBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI                                                             0xd0380018
8662 
8663 
8664 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFPFVFDEC1
8665 // base address: 0xd0380000
8666 #define cfgRCC_DEV0_EPF0_VF7_RCC_ERR_LOG                                                                0xd0383694
8667 #define cfgRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN                                                       0xd0383780
8668 #define cfgRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE                                                         0xd038378c
8669 #define cfgRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED                                                        0xd0383790
8670 #define cfgRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER                                                    0xd0383794
8671 
8672 
8673 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1
8674 // base address: 0xd0380000
8675 #define cfgBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS                                                          0xd038382c
8676 #define cfgBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG                                                      0xd0383830
8677 #define cfgBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                    0xd038384c
8678 #define cfgBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                     0xd0383850
8679 #define cfgBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL                                         0xd0383854
8680 #define cfgBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL                                            0xd0383858
8681 #define cfgBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL                                            0xd038385c
8682 #define cfgBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ                                                       0xd0383898
8683 #define cfgBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE                                                      0xd038389c
8684 #define cfgBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING                                                       0xd03838a0
8685 #define cfgBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS                                                0xd03838c8
8686 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0                                                  0xd0383958
8687 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1                                                  0xd038395c
8688 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2                                                  0xd0383960
8689 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3                                                  0xd0383964
8690 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0                                                  0xd0383968
8691 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1                                                  0xd038396c
8692 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2                                                  0xd0383970
8693 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3                                                  0xd0383974
8694 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL                                                         0xd0383978
8695 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL                                                        0xd038397c
8696 #define cfgBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX                                                        0xd0383980
8697 
8698 
8699 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFDEC2
8700 // base address: 0xd0380000
8701 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO                                                      0xd03c2000
8702 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI                                                      0xd03c2004
8703 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA                                                     0xd03c2008
8704 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL                                                      0xd03c200c
8705 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO                                                      0xd03c2010
8706 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI                                                      0xd03c2014
8707 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA                                                     0xd03c2018
8708 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL                                                      0xd03c201c
8709 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO                                                      0xd03c2020
8710 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI                                                      0xd03c2024
8711 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA                                                     0xd03c2028
8712 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL                                                      0xd03c202c
8713 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO                                                      0xd03c2030
8714 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI                                                      0xd03c2034
8715 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA                                                     0xd03c2038
8716 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL                                                      0xd03c203c
8717 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_PBA                                                                0xd03c3000
8718 
8719 
8720 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_SYSPFVFDEC
8721 // base address: 0xd0400000
8722 #define cfgBIF_BX_DEV0_EPF0_VF8_MM_INDEX                                                                0xd0400000
8723 #define cfgBIF_BX_DEV0_EPF0_VF8_MM_DATA                                                                 0xd0400004
8724 #define cfgBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI                                                             0xd0400018
8725 
8726 
8727 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFPFVFDEC1
8728 // base address: 0xd0400000
8729 #define cfgRCC_DEV0_EPF0_VF8_RCC_ERR_LOG                                                                0xd0403694
8730 #define cfgRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN                                                       0xd0403780
8731 #define cfgRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE                                                         0xd040378c
8732 #define cfgRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED                                                        0xd0403790
8733 #define cfgRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER                                                    0xd0403794
8734 
8735 
8736 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_BIFPFVFDEC1
8737 // base address: 0xd0400000
8738 #define cfgBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS                                                          0xd040382c
8739 #define cfgBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG                                                      0xd0403830
8740 #define cfgBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                    0xd040384c
8741 #define cfgBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                     0xd0403850
8742 #define cfgBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL                                         0xd0403854
8743 #define cfgBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL                                            0xd0403858
8744 #define cfgBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL                                            0xd040385c
8745 #define cfgBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ                                                       0xd0403898
8746 #define cfgBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE                                                      0xd040389c
8747 #define cfgBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING                                                       0xd04038a0
8748 #define cfgBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS                                                0xd04038c8
8749 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0                                                  0xd0403958
8750 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1                                                  0xd040395c
8751 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2                                                  0xd0403960
8752 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3                                                  0xd0403964
8753 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0                                                  0xd0403968
8754 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1                                                  0xd040396c
8755 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2                                                  0xd0403970
8756 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3                                                  0xd0403974
8757 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL                                                         0xd0403978
8758 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL                                                        0xd040397c
8759 #define cfgBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX                                                        0xd0403980
8760 
8761 
8762 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFDEC2
8763 // base address: 0xd0400000
8764 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO                                                      0xd0442000
8765 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI                                                      0xd0442004
8766 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA                                                     0xd0442008
8767 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL                                                      0xd044200c
8768 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO                                                      0xd0442010
8769 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI                                                      0xd0442014
8770 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA                                                     0xd0442018
8771 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL                                                      0xd044201c
8772 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO                                                      0xd0442020
8773 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI                                                      0xd0442024
8774 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA                                                     0xd0442028
8775 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL                                                      0xd044202c
8776 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO                                                      0xd0442030
8777 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI                                                      0xd0442034
8778 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA                                                     0xd0442038
8779 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL                                                      0xd044203c
8780 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_PBA                                                                0xd0443000
8781 
8782 
8783 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_SYSPFVFDEC
8784 // base address: 0xd0480000
8785 #define cfgBIF_BX_DEV0_EPF0_VF9_MM_INDEX                                                                0xd0480000
8786 #define cfgBIF_BX_DEV0_EPF0_VF9_MM_DATA                                                                 0xd0480004
8787 #define cfgBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI                                                             0xd0480018
8788 
8789 
8790 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFPFVFDEC1
8791 // base address: 0xd0480000
8792 #define cfgRCC_DEV0_EPF0_VF9_RCC_ERR_LOG                                                                0xd0483694
8793 #define cfgRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN                                                       0xd0483780
8794 #define cfgRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE                                                         0xd048378c
8795 #define cfgRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED                                                        0xd0483790
8796 #define cfgRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER                                                    0xd0483794
8797 
8798 
8799 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_BIFPFVFDEC1
8800 // base address: 0xd0480000
8801 #define cfgBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS                                                          0xd048382c
8802 #define cfgBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG                                                      0xd0483830
8803 #define cfgBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                    0xd048384c
8804 #define cfgBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                     0xd0483850
8805 #define cfgBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL                                         0xd0483854
8806 #define cfgBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL                                            0xd0483858
8807 #define cfgBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL                                            0xd048385c
8808 #define cfgBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ                                                       0xd0483898
8809 #define cfgBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE                                                      0xd048389c
8810 #define cfgBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING                                                       0xd04838a0
8811 #define cfgBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS                                                0xd04838c8
8812 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0                                                  0xd0483958
8813 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1                                                  0xd048395c
8814 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2                                                  0xd0483960
8815 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3                                                  0xd0483964
8816 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0                                                  0xd0483968
8817 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1                                                  0xd048396c
8818 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2                                                  0xd0483970
8819 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3                                                  0xd0483974
8820 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL                                                         0xd0483978
8821 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL                                                        0xd048397c
8822 #define cfgBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX                                                        0xd0483980
8823 
8824 
8825 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFDEC2
8826 // base address: 0xd0480000
8827 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO                                                      0xd04c2000
8828 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI                                                      0xd04c2004
8829 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA                                                     0xd04c2008
8830 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL                                                      0xd04c200c
8831 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO                                                      0xd04c2010
8832 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI                                                      0xd04c2014
8833 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA                                                     0xd04c2018
8834 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL                                                      0xd04c201c
8835 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO                                                      0xd04c2020
8836 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI                                                      0xd04c2024
8837 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA                                                     0xd04c2028
8838 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL                                                      0xd04c202c
8839 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO                                                      0xd04c2030
8840 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI                                                      0xd04c2034
8841 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA                                                     0xd04c2038
8842 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL                                                      0xd04c203c
8843 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_PBA                                                                0xd04c3000
8844 
8845 
8846 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_SYSPFVFDEC
8847 // base address: 0xd0500000
8848 #define cfgBIF_BX_DEV0_EPF0_VF10_MM_INDEX                                                               0xd0500000
8849 #define cfgBIF_BX_DEV0_EPF0_VF10_MM_DATA                                                                0xd0500004
8850 #define cfgBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI                                                            0xd0500018
8851 
8852 
8853 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFPFVFDEC1
8854 // base address: 0xd0500000
8855 #define cfgRCC_DEV0_EPF0_VF10_RCC_ERR_LOG                                                               0xd0503694
8856 #define cfgRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN                                                      0xd0503780
8857 #define cfgRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE                                                        0xd050378c
8858 #define cfgRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED                                                       0xd0503790
8859 #define cfgRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER                                                   0xd0503794
8860 
8861 
8862 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_BIFPFVFDEC1
8863 // base address: 0xd0500000
8864 #define cfgBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS                                                         0xd050382c
8865 #define cfgBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG                                                     0xd0503830
8866 #define cfgBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0xd050384c
8867 #define cfgBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0xd0503850
8868 #define cfgBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL                                        0xd0503854
8869 #define cfgBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL                                           0xd0503858
8870 #define cfgBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0xd050385c
8871 #define cfgBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ                                                      0xd0503898
8872 #define cfgBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE                                                     0xd050389c
8873 #define cfgBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING                                                      0xd05038a0
8874 #define cfgBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS                                               0xd05038c8
8875 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0                                                 0xd0503958
8876 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1                                                 0xd050395c
8877 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2                                                 0xd0503960
8878 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3                                                 0xd0503964
8879 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0                                                 0xd0503968
8880 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1                                                 0xd050396c
8881 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2                                                 0xd0503970
8882 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3                                                 0xd0503974
8883 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL                                                        0xd0503978
8884 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL                                                       0xd050397c
8885 #define cfgBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX                                                       0xd0503980
8886 
8887 
8888 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFDEC2
8889 // base address: 0xd0500000
8890 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO                                                     0xd0542000
8891 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI                                                     0xd0542004
8892 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA                                                    0xd0542008
8893 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL                                                     0xd054200c
8894 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO                                                     0xd0542010
8895 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI                                                     0xd0542014
8896 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA                                                    0xd0542018
8897 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL                                                     0xd054201c
8898 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO                                                     0xd0542020
8899 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI                                                     0xd0542024
8900 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA                                                    0xd0542028
8901 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL                                                     0xd054202c
8902 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO                                                     0xd0542030
8903 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI                                                     0xd0542034
8904 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA                                                    0xd0542038
8905 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL                                                     0xd054203c
8906 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_PBA                                                               0xd0543000
8907 
8908 
8909 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_SYSPFVFDEC
8910 // base address: 0xd0580000
8911 #define cfgBIF_BX_DEV0_EPF0_VF11_MM_INDEX                                                               0xd0580000
8912 #define cfgBIF_BX_DEV0_EPF0_VF11_MM_DATA                                                                0xd0580004
8913 #define cfgBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI                                                            0xd0580018
8914 
8915 
8916 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFPFVFDEC1
8917 // base address: 0xd0580000
8918 #define cfgRCC_DEV0_EPF0_VF11_RCC_ERR_LOG                                                               0xd0583694
8919 #define cfgRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN                                                      0xd0583780
8920 #define cfgRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE                                                        0xd058378c
8921 #define cfgRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED                                                       0xd0583790
8922 #define cfgRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER                                                   0xd0583794
8923 
8924 
8925 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_BIFPFVFDEC1
8926 // base address: 0xd0580000
8927 #define cfgBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS                                                         0xd058382c
8928 #define cfgBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG                                                     0xd0583830
8929 #define cfgBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0xd058384c
8930 #define cfgBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0xd0583850
8931 #define cfgBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL                                        0xd0583854
8932 #define cfgBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL                                           0xd0583858
8933 #define cfgBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0xd058385c
8934 #define cfgBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ                                                      0xd0583898
8935 #define cfgBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE                                                     0xd058389c
8936 #define cfgBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING                                                      0xd05838a0
8937 #define cfgBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS                                               0xd05838c8
8938 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0                                                 0xd0583958
8939 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1                                                 0xd058395c
8940 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2                                                 0xd0583960
8941 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3                                                 0xd0583964
8942 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0                                                 0xd0583968
8943 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1                                                 0xd058396c
8944 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2                                                 0xd0583970
8945 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3                                                 0xd0583974
8946 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL                                                        0xd0583978
8947 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL                                                       0xd058397c
8948 #define cfgBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX                                                       0xd0583980
8949 
8950 
8951 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFDEC2
8952 // base address: 0xd0580000
8953 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO                                                     0xd05c2000
8954 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI                                                     0xd05c2004
8955 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA                                                    0xd05c2008
8956 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL                                                     0xd05c200c
8957 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO                                                     0xd05c2010
8958 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI                                                     0xd05c2014
8959 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA                                                    0xd05c2018
8960 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL                                                     0xd05c201c
8961 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO                                                     0xd05c2020
8962 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI                                                     0xd05c2024
8963 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA                                                    0xd05c2028
8964 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL                                                     0xd05c202c
8965 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO                                                     0xd05c2030
8966 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI                                                     0xd05c2034
8967 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA                                                    0xd05c2038
8968 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL                                                     0xd05c203c
8969 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_PBA                                                               0xd05c3000
8970 
8971 
8972 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_SYSPFVFDEC
8973 // base address: 0xd0600000
8974 #define cfgBIF_BX_DEV0_EPF0_VF12_MM_INDEX                                                               0xd0600000
8975 #define cfgBIF_BX_DEV0_EPF0_VF12_MM_DATA                                                                0xd0600004
8976 #define cfgBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI                                                            0xd0600018
8977 
8978 
8979 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFPFVFDEC1
8980 // base address: 0xd0600000
8981 #define cfgRCC_DEV0_EPF0_VF12_RCC_ERR_LOG                                                               0xd0603694
8982 #define cfgRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN                                                      0xd0603780
8983 #define cfgRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE                                                        0xd060378c
8984 #define cfgRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED                                                       0xd0603790
8985 #define cfgRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER                                                   0xd0603794
8986 
8987 
8988 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_BIFPFVFDEC1
8989 // base address: 0xd0600000
8990 #define cfgBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS                                                         0xd060382c
8991 #define cfgBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG                                                     0xd0603830
8992 #define cfgBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0xd060384c
8993 #define cfgBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0xd0603850
8994 #define cfgBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL                                        0xd0603854
8995 #define cfgBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL                                           0xd0603858
8996 #define cfgBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0xd060385c
8997 #define cfgBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ                                                      0xd0603898
8998 #define cfgBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE                                                     0xd060389c
8999 #define cfgBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING                                                      0xd06038a0
9000 #define cfgBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS                                               0xd06038c8
9001 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0                                                 0xd0603958
9002 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1                                                 0xd060395c
9003 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2                                                 0xd0603960
9004 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3                                                 0xd0603964
9005 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0                                                 0xd0603968
9006 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1                                                 0xd060396c
9007 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2                                                 0xd0603970
9008 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3                                                 0xd0603974
9009 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL                                                        0xd0603978
9010 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL                                                       0xd060397c
9011 #define cfgBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX                                                       0xd0603980
9012 
9013 
9014 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFDEC2
9015 // base address: 0xd0600000
9016 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO                                                     0xd0642000
9017 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI                                                     0xd0642004
9018 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA                                                    0xd0642008
9019 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL                                                     0xd064200c
9020 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO                                                     0xd0642010
9021 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI                                                     0xd0642014
9022 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA                                                    0xd0642018
9023 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL                                                     0xd064201c
9024 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO                                                     0xd0642020
9025 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI                                                     0xd0642024
9026 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA                                                    0xd0642028
9027 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL                                                     0xd064202c
9028 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO                                                     0xd0642030
9029 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI                                                     0xd0642034
9030 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA                                                    0xd0642038
9031 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL                                                     0xd064203c
9032 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_PBA                                                               0xd0643000
9033 
9034 
9035 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_SYSPFVFDEC
9036 // base address: 0xd0680000
9037 #define cfgBIF_BX_DEV0_EPF0_VF13_MM_INDEX                                                               0xd0680000
9038 #define cfgBIF_BX_DEV0_EPF0_VF13_MM_DATA                                                                0xd0680004
9039 #define cfgBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI                                                            0xd0680018
9040 
9041 
9042 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFPFVFDEC1
9043 // base address: 0xd0680000
9044 #define cfgRCC_DEV0_EPF0_VF13_RCC_ERR_LOG                                                               0xd0683694
9045 #define cfgRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN                                                      0xd0683780
9046 #define cfgRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE                                                        0xd068378c
9047 #define cfgRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED                                                       0xd0683790
9048 #define cfgRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER                                                   0xd0683794
9049 
9050 
9051 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_BIFPFVFDEC1
9052 // base address: 0xd0680000
9053 #define cfgBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS                                                         0xd068382c
9054 #define cfgBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG                                                     0xd0683830
9055 #define cfgBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0xd068384c
9056 #define cfgBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0xd0683850
9057 #define cfgBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL                                        0xd0683854
9058 #define cfgBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL                                           0xd0683858
9059 #define cfgBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0xd068385c
9060 #define cfgBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ                                                      0xd0683898
9061 #define cfgBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE                                                     0xd068389c
9062 #define cfgBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING                                                      0xd06838a0
9063 #define cfgBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS                                               0xd06838c8
9064 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0                                                 0xd0683958
9065 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1                                                 0xd068395c
9066 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2                                                 0xd0683960
9067 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3                                                 0xd0683964
9068 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0                                                 0xd0683968
9069 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1                                                 0xd068396c
9070 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2                                                 0xd0683970
9071 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3                                                 0xd0683974
9072 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL                                                        0xd0683978
9073 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL                                                       0xd068397c
9074 #define cfgBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX                                                       0xd0683980
9075 
9076 
9077 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFDEC2
9078 // base address: 0xd0680000
9079 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO                                                     0xd06c2000
9080 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI                                                     0xd06c2004
9081 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA                                                    0xd06c2008
9082 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL                                                     0xd06c200c
9083 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO                                                     0xd06c2010
9084 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI                                                     0xd06c2014
9085 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA                                                    0xd06c2018
9086 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL                                                     0xd06c201c
9087 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO                                                     0xd06c2020
9088 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI                                                     0xd06c2024
9089 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA                                                    0xd06c2028
9090 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL                                                     0xd06c202c
9091 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO                                                     0xd06c2030
9092 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI                                                     0xd06c2034
9093 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA                                                    0xd06c2038
9094 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL                                                     0xd06c203c
9095 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_PBA                                                               0xd06c3000
9096 
9097 
9098 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_SYSPFVFDEC
9099 // base address: 0xd0700000
9100 #define cfgBIF_BX_DEV0_EPF0_VF14_MM_INDEX                                                               0xd0700000
9101 #define cfgBIF_BX_DEV0_EPF0_VF14_MM_DATA                                                                0xd0700004
9102 #define cfgBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI                                                            0xd0700018
9103 
9104 
9105 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFPFVFDEC1
9106 // base address: 0xd0700000
9107 #define cfgRCC_DEV0_EPF0_VF14_RCC_ERR_LOG                                                               0xd0703694
9108 #define cfgRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN                                                      0xd0703780
9109 #define cfgRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE                                                        0xd070378c
9110 #define cfgRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED                                                       0xd0703790
9111 #define cfgRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER                                                   0xd0703794
9112 
9113 
9114 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_BIFPFVFDEC1
9115 // base address: 0xd0700000
9116 #define cfgBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS                                                         0xd070382c
9117 #define cfgBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG                                                     0xd0703830
9118 #define cfgBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0xd070384c
9119 #define cfgBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0xd0703850
9120 #define cfgBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL                                        0xd0703854
9121 #define cfgBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL                                           0xd0703858
9122 #define cfgBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0xd070385c
9123 #define cfgBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ                                                      0xd0703898
9124 #define cfgBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE                                                     0xd070389c
9125 #define cfgBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING                                                      0xd07038a0
9126 #define cfgBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS                                               0xd07038c8
9127 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0                                                 0xd0703958
9128 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1                                                 0xd070395c
9129 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2                                                 0xd0703960
9130 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3                                                 0xd0703964
9131 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0                                                 0xd0703968
9132 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1                                                 0xd070396c
9133 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2                                                 0xd0703970
9134 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3                                                 0xd0703974
9135 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL                                                        0xd0703978
9136 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL                                                       0xd070397c
9137 #define cfgBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX                                                       0xd0703980
9138 
9139 
9140 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFDEC2
9141 // base address: 0xd0700000
9142 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO                                                     0xd0742000
9143 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI                                                     0xd0742004
9144 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA                                                    0xd0742008
9145 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL                                                     0xd074200c
9146 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO                                                     0xd0742010
9147 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI                                                     0xd0742014
9148 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA                                                    0xd0742018
9149 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL                                                     0xd074201c
9150 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO                                                     0xd0742020
9151 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI                                                     0xd0742024
9152 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA                                                    0xd0742028
9153 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL                                                     0xd074202c
9154 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO                                                     0xd0742030
9155 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI                                                     0xd0742034
9156 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA                                                    0xd0742038
9157 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL                                                     0xd074203c
9158 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_PBA                                                               0xd0743000
9159 
9160 
9161 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_SYSPFVFDEC
9162 // base address: 0xd0780000
9163 #define cfgBIF_BX_DEV0_EPF0_VF15_MM_INDEX                                                               0xd0780000
9164 #define cfgBIF_BX_DEV0_EPF0_VF15_MM_DATA                                                                0xd0780004
9165 #define cfgBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI                                                            0xd0780018
9166 
9167 
9168 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFPFVFDEC1
9169 // base address: 0xd0780000
9170 #define cfgRCC_DEV0_EPF0_VF15_RCC_ERR_LOG                                                               0xd0783694
9171 #define cfgRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN                                                      0xd0783780
9172 #define cfgRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE                                                        0xd078378c
9173 #define cfgRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED                                                       0xd0783790
9174 #define cfgRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER                                                   0xd0783794
9175 
9176 
9177 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_BIFPFVFDEC1
9178 // base address: 0xd0780000
9179 #define cfgBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS                                                         0xd078382c
9180 #define cfgBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG                                                     0xd0783830
9181 #define cfgBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0xd078384c
9182 #define cfgBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0xd0783850
9183 #define cfgBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL                                        0xd0783854
9184 #define cfgBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL                                           0xd0783858
9185 #define cfgBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0xd078385c
9186 #define cfgBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ                                                      0xd0783898
9187 #define cfgBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE                                                     0xd078389c
9188 #define cfgBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING                                                      0xd07838a0
9189 #define cfgBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS                                               0xd07838c8
9190 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0                                                 0xd0783958
9191 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1                                                 0xd078395c
9192 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2                                                 0xd0783960
9193 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3                                                 0xd0783964
9194 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0                                                 0xd0783968
9195 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1                                                 0xd078396c
9196 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2                                                 0xd0783970
9197 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3                                                 0xd0783974
9198 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL                                                        0xd0783978
9199 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL                                                       0xd078397c
9200 #define cfgBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX                                                       0xd0783980
9201 
9202 
9203 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFDEC2
9204 // base address: 0xd0780000
9205 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO                                                     0xd07c2000
9206 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI                                                     0xd07c2004
9207 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA                                                    0xd07c2008
9208 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL                                                     0xd07c200c
9209 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO                                                     0xd07c2010
9210 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI                                                     0xd07c2014
9211 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA                                                    0xd07c2018
9212 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL                                                     0xd07c201c
9213 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO                                                     0xd07c2020
9214 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI                                                     0xd07c2024
9215 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA                                                    0xd07c2028
9216 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL                                                     0xd07c202c
9217 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO                                                     0xd07c2030
9218 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI                                                     0xd07c2034
9219 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA                                                    0xd07c2038
9220 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL                                                     0xd07c203c
9221 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_PBA                                                               0xd07c3000
9222 
9223 
9224 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf16_SYSPFVFDEC
9225 // base address: 0xd0800000
9226 #define cfgBIF_BX_DEV0_EPF0_VF16_MM_INDEX                                                               0xd0800000
9227 #define cfgBIF_BX_DEV0_EPF0_VF16_MM_DATA                                                                0xd0800004
9228 #define cfgBIF_BX_DEV0_EPF0_VF16_MM_INDEX_HI                                                            0xd0800018
9229 
9230 
9231 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf16_BIFPFVFDEC1
9232 // base address: 0xd0800000
9233 #define cfgRCC_DEV0_EPF0_VF16_RCC_ERR_LOG                                                               0xd0803694
9234 #define cfgRCC_DEV0_EPF0_VF16_RCC_DOORBELL_APER_EN                                                      0xd0803780
9235 #define cfgRCC_DEV0_EPF0_VF16_RCC_CONFIG_MEMSIZE                                                        0xd080378c
9236 #define cfgRCC_DEV0_EPF0_VF16_RCC_CONFIG_RESERVED                                                       0xd0803790
9237 #define cfgRCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER                                                   0xd0803794
9238 
9239 
9240 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf16_BIFPFVFDEC1
9241 // base address: 0xd0800000
9242 #define cfgBIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS                                                         0xd080382c
9243 #define cfgBIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG                                                     0xd0803830
9244 #define cfgBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0xd080384c
9245 #define cfgBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0xd0803850
9246 #define cfgBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL                                        0xd0803854
9247 #define cfgBIF_BX_DEV0_EPF0_VF16_HDP_REG_COHERENCY_FLUSH_CNTL                                           0xd0803858
9248 #define cfgBIF_BX_DEV0_EPF0_VF16_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0xd080385c
9249 #define cfgBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ                                                      0xd0803898
9250 #define cfgBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE                                                     0xd080389c
9251 #define cfgBIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING                                                      0xd08038a0
9252 #define cfgBIF_BX_DEV0_EPF0_VF16_NBIF_GFX_ADDR_LUT_BYPASS                                               0xd08038c8
9253 #define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW0                                                 0xd0803958
9254 #define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW1                                                 0xd080395c
9255 #define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW2                                                 0xd0803960
9256 #define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW3                                                 0xd0803964
9257 #define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW0                                                 0xd0803968
9258 #define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW1                                                 0xd080396c
9259 #define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW2                                                 0xd0803970
9260 #define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW3                                                 0xd0803974
9261 #define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL                                                        0xd0803978
9262 #define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL                                                       0xd080397c
9263 #define cfgBIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX                                                       0xd0803980
9264 
9265 
9266 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf16_BIFDEC2
9267 // base address: 0xd0800000
9268 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_LO                                                     0xd0842000
9269 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_HI                                                     0xd0842004
9270 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_MSG_DATA                                                    0xd0842008
9271 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_CONTROL                                                     0xd084200c
9272 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_LO                                                     0xd0842010
9273 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_HI                                                     0xd0842014
9274 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_MSG_DATA                                                    0xd0842018
9275 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_CONTROL                                                     0xd084201c
9276 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_LO                                                     0xd0842020
9277 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_HI                                                     0xd0842024
9278 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_MSG_DATA                                                    0xd0842028
9279 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_CONTROL                                                     0xd084202c
9280 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_LO                                                     0xd0842030
9281 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_HI                                                     0xd0842034
9282 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_MSG_DATA                                                    0xd0842038
9283 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_CONTROL                                                     0xd084203c
9284 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_PBA                                                               0xd0843000
9285 
9286 
9287 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf17_SYSPFVFDEC
9288 // base address: 0xd0880000
9289 #define cfgBIF_BX_DEV0_EPF0_VF17_MM_INDEX                                                               0xd0880000
9290 #define cfgBIF_BX_DEV0_EPF0_VF17_MM_DATA                                                                0xd0880004
9291 #define cfgBIF_BX_DEV0_EPF0_VF17_MM_INDEX_HI                                                            0xd0880018
9292 
9293 
9294 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf17_BIFPFVFDEC1
9295 // base address: 0xd0880000
9296 #define cfgRCC_DEV0_EPF0_VF17_RCC_ERR_LOG                                                               0xd0883694
9297 #define cfgRCC_DEV0_EPF0_VF17_RCC_DOORBELL_APER_EN                                                      0xd0883780
9298 #define cfgRCC_DEV0_EPF0_VF17_RCC_CONFIG_MEMSIZE                                                        0xd088378c
9299 #define cfgRCC_DEV0_EPF0_VF17_RCC_CONFIG_RESERVED                                                       0xd0883790
9300 #define cfgRCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER                                                   0xd0883794
9301 
9302 
9303 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf17_BIFPFVFDEC1
9304 // base address: 0xd0880000
9305 #define cfgBIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS                                                         0xd088382c
9306 #define cfgBIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG                                                     0xd0883830
9307 #define cfgBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0xd088384c
9308 #define cfgBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0xd0883850
9309 #define cfgBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL                                        0xd0883854
9310 #define cfgBIF_BX_DEV0_EPF0_VF17_HDP_REG_COHERENCY_FLUSH_CNTL                                           0xd0883858
9311 #define cfgBIF_BX_DEV0_EPF0_VF17_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0xd088385c
9312 #define cfgBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ                                                      0xd0883898
9313 #define cfgBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE                                                     0xd088389c
9314 #define cfgBIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING                                                      0xd08838a0
9315 #define cfgBIF_BX_DEV0_EPF0_VF17_NBIF_GFX_ADDR_LUT_BYPASS                                               0xd08838c8
9316 #define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW0                                                 0xd0883958
9317 #define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW1                                                 0xd088395c
9318 #define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW2                                                 0xd0883960
9319 #define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW3                                                 0xd0883964
9320 #define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW0                                                 0xd0883968
9321 #define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW1                                                 0xd088396c
9322 #define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW2                                                 0xd0883970
9323 #define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW3                                                 0xd0883974
9324 #define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL                                                        0xd0883978
9325 #define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL                                                       0xd088397c
9326 #define cfgBIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX                                                       0xd0883980
9327 
9328 
9329 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf17_BIFDEC2
9330 // base address: 0xd0880000
9331 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_LO                                                     0xd08c2000
9332 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_HI                                                     0xd08c2004
9333 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_MSG_DATA                                                    0xd08c2008
9334 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_CONTROL                                                     0xd08c200c
9335 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_LO                                                     0xd08c2010
9336 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_HI                                                     0xd08c2014
9337 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_MSG_DATA                                                    0xd08c2018
9338 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_CONTROL                                                     0xd08c201c
9339 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_LO                                                     0xd08c2020
9340 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_HI                                                     0xd08c2024
9341 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_MSG_DATA                                                    0xd08c2028
9342 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_CONTROL                                                     0xd08c202c
9343 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_LO                                                     0xd08c2030
9344 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_HI                                                     0xd08c2034
9345 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_MSG_DATA                                                    0xd08c2038
9346 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_CONTROL                                                     0xd08c203c
9347 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_PBA                                                               0xd08c3000
9348 
9349 
9350 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf18_SYSPFVFDEC
9351 // base address: 0xd0900000
9352 #define cfgBIF_BX_DEV0_EPF0_VF18_MM_INDEX                                                               0xd0900000
9353 #define cfgBIF_BX_DEV0_EPF0_VF18_MM_DATA                                                                0xd0900004
9354 #define cfgBIF_BX_DEV0_EPF0_VF18_MM_INDEX_HI                                                            0xd0900018
9355 
9356 
9357 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf18_BIFPFVFDEC1
9358 // base address: 0xd0900000
9359 #define cfgRCC_DEV0_EPF0_VF18_RCC_ERR_LOG                                                               0xd0903694
9360 #define cfgRCC_DEV0_EPF0_VF18_RCC_DOORBELL_APER_EN                                                      0xd0903780
9361 #define cfgRCC_DEV0_EPF0_VF18_RCC_CONFIG_MEMSIZE                                                        0xd090378c
9362 #define cfgRCC_DEV0_EPF0_VF18_RCC_CONFIG_RESERVED                                                       0xd0903790
9363 #define cfgRCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER                                                   0xd0903794
9364 
9365 
9366 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf18_BIFPFVFDEC1
9367 // base address: 0xd0900000
9368 #define cfgBIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS                                                         0xd090382c
9369 #define cfgBIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG                                                     0xd0903830
9370 #define cfgBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0xd090384c
9371 #define cfgBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0xd0903850
9372 #define cfgBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL                                        0xd0903854
9373 #define cfgBIF_BX_DEV0_EPF0_VF18_HDP_REG_COHERENCY_FLUSH_CNTL                                           0xd0903858
9374 #define cfgBIF_BX_DEV0_EPF0_VF18_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0xd090385c
9375 #define cfgBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ                                                      0xd0903898
9376 #define cfgBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE                                                     0xd090389c
9377 #define cfgBIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING                                                      0xd09038a0
9378 #define cfgBIF_BX_DEV0_EPF0_VF18_NBIF_GFX_ADDR_LUT_BYPASS                                               0xd09038c8
9379 #define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW0                                                 0xd0903958
9380 #define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW1                                                 0xd090395c
9381 #define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW2                                                 0xd0903960
9382 #define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW3                                                 0xd0903964
9383 #define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW0                                                 0xd0903968
9384 #define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW1                                                 0xd090396c
9385 #define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW2                                                 0xd0903970
9386 #define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW3                                                 0xd0903974
9387 #define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL                                                        0xd0903978
9388 #define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL                                                       0xd090397c
9389 #define cfgBIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX                                                       0xd0903980
9390 
9391 
9392 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf18_BIFDEC2
9393 // base address: 0xd0900000
9394 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_LO                                                     0xd0942000
9395 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_HI                                                     0xd0942004
9396 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_MSG_DATA                                                    0xd0942008
9397 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_CONTROL                                                     0xd094200c
9398 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_LO                                                     0xd0942010
9399 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_HI                                                     0xd0942014
9400 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_MSG_DATA                                                    0xd0942018
9401 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_CONTROL                                                     0xd094201c
9402 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_LO                                                     0xd0942020
9403 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_HI                                                     0xd0942024
9404 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_MSG_DATA                                                    0xd0942028
9405 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_CONTROL                                                     0xd094202c
9406 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_LO                                                     0xd0942030
9407 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_HI                                                     0xd0942034
9408 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_MSG_DATA                                                    0xd0942038
9409 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_CONTROL                                                     0xd094203c
9410 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_PBA                                                               0xd0943000
9411 
9412 
9413 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf19_SYSPFVFDEC
9414 // base address: 0xd0980000
9415 #define cfgBIF_BX_DEV0_EPF0_VF19_MM_INDEX                                                               0xd0980000
9416 #define cfgBIF_BX_DEV0_EPF0_VF19_MM_DATA                                                                0xd0980004
9417 #define cfgBIF_BX_DEV0_EPF0_VF19_MM_INDEX_HI                                                            0xd0980018
9418 
9419 
9420 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf19_BIFPFVFDEC1
9421 // base address: 0xd0980000
9422 #define cfgRCC_DEV0_EPF0_VF19_RCC_ERR_LOG                                                               0xd0983694
9423 #define cfgRCC_DEV0_EPF0_VF19_RCC_DOORBELL_APER_EN                                                      0xd0983780
9424 #define cfgRCC_DEV0_EPF0_VF19_RCC_CONFIG_MEMSIZE                                                        0xd098378c
9425 #define cfgRCC_DEV0_EPF0_VF19_RCC_CONFIG_RESERVED                                                       0xd0983790
9426 #define cfgRCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER                                                   0xd0983794
9427 
9428 
9429 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf19_BIFPFVFDEC1
9430 // base address: 0xd0980000
9431 #define cfgBIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS                                                         0xd098382c
9432 #define cfgBIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG                                                     0xd0983830
9433 #define cfgBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0xd098384c
9434 #define cfgBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0xd0983850
9435 #define cfgBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL                                        0xd0983854
9436 #define cfgBIF_BX_DEV0_EPF0_VF19_HDP_REG_COHERENCY_FLUSH_CNTL                                           0xd0983858
9437 #define cfgBIF_BX_DEV0_EPF0_VF19_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0xd098385c
9438 #define cfgBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ                                                      0xd0983898
9439 #define cfgBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE                                                     0xd098389c
9440 #define cfgBIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING                                                      0xd09838a0
9441 #define cfgBIF_BX_DEV0_EPF0_VF19_NBIF_GFX_ADDR_LUT_BYPASS                                               0xd09838c8
9442 #define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW0                                                 0xd0983958
9443 #define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW1                                                 0xd098395c
9444 #define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW2                                                 0xd0983960
9445 #define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW3                                                 0xd0983964
9446 #define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW0                                                 0xd0983968
9447 #define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW1                                                 0xd098396c
9448 #define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW2                                                 0xd0983970
9449 #define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW3                                                 0xd0983974
9450 #define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL                                                        0xd0983978
9451 #define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL                                                       0xd098397c
9452 #define cfgBIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX                                                       0xd0983980
9453 
9454 
9455 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf19_BIFDEC2
9456 // base address: 0xd0980000
9457 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_LO                                                     0xd09c2000
9458 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_HI                                                     0xd09c2004
9459 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_MSG_DATA                                                    0xd09c2008
9460 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_CONTROL                                                     0xd09c200c
9461 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_LO                                                     0xd09c2010
9462 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_HI                                                     0xd09c2014
9463 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_MSG_DATA                                                    0xd09c2018
9464 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_CONTROL                                                     0xd09c201c
9465 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_LO                                                     0xd09c2020
9466 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_HI                                                     0xd09c2024
9467 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_MSG_DATA                                                    0xd09c2028
9468 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_CONTROL                                                     0xd09c202c
9469 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_LO                                                     0xd09c2030
9470 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_HI                                                     0xd09c2034
9471 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_MSG_DATA                                                    0xd09c2038
9472 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_CONTROL                                                     0xd09c203c
9473 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_PBA                                                               0xd09c3000
9474 
9475 
9476 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf20_SYSPFVFDEC
9477 // base address: 0xd0a00000
9478 #define cfgBIF_BX_DEV0_EPF0_VF20_MM_INDEX                                                               0xd0a00000
9479 #define cfgBIF_BX_DEV0_EPF0_VF20_MM_DATA                                                                0xd0a00004
9480 #define cfgBIF_BX_DEV0_EPF0_VF20_MM_INDEX_HI                                                            0xd0a00018
9481 
9482 
9483 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf20_BIFPFVFDEC1
9484 // base address: 0xd0a00000
9485 #define cfgRCC_DEV0_EPF0_VF20_RCC_ERR_LOG                                                               0xd0a03694
9486 #define cfgRCC_DEV0_EPF0_VF20_RCC_DOORBELL_APER_EN                                                      0xd0a03780
9487 #define cfgRCC_DEV0_EPF0_VF20_RCC_CONFIG_MEMSIZE                                                        0xd0a0378c
9488 #define cfgRCC_DEV0_EPF0_VF20_RCC_CONFIG_RESERVED                                                       0xd0a03790
9489 #define cfgRCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER                                                   0xd0a03794
9490 
9491 
9492 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf20_BIFPFVFDEC1
9493 // base address: 0xd0a00000
9494 #define cfgBIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS                                                         0xd0a0382c
9495 #define cfgBIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG                                                     0xd0a03830
9496 #define cfgBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0xd0a0384c
9497 #define cfgBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0xd0a03850
9498 #define cfgBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL                                        0xd0a03854
9499 #define cfgBIF_BX_DEV0_EPF0_VF20_HDP_REG_COHERENCY_FLUSH_CNTL                                           0xd0a03858
9500 #define cfgBIF_BX_DEV0_EPF0_VF20_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0xd0a0385c
9501 #define cfgBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ                                                      0xd0a03898
9502 #define cfgBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE                                                     0xd0a0389c
9503 #define cfgBIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING                                                      0xd0a038a0
9504 #define cfgBIF_BX_DEV0_EPF0_VF20_NBIF_GFX_ADDR_LUT_BYPASS                                               0xd0a038c8
9505 #define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW0                                                 0xd0a03958
9506 #define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW1                                                 0xd0a0395c
9507 #define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW2                                                 0xd0a03960
9508 #define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW3                                                 0xd0a03964
9509 #define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW0                                                 0xd0a03968
9510 #define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW1                                                 0xd0a0396c
9511 #define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW2                                                 0xd0a03970
9512 #define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW3                                                 0xd0a03974
9513 #define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL                                                        0xd0a03978
9514 #define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL                                                       0xd0a0397c
9515 #define cfgBIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX                                                       0xd0a03980
9516 
9517 
9518 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf20_BIFDEC2
9519 // base address: 0xd0a00000
9520 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_LO                                                     0xd0a42000
9521 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_HI                                                     0xd0a42004
9522 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_MSG_DATA                                                    0xd0a42008
9523 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_CONTROL                                                     0xd0a4200c
9524 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_LO                                                     0xd0a42010
9525 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_HI                                                     0xd0a42014
9526 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_MSG_DATA                                                    0xd0a42018
9527 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_CONTROL                                                     0xd0a4201c
9528 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_LO                                                     0xd0a42020
9529 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_HI                                                     0xd0a42024
9530 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_MSG_DATA                                                    0xd0a42028
9531 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_CONTROL                                                     0xd0a4202c
9532 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_LO                                                     0xd0a42030
9533 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_HI                                                     0xd0a42034
9534 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_MSG_DATA                                                    0xd0a42038
9535 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_CONTROL                                                     0xd0a4203c
9536 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_PBA                                                               0xd0a43000
9537 
9538 
9539 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf21_SYSPFVFDEC
9540 // base address: 0xd0a80000
9541 #define cfgBIF_BX_DEV0_EPF0_VF21_MM_INDEX                                                               0xd0a80000
9542 #define cfgBIF_BX_DEV0_EPF0_VF21_MM_DATA                                                                0xd0a80004
9543 #define cfgBIF_BX_DEV0_EPF0_VF21_MM_INDEX_HI                                                            0xd0a80018
9544 
9545 
9546 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf21_BIFPFVFDEC1
9547 // base address: 0xd0a80000
9548 #define cfgRCC_DEV0_EPF0_VF21_RCC_ERR_LOG                                                               0xd0a83694
9549 #define cfgRCC_DEV0_EPF0_VF21_RCC_DOORBELL_APER_EN                                                      0xd0a83780
9550 #define cfgRCC_DEV0_EPF0_VF21_RCC_CONFIG_MEMSIZE                                                        0xd0a8378c
9551 #define cfgRCC_DEV0_EPF0_VF21_RCC_CONFIG_RESERVED                                                       0xd0a83790
9552 #define cfgRCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER                                                   0xd0a83794
9553 
9554 
9555 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf21_BIFPFVFDEC1
9556 // base address: 0xd0a80000
9557 #define cfgBIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS                                                         0xd0a8382c
9558 #define cfgBIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG                                                     0xd0a83830
9559 #define cfgBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0xd0a8384c
9560 #define cfgBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0xd0a83850
9561 #define cfgBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL                                        0xd0a83854
9562 #define cfgBIF_BX_DEV0_EPF0_VF21_HDP_REG_COHERENCY_FLUSH_CNTL                                           0xd0a83858
9563 #define cfgBIF_BX_DEV0_EPF0_VF21_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0xd0a8385c
9564 #define cfgBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ                                                      0xd0a83898
9565 #define cfgBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE                                                     0xd0a8389c
9566 #define cfgBIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING                                                      0xd0a838a0
9567 #define cfgBIF_BX_DEV0_EPF0_VF21_NBIF_GFX_ADDR_LUT_BYPASS                                               0xd0a838c8
9568 #define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW0                                                 0xd0a83958
9569 #define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW1                                                 0xd0a8395c
9570 #define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW2                                                 0xd0a83960
9571 #define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW3                                                 0xd0a83964
9572 #define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW0                                                 0xd0a83968
9573 #define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW1                                                 0xd0a8396c
9574 #define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW2                                                 0xd0a83970
9575 #define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW3                                                 0xd0a83974
9576 #define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL                                                        0xd0a83978
9577 #define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL                                                       0xd0a8397c
9578 #define cfgBIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX                                                       0xd0a83980
9579 
9580 
9581 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf21_BIFDEC2
9582 // base address: 0xd0a80000
9583 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_LO                                                     0xd0ac2000
9584 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_HI                                                     0xd0ac2004
9585 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_MSG_DATA                                                    0xd0ac2008
9586 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_CONTROL                                                     0xd0ac200c
9587 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_LO                                                     0xd0ac2010
9588 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_HI                                                     0xd0ac2014
9589 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_MSG_DATA                                                    0xd0ac2018
9590 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_CONTROL                                                     0xd0ac201c
9591 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_LO                                                     0xd0ac2020
9592 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_HI                                                     0xd0ac2024
9593 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_MSG_DATA                                                    0xd0ac2028
9594 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_CONTROL                                                     0xd0ac202c
9595 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_LO                                                     0xd0ac2030
9596 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_HI                                                     0xd0ac2034
9597 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_MSG_DATA                                                    0xd0ac2038
9598 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_CONTROL                                                     0xd0ac203c
9599 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_PBA                                                               0xd0ac3000
9600 
9601 
9602 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf22_SYSPFVFDEC
9603 // base address: 0xd0b00000
9604 #define cfgBIF_BX_DEV0_EPF0_VF22_MM_INDEX                                                               0xd0b00000
9605 #define cfgBIF_BX_DEV0_EPF0_VF22_MM_DATA                                                                0xd0b00004
9606 #define cfgBIF_BX_DEV0_EPF0_VF22_MM_INDEX_HI                                                            0xd0b00018
9607 
9608 
9609 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf22_BIFPFVFDEC1
9610 // base address: 0xd0b00000
9611 #define cfgRCC_DEV0_EPF0_VF22_RCC_ERR_LOG                                                               0xd0b03694
9612 #define cfgRCC_DEV0_EPF0_VF22_RCC_DOORBELL_APER_EN                                                      0xd0b03780
9613 #define cfgRCC_DEV0_EPF0_VF22_RCC_CONFIG_MEMSIZE                                                        0xd0b0378c
9614 #define cfgRCC_DEV0_EPF0_VF22_RCC_CONFIG_RESERVED                                                       0xd0b03790
9615 #define cfgRCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER                                                   0xd0b03794
9616 
9617 
9618 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf22_BIFPFVFDEC1
9619 // base address: 0xd0b00000
9620 #define cfgBIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS                                                         0xd0b0382c
9621 #define cfgBIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG                                                     0xd0b03830
9622 #define cfgBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0xd0b0384c
9623 #define cfgBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0xd0b03850
9624 #define cfgBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL                                        0xd0b03854
9625 #define cfgBIF_BX_DEV0_EPF0_VF22_HDP_REG_COHERENCY_FLUSH_CNTL                                           0xd0b03858
9626 #define cfgBIF_BX_DEV0_EPF0_VF22_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0xd0b0385c
9627 #define cfgBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ                                                      0xd0b03898
9628 #define cfgBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE                                                     0xd0b0389c
9629 #define cfgBIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING                                                      0xd0b038a0
9630 #define cfgBIF_BX_DEV0_EPF0_VF22_NBIF_GFX_ADDR_LUT_BYPASS                                               0xd0b038c8
9631 #define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW0                                                 0xd0b03958
9632 #define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW1                                                 0xd0b0395c
9633 #define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW2                                                 0xd0b03960
9634 #define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW3                                                 0xd0b03964
9635 #define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW0                                                 0xd0b03968
9636 #define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW1                                                 0xd0b0396c
9637 #define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW2                                                 0xd0b03970
9638 #define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW3                                                 0xd0b03974
9639 #define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL                                                        0xd0b03978
9640 #define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL                                                       0xd0b0397c
9641 #define cfgBIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX                                                       0xd0b03980
9642 
9643 
9644 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf22_BIFDEC2
9645 // base address: 0xd0b00000
9646 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_LO                                                     0xd0b42000
9647 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_HI                                                     0xd0b42004
9648 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_MSG_DATA                                                    0xd0b42008
9649 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_CONTROL                                                     0xd0b4200c
9650 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_LO                                                     0xd0b42010
9651 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_HI                                                     0xd0b42014
9652 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_MSG_DATA                                                    0xd0b42018
9653 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_CONTROL                                                     0xd0b4201c
9654 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_LO                                                     0xd0b42020
9655 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_HI                                                     0xd0b42024
9656 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_MSG_DATA                                                    0xd0b42028
9657 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_CONTROL                                                     0xd0b4202c
9658 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_LO                                                     0xd0b42030
9659 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_HI                                                     0xd0b42034
9660 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_MSG_DATA                                                    0xd0b42038
9661 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_CONTROL                                                     0xd0b4203c
9662 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_PBA                                                               0xd0b43000
9663 
9664 
9665 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf23_SYSPFVFDEC
9666 // base address: 0xd0b80000
9667 #define cfgBIF_BX_DEV0_EPF0_VF23_MM_INDEX                                                               0xd0b80000
9668 #define cfgBIF_BX_DEV0_EPF0_VF23_MM_DATA                                                                0xd0b80004
9669 #define cfgBIF_BX_DEV0_EPF0_VF23_MM_INDEX_HI                                                            0xd0b80018
9670 
9671 
9672 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf23_BIFPFVFDEC1
9673 // base address: 0xd0b80000
9674 #define cfgRCC_DEV0_EPF0_VF23_RCC_ERR_LOG                                                               0xd0b83694
9675 #define cfgRCC_DEV0_EPF0_VF23_RCC_DOORBELL_APER_EN                                                      0xd0b83780
9676 #define cfgRCC_DEV0_EPF0_VF23_RCC_CONFIG_MEMSIZE                                                        0xd0b8378c
9677 #define cfgRCC_DEV0_EPF0_VF23_RCC_CONFIG_RESERVED                                                       0xd0b83790
9678 #define cfgRCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER                                                   0xd0b83794
9679 
9680 
9681 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf23_BIFPFVFDEC1
9682 // base address: 0xd0b80000
9683 #define cfgBIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS                                                         0xd0b8382c
9684 #define cfgBIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG                                                     0xd0b83830
9685 #define cfgBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0xd0b8384c
9686 #define cfgBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0xd0b83850
9687 #define cfgBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL                                        0xd0b83854
9688 #define cfgBIF_BX_DEV0_EPF0_VF23_HDP_REG_COHERENCY_FLUSH_CNTL                                           0xd0b83858
9689 #define cfgBIF_BX_DEV0_EPF0_VF23_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0xd0b8385c
9690 #define cfgBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ                                                      0xd0b83898
9691 #define cfgBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE                                                     0xd0b8389c
9692 #define cfgBIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING                                                      0xd0b838a0
9693 #define cfgBIF_BX_DEV0_EPF0_VF23_NBIF_GFX_ADDR_LUT_BYPASS                                               0xd0b838c8
9694 #define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW0                                                 0xd0b83958
9695 #define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW1                                                 0xd0b8395c
9696 #define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW2                                                 0xd0b83960
9697 #define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW3                                                 0xd0b83964
9698 #define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW0                                                 0xd0b83968
9699 #define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW1                                                 0xd0b8396c
9700 #define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW2                                                 0xd0b83970
9701 #define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW3                                                 0xd0b83974
9702 #define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL                                                        0xd0b83978
9703 #define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL                                                       0xd0b8397c
9704 #define cfgBIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX                                                       0xd0b83980
9705 
9706 
9707 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf23_BIFDEC2
9708 // base address: 0xd0b80000
9709 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_LO                                                     0xd0bc2000
9710 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_HI                                                     0xd0bc2004
9711 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_MSG_DATA                                                    0xd0bc2008
9712 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_CONTROL                                                     0xd0bc200c
9713 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_LO                                                     0xd0bc2010
9714 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_HI                                                     0xd0bc2014
9715 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_MSG_DATA                                                    0xd0bc2018
9716 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_CONTROL                                                     0xd0bc201c
9717 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_LO                                                     0xd0bc2020
9718 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_HI                                                     0xd0bc2024
9719 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_MSG_DATA                                                    0xd0bc2028
9720 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_CONTROL                                                     0xd0bc202c
9721 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_LO                                                     0xd0bc2030
9722 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_HI                                                     0xd0bc2034
9723 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_MSG_DATA                                                    0xd0bc2038
9724 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_CONTROL                                                     0xd0bc203c
9725 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_PBA                                                               0xd0bc3000
9726 
9727 
9728 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf24_SYSPFVFDEC
9729 // base address: 0xd0c00000
9730 #define cfgBIF_BX_DEV0_EPF0_VF24_MM_INDEX                                                               0xd0c00000
9731 #define cfgBIF_BX_DEV0_EPF0_VF24_MM_DATA                                                                0xd0c00004
9732 #define cfgBIF_BX_DEV0_EPF0_VF24_MM_INDEX_HI                                                            0xd0c00018
9733 
9734 
9735 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf24_BIFPFVFDEC1
9736 // base address: 0xd0c00000
9737 #define cfgRCC_DEV0_EPF0_VF24_RCC_ERR_LOG                                                               0xd0c03694
9738 #define cfgRCC_DEV0_EPF0_VF24_RCC_DOORBELL_APER_EN                                                      0xd0c03780
9739 #define cfgRCC_DEV0_EPF0_VF24_RCC_CONFIG_MEMSIZE                                                        0xd0c0378c
9740 #define cfgRCC_DEV0_EPF0_VF24_RCC_CONFIG_RESERVED                                                       0xd0c03790
9741 #define cfgRCC_DEV0_EPF0_VF24_RCC_IOV_FUNC_IDENTIFIER                                                   0xd0c03794
9742 
9743 
9744 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf24_BIFPFVFDEC1
9745 // base address: 0xd0c00000
9746 #define cfgBIF_BX_DEV0_EPF0_VF24_BIF_BME_STATUS                                                         0xd0c0382c
9747 #define cfgBIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG                                                     0xd0c03830
9748 #define cfgBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0xd0c0384c
9749 #define cfgBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0xd0c03850
9750 #define cfgBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_CNTL                                        0xd0c03854
9751 #define cfgBIF_BX_DEV0_EPF0_VF24_HDP_REG_COHERENCY_FLUSH_CNTL                                           0xd0c03858
9752 #define cfgBIF_BX_DEV0_EPF0_VF24_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0xd0c0385c
9753 #define cfgBIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ                                                      0xd0c03898
9754 #define cfgBIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE                                                     0xd0c0389c
9755 #define cfgBIF_BX_DEV0_EPF0_VF24_BIF_TRANS_PENDING                                                      0xd0c038a0
9756 #define cfgBIF_BX_DEV0_EPF0_VF24_NBIF_GFX_ADDR_LUT_BYPASS                                               0xd0c038c8
9757 #define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW0                                                 0xd0c03958
9758 #define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW1                                                 0xd0c0395c
9759 #define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW2                                                 0xd0c03960
9760 #define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW3                                                 0xd0c03964
9761 #define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW0                                                 0xd0c03968
9762 #define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW1                                                 0xd0c0396c
9763 #define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW2                                                 0xd0c03970
9764 #define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW3                                                 0xd0c03974
9765 #define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL                                                        0xd0c03978
9766 #define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_INT_CNTL                                                       0xd0c0397c
9767 #define cfgBIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX                                                       0xd0c03980
9768 
9769 
9770 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf24_BIFDEC2
9771 // base address: 0xd0c00000
9772 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_LO                                                     0xd0c42000
9773 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_HI                                                     0xd0c42004
9774 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_MSG_DATA                                                    0xd0c42008
9775 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_CONTROL                                                     0xd0c4200c
9776 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_LO                                                     0xd0c42010
9777 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_HI                                                     0xd0c42014
9778 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_MSG_DATA                                                    0xd0c42018
9779 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_CONTROL                                                     0xd0c4201c
9780 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_LO                                                     0xd0c42020
9781 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_HI                                                     0xd0c42024
9782 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_MSG_DATA                                                    0xd0c42028
9783 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_CONTROL                                                     0xd0c4202c
9784 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_LO                                                     0xd0c42030
9785 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_HI                                                     0xd0c42034
9786 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_MSG_DATA                                                    0xd0c42038
9787 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_CONTROL                                                     0xd0c4203c
9788 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_PBA                                                               0xd0c43000
9789 
9790 
9791 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf25_SYSPFVFDEC
9792 // base address: 0xd0c80000
9793 #define cfgBIF_BX_DEV0_EPF0_VF25_MM_INDEX                                                               0xd0c80000
9794 #define cfgBIF_BX_DEV0_EPF0_VF25_MM_DATA                                                                0xd0c80004
9795 #define cfgBIF_BX_DEV0_EPF0_VF25_MM_INDEX_HI                                                            0xd0c80018
9796 
9797 
9798 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf25_BIFPFVFDEC1
9799 // base address: 0xd0c80000
9800 #define cfgRCC_DEV0_EPF0_VF25_RCC_ERR_LOG                                                               0xd0c83694
9801 #define cfgRCC_DEV0_EPF0_VF25_RCC_DOORBELL_APER_EN                                                      0xd0c83780
9802 #define cfgRCC_DEV0_EPF0_VF25_RCC_CONFIG_MEMSIZE                                                        0xd0c8378c
9803 #define cfgRCC_DEV0_EPF0_VF25_RCC_CONFIG_RESERVED                                                       0xd0c83790
9804 #define cfgRCC_DEV0_EPF0_VF25_RCC_IOV_FUNC_IDENTIFIER                                                   0xd0c83794
9805 
9806 
9807 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf25_BIFPFVFDEC1
9808 // base address: 0xd0c80000
9809 #define cfgBIF_BX_DEV0_EPF0_VF25_BIF_BME_STATUS                                                         0xd0c8382c
9810 #define cfgBIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG                                                     0xd0c83830
9811 #define cfgBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0xd0c8384c
9812 #define cfgBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0xd0c83850
9813 #define cfgBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_CNTL                                        0xd0c83854
9814 #define cfgBIF_BX_DEV0_EPF0_VF25_HDP_REG_COHERENCY_FLUSH_CNTL                                           0xd0c83858
9815 #define cfgBIF_BX_DEV0_EPF0_VF25_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0xd0c8385c
9816 #define cfgBIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ                                                      0xd0c83898
9817 #define cfgBIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE                                                     0xd0c8389c
9818 #define cfgBIF_BX_DEV0_EPF0_VF25_BIF_TRANS_PENDING                                                      0xd0c838a0
9819 #define cfgBIF_BX_DEV0_EPF0_VF25_NBIF_GFX_ADDR_LUT_BYPASS                                               0xd0c838c8
9820 #define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW0                                                 0xd0c83958
9821 #define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW1                                                 0xd0c8395c
9822 #define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW2                                                 0xd0c83960
9823 #define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW3                                                 0xd0c83964
9824 #define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW0                                                 0xd0c83968
9825 #define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW1                                                 0xd0c8396c
9826 #define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW2                                                 0xd0c83970
9827 #define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW3                                                 0xd0c83974
9828 #define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL                                                        0xd0c83978
9829 #define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_INT_CNTL                                                       0xd0c8397c
9830 #define cfgBIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX                                                       0xd0c83980
9831 
9832 
9833 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf25_BIFDEC2
9834 // base address: 0xd0c80000
9835 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_LO                                                     0xd0cc2000
9836 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_HI                                                     0xd0cc2004
9837 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_MSG_DATA                                                    0xd0cc2008
9838 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_CONTROL                                                     0xd0cc200c
9839 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_LO                                                     0xd0cc2010
9840 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_HI                                                     0xd0cc2014
9841 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_MSG_DATA                                                    0xd0cc2018
9842 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_CONTROL                                                     0xd0cc201c
9843 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_LO                                                     0xd0cc2020
9844 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_HI                                                     0xd0cc2024
9845 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_MSG_DATA                                                    0xd0cc2028
9846 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_CONTROL                                                     0xd0cc202c
9847 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_LO                                                     0xd0cc2030
9848 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_HI                                                     0xd0cc2034
9849 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_MSG_DATA                                                    0xd0cc2038
9850 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_CONTROL                                                     0xd0cc203c
9851 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_PBA                                                               0xd0cc3000
9852 
9853 
9854 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf26_SYSPFVFDEC
9855 // base address: 0xd0d00000
9856 #define cfgBIF_BX_DEV0_EPF0_VF26_MM_INDEX                                                               0xd0d00000
9857 #define cfgBIF_BX_DEV0_EPF0_VF26_MM_DATA                                                                0xd0d00004
9858 #define cfgBIF_BX_DEV0_EPF0_VF26_MM_INDEX_HI                                                            0xd0d00018
9859 
9860 
9861 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf26_BIFPFVFDEC1
9862 // base address: 0xd0d00000
9863 #define cfgRCC_DEV0_EPF0_VF26_RCC_ERR_LOG                                                               0xd0d03694
9864 #define cfgRCC_DEV0_EPF0_VF26_RCC_DOORBELL_APER_EN                                                      0xd0d03780
9865 #define cfgRCC_DEV0_EPF0_VF26_RCC_CONFIG_MEMSIZE                                                        0xd0d0378c
9866 #define cfgRCC_DEV0_EPF0_VF26_RCC_CONFIG_RESERVED                                                       0xd0d03790
9867 #define cfgRCC_DEV0_EPF0_VF26_RCC_IOV_FUNC_IDENTIFIER                                                   0xd0d03794
9868 
9869 
9870 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf26_BIFPFVFDEC1
9871 // base address: 0xd0d00000
9872 #define cfgBIF_BX_DEV0_EPF0_VF26_BIF_BME_STATUS                                                         0xd0d0382c
9873 #define cfgBIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG                                                     0xd0d03830
9874 #define cfgBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0xd0d0384c
9875 #define cfgBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0xd0d03850
9876 #define cfgBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_CNTL                                        0xd0d03854
9877 #define cfgBIF_BX_DEV0_EPF0_VF26_HDP_REG_COHERENCY_FLUSH_CNTL                                           0xd0d03858
9878 #define cfgBIF_BX_DEV0_EPF0_VF26_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0xd0d0385c
9879 #define cfgBIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ                                                      0xd0d03898
9880 #define cfgBIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE                                                     0xd0d0389c
9881 #define cfgBIF_BX_DEV0_EPF0_VF26_BIF_TRANS_PENDING                                                      0xd0d038a0
9882 #define cfgBIF_BX_DEV0_EPF0_VF26_NBIF_GFX_ADDR_LUT_BYPASS                                               0xd0d038c8
9883 #define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW0                                                 0xd0d03958
9884 #define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW1                                                 0xd0d0395c
9885 #define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW2                                                 0xd0d03960
9886 #define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW3                                                 0xd0d03964
9887 #define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW0                                                 0xd0d03968
9888 #define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW1                                                 0xd0d0396c
9889 #define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW2                                                 0xd0d03970
9890 #define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW3                                                 0xd0d03974
9891 #define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL                                                        0xd0d03978
9892 #define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_INT_CNTL                                                       0xd0d0397c
9893 #define cfgBIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX                                                       0xd0d03980
9894 
9895 
9896 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf26_BIFDEC2
9897 // base address: 0xd0d00000
9898 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_LO                                                     0xd0d42000
9899 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_HI                                                     0xd0d42004
9900 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_MSG_DATA                                                    0xd0d42008
9901 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_CONTROL                                                     0xd0d4200c
9902 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_LO                                                     0xd0d42010
9903 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_HI                                                     0xd0d42014
9904 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_MSG_DATA                                                    0xd0d42018
9905 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_CONTROL                                                     0xd0d4201c
9906 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_LO                                                     0xd0d42020
9907 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_HI                                                     0xd0d42024
9908 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_MSG_DATA                                                    0xd0d42028
9909 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_CONTROL                                                     0xd0d4202c
9910 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_LO                                                     0xd0d42030
9911 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_HI                                                     0xd0d42034
9912 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_MSG_DATA                                                    0xd0d42038
9913 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_CONTROL                                                     0xd0d4203c
9914 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_PBA                                                               0xd0d43000
9915 
9916 
9917 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf27_SYSPFVFDEC
9918 // base address: 0xd0d80000
9919 #define cfgBIF_BX_DEV0_EPF0_VF27_MM_INDEX                                                               0xd0d80000
9920 #define cfgBIF_BX_DEV0_EPF0_VF27_MM_DATA                                                                0xd0d80004
9921 #define cfgBIF_BX_DEV0_EPF0_VF27_MM_INDEX_HI                                                            0xd0d80018
9922 
9923 
9924 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf27_BIFPFVFDEC1
9925 // base address: 0xd0d80000
9926 #define cfgRCC_DEV0_EPF0_VF27_RCC_ERR_LOG                                                               0xd0d83694
9927 #define cfgRCC_DEV0_EPF0_VF27_RCC_DOORBELL_APER_EN                                                      0xd0d83780
9928 #define cfgRCC_DEV0_EPF0_VF27_RCC_CONFIG_MEMSIZE                                                        0xd0d8378c
9929 #define cfgRCC_DEV0_EPF0_VF27_RCC_CONFIG_RESERVED                                                       0xd0d83790
9930 #define cfgRCC_DEV0_EPF0_VF27_RCC_IOV_FUNC_IDENTIFIER                                                   0xd0d83794
9931 
9932 
9933 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf27_BIFPFVFDEC1
9934 // base address: 0xd0d80000
9935 #define cfgBIF_BX_DEV0_EPF0_VF27_BIF_BME_STATUS                                                         0xd0d8382c
9936 #define cfgBIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG                                                     0xd0d83830
9937 #define cfgBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0xd0d8384c
9938 #define cfgBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0xd0d83850
9939 #define cfgBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_CNTL                                        0xd0d83854
9940 #define cfgBIF_BX_DEV0_EPF0_VF27_HDP_REG_COHERENCY_FLUSH_CNTL                                           0xd0d83858
9941 #define cfgBIF_BX_DEV0_EPF0_VF27_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0xd0d8385c
9942 #define cfgBIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ                                                      0xd0d83898
9943 #define cfgBIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE                                                     0xd0d8389c
9944 #define cfgBIF_BX_DEV0_EPF0_VF27_BIF_TRANS_PENDING                                                      0xd0d838a0
9945 #define cfgBIF_BX_DEV0_EPF0_VF27_NBIF_GFX_ADDR_LUT_BYPASS                                               0xd0d838c8
9946 #define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW0                                                 0xd0d83958
9947 #define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW1                                                 0xd0d8395c
9948 #define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW2                                                 0xd0d83960
9949 #define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW3                                                 0xd0d83964
9950 #define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW0                                                 0xd0d83968
9951 #define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW1                                                 0xd0d8396c
9952 #define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW2                                                 0xd0d83970
9953 #define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW3                                                 0xd0d83974
9954 #define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL                                                        0xd0d83978
9955 #define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_INT_CNTL                                                       0xd0d8397c
9956 #define cfgBIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX                                                       0xd0d83980
9957 
9958 
9959 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf27_BIFDEC2
9960 // base address: 0xd0d80000
9961 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_LO                                                     0xd0dc2000
9962 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_HI                                                     0xd0dc2004
9963 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_MSG_DATA                                                    0xd0dc2008
9964 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_CONTROL                                                     0xd0dc200c
9965 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_LO                                                     0xd0dc2010
9966 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_HI                                                     0xd0dc2014
9967 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_MSG_DATA                                                    0xd0dc2018
9968 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_CONTROL                                                     0xd0dc201c
9969 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_LO                                                     0xd0dc2020
9970 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_HI                                                     0xd0dc2024
9971 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_MSG_DATA                                                    0xd0dc2028
9972 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_CONTROL                                                     0xd0dc202c
9973 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_LO                                                     0xd0dc2030
9974 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_HI                                                     0xd0dc2034
9975 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_MSG_DATA                                                    0xd0dc2038
9976 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_CONTROL                                                     0xd0dc203c
9977 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_PBA                                                               0xd0dc3000
9978 
9979 
9980 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf28_SYSPFVFDEC
9981 // base address: 0xd0e00000
9982 #define cfgBIF_BX_DEV0_EPF0_VF28_MM_INDEX                                                               0xd0e00000
9983 #define cfgBIF_BX_DEV0_EPF0_VF28_MM_DATA                                                                0xd0e00004
9984 #define cfgBIF_BX_DEV0_EPF0_VF28_MM_INDEX_HI                                                            0xd0e00018
9985 
9986 
9987 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf28_BIFPFVFDEC1
9988 // base address: 0xd0e00000
9989 #define cfgRCC_DEV0_EPF0_VF28_RCC_ERR_LOG                                                               0xd0e03694
9990 #define cfgRCC_DEV0_EPF0_VF28_RCC_DOORBELL_APER_EN                                                      0xd0e03780
9991 #define cfgRCC_DEV0_EPF0_VF28_RCC_CONFIG_MEMSIZE                                                        0xd0e0378c
9992 #define cfgRCC_DEV0_EPF0_VF28_RCC_CONFIG_RESERVED                                                       0xd0e03790
9993 #define cfgRCC_DEV0_EPF0_VF28_RCC_IOV_FUNC_IDENTIFIER                                                   0xd0e03794
9994 
9995 
9996 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf28_BIFPFVFDEC1
9997 // base address: 0xd0e00000
9998 #define cfgBIF_BX_DEV0_EPF0_VF28_BIF_BME_STATUS                                                         0xd0e0382c
9999 #define cfgBIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG                                                     0xd0e03830
10000 #define cfgBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0xd0e0384c
10001 #define cfgBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0xd0e03850
10002 #define cfgBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_CNTL                                        0xd0e03854
10003 #define cfgBIF_BX_DEV0_EPF0_VF28_HDP_REG_COHERENCY_FLUSH_CNTL                                           0xd0e03858
10004 #define cfgBIF_BX_DEV0_EPF0_VF28_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0xd0e0385c
10005 #define cfgBIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ                                                      0xd0e03898
10006 #define cfgBIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE                                                     0xd0e0389c
10007 #define cfgBIF_BX_DEV0_EPF0_VF28_BIF_TRANS_PENDING                                                      0xd0e038a0
10008 #define cfgBIF_BX_DEV0_EPF0_VF28_NBIF_GFX_ADDR_LUT_BYPASS                                               0xd0e038c8
10009 #define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW0                                                 0xd0e03958
10010 #define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW1                                                 0xd0e0395c
10011 #define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW2                                                 0xd0e03960
10012 #define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW3                                                 0xd0e03964
10013 #define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW0                                                 0xd0e03968
10014 #define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW1                                                 0xd0e0396c
10015 #define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW2                                                 0xd0e03970
10016 #define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW3                                                 0xd0e03974
10017 #define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL                                                        0xd0e03978
10018 #define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_INT_CNTL                                                       0xd0e0397c
10019 #define cfgBIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX                                                       0xd0e03980
10020 
10021 
10022 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf28_BIFDEC2
10023 // base address: 0xd0e00000
10024 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_LO                                                     0xd0e42000
10025 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_HI                                                     0xd0e42004
10026 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_MSG_DATA                                                    0xd0e42008
10027 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_CONTROL                                                     0xd0e4200c
10028 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_LO                                                     0xd0e42010
10029 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_HI                                                     0xd0e42014
10030 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_MSG_DATA                                                    0xd0e42018
10031 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_CONTROL                                                     0xd0e4201c
10032 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_LO                                                     0xd0e42020
10033 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_HI                                                     0xd0e42024
10034 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_MSG_DATA                                                    0xd0e42028
10035 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_CONTROL                                                     0xd0e4202c
10036 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_LO                                                     0xd0e42030
10037 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_HI                                                     0xd0e42034
10038 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_MSG_DATA                                                    0xd0e42038
10039 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_CONTROL                                                     0xd0e4203c
10040 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_PBA                                                               0xd0e43000
10041 
10042 
10043 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf29_SYSPFVFDEC
10044 // base address: 0xd0e80000
10045 #define cfgBIF_BX_DEV0_EPF0_VF29_MM_INDEX                                                               0xd0e80000
10046 #define cfgBIF_BX_DEV0_EPF0_VF29_MM_DATA                                                                0xd0e80004
10047 #define cfgBIF_BX_DEV0_EPF0_VF29_MM_INDEX_HI                                                            0xd0e80018
10048 
10049 
10050 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf29_BIFPFVFDEC1
10051 // base address: 0xd0e80000
10052 #define cfgRCC_DEV0_EPF0_VF29_RCC_ERR_LOG                                                               0xd0e83694
10053 #define cfgRCC_DEV0_EPF0_VF29_RCC_DOORBELL_APER_EN                                                      0xd0e83780
10054 #define cfgRCC_DEV0_EPF0_VF29_RCC_CONFIG_MEMSIZE                                                        0xd0e8378c
10055 #define cfgRCC_DEV0_EPF0_VF29_RCC_CONFIG_RESERVED                                                       0xd0e83790
10056 #define cfgRCC_DEV0_EPF0_VF29_RCC_IOV_FUNC_IDENTIFIER                                                   0xd0e83794
10057 
10058 
10059 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf29_BIFPFVFDEC1
10060 // base address: 0xd0e80000
10061 #define cfgBIF_BX_DEV0_EPF0_VF29_BIF_BME_STATUS                                                         0xd0e8382c
10062 #define cfgBIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG                                                     0xd0e83830
10063 #define cfgBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0xd0e8384c
10064 #define cfgBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0xd0e83850
10065 #define cfgBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_CNTL                                        0xd0e83854
10066 #define cfgBIF_BX_DEV0_EPF0_VF29_HDP_REG_COHERENCY_FLUSH_CNTL                                           0xd0e83858
10067 #define cfgBIF_BX_DEV0_EPF0_VF29_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0xd0e8385c
10068 #define cfgBIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ                                                      0xd0e83898
10069 #define cfgBIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE                                                     0xd0e8389c
10070 #define cfgBIF_BX_DEV0_EPF0_VF29_BIF_TRANS_PENDING                                                      0xd0e838a0
10071 #define cfgBIF_BX_DEV0_EPF0_VF29_NBIF_GFX_ADDR_LUT_BYPASS                                               0xd0e838c8
10072 #define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW0                                                 0xd0e83958
10073 #define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW1                                                 0xd0e8395c
10074 #define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW2                                                 0xd0e83960
10075 #define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW3                                                 0xd0e83964
10076 #define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW0                                                 0xd0e83968
10077 #define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW1                                                 0xd0e8396c
10078 #define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW2                                                 0xd0e83970
10079 #define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW3                                                 0xd0e83974
10080 #define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL                                                        0xd0e83978
10081 #define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_INT_CNTL                                                       0xd0e8397c
10082 #define cfgBIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX                                                       0xd0e83980
10083 
10084 
10085 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf29_BIFDEC2
10086 // base address: 0xd0e80000
10087 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_LO                                                     0xd0ec2000
10088 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_HI                                                     0xd0ec2004
10089 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_MSG_DATA                                                    0xd0ec2008
10090 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_CONTROL                                                     0xd0ec200c
10091 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_LO                                                     0xd0ec2010
10092 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_HI                                                     0xd0ec2014
10093 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_MSG_DATA                                                    0xd0ec2018
10094 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_CONTROL                                                     0xd0ec201c
10095 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_LO                                                     0xd0ec2020
10096 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_HI                                                     0xd0ec2024
10097 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_MSG_DATA                                                    0xd0ec2028
10098 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_CONTROL                                                     0xd0ec202c
10099 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_LO                                                     0xd0ec2030
10100 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_HI                                                     0xd0ec2034
10101 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_MSG_DATA                                                    0xd0ec2038
10102 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_CONTROL                                                     0xd0ec203c
10103 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_PBA                                                               0xd0ec3000
10104 
10105 
10106 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf30_SYSPFVFDEC
10107 // base address: 0xd0f00000
10108 #define cfgBIF_BX_DEV0_EPF0_VF30_MM_INDEX                                                               0xd0f00000
10109 #define cfgBIF_BX_DEV0_EPF0_VF30_MM_DATA                                                                0xd0f00004
10110 #define cfgBIF_BX_DEV0_EPF0_VF30_MM_INDEX_HI                                                            0xd0f00018
10111 
10112 
10113 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf30_BIFPFVFDEC1
10114 // base address: 0xd0f00000
10115 #define cfgRCC_DEV0_EPF0_VF30_RCC_ERR_LOG                                                               0xd0f03694
10116 #define cfgRCC_DEV0_EPF0_VF30_RCC_DOORBELL_APER_EN                                                      0xd0f03780
10117 #define cfgRCC_DEV0_EPF0_VF30_RCC_CONFIG_MEMSIZE                                                        0xd0f0378c
10118 #define cfgRCC_DEV0_EPF0_VF30_RCC_CONFIG_RESERVED                                                       0xd0f03790
10119 #define cfgRCC_DEV0_EPF0_VF30_RCC_IOV_FUNC_IDENTIFIER                                                   0xd0f03794
10120 
10121 
10122 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf30_BIFPFVFDEC1
10123 // base address: 0xd0f00000
10124 #define cfgBIF_BX_DEV0_EPF0_VF30_BIF_BME_STATUS                                                         0xd0f0382c
10125 #define cfgBIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG                                                     0xd0f03830
10126 #define cfgBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                   0xd0f0384c
10127 #define cfgBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                    0xd0f03850
10128 #define cfgBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_CNTL                                        0xd0f03854
10129 #define cfgBIF_BX_DEV0_EPF0_VF30_HDP_REG_COHERENCY_FLUSH_CNTL                                           0xd0f03858
10130 #define cfgBIF_BX_DEV0_EPF0_VF30_HDP_MEM_COHERENCY_FLUSH_CNTL                                           0xd0f0385c
10131 #define cfgBIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ                                                      0xd0f03898
10132 #define cfgBIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE                                                     0xd0f0389c
10133 #define cfgBIF_BX_DEV0_EPF0_VF30_BIF_TRANS_PENDING                                                      0xd0f038a0
10134 #define cfgBIF_BX_DEV0_EPF0_VF30_NBIF_GFX_ADDR_LUT_BYPASS                                               0xd0f038c8
10135 #define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW0                                                 0xd0f03958
10136 #define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW1                                                 0xd0f0395c
10137 #define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW2                                                 0xd0f03960
10138 #define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW3                                                 0xd0f03964
10139 #define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW0                                                 0xd0f03968
10140 #define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW1                                                 0xd0f0396c
10141 #define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW2                                                 0xd0f03970
10142 #define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW3                                                 0xd0f03974
10143 #define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL                                                        0xd0f03978
10144 #define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_INT_CNTL                                                       0xd0f0397c
10145 #define cfgBIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX                                                       0xd0f03980
10146 
10147 
10148 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf30_BIFDEC2
10149 // base address: 0xd0f00000
10150 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_LO                                                     0xd0f42000
10151 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_HI                                                     0xd0f42004
10152 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_MSG_DATA                                                    0xd0f42008
10153 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_CONTROL                                                     0xd0f4200c
10154 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_LO                                                     0xd0f42010
10155 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_HI                                                     0xd0f42014
10156 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_MSG_DATA                                                    0xd0f42018
10157 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_CONTROL                                                     0xd0f4201c
10158 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_LO                                                     0xd0f42020
10159 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_HI                                                     0xd0f42024
10160 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_MSG_DATA                                                    0xd0f42028
10161 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_CONTROL                                                     0xd0f4202c
10162 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_LO                                                     0xd0f42030
10163 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_HI                                                     0xd0f42034
10164 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_MSG_DATA                                                    0xd0f42038
10165 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_CONTROL                                                     0xd0f4203c
10166 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_PBA                                                               0xd0f43000
10167 
10168 
10169 // addressBlock: nbio_pcie0_pswuscfg0_cfgdecp
10170 // base address: 0xfffe00000000
10171 #define cfgPSWUSCFG0_1_VENDOR_ID                                                                        0xfffe00000000
10172 #define cfgPSWUSCFG0_1_DEVICE_ID                                                                        0xfffe00000002
10173 #define cfgPSWUSCFG0_1_COMMAND                                                                          0xfffe00000004
10174 #define cfgPSWUSCFG0_1_STATUS                                                                           0xfffe00000006
10175 #define cfgPSWUSCFG0_1_REVISION_ID                                                                      0xfffe00000008
10176 #define cfgPSWUSCFG0_1_PROG_INTERFACE                                                                   0xfffe00000009
10177 #define cfgPSWUSCFG0_1_SUB_CLASS                                                                        0xfffe0000000a
10178 #define cfgPSWUSCFG0_1_BASE_CLASS                                                                       0xfffe0000000b
10179 #define cfgPSWUSCFG0_1_CACHE_LINE                                                                       0xfffe0000000c
10180 #define cfgPSWUSCFG0_1_LATENCY                                                                          0xfffe0000000d
10181 #define cfgPSWUSCFG0_1_HEADER                                                                           0xfffe0000000e
10182 #define cfgPSWUSCFG0_1_BIST                                                                             0xfffe0000000f
10183 #define cfgPSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY                                                           0xfffe00000018
10184 #define cfgPSWUSCFG0_1_IO_BASE_LIMIT                                                                    0xfffe0000001c
10185 #define cfgPSWUSCFG0_1_SECONDARY_STATUS                                                                 0xfffe0000001e
10186 #define cfgPSWUSCFG0_1_MEM_BASE_LIMIT                                                                   0xfffe00000020
10187 #define cfgPSWUSCFG0_1_PREF_BASE_LIMIT                                                                  0xfffe00000024
10188 #define cfgPSWUSCFG0_1_PREF_BASE_UPPER                                                                  0xfffe00000028
10189 #define cfgPSWUSCFG0_1_PREF_LIMIT_UPPER                                                                 0xfffe0000002c
10190 #define cfgPSWUSCFG0_1_IO_BASE_LIMIT_HI                                                                 0xfffe00000030
10191 #define cfgPSWUSCFG0_1_CAP_PTR                                                                          0xfffe00000034
10192 #define cfgPSWUSCFG0_1_ROM_BASE_ADDR                                                                    0xfffe00000038
10193 #define cfgPSWUSCFG0_1_INTERRUPT_LINE                                                                   0xfffe0000003c
10194 #define cfgPSWUSCFG0_1_INTERRUPT_PIN                                                                    0xfffe0000003d
10195 #define cfgPSWUSCFG0_1_IRQ_BRIDGE_CNTL                                                                  0xfffe0000003e
10196 #define cfgPSWUSCFG0_1_EXT_BRIDGE_CNTL                                                                  0xfffe00000040
10197 #define cfgPSWUSCFG0_1_VENDOR_CAP_LIST                                                                  0xfffe00000048
10198 #define cfgPSWUSCFG0_1_ADAPTER_ID_W                                                                     0xfffe0000004c
10199 #define cfgPSWUSCFG0_1_PMI_CAP_LIST                                                                     0xfffe00000050
10200 #define cfgPSWUSCFG0_1_PMI_CAP                                                                          0xfffe00000052
10201 #define cfgPSWUSCFG0_1_PMI_STATUS_CNTL                                                                  0xfffe00000054
10202 #define cfgPSWUSCFG0_1_PCIE_CAP_LIST                                                                    0xfffe00000058
10203 #define cfgPSWUSCFG0_1_PCIE_CAP                                                                         0xfffe0000005a
10204 #define cfgPSWUSCFG0_1_DEVICE_CAP                                                                       0xfffe0000005c
10205 #define cfgPSWUSCFG0_1_DEVICE_CNTL                                                                      0xfffe00000060
10206 #define cfgPSWUSCFG0_1_DEVICE_STATUS                                                                    0xfffe00000062
10207 #define cfgPSWUSCFG0_1_LINK_CAP                                                                         0xfffe00000064
10208 #define cfgPSWUSCFG0_1_LINK_CNTL                                                                        0xfffe00000068
10209 #define cfgPSWUSCFG0_1_LINK_STATUS                                                                      0xfffe0000006a
10210 #define cfgPSWUSCFG0_1_DEVICE_CAP2                                                                      0xfffe0000007c
10211 #define cfgPSWUSCFG0_1_DEVICE_CNTL2                                                                     0xfffe00000080
10212 #define cfgPSWUSCFG0_1_DEVICE_STATUS2                                                                   0xfffe00000082
10213 #define cfgPSWUSCFG0_1_LINK_CAP2                                                                        0xfffe00000084
10214 #define cfgPSWUSCFG0_1_LINK_CNTL2                                                                       0xfffe00000088
10215 #define cfgPSWUSCFG0_1_LINK_STATUS2                                                                     0xfffe0000008a
10216 #define cfgPSWUSCFG0_1_MSI_CAP_LIST                                                                     0xfffe000000a0
10217 #define cfgPSWUSCFG0_1_MSI_MSG_CNTL                                                                     0xfffe000000a2
10218 #define cfgPSWUSCFG0_1_MSI_MSG_ADDR_LO                                                                  0xfffe000000a4
10219 #define cfgPSWUSCFG0_1_MSI_MSG_ADDR_HI                                                                  0xfffe000000a8
10220 #define cfgPSWUSCFG0_1_MSI_MSG_DATA                                                                     0xfffe000000a8
10221 #define cfgPSWUSCFG0_1_MSI_MSG_DATA_64                                                                  0xfffe000000ac
10222 #define cfgPSWUSCFG0_1_SSID_CAP_LIST                                                                    0xfffe000000c0
10223 #define cfgPSWUSCFG0_1_SSID_CAP                                                                         0xfffe000000c4
10224 #define cfgPSWUSCFG0_1_MSI_MAP_CAP_LIST                                                                 0xfffe000000c8
10225 #define cfgPSWUSCFG0_1_MSI_MAP_CAP                                                                      0xfffe000000ca
10226 #define cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                                0xfffe00000100
10227 #define cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR                                                         0xfffe00000104
10228 #define cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC1                                                            0xfffe00000108
10229 #define cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC2                                                            0xfffe0000010c
10230 #define cfgPSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST                                                             0xfffe00000110
10231 #define cfgPSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1                                                            0xfffe00000114
10232 #define cfgPSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2                                                            0xfffe00000118
10233 #define cfgPSWUSCFG0_1_PCIE_PORT_VC_CNTL                                                                0xfffe0000011c
10234 #define cfgPSWUSCFG0_1_PCIE_PORT_VC_STATUS                                                              0xfffe0000011e
10235 #define cfgPSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP                                                            0xfffe00000120
10236 #define cfgPSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL                                                           0xfffe00000124
10237 #define cfgPSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS                                                         0xfffe0000012a
10238 #define cfgPSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP                                                            0xfffe0000012c
10239 #define cfgPSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL                                                           0xfffe00000130
10240 #define cfgPSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS                                                         0xfffe00000136
10241 #define cfgPSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                                 0xfffe00000140
10242 #define cfgPSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW1                                                          0xfffe00000144
10243 #define cfgPSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW2                                                          0xfffe00000148
10244 #define cfgPSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                                    0xfffe00000150
10245 #define cfgPSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS                                                           0xfffe00000154
10246 #define cfgPSWUSCFG0_1_PCIE_UNCORR_ERR_MASK                                                             0xfffe00000158
10247 #define cfgPSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY                                                         0xfffe0000015c
10248 #define cfgPSWUSCFG0_1_PCIE_CORR_ERR_STATUS                                                             0xfffe00000160
10249 #define cfgPSWUSCFG0_1_PCIE_CORR_ERR_MASK                                                               0xfffe00000164
10250 #define cfgPSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL                                                            0xfffe00000168
10251 #define cfgPSWUSCFG0_1_PCIE_HDR_LOG0                                                                    0xfffe0000016c
10252 #define cfgPSWUSCFG0_1_PCIE_HDR_LOG1                                                                    0xfffe00000170
10253 #define cfgPSWUSCFG0_1_PCIE_HDR_LOG2                                                                    0xfffe00000174
10254 #define cfgPSWUSCFG0_1_PCIE_HDR_LOG3                                                                    0xfffe00000178
10255 #define cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG0                                                             0xfffe00000188
10256 #define cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG1                                                             0xfffe0000018c
10257 #define cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG2                                                             0xfffe00000190
10258 #define cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG3                                                             0xfffe00000194
10259 #define cfgPSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST                                                      0xfffe00000270
10260 #define cfgPSWUSCFG0_1_PCIE_LINK_CNTL3                                                                  0xfffe00000274
10261 #define cfgPSWUSCFG0_1_PCIE_LANE_ERROR_STATUS                                                           0xfffe00000278
10262 #define cfgPSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL                                                    0xfffe0000027c
10263 #define cfgPSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL                                                    0xfffe0000027e
10264 #define cfgPSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL                                                    0xfffe00000280
10265 #define cfgPSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL                                                    0xfffe00000282
10266 #define cfgPSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL                                                    0xfffe00000284
10267 #define cfgPSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL                                                    0xfffe00000286
10268 #define cfgPSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL                                                    0xfffe00000288
10269 #define cfgPSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL                                                    0xfffe0000028a
10270 #define cfgPSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL                                                    0xfffe0000028c
10271 #define cfgPSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL                                                    0xfffe0000028e
10272 #define cfgPSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL                                                   0xfffe00000290
10273 #define cfgPSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL                                                   0xfffe00000292
10274 #define cfgPSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL                                                   0xfffe00000294
10275 #define cfgPSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL                                                   0xfffe00000296
10276 #define cfgPSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL                                                   0xfffe00000298
10277 #define cfgPSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL                                                   0xfffe0000029a
10278 #define cfgPSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST                                                            0xfffe000002a0
10279 #define cfgPSWUSCFG0_1_PCIE_ACS_CAP                                                                     0xfffe000002a4
10280 #define cfgPSWUSCFG0_1_PCIE_ACS_CNTL                                                                    0xfffe000002a6
10281 #define cfgPSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST                                                             0xfffe000002f0
10282 #define cfgPSWUSCFG0_1_PCIE_MC_CAP                                                                      0xfffe000002f4
10283 #define cfgPSWUSCFG0_1_PCIE_MC_CNTL                                                                     0xfffe000002f6
10284 #define cfgPSWUSCFG0_1_PCIE_MC_ADDR0                                                                    0xfffe000002f8
10285 #define cfgPSWUSCFG0_1_PCIE_MC_ADDR1                                                                    0xfffe000002fc
10286 #define cfgPSWUSCFG0_1_PCIE_MC_RCV0                                                                     0xfffe00000300
10287 #define cfgPSWUSCFG0_1_PCIE_MC_RCV1                                                                     0xfffe00000304
10288 #define cfgPSWUSCFG0_1_PCIE_MC_BLOCK_ALL0                                                               0xfffe00000308
10289 #define cfgPSWUSCFG0_1_PCIE_MC_BLOCK_ALL1                                                               0xfffe0000030c
10290 #define cfgPSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_0                                                     0xfffe00000310
10291 #define cfgPSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_1                                                     0xfffe00000314
10292 #define cfgPSWUSCFG0_1_PCIE_MC_OVERLAY_BAR0                                                             0xfffe00000318
10293 #define cfgPSWUSCFG0_1_PCIE_MC_OVERLAY_BAR1                                                             0xfffe0000031c
10294 #define cfgPSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST                                                            0xfffe00000320
10295 #define cfgPSWUSCFG0_1_PCIE_LTR_CAP                                                                     0xfffe00000324
10296 #define cfgPSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST                                                            0xfffe00000328
10297 #define cfgPSWUSCFG0_1_PCIE_ARI_CAP                                                                     0xfffe0000032c
10298 #define cfgPSWUSCFG0_1_PCIE_ARI_CNTL                                                                    0xfffe0000032e
10299 #define cfgPSWUSCFG0_1_PCIE_L1_PM_SUB_CAP_LIST                                                          0xfffe00000370
10300 #define cfgPSWUSCFG0_1_PCIE_L1_PM_SUB_CAP                                                               0xfffe00000374
10301 #define cfgPSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL                                                              0xfffe00000378
10302 #define cfgPSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL2                                                             0xfffe0000037c
10303 #define cfgPSWUSCFG0_1_PCIE_ESM_CAP_LIST                                                                0xfffe000003c4
10304 #define cfgPSWUSCFG0_1_PCIE_ESM_HEADER_1                                                                0xfffe000003c8
10305 #define cfgPSWUSCFG0_1_PCIE_ESM_HEADER_2                                                                0xfffe000003cc
10306 #define cfgPSWUSCFG0_1_PCIE_ESM_STATUS                                                                  0xfffe000003ce
10307 #define cfgPSWUSCFG0_1_PCIE_ESM_CTRL                                                                    0xfffe000003d0
10308 #define cfgPSWUSCFG0_1_PCIE_ESM_CAP_1                                                                   0xfffe000003d4
10309 #define cfgPSWUSCFG0_1_PCIE_ESM_CAP_2                                                                   0xfffe000003d8
10310 #define cfgPSWUSCFG0_1_PCIE_ESM_CAP_3                                                                   0xfffe000003dc
10311 #define cfgPSWUSCFG0_1_PCIE_ESM_CAP_4                                                                   0xfffe000003e0
10312 #define cfgPSWUSCFG0_1_PCIE_ESM_CAP_5                                                                   0xfffe000003e4
10313 #define cfgPSWUSCFG0_1_PCIE_ESM_CAP_6                                                                   0xfffe000003e8
10314 #define cfgPSWUSCFG0_1_PCIE_ESM_CAP_7                                                                   0xfffe000003ec
10315 #define cfgPSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST                                                            0xfffe00000400
10316 #define cfgPSWUSCFG0_1_DATA_LINK_FEATURE_CAP                                                            0xfffe00000404
10317 #define cfgPSWUSCFG0_1_DATA_LINK_FEATURE_STATUS                                                         0xfffe00000408
10318 #define cfgPSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST                                                       0xfffe00000410
10319 #define cfgPSWUSCFG0_1_LINK_CAP_16GT                                                                    0xfffe00000414
10320 #define cfgPSWUSCFG0_1_LINK_CNTL_16GT                                                                   0xfffe00000418
10321 #define cfgPSWUSCFG0_1_LINK_STATUS_16GT                                                                 0xfffe0000041c
10322 #define cfgPSWUSCFG0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT                                                0xfffe00000420
10323 #define cfgPSWUSCFG0_1_RTM1_PARITY_MISMATCH_STATUS_16GT                                                 0xfffe00000424
10324 #define cfgPSWUSCFG0_1_RTM2_PARITY_MISMATCH_STATUS_16GT                                                 0xfffe00000428
10325 #define cfgPSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT                                                    0xfffe00000430
10326 #define cfgPSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT                                                    0xfffe00000431
10327 #define cfgPSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT                                                    0xfffe00000432
10328 #define cfgPSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT                                                    0xfffe00000433
10329 #define cfgPSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT                                                    0xfffe00000434
10330 #define cfgPSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT                                                    0xfffe00000435
10331 #define cfgPSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT                                                    0xfffe00000436
10332 #define cfgPSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT                                                    0xfffe00000437
10333 #define cfgPSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT                                                    0xfffe00000438
10334 #define cfgPSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT                                                    0xfffe00000439
10335 #define cfgPSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT                                                   0xfffe0000043a
10336 #define cfgPSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT                                                   0xfffe0000043b
10337 #define cfgPSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT                                                   0xfffe0000043c
10338 #define cfgPSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT                                                   0xfffe0000043d
10339 #define cfgPSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT                                                   0xfffe0000043e
10340 #define cfgPSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT                                                   0xfffe0000043f
10341 #define cfgPSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST                                                      0xfffe00000440
10342 #define cfgPSWUSCFG0_1_MARGINING_PORT_CAP                                                               0xfffe00000444
10343 #define cfgPSWUSCFG0_1_MARGINING_PORT_STATUS                                                            0xfffe00000446
10344 #define cfgPSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL                                                       0xfffe00000448
10345 #define cfgPSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS                                                     0xfffe0000044a
10346 #define cfgPSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL                                                       0xfffe0000044c
10347 #define cfgPSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS                                                     0xfffe0000044e
10348 #define cfgPSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL                                                       0xfffe00000450
10349 #define cfgPSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS                                                     0xfffe00000452
10350 #define cfgPSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL                                                       0xfffe00000454
10351 #define cfgPSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS                                                     0xfffe00000456
10352 #define cfgPSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL                                                       0xfffe00000458
10353 #define cfgPSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS                                                     0xfffe0000045a
10354 #define cfgPSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL                                                       0xfffe0000045c
10355 #define cfgPSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS                                                     0xfffe0000045e
10356 #define cfgPSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL                                                       0xfffe00000460
10357 #define cfgPSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS                                                     0xfffe00000462
10358 #define cfgPSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL                                                       0xfffe00000464
10359 #define cfgPSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS                                                     0xfffe00000466
10360 #define cfgPSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL                                                       0xfffe00000468
10361 #define cfgPSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS                                                     0xfffe0000046a
10362 #define cfgPSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL                                                       0xfffe0000046c
10363 #define cfgPSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS                                                     0xfffe0000046e
10364 #define cfgPSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL                                                      0xfffe00000470
10365 #define cfgPSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS                                                    0xfffe00000472
10366 #define cfgPSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL                                                      0xfffe00000474
10367 #define cfgPSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS                                                    0xfffe00000476
10368 #define cfgPSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL                                                      0xfffe00000478
10369 #define cfgPSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS                                                    0xfffe0000047a
10370 #define cfgPSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL                                                      0xfffe0000047c
10371 #define cfgPSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS                                                    0xfffe0000047e
10372 #define cfgPSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL                                                      0xfffe00000480
10373 #define cfgPSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS                                                    0xfffe00000482
10374 #define cfgPSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL                                                      0xfffe00000484
10375 #define cfgPSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS                                                    0xfffe00000486
10376 #define cfgPSWUSCFG0_1_PCIE_CCIX_CAP_LIST                                                               0xfffe00000488
10377 #define cfgPSWUSCFG0_1_PCIE_CCIX_HEADER_1                                                               0xfffe0000048c
10378 #define cfgPSWUSCFG0_1_PCIE_CCIX_HEADER_2                                                               0xfffe00000490
10379 #define cfgPSWUSCFG0_1_PCIE_CCIX_CAP                                                                    0xfffe00000492
10380 #define cfgPSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP                                                           0xfffe00000494
10381 #define cfgPSWUSCFG0_1_PCIE_CCIX_ESM_OPTL_CAP                                                           0xfffe00000498
10382 #define cfgPSWUSCFG0_1_PCIE_CCIX_ESM_STATUS                                                             0xfffe0000049c
10383 #define cfgPSWUSCFG0_1_PCIE_CCIX_ESM_CNTL                                                               0xfffe000004a0
10384 #define cfgPSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT                                                0xfffe000004a4
10385 #define cfgPSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT                                                0xfffe000004a5
10386 #define cfgPSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT                                                0xfffe000004a6
10387 #define cfgPSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT                                                0xfffe000004a7
10388 #define cfgPSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT                                                0xfffe000004a8
10389 #define cfgPSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT                                                0xfffe000004a9
10390 #define cfgPSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT                                                0xfffe000004aa
10391 #define cfgPSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT                                                0xfffe000004ab
10392 #define cfgPSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT                                                0xfffe000004ac
10393 #define cfgPSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT                                                0xfffe000004ad
10394 #define cfgPSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT                                               0xfffe000004ae
10395 #define cfgPSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT                                               0xfffe000004af
10396 #define cfgPSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT                                               0xfffe000004b0
10397 #define cfgPSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT                                               0xfffe000004b1
10398 #define cfgPSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT                                               0xfffe000004b2
10399 #define cfgPSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT                                               0xfffe000004b3
10400 #define cfgPSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT                                                0xfffe000004b4
10401 #define cfgPSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT                                                0xfffe000004b5
10402 #define cfgPSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT                                                0xfffe000004b6
10403 #define cfgPSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT                                                0xfffe000004b7
10404 #define cfgPSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT                                                0xfffe000004b8
10405 #define cfgPSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT                                                0xfffe000004b9
10406 #define cfgPSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT                                                0xfffe000004ba
10407 #define cfgPSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT                                                0xfffe000004bb
10408 #define cfgPSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT                                                0xfffe000004bc
10409 #define cfgPSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT                                                0xfffe000004bd
10410 #define cfgPSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT                                               0xfffe000004be
10411 #define cfgPSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT                                               0xfffe000004bf
10412 #define cfgPSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT                                               0xfffe000004c0
10413 #define cfgPSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT                                               0xfffe000004c1
10414 #define cfgPSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT                                               0xfffe000004c2
10415 #define cfgPSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT                                               0xfffe000004c3
10416 #define cfgPSWUSCFG0_1_PCIE_CCIX_TRANS_CAP                                                              0xfffe000004c4
10417 #define cfgPSWUSCFG0_1_PCIE_CCIX_TRANS_CNTL                                                             0xfffe000004c8
10418 
10419 
10420 // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC:1
10421 // base address: 0x0
10422 #define cfgBIF_BX_PF0_MM_INDEX                                                                          0x0000
10423 #define cfgBIF_BX_PF0_MM_DATA                                                                           0x0004
10424 #define cfgBIF_BX_PF0_MM_INDEX_HI                                                                       0x0018
10425 
10426 
10427 // addressBlock: nbio_nbif0_bif_swus_SUMDEC
10428 // base address: 0x100000
10429 #define cfgSUM_INDEX                                                                                    0x1000e0
10430 #define cfgSUM_DATA                                                                                     0x1000e4
10431 
10432 
10433 // addressBlock: nbio_nbif0_bif_cfg_dev0_swds_bifcfgdecp
10434 // base address: 0xfffe10100000
10435 #define cfgBIF_CFG_DEV0_SWDS1_VENDOR_ID                                                                 0xfffe10100000
10436 #define cfgBIF_CFG_DEV0_SWDS1_DEVICE_ID                                                                 0xfffe10100002
10437 #define cfgBIF_CFG_DEV0_SWDS1_COMMAND                                                                   0xfffe10100004
10438 #define cfgBIF_CFG_DEV0_SWDS1_STATUS                                                                    0xfffe10100006
10439 #define cfgBIF_CFG_DEV0_SWDS1_REVISION_ID                                                               0xfffe10100008
10440 #define cfgBIF_CFG_DEV0_SWDS1_PROG_INTERFACE                                                            0xfffe10100009
10441 #define cfgBIF_CFG_DEV0_SWDS1_SUB_CLASS                                                                 0xfffe1010000a
10442 #define cfgBIF_CFG_DEV0_SWDS1_BASE_CLASS                                                                0xfffe1010000b
10443 #define cfgBIF_CFG_DEV0_SWDS1_CACHE_LINE                                                                0xfffe1010000c
10444 #define cfgBIF_CFG_DEV0_SWDS1_LATENCY                                                                   0xfffe1010000d
10445 #define cfgBIF_CFG_DEV0_SWDS1_HEADER                                                                    0xfffe1010000e
10446 #define cfgBIF_CFG_DEV0_SWDS1_BIST                                                                      0xfffe1010000f
10447 #define cfgBIF_CFG_DEV0_SWDS1_BASE_ADDR_1                                                               0xfffe10100010
10448 #define cfgBIF_CFG_DEV0_SWDS1_BASE_ADDR_2                                                               0xfffe10100014
10449 #define cfgBIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY                                                    0xfffe10100018
10450 #define cfgBIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT                                                             0xfffe1010001c
10451 #define cfgBIF_CFG_DEV0_SWDS1_SECONDARY_STATUS                                                          0xfffe1010001e
10452 #define cfgBIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT                                                            0xfffe10100020
10453 #define cfgBIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT                                                           0xfffe10100024
10454 #define cfgBIF_CFG_DEV0_SWDS1_PREF_BASE_UPPER                                                           0xfffe10100028
10455 #define cfgBIF_CFG_DEV0_SWDS1_PREF_LIMIT_UPPER                                                          0xfffe1010002c
10456 #define cfgBIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_HI                                                          0xfffe10100030
10457 #define cfgBIF_CFG_DEV0_SWDS1_CAP_PTR                                                                   0xfffe10100034
10458 #define cfgBIF_CFG_DEV0_SWDS1_ROM_BASE_ADDR                                                             0xfffe10100038
10459 #define cfgBIF_CFG_DEV0_SWDS1_INTERRUPT_LINE                                                            0xfffe1010003c
10460 #define cfgBIF_CFG_DEV0_SWDS1_INTERRUPT_PIN                                                             0xfffe1010003d
10461 #define cfgBIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL                                                           0xfffe1010003e
10462 #define cfgBIF_CFG_DEV0_SWDS1_PMI_CAP_LIST                                                              0xfffe10100050
10463 #define cfgBIF_CFG_DEV0_SWDS1_PMI_CAP                                                                   0xfffe10100052
10464 #define cfgBIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL                                                           0xfffe10100054
10465 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_CAP_LIST                                                             0xfffe10100058
10466 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_CAP                                                                  0xfffe1010005a
10467 #define cfgBIF_CFG_DEV0_SWDS1_DEVICE_CAP                                                                0xfffe1010005c
10468 #define cfgBIF_CFG_DEV0_SWDS1_DEVICE_CNTL                                                               0xfffe10100060
10469 #define cfgBIF_CFG_DEV0_SWDS1_DEVICE_STATUS                                                             0xfffe10100062
10470 #define cfgBIF_CFG_DEV0_SWDS1_LINK_CAP                                                                  0xfffe10100064
10471 #define cfgBIF_CFG_DEV0_SWDS1_LINK_CNTL                                                                 0xfffe10100068
10472 #define cfgBIF_CFG_DEV0_SWDS1_LINK_STATUS                                                               0xfffe1010006a
10473 #define cfgBIF_CFG_DEV0_SWDS1_SLOT_CAP                                                                  0xfffe1010006c
10474 #define cfgBIF_CFG_DEV0_SWDS1_SLOT_CNTL                                                                 0xfffe10100070
10475 #define cfgBIF_CFG_DEV0_SWDS1_SLOT_STATUS                                                               0xfffe10100072
10476 #define cfgBIF_CFG_DEV0_SWDS1_DEVICE_CAP2                                                               0xfffe1010007c
10477 #define cfgBIF_CFG_DEV0_SWDS1_DEVICE_CNTL2                                                              0xfffe10100080
10478 #define cfgBIF_CFG_DEV0_SWDS1_DEVICE_STATUS2                                                            0xfffe10100082
10479 #define cfgBIF_CFG_DEV0_SWDS1_LINK_CAP2                                                                 0xfffe10100084
10480 #define cfgBIF_CFG_DEV0_SWDS1_LINK_CNTL2                                                                0xfffe10100088
10481 #define cfgBIF_CFG_DEV0_SWDS1_LINK_STATUS2                                                              0xfffe1010008a
10482 #define cfgBIF_CFG_DEV0_SWDS1_SLOT_CAP2                                                                 0xfffe1010008c
10483 #define cfgBIF_CFG_DEV0_SWDS1_SLOT_CNTL2                                                                0xfffe10100090
10484 #define cfgBIF_CFG_DEV0_SWDS1_SLOT_STATUS2                                                              0xfffe10100092
10485 #define cfgBIF_CFG_DEV0_SWDS1_MSI_CAP_LIST                                                              0xfffe101000a0
10486 #define cfgBIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL                                                              0xfffe101000a2
10487 #define cfgBIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_LO                                                           0xfffe101000a4
10488 #define cfgBIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_HI                                                           0xfffe101000a8
10489 #define cfgBIF_CFG_DEV0_SWDS1_MSI_MSG_DATA                                                              0xfffe101000a8
10490 #define cfgBIF_CFG_DEV0_SWDS1_MSI_MSG_DATA_64                                                           0xfffe101000ac
10491 #define cfgBIF_CFG_DEV0_SWDS1_SSID_CAP_LIST                                                             0xfffe101000c0
10492 #define cfgBIF_CFG_DEV0_SWDS1_SSID_CAP                                                                  0xfffe101000c4
10493 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                         0xfffe10100100
10494 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR                                                  0xfffe10100104
10495 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC1                                                     0xfffe10100108
10496 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC2                                                     0xfffe1010010c
10497 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST                                                      0xfffe10100110
10498 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1                                                     0xfffe10100114
10499 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG2                                                     0xfffe10100118
10500 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CNTL                                                         0xfffe1010011c
10501 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_STATUS                                                       0xfffe1010011e
10502 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP                                                     0xfffe10100120
10503 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL                                                    0xfffe10100124
10504 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_STATUS                                                  0xfffe1010012a
10505 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP                                                     0xfffe1010012c
10506 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL                                                    0xfffe10100130
10507 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_STATUS                                                  0xfffe10100136
10508 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                          0xfffe10100140
10509 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW1                                                   0xfffe10100144
10510 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW2                                                   0xfffe10100148
10511 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                             0xfffe10100150
10512 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS                                                    0xfffe10100154
10513 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK                                                      0xfffe10100158
10514 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY                                                  0xfffe1010015c
10515 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS                                                      0xfffe10100160
10516 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK                                                        0xfffe10100164
10517 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL                                                     0xfffe10100168
10518 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG0                                                             0xfffe1010016c
10519 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG1                                                             0xfffe10100170
10520 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG2                                                             0xfffe10100174
10521 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG3                                                             0xfffe10100178
10522 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG0                                                      0xfffe10100188
10523 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG1                                                      0xfffe1010018c
10524 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG2                                                      0xfffe10100190
10525 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG3                                                      0xfffe10100194
10526 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST                                               0xfffe10100270
10527 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3                                                           0xfffe10100274
10528 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_ERROR_STATUS                                                    0xfffe10100278
10529 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL                                             0xfffe1010027c
10530 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL                                             0xfffe1010027e
10531 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL                                             0xfffe10100280
10532 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL                                             0xfffe10100282
10533 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL                                             0xfffe10100284
10534 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL                                             0xfffe10100286
10535 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL                                             0xfffe10100288
10536 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL                                             0xfffe1010028a
10537 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL                                             0xfffe1010028c
10538 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL                                             0xfffe1010028e
10539 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL                                            0xfffe10100290
10540 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL                                            0xfffe10100292
10541 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL                                            0xfffe10100294
10542 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL                                            0xfffe10100296
10543 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL                                            0xfffe10100298
10544 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL                                            0xfffe1010029a
10545 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST                                                     0xfffe101002a0
10546 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP                                                              0xfffe101002a4
10547 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL                                                             0xfffe101002a6
10548 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_DLF_ENH_CAP_LIST                                                     0xfffe10100400
10549 #define cfgBIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_CAP                                                     0xfffe10100404
10550 #define cfgBIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_STATUS                                                  0xfffe10100408
10551 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_PHY_16GT_ENH_CAP_LIST                                                0xfffe10100410
10552 #define cfgBIF_CFG_DEV0_SWDS1_LINK_CAP_16GT                                                             0xfffe10100414
10553 #define cfgBIF_CFG_DEV0_SWDS1_LINK_CNTL_16GT                                                            0xfffe10100418
10554 #define cfgBIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT                                                          0xfffe1010041c
10555 #define cfgBIF_CFG_DEV0_SWDS1_LOCAL_PARITY_MISMATCH_STATUS_16GT                                         0xfffe10100420
10556 #define cfgBIF_CFG_DEV0_SWDS1_RTM1_PARITY_MISMATCH_STATUS_16GT                                          0xfffe10100424
10557 #define cfgBIF_CFG_DEV0_SWDS1_RTM2_PARITY_MISMATCH_STATUS_16GT                                          0xfffe10100428
10558 #define cfgBIF_CFG_DEV0_SWDS1_LANE_0_EQUALIZATION_CNTL_16GT                                             0xfffe10100430
10559 #define cfgBIF_CFG_DEV0_SWDS1_LANE_1_EQUALIZATION_CNTL_16GT                                             0xfffe10100431
10560 #define cfgBIF_CFG_DEV0_SWDS1_LANE_2_EQUALIZATION_CNTL_16GT                                             0xfffe10100432
10561 #define cfgBIF_CFG_DEV0_SWDS1_LANE_3_EQUALIZATION_CNTL_16GT                                             0xfffe10100433
10562 #define cfgBIF_CFG_DEV0_SWDS1_LANE_4_EQUALIZATION_CNTL_16GT                                             0xfffe10100434
10563 #define cfgBIF_CFG_DEV0_SWDS1_LANE_5_EQUALIZATION_CNTL_16GT                                             0xfffe10100435
10564 #define cfgBIF_CFG_DEV0_SWDS1_LANE_6_EQUALIZATION_CNTL_16GT                                             0xfffe10100436
10565 #define cfgBIF_CFG_DEV0_SWDS1_LANE_7_EQUALIZATION_CNTL_16GT                                             0xfffe10100437
10566 #define cfgBIF_CFG_DEV0_SWDS1_LANE_8_EQUALIZATION_CNTL_16GT                                             0xfffe10100438
10567 #define cfgBIF_CFG_DEV0_SWDS1_LANE_9_EQUALIZATION_CNTL_16GT                                             0xfffe10100439
10568 #define cfgBIF_CFG_DEV0_SWDS1_LANE_10_EQUALIZATION_CNTL_16GT                                            0xfffe1010043a
10569 #define cfgBIF_CFG_DEV0_SWDS1_LANE_11_EQUALIZATION_CNTL_16GT                                            0xfffe1010043b
10570 #define cfgBIF_CFG_DEV0_SWDS1_LANE_12_EQUALIZATION_CNTL_16GT                                            0xfffe1010043c
10571 #define cfgBIF_CFG_DEV0_SWDS1_LANE_13_EQUALIZATION_CNTL_16GT                                            0xfffe1010043d
10572 #define cfgBIF_CFG_DEV0_SWDS1_LANE_14_EQUALIZATION_CNTL_16GT                                            0xfffe1010043e
10573 #define cfgBIF_CFG_DEV0_SWDS1_LANE_15_EQUALIZATION_CNTL_16GT                                            0xfffe1010043f
10574 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_MARGINING_ENH_CAP_LIST                                               0xfffe10100440
10575 #define cfgBIF_CFG_DEV0_SWDS1_MARGINING_PORT_CAP                                                        0xfffe10100444
10576 #define cfgBIF_CFG_DEV0_SWDS1_MARGINING_PORT_STATUS                                                     0xfffe10100446
10577 #define cfgBIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_CNTL                                                0xfffe10100448
10578 #define cfgBIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_STATUS                                              0xfffe1010044a
10579 #define cfgBIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_CNTL                                                0xfffe1010044c
10580 #define cfgBIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_STATUS                                              0xfffe1010044e
10581 #define cfgBIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_CNTL                                                0xfffe10100450
10582 #define cfgBIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_STATUS                                              0xfffe10100452
10583 #define cfgBIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_CNTL                                                0xfffe10100454
10584 #define cfgBIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_STATUS                                              0xfffe10100456
10585 #define cfgBIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_CNTL                                                0xfffe10100458
10586 #define cfgBIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_STATUS                                              0xfffe1010045a
10587 #define cfgBIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_CNTL                                                0xfffe1010045c
10588 #define cfgBIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_STATUS                                              0xfffe1010045e
10589 #define cfgBIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_CNTL                                                0xfffe10100460
10590 #define cfgBIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_STATUS                                              0xfffe10100462
10591 #define cfgBIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_CNTL                                                0xfffe10100464
10592 #define cfgBIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_STATUS                                              0xfffe10100466
10593 #define cfgBIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_CNTL                                                0xfffe10100468
10594 #define cfgBIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_STATUS                                              0xfffe1010046a
10595 #define cfgBIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_CNTL                                                0xfffe1010046c
10596 #define cfgBIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_STATUS                                              0xfffe1010046e
10597 #define cfgBIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_CNTL                                               0xfffe10100470
10598 #define cfgBIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_STATUS                                             0xfffe10100472
10599 #define cfgBIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_CNTL                                               0xfffe10100474
10600 #define cfgBIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_STATUS                                             0xfffe10100476
10601 #define cfgBIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_CNTL                                               0xfffe10100478
10602 #define cfgBIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_STATUS                                             0xfffe1010047a
10603 #define cfgBIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_CNTL                                               0xfffe1010047c
10604 #define cfgBIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_STATUS                                             0xfffe1010047e
10605 #define cfgBIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_CNTL                                               0xfffe10100480
10606 #define cfgBIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_STATUS                                             0xfffe10100482
10607 #define cfgBIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_CNTL                                               0xfffe10100484
10608 #define cfgBIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_STATUS                                             0xfffe10100486
10609 
10610 
10611 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp
10612 // base address: 0xfffe10200000
10613 #define cfgBIF_CFG_DEV0_EPF0_1_VENDOR_ID                                                                0xfffe10200000
10614 #define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_ID                                                                0xfffe10200002
10615 #define cfgBIF_CFG_DEV0_EPF0_1_COMMAND                                                                  0xfffe10200004
10616 #define cfgBIF_CFG_DEV0_EPF0_1_STATUS                                                                   0xfffe10200006
10617 #define cfgBIF_CFG_DEV0_EPF0_1_REVISION_ID                                                              0xfffe10200008
10618 #define cfgBIF_CFG_DEV0_EPF0_1_PROG_INTERFACE                                                           0xfffe10200009
10619 #define cfgBIF_CFG_DEV0_EPF0_1_SUB_CLASS                                                                0xfffe1020000a
10620 #define cfgBIF_CFG_DEV0_EPF0_1_BASE_CLASS                                                               0xfffe1020000b
10621 #define cfgBIF_CFG_DEV0_EPF0_1_CACHE_LINE                                                               0xfffe1020000c
10622 #define cfgBIF_CFG_DEV0_EPF0_1_LATENCY                                                                  0xfffe1020000d
10623 #define cfgBIF_CFG_DEV0_EPF0_1_HEADER                                                                   0xfffe1020000e
10624 #define cfgBIF_CFG_DEV0_EPF0_1_BIST                                                                     0xfffe1020000f
10625 #define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_1                                                              0xfffe10200010
10626 #define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_2                                                              0xfffe10200014
10627 #define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_3                                                              0xfffe10200018
10628 #define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_4                                                              0xfffe1020001c
10629 #define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_5                                                              0xfffe10200020
10630 #define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_6                                                              0xfffe10200024
10631 #define cfgBIF_CFG_DEV0_EPF0_1_CARDBUS_CIS_PTR                                                          0xfffe10200028
10632 #define cfgBIF_CFG_DEV0_EPF0_1_ADAPTER_ID                                                               0xfffe1020002c
10633 #define cfgBIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR                                                            0xfffe10200030
10634 #define cfgBIF_CFG_DEV0_EPF0_1_CAP_PTR                                                                  0xfffe10200034
10635 #define cfgBIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE                                                           0xfffe1020003c
10636 #define cfgBIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN                                                            0xfffe1020003d
10637 #define cfgBIF_CFG_DEV0_EPF0_1_MIN_GRANT                                                                0xfffe1020003e
10638 #define cfgBIF_CFG_DEV0_EPF0_1_MAX_LATENCY                                                              0xfffe1020003f
10639 #define cfgBIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST                                                          0xfffe10200048
10640 #define cfgBIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W                                                             0xfffe1020004c
10641 #define cfgBIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST                                                             0xfffe10200050
10642 #define cfgBIF_CFG_DEV0_EPF0_1_PMI_CAP                                                                  0xfffe10200052
10643 #define cfgBIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL                                                          0xfffe10200054
10644 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST                                                            0xfffe10200064
10645 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_CAP                                                                 0xfffe10200066
10646 #define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CAP                                                               0xfffe10200068
10647 #define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL                                                              0xfffe1020006c
10648 #define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS                                                            0xfffe1020006e
10649 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP                                                                 0xfffe10200070
10650 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL                                                                0xfffe10200074
10651 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS                                                              0xfffe10200076
10652 #define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CAP2                                                              0xfffe10200088
10653 #define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2                                                             0xfffe1020008c
10654 #define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2                                                           0xfffe1020008e
10655 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP2                                                                0xfffe10200090
10656 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL2                                                               0xfffe10200094
10657 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS2                                                             0xfffe10200096
10658 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST                                                             0xfffe102000a0
10659 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL                                                             0xfffe102000a2
10660 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO                                                          0xfffe102000a4
10661 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI                                                          0xfffe102000a8
10662 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA                                                             0xfffe102000a8
10663 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_MASK                                                                 0xfffe102000ac
10664 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64                                                          0xfffe102000ac
10665 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_MASK_64                                                              0xfffe102000b0
10666 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_PENDING                                                              0xfffe102000b0
10667 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_PENDING_64                                                           0xfffe102000b4
10668 #define cfgBIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST                                                            0xfffe102000c0
10669 #define cfgBIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL                                                            0xfffe102000c2
10670 #define cfgBIF_CFG_DEV0_EPF0_1_MSIX_TABLE                                                               0xfffe102000c4
10671 #define cfgBIF_CFG_DEV0_EPF0_1_MSIX_PBA                                                                 0xfffe102000c8
10672 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                        0xfffe10200100
10673 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR                                                 0xfffe10200104
10674 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1                                                    0xfffe10200108
10675 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2                                                    0xfffe1020010c
10676 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST                                                     0xfffe10200110
10677 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1                                                    0xfffe10200114
10678 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2                                                    0xfffe10200118
10679 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL                                                        0xfffe1020011c
10680 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS                                                      0xfffe1020011e
10681 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP                                                    0xfffe10200120
10682 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL                                                   0xfffe10200124
10683 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS                                                 0xfffe1020012a
10684 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP                                                    0xfffe1020012c
10685 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL                                                   0xfffe10200130
10686 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS                                                 0xfffe10200136
10687 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                         0xfffe10200140
10688 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1                                                  0xfffe10200144
10689 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2                                                  0xfffe10200148
10690 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                            0xfffe10200150
10691 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS                                                   0xfffe10200154
10692 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK                                                     0xfffe10200158
10693 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY                                                 0xfffe1020015c
10694 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS                                                     0xfffe10200160
10695 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK                                                       0xfffe10200164
10696 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL                                                    0xfffe10200168
10697 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0                                                            0xfffe1020016c
10698 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1                                                            0xfffe10200170
10699 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2                                                            0xfffe10200174
10700 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3                                                            0xfffe10200178
10701 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0                                                     0xfffe10200188
10702 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1                                                     0xfffe1020018c
10703 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2                                                     0xfffe10200190
10704 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3                                                     0xfffe10200194
10705 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST                                                    0xfffe10200200
10706 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP                                                            0xfffe10200204
10707 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL                                                           0xfffe10200208
10708 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP                                                            0xfffe1020020c
10709 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL                                                           0xfffe10200210
10710 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP                                                            0xfffe10200214
10711 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL                                                           0xfffe10200218
10712 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP                                                            0xfffe1020021c
10713 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL                                                           0xfffe10200220
10714 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP                                                            0xfffe10200224
10715 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL                                                           0xfffe10200228
10716 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP                                                            0xfffe1020022c
10717 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL                                                           0xfffe10200230
10718 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST                                             0xfffe10200240
10719 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT                                              0xfffe10200244
10720 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA                                                     0xfffe10200248
10721 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP                                                      0xfffe1020024c
10722 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST                                                    0xfffe10200250
10723 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP                                                             0xfffe10200254
10724 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR                                               0xfffe10200258
10725 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS                                                          0xfffe1020025c
10726 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL                                                            0xfffe1020025e
10727 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                            0xfffe10200260
10728 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                            0xfffe10200261
10729 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                            0xfffe10200262
10730 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                            0xfffe10200263
10731 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                            0xfffe10200264
10732 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                            0xfffe10200265
10733 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                            0xfffe10200266
10734 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                            0xfffe10200267
10735 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST                                              0xfffe10200270
10736 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3                                                          0xfffe10200274
10737 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS                                                   0xfffe10200278
10738 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL                                            0xfffe1020027c
10739 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL                                            0xfffe1020027e
10740 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL                                            0xfffe10200280
10741 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL                                            0xfffe10200282
10742 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL                                            0xfffe10200284
10743 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL                                            0xfffe10200286
10744 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL                                            0xfffe10200288
10745 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL                                            0xfffe1020028a
10746 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL                                            0xfffe1020028c
10747 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL                                            0xfffe1020028e
10748 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL                                           0xfffe10200290
10749 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL                                           0xfffe10200292
10750 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL                                           0xfffe10200294
10751 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL                                           0xfffe10200296
10752 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL                                           0xfffe10200298
10753 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL                                           0xfffe1020029a
10754 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST                                                    0xfffe102002a0
10755 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP                                                             0xfffe102002a4
10756 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL                                                            0xfffe102002a6
10757 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST                                                    0xfffe102002b0
10758 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP                                                             0xfffe102002b4
10759 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL                                                            0xfffe102002b6
10760 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST                                               0xfffe102002c0
10761 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL                                                       0xfffe102002c4
10762 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS                                                     0xfffe102002c6
10763 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY                                          0xfffe102002c8
10764 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC                                             0xfffe102002cc
10765 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST                                                  0xfffe102002d0
10766 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP                                                           0xfffe102002d4
10767 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL                                                          0xfffe102002d6
10768 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST                                                     0xfffe102002f0
10769 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP                                                              0xfffe102002f4
10770 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL                                                             0xfffe102002f6
10771 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0                                                            0xfffe102002f8
10772 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1                                                            0xfffe102002fc
10773 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0                                                             0xfffe10200300
10774 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1                                                             0xfffe10200304
10775 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0                                                       0xfffe10200308
10776 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1                                                       0xfffe1020030c
10777 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0                                             0xfffe10200310
10778 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1                                             0xfffe10200314
10779 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST                                                    0xfffe10200320
10780 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP                                                             0xfffe10200324
10781 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST                                                    0xfffe10200328
10782 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP                                                             0xfffe1020032c
10783 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL                                                            0xfffe1020032e
10784 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST                                                  0xfffe10200330
10785 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP                                                           0xfffe10200334
10786 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL                                                       0xfffe10200338
10787 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS                                                        0xfffe1020033a
10788 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS                                                   0xfffe1020033c
10789 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS                                                     0xfffe1020033e
10790 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS                                                       0xfffe10200340
10791 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK                                                 0xfffe10200342
10792 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET                                               0xfffe10200344
10793 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE                                                     0xfffe10200346
10794 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID                                                  0xfffe1020034a
10795 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE                                           0xfffe1020034c
10796 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE                                              0xfffe10200350
10797 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0                                                0xfffe10200354
10798 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1                                                0xfffe10200358
10799 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2                                                0xfffe1020035c
10800 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3                                                0xfffe10200360
10801 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4                                                0xfffe10200364
10802 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5                                                0xfffe10200368
10803 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET                               0xfffe1020036c
10804 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST                                               0xfffe10200370
10805 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP                                                        0xfffe10200374
10806 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL                                                       0xfffe10200378
10807 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST                                                    0xfffe10200400
10808 #define cfgBIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP                                                    0xfffe10200404
10809 #define cfgBIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS                                                 0xfffe10200408
10810 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST                                               0xfffe10200410
10811 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP_16GT                                                            0xfffe10200414
10812 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL_16GT                                                           0xfffe10200418
10813 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT                                                         0xfffe1020041c
10814 #define cfgBIF_CFG_DEV0_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT                                        0xfffe10200420
10815 #define cfgBIF_CFG_DEV0_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT                                         0xfffe10200424
10816 #define cfgBIF_CFG_DEV0_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT                                         0xfffe10200428
10817 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT                                            0xfffe10200430
10818 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT                                            0xfffe10200431
10819 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT                                            0xfffe10200432
10820 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT                                            0xfffe10200433
10821 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT                                            0xfffe10200434
10822 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT                                            0xfffe10200435
10823 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT                                            0xfffe10200436
10824 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT                                            0xfffe10200437
10825 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT                                            0xfffe10200438
10826 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT                                            0xfffe10200439
10827 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT                                           0xfffe1020043a
10828 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT                                           0xfffe1020043b
10829 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT                                           0xfffe1020043c
10830 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT                                           0xfffe1020043d
10831 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT                                           0xfffe1020043e
10832 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT                                           0xfffe1020043f
10833 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST                                              0xfffe10200440
10834 #define cfgBIF_CFG_DEV0_EPF0_1_MARGINING_PORT_CAP                                                       0xfffe10200444
10835 #define cfgBIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS                                                    0xfffe10200446
10836 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL                                               0xfffe10200448
10837 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS                                             0xfffe1020044a
10838 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL                                               0xfffe1020044c
10839 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS                                             0xfffe1020044e
10840 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL                                               0xfffe10200450
10841 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS                                             0xfffe10200452
10842 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL                                               0xfffe10200454
10843 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS                                             0xfffe10200456
10844 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL                                               0xfffe10200458
10845 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS                                             0xfffe1020045a
10846 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL                                               0xfffe1020045c
10847 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS                                             0xfffe1020045e
10848 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL                                               0xfffe10200460
10849 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS                                             0xfffe10200462
10850 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL                                               0xfffe10200464
10851 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS                                             0xfffe10200466
10852 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL                                               0xfffe10200468
10853 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS                                             0xfffe1020046a
10854 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL                                               0xfffe1020046c
10855 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS                                             0xfffe1020046e
10856 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL                                              0xfffe10200470
10857 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS                                            0xfffe10200472
10858 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL                                              0xfffe10200474
10859 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS                                            0xfffe10200476
10860 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL                                              0xfffe10200478
10861 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS                                            0xfffe1020047a
10862 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL                                              0xfffe1020047c
10863 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS                                            0xfffe1020047e
10864 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL                                              0xfffe10200480
10865 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS                                            0xfffe10200482
10866 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL                                              0xfffe10200484
10867 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS                                            0xfffe10200486
10868 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST                                          0xfffe102004c0
10869 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CAP                                                  0xfffe102004c4
10870 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL                                                 0xfffe102004c8
10871 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CAP                                                  0xfffe102004cc
10872 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL                                                 0xfffe102004d0
10873 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CAP                                                  0xfffe102004d4
10874 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL                                                 0xfffe102004d8
10875 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CAP                                                  0xfffe102004dc
10876 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL                                                 0xfffe102004e0
10877 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CAP                                                  0xfffe102004e4
10878 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL                                                 0xfffe102004e8
10879 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CAP                                                  0xfffe102004ec
10880 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL                                                 0xfffe102004f0
10881 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV                                 0xfffe10200500
10882 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV                                          0xfffe10200504
10883 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW                             0xfffe10200508
10884 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE                              0xfffe1020050c
10885 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS                              0xfffe10200510
10886 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL                            0xfffe10200514
10887 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0                            0xfffe10200518
10888 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1                            0xfffe1020051c
10889 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2                            0xfffe10200520
10890 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT                                  0xfffe10200524
10891 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB                                 0xfffe10200528
10892 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS                                  0xfffe1020052c
10893 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION                                   0xfffe10200530
10894 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE                     0xfffe10200534
10895 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB                                   0xfffe10200538
10896 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB                                   0xfffe1020053c
10897 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB                                   0xfffe10200540
10898 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB                                   0xfffe10200544
10899 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB                                   0xfffe10200548
10900 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB                                   0xfffe1020054c
10901 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB                                   0xfffe10200550
10902 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB                                   0xfffe10200554
10903 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB                                   0xfffe10200558
10904 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB                                   0xfffe1020055c
10905 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB                                  0xfffe10200560
10906 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB                                  0xfffe10200564
10907 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB                                  0xfffe10200568
10908 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB                                  0xfffe1020056c
10909 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB                                  0xfffe10200570
10910 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB                                  0xfffe10200574
10911 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB                                  0xfffe10200578
10912 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB                                  0xfffe1020057c
10913 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB                                  0xfffe10200580
10914 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB                                  0xfffe10200584
10915 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB                                  0xfffe10200588
10916 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB                                  0xfffe1020058c
10917 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB                                  0xfffe10200590
10918 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB                                  0xfffe10200594
10919 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB                                  0xfffe10200598
10920 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB                                  0xfffe1020059c
10921 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB                                  0xfffe102005a0
10922 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB                                  0xfffe102005a4
10923 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB                                  0xfffe102005a8
10924 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB                                  0xfffe102005ac
10925 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB                                  0xfffe102005b0
10926 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0                               0xfffe102005c0
10927 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1                               0xfffe102005c4
10928 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2                               0xfffe102005c8
10929 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3                               0xfffe102005cc
10930 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4                               0xfffe102005d0
10931 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5                               0xfffe102005d4
10932 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6                               0xfffe102005d8
10933 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7                               0xfffe102005dc
10934 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8                               0xfffe102005e0
10935 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0                               0xfffe102005f0
10936 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1                               0xfffe102005f4
10937 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2                               0xfffe102005f8
10938 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3                               0xfffe102005fc
10939 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4                               0xfffe10200600
10940 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5                               0xfffe10200604
10941 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6                               0xfffe10200608
10942 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7                               0xfffe1020060c
10943 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8                               0xfffe10200610
10944 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0                               0xfffe10200620
10945 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1                               0xfffe10200624
10946 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2                               0xfffe10200628
10947 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3                               0xfffe1020062c
10948 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4                               0xfffe10200630
10949 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5                               0xfffe10200634
10950 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6                               0xfffe10200638
10951 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7                               0xfffe1020063c
10952 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8                               0xfffe10200640
10953 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0                              0xfffe10200650
10954 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1                              0xfffe10200654
10955 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2                              0xfffe10200658
10956 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3                              0xfffe1020065c
10957 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4                              0xfffe10200660
10958 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5                              0xfffe10200664
10959 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6                              0xfffe10200668
10960 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7                              0xfffe1020066c
10961 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8                              0xfffe10200670
10962 
10963 
10964 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp
10965 // base address: 0xfffe10201000
10966 #define cfgBIF_CFG_DEV0_EPF1_1_VENDOR_ID                                                                0xfffe10201000
10967 #define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_ID                                                                0xfffe10201002
10968 #define cfgBIF_CFG_DEV0_EPF1_1_COMMAND                                                                  0xfffe10201004
10969 #define cfgBIF_CFG_DEV0_EPF1_1_STATUS                                                                   0xfffe10201006
10970 #define cfgBIF_CFG_DEV0_EPF1_1_REVISION_ID                                                              0xfffe10201008
10971 #define cfgBIF_CFG_DEV0_EPF1_1_PROG_INTERFACE                                                           0xfffe10201009
10972 #define cfgBIF_CFG_DEV0_EPF1_1_SUB_CLASS                                                                0xfffe1020100a
10973 #define cfgBIF_CFG_DEV0_EPF1_1_BASE_CLASS                                                               0xfffe1020100b
10974 #define cfgBIF_CFG_DEV0_EPF1_1_CACHE_LINE                                                               0xfffe1020100c
10975 #define cfgBIF_CFG_DEV0_EPF1_1_LATENCY                                                                  0xfffe1020100d
10976 #define cfgBIF_CFG_DEV0_EPF1_1_HEADER                                                                   0xfffe1020100e
10977 #define cfgBIF_CFG_DEV0_EPF1_1_BIST                                                                     0xfffe1020100f
10978 #define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_1                                                              0xfffe10201010
10979 #define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_2                                                              0xfffe10201014
10980 #define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_3                                                              0xfffe10201018
10981 #define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_4                                                              0xfffe1020101c
10982 #define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_5                                                              0xfffe10201020
10983 #define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_6                                                              0xfffe10201024
10984 #define cfgBIF_CFG_DEV0_EPF1_1_CARDBUS_CIS_PTR                                                          0xfffe10201028
10985 #define cfgBIF_CFG_DEV0_EPF1_1_ADAPTER_ID                                                               0xfffe1020102c
10986 #define cfgBIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR                                                            0xfffe10201030
10987 #define cfgBIF_CFG_DEV0_EPF1_1_CAP_PTR                                                                  0xfffe10201034
10988 #define cfgBIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE                                                           0xfffe1020103c
10989 #define cfgBIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN                                                            0xfffe1020103d
10990 #define cfgBIF_CFG_DEV0_EPF1_1_MIN_GRANT                                                                0xfffe1020103e
10991 #define cfgBIF_CFG_DEV0_EPF1_1_MAX_LATENCY                                                              0xfffe1020103f
10992 #define cfgBIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST                                                          0xfffe10201048
10993 #define cfgBIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W                                                             0xfffe1020104c
10994 #define cfgBIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST                                                             0xfffe10201050
10995 #define cfgBIF_CFG_DEV0_EPF1_1_PMI_CAP                                                                  0xfffe10201052
10996 #define cfgBIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL                                                          0xfffe10201054
10997 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST                                                            0xfffe10201064
10998 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_CAP                                                                 0xfffe10201066
10999 #define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CAP                                                               0xfffe10201068
11000 #define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL                                                              0xfffe1020106c
11001 #define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS                                                            0xfffe1020106e
11002 #define cfgBIF_CFG_DEV0_EPF1_1_LINK_CAP                                                                 0xfffe10201070
11003 #define cfgBIF_CFG_DEV0_EPF1_1_LINK_CNTL                                                                0xfffe10201074
11004 #define cfgBIF_CFG_DEV0_EPF1_1_LINK_STATUS                                                              0xfffe10201076
11005 #define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CAP2                                                              0xfffe10201088
11006 #define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2                                                             0xfffe1020108c
11007 #define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2                                                           0xfffe1020108e
11008 #define cfgBIF_CFG_DEV0_EPF1_1_LINK_CAP2                                                                0xfffe10201090
11009 #define cfgBIF_CFG_DEV0_EPF1_1_LINK_CNTL2                                                               0xfffe10201094
11010 #define cfgBIF_CFG_DEV0_EPF1_1_LINK_STATUS2                                                             0xfffe10201096
11011 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST                                                             0xfffe102010a0
11012 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL                                                             0xfffe102010a2
11013 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO                                                          0xfffe102010a4
11014 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI                                                          0xfffe102010a8
11015 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA                                                             0xfffe102010a8
11016 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_MASK                                                                 0xfffe102010ac
11017 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64                                                          0xfffe102010ac
11018 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_MASK_64                                                              0xfffe102010b0
11019 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_PENDING                                                              0xfffe102010b0
11020 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_PENDING_64                                                           0xfffe102010b4
11021 #define cfgBIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST                                                            0xfffe102010c0
11022 #define cfgBIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL                                                            0xfffe102010c2
11023 #define cfgBIF_CFG_DEV0_EPF1_1_MSIX_TABLE                                                               0xfffe102010c4
11024 #define cfgBIF_CFG_DEV0_EPF1_1_MSIX_PBA                                                                 0xfffe102010c8
11025 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                        0xfffe10201100
11026 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR                                                 0xfffe10201104
11027 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1                                                    0xfffe10201108
11028 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2                                                    0xfffe1020110c
11029 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST                                                     0xfffe10201110
11030 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1                                                    0xfffe10201114
11031 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2                                                    0xfffe10201118
11032 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL                                                        0xfffe1020111c
11033 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS                                                      0xfffe1020111e
11034 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP                                                    0xfffe10201120
11035 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL                                                   0xfffe10201124
11036 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS                                                 0xfffe1020112a
11037 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP                                                    0xfffe1020112c
11038 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL                                                   0xfffe10201130
11039 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS                                                 0xfffe10201136
11040 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                         0xfffe10201140
11041 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1                                                  0xfffe10201144
11042 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2                                                  0xfffe10201148
11043 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                            0xfffe10201150
11044 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS                                                   0xfffe10201154
11045 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK                                                     0xfffe10201158
11046 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY                                                 0xfffe1020115c
11047 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS                                                     0xfffe10201160
11048 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK                                                       0xfffe10201164
11049 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL                                                    0xfffe10201168
11050 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0                                                            0xfffe1020116c
11051 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1                                                            0xfffe10201170
11052 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2                                                            0xfffe10201174
11053 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3                                                            0xfffe10201178
11054 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0                                                     0xfffe10201188
11055 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1                                                     0xfffe1020118c
11056 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2                                                     0xfffe10201190
11057 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3                                                     0xfffe10201194
11058 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST                                                    0xfffe10201200
11059 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP                                                            0xfffe10201204
11060 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL                                                           0xfffe10201208
11061 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP                                                            0xfffe1020120c
11062 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL                                                           0xfffe10201210
11063 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP                                                            0xfffe10201214
11064 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL                                                           0xfffe10201218
11065 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP                                                            0xfffe1020121c
11066 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL                                                           0xfffe10201220
11067 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP                                                            0xfffe10201224
11068 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL                                                           0xfffe10201228
11069 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP                                                            0xfffe1020122c
11070 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL                                                           0xfffe10201230
11071 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST                                             0xfffe10201240
11072 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT                                              0xfffe10201244
11073 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA                                                     0xfffe10201248
11074 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP                                                      0xfffe1020124c
11075 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST                                                    0xfffe10201250
11076 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP                                                             0xfffe10201254
11077 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR                                               0xfffe10201258
11078 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS                                                          0xfffe1020125c
11079 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL                                                            0xfffe1020125e
11080 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                            0xfffe10201260
11081 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                            0xfffe10201261
11082 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                            0xfffe10201262
11083 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                            0xfffe10201263
11084 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                            0xfffe10201264
11085 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                            0xfffe10201265
11086 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                            0xfffe10201266
11087 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                            0xfffe10201267
11088 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST                                              0xfffe10201270
11089 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3                                                          0xfffe10201274
11090 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS                                                   0xfffe10201278
11091 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL                                            0xfffe1020127c
11092 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL                                            0xfffe1020127e
11093 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL                                            0xfffe10201280
11094 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL                                            0xfffe10201282
11095 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL                                            0xfffe10201284
11096 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL                                            0xfffe10201286
11097 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL                                            0xfffe10201288
11098 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL                                            0xfffe1020128a
11099 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL                                            0xfffe1020128c
11100 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL                                            0xfffe1020128e
11101 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL                                           0xfffe10201290
11102 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL                                           0xfffe10201292
11103 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL                                           0xfffe10201294
11104 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL                                           0xfffe10201296
11105 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL                                           0xfffe10201298
11106 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL                                           0xfffe1020129a
11107 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST                                                    0xfffe102012a0
11108 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP                                                             0xfffe102012a4
11109 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL                                                            0xfffe102012a6
11110 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST                                                    0xfffe102012b0
11111 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP                                                             0xfffe102012b4
11112 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL                                                            0xfffe102012b6
11113 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST                                               0xfffe102012c0
11114 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL                                                       0xfffe102012c4
11115 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS                                                     0xfffe102012c6
11116 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY                                          0xfffe102012c8
11117 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC                                             0xfffe102012cc
11118 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST                                                  0xfffe102012d0
11119 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP                                                           0xfffe102012d4
11120 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL                                                          0xfffe102012d6
11121 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST                                                     0xfffe102012f0
11122 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP                                                              0xfffe102012f4
11123 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL                                                             0xfffe102012f6
11124 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0                                                            0xfffe102012f8
11125 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1                                                            0xfffe102012fc
11126 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0                                                             0xfffe10201300
11127 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1                                                             0xfffe10201304
11128 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0                                                       0xfffe10201308
11129 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1                                                       0xfffe1020130c
11130 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0                                             0xfffe10201310
11131 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1                                             0xfffe10201314
11132 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST                                                    0xfffe10201320
11133 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP                                                             0xfffe10201324
11134 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST                                                    0xfffe10201328
11135 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP                                                             0xfffe1020132c
11136 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL                                                            0xfffe1020132e
11137 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST                                                  0xfffe10201330
11138 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP                                                           0xfffe10201334
11139 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL                                                       0xfffe10201338
11140 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS                                                        0xfffe1020133a
11141 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS                                                   0xfffe1020133c
11142 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS                                                     0xfffe1020133e
11143 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS                                                       0xfffe10201340
11144 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK                                                 0xfffe10201342
11145 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET                                               0xfffe10201344
11146 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE                                                     0xfffe10201346
11147 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID                                                  0xfffe1020134a
11148 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE                                           0xfffe1020134c
11149 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE                                              0xfffe10201350
11150 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0                                                0xfffe10201354
11151 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1                                                0xfffe10201358
11152 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2                                                0xfffe1020135c
11153 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3                                                0xfffe10201360
11154 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4                                                0xfffe10201364
11155 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5                                                0xfffe10201368
11156 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET                               0xfffe1020136c
11157 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST                                               0xfffe10201370
11158 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP                                                        0xfffe10201374
11159 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL                                                       0xfffe10201378
11160 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST                                                    0xfffe10201400
11161 #define cfgBIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_CAP                                                    0xfffe10201404
11162 #define cfgBIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_STATUS                                                 0xfffe10201408
11163 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST                                               0xfffe10201410
11164 #define cfgBIF_CFG_DEV0_EPF1_1_LINK_CAP_16GT                                                            0xfffe10201414
11165 #define cfgBIF_CFG_DEV0_EPF1_1_LINK_CNTL_16GT                                                           0xfffe10201418
11166 #define cfgBIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT                                                         0xfffe1020141c
11167 #define cfgBIF_CFG_DEV0_EPF1_1_LOCAL_PARITY_MISMATCH_STATUS_16GT                                        0xfffe10201420
11168 #define cfgBIF_CFG_DEV0_EPF1_1_RTM1_PARITY_MISMATCH_STATUS_16GT                                         0xfffe10201424
11169 #define cfgBIF_CFG_DEV0_EPF1_1_RTM2_PARITY_MISMATCH_STATUS_16GT                                         0xfffe10201428
11170 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_0_EQUALIZATION_CNTL_16GT                                            0xfffe10201430
11171 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_1_EQUALIZATION_CNTL_16GT                                            0xfffe10201431
11172 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_2_EQUALIZATION_CNTL_16GT                                            0xfffe10201432
11173 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_3_EQUALIZATION_CNTL_16GT                                            0xfffe10201433
11174 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_4_EQUALIZATION_CNTL_16GT                                            0xfffe10201434
11175 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_5_EQUALIZATION_CNTL_16GT                                            0xfffe10201435
11176 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_6_EQUALIZATION_CNTL_16GT                                            0xfffe10201436
11177 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_7_EQUALIZATION_CNTL_16GT                                            0xfffe10201437
11178 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_8_EQUALIZATION_CNTL_16GT                                            0xfffe10201438
11179 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_9_EQUALIZATION_CNTL_16GT                                            0xfffe10201439
11180 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_10_EQUALIZATION_CNTL_16GT                                           0xfffe1020143a
11181 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_11_EQUALIZATION_CNTL_16GT                                           0xfffe1020143b
11182 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_12_EQUALIZATION_CNTL_16GT                                           0xfffe1020143c
11183 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_13_EQUALIZATION_CNTL_16GT                                           0xfffe1020143d
11184 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_14_EQUALIZATION_CNTL_16GT                                           0xfffe1020143e
11185 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_15_EQUALIZATION_CNTL_16GT                                           0xfffe1020143f
11186 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST                                              0xfffe10201440
11187 #define cfgBIF_CFG_DEV0_EPF1_1_MARGINING_PORT_CAP                                                       0xfffe10201444
11188 #define cfgBIF_CFG_DEV0_EPF1_1_MARGINING_PORT_STATUS                                                    0xfffe10201446
11189 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL                                               0xfffe10201448
11190 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS                                             0xfffe1020144a
11191 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL                                               0xfffe1020144c
11192 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS                                             0xfffe1020144e
11193 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL                                               0xfffe10201450
11194 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS                                             0xfffe10201452
11195 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL                                               0xfffe10201454
11196 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS                                             0xfffe10201456
11197 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL                                               0xfffe10201458
11198 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS                                             0xfffe1020145a
11199 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL                                               0xfffe1020145c
11200 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS                                             0xfffe1020145e
11201 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL                                               0xfffe10201460
11202 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS                                             0xfffe10201462
11203 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL                                               0xfffe10201464
11204 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS                                             0xfffe10201466
11205 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL                                               0xfffe10201468
11206 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS                                             0xfffe1020146a
11207 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL                                               0xfffe1020146c
11208 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS                                             0xfffe1020146e
11209 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL                                              0xfffe10201470
11210 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS                                            0xfffe10201472
11211 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL                                              0xfffe10201474
11212 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS                                            0xfffe10201476
11213 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL                                              0xfffe10201478
11214 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS                                            0xfffe1020147a
11215 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL                                              0xfffe1020147c
11216 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS                                            0xfffe1020147e
11217 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL                                              0xfffe10201480
11218 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS                                            0xfffe10201482
11219 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL                                              0xfffe10201484
11220 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS                                            0xfffe10201486
11221 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST                                          0xfffe102014c0
11222 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CAP                                                  0xfffe102014c4
11223 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL                                                 0xfffe102014c8
11224 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CAP                                                  0xfffe102014cc
11225 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL                                                 0xfffe102014d0
11226 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CAP                                                  0xfffe102014d4
11227 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL                                                 0xfffe102014d8
11228 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CAP                                                  0xfffe102014dc
11229 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL                                                 0xfffe102014e0
11230 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CAP                                                  0xfffe102014e4
11231 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL                                                 0xfffe102014e8
11232 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CAP                                                  0xfffe102014ec
11233 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL                                                 0xfffe102014f0
11234 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV                                 0xfffe10201500
11235 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV                                          0xfffe10201504
11236 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW                             0xfffe10201508
11237 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE                              0xfffe1020150c
11238 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS                              0xfffe10201510
11239 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL                            0xfffe10201514
11240 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0                            0xfffe10201518
11241 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1                            0xfffe1020151c
11242 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2                            0xfffe10201520
11243 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT                                  0xfffe10201524
11244 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB                                 0xfffe10201528
11245 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS                                  0xfffe1020152c
11246 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION                                   0xfffe10201530
11247 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE                     0xfffe10201534
11248 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB                                   0xfffe10201538
11249 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB                                   0xfffe1020153c
11250 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB                                   0xfffe10201540
11251 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB                                   0xfffe10201544
11252 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB                                   0xfffe10201548
11253 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB                                   0xfffe1020154c
11254 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB                                   0xfffe10201550
11255 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB                                   0xfffe10201554
11256 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB                                   0xfffe10201558
11257 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB                                   0xfffe1020155c
11258 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB                                  0xfffe10201560
11259 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB                                  0xfffe10201564
11260 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB                                  0xfffe10201568
11261 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB                                  0xfffe1020156c
11262 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB                                  0xfffe10201570
11263 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB                                  0xfffe10201574
11264 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB                                  0xfffe10201578
11265 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB                                  0xfffe1020157c
11266 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB                                  0xfffe10201580
11267 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB                                  0xfffe10201584
11268 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB                                  0xfffe10201588
11269 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB                                  0xfffe1020158c
11270 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB                                  0xfffe10201590
11271 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB                                  0xfffe10201594
11272 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB                                  0xfffe10201598
11273 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB                                  0xfffe1020159c
11274 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB                                  0xfffe102015a0
11275 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB                                  0xfffe102015a4
11276 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB                                  0xfffe102015a8
11277 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB                                  0xfffe102015ac
11278 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB                                  0xfffe102015b0
11279 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0                               0xfffe102015c0
11280 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1                               0xfffe102015c4
11281 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2                               0xfffe102015c8
11282 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3                               0xfffe102015cc
11283 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4                               0xfffe102015d0
11284 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5                               0xfffe102015d4
11285 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6                               0xfffe102015d8
11286 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7                               0xfffe102015dc
11287 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8                               0xfffe102015e0
11288 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0                               0xfffe102015f0
11289 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1                               0xfffe102015f4
11290 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2                               0xfffe102015f8
11291 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3                               0xfffe102015fc
11292 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4                               0xfffe10201600
11293 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5                               0xfffe10201604
11294 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6                               0xfffe10201608
11295 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7                               0xfffe1020160c
11296 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8                               0xfffe10201610
11297 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0                               0xfffe10201620
11298 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1                               0xfffe10201624
11299 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2                               0xfffe10201628
11300 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3                               0xfffe1020162c
11301 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4                               0xfffe10201630
11302 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5                               0xfffe10201634
11303 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6                               0xfffe10201638
11304 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7                               0xfffe1020163c
11305 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8                               0xfffe10201640
11306 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0                              0xfffe10201650
11307 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1                              0xfffe10201654
11308 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2                              0xfffe10201658
11309 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3                              0xfffe1020165c
11310 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4                              0xfffe10201660
11311 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5                              0xfffe10201664
11312 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6                              0xfffe10201668
11313 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7                              0xfffe1020166c
11314 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8                              0xfffe10201670
11315 
11316 
11317 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp
11318 // base address: 0xfffe10202000
11319 #define cfgBIF_CFG_DEV0_EPF2_1_VENDOR_ID                                                                0xfffe10202000
11320 #define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_ID                                                                0xfffe10202002
11321 #define cfgBIF_CFG_DEV0_EPF2_1_COMMAND                                                                  0xfffe10202004
11322 #define cfgBIF_CFG_DEV0_EPF2_1_STATUS                                                                   0xfffe10202006
11323 #define cfgBIF_CFG_DEV0_EPF2_1_REVISION_ID                                                              0xfffe10202008
11324 #define cfgBIF_CFG_DEV0_EPF2_1_PROG_INTERFACE                                                           0xfffe10202009
11325 #define cfgBIF_CFG_DEV0_EPF2_1_SUB_CLASS                                                                0xfffe1020200a
11326 #define cfgBIF_CFG_DEV0_EPF2_1_BASE_CLASS                                                               0xfffe1020200b
11327 #define cfgBIF_CFG_DEV0_EPF2_1_CACHE_LINE                                                               0xfffe1020200c
11328 #define cfgBIF_CFG_DEV0_EPF2_1_LATENCY                                                                  0xfffe1020200d
11329 #define cfgBIF_CFG_DEV0_EPF2_1_HEADER                                                                   0xfffe1020200e
11330 #define cfgBIF_CFG_DEV0_EPF2_1_BIST                                                                     0xfffe1020200f
11331 #define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_1                                                              0xfffe10202010
11332 #define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_2                                                              0xfffe10202014
11333 #define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_3                                                              0xfffe10202018
11334 #define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_4                                                              0xfffe1020201c
11335 #define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_5                                                              0xfffe10202020
11336 #define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_6                                                              0xfffe10202024
11337 #define cfgBIF_CFG_DEV0_EPF2_1_CARDBUS_CIS_PTR                                                          0xfffe10202028
11338 #define cfgBIF_CFG_DEV0_EPF2_1_ADAPTER_ID                                                               0xfffe1020202c
11339 #define cfgBIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR                                                            0xfffe10202030
11340 #define cfgBIF_CFG_DEV0_EPF2_1_CAP_PTR                                                                  0xfffe10202034
11341 #define cfgBIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE                                                           0xfffe1020203c
11342 #define cfgBIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN                                                            0xfffe1020203d
11343 #define cfgBIF_CFG_DEV0_EPF2_1_MIN_GRANT                                                                0xfffe1020203e
11344 #define cfgBIF_CFG_DEV0_EPF2_1_MAX_LATENCY                                                              0xfffe1020203f
11345 #define cfgBIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST                                                          0xfffe10202048
11346 #define cfgBIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W                                                             0xfffe1020204c
11347 #define cfgBIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST                                                             0xfffe10202050
11348 #define cfgBIF_CFG_DEV0_EPF2_1_PMI_CAP                                                                  0xfffe10202052
11349 #define cfgBIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL                                                          0xfffe10202054
11350 #define cfgBIF_CFG_DEV0_EPF2_1_SBRN                                                                     0xfffe10202060
11351 #define cfgBIF_CFG_DEV0_EPF2_1_FLADJ                                                                    0xfffe10202061
11352 #define cfgBIF_CFG_DEV0_EPF2_1_DBESL_DBESLD                                                             0xfffe10202062
11353 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST                                                            0xfffe10202064
11354 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_CAP                                                                 0xfffe10202066
11355 #define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CAP                                                               0xfffe10202068
11356 #define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CNTL                                                              0xfffe1020206c
11357 #define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_STATUS                                                            0xfffe1020206e
11358 #define cfgBIF_CFG_DEV0_EPF2_1_LINK_CAP                                                                 0xfffe10202070
11359 #define cfgBIF_CFG_DEV0_EPF2_1_LINK_CNTL                                                                0xfffe10202074
11360 #define cfgBIF_CFG_DEV0_EPF2_1_LINK_STATUS                                                              0xfffe10202076
11361 #define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CAP2                                                              0xfffe10202088
11362 #define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2                                                             0xfffe1020208c
11363 #define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2                                                           0xfffe1020208e
11364 #define cfgBIF_CFG_DEV0_EPF2_1_LINK_CAP2                                                                0xfffe10202090
11365 #define cfgBIF_CFG_DEV0_EPF2_1_LINK_CNTL2                                                               0xfffe10202094
11366 #define cfgBIF_CFG_DEV0_EPF2_1_LINK_STATUS2                                                             0xfffe10202096
11367 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST                                                             0xfffe102020a0
11368 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL                                                             0xfffe102020a2
11369 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO                                                          0xfffe102020a4
11370 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI                                                          0xfffe102020a8
11371 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA                                                             0xfffe102020a8
11372 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_MASK                                                                 0xfffe102020ac
11373 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64                                                          0xfffe102020ac
11374 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_MASK_64                                                              0xfffe102020b0
11375 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_PENDING                                                              0xfffe102020b0
11376 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_PENDING_64                                                           0xfffe102020b4
11377 #define cfgBIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST                                                            0xfffe102020c0
11378 #define cfgBIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL                                                            0xfffe102020c2
11379 #define cfgBIF_CFG_DEV0_EPF2_1_MSIX_TABLE                                                               0xfffe102020c4
11380 #define cfgBIF_CFG_DEV0_EPF2_1_MSIX_PBA                                                                 0xfffe102020c8
11381 #define cfgBIF_CFG_DEV0_EPF2_1_SATA_CAP_0                                                               0xfffe102020d0
11382 #define cfgBIF_CFG_DEV0_EPF2_1_SATA_CAP_1                                                               0xfffe102020d4
11383 #define cfgBIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX                                                           0xfffe102020d8
11384 #define cfgBIF_CFG_DEV0_EPF2_1_SATA_IDP_DATA                                                            0xfffe102020dc
11385 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                        0xfffe10202100
11386 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR                                                 0xfffe10202104
11387 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1                                                    0xfffe10202108
11388 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2                                                    0xfffe1020210c
11389 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                            0xfffe10202150
11390 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS                                                   0xfffe10202154
11391 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK                                                     0xfffe10202158
11392 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY                                                 0xfffe1020215c
11393 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS                                                     0xfffe10202160
11394 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK                                                       0xfffe10202164
11395 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL                                                    0xfffe10202168
11396 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0                                                            0xfffe1020216c
11397 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1                                                            0xfffe10202170
11398 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2                                                            0xfffe10202174
11399 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3                                                            0xfffe10202178
11400 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0                                                     0xfffe10202188
11401 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1                                                     0xfffe1020218c
11402 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2                                                     0xfffe10202190
11403 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3                                                     0xfffe10202194
11404 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST                                                    0xfffe10202200
11405 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP                                                            0xfffe10202204
11406 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL                                                           0xfffe10202208
11407 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP                                                            0xfffe1020220c
11408 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL                                                           0xfffe10202210
11409 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP                                                            0xfffe10202214
11410 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL                                                           0xfffe10202218
11411 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP                                                            0xfffe1020221c
11412 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL                                                           0xfffe10202220
11413 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP                                                            0xfffe10202224
11414 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL                                                           0xfffe10202228
11415 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP                                                            0xfffe1020222c
11416 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL                                                           0xfffe10202230
11417 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST                                             0xfffe10202240
11418 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT                                              0xfffe10202244
11419 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA                                                     0xfffe10202248
11420 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP                                                      0xfffe1020224c
11421 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST                                                    0xfffe10202250
11422 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP                                                             0xfffe10202254
11423 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR                                               0xfffe10202258
11424 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS                                                          0xfffe1020225c
11425 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL                                                            0xfffe1020225e
11426 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                            0xfffe10202260
11427 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                            0xfffe10202261
11428 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                            0xfffe10202262
11429 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                            0xfffe10202263
11430 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                            0xfffe10202264
11431 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                            0xfffe10202265
11432 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                            0xfffe10202266
11433 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                            0xfffe10202267
11434 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST                                                    0xfffe102022a0
11435 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP                                                             0xfffe102022a4
11436 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL                                                            0xfffe102022a6
11437 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST                                                  0xfffe102022d0
11438 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP                                                           0xfffe102022d4
11439 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL                                                          0xfffe102022d6
11440 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST                                                    0xfffe10202328
11441 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP                                                             0xfffe1020232c
11442 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL                                                            0xfffe1020232e
11443 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST                                               0xfffe10202370
11444 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP                                                        0xfffe10202374
11445 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CNTL                                                       0xfffe10202378
11446 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_0                                                      0xfffe1020237c
11447 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_1                                                      0xfffe1020237e
11448 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_2                                                      0xfffe10202380
11449 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_3                                                      0xfffe10202382
11450 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_4                                                      0xfffe10202384
11451 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_5                                                      0xfffe10202386
11452 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_6                                                      0xfffe10202388
11453 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_7                                                      0xfffe1020238a
11454 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_8                                                      0xfffe1020238c
11455 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_9                                                      0xfffe1020238e
11456 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_10                                                     0xfffe10202390
11457 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_11                                                     0xfffe10202392
11458 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_12                                                     0xfffe10202394
11459 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_13                                                     0xfffe10202396
11460 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_14                                                     0xfffe10202398
11461 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_15                                                     0xfffe1020239a
11462 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_16                                                     0xfffe1020239c
11463 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_17                                                     0xfffe1020239e
11464 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_18                                                     0xfffe102023a0
11465 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_19                                                     0xfffe102023a2
11466 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_20                                                     0xfffe102023a4
11467 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_21                                                     0xfffe102023a6
11468 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_22                                                     0xfffe102023a8
11469 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_23                                                     0xfffe102023aa
11470 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_24                                                     0xfffe102023ac
11471 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_25                                                     0xfffe102023ae
11472 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_26                                                     0xfffe102023b0
11473 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_27                                                     0xfffe102023b2
11474 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_28                                                     0xfffe102023b4
11475 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_29                                                     0xfffe102023b6
11476 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_30                                                     0xfffe102023b8
11477 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_31                                                     0xfffe102023ba
11478 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_32                                                     0xfffe102023bc
11479 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_33                                                     0xfffe102023be
11480 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_34                                                     0xfffe102023c0
11481 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_35                                                     0xfffe102023c2
11482 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_36                                                     0xfffe102023c4
11483 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_37                                                     0xfffe102023c6
11484 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_38                                                     0xfffe102023c8
11485 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_39                                                     0xfffe102023ca
11486 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_40                                                     0xfffe102023cc
11487 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_41                                                     0xfffe102023ce
11488 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_42                                                     0xfffe102023d0
11489 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_43                                                     0xfffe102023d2
11490 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_44                                                     0xfffe102023d4
11491 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_45                                                     0xfffe102023d6
11492 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_46                                                     0xfffe102023d8
11493 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_47                                                     0xfffe102023da
11494 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_48                                                     0xfffe102023dc
11495 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_49                                                     0xfffe102023de
11496 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_50                                                     0xfffe102023e0
11497 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_51                                                     0xfffe102023e2
11498 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_52                                                     0xfffe102023e4
11499 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_53                                                     0xfffe102023e6
11500 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_54                                                     0xfffe102023e8
11501 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_55                                                     0xfffe102023ea
11502 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_56                                                     0xfffe102023ec
11503 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_57                                                     0xfffe102023ee
11504 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_58                                                     0xfffe102023f0
11505 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_59                                                     0xfffe102023f2
11506 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_60                                                     0xfffe102023f4
11507 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_61                                                     0xfffe102023f6
11508 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_62                                                     0xfffe102023f8
11509 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_63                                                     0xfffe102023fa
11510 
11511 
11512 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp
11513 // base address: 0xfffe10203000
11514 #define cfgBIF_CFG_DEV0_EPF3_1_VENDOR_ID                                                                0xfffe10203000
11515 #define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_ID                                                                0xfffe10203002
11516 #define cfgBIF_CFG_DEV0_EPF3_1_COMMAND                                                                  0xfffe10203004
11517 #define cfgBIF_CFG_DEV0_EPF3_1_STATUS                                                                   0xfffe10203006
11518 #define cfgBIF_CFG_DEV0_EPF3_1_REVISION_ID                                                              0xfffe10203008
11519 #define cfgBIF_CFG_DEV0_EPF3_1_PROG_INTERFACE                                                           0xfffe10203009
11520 #define cfgBIF_CFG_DEV0_EPF3_1_SUB_CLASS                                                                0xfffe1020300a
11521 #define cfgBIF_CFG_DEV0_EPF3_1_BASE_CLASS                                                               0xfffe1020300b
11522 #define cfgBIF_CFG_DEV0_EPF3_1_CACHE_LINE                                                               0xfffe1020300c
11523 #define cfgBIF_CFG_DEV0_EPF3_1_LATENCY                                                                  0xfffe1020300d
11524 #define cfgBIF_CFG_DEV0_EPF3_1_HEADER                                                                   0xfffe1020300e
11525 #define cfgBIF_CFG_DEV0_EPF3_1_BIST                                                                     0xfffe1020300f
11526 #define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_1                                                              0xfffe10203010
11527 #define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_2                                                              0xfffe10203014
11528 #define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_3                                                              0xfffe10203018
11529 #define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_4                                                              0xfffe1020301c
11530 #define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_5                                                              0xfffe10203020
11531 #define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_6                                                              0xfffe10203024
11532 #define cfgBIF_CFG_DEV0_EPF3_1_CARDBUS_CIS_PTR                                                          0xfffe10203028
11533 #define cfgBIF_CFG_DEV0_EPF3_1_ADAPTER_ID                                                               0xfffe1020302c
11534 #define cfgBIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR                                                            0xfffe10203030
11535 #define cfgBIF_CFG_DEV0_EPF3_1_CAP_PTR                                                                  0xfffe10203034
11536 #define cfgBIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE                                                           0xfffe1020303c
11537 #define cfgBIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN                                                            0xfffe1020303d
11538 #define cfgBIF_CFG_DEV0_EPF3_1_MIN_GRANT                                                                0xfffe1020303e
11539 #define cfgBIF_CFG_DEV0_EPF3_1_MAX_LATENCY                                                              0xfffe1020303f
11540 #define cfgBIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST                                                          0xfffe10203048
11541 #define cfgBIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W                                                             0xfffe1020304c
11542 #define cfgBIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST                                                             0xfffe10203050
11543 #define cfgBIF_CFG_DEV0_EPF3_1_PMI_CAP                                                                  0xfffe10203052
11544 #define cfgBIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL                                                          0xfffe10203054
11545 #define cfgBIF_CFG_DEV0_EPF3_1_SBRN                                                                     0xfffe10203060
11546 #define cfgBIF_CFG_DEV0_EPF3_1_FLADJ                                                                    0xfffe10203061
11547 #define cfgBIF_CFG_DEV0_EPF3_1_DBESL_DBESLD                                                             0xfffe10203062
11548 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST                                                            0xfffe10203064
11549 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_CAP                                                                 0xfffe10203066
11550 #define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CAP                                                               0xfffe10203068
11551 #define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CNTL                                                              0xfffe1020306c
11552 #define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_STATUS                                                            0xfffe1020306e
11553 #define cfgBIF_CFG_DEV0_EPF3_1_LINK_CAP                                                                 0xfffe10203070
11554 #define cfgBIF_CFG_DEV0_EPF3_1_LINK_CNTL                                                                0xfffe10203074
11555 #define cfgBIF_CFG_DEV0_EPF3_1_LINK_STATUS                                                              0xfffe10203076
11556 #define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CAP2                                                              0xfffe10203088
11557 #define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2                                                             0xfffe1020308c
11558 #define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2                                                           0xfffe1020308e
11559 #define cfgBIF_CFG_DEV0_EPF3_1_LINK_CAP2                                                                0xfffe10203090
11560 #define cfgBIF_CFG_DEV0_EPF3_1_LINK_CNTL2                                                               0xfffe10203094
11561 #define cfgBIF_CFG_DEV0_EPF3_1_LINK_STATUS2                                                             0xfffe10203096
11562 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST                                                             0xfffe102030a0
11563 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL                                                             0xfffe102030a2
11564 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO                                                          0xfffe102030a4
11565 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI                                                          0xfffe102030a8
11566 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA                                                             0xfffe102030a8
11567 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_MASK                                                                 0xfffe102030ac
11568 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64                                                          0xfffe102030ac
11569 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_MASK_64                                                              0xfffe102030b0
11570 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_PENDING                                                              0xfffe102030b0
11571 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_PENDING_64                                                           0xfffe102030b4
11572 #define cfgBIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST                                                            0xfffe102030c0
11573 #define cfgBIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL                                                            0xfffe102030c2
11574 #define cfgBIF_CFG_DEV0_EPF3_1_MSIX_TABLE                                                               0xfffe102030c4
11575 #define cfgBIF_CFG_DEV0_EPF3_1_MSIX_PBA                                                                 0xfffe102030c8
11576 #define cfgBIF_CFG_DEV0_EPF3_1_SATA_CAP_0                                                               0xfffe102030d0
11577 #define cfgBIF_CFG_DEV0_EPF3_1_SATA_CAP_1                                                               0xfffe102030d4
11578 #define cfgBIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX                                                           0xfffe102030d8
11579 #define cfgBIF_CFG_DEV0_EPF3_1_SATA_IDP_DATA                                                            0xfffe102030dc
11580 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                        0xfffe10203100
11581 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR                                                 0xfffe10203104
11582 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1                                                    0xfffe10203108
11583 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2                                                    0xfffe1020310c
11584 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                            0xfffe10203150
11585 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS                                                   0xfffe10203154
11586 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK                                                     0xfffe10203158
11587 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY                                                 0xfffe1020315c
11588 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS                                                     0xfffe10203160
11589 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK                                                       0xfffe10203164
11590 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL                                                    0xfffe10203168
11591 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0                                                            0xfffe1020316c
11592 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1                                                            0xfffe10203170
11593 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2                                                            0xfffe10203174
11594 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3                                                            0xfffe10203178
11595 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0                                                     0xfffe10203188
11596 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1                                                     0xfffe1020318c
11597 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2                                                     0xfffe10203190
11598 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3                                                     0xfffe10203194
11599 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST                                                    0xfffe10203200
11600 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP                                                            0xfffe10203204
11601 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL                                                           0xfffe10203208
11602 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP                                                            0xfffe1020320c
11603 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL                                                           0xfffe10203210
11604 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP                                                            0xfffe10203214
11605 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL                                                           0xfffe10203218
11606 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP                                                            0xfffe1020321c
11607 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL                                                           0xfffe10203220
11608 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP                                                            0xfffe10203224
11609 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL                                                           0xfffe10203228
11610 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP                                                            0xfffe1020322c
11611 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL                                                           0xfffe10203230
11612 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST                                             0xfffe10203240
11613 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT                                              0xfffe10203244
11614 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA                                                     0xfffe10203248
11615 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP                                                      0xfffe1020324c
11616 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST                                                    0xfffe10203250
11617 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP                                                             0xfffe10203254
11618 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR                                               0xfffe10203258
11619 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS                                                          0xfffe1020325c
11620 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL                                                            0xfffe1020325e
11621 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                            0xfffe10203260
11622 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                            0xfffe10203261
11623 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                            0xfffe10203262
11624 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                            0xfffe10203263
11625 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                            0xfffe10203264
11626 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                            0xfffe10203265
11627 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                            0xfffe10203266
11628 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                            0xfffe10203267
11629 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST                                                    0xfffe102032a0
11630 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP                                                             0xfffe102032a4
11631 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL                                                            0xfffe102032a6
11632 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST                                                  0xfffe102032d0
11633 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP                                                           0xfffe102032d4
11634 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL                                                          0xfffe102032d6
11635 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST                                                    0xfffe10203328
11636 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP                                                             0xfffe1020332c
11637 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL                                                            0xfffe1020332e
11638 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST                                               0xfffe10203370
11639 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP                                                        0xfffe10203374
11640 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CNTL                                                       0xfffe10203378
11641 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_0                                                      0xfffe1020337c
11642 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_1                                                      0xfffe1020337e
11643 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_2                                                      0xfffe10203380
11644 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_3                                                      0xfffe10203382
11645 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_4                                                      0xfffe10203384
11646 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_5                                                      0xfffe10203386
11647 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_6                                                      0xfffe10203388
11648 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_7                                                      0xfffe1020338a
11649 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_8                                                      0xfffe1020338c
11650 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_9                                                      0xfffe1020338e
11651 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_10                                                     0xfffe10203390
11652 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_11                                                     0xfffe10203392
11653 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_12                                                     0xfffe10203394
11654 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_13                                                     0xfffe10203396
11655 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_14                                                     0xfffe10203398
11656 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_15                                                     0xfffe1020339a
11657 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_16                                                     0xfffe1020339c
11658 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_17                                                     0xfffe1020339e
11659 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_18                                                     0xfffe102033a0
11660 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_19                                                     0xfffe102033a2
11661 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_20                                                     0xfffe102033a4
11662 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_21                                                     0xfffe102033a6
11663 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_22                                                     0xfffe102033a8
11664 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_23                                                     0xfffe102033aa
11665 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_24                                                     0xfffe102033ac
11666 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_25                                                     0xfffe102033ae
11667 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_26                                                     0xfffe102033b0
11668 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_27                                                     0xfffe102033b2
11669 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_28                                                     0xfffe102033b4
11670 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_29                                                     0xfffe102033b6
11671 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_30                                                     0xfffe102033b8
11672 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_31                                                     0xfffe102033ba
11673 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_32                                                     0xfffe102033bc
11674 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_33                                                     0xfffe102033be
11675 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_34                                                     0xfffe102033c0
11676 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_35                                                     0xfffe102033c2
11677 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_36                                                     0xfffe102033c4
11678 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_37                                                     0xfffe102033c6
11679 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_38                                                     0xfffe102033c8
11680 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_39                                                     0xfffe102033ca
11681 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_40                                                     0xfffe102033cc
11682 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_41                                                     0xfffe102033ce
11683 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_42                                                     0xfffe102033d0
11684 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_43                                                     0xfffe102033d2
11685 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_44                                                     0xfffe102033d4
11686 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_45                                                     0xfffe102033d6
11687 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_46                                                     0xfffe102033d8
11688 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_47                                                     0xfffe102033da
11689 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_48                                                     0xfffe102033dc
11690 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_49                                                     0xfffe102033de
11691 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_50                                                     0xfffe102033e0
11692 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_51                                                     0xfffe102033e2
11693 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_52                                                     0xfffe102033e4
11694 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_53                                                     0xfffe102033e6
11695 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_54                                                     0xfffe102033e8
11696 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_55                                                     0xfffe102033ea
11697 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_56                                                     0xfffe102033ec
11698 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_57                                                     0xfffe102033ee
11699 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_58                                                     0xfffe102033f0
11700 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_59                                                     0xfffe102033f2
11701 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_60                                                     0xfffe102033f4
11702 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_61                                                     0xfffe102033f6
11703 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_62                                                     0xfffe102033f8
11704 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_63                                                     0xfffe102033fa
11705 
11706 
11707 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp
11708 // base address: 0xfffe10300000
11709 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_VENDOR_ID                                                            0xfffe10300000
11710 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_ID                                                            0xfffe10300002
11711 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_COMMAND                                                              0xfffe10300004
11712 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_STATUS                                                               0xfffe10300006
11713 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID                                                          0xfffe10300008
11714 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PROG_INTERFACE                                                       0xfffe10300009
11715 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_SUB_CLASS                                                            0xfffe1030000a
11716 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_CLASS                                                           0xfffe1030000b
11717 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_CACHE_LINE                                                           0xfffe1030000c
11718 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_LATENCY                                                              0xfffe1030000d
11719 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_HEADER                                                               0xfffe1030000e
11720 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BIST                                                                 0xfffe1030000f
11721 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_1                                                          0xfffe10300010
11722 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_2                                                          0xfffe10300014
11723 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_3                                                          0xfffe10300018
11724 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_4                                                          0xfffe1030001c
11725 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_5                                                          0xfffe10300020
11726 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_6                                                          0xfffe10300024
11727 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_CARDBUS_CIS_PTR                                                      0xfffe10300028
11728 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID                                                           0xfffe1030002c
11729 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR                                                        0xfffe10300030
11730 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_CAP_PTR                                                              0xfffe10300034
11731 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_LINE                                                       0xfffe1030003c
11732 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_PIN                                                        0xfffe1030003d
11733 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MIN_GRANT                                                            0xfffe1030003e
11734 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MAX_LATENCY                                                          0xfffe1030003f
11735 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST                                                        0xfffe10300064
11736 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP                                                             0xfffe10300066
11737 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP                                                           0xfffe10300068
11738 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL                                                          0xfffe1030006c
11739 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS                                                        0xfffe1030006e
11740 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP                                                             0xfffe10300070
11741 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL                                                            0xfffe10300074
11742 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS                                                          0xfffe10300076
11743 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2                                                          0xfffe10300088
11744 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2                                                         0xfffe1030008c
11745 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS2                                                       0xfffe1030008e
11746 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2                                                            0xfffe10300090
11747 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2                                                           0xfffe10300094
11748 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2                                                         0xfffe10300096
11749 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST                                                         0xfffe103000a0
11750 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL                                                         0xfffe103000a2
11751 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_LO                                                      0xfffe103000a4
11752 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_HI                                                      0xfffe103000a8
11753 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA                                                         0xfffe103000a8
11754 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK                                                             0xfffe103000ac
11755 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_64                                                      0xfffe103000ac
11756 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_64                                                          0xfffe103000b0
11757 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING                                                          0xfffe103000b0
11758 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_64                                                       0xfffe103000b4
11759 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST                                                        0xfffe103000c0
11760 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL                                                        0xfffe103000c2
11761 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE                                                           0xfffe103000c4
11762 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA                                                             0xfffe103000c8
11763 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                    0xfffe10300100
11764 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR                                             0xfffe10300104
11765 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC1                                                0xfffe10300108
11766 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC2                                                0xfffe1030010c
11767 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                        0xfffe10300150
11768 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS                                               0xfffe10300154
11769 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK                                                 0xfffe10300158
11770 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY                                             0xfffe1030015c
11771 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS                                                 0xfffe10300160
11772 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK                                                   0xfffe10300164
11773 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL                                                0xfffe10300168
11774 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG0                                                        0xfffe1030016c
11775 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG1                                                        0xfffe10300170
11776 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG2                                                        0xfffe10300174
11777 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG3                                                        0xfffe10300178
11778 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG0                                                 0xfffe10300188
11779 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG1                                                 0xfffe1030018c
11780 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG2                                                 0xfffe10300190
11781 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG3                                                 0xfffe10300194
11782 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST                                                0xfffe103002b0
11783 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP                                                         0xfffe103002b4
11784 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CNTL                                                        0xfffe103002b6
11785 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST                                                0xfffe10300328
11786 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP                                                         0xfffe1030032c
11787 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL                                                        0xfffe1030032e
11788 
11789 
11790 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp
11791 // base address: 0xfffe10301000
11792 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_VENDOR_ID                                                            0xfffe10301000
11793 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_ID                                                            0xfffe10301002
11794 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_COMMAND                                                              0xfffe10301004
11795 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_STATUS                                                               0xfffe10301006
11796 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID                                                          0xfffe10301008
11797 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PROG_INTERFACE                                                       0xfffe10301009
11798 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_SUB_CLASS                                                            0xfffe1030100a
11799 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_CLASS                                                           0xfffe1030100b
11800 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_CACHE_LINE                                                           0xfffe1030100c
11801 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_LATENCY                                                              0xfffe1030100d
11802 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_HEADER                                                               0xfffe1030100e
11803 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BIST                                                                 0xfffe1030100f
11804 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_1                                                          0xfffe10301010
11805 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_2                                                          0xfffe10301014
11806 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_3                                                          0xfffe10301018
11807 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_4                                                          0xfffe1030101c
11808 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_5                                                          0xfffe10301020
11809 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_6                                                          0xfffe10301024
11810 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_CARDBUS_CIS_PTR                                                      0xfffe10301028
11811 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID                                                           0xfffe1030102c
11812 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR                                                        0xfffe10301030
11813 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_CAP_PTR                                                              0xfffe10301034
11814 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_LINE                                                       0xfffe1030103c
11815 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_PIN                                                        0xfffe1030103d
11816 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MIN_GRANT                                                            0xfffe1030103e
11817 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MAX_LATENCY                                                          0xfffe1030103f
11818 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST                                                        0xfffe10301064
11819 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP                                                             0xfffe10301066
11820 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP                                                           0xfffe10301068
11821 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL                                                          0xfffe1030106c
11822 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS                                                        0xfffe1030106e
11823 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP                                                             0xfffe10301070
11824 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL                                                            0xfffe10301074
11825 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS                                                          0xfffe10301076
11826 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2                                                          0xfffe10301088
11827 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2                                                         0xfffe1030108c
11828 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS2                                                       0xfffe1030108e
11829 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2                                                            0xfffe10301090
11830 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2                                                           0xfffe10301094
11831 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2                                                         0xfffe10301096
11832 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST                                                         0xfffe103010a0
11833 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL                                                         0xfffe103010a2
11834 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_LO                                                      0xfffe103010a4
11835 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_HI                                                      0xfffe103010a8
11836 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA                                                         0xfffe103010a8
11837 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK                                                             0xfffe103010ac
11838 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_64                                                      0xfffe103010ac
11839 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_64                                                          0xfffe103010b0
11840 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING                                                          0xfffe103010b0
11841 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_64                                                       0xfffe103010b4
11842 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST                                                        0xfffe103010c0
11843 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL                                                        0xfffe103010c2
11844 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE                                                           0xfffe103010c4
11845 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA                                                             0xfffe103010c8
11846 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                    0xfffe10301100
11847 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR                                             0xfffe10301104
11848 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC1                                                0xfffe10301108
11849 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC2                                                0xfffe1030110c
11850 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                        0xfffe10301150
11851 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS                                               0xfffe10301154
11852 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK                                                 0xfffe10301158
11853 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY                                             0xfffe1030115c
11854 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS                                                 0xfffe10301160
11855 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK                                                   0xfffe10301164
11856 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL                                                0xfffe10301168
11857 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG0                                                        0xfffe1030116c
11858 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG1                                                        0xfffe10301170
11859 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG2                                                        0xfffe10301174
11860 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG3                                                        0xfffe10301178
11861 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG0                                                 0xfffe10301188
11862 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG1                                                 0xfffe1030118c
11863 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG2                                                 0xfffe10301190
11864 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG3                                                 0xfffe10301194
11865 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST                                                0xfffe103012b0
11866 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP                                                         0xfffe103012b4
11867 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CNTL                                                        0xfffe103012b6
11868 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST                                                0xfffe10301328
11869 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP                                                         0xfffe1030132c
11870 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL                                                        0xfffe1030132e
11871 
11872 
11873 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp
11874 // base address: 0xfffe10302000
11875 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_VENDOR_ID                                                            0xfffe10302000
11876 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_ID                                                            0xfffe10302002
11877 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_COMMAND                                                              0xfffe10302004
11878 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_STATUS                                                               0xfffe10302006
11879 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID                                                          0xfffe10302008
11880 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PROG_INTERFACE                                                       0xfffe10302009
11881 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_SUB_CLASS                                                            0xfffe1030200a
11882 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_CLASS                                                           0xfffe1030200b
11883 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_CACHE_LINE                                                           0xfffe1030200c
11884 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_LATENCY                                                              0xfffe1030200d
11885 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_HEADER                                                               0xfffe1030200e
11886 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BIST                                                                 0xfffe1030200f
11887 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_1                                                          0xfffe10302010
11888 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_2                                                          0xfffe10302014
11889 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_3                                                          0xfffe10302018
11890 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_4                                                          0xfffe1030201c
11891 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_5                                                          0xfffe10302020
11892 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_6                                                          0xfffe10302024
11893 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_CARDBUS_CIS_PTR                                                      0xfffe10302028
11894 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID                                                           0xfffe1030202c
11895 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR                                                        0xfffe10302030
11896 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_CAP_PTR                                                              0xfffe10302034
11897 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_LINE                                                       0xfffe1030203c
11898 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_PIN                                                        0xfffe1030203d
11899 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MIN_GRANT                                                            0xfffe1030203e
11900 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MAX_LATENCY                                                          0xfffe1030203f
11901 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST                                                        0xfffe10302064
11902 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP                                                             0xfffe10302066
11903 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP                                                           0xfffe10302068
11904 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL                                                          0xfffe1030206c
11905 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS                                                        0xfffe1030206e
11906 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP                                                             0xfffe10302070
11907 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL                                                            0xfffe10302074
11908 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS                                                          0xfffe10302076
11909 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2                                                          0xfffe10302088
11910 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2                                                         0xfffe1030208c
11911 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS2                                                       0xfffe1030208e
11912 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2                                                            0xfffe10302090
11913 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2                                                           0xfffe10302094
11914 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2                                                         0xfffe10302096
11915 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST                                                         0xfffe103020a0
11916 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL                                                         0xfffe103020a2
11917 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_LO                                                      0xfffe103020a4
11918 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_HI                                                      0xfffe103020a8
11919 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA                                                         0xfffe103020a8
11920 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK                                                             0xfffe103020ac
11921 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_64                                                      0xfffe103020ac
11922 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_64                                                          0xfffe103020b0
11923 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING                                                          0xfffe103020b0
11924 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_64                                                       0xfffe103020b4
11925 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST                                                        0xfffe103020c0
11926 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL                                                        0xfffe103020c2
11927 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE                                                           0xfffe103020c4
11928 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA                                                             0xfffe103020c8
11929 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                    0xfffe10302100
11930 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR                                             0xfffe10302104
11931 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC1                                                0xfffe10302108
11932 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC2                                                0xfffe1030210c
11933 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                        0xfffe10302150
11934 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS                                               0xfffe10302154
11935 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK                                                 0xfffe10302158
11936 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY                                             0xfffe1030215c
11937 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS                                                 0xfffe10302160
11938 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK                                                   0xfffe10302164
11939 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL                                                0xfffe10302168
11940 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG0                                                        0xfffe1030216c
11941 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG1                                                        0xfffe10302170
11942 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG2                                                        0xfffe10302174
11943 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG3                                                        0xfffe10302178
11944 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG0                                                 0xfffe10302188
11945 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG1                                                 0xfffe1030218c
11946 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG2                                                 0xfffe10302190
11947 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG3                                                 0xfffe10302194
11948 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST                                                0xfffe103022b0
11949 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP                                                         0xfffe103022b4
11950 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CNTL                                                        0xfffe103022b6
11951 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST                                                0xfffe10302328
11952 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP                                                         0xfffe1030232c
11953 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL                                                        0xfffe1030232e
11954 
11955 
11956 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp
11957 // base address: 0xfffe10303000
11958 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_VENDOR_ID                                                            0xfffe10303000
11959 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_ID                                                            0xfffe10303002
11960 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_COMMAND                                                              0xfffe10303004
11961 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_STATUS                                                               0xfffe10303006
11962 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID                                                          0xfffe10303008
11963 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PROG_INTERFACE                                                       0xfffe10303009
11964 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_SUB_CLASS                                                            0xfffe1030300a
11965 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_CLASS                                                           0xfffe1030300b
11966 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_CACHE_LINE                                                           0xfffe1030300c
11967 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_LATENCY                                                              0xfffe1030300d
11968 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_HEADER                                                               0xfffe1030300e
11969 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BIST                                                                 0xfffe1030300f
11970 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_1                                                          0xfffe10303010
11971 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_2                                                          0xfffe10303014
11972 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_3                                                          0xfffe10303018
11973 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_4                                                          0xfffe1030301c
11974 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_5                                                          0xfffe10303020
11975 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_6                                                          0xfffe10303024
11976 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_CARDBUS_CIS_PTR                                                      0xfffe10303028
11977 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID                                                           0xfffe1030302c
11978 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR                                                        0xfffe10303030
11979 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_CAP_PTR                                                              0xfffe10303034
11980 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_LINE                                                       0xfffe1030303c
11981 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_PIN                                                        0xfffe1030303d
11982 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MIN_GRANT                                                            0xfffe1030303e
11983 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MAX_LATENCY                                                          0xfffe1030303f
11984 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST                                                        0xfffe10303064
11985 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP                                                             0xfffe10303066
11986 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP                                                           0xfffe10303068
11987 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL                                                          0xfffe1030306c
11988 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS                                                        0xfffe1030306e
11989 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP                                                             0xfffe10303070
11990 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL                                                            0xfffe10303074
11991 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS                                                          0xfffe10303076
11992 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2                                                          0xfffe10303088
11993 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2                                                         0xfffe1030308c
11994 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS2                                                       0xfffe1030308e
11995 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2                                                            0xfffe10303090
11996 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2                                                           0xfffe10303094
11997 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2                                                         0xfffe10303096
11998 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST                                                         0xfffe103030a0
11999 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL                                                         0xfffe103030a2
12000 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_LO                                                      0xfffe103030a4
12001 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_HI                                                      0xfffe103030a8
12002 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA                                                         0xfffe103030a8
12003 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK                                                             0xfffe103030ac
12004 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_64                                                      0xfffe103030ac
12005 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_64                                                          0xfffe103030b0
12006 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING                                                          0xfffe103030b0
12007 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_64                                                       0xfffe103030b4
12008 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST                                                        0xfffe103030c0
12009 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL                                                        0xfffe103030c2
12010 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE                                                           0xfffe103030c4
12011 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA                                                             0xfffe103030c8
12012 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                    0xfffe10303100
12013 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR                                             0xfffe10303104
12014 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC1                                                0xfffe10303108
12015 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC2                                                0xfffe1030310c
12016 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                        0xfffe10303150
12017 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS                                               0xfffe10303154
12018 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK                                                 0xfffe10303158
12019 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY                                             0xfffe1030315c
12020 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS                                                 0xfffe10303160
12021 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK                                                   0xfffe10303164
12022 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL                                                0xfffe10303168
12023 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG0                                                        0xfffe1030316c
12024 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG1                                                        0xfffe10303170
12025 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG2                                                        0xfffe10303174
12026 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG3                                                        0xfffe10303178
12027 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG0                                                 0xfffe10303188
12028 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG1                                                 0xfffe1030318c
12029 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG2                                                 0xfffe10303190
12030 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG3                                                 0xfffe10303194
12031 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST                                                0xfffe103032b0
12032 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP                                                         0xfffe103032b4
12033 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CNTL                                                        0xfffe103032b6
12034 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST                                                0xfffe10303328
12035 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP                                                         0xfffe1030332c
12036 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL                                                        0xfffe1030332e
12037 
12038 
12039 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp
12040 // base address: 0xfffe10304000
12041 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_VENDOR_ID                                                            0xfffe10304000
12042 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_ID                                                            0xfffe10304002
12043 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_COMMAND                                                              0xfffe10304004
12044 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_STATUS                                                               0xfffe10304006
12045 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID                                                          0xfffe10304008
12046 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PROG_INTERFACE                                                       0xfffe10304009
12047 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_SUB_CLASS                                                            0xfffe1030400a
12048 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_CLASS                                                           0xfffe1030400b
12049 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_CACHE_LINE                                                           0xfffe1030400c
12050 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_LATENCY                                                              0xfffe1030400d
12051 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_HEADER                                                               0xfffe1030400e
12052 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BIST                                                                 0xfffe1030400f
12053 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_1                                                          0xfffe10304010
12054 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_2                                                          0xfffe10304014
12055 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_3                                                          0xfffe10304018
12056 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_4                                                          0xfffe1030401c
12057 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_5                                                          0xfffe10304020
12058 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_6                                                          0xfffe10304024
12059 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_CARDBUS_CIS_PTR                                                      0xfffe10304028
12060 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID                                                           0xfffe1030402c
12061 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR                                                        0xfffe10304030
12062 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_CAP_PTR                                                              0xfffe10304034
12063 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_LINE                                                       0xfffe1030403c
12064 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_PIN                                                        0xfffe1030403d
12065 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MIN_GRANT                                                            0xfffe1030403e
12066 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MAX_LATENCY                                                          0xfffe1030403f
12067 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST                                                        0xfffe10304064
12068 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP                                                             0xfffe10304066
12069 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP                                                           0xfffe10304068
12070 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL                                                          0xfffe1030406c
12071 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS                                                        0xfffe1030406e
12072 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP                                                             0xfffe10304070
12073 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL                                                            0xfffe10304074
12074 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS                                                          0xfffe10304076
12075 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2                                                          0xfffe10304088
12076 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2                                                         0xfffe1030408c
12077 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS2                                                       0xfffe1030408e
12078 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2                                                            0xfffe10304090
12079 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2                                                           0xfffe10304094
12080 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2                                                         0xfffe10304096
12081 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST                                                         0xfffe103040a0
12082 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL                                                         0xfffe103040a2
12083 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_LO                                                      0xfffe103040a4
12084 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_HI                                                      0xfffe103040a8
12085 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA                                                         0xfffe103040a8
12086 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK                                                             0xfffe103040ac
12087 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_64                                                      0xfffe103040ac
12088 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_64                                                          0xfffe103040b0
12089 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING                                                          0xfffe103040b0
12090 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_64                                                       0xfffe103040b4
12091 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST                                                        0xfffe103040c0
12092 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL                                                        0xfffe103040c2
12093 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE                                                           0xfffe103040c4
12094 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA                                                             0xfffe103040c8
12095 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                    0xfffe10304100
12096 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR                                             0xfffe10304104
12097 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC1                                                0xfffe10304108
12098 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC2                                                0xfffe1030410c
12099 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                        0xfffe10304150
12100 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS                                               0xfffe10304154
12101 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK                                                 0xfffe10304158
12102 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY                                             0xfffe1030415c
12103 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS                                                 0xfffe10304160
12104 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK                                                   0xfffe10304164
12105 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL                                                0xfffe10304168
12106 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG0                                                        0xfffe1030416c
12107 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG1                                                        0xfffe10304170
12108 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG2                                                        0xfffe10304174
12109 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG3                                                        0xfffe10304178
12110 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG0                                                 0xfffe10304188
12111 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG1                                                 0xfffe1030418c
12112 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG2                                                 0xfffe10304190
12113 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG3                                                 0xfffe10304194
12114 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST                                                0xfffe103042b0
12115 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP                                                         0xfffe103042b4
12116 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CNTL                                                        0xfffe103042b6
12117 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST                                                0xfffe10304328
12118 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP                                                         0xfffe1030432c
12119 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL                                                        0xfffe1030432e
12120 
12121 
12122 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp
12123 // base address: 0xfffe10305000
12124 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_VENDOR_ID                                                            0xfffe10305000
12125 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_ID                                                            0xfffe10305002
12126 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_COMMAND                                                              0xfffe10305004
12127 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_STATUS                                                               0xfffe10305006
12128 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID                                                          0xfffe10305008
12129 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PROG_INTERFACE                                                       0xfffe10305009
12130 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_SUB_CLASS                                                            0xfffe1030500a
12131 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_CLASS                                                           0xfffe1030500b
12132 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_CACHE_LINE                                                           0xfffe1030500c
12133 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_LATENCY                                                              0xfffe1030500d
12134 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_HEADER                                                               0xfffe1030500e
12135 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BIST                                                                 0xfffe1030500f
12136 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_1                                                          0xfffe10305010
12137 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_2                                                          0xfffe10305014
12138 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_3                                                          0xfffe10305018
12139 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_4                                                          0xfffe1030501c
12140 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_5                                                          0xfffe10305020
12141 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_6                                                          0xfffe10305024
12142 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_CARDBUS_CIS_PTR                                                      0xfffe10305028
12143 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID                                                           0xfffe1030502c
12144 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR                                                        0xfffe10305030
12145 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR                                                              0xfffe10305034
12146 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_LINE                                                       0xfffe1030503c
12147 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_PIN                                                        0xfffe1030503d
12148 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MIN_GRANT                                                            0xfffe1030503e
12149 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MAX_LATENCY                                                          0xfffe1030503f
12150 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST                                                        0xfffe10305064
12151 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP                                                             0xfffe10305066
12152 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP                                                           0xfffe10305068
12153 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL                                                          0xfffe1030506c
12154 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS                                                        0xfffe1030506e
12155 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP                                                             0xfffe10305070
12156 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL                                                            0xfffe10305074
12157 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS                                                          0xfffe10305076
12158 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2                                                          0xfffe10305088
12159 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2                                                         0xfffe1030508c
12160 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS2                                                       0xfffe1030508e
12161 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2                                                            0xfffe10305090
12162 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2                                                           0xfffe10305094
12163 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2                                                         0xfffe10305096
12164 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST                                                         0xfffe103050a0
12165 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL                                                         0xfffe103050a2
12166 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_LO                                                      0xfffe103050a4
12167 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_HI                                                      0xfffe103050a8
12168 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA                                                         0xfffe103050a8
12169 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK                                                             0xfffe103050ac
12170 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_64                                                      0xfffe103050ac
12171 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_64                                                          0xfffe103050b0
12172 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING                                                          0xfffe103050b0
12173 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_64                                                       0xfffe103050b4
12174 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST                                                        0xfffe103050c0
12175 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL                                                        0xfffe103050c2
12176 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE                                                           0xfffe103050c4
12177 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA                                                             0xfffe103050c8
12178 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                    0xfffe10305100
12179 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR                                             0xfffe10305104
12180 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC1                                                0xfffe10305108
12181 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC2                                                0xfffe1030510c
12182 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                        0xfffe10305150
12183 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS                                               0xfffe10305154
12184 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK                                                 0xfffe10305158
12185 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY                                             0xfffe1030515c
12186 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS                                                 0xfffe10305160
12187 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK                                                   0xfffe10305164
12188 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL                                                0xfffe10305168
12189 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG0                                                        0xfffe1030516c
12190 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG1                                                        0xfffe10305170
12191 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG2                                                        0xfffe10305174
12192 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG3                                                        0xfffe10305178
12193 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG0                                                 0xfffe10305188
12194 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG1                                                 0xfffe1030518c
12195 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG2                                                 0xfffe10305190
12196 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG3                                                 0xfffe10305194
12197 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST                                                0xfffe103052b0
12198 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP                                                         0xfffe103052b4
12199 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CNTL                                                        0xfffe103052b6
12200 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST                                                0xfffe10305328
12201 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP                                                         0xfffe1030532c
12202 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL                                                        0xfffe1030532e
12203 
12204 
12205 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp
12206 // base address: 0xfffe10306000
12207 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_VENDOR_ID                                                            0xfffe10306000
12208 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_ID                                                            0xfffe10306002
12209 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_COMMAND                                                              0xfffe10306004
12210 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_STATUS                                                               0xfffe10306006
12211 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID                                                          0xfffe10306008
12212 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PROG_INTERFACE                                                       0xfffe10306009
12213 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_SUB_CLASS                                                            0xfffe1030600a
12214 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_CLASS                                                           0xfffe1030600b
12215 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_CACHE_LINE                                                           0xfffe1030600c
12216 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_LATENCY                                                              0xfffe1030600d
12217 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_HEADER                                                               0xfffe1030600e
12218 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BIST                                                                 0xfffe1030600f
12219 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_1                                                          0xfffe10306010
12220 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_2                                                          0xfffe10306014
12221 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_3                                                          0xfffe10306018
12222 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_4                                                          0xfffe1030601c
12223 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_5                                                          0xfffe10306020
12224 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_6                                                          0xfffe10306024
12225 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_CARDBUS_CIS_PTR                                                      0xfffe10306028
12226 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID                                                           0xfffe1030602c
12227 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR                                                        0xfffe10306030
12228 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_CAP_PTR                                                              0xfffe10306034
12229 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_LINE                                                       0xfffe1030603c
12230 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_PIN                                                        0xfffe1030603d
12231 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MIN_GRANT                                                            0xfffe1030603e
12232 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MAX_LATENCY                                                          0xfffe1030603f
12233 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST                                                        0xfffe10306064
12234 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP                                                             0xfffe10306066
12235 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP                                                           0xfffe10306068
12236 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL                                                          0xfffe1030606c
12237 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS                                                        0xfffe1030606e
12238 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP                                                             0xfffe10306070
12239 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL                                                            0xfffe10306074
12240 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS                                                          0xfffe10306076
12241 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2                                                          0xfffe10306088
12242 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2                                                         0xfffe1030608c
12243 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS2                                                       0xfffe1030608e
12244 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2                                                            0xfffe10306090
12245 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2                                                           0xfffe10306094
12246 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2                                                         0xfffe10306096
12247 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST                                                         0xfffe103060a0
12248 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL                                                         0xfffe103060a2
12249 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_LO                                                      0xfffe103060a4
12250 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_HI                                                      0xfffe103060a8
12251 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA                                                         0xfffe103060a8
12252 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK                                                             0xfffe103060ac
12253 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_64                                                      0xfffe103060ac
12254 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_64                                                          0xfffe103060b0
12255 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING                                                          0xfffe103060b0
12256 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_64                                                       0xfffe103060b4
12257 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST                                                        0xfffe103060c0
12258 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL                                                        0xfffe103060c2
12259 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE                                                           0xfffe103060c4
12260 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA                                                             0xfffe103060c8
12261 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                    0xfffe10306100
12262 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR                                             0xfffe10306104
12263 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC1                                                0xfffe10306108
12264 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC2                                                0xfffe1030610c
12265 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                        0xfffe10306150
12266 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS                                               0xfffe10306154
12267 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK                                                 0xfffe10306158
12268 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY                                             0xfffe1030615c
12269 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS                                                 0xfffe10306160
12270 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK                                                   0xfffe10306164
12271 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL                                                0xfffe10306168
12272 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG0                                                        0xfffe1030616c
12273 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG1                                                        0xfffe10306170
12274 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG2                                                        0xfffe10306174
12275 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG3                                                        0xfffe10306178
12276 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG0                                                 0xfffe10306188
12277 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG1                                                 0xfffe1030618c
12278 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG2                                                 0xfffe10306190
12279 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG3                                                 0xfffe10306194
12280 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST                                                0xfffe103062b0
12281 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP                                                         0xfffe103062b4
12282 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CNTL                                                        0xfffe103062b6
12283 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST                                                0xfffe10306328
12284 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP                                                         0xfffe1030632c
12285 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL                                                        0xfffe1030632e
12286 
12287 
12288 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp
12289 // base address: 0xfffe10307000
12290 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_VENDOR_ID                                                            0xfffe10307000
12291 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_ID                                                            0xfffe10307002
12292 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_COMMAND                                                              0xfffe10307004
12293 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_STATUS                                                               0xfffe10307006
12294 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID                                                          0xfffe10307008
12295 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PROG_INTERFACE                                                       0xfffe10307009
12296 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_SUB_CLASS                                                            0xfffe1030700a
12297 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_CLASS                                                           0xfffe1030700b
12298 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_CACHE_LINE                                                           0xfffe1030700c
12299 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_LATENCY                                                              0xfffe1030700d
12300 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_HEADER                                                               0xfffe1030700e
12301 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BIST                                                                 0xfffe1030700f
12302 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_1                                                          0xfffe10307010
12303 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_2                                                          0xfffe10307014
12304 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_3                                                          0xfffe10307018
12305 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_4                                                          0xfffe1030701c
12306 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_5                                                          0xfffe10307020
12307 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_6                                                          0xfffe10307024
12308 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_CARDBUS_CIS_PTR                                                      0xfffe10307028
12309 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID                                                           0xfffe1030702c
12310 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR                                                        0xfffe10307030
12311 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_CAP_PTR                                                              0xfffe10307034
12312 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_LINE                                                       0xfffe1030703c
12313 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_PIN                                                        0xfffe1030703d
12314 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MIN_GRANT                                                            0xfffe1030703e
12315 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MAX_LATENCY                                                          0xfffe1030703f
12316 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST                                                        0xfffe10307064
12317 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP                                                             0xfffe10307066
12318 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP                                                           0xfffe10307068
12319 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL                                                          0xfffe1030706c
12320 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS                                                        0xfffe1030706e
12321 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP                                                             0xfffe10307070
12322 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL                                                            0xfffe10307074
12323 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS                                                          0xfffe10307076
12324 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2                                                          0xfffe10307088
12325 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2                                                         0xfffe1030708c
12326 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS2                                                       0xfffe1030708e
12327 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2                                                            0xfffe10307090
12328 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2                                                           0xfffe10307094
12329 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2                                                         0xfffe10307096
12330 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST                                                         0xfffe103070a0
12331 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL                                                         0xfffe103070a2
12332 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_LO                                                      0xfffe103070a4
12333 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_HI                                                      0xfffe103070a8
12334 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA                                                         0xfffe103070a8
12335 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK                                                             0xfffe103070ac
12336 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_64                                                      0xfffe103070ac
12337 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_64                                                          0xfffe103070b0
12338 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING                                                          0xfffe103070b0
12339 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_64                                                       0xfffe103070b4
12340 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST                                                        0xfffe103070c0
12341 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL                                                        0xfffe103070c2
12342 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE                                                           0xfffe103070c4
12343 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA                                                             0xfffe103070c8
12344 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                    0xfffe10307100
12345 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR                                             0xfffe10307104
12346 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC1                                                0xfffe10307108
12347 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC2                                                0xfffe1030710c
12348 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                        0xfffe10307150
12349 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS                                               0xfffe10307154
12350 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK                                                 0xfffe10307158
12351 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY                                             0xfffe1030715c
12352 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS                                                 0xfffe10307160
12353 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK                                                   0xfffe10307164
12354 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL                                                0xfffe10307168
12355 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG0                                                        0xfffe1030716c
12356 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG1                                                        0xfffe10307170
12357 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG2                                                        0xfffe10307174
12358 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG3                                                        0xfffe10307178
12359 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG0                                                 0xfffe10307188
12360 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG1                                                 0xfffe1030718c
12361 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG2                                                 0xfffe10307190
12362 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG3                                                 0xfffe10307194
12363 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST                                                0xfffe103072b0
12364 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP                                                         0xfffe103072b4
12365 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CNTL                                                        0xfffe103072b6
12366 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST                                                0xfffe10307328
12367 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP                                                         0xfffe1030732c
12368 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL                                                        0xfffe1030732e
12369 
12370 
12371 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf8_bifcfgdecp
12372 // base address: 0xfffe10308000
12373 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_VENDOR_ID                                                            0xfffe10308000
12374 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_ID                                                            0xfffe10308002
12375 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_COMMAND                                                              0xfffe10308004
12376 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_STATUS                                                               0xfffe10308006
12377 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID                                                          0xfffe10308008
12378 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PROG_INTERFACE                                                       0xfffe10308009
12379 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_SUB_CLASS                                                            0xfffe1030800a
12380 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_CLASS                                                           0xfffe1030800b
12381 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_CACHE_LINE                                                           0xfffe1030800c
12382 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_LATENCY                                                              0xfffe1030800d
12383 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_HEADER                                                               0xfffe1030800e
12384 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BIST                                                                 0xfffe1030800f
12385 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_1                                                          0xfffe10308010
12386 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_2                                                          0xfffe10308014
12387 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_3                                                          0xfffe10308018
12388 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_4                                                          0xfffe1030801c
12389 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_5                                                          0xfffe10308020
12390 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_6                                                          0xfffe10308024
12391 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_CARDBUS_CIS_PTR                                                      0xfffe10308028
12392 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID                                                           0xfffe1030802c
12393 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR                                                        0xfffe10308030
12394 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_CAP_PTR                                                              0xfffe10308034
12395 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_LINE                                                       0xfffe1030803c
12396 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_PIN                                                        0xfffe1030803d
12397 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MIN_GRANT                                                            0xfffe1030803e
12398 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MAX_LATENCY                                                          0xfffe1030803f
12399 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST                                                        0xfffe10308064
12400 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP                                                             0xfffe10308066
12401 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP                                                           0xfffe10308068
12402 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL                                                          0xfffe1030806c
12403 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS                                                        0xfffe1030806e
12404 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP                                                             0xfffe10308070
12405 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL                                                            0xfffe10308074
12406 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS                                                          0xfffe10308076
12407 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2                                                          0xfffe10308088
12408 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2                                                         0xfffe1030808c
12409 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS2                                                       0xfffe1030808e
12410 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2                                                            0xfffe10308090
12411 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2                                                           0xfffe10308094
12412 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2                                                         0xfffe10308096
12413 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST                                                         0xfffe103080a0
12414 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL                                                         0xfffe103080a2
12415 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_LO                                                      0xfffe103080a4
12416 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_HI                                                      0xfffe103080a8
12417 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA                                                         0xfffe103080a8
12418 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK                                                             0xfffe103080ac
12419 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_64                                                      0xfffe103080ac
12420 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_64                                                          0xfffe103080b0
12421 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING                                                          0xfffe103080b0
12422 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_64                                                       0xfffe103080b4
12423 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST                                                        0xfffe103080c0
12424 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL                                                        0xfffe103080c2
12425 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE                                                           0xfffe103080c4
12426 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA                                                             0xfffe103080c8
12427 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                    0xfffe10308100
12428 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR                                             0xfffe10308104
12429 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC1                                                0xfffe10308108
12430 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC2                                                0xfffe1030810c
12431 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                        0xfffe10308150
12432 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS                                               0xfffe10308154
12433 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK                                                 0xfffe10308158
12434 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY                                             0xfffe1030815c
12435 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS                                                 0xfffe10308160
12436 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK                                                   0xfffe10308164
12437 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL                                                0xfffe10308168
12438 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG0                                                        0xfffe1030816c
12439 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG1                                                        0xfffe10308170
12440 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG2                                                        0xfffe10308174
12441 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG3                                                        0xfffe10308178
12442 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG0                                                 0xfffe10308188
12443 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG1                                                 0xfffe1030818c
12444 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG2                                                 0xfffe10308190
12445 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG3                                                 0xfffe10308194
12446 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST                                                0xfffe103082b0
12447 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP                                                         0xfffe103082b4
12448 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CNTL                                                        0xfffe103082b6
12449 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST                                                0xfffe10308328
12450 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP                                                         0xfffe1030832c
12451 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL                                                        0xfffe1030832e
12452 
12453 
12454 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf9_bifcfgdecp
12455 // base address: 0xfffe10309000
12456 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_VENDOR_ID                                                            0xfffe10309000
12457 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_ID                                                            0xfffe10309002
12458 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_COMMAND                                                              0xfffe10309004
12459 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_STATUS                                                               0xfffe10309006
12460 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID                                                          0xfffe10309008
12461 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PROG_INTERFACE                                                       0xfffe10309009
12462 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_SUB_CLASS                                                            0xfffe1030900a
12463 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_CLASS                                                           0xfffe1030900b
12464 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_CACHE_LINE                                                           0xfffe1030900c
12465 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_LATENCY                                                              0xfffe1030900d
12466 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_HEADER                                                               0xfffe1030900e
12467 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BIST                                                                 0xfffe1030900f
12468 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_1                                                          0xfffe10309010
12469 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_2                                                          0xfffe10309014
12470 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_3                                                          0xfffe10309018
12471 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_4                                                          0xfffe1030901c
12472 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_5                                                          0xfffe10309020
12473 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_6                                                          0xfffe10309024
12474 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_CARDBUS_CIS_PTR                                                      0xfffe10309028
12475 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID                                                           0xfffe1030902c
12476 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR                                                        0xfffe10309030
12477 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_CAP_PTR                                                              0xfffe10309034
12478 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_LINE                                                       0xfffe1030903c
12479 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_PIN                                                        0xfffe1030903d
12480 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MIN_GRANT                                                            0xfffe1030903e
12481 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MAX_LATENCY                                                          0xfffe1030903f
12482 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST                                                        0xfffe10309064
12483 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP                                                             0xfffe10309066
12484 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP                                                           0xfffe10309068
12485 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL                                                          0xfffe1030906c
12486 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS                                                        0xfffe1030906e
12487 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP                                                             0xfffe10309070
12488 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL                                                            0xfffe10309074
12489 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS                                                          0xfffe10309076
12490 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2                                                          0xfffe10309088
12491 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2                                                         0xfffe1030908c
12492 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS2                                                       0xfffe1030908e
12493 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2                                                            0xfffe10309090
12494 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2                                                           0xfffe10309094
12495 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2                                                         0xfffe10309096
12496 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST                                                         0xfffe103090a0
12497 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL                                                         0xfffe103090a2
12498 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_LO                                                      0xfffe103090a4
12499 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_HI                                                      0xfffe103090a8
12500 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA                                                         0xfffe103090a8
12501 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK                                                             0xfffe103090ac
12502 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_64                                                      0xfffe103090ac
12503 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_64                                                          0xfffe103090b0
12504 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING                                                          0xfffe103090b0
12505 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_64                                                       0xfffe103090b4
12506 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST                                                        0xfffe103090c0
12507 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL                                                        0xfffe103090c2
12508 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE                                                           0xfffe103090c4
12509 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA                                                             0xfffe103090c8
12510 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                    0xfffe10309100
12511 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR                                             0xfffe10309104
12512 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC1                                                0xfffe10309108
12513 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC2                                                0xfffe1030910c
12514 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                        0xfffe10309150
12515 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS                                               0xfffe10309154
12516 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK                                                 0xfffe10309158
12517 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY                                             0xfffe1030915c
12518 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS                                                 0xfffe10309160
12519 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK                                                   0xfffe10309164
12520 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL                                                0xfffe10309168
12521 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG0                                                        0xfffe1030916c
12522 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG1                                                        0xfffe10309170
12523 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG2                                                        0xfffe10309174
12524 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG3                                                        0xfffe10309178
12525 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG0                                                 0xfffe10309188
12526 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG1                                                 0xfffe1030918c
12527 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG2                                                 0xfffe10309190
12528 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG3                                                 0xfffe10309194
12529 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST                                                0xfffe103092b0
12530 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP                                                         0xfffe103092b4
12531 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CNTL                                                        0xfffe103092b6
12532 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST                                                0xfffe10309328
12533 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP                                                         0xfffe1030932c
12534 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL                                                        0xfffe1030932e
12535 
12536 
12537 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf10_bifcfgdecp
12538 // base address: 0xfffe1030a000
12539 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_VENDOR_ID                                                           0xfffe1030a000
12540 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_ID                                                           0xfffe1030a002
12541 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_COMMAND                                                             0xfffe1030a004
12542 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_STATUS                                                              0xfffe1030a006
12543 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID                                                         0xfffe1030a008
12544 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PROG_INTERFACE                                                      0xfffe1030a009
12545 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_SUB_CLASS                                                           0xfffe1030a00a
12546 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_CLASS                                                          0xfffe1030a00b
12547 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_CACHE_LINE                                                          0xfffe1030a00c
12548 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_LATENCY                                                             0xfffe1030a00d
12549 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_HEADER                                                              0xfffe1030a00e
12550 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BIST                                                                0xfffe1030a00f
12551 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_1                                                         0xfffe1030a010
12552 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_2                                                         0xfffe1030a014
12553 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_3                                                         0xfffe1030a018
12554 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_4                                                         0xfffe1030a01c
12555 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_5                                                         0xfffe1030a020
12556 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_6                                                         0xfffe1030a024
12557 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_CARDBUS_CIS_PTR                                                     0xfffe1030a028
12558 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID                                                          0xfffe1030a02c
12559 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR                                                       0xfffe1030a030
12560 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_CAP_PTR                                                             0xfffe1030a034
12561 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_LINE                                                      0xfffe1030a03c
12562 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_PIN                                                       0xfffe1030a03d
12563 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MIN_GRANT                                                           0xfffe1030a03e
12564 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MAX_LATENCY                                                         0xfffe1030a03f
12565 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST                                                       0xfffe1030a064
12566 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP                                                            0xfffe1030a066
12567 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP                                                          0xfffe1030a068
12568 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL                                                         0xfffe1030a06c
12569 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS                                                       0xfffe1030a06e
12570 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP                                                            0xfffe1030a070
12571 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL                                                           0xfffe1030a074
12572 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS                                                         0xfffe1030a076
12573 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2                                                         0xfffe1030a088
12574 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2                                                        0xfffe1030a08c
12575 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS2                                                      0xfffe1030a08e
12576 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2                                                           0xfffe1030a090
12577 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2                                                          0xfffe1030a094
12578 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2                                                        0xfffe1030a096
12579 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST                                                        0xfffe1030a0a0
12580 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL                                                        0xfffe1030a0a2
12581 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_LO                                                     0xfffe1030a0a4
12582 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_HI                                                     0xfffe1030a0a8
12583 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA                                                        0xfffe1030a0a8
12584 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK                                                            0xfffe1030a0ac
12585 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_64                                                     0xfffe1030a0ac
12586 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_64                                                         0xfffe1030a0b0
12587 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING                                                         0xfffe1030a0b0
12588 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_64                                                      0xfffe1030a0b4
12589 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST                                                       0xfffe1030a0c0
12590 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL                                                       0xfffe1030a0c2
12591 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE                                                          0xfffe1030a0c4
12592 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA                                                            0xfffe1030a0c8
12593 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0xfffe1030a100
12594 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR                                            0xfffe1030a104
12595 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC1                                               0xfffe1030a108
12596 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC2                                               0xfffe1030a10c
12597 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0xfffe1030a150
12598 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS                                              0xfffe1030a154
12599 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK                                                0xfffe1030a158
12600 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY                                            0xfffe1030a15c
12601 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS                                                0xfffe1030a160
12602 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK                                                  0xfffe1030a164
12603 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL                                               0xfffe1030a168
12604 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG0                                                       0xfffe1030a16c
12605 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG1                                                       0xfffe1030a170
12606 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG2                                                       0xfffe1030a174
12607 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG3                                                       0xfffe1030a178
12608 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG0                                                0xfffe1030a188
12609 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG1                                                0xfffe1030a18c
12610 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG2                                                0xfffe1030a190
12611 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG3                                                0xfffe1030a194
12612 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST                                               0xfffe1030a2b0
12613 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP                                                        0xfffe1030a2b4
12614 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CNTL                                                       0xfffe1030a2b6
12615 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST                                               0xfffe1030a328
12616 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP                                                        0xfffe1030a32c
12617 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL                                                       0xfffe1030a32e
12618 
12619 
12620 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf11_bifcfgdecp
12621 // base address: 0xfffe1030b000
12622 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_VENDOR_ID                                                           0xfffe1030b000
12623 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_ID                                                           0xfffe1030b002
12624 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_COMMAND                                                             0xfffe1030b004
12625 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_STATUS                                                              0xfffe1030b006
12626 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID                                                         0xfffe1030b008
12627 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PROG_INTERFACE                                                      0xfffe1030b009
12628 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_SUB_CLASS                                                           0xfffe1030b00a
12629 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_CLASS                                                          0xfffe1030b00b
12630 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_CACHE_LINE                                                          0xfffe1030b00c
12631 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_LATENCY                                                             0xfffe1030b00d
12632 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_HEADER                                                              0xfffe1030b00e
12633 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BIST                                                                0xfffe1030b00f
12634 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_1                                                         0xfffe1030b010
12635 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_2                                                         0xfffe1030b014
12636 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_3                                                         0xfffe1030b018
12637 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_4                                                         0xfffe1030b01c
12638 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_5                                                         0xfffe1030b020
12639 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_6                                                         0xfffe1030b024
12640 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_CARDBUS_CIS_PTR                                                     0xfffe1030b028
12641 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID                                                          0xfffe1030b02c
12642 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR                                                       0xfffe1030b030
12643 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_CAP_PTR                                                             0xfffe1030b034
12644 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_LINE                                                      0xfffe1030b03c
12645 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_PIN                                                       0xfffe1030b03d
12646 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MIN_GRANT                                                           0xfffe1030b03e
12647 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MAX_LATENCY                                                         0xfffe1030b03f
12648 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST                                                       0xfffe1030b064
12649 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP                                                            0xfffe1030b066
12650 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP                                                          0xfffe1030b068
12651 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL                                                         0xfffe1030b06c
12652 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS                                                       0xfffe1030b06e
12653 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP                                                            0xfffe1030b070
12654 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL                                                           0xfffe1030b074
12655 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS                                                         0xfffe1030b076
12656 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2                                                         0xfffe1030b088
12657 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2                                                        0xfffe1030b08c
12658 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS2                                                      0xfffe1030b08e
12659 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2                                                           0xfffe1030b090
12660 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2                                                          0xfffe1030b094
12661 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2                                                        0xfffe1030b096
12662 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST                                                        0xfffe1030b0a0
12663 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL                                                        0xfffe1030b0a2
12664 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_LO                                                     0xfffe1030b0a4
12665 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_HI                                                     0xfffe1030b0a8
12666 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA                                                        0xfffe1030b0a8
12667 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK                                                            0xfffe1030b0ac
12668 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_64                                                     0xfffe1030b0ac
12669 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_64                                                         0xfffe1030b0b0
12670 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING                                                         0xfffe1030b0b0
12671 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_64                                                      0xfffe1030b0b4
12672 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST                                                       0xfffe1030b0c0
12673 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL                                                       0xfffe1030b0c2
12674 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE                                                          0xfffe1030b0c4
12675 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA                                                            0xfffe1030b0c8
12676 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0xfffe1030b100
12677 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR                                            0xfffe1030b104
12678 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC1                                               0xfffe1030b108
12679 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC2                                               0xfffe1030b10c
12680 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0xfffe1030b150
12681 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS                                              0xfffe1030b154
12682 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK                                                0xfffe1030b158
12683 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY                                            0xfffe1030b15c
12684 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS                                                0xfffe1030b160
12685 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK                                                  0xfffe1030b164
12686 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL                                               0xfffe1030b168
12687 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG0                                                       0xfffe1030b16c
12688 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG1                                                       0xfffe1030b170
12689 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG2                                                       0xfffe1030b174
12690 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG3                                                       0xfffe1030b178
12691 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG0                                                0xfffe1030b188
12692 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG1                                                0xfffe1030b18c
12693 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG2                                                0xfffe1030b190
12694 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG3                                                0xfffe1030b194
12695 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST                                               0xfffe1030b2b0
12696 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP                                                        0xfffe1030b2b4
12697 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CNTL                                                       0xfffe1030b2b6
12698 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST                                               0xfffe1030b328
12699 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP                                                        0xfffe1030b32c
12700 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL                                                       0xfffe1030b32e
12701 
12702 
12703 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf12_bifcfgdecp
12704 // base address: 0xfffe1030c000
12705 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_VENDOR_ID                                                           0xfffe1030c000
12706 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_ID                                                           0xfffe1030c002
12707 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_COMMAND                                                             0xfffe1030c004
12708 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_STATUS                                                              0xfffe1030c006
12709 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID                                                         0xfffe1030c008
12710 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PROG_INTERFACE                                                      0xfffe1030c009
12711 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_SUB_CLASS                                                           0xfffe1030c00a
12712 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_CLASS                                                          0xfffe1030c00b
12713 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_CACHE_LINE                                                          0xfffe1030c00c
12714 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_LATENCY                                                             0xfffe1030c00d
12715 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_HEADER                                                              0xfffe1030c00e
12716 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BIST                                                                0xfffe1030c00f
12717 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_1                                                         0xfffe1030c010
12718 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_2                                                         0xfffe1030c014
12719 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_3                                                         0xfffe1030c018
12720 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_4                                                         0xfffe1030c01c
12721 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_5                                                         0xfffe1030c020
12722 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_6                                                         0xfffe1030c024
12723 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_CARDBUS_CIS_PTR                                                     0xfffe1030c028
12724 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID                                                          0xfffe1030c02c
12725 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR                                                       0xfffe1030c030
12726 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_CAP_PTR                                                             0xfffe1030c034
12727 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_LINE                                                      0xfffe1030c03c
12728 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_PIN                                                       0xfffe1030c03d
12729 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MIN_GRANT                                                           0xfffe1030c03e
12730 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MAX_LATENCY                                                         0xfffe1030c03f
12731 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST                                                       0xfffe1030c064
12732 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP                                                            0xfffe1030c066
12733 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP                                                          0xfffe1030c068
12734 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL                                                         0xfffe1030c06c
12735 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS                                                       0xfffe1030c06e
12736 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP                                                            0xfffe1030c070
12737 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL                                                           0xfffe1030c074
12738 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS                                                         0xfffe1030c076
12739 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2                                                         0xfffe1030c088
12740 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2                                                        0xfffe1030c08c
12741 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS2                                                      0xfffe1030c08e
12742 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2                                                           0xfffe1030c090
12743 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2                                                          0xfffe1030c094
12744 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2                                                        0xfffe1030c096
12745 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST                                                        0xfffe1030c0a0
12746 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL                                                        0xfffe1030c0a2
12747 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_LO                                                     0xfffe1030c0a4
12748 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_HI                                                     0xfffe1030c0a8
12749 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA                                                        0xfffe1030c0a8
12750 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK                                                            0xfffe1030c0ac
12751 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_64                                                     0xfffe1030c0ac
12752 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_64                                                         0xfffe1030c0b0
12753 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING                                                         0xfffe1030c0b0
12754 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_64                                                      0xfffe1030c0b4
12755 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST                                                       0xfffe1030c0c0
12756 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL                                                       0xfffe1030c0c2
12757 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE                                                          0xfffe1030c0c4
12758 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA                                                            0xfffe1030c0c8
12759 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0xfffe1030c100
12760 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR                                            0xfffe1030c104
12761 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC1                                               0xfffe1030c108
12762 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC2                                               0xfffe1030c10c
12763 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0xfffe1030c150
12764 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS                                              0xfffe1030c154
12765 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK                                                0xfffe1030c158
12766 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY                                            0xfffe1030c15c
12767 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS                                                0xfffe1030c160
12768 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK                                                  0xfffe1030c164
12769 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL                                               0xfffe1030c168
12770 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG0                                                       0xfffe1030c16c
12771 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG1                                                       0xfffe1030c170
12772 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG2                                                       0xfffe1030c174
12773 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG3                                                       0xfffe1030c178
12774 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG0                                                0xfffe1030c188
12775 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG1                                                0xfffe1030c18c
12776 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG2                                                0xfffe1030c190
12777 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG3                                                0xfffe1030c194
12778 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST                                               0xfffe1030c2b0
12779 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP                                                        0xfffe1030c2b4
12780 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CNTL                                                       0xfffe1030c2b6
12781 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST                                               0xfffe1030c328
12782 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP                                                        0xfffe1030c32c
12783 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL                                                       0xfffe1030c32e
12784 
12785 
12786 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf13_bifcfgdecp
12787 // base address: 0xfffe1030d000
12788 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_VENDOR_ID                                                           0xfffe1030d000
12789 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_ID                                                           0xfffe1030d002
12790 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_COMMAND                                                             0xfffe1030d004
12791 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_STATUS                                                              0xfffe1030d006
12792 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID                                                         0xfffe1030d008
12793 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PROG_INTERFACE                                                      0xfffe1030d009
12794 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_SUB_CLASS                                                           0xfffe1030d00a
12795 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_CLASS                                                          0xfffe1030d00b
12796 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_CACHE_LINE                                                          0xfffe1030d00c
12797 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_LATENCY                                                             0xfffe1030d00d
12798 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_HEADER                                                              0xfffe1030d00e
12799 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BIST                                                                0xfffe1030d00f
12800 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_1                                                         0xfffe1030d010
12801 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_2                                                         0xfffe1030d014
12802 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_3                                                         0xfffe1030d018
12803 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_4                                                         0xfffe1030d01c
12804 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_5                                                         0xfffe1030d020
12805 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_6                                                         0xfffe1030d024
12806 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_CARDBUS_CIS_PTR                                                     0xfffe1030d028
12807 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID                                                          0xfffe1030d02c
12808 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR                                                       0xfffe1030d030
12809 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_CAP_PTR                                                             0xfffe1030d034
12810 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_LINE                                                      0xfffe1030d03c
12811 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_PIN                                                       0xfffe1030d03d
12812 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MIN_GRANT                                                           0xfffe1030d03e
12813 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MAX_LATENCY                                                         0xfffe1030d03f
12814 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST                                                       0xfffe1030d064
12815 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP                                                            0xfffe1030d066
12816 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP                                                          0xfffe1030d068
12817 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL                                                         0xfffe1030d06c
12818 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS                                                       0xfffe1030d06e
12819 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP                                                            0xfffe1030d070
12820 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL                                                           0xfffe1030d074
12821 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS                                                         0xfffe1030d076
12822 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2                                                         0xfffe1030d088
12823 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2                                                        0xfffe1030d08c
12824 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS2                                                      0xfffe1030d08e
12825 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2                                                           0xfffe1030d090
12826 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2                                                          0xfffe1030d094
12827 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2                                                        0xfffe1030d096
12828 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST                                                        0xfffe1030d0a0
12829 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL                                                        0xfffe1030d0a2
12830 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_LO                                                     0xfffe1030d0a4
12831 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_HI                                                     0xfffe1030d0a8
12832 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA                                                        0xfffe1030d0a8
12833 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK                                                            0xfffe1030d0ac
12834 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_64                                                     0xfffe1030d0ac
12835 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_64                                                         0xfffe1030d0b0
12836 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING                                                         0xfffe1030d0b0
12837 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_64                                                      0xfffe1030d0b4
12838 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST                                                       0xfffe1030d0c0
12839 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL                                                       0xfffe1030d0c2
12840 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE                                                          0xfffe1030d0c4
12841 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA                                                            0xfffe1030d0c8
12842 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0xfffe1030d100
12843 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR                                            0xfffe1030d104
12844 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC1                                               0xfffe1030d108
12845 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC2                                               0xfffe1030d10c
12846 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0xfffe1030d150
12847 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS                                              0xfffe1030d154
12848 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK                                                0xfffe1030d158
12849 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY                                            0xfffe1030d15c
12850 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS                                                0xfffe1030d160
12851 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK                                                  0xfffe1030d164
12852 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL                                               0xfffe1030d168
12853 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG0                                                       0xfffe1030d16c
12854 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG1                                                       0xfffe1030d170
12855 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG2                                                       0xfffe1030d174
12856 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG3                                                       0xfffe1030d178
12857 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG0                                                0xfffe1030d188
12858 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG1                                                0xfffe1030d18c
12859 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG2                                                0xfffe1030d190
12860 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG3                                                0xfffe1030d194
12861 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST                                               0xfffe1030d2b0
12862 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP                                                        0xfffe1030d2b4
12863 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CNTL                                                       0xfffe1030d2b6
12864 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST                                               0xfffe1030d328
12865 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP                                                        0xfffe1030d32c
12866 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL                                                       0xfffe1030d32e
12867 
12868 
12869 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf14_bifcfgdecp
12870 // base address: 0xfffe1030e000
12871 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_VENDOR_ID                                                           0xfffe1030e000
12872 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_ID                                                           0xfffe1030e002
12873 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_COMMAND                                                             0xfffe1030e004
12874 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_STATUS                                                              0xfffe1030e006
12875 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID                                                         0xfffe1030e008
12876 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PROG_INTERFACE                                                      0xfffe1030e009
12877 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_SUB_CLASS                                                           0xfffe1030e00a
12878 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_CLASS                                                          0xfffe1030e00b
12879 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_CACHE_LINE                                                          0xfffe1030e00c
12880 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_LATENCY                                                             0xfffe1030e00d
12881 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_HEADER                                                              0xfffe1030e00e
12882 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BIST                                                                0xfffe1030e00f
12883 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_1                                                         0xfffe1030e010
12884 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_2                                                         0xfffe1030e014
12885 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_3                                                         0xfffe1030e018
12886 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_4                                                         0xfffe1030e01c
12887 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_5                                                         0xfffe1030e020
12888 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_6                                                         0xfffe1030e024
12889 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_CARDBUS_CIS_PTR                                                     0xfffe1030e028
12890 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID                                                          0xfffe1030e02c
12891 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR                                                       0xfffe1030e030
12892 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_CAP_PTR                                                             0xfffe1030e034
12893 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_LINE                                                      0xfffe1030e03c
12894 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_PIN                                                       0xfffe1030e03d
12895 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MIN_GRANT                                                           0xfffe1030e03e
12896 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MAX_LATENCY                                                         0xfffe1030e03f
12897 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST                                                       0xfffe1030e064
12898 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP                                                            0xfffe1030e066
12899 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP                                                          0xfffe1030e068
12900 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL                                                         0xfffe1030e06c
12901 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS                                                       0xfffe1030e06e
12902 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP                                                            0xfffe1030e070
12903 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL                                                           0xfffe1030e074
12904 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS                                                         0xfffe1030e076
12905 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2                                                         0xfffe1030e088
12906 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2                                                        0xfffe1030e08c
12907 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS2                                                      0xfffe1030e08e
12908 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2                                                           0xfffe1030e090
12909 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2                                                          0xfffe1030e094
12910 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2                                                        0xfffe1030e096
12911 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST                                                        0xfffe1030e0a0
12912 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL                                                        0xfffe1030e0a2
12913 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_LO                                                     0xfffe1030e0a4
12914 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_HI                                                     0xfffe1030e0a8
12915 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA                                                        0xfffe1030e0a8
12916 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK                                                            0xfffe1030e0ac
12917 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_64                                                     0xfffe1030e0ac
12918 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_64                                                         0xfffe1030e0b0
12919 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING                                                         0xfffe1030e0b0
12920 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_64                                                      0xfffe1030e0b4
12921 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST                                                       0xfffe1030e0c0
12922 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL                                                       0xfffe1030e0c2
12923 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE                                                          0xfffe1030e0c4
12924 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA                                                            0xfffe1030e0c8
12925 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0xfffe1030e100
12926 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR                                            0xfffe1030e104
12927 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC1                                               0xfffe1030e108
12928 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC2                                               0xfffe1030e10c
12929 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0xfffe1030e150
12930 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS                                              0xfffe1030e154
12931 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK                                                0xfffe1030e158
12932 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY                                            0xfffe1030e15c
12933 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS                                                0xfffe1030e160
12934 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK                                                  0xfffe1030e164
12935 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL                                               0xfffe1030e168
12936 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG0                                                       0xfffe1030e16c
12937 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG1                                                       0xfffe1030e170
12938 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG2                                                       0xfffe1030e174
12939 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG3                                                       0xfffe1030e178
12940 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG0                                                0xfffe1030e188
12941 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG1                                                0xfffe1030e18c
12942 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG2                                                0xfffe1030e190
12943 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG3                                                0xfffe1030e194
12944 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST                                               0xfffe1030e2b0
12945 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP                                                        0xfffe1030e2b4
12946 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CNTL                                                       0xfffe1030e2b6
12947 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST                                               0xfffe1030e328
12948 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP                                                        0xfffe1030e32c
12949 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL                                                       0xfffe1030e32e
12950 
12951 
12952 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf15_bifcfgdecp
12953 // base address: 0xfffe1030f000
12954 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_VENDOR_ID                                                           0xfffe1030f000
12955 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_ID                                                           0xfffe1030f002
12956 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_COMMAND                                                             0xfffe1030f004
12957 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_STATUS                                                              0xfffe1030f006
12958 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID                                                         0xfffe1030f008
12959 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PROG_INTERFACE                                                      0xfffe1030f009
12960 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_SUB_CLASS                                                           0xfffe1030f00a
12961 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_CLASS                                                          0xfffe1030f00b
12962 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_CACHE_LINE                                                          0xfffe1030f00c
12963 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_LATENCY                                                             0xfffe1030f00d
12964 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_HEADER                                                              0xfffe1030f00e
12965 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BIST                                                                0xfffe1030f00f
12966 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_1                                                         0xfffe1030f010
12967 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_2                                                         0xfffe1030f014
12968 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_3                                                         0xfffe1030f018
12969 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_4                                                         0xfffe1030f01c
12970 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_5                                                         0xfffe1030f020
12971 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_6                                                         0xfffe1030f024
12972 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_CARDBUS_CIS_PTR                                                     0xfffe1030f028
12973 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID                                                          0xfffe1030f02c
12974 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR                                                       0xfffe1030f030
12975 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_CAP_PTR                                                             0xfffe1030f034
12976 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_LINE                                                      0xfffe1030f03c
12977 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_PIN                                                       0xfffe1030f03d
12978 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MIN_GRANT                                                           0xfffe1030f03e
12979 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MAX_LATENCY                                                         0xfffe1030f03f
12980 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST                                                       0xfffe1030f064
12981 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP                                                            0xfffe1030f066
12982 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP                                                          0xfffe1030f068
12983 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL                                                         0xfffe1030f06c
12984 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS                                                       0xfffe1030f06e
12985 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP                                                            0xfffe1030f070
12986 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL                                                           0xfffe1030f074
12987 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS                                                         0xfffe1030f076
12988 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2                                                         0xfffe1030f088
12989 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2                                                        0xfffe1030f08c
12990 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS2                                                      0xfffe1030f08e
12991 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2                                                           0xfffe1030f090
12992 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2                                                          0xfffe1030f094
12993 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2                                                        0xfffe1030f096
12994 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST                                                        0xfffe1030f0a0
12995 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL                                                        0xfffe1030f0a2
12996 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_LO                                                     0xfffe1030f0a4
12997 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_HI                                                     0xfffe1030f0a8
12998 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA                                                        0xfffe1030f0a8
12999 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK                                                            0xfffe1030f0ac
13000 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_64                                                     0xfffe1030f0ac
13001 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_64                                                         0xfffe1030f0b0
13002 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING                                                         0xfffe1030f0b0
13003 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_64                                                      0xfffe1030f0b4
13004 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST                                                       0xfffe1030f0c0
13005 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL                                                       0xfffe1030f0c2
13006 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE                                                          0xfffe1030f0c4
13007 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA                                                            0xfffe1030f0c8
13008 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0xfffe1030f100
13009 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR                                            0xfffe1030f104
13010 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC1                                               0xfffe1030f108
13011 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC2                                               0xfffe1030f10c
13012 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0xfffe1030f150
13013 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS                                              0xfffe1030f154
13014 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK                                                0xfffe1030f158
13015 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY                                            0xfffe1030f15c
13016 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS                                                0xfffe1030f160
13017 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK                                                  0xfffe1030f164
13018 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL                                               0xfffe1030f168
13019 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG0                                                       0xfffe1030f16c
13020 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG1                                                       0xfffe1030f170
13021 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG2                                                       0xfffe1030f174
13022 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG3                                                       0xfffe1030f178
13023 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG0                                                0xfffe1030f188
13024 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG1                                                0xfffe1030f18c
13025 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG2                                                0xfffe1030f190
13026 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG3                                                0xfffe1030f194
13027 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST                                               0xfffe1030f2b0
13028 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP                                                        0xfffe1030f2b4
13029 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CNTL                                                       0xfffe1030f2b6
13030 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST                                               0xfffe1030f328
13031 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP                                                        0xfffe1030f32c
13032 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL                                                       0xfffe1030f32e
13033 
13034 
13035 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf16_bifcfgdecp
13036 // base address: 0xfffe10310000
13037 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_VENDOR_ID                                                           0xfffe10310000
13038 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_ID                                                           0xfffe10310002
13039 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_COMMAND                                                             0xfffe10310004
13040 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_STATUS                                                              0xfffe10310006
13041 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_REVISION_ID                                                         0xfffe10310008
13042 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PROG_INTERFACE                                                      0xfffe10310009
13043 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_SUB_CLASS                                                           0xfffe1031000a
13044 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_CLASS                                                          0xfffe1031000b
13045 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_CACHE_LINE                                                          0xfffe1031000c
13046 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_LATENCY                                                             0xfffe1031000d
13047 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_HEADER                                                              0xfffe1031000e
13048 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_BIST                                                                0xfffe1031000f
13049 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_1                                                         0xfffe10310010
13050 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_2                                                         0xfffe10310014
13051 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_3                                                         0xfffe10310018
13052 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_4                                                         0xfffe1031001c
13053 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_5                                                         0xfffe10310020
13054 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_6                                                         0xfffe10310024
13055 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_CARDBUS_CIS_PTR                                                     0xfffe10310028
13056 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_ADAPTER_ID                                                          0xfffe1031002c
13057 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_ROM_BASE_ADDR                                                       0xfffe10310030
13058 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_CAP_PTR                                                             0xfffe10310034
13059 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_INTERRUPT_LINE                                                      0xfffe1031003c
13060 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_INTERRUPT_PIN                                                       0xfffe1031003d
13061 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MIN_GRANT                                                           0xfffe1031003e
13062 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MAX_LATENCY                                                         0xfffe1031003f
13063 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP_LIST                                                       0xfffe10310064
13064 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP                                                            0xfffe10310066
13065 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP                                                          0xfffe10310068
13066 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL                                                         0xfffe1031006c
13067 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS                                                       0xfffe1031006e
13068 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP                                                            0xfffe10310070
13069 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL                                                           0xfffe10310074
13070 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS                                                         0xfffe10310076
13071 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2                                                         0xfffe10310088
13072 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2                                                        0xfffe1031008c
13073 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS2                                                      0xfffe1031008e
13074 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2                                                           0xfffe10310090
13075 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2                                                          0xfffe10310094
13076 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2                                                        0xfffe10310096
13077 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_CAP_LIST                                                        0xfffe103100a0
13078 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL                                                        0xfffe103100a2
13079 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_ADDR_LO                                                     0xfffe103100a4
13080 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_ADDR_HI                                                     0xfffe103100a8
13081 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_DATA                                                        0xfffe103100a8
13082 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MASK                                                            0xfffe103100ac
13083 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_DATA_64                                                     0xfffe103100ac
13084 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MASK_64                                                         0xfffe103100b0
13085 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_PENDING                                                         0xfffe103100b0
13086 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_PENDING_64                                                      0xfffe103100b4
13087 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSIX_CAP_LIST                                                       0xfffe103100c0
13088 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSIX_MSG_CNTL                                                       0xfffe103100c2
13089 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSIX_TABLE                                                          0xfffe103100c4
13090 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSIX_PBA                                                            0xfffe103100c8
13091 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0xfffe10310100
13092 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_HDR                                            0xfffe10310104
13093 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC1                                               0xfffe10310108
13094 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC2                                               0xfffe1031010c
13095 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0xfffe10310150
13096 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS                                              0xfffe10310154
13097 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK                                                0xfffe10310158
13098 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY                                            0xfffe1031015c
13099 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS                                                0xfffe10310160
13100 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK                                                  0xfffe10310164
13101 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL                                               0xfffe10310168
13102 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG0                                                       0xfffe1031016c
13103 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG1                                                       0xfffe10310170
13104 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG2                                                       0xfffe10310174
13105 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG3                                                       0xfffe10310178
13106 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG0                                                0xfffe10310188
13107 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG1                                                0xfffe1031018c
13108 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG2                                                0xfffe10310190
13109 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG3                                                0xfffe10310194
13110 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_ENH_CAP_LIST                                               0xfffe103102b0
13111 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CAP                                                        0xfffe103102b4
13112 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CNTL                                                       0xfffe103102b6
13113 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_ENH_CAP_LIST                                               0xfffe10310328
13114 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CAP                                                        0xfffe1031032c
13115 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CNTL                                                       0xfffe1031032e
13116 
13117 
13118 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf17_bifcfgdecp
13119 // base address: 0xfffe10311000
13120 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_VENDOR_ID                                                           0xfffe10311000
13121 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_ID                                                           0xfffe10311002
13122 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_COMMAND                                                             0xfffe10311004
13123 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_STATUS                                                              0xfffe10311006
13124 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_REVISION_ID                                                         0xfffe10311008
13125 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PROG_INTERFACE                                                      0xfffe10311009
13126 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_SUB_CLASS                                                           0xfffe1031100a
13127 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_CLASS                                                          0xfffe1031100b
13128 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_CACHE_LINE                                                          0xfffe1031100c
13129 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_LATENCY                                                             0xfffe1031100d
13130 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_HEADER                                                              0xfffe1031100e
13131 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_BIST                                                                0xfffe1031100f
13132 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_1                                                         0xfffe10311010
13133 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_2                                                         0xfffe10311014
13134 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_3                                                         0xfffe10311018
13135 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_4                                                         0xfffe1031101c
13136 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_5                                                         0xfffe10311020
13137 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_6                                                         0xfffe10311024
13138 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_CARDBUS_CIS_PTR                                                     0xfffe10311028
13139 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_ADAPTER_ID                                                          0xfffe1031102c
13140 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_ROM_BASE_ADDR                                                       0xfffe10311030
13141 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_CAP_PTR                                                             0xfffe10311034
13142 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_INTERRUPT_LINE                                                      0xfffe1031103c
13143 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_INTERRUPT_PIN                                                       0xfffe1031103d
13144 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MIN_GRANT                                                           0xfffe1031103e
13145 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MAX_LATENCY                                                         0xfffe1031103f
13146 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP_LIST                                                       0xfffe10311064
13147 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP                                                            0xfffe10311066
13148 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP                                                          0xfffe10311068
13149 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL                                                         0xfffe1031106c
13150 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS                                                       0xfffe1031106e
13151 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP                                                            0xfffe10311070
13152 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL                                                           0xfffe10311074
13153 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS                                                         0xfffe10311076
13154 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2                                                         0xfffe10311088
13155 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2                                                        0xfffe1031108c
13156 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS2                                                      0xfffe1031108e
13157 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2                                                           0xfffe10311090
13158 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2                                                          0xfffe10311094
13159 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2                                                        0xfffe10311096
13160 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_CAP_LIST                                                        0xfffe103110a0
13161 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL                                                        0xfffe103110a2
13162 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_ADDR_LO                                                     0xfffe103110a4
13163 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_ADDR_HI                                                     0xfffe103110a8
13164 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_DATA                                                        0xfffe103110a8
13165 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MASK                                                            0xfffe103110ac
13166 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_DATA_64                                                     0xfffe103110ac
13167 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MASK_64                                                         0xfffe103110b0
13168 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_PENDING                                                         0xfffe103110b0
13169 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_PENDING_64                                                      0xfffe103110b4
13170 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSIX_CAP_LIST                                                       0xfffe103110c0
13171 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSIX_MSG_CNTL                                                       0xfffe103110c2
13172 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSIX_TABLE                                                          0xfffe103110c4
13173 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSIX_PBA                                                            0xfffe103110c8
13174 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0xfffe10311100
13175 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_HDR                                            0xfffe10311104
13176 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC1                                               0xfffe10311108
13177 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC2                                               0xfffe1031110c
13178 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0xfffe10311150
13179 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS                                              0xfffe10311154
13180 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK                                                0xfffe10311158
13181 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY                                            0xfffe1031115c
13182 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS                                                0xfffe10311160
13183 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK                                                  0xfffe10311164
13184 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL                                               0xfffe10311168
13185 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG0                                                       0xfffe1031116c
13186 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG1                                                       0xfffe10311170
13187 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG2                                                       0xfffe10311174
13188 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG3                                                       0xfffe10311178
13189 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG0                                                0xfffe10311188
13190 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG1                                                0xfffe1031118c
13191 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG2                                                0xfffe10311190
13192 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG3                                                0xfffe10311194
13193 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_ENH_CAP_LIST                                               0xfffe103112b0
13194 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CAP                                                        0xfffe103112b4
13195 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CNTL                                                       0xfffe103112b6
13196 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_ENH_CAP_LIST                                               0xfffe10311328
13197 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CAP                                                        0xfffe1031132c
13198 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CNTL                                                       0xfffe1031132e
13199 
13200 
13201 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf18_bifcfgdecp
13202 // base address: 0xfffe10312000
13203 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_VENDOR_ID                                                           0xfffe10312000
13204 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_ID                                                           0xfffe10312002
13205 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_COMMAND                                                             0xfffe10312004
13206 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_STATUS                                                              0xfffe10312006
13207 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_REVISION_ID                                                         0xfffe10312008
13208 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PROG_INTERFACE                                                      0xfffe10312009
13209 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_SUB_CLASS                                                           0xfffe1031200a
13210 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_CLASS                                                          0xfffe1031200b
13211 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_CACHE_LINE                                                          0xfffe1031200c
13212 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_LATENCY                                                             0xfffe1031200d
13213 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_HEADER                                                              0xfffe1031200e
13214 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_BIST                                                                0xfffe1031200f
13215 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_1                                                         0xfffe10312010
13216 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_2                                                         0xfffe10312014
13217 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_3                                                         0xfffe10312018
13218 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_4                                                         0xfffe1031201c
13219 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_5                                                         0xfffe10312020
13220 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_6                                                         0xfffe10312024
13221 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_CARDBUS_CIS_PTR                                                     0xfffe10312028
13222 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_ADAPTER_ID                                                          0xfffe1031202c
13223 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_ROM_BASE_ADDR                                                       0xfffe10312030
13224 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_CAP_PTR                                                             0xfffe10312034
13225 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_INTERRUPT_LINE                                                      0xfffe1031203c
13226 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_INTERRUPT_PIN                                                       0xfffe1031203d
13227 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MIN_GRANT                                                           0xfffe1031203e
13228 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MAX_LATENCY                                                         0xfffe1031203f
13229 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP_LIST                                                       0xfffe10312064
13230 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP                                                            0xfffe10312066
13231 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP                                                          0xfffe10312068
13232 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL                                                         0xfffe1031206c
13233 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS                                                       0xfffe1031206e
13234 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP                                                            0xfffe10312070
13235 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL                                                           0xfffe10312074
13236 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS                                                         0xfffe10312076
13237 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2                                                         0xfffe10312088
13238 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2                                                        0xfffe1031208c
13239 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS2                                                      0xfffe1031208e
13240 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2                                                           0xfffe10312090
13241 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2                                                          0xfffe10312094
13242 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2                                                        0xfffe10312096
13243 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_CAP_LIST                                                        0xfffe103120a0
13244 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL                                                        0xfffe103120a2
13245 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_ADDR_LO                                                     0xfffe103120a4
13246 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_ADDR_HI                                                     0xfffe103120a8
13247 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_DATA                                                        0xfffe103120a8
13248 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MASK                                                            0xfffe103120ac
13249 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_DATA_64                                                     0xfffe103120ac
13250 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MASK_64                                                         0xfffe103120b0
13251 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_PENDING                                                         0xfffe103120b0
13252 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_PENDING_64                                                      0xfffe103120b4
13253 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSIX_CAP_LIST                                                       0xfffe103120c0
13254 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSIX_MSG_CNTL                                                       0xfffe103120c2
13255 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSIX_TABLE                                                          0xfffe103120c4
13256 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSIX_PBA                                                            0xfffe103120c8
13257 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0xfffe10312100
13258 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_HDR                                            0xfffe10312104
13259 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC1                                               0xfffe10312108
13260 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC2                                               0xfffe1031210c
13261 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0xfffe10312150
13262 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS                                              0xfffe10312154
13263 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK                                                0xfffe10312158
13264 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY                                            0xfffe1031215c
13265 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS                                                0xfffe10312160
13266 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK                                                  0xfffe10312164
13267 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL                                               0xfffe10312168
13268 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG0                                                       0xfffe1031216c
13269 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG1                                                       0xfffe10312170
13270 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG2                                                       0xfffe10312174
13271 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG3                                                       0xfffe10312178
13272 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG0                                                0xfffe10312188
13273 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG1                                                0xfffe1031218c
13274 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG2                                                0xfffe10312190
13275 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG3                                                0xfffe10312194
13276 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_ENH_CAP_LIST                                               0xfffe103122b0
13277 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CAP                                                        0xfffe103122b4
13278 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CNTL                                                       0xfffe103122b6
13279 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_ENH_CAP_LIST                                               0xfffe10312328
13280 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CAP                                                        0xfffe1031232c
13281 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CNTL                                                       0xfffe1031232e
13282 
13283 
13284 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf19_bifcfgdecp
13285 // base address: 0xfffe10313000
13286 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_VENDOR_ID                                                           0xfffe10313000
13287 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_ID                                                           0xfffe10313002
13288 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_COMMAND                                                             0xfffe10313004
13289 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_STATUS                                                              0xfffe10313006
13290 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_REVISION_ID                                                         0xfffe10313008
13291 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PROG_INTERFACE                                                      0xfffe10313009
13292 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_SUB_CLASS                                                           0xfffe1031300a
13293 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_CLASS                                                          0xfffe1031300b
13294 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_CACHE_LINE                                                          0xfffe1031300c
13295 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_LATENCY                                                             0xfffe1031300d
13296 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_HEADER                                                              0xfffe1031300e
13297 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_BIST                                                                0xfffe1031300f
13298 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_1                                                         0xfffe10313010
13299 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_2                                                         0xfffe10313014
13300 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_3                                                         0xfffe10313018
13301 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_4                                                         0xfffe1031301c
13302 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_5                                                         0xfffe10313020
13303 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_6                                                         0xfffe10313024
13304 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_CARDBUS_CIS_PTR                                                     0xfffe10313028
13305 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_ADAPTER_ID                                                          0xfffe1031302c
13306 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_ROM_BASE_ADDR                                                       0xfffe10313030
13307 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_CAP_PTR                                                             0xfffe10313034
13308 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_INTERRUPT_LINE                                                      0xfffe1031303c
13309 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_INTERRUPT_PIN                                                       0xfffe1031303d
13310 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MIN_GRANT                                                           0xfffe1031303e
13311 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MAX_LATENCY                                                         0xfffe1031303f
13312 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP_LIST                                                       0xfffe10313064
13313 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP                                                            0xfffe10313066
13314 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP                                                          0xfffe10313068
13315 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL                                                         0xfffe1031306c
13316 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS                                                       0xfffe1031306e
13317 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP                                                            0xfffe10313070
13318 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL                                                           0xfffe10313074
13319 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS                                                         0xfffe10313076
13320 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2                                                         0xfffe10313088
13321 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2                                                        0xfffe1031308c
13322 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS2                                                      0xfffe1031308e
13323 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2                                                           0xfffe10313090
13324 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2                                                          0xfffe10313094
13325 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2                                                        0xfffe10313096
13326 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_CAP_LIST                                                        0xfffe103130a0
13327 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL                                                        0xfffe103130a2
13328 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_ADDR_LO                                                     0xfffe103130a4
13329 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_ADDR_HI                                                     0xfffe103130a8
13330 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_DATA                                                        0xfffe103130a8
13331 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MASK                                                            0xfffe103130ac
13332 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_DATA_64                                                     0xfffe103130ac
13333 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MASK_64                                                         0xfffe103130b0
13334 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_PENDING                                                         0xfffe103130b0
13335 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_PENDING_64                                                      0xfffe103130b4
13336 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSIX_CAP_LIST                                                       0xfffe103130c0
13337 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSIX_MSG_CNTL                                                       0xfffe103130c2
13338 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSIX_TABLE                                                          0xfffe103130c4
13339 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSIX_PBA                                                            0xfffe103130c8
13340 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0xfffe10313100
13341 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_HDR                                            0xfffe10313104
13342 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC1                                               0xfffe10313108
13343 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC2                                               0xfffe1031310c
13344 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0xfffe10313150
13345 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS                                              0xfffe10313154
13346 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK                                                0xfffe10313158
13347 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY                                            0xfffe1031315c
13348 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS                                                0xfffe10313160
13349 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK                                                  0xfffe10313164
13350 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL                                               0xfffe10313168
13351 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG0                                                       0xfffe1031316c
13352 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG1                                                       0xfffe10313170
13353 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG2                                                       0xfffe10313174
13354 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG3                                                       0xfffe10313178
13355 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG0                                                0xfffe10313188
13356 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG1                                                0xfffe1031318c
13357 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG2                                                0xfffe10313190
13358 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG3                                                0xfffe10313194
13359 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_ENH_CAP_LIST                                               0xfffe103132b0
13360 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CAP                                                        0xfffe103132b4
13361 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CNTL                                                       0xfffe103132b6
13362 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_ENH_CAP_LIST                                               0xfffe10313328
13363 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CAP                                                        0xfffe1031332c
13364 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CNTL                                                       0xfffe1031332e
13365 
13366 
13367 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf20_bifcfgdecp
13368 // base address: 0xfffe10314000
13369 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_VENDOR_ID                                                           0xfffe10314000
13370 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_ID                                                           0xfffe10314002
13371 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_COMMAND                                                             0xfffe10314004
13372 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_STATUS                                                              0xfffe10314006
13373 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_REVISION_ID                                                         0xfffe10314008
13374 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PROG_INTERFACE                                                      0xfffe10314009
13375 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_SUB_CLASS                                                           0xfffe1031400a
13376 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_CLASS                                                          0xfffe1031400b
13377 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_CACHE_LINE                                                          0xfffe1031400c
13378 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_LATENCY                                                             0xfffe1031400d
13379 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_HEADER                                                              0xfffe1031400e
13380 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_BIST                                                                0xfffe1031400f
13381 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_1                                                         0xfffe10314010
13382 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_2                                                         0xfffe10314014
13383 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_3                                                         0xfffe10314018
13384 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_4                                                         0xfffe1031401c
13385 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_5                                                         0xfffe10314020
13386 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_6                                                         0xfffe10314024
13387 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_CARDBUS_CIS_PTR                                                     0xfffe10314028
13388 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_ADAPTER_ID                                                          0xfffe1031402c
13389 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_ROM_BASE_ADDR                                                       0xfffe10314030
13390 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_CAP_PTR                                                             0xfffe10314034
13391 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_INTERRUPT_LINE                                                      0xfffe1031403c
13392 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_INTERRUPT_PIN                                                       0xfffe1031403d
13393 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MIN_GRANT                                                           0xfffe1031403e
13394 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MAX_LATENCY                                                         0xfffe1031403f
13395 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP_LIST                                                       0xfffe10314064
13396 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP                                                            0xfffe10314066
13397 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP                                                          0xfffe10314068
13398 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL                                                         0xfffe1031406c
13399 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS                                                       0xfffe1031406e
13400 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP                                                            0xfffe10314070
13401 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL                                                           0xfffe10314074
13402 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS                                                         0xfffe10314076
13403 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2                                                         0xfffe10314088
13404 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2                                                        0xfffe1031408c
13405 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS2                                                      0xfffe1031408e
13406 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2                                                           0xfffe10314090
13407 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2                                                          0xfffe10314094
13408 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2                                                        0xfffe10314096
13409 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_CAP_LIST                                                        0xfffe103140a0
13410 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL                                                        0xfffe103140a2
13411 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_ADDR_LO                                                     0xfffe103140a4
13412 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_ADDR_HI                                                     0xfffe103140a8
13413 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_DATA                                                        0xfffe103140a8
13414 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MASK                                                            0xfffe103140ac
13415 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_DATA_64                                                     0xfffe103140ac
13416 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MASK_64                                                         0xfffe103140b0
13417 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_PENDING                                                         0xfffe103140b0
13418 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_PENDING_64                                                      0xfffe103140b4
13419 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSIX_CAP_LIST                                                       0xfffe103140c0
13420 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSIX_MSG_CNTL                                                       0xfffe103140c2
13421 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSIX_TABLE                                                          0xfffe103140c4
13422 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSIX_PBA                                                            0xfffe103140c8
13423 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0xfffe10314100
13424 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_HDR                                            0xfffe10314104
13425 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC1                                               0xfffe10314108
13426 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC2                                               0xfffe1031410c
13427 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0xfffe10314150
13428 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS                                              0xfffe10314154
13429 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK                                                0xfffe10314158
13430 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY                                            0xfffe1031415c
13431 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS                                                0xfffe10314160
13432 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK                                                  0xfffe10314164
13433 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL                                               0xfffe10314168
13434 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG0                                                       0xfffe1031416c
13435 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG1                                                       0xfffe10314170
13436 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG2                                                       0xfffe10314174
13437 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG3                                                       0xfffe10314178
13438 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG0                                                0xfffe10314188
13439 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG1                                                0xfffe1031418c
13440 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG2                                                0xfffe10314190
13441 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG3                                                0xfffe10314194
13442 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_ENH_CAP_LIST                                               0xfffe103142b0
13443 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CAP                                                        0xfffe103142b4
13444 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CNTL                                                       0xfffe103142b6
13445 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_ENH_CAP_LIST                                               0xfffe10314328
13446 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CAP                                                        0xfffe1031432c
13447 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CNTL                                                       0xfffe1031432e
13448 
13449 
13450 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf21_bifcfgdecp
13451 // base address: 0xfffe10315000
13452 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_VENDOR_ID                                                           0xfffe10315000
13453 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_ID                                                           0xfffe10315002
13454 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_COMMAND                                                             0xfffe10315004
13455 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_STATUS                                                              0xfffe10315006
13456 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_REVISION_ID                                                         0xfffe10315008
13457 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PROG_INTERFACE                                                      0xfffe10315009
13458 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_SUB_CLASS                                                           0xfffe1031500a
13459 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_CLASS                                                          0xfffe1031500b
13460 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_CACHE_LINE                                                          0xfffe1031500c
13461 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_LATENCY                                                             0xfffe1031500d
13462 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_HEADER                                                              0xfffe1031500e
13463 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_BIST                                                                0xfffe1031500f
13464 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_1                                                         0xfffe10315010
13465 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_2                                                         0xfffe10315014
13466 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_3                                                         0xfffe10315018
13467 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_4                                                         0xfffe1031501c
13468 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_5                                                         0xfffe10315020
13469 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_6                                                         0xfffe10315024
13470 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_CARDBUS_CIS_PTR                                                     0xfffe10315028
13471 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_ADAPTER_ID                                                          0xfffe1031502c
13472 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_ROM_BASE_ADDR                                                       0xfffe10315030
13473 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_CAP_PTR                                                             0xfffe10315034
13474 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_INTERRUPT_LINE                                                      0xfffe1031503c
13475 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_INTERRUPT_PIN                                                       0xfffe1031503d
13476 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MIN_GRANT                                                           0xfffe1031503e
13477 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MAX_LATENCY                                                         0xfffe1031503f
13478 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP_LIST                                                       0xfffe10315064
13479 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP                                                            0xfffe10315066
13480 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP                                                          0xfffe10315068
13481 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL                                                         0xfffe1031506c
13482 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS                                                       0xfffe1031506e
13483 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP                                                            0xfffe10315070
13484 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL                                                           0xfffe10315074
13485 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS                                                         0xfffe10315076
13486 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2                                                         0xfffe10315088
13487 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2                                                        0xfffe1031508c
13488 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS2                                                      0xfffe1031508e
13489 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2                                                           0xfffe10315090
13490 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2                                                          0xfffe10315094
13491 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2                                                        0xfffe10315096
13492 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_CAP_LIST                                                        0xfffe103150a0
13493 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL                                                        0xfffe103150a2
13494 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_ADDR_LO                                                     0xfffe103150a4
13495 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_ADDR_HI                                                     0xfffe103150a8
13496 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_DATA                                                        0xfffe103150a8
13497 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MASK                                                            0xfffe103150ac
13498 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_DATA_64                                                     0xfffe103150ac
13499 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MASK_64                                                         0xfffe103150b0
13500 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_PENDING                                                         0xfffe103150b0
13501 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_PENDING_64                                                      0xfffe103150b4
13502 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSIX_CAP_LIST                                                       0xfffe103150c0
13503 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSIX_MSG_CNTL                                                       0xfffe103150c2
13504 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSIX_TABLE                                                          0xfffe103150c4
13505 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSIX_PBA                                                            0xfffe103150c8
13506 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0xfffe10315100
13507 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_HDR                                            0xfffe10315104
13508 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC1                                               0xfffe10315108
13509 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC2                                               0xfffe1031510c
13510 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0xfffe10315150
13511 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS                                              0xfffe10315154
13512 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK                                                0xfffe10315158
13513 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY                                            0xfffe1031515c
13514 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS                                                0xfffe10315160
13515 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK                                                  0xfffe10315164
13516 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL                                               0xfffe10315168
13517 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG0                                                       0xfffe1031516c
13518 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG1                                                       0xfffe10315170
13519 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG2                                                       0xfffe10315174
13520 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG3                                                       0xfffe10315178
13521 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG0                                                0xfffe10315188
13522 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG1                                                0xfffe1031518c
13523 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG2                                                0xfffe10315190
13524 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG3                                                0xfffe10315194
13525 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_ENH_CAP_LIST                                               0xfffe103152b0
13526 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CAP                                                        0xfffe103152b4
13527 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CNTL                                                       0xfffe103152b6
13528 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_ENH_CAP_LIST                                               0xfffe10315328
13529 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CAP                                                        0xfffe1031532c
13530 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CNTL                                                       0xfffe1031532e
13531 
13532 
13533 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf22_bifcfgdecp
13534 // base address: 0xfffe10316000
13535 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_VENDOR_ID                                                           0xfffe10316000
13536 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_ID                                                           0xfffe10316002
13537 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_COMMAND                                                             0xfffe10316004
13538 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_STATUS                                                              0xfffe10316006
13539 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_REVISION_ID                                                         0xfffe10316008
13540 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PROG_INTERFACE                                                      0xfffe10316009
13541 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_SUB_CLASS                                                           0xfffe1031600a
13542 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_CLASS                                                          0xfffe1031600b
13543 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_CACHE_LINE                                                          0xfffe1031600c
13544 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_LATENCY                                                             0xfffe1031600d
13545 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_HEADER                                                              0xfffe1031600e
13546 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_BIST                                                                0xfffe1031600f
13547 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_1                                                         0xfffe10316010
13548 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_2                                                         0xfffe10316014
13549 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_3                                                         0xfffe10316018
13550 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_4                                                         0xfffe1031601c
13551 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_5                                                         0xfffe10316020
13552 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_6                                                         0xfffe10316024
13553 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_CARDBUS_CIS_PTR                                                     0xfffe10316028
13554 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_ADAPTER_ID                                                          0xfffe1031602c
13555 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_ROM_BASE_ADDR                                                       0xfffe10316030
13556 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_CAP_PTR                                                             0xfffe10316034
13557 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_INTERRUPT_LINE                                                      0xfffe1031603c
13558 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_INTERRUPT_PIN                                                       0xfffe1031603d
13559 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MIN_GRANT                                                           0xfffe1031603e
13560 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MAX_LATENCY                                                         0xfffe1031603f
13561 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP_LIST                                                       0xfffe10316064
13562 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP                                                            0xfffe10316066
13563 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP                                                          0xfffe10316068
13564 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL                                                         0xfffe1031606c
13565 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS                                                       0xfffe1031606e
13566 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP                                                            0xfffe10316070
13567 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL                                                           0xfffe10316074
13568 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS                                                         0xfffe10316076
13569 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2                                                         0xfffe10316088
13570 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2                                                        0xfffe1031608c
13571 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS2                                                      0xfffe1031608e
13572 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2                                                           0xfffe10316090
13573 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2                                                          0xfffe10316094
13574 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2                                                        0xfffe10316096
13575 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_CAP_LIST                                                        0xfffe103160a0
13576 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL                                                        0xfffe103160a2
13577 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_ADDR_LO                                                     0xfffe103160a4
13578 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_ADDR_HI                                                     0xfffe103160a8
13579 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_DATA                                                        0xfffe103160a8
13580 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MASK                                                            0xfffe103160ac
13581 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_DATA_64                                                     0xfffe103160ac
13582 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MASK_64                                                         0xfffe103160b0
13583 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_PENDING                                                         0xfffe103160b0
13584 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_PENDING_64                                                      0xfffe103160b4
13585 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSIX_CAP_LIST                                                       0xfffe103160c0
13586 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSIX_MSG_CNTL                                                       0xfffe103160c2
13587 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSIX_TABLE                                                          0xfffe103160c4
13588 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSIX_PBA                                                            0xfffe103160c8
13589 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0xfffe10316100
13590 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_HDR                                            0xfffe10316104
13591 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC1                                               0xfffe10316108
13592 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC2                                               0xfffe1031610c
13593 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0xfffe10316150
13594 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS                                              0xfffe10316154
13595 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK                                                0xfffe10316158
13596 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY                                            0xfffe1031615c
13597 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS                                                0xfffe10316160
13598 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK                                                  0xfffe10316164
13599 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL                                               0xfffe10316168
13600 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG0                                                       0xfffe1031616c
13601 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG1                                                       0xfffe10316170
13602 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG2                                                       0xfffe10316174
13603 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG3                                                       0xfffe10316178
13604 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG0                                                0xfffe10316188
13605 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG1                                                0xfffe1031618c
13606 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG2                                                0xfffe10316190
13607 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG3                                                0xfffe10316194
13608 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_ENH_CAP_LIST                                               0xfffe103162b0
13609 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CAP                                                        0xfffe103162b4
13610 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CNTL                                                       0xfffe103162b6
13611 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_ENH_CAP_LIST                                               0xfffe10316328
13612 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CAP                                                        0xfffe1031632c
13613 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CNTL                                                       0xfffe1031632e
13614 
13615 
13616 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf23_bifcfgdecp
13617 // base address: 0xfffe10317000
13618 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_VENDOR_ID                                                           0xfffe10317000
13619 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_ID                                                           0xfffe10317002
13620 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_COMMAND                                                             0xfffe10317004
13621 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_STATUS                                                              0xfffe10317006
13622 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_REVISION_ID                                                         0xfffe10317008
13623 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PROG_INTERFACE                                                      0xfffe10317009
13624 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_SUB_CLASS                                                           0xfffe1031700a
13625 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_CLASS                                                          0xfffe1031700b
13626 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_CACHE_LINE                                                          0xfffe1031700c
13627 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_LATENCY                                                             0xfffe1031700d
13628 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_HEADER                                                              0xfffe1031700e
13629 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_BIST                                                                0xfffe1031700f
13630 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_1                                                         0xfffe10317010
13631 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_2                                                         0xfffe10317014
13632 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_3                                                         0xfffe10317018
13633 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_4                                                         0xfffe1031701c
13634 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_5                                                         0xfffe10317020
13635 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_6                                                         0xfffe10317024
13636 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_CARDBUS_CIS_PTR                                                     0xfffe10317028
13637 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_ADAPTER_ID                                                          0xfffe1031702c
13638 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_ROM_BASE_ADDR                                                       0xfffe10317030
13639 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_CAP_PTR                                                             0xfffe10317034
13640 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_INTERRUPT_LINE                                                      0xfffe1031703c
13641 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_INTERRUPT_PIN                                                       0xfffe1031703d
13642 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MIN_GRANT                                                           0xfffe1031703e
13643 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MAX_LATENCY                                                         0xfffe1031703f
13644 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP_LIST                                                       0xfffe10317064
13645 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP                                                            0xfffe10317066
13646 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP                                                          0xfffe10317068
13647 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL                                                         0xfffe1031706c
13648 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS                                                       0xfffe1031706e
13649 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP                                                            0xfffe10317070
13650 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL                                                           0xfffe10317074
13651 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS                                                         0xfffe10317076
13652 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2                                                         0xfffe10317088
13653 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2                                                        0xfffe1031708c
13654 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS2                                                      0xfffe1031708e
13655 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2                                                           0xfffe10317090
13656 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2                                                          0xfffe10317094
13657 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2                                                        0xfffe10317096
13658 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_CAP_LIST                                                        0xfffe103170a0
13659 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL                                                        0xfffe103170a2
13660 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_ADDR_LO                                                     0xfffe103170a4
13661 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_ADDR_HI                                                     0xfffe103170a8
13662 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_DATA                                                        0xfffe103170a8
13663 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MASK                                                            0xfffe103170ac
13664 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_DATA_64                                                     0xfffe103170ac
13665 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MASK_64                                                         0xfffe103170b0
13666 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_PENDING                                                         0xfffe103170b0
13667 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_PENDING_64                                                      0xfffe103170b4
13668 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSIX_CAP_LIST                                                       0xfffe103170c0
13669 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSIX_MSG_CNTL                                                       0xfffe103170c2
13670 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSIX_TABLE                                                          0xfffe103170c4
13671 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSIX_PBA                                                            0xfffe103170c8
13672 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0xfffe10317100
13673 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_HDR                                            0xfffe10317104
13674 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC1                                               0xfffe10317108
13675 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC2                                               0xfffe1031710c
13676 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0xfffe10317150
13677 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS                                              0xfffe10317154
13678 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK                                                0xfffe10317158
13679 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY                                            0xfffe1031715c
13680 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS                                                0xfffe10317160
13681 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK                                                  0xfffe10317164
13682 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL                                               0xfffe10317168
13683 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG0                                                       0xfffe1031716c
13684 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG1                                                       0xfffe10317170
13685 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG2                                                       0xfffe10317174
13686 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG3                                                       0xfffe10317178
13687 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG0                                                0xfffe10317188
13688 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG1                                                0xfffe1031718c
13689 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG2                                                0xfffe10317190
13690 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG3                                                0xfffe10317194
13691 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_ENH_CAP_LIST                                               0xfffe103172b0
13692 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CAP                                                        0xfffe103172b4
13693 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CNTL                                                       0xfffe103172b6
13694 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_ENH_CAP_LIST                                               0xfffe10317328
13695 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CAP                                                        0xfffe1031732c
13696 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CNTL                                                       0xfffe1031732e
13697 
13698 
13699 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf24_bifcfgdecp
13700 // base address: 0xfffe10318000
13701 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_VENDOR_ID                                                           0xfffe10318000
13702 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_ID                                                           0xfffe10318002
13703 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_COMMAND                                                             0xfffe10318004
13704 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_STATUS                                                              0xfffe10318006
13705 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_REVISION_ID                                                         0xfffe10318008
13706 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PROG_INTERFACE                                                      0xfffe10318009
13707 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_SUB_CLASS                                                           0xfffe1031800a
13708 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_CLASS                                                          0xfffe1031800b
13709 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_CACHE_LINE                                                          0xfffe1031800c
13710 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_LATENCY                                                             0xfffe1031800d
13711 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_HEADER                                                              0xfffe1031800e
13712 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_BIST                                                                0xfffe1031800f
13713 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_1                                                         0xfffe10318010
13714 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_2                                                         0xfffe10318014
13715 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_3                                                         0xfffe10318018
13716 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_4                                                         0xfffe1031801c
13717 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_5                                                         0xfffe10318020
13718 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_6                                                         0xfffe10318024
13719 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_CARDBUS_CIS_PTR                                                     0xfffe10318028
13720 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_ADAPTER_ID                                                          0xfffe1031802c
13721 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_ROM_BASE_ADDR                                                       0xfffe10318030
13722 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_CAP_PTR                                                             0xfffe10318034
13723 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_INTERRUPT_LINE                                                      0xfffe1031803c
13724 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_INTERRUPT_PIN                                                       0xfffe1031803d
13725 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MIN_GRANT                                                           0xfffe1031803e
13726 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MAX_LATENCY                                                         0xfffe1031803f
13727 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP_LIST                                                       0xfffe10318064
13728 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP                                                            0xfffe10318066
13729 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP                                                          0xfffe10318068
13730 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL                                                         0xfffe1031806c
13731 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS                                                       0xfffe1031806e
13732 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP                                                            0xfffe10318070
13733 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL                                                           0xfffe10318074
13734 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS                                                         0xfffe10318076
13735 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2                                                         0xfffe10318088
13736 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2                                                        0xfffe1031808c
13737 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS2                                                      0xfffe1031808e
13738 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2                                                           0xfffe10318090
13739 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2                                                          0xfffe10318094
13740 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2                                                        0xfffe10318096
13741 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_CAP_LIST                                                        0xfffe103180a0
13742 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL                                                        0xfffe103180a2
13743 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_ADDR_LO                                                     0xfffe103180a4
13744 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_ADDR_HI                                                     0xfffe103180a8
13745 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_DATA                                                        0xfffe103180a8
13746 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MASK                                                            0xfffe103180ac
13747 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_DATA_64                                                     0xfffe103180ac
13748 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MASK_64                                                         0xfffe103180b0
13749 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_PENDING                                                         0xfffe103180b0
13750 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_PENDING_64                                                      0xfffe103180b4
13751 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSIX_CAP_LIST                                                       0xfffe103180c0
13752 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSIX_MSG_CNTL                                                       0xfffe103180c2
13753 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSIX_TABLE                                                          0xfffe103180c4
13754 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSIX_PBA                                                            0xfffe103180c8
13755 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0xfffe10318100
13756 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_HDR                                            0xfffe10318104
13757 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC1                                               0xfffe10318108
13758 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC2                                               0xfffe1031810c
13759 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0xfffe10318150
13760 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS                                              0xfffe10318154
13761 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK                                                0xfffe10318158
13762 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY                                            0xfffe1031815c
13763 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS                                                0xfffe10318160
13764 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK                                                  0xfffe10318164
13765 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL                                               0xfffe10318168
13766 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG0                                                       0xfffe1031816c
13767 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG1                                                       0xfffe10318170
13768 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG2                                                       0xfffe10318174
13769 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG3                                                       0xfffe10318178
13770 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG0                                                0xfffe10318188
13771 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG1                                                0xfffe1031818c
13772 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG2                                                0xfffe10318190
13773 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG3                                                0xfffe10318194
13774 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_ENH_CAP_LIST                                               0xfffe103182b0
13775 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CAP                                                        0xfffe103182b4
13776 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CNTL                                                       0xfffe103182b6
13777 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_ENH_CAP_LIST                                               0xfffe10318328
13778 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CAP                                                        0xfffe1031832c
13779 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CNTL                                                       0xfffe1031832e
13780 
13781 
13782 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf25_bifcfgdecp
13783 // base address: 0xfffe10319000
13784 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_VENDOR_ID                                                           0xfffe10319000
13785 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_ID                                                           0xfffe10319002
13786 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_COMMAND                                                             0xfffe10319004
13787 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_STATUS                                                              0xfffe10319006
13788 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_REVISION_ID                                                         0xfffe10319008
13789 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PROG_INTERFACE                                                      0xfffe10319009
13790 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_SUB_CLASS                                                           0xfffe1031900a
13791 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_CLASS                                                          0xfffe1031900b
13792 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_CACHE_LINE                                                          0xfffe1031900c
13793 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_LATENCY                                                             0xfffe1031900d
13794 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_HEADER                                                              0xfffe1031900e
13795 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_BIST                                                                0xfffe1031900f
13796 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_1                                                         0xfffe10319010
13797 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_2                                                         0xfffe10319014
13798 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_3                                                         0xfffe10319018
13799 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_4                                                         0xfffe1031901c
13800 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_5                                                         0xfffe10319020
13801 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_6                                                         0xfffe10319024
13802 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_CARDBUS_CIS_PTR                                                     0xfffe10319028
13803 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_ADAPTER_ID                                                          0xfffe1031902c
13804 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_ROM_BASE_ADDR                                                       0xfffe10319030
13805 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_CAP_PTR                                                             0xfffe10319034
13806 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_INTERRUPT_LINE                                                      0xfffe1031903c
13807 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_INTERRUPT_PIN                                                       0xfffe1031903d
13808 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MIN_GRANT                                                           0xfffe1031903e
13809 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MAX_LATENCY                                                         0xfffe1031903f
13810 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP_LIST                                                       0xfffe10319064
13811 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP                                                            0xfffe10319066
13812 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP                                                          0xfffe10319068
13813 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL                                                         0xfffe1031906c
13814 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS                                                       0xfffe1031906e
13815 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP                                                            0xfffe10319070
13816 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL                                                           0xfffe10319074
13817 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS                                                         0xfffe10319076
13818 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2                                                         0xfffe10319088
13819 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2                                                        0xfffe1031908c
13820 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS2                                                      0xfffe1031908e
13821 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2                                                           0xfffe10319090
13822 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2                                                          0xfffe10319094
13823 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2                                                        0xfffe10319096
13824 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_CAP_LIST                                                        0xfffe103190a0
13825 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL                                                        0xfffe103190a2
13826 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_ADDR_LO                                                     0xfffe103190a4
13827 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_ADDR_HI                                                     0xfffe103190a8
13828 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_DATA                                                        0xfffe103190a8
13829 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MASK                                                            0xfffe103190ac
13830 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_DATA_64                                                     0xfffe103190ac
13831 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MASK_64                                                         0xfffe103190b0
13832 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_PENDING                                                         0xfffe103190b0
13833 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_PENDING_64                                                      0xfffe103190b4
13834 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSIX_CAP_LIST                                                       0xfffe103190c0
13835 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSIX_MSG_CNTL                                                       0xfffe103190c2
13836 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSIX_TABLE                                                          0xfffe103190c4
13837 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSIX_PBA                                                            0xfffe103190c8
13838 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0xfffe10319100
13839 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_HDR                                            0xfffe10319104
13840 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC1                                               0xfffe10319108
13841 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC2                                               0xfffe1031910c
13842 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0xfffe10319150
13843 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS                                              0xfffe10319154
13844 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK                                                0xfffe10319158
13845 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY                                            0xfffe1031915c
13846 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS                                                0xfffe10319160
13847 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK                                                  0xfffe10319164
13848 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL                                               0xfffe10319168
13849 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG0                                                       0xfffe1031916c
13850 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG1                                                       0xfffe10319170
13851 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG2                                                       0xfffe10319174
13852 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG3                                                       0xfffe10319178
13853 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG0                                                0xfffe10319188
13854 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG1                                                0xfffe1031918c
13855 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG2                                                0xfffe10319190
13856 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG3                                                0xfffe10319194
13857 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_ENH_CAP_LIST                                               0xfffe103192b0
13858 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CAP                                                        0xfffe103192b4
13859 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CNTL                                                       0xfffe103192b6
13860 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_ENH_CAP_LIST                                               0xfffe10319328
13861 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CAP                                                        0xfffe1031932c
13862 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CNTL                                                       0xfffe1031932e
13863 
13864 
13865 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf26_bifcfgdecp
13866 // base address: 0xfffe1031a000
13867 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_VENDOR_ID                                                           0xfffe1031a000
13868 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_ID                                                           0xfffe1031a002
13869 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_COMMAND                                                             0xfffe1031a004
13870 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_STATUS                                                              0xfffe1031a006
13871 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_REVISION_ID                                                         0xfffe1031a008
13872 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PROG_INTERFACE                                                      0xfffe1031a009
13873 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_SUB_CLASS                                                           0xfffe1031a00a
13874 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_CLASS                                                          0xfffe1031a00b
13875 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_CACHE_LINE                                                          0xfffe1031a00c
13876 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_LATENCY                                                             0xfffe1031a00d
13877 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_HEADER                                                              0xfffe1031a00e
13878 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_BIST                                                                0xfffe1031a00f
13879 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_1                                                         0xfffe1031a010
13880 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_2                                                         0xfffe1031a014
13881 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_3                                                         0xfffe1031a018
13882 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_4                                                         0xfffe1031a01c
13883 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_5                                                         0xfffe1031a020
13884 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_6                                                         0xfffe1031a024
13885 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_CARDBUS_CIS_PTR                                                     0xfffe1031a028
13886 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_ADAPTER_ID                                                          0xfffe1031a02c
13887 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_ROM_BASE_ADDR                                                       0xfffe1031a030
13888 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_CAP_PTR                                                             0xfffe1031a034
13889 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_INTERRUPT_LINE                                                      0xfffe1031a03c
13890 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_INTERRUPT_PIN                                                       0xfffe1031a03d
13891 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MIN_GRANT                                                           0xfffe1031a03e
13892 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MAX_LATENCY                                                         0xfffe1031a03f
13893 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP_LIST                                                       0xfffe1031a064
13894 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP                                                            0xfffe1031a066
13895 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP                                                          0xfffe1031a068
13896 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL                                                         0xfffe1031a06c
13897 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS                                                       0xfffe1031a06e
13898 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP                                                            0xfffe1031a070
13899 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL                                                           0xfffe1031a074
13900 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS                                                         0xfffe1031a076
13901 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2                                                         0xfffe1031a088
13902 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2                                                        0xfffe1031a08c
13903 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS2                                                      0xfffe1031a08e
13904 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2                                                           0xfffe1031a090
13905 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2                                                          0xfffe1031a094
13906 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2                                                        0xfffe1031a096
13907 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_CAP_LIST                                                        0xfffe1031a0a0
13908 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL                                                        0xfffe1031a0a2
13909 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_ADDR_LO                                                     0xfffe1031a0a4
13910 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_ADDR_HI                                                     0xfffe1031a0a8
13911 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_DATA                                                        0xfffe1031a0a8
13912 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MASK                                                            0xfffe1031a0ac
13913 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_DATA_64                                                     0xfffe1031a0ac
13914 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MASK_64                                                         0xfffe1031a0b0
13915 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_PENDING                                                         0xfffe1031a0b0
13916 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_PENDING_64                                                      0xfffe1031a0b4
13917 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSIX_CAP_LIST                                                       0xfffe1031a0c0
13918 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSIX_MSG_CNTL                                                       0xfffe1031a0c2
13919 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSIX_TABLE                                                          0xfffe1031a0c4
13920 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSIX_PBA                                                            0xfffe1031a0c8
13921 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0xfffe1031a100
13922 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_HDR                                            0xfffe1031a104
13923 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC1                                               0xfffe1031a108
13924 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC2                                               0xfffe1031a10c
13925 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0xfffe1031a150
13926 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS                                              0xfffe1031a154
13927 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK                                                0xfffe1031a158
13928 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY                                            0xfffe1031a15c
13929 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS                                                0xfffe1031a160
13930 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK                                                  0xfffe1031a164
13931 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL                                               0xfffe1031a168
13932 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG0                                                       0xfffe1031a16c
13933 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG1                                                       0xfffe1031a170
13934 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG2                                                       0xfffe1031a174
13935 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG3                                                       0xfffe1031a178
13936 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG0                                                0xfffe1031a188
13937 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG1                                                0xfffe1031a18c
13938 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG2                                                0xfffe1031a190
13939 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG3                                                0xfffe1031a194
13940 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_ENH_CAP_LIST                                               0xfffe1031a2b0
13941 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CAP                                                        0xfffe1031a2b4
13942 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CNTL                                                       0xfffe1031a2b6
13943 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_ENH_CAP_LIST                                               0xfffe1031a328
13944 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CAP                                                        0xfffe1031a32c
13945 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CNTL                                                       0xfffe1031a32e
13946 
13947 
13948 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf27_bifcfgdecp
13949 // base address: 0xfffe1031b000
13950 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_VENDOR_ID                                                           0xfffe1031b000
13951 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_ID                                                           0xfffe1031b002
13952 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_COMMAND                                                             0xfffe1031b004
13953 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_STATUS                                                              0xfffe1031b006
13954 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_REVISION_ID                                                         0xfffe1031b008
13955 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PROG_INTERFACE                                                      0xfffe1031b009
13956 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_SUB_CLASS                                                           0xfffe1031b00a
13957 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_CLASS                                                          0xfffe1031b00b
13958 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_CACHE_LINE                                                          0xfffe1031b00c
13959 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_LATENCY                                                             0xfffe1031b00d
13960 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_HEADER                                                              0xfffe1031b00e
13961 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_BIST                                                                0xfffe1031b00f
13962 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_1                                                         0xfffe1031b010
13963 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_2                                                         0xfffe1031b014
13964 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_3                                                         0xfffe1031b018
13965 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_4                                                         0xfffe1031b01c
13966 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_5                                                         0xfffe1031b020
13967 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_6                                                         0xfffe1031b024
13968 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_CARDBUS_CIS_PTR                                                     0xfffe1031b028
13969 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_ADAPTER_ID                                                          0xfffe1031b02c
13970 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_ROM_BASE_ADDR                                                       0xfffe1031b030
13971 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_CAP_PTR                                                             0xfffe1031b034
13972 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_INTERRUPT_LINE                                                      0xfffe1031b03c
13973 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_INTERRUPT_PIN                                                       0xfffe1031b03d
13974 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MIN_GRANT                                                           0xfffe1031b03e
13975 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MAX_LATENCY                                                         0xfffe1031b03f
13976 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP_LIST                                                       0xfffe1031b064
13977 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP                                                            0xfffe1031b066
13978 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP                                                          0xfffe1031b068
13979 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL                                                         0xfffe1031b06c
13980 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS                                                       0xfffe1031b06e
13981 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP                                                            0xfffe1031b070
13982 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL                                                           0xfffe1031b074
13983 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS                                                         0xfffe1031b076
13984 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2                                                         0xfffe1031b088
13985 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2                                                        0xfffe1031b08c
13986 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS2                                                      0xfffe1031b08e
13987 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2                                                           0xfffe1031b090
13988 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2                                                          0xfffe1031b094
13989 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2                                                        0xfffe1031b096
13990 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_CAP_LIST                                                        0xfffe1031b0a0
13991 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL                                                        0xfffe1031b0a2
13992 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_ADDR_LO                                                     0xfffe1031b0a4
13993 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_ADDR_HI                                                     0xfffe1031b0a8
13994 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_DATA                                                        0xfffe1031b0a8
13995 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MASK                                                            0xfffe1031b0ac
13996 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_DATA_64                                                     0xfffe1031b0ac
13997 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MASK_64                                                         0xfffe1031b0b0
13998 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_PENDING                                                         0xfffe1031b0b0
13999 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_PENDING_64                                                      0xfffe1031b0b4
14000 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSIX_CAP_LIST                                                       0xfffe1031b0c0
14001 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSIX_MSG_CNTL                                                       0xfffe1031b0c2
14002 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSIX_TABLE                                                          0xfffe1031b0c4
14003 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSIX_PBA                                                            0xfffe1031b0c8
14004 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0xfffe1031b100
14005 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_HDR                                            0xfffe1031b104
14006 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC1                                               0xfffe1031b108
14007 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC2                                               0xfffe1031b10c
14008 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0xfffe1031b150
14009 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS                                              0xfffe1031b154
14010 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK                                                0xfffe1031b158
14011 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY                                            0xfffe1031b15c
14012 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS                                                0xfffe1031b160
14013 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK                                                  0xfffe1031b164
14014 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL                                               0xfffe1031b168
14015 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG0                                                       0xfffe1031b16c
14016 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG1                                                       0xfffe1031b170
14017 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG2                                                       0xfffe1031b174
14018 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG3                                                       0xfffe1031b178
14019 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG0                                                0xfffe1031b188
14020 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG1                                                0xfffe1031b18c
14021 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG2                                                0xfffe1031b190
14022 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG3                                                0xfffe1031b194
14023 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_ENH_CAP_LIST                                               0xfffe1031b2b0
14024 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CAP                                                        0xfffe1031b2b4
14025 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CNTL                                                       0xfffe1031b2b6
14026 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_ENH_CAP_LIST                                               0xfffe1031b328
14027 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CAP                                                        0xfffe1031b32c
14028 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CNTL                                                       0xfffe1031b32e
14029 
14030 
14031 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf28_bifcfgdecp
14032 // base address: 0xfffe1031c000
14033 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_VENDOR_ID                                                           0xfffe1031c000
14034 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_ID                                                           0xfffe1031c002
14035 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_COMMAND                                                             0xfffe1031c004
14036 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_STATUS                                                              0xfffe1031c006
14037 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_REVISION_ID                                                         0xfffe1031c008
14038 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PROG_INTERFACE                                                      0xfffe1031c009
14039 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_SUB_CLASS                                                           0xfffe1031c00a
14040 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_CLASS                                                          0xfffe1031c00b
14041 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_CACHE_LINE                                                          0xfffe1031c00c
14042 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_LATENCY                                                             0xfffe1031c00d
14043 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_HEADER                                                              0xfffe1031c00e
14044 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_BIST                                                                0xfffe1031c00f
14045 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_1                                                         0xfffe1031c010
14046 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_2                                                         0xfffe1031c014
14047 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_3                                                         0xfffe1031c018
14048 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_4                                                         0xfffe1031c01c
14049 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_5                                                         0xfffe1031c020
14050 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_6                                                         0xfffe1031c024
14051 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_CARDBUS_CIS_PTR                                                     0xfffe1031c028
14052 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_ADAPTER_ID                                                          0xfffe1031c02c
14053 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_ROM_BASE_ADDR                                                       0xfffe1031c030
14054 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_CAP_PTR                                                             0xfffe1031c034
14055 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_INTERRUPT_LINE                                                      0xfffe1031c03c
14056 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_INTERRUPT_PIN                                                       0xfffe1031c03d
14057 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MIN_GRANT                                                           0xfffe1031c03e
14058 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MAX_LATENCY                                                         0xfffe1031c03f
14059 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP_LIST                                                       0xfffe1031c064
14060 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP                                                            0xfffe1031c066
14061 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP                                                          0xfffe1031c068
14062 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL                                                         0xfffe1031c06c
14063 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS                                                       0xfffe1031c06e
14064 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP                                                            0xfffe1031c070
14065 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL                                                           0xfffe1031c074
14066 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS                                                         0xfffe1031c076
14067 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2                                                         0xfffe1031c088
14068 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2                                                        0xfffe1031c08c
14069 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS2                                                      0xfffe1031c08e
14070 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2                                                           0xfffe1031c090
14071 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2                                                          0xfffe1031c094
14072 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2                                                        0xfffe1031c096
14073 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_CAP_LIST                                                        0xfffe1031c0a0
14074 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL                                                        0xfffe1031c0a2
14075 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_ADDR_LO                                                     0xfffe1031c0a4
14076 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_ADDR_HI                                                     0xfffe1031c0a8
14077 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_DATA                                                        0xfffe1031c0a8
14078 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MASK                                                            0xfffe1031c0ac
14079 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_DATA_64                                                     0xfffe1031c0ac
14080 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MASK_64                                                         0xfffe1031c0b0
14081 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_PENDING                                                         0xfffe1031c0b0
14082 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_PENDING_64                                                      0xfffe1031c0b4
14083 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSIX_CAP_LIST                                                       0xfffe1031c0c0
14084 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSIX_MSG_CNTL                                                       0xfffe1031c0c2
14085 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSIX_TABLE                                                          0xfffe1031c0c4
14086 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSIX_PBA                                                            0xfffe1031c0c8
14087 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0xfffe1031c100
14088 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_HDR                                            0xfffe1031c104
14089 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC1                                               0xfffe1031c108
14090 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC2                                               0xfffe1031c10c
14091 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0xfffe1031c150
14092 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS                                              0xfffe1031c154
14093 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK                                                0xfffe1031c158
14094 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY                                            0xfffe1031c15c
14095 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS                                                0xfffe1031c160
14096 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK                                                  0xfffe1031c164
14097 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL                                               0xfffe1031c168
14098 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG0                                                       0xfffe1031c16c
14099 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG1                                                       0xfffe1031c170
14100 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG2                                                       0xfffe1031c174
14101 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG3                                                       0xfffe1031c178
14102 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG0                                                0xfffe1031c188
14103 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG1                                                0xfffe1031c18c
14104 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG2                                                0xfffe1031c190
14105 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG3                                                0xfffe1031c194
14106 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_ENH_CAP_LIST                                               0xfffe1031c2b0
14107 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CAP                                                        0xfffe1031c2b4
14108 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CNTL                                                       0xfffe1031c2b6
14109 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_ENH_CAP_LIST                                               0xfffe1031c328
14110 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CAP                                                        0xfffe1031c32c
14111 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CNTL                                                       0xfffe1031c32e
14112 
14113 
14114 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf29_bifcfgdecp
14115 // base address: 0xfffe1031d000
14116 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_VENDOR_ID                                                           0xfffe1031d000
14117 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_ID                                                           0xfffe1031d002
14118 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_COMMAND                                                             0xfffe1031d004
14119 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_STATUS                                                              0xfffe1031d006
14120 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_REVISION_ID                                                         0xfffe1031d008
14121 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PROG_INTERFACE                                                      0xfffe1031d009
14122 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_SUB_CLASS                                                           0xfffe1031d00a
14123 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_CLASS                                                          0xfffe1031d00b
14124 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_CACHE_LINE                                                          0xfffe1031d00c
14125 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_LATENCY                                                             0xfffe1031d00d
14126 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_HEADER                                                              0xfffe1031d00e
14127 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_BIST                                                                0xfffe1031d00f
14128 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_1                                                         0xfffe1031d010
14129 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_2                                                         0xfffe1031d014
14130 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_3                                                         0xfffe1031d018
14131 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_4                                                         0xfffe1031d01c
14132 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_5                                                         0xfffe1031d020
14133 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_6                                                         0xfffe1031d024
14134 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_CARDBUS_CIS_PTR                                                     0xfffe1031d028
14135 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_ADAPTER_ID                                                          0xfffe1031d02c
14136 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_ROM_BASE_ADDR                                                       0xfffe1031d030
14137 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_CAP_PTR                                                             0xfffe1031d034
14138 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_INTERRUPT_LINE                                                      0xfffe1031d03c
14139 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_INTERRUPT_PIN                                                       0xfffe1031d03d
14140 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MIN_GRANT                                                           0xfffe1031d03e
14141 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MAX_LATENCY                                                         0xfffe1031d03f
14142 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP_LIST                                                       0xfffe1031d064
14143 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP                                                            0xfffe1031d066
14144 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP                                                          0xfffe1031d068
14145 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL                                                         0xfffe1031d06c
14146 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS                                                       0xfffe1031d06e
14147 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP                                                            0xfffe1031d070
14148 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL                                                           0xfffe1031d074
14149 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS                                                         0xfffe1031d076
14150 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2                                                         0xfffe1031d088
14151 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2                                                        0xfffe1031d08c
14152 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS2                                                      0xfffe1031d08e
14153 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2                                                           0xfffe1031d090
14154 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2                                                          0xfffe1031d094
14155 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2                                                        0xfffe1031d096
14156 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_CAP_LIST                                                        0xfffe1031d0a0
14157 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL                                                        0xfffe1031d0a2
14158 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_ADDR_LO                                                     0xfffe1031d0a4
14159 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_ADDR_HI                                                     0xfffe1031d0a8
14160 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_DATA                                                        0xfffe1031d0a8
14161 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MASK                                                            0xfffe1031d0ac
14162 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_DATA_64                                                     0xfffe1031d0ac
14163 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MASK_64                                                         0xfffe1031d0b0
14164 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_PENDING                                                         0xfffe1031d0b0
14165 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_PENDING_64                                                      0xfffe1031d0b4
14166 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSIX_CAP_LIST                                                       0xfffe1031d0c0
14167 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSIX_MSG_CNTL                                                       0xfffe1031d0c2
14168 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSIX_TABLE                                                          0xfffe1031d0c4
14169 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSIX_PBA                                                            0xfffe1031d0c8
14170 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0xfffe1031d100
14171 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_HDR                                            0xfffe1031d104
14172 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC1                                               0xfffe1031d108
14173 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC2                                               0xfffe1031d10c
14174 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0xfffe1031d150
14175 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS                                              0xfffe1031d154
14176 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK                                                0xfffe1031d158
14177 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY                                            0xfffe1031d15c
14178 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS                                                0xfffe1031d160
14179 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK                                                  0xfffe1031d164
14180 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL                                               0xfffe1031d168
14181 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG0                                                       0xfffe1031d16c
14182 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG1                                                       0xfffe1031d170
14183 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG2                                                       0xfffe1031d174
14184 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG3                                                       0xfffe1031d178
14185 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG0                                                0xfffe1031d188
14186 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG1                                                0xfffe1031d18c
14187 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG2                                                0xfffe1031d190
14188 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG3                                                0xfffe1031d194
14189 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_ENH_CAP_LIST                                               0xfffe1031d2b0
14190 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CAP                                                        0xfffe1031d2b4
14191 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CNTL                                                       0xfffe1031d2b6
14192 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_ENH_CAP_LIST                                               0xfffe1031d328
14193 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CAP                                                        0xfffe1031d32c
14194 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CNTL                                                       0xfffe1031d32e
14195 
14196 
14197 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf30_bifcfgdecp
14198 // base address: 0xfffe1031e000
14199 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_VENDOR_ID                                                           0xfffe1031e000
14200 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_ID                                                           0xfffe1031e002
14201 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_COMMAND                                                             0xfffe1031e004
14202 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_STATUS                                                              0xfffe1031e006
14203 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_REVISION_ID                                                         0xfffe1031e008
14204 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PROG_INTERFACE                                                      0xfffe1031e009
14205 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_SUB_CLASS                                                           0xfffe1031e00a
14206 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_CLASS                                                          0xfffe1031e00b
14207 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_CACHE_LINE                                                          0xfffe1031e00c
14208 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_LATENCY                                                             0xfffe1031e00d
14209 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_HEADER                                                              0xfffe1031e00e
14210 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_BIST                                                                0xfffe1031e00f
14211 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_1                                                         0xfffe1031e010
14212 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_2                                                         0xfffe1031e014
14213 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_3                                                         0xfffe1031e018
14214 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_4                                                         0xfffe1031e01c
14215 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_5                                                         0xfffe1031e020
14216 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_6                                                         0xfffe1031e024
14217 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_CARDBUS_CIS_PTR                                                     0xfffe1031e028
14218 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_ADAPTER_ID                                                          0xfffe1031e02c
14219 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_ROM_BASE_ADDR                                                       0xfffe1031e030
14220 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_CAP_PTR                                                             0xfffe1031e034
14221 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_INTERRUPT_LINE                                                      0xfffe1031e03c
14222 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_INTERRUPT_PIN                                                       0xfffe1031e03d
14223 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MIN_GRANT                                                           0xfffe1031e03e
14224 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MAX_LATENCY                                                         0xfffe1031e03f
14225 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP_LIST                                                       0xfffe1031e064
14226 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP                                                            0xfffe1031e066
14227 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP                                                          0xfffe1031e068
14228 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL                                                         0xfffe1031e06c
14229 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS                                                       0xfffe1031e06e
14230 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP                                                            0xfffe1031e070
14231 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL                                                           0xfffe1031e074
14232 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS                                                         0xfffe1031e076
14233 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2                                                         0xfffe1031e088
14234 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2                                                        0xfffe1031e08c
14235 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS2                                                      0xfffe1031e08e
14236 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2                                                           0xfffe1031e090
14237 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2                                                          0xfffe1031e094
14238 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2                                                        0xfffe1031e096
14239 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_CAP_LIST                                                        0xfffe1031e0a0
14240 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL                                                        0xfffe1031e0a2
14241 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_ADDR_LO                                                     0xfffe1031e0a4
14242 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_ADDR_HI                                                     0xfffe1031e0a8
14243 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_DATA                                                        0xfffe1031e0a8
14244 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MASK                                                            0xfffe1031e0ac
14245 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_DATA_64                                                     0xfffe1031e0ac
14246 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MASK_64                                                         0xfffe1031e0b0
14247 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_PENDING                                                         0xfffe1031e0b0
14248 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_PENDING_64                                                      0xfffe1031e0b4
14249 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSIX_CAP_LIST                                                       0xfffe1031e0c0
14250 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSIX_MSG_CNTL                                                       0xfffe1031e0c2
14251 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSIX_TABLE                                                          0xfffe1031e0c4
14252 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSIX_PBA                                                            0xfffe1031e0c8
14253 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                   0xfffe1031e100
14254 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_HDR                                            0xfffe1031e104
14255 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC1                                               0xfffe1031e108
14256 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC2                                               0xfffe1031e10c
14257 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                       0xfffe1031e150
14258 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS                                              0xfffe1031e154
14259 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK                                                0xfffe1031e158
14260 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY                                            0xfffe1031e15c
14261 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS                                                0xfffe1031e160
14262 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK                                                  0xfffe1031e164
14263 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL                                               0xfffe1031e168
14264 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG0                                                       0xfffe1031e16c
14265 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG1                                                       0xfffe1031e170
14266 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG2                                                       0xfffe1031e174
14267 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG3                                                       0xfffe1031e178
14268 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG0                                                0xfffe1031e188
14269 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG1                                                0xfffe1031e18c
14270 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG2                                                0xfffe1031e190
14271 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG3                                                0xfffe1031e194
14272 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_ENH_CAP_LIST                                               0xfffe1031e2b0
14273 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CAP                                                        0xfffe1031e2b4
14274 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CNTL                                                       0xfffe1031e2b6
14275 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_ENH_CAP_LIST                                               0xfffe1031e328
14276 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CAP                                                        0xfffe1031e32c
14277 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CNTL                                                       0xfffe1031e32e
14278 
14279 
14280 // addressBlock: nbio_nbif0_rcc_shadow_reg_shadowdec
14281 // base address: 0xfffe30000000
14282 #define cfgSHADOW_COMMAND                                                                               0xfffe30000004
14283 #define cfgSHADOW_BASE_ADDR_1                                                                           0xfffe30000010
14284 #define cfgSHADOW_BASE_ADDR_2                                                                           0xfffe30000014
14285 #define cfgSHADOW_SUB_BUS_NUMBER_LATENCY                                                                0xfffe30000018
14286 #define cfgSHADOW_IO_BASE_LIMIT                                                                         0xfffe3000001c
14287 #define cfgSHADOW_MEM_BASE_LIMIT                                                                        0xfffe30000020
14288 #define cfgSHADOW_PREF_BASE_LIMIT                                                                       0xfffe30000024
14289 #define cfgSHADOW_PREF_BASE_UPPER                                                                       0xfffe30000028
14290 #define cfgSHADOW_PREF_LIMIT_UPPER                                                                      0xfffe3000002c
14291 #define cfgSHADOW_IO_BASE_LIMIT_HI                                                                      0xfffe30000030
14292 #define cfgSHADOW_IRQ_BRIDGE_CNTL                                                                       0xfffe3000003e
14293 #define cfgSUC_INDEX                                                                                    0xfffe300000e0
14294 #define cfgSUC_DATA                                                                                     0xfffe300000e4
14295 
14296 
14297 // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC
14298 // base address: 0x30300000
14299 #define cfgBIF_BX_PF1_MM_INDEX                                                                          0x30300000
14300 #define cfgBIF_BX_PF1_MM_DATA                                                                           0x30300004
14301 #define cfgBIF_BX_PF1_MM_INDEX_HI                                                                       0x30300018
14302 
14303 
14304 // addressBlock: nbio_nbif0_bif_bx_SYSDEC
14305 // base address: 0x30300000
14306 #define cfgSYSHUB_INDEX_OVLP                                                                            0x30300020
14307 #define cfgSYSHUB_DATA_OVLP                                                                             0x30300024
14308 #define cfgPCIE_INDEX                                                                                   0x30300030
14309 #define cfgPCIE_DATA                                                                                    0x30300034
14310 #define cfgPCIE_INDEX2                                                                                  0x30300038
14311 #define cfgPCIE_DATA2                                                                                   0x3030003c
14312 #define cfgSBIOS_SCRATCH_0                                                                              0x30300120
14313 #define cfgSBIOS_SCRATCH_1                                                                              0x30300124
14314 #define cfgSBIOS_SCRATCH_2                                                                              0x30300128
14315 #define cfgSBIOS_SCRATCH_3                                                                              0x3030012c
14316 #define cfgBIOS_SCRATCH_0                                                                               0x30300130
14317 #define cfgBIOS_SCRATCH_1                                                                               0x30300134
14318 #define cfgBIOS_SCRATCH_2                                                                               0x30300138
14319 #define cfgBIOS_SCRATCH_3                                                                               0x3030013c
14320 #define cfgBIOS_SCRATCH_4                                                                               0x30300140
14321 #define cfgBIOS_SCRATCH_5                                                                               0x30300144
14322 #define cfgBIOS_SCRATCH_6                                                                               0x30300148
14323 #define cfgBIOS_SCRATCH_7                                                                               0x3030014c
14324 #define cfgBIOS_SCRATCH_8                                                                               0x30300150
14325 #define cfgBIOS_SCRATCH_9                                                                               0x30300154
14326 #define cfgBIOS_SCRATCH_10                                                                              0x30300158
14327 #define cfgBIOS_SCRATCH_11                                                                              0x3030015c
14328 #define cfgBIOS_SCRATCH_12                                                                              0x30300160
14329 #define cfgBIOS_SCRATCH_13                                                                              0x30300164
14330 #define cfgBIOS_SCRATCH_14                                                                              0x30300168
14331 #define cfgBIOS_SCRATCH_15                                                                              0x3030016c
14332 #define cfgBIF_RLC_INTR_CNTL                                                                            0x30300180
14333 #define cfgBIF_VCE_INTR_CNTL                                                                            0x30300184
14334 #define cfgBIF_UVD_INTR_CNTL                                                                            0x30300188
14335 #define cfgGFX_MMIOREG_CAM_ADDR0                                                                        0x30300200
14336 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR0                                                                  0x30300204
14337 #define cfgGFX_MMIOREG_CAM_ADDR1                                                                        0x30300208
14338 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR1                                                                  0x3030020c
14339 #define cfgGFX_MMIOREG_CAM_ADDR2                                                                        0x30300210
14340 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR2                                                                  0x30300214
14341 #define cfgGFX_MMIOREG_CAM_ADDR3                                                                        0x30300218
14342 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR3                                                                  0x3030021c
14343 #define cfgGFX_MMIOREG_CAM_ADDR4                                                                        0x30300220
14344 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR4                                                                  0x30300224
14345 #define cfgGFX_MMIOREG_CAM_ADDR5                                                                        0x30300228
14346 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR5                                                                  0x3030022c
14347 #define cfgGFX_MMIOREG_CAM_ADDR6                                                                        0x30300230
14348 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR6                                                                  0x30300234
14349 #define cfgGFX_MMIOREG_CAM_ADDR7                                                                        0x30300238
14350 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR7                                                                  0x3030023c
14351 #define cfgGFX_MMIOREG_CAM_CNTL                                                                         0x30300240
14352 #define cfgGFX_MMIOREG_CAM_ZERO_CPL                                                                     0x30300244
14353 #define cfgGFX_MMIOREG_CAM_ONE_CPL                                                                      0x30300248
14354 #define cfgGFX_MMIOREG_CAM_PROGRAMMABLE_CPL                                                             0x3030024c
14355 
14356 
14357 // addressBlock: nbio_nbif0_syshub_mmreg_syshubdec
14358 // base address: 0x30300000
14359 #define cfgSYSHUB_INDEX                                                                                 0x30300020
14360 #define cfgSYSHUB_DATA                                                                                  0x30300024
14361 
14362 
14363 // addressBlock: nbio_nbif0_rcc_strap_BIFDEC1
14364 // base address: 0x30300000
14365 #define cfgRCC_BIF_STRAP0                                                                               0x30303480
14366 #define cfgRCC_BIF_STRAP1                                                                               0x30303484
14367 #define cfgRCC_BIF_STRAP2                                                                               0x30303488
14368 #define cfgRCC_BIF_STRAP3                                                                               0x3030348c
14369 #define cfgRCC_BIF_STRAP4                                                                               0x30303490
14370 #define cfgRCC_BIF_STRAP5                                                                               0x30303494
14371 #define cfgRCC_BIF_STRAP6                                                                               0x30303498
14372 #define cfgRCC_DEV0_PORT_STRAP0                                                                         0x3030349c
14373 #define cfgRCC_DEV0_PORT_STRAP1                                                                         0x303034a0
14374 #define cfgRCC_DEV0_PORT_STRAP2                                                                         0x303034a4
14375 #define cfgRCC_DEV0_PORT_STRAP3                                                                         0x303034a8
14376 #define cfgRCC_DEV0_PORT_STRAP4                                                                         0x303034ac
14377 #define cfgRCC_DEV0_PORT_STRAP5                                                                         0x303034b0
14378 #define cfgRCC_DEV0_PORT_STRAP6                                                                         0x303034b4
14379 #define cfgRCC_DEV0_PORT_STRAP7                                                                         0x303034b8
14380 #define cfgRCC_DEV0_PORT_STRAP8                                                                         0x303034bc
14381 #define cfgRCC_DEV0_PORT_STRAP9                                                                         0x303034c0
14382 #define cfgRCC_DEV0_EPF0_STRAP0                                                                         0x303034c4
14383 #define cfgRCC_DEV0_EPF0_STRAP1                                                                         0x303034c8
14384 #define cfgRCC_DEV0_EPF0_STRAP13                                                                        0x303034cc
14385 #define cfgRCC_DEV0_EPF0_STRAP2                                                                         0x303034d0
14386 #define cfgRCC_DEV0_EPF0_STRAP3                                                                         0x303034d4
14387 #define cfgRCC_DEV0_EPF0_STRAP4                                                                         0x303034d8
14388 #define cfgRCC_DEV0_EPF0_STRAP5                                                                         0x303034dc
14389 #define cfgRCC_DEV0_EPF0_STRAP8                                                                         0x303034e0
14390 #define cfgRCC_DEV0_EPF0_STRAP9                                                                         0x303034e4
14391 #define cfgRCC_DEV0_EPF1_STRAP0                                                                         0x303034e8
14392 #define cfgRCC_DEV0_EPF1_STRAP10                                                                        0x303034ec
14393 #define cfgRCC_DEV0_EPF1_STRAP11                                                                        0x303034f0
14394 #define cfgRCC_DEV0_EPF1_STRAP12                                                                        0x303034f4
14395 #define cfgRCC_DEV0_EPF1_STRAP13                                                                        0x303034f8
14396 #define cfgRCC_DEV0_EPF1_STRAP2                                                                         0x303034fc
14397 #define cfgRCC_DEV0_EPF1_STRAP3                                                                         0x30303500
14398 #define cfgRCC_DEV0_EPF1_STRAP4                                                                         0x30303504
14399 #define cfgRCC_DEV0_EPF1_STRAP5                                                                         0x30303508
14400 #define cfgRCC_DEV0_EPF1_STRAP6                                                                         0x3030350c
14401 #define cfgRCC_DEV0_EPF1_STRAP7                                                                         0x30303510
14402 
14403 
14404 // addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1
14405 // base address: 0x30300000
14406 #define cfgEP_PCIE_SCRATCH                                                                              0x30303514
14407 #define cfgEP_PCIE_CNTL                                                                                 0x3030351c
14408 #define cfgEP_PCIE_INT_CNTL                                                                             0x30303520
14409 #define cfgEP_PCIE_INT_STATUS                                                                           0x30303524
14410 #define cfgEP_PCIE_RX_CNTL2                                                                             0x30303528
14411 #define cfgEP_PCIE_BUS_CNTL                                                                             0x3030352c
14412 #define cfgEP_PCIE_CFG_CNTL                                                                             0x30303530
14413 #define cfgEP_PCIE_TX_LTR_CNTL                                                                          0x30303538
14414 #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0                                                             0x3030353c
14415 #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1                                                             0x3030353d
14416 #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2                                                             0x3030353e
14417 #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3                                                             0x3030353f
14418 #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4                                                             0x30303540
14419 #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5                                                             0x30303541
14420 #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6                                                             0x30303542
14421 #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7                                                             0x30303543
14422 #define cfgEP_PCIE_STRAP_MISC                                                                           0x30303544
14423 #define cfgEP_PCIE_STRAP_MISC2                                                                          0x30303548
14424 #define cfgEP_PCIE_F0_DPA_CAP                                                                           0x30303550
14425 #define cfgEP_PCIE_F0_DPA_LATENCY_INDICATOR                                                             0x30303554
14426 #define cfgEP_PCIE_F0_DPA_CNTL                                                                          0x30303555
14427 #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0                                                             0x30303557
14428 #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1                                                             0x30303558
14429 #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2                                                             0x30303559
14430 #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3                                                             0x3030355a
14431 #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4                                                             0x3030355b
14432 #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5                                                             0x3030355c
14433 #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6                                                             0x3030355d
14434 #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7                                                             0x3030355e
14435 #define cfgEP_PCIE_PME_CONTROL                                                                          0x3030355f
14436 #define cfgEP_PCIEP_RESERVED                                                                            0x30303560
14437 #define cfgEP_PCIE_TX_CNTL                                                                              0x30303568
14438 #define cfgEP_PCIE_TX_REQUESTER_ID                                                                      0x3030356c
14439 #define cfgEP_PCIE_ERR_CNTL                                                                             0x30303570
14440 #define cfgEP_PCIE_RX_CNTL                                                                              0x30303574
14441 #define cfgEP_PCIE_LC_SPEED_CNTL                                                                        0x30303578
14442 
14443 
14444 // addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1
14445 // base address: 0x30300000
14446 #define cfgDN_PCIE_RESERVED                                                                             0x30303580
14447 #define cfgDN_PCIE_SCRATCH                                                                              0x30303584
14448 #define cfgDN_PCIE_CNTL                                                                                 0x3030358c
14449 #define cfgDN_PCIE_CONFIG_CNTL                                                                          0x30303590
14450 #define cfgDN_PCIE_RX_CNTL2                                                                             0x30303594
14451 #define cfgDN_PCIE_BUS_CNTL                                                                             0x30303598
14452 #define cfgDN_PCIE_CFG_CNTL                                                                             0x3030359c
14453 #define cfgDN_PCIE_STRAP_F0                                                                             0x303035a0
14454 #define cfgDN_PCIE_STRAP_MISC                                                                           0x303035a4
14455 #define cfgDN_PCIE_STRAP_MISC2                                                                          0x303035a8
14456 
14457 
14458 // addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1
14459 // base address: 0x30300000
14460 #define cfgPCIE_ERR_CNTL                                                                                0x303035bc
14461 #define cfgPCIE_RX_CNTL                                                                                 0x303035c0
14462 #define cfgPCIE_LC_SPEED_CNTL                                                                           0x303035c4
14463 #define cfgPCIE_LC_CNTL2                                                                                0x303035c8
14464 #define cfgPCIEP_STRAP_MISC                                                                             0x303035cc
14465 #define cfgLTR_MSG_INFO_FROM_EP                                                                         0x303035d0
14466 
14467 
14468 // addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1[13440..14975]
14469 // base address: 0x30303480
14470 #define cfgRCC_DEV0_EPF0_RCC_ERR_LOG                                                                    0x30303694
14471 #define cfgRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN                                                           0x30303780
14472 #define cfgRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE                                                             0x3030378c
14473 #define cfgRCC_DEV0_EPF0_RCC_CONFIG_RESERVED                                                            0x30303790
14474 #define cfgRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER                                                        0x30303794
14475 
14476 
14477 // addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1
14478 // base address: 0x30300000
14479 #define cfgRCC_ERR_INT_CNTL                                                                             0x30303698
14480 #define cfgRCC_BACO_CNTL_MISC                                                                           0x3030369c
14481 #define cfgRCC_RESET_EN                                                                                 0x303036a0
14482 #define cfgRCC_VDM_SUPPORT                                                                              0x303036a4
14483 #define cfgRCC_MARGIN_PARAM_CNTL0                                                                       0x303036a8
14484 #define cfgRCC_MARGIN_PARAM_CNTL1                                                                       0x303036ac
14485 #define cfgRCC_GPUIOV_REGION                                                                            0x303036b0
14486 #define cfgRCC_PEER_REG_RANGE0                                                                          0x30303778
14487 #define cfgRCC_PEER_REG_RANGE1                                                                          0x3030377c
14488 #define cfgRCC_BUS_CNTL                                                                                 0x30303784
14489 #define cfgRCC_CONFIG_CNTL                                                                              0x30303788
14490 #define cfgRCC_CONFIG_F0_BASE                                                                           0x30303798
14491 #define cfgRCC_CONFIG_APER_SIZE                                                                         0x3030379c
14492 #define cfgRCC_CONFIG_REG_APER_SIZE                                                                     0x303037a0
14493 #define cfgRCC_XDMA_LO                                                                                  0x303037a4
14494 #define cfgRCC_XDMA_HI                                                                                  0x303037a8
14495 #define cfgRCC_FEATURES_CONTROL_MISC                                                                    0x303037ac
14496 #define cfgRCC_BUSNUM_CNTL1                                                                             0x303037b0
14497 #define cfgRCC_BUSNUM_LIST0                                                                             0x303037b4
14498 #define cfgRCC_BUSNUM_LIST1                                                                             0x303037b8
14499 #define cfgRCC_BUSNUM_CNTL2                                                                             0x303037bc
14500 #define cfgRCC_CAPTURE_HOST_BUSNUM                                                                      0x303037c0
14501 #define cfgRCC_HOST_BUSNUM                                                                              0x303037c4
14502 #define cfgRCC_PEER0_FB_OFFSET_HI                                                                       0x303037c8
14503 #define cfgRCC_PEER0_FB_OFFSET_LO                                                                       0x303037cc
14504 #define cfgRCC_PEER1_FB_OFFSET_HI                                                                       0x303037d0
14505 #define cfgRCC_PEER1_FB_OFFSET_LO                                                                       0x303037d4
14506 #define cfgRCC_PEER2_FB_OFFSET_HI                                                                       0x303037d8
14507 #define cfgRCC_PEER2_FB_OFFSET_LO                                                                       0x303037dc
14508 #define cfgRCC_PEER3_FB_OFFSET_HI                                                                       0x303037e0
14509 #define cfgRCC_PEER3_FB_OFFSET_LO                                                                       0x303037e4
14510 #define cfgRCC_DEVFUNCNUM_LIST0                                                                         0x303037e8
14511 #define cfgRCC_DEVFUNCNUM_LIST1                                                                         0x303037ec
14512 #define cfgRCC_DEV0_LINK_CNTL                                                                           0x303037f4
14513 #define cfgRCC_CMN_LINK_CNTL                                                                            0x303037f8
14514 #define cfgRCC_EP_REQUESTERID_RESTORE                                                                   0x303037fc
14515 #define cfgRCC_LTR_LSWITCH_CNTL                                                                         0x30303800
14516 #define cfgRCC_MH_ARB_CNTL                                                                              0x30303804
14517 
14518 
14519 // addressBlock: nbio_nbif0_bif_bx_BIFDEC1
14520 // base address: 0x30300000
14521 #define cfgCC_BIF_BX_STRAP0                                                                             0x30303808
14522 #define cfgCC_BIF_BX_PINSTRAP0                                                                          0x30303810
14523 #define cfgBIF_MM_INDACCESS_CNTL                                                                        0x30303818
14524 #define cfgBUS_CNTL                                                                                     0x3030381c
14525 #define cfgBIF_SCRATCH0                                                                                 0x30303820
14526 #define cfgBIF_SCRATCH1                                                                                 0x30303824
14527 #define cfgBX_RESET_EN                                                                                  0x30303834
14528 #define cfgMM_CFGREGS_CNTL                                                                              0x30303838
14529 #define cfgBX_RESET_CNTL                                                                                0x30303840
14530 #define cfgINTERRUPT_CNTL                                                                               0x30303844
14531 #define cfgINTERRUPT_CNTL2                                                                              0x30303848
14532 #define cfgCLKREQB_PAD_CNTL                                                                             0x30303860
14533 #define cfgBIF_FEATURES_CONTROL_MISC                                                                    0x3030386c
14534 #define cfgBIF_DOORBELL_CNTL                                                                            0x30303870
14535 #define cfgBIF_DOORBELL_INT_CNTL                                                                        0x30303874
14536 #define cfgBIF_FB_EN                                                                                    0x3030387c
14537 #define cfgBIF_INTR_CNTL                                                                                0x30303880
14538 #define cfgBIF_MST_TRANS_PENDING_VF                                                                     0x303038a4
14539 #define cfgBIF_SLV_TRANS_PENDING_VF                                                                     0x303038a8
14540 #define cfgBACO_CNTL                                                                                    0x303038ac
14541 #define cfgBIF_BACO_EXIT_TIME0                                                                          0x303038b0
14542 #define cfgBIF_BACO_EXIT_TIMER1                                                                         0x303038b4
14543 #define cfgBIF_BACO_EXIT_TIMER2                                                                         0x303038b8
14544 #define cfgBIF_BACO_EXIT_TIMER3                                                                         0x303038bc
14545 #define cfgBIF_BACO_EXIT_TIMER4                                                                         0x303038c0
14546 #define cfgMEM_TYPE_CNTL                                                                                0x303038c4
14547 #define cfgNBIF_GFX_ADDR_LUT_CNTL                                                                       0x303038cc
14548 #define cfgNBIF_GFX_ADDR_LUT_0                                                                          0x303038d0
14549 #define cfgNBIF_GFX_ADDR_LUT_1                                                                          0x303038d4
14550 #define cfgNBIF_GFX_ADDR_LUT_2                                                                          0x303038d8
14551 #define cfgNBIF_GFX_ADDR_LUT_3                                                                          0x303038dc
14552 #define cfgNBIF_GFX_ADDR_LUT_4                                                                          0x303038e0
14553 #define cfgNBIF_GFX_ADDR_LUT_5                                                                          0x303038e4
14554 #define cfgNBIF_GFX_ADDR_LUT_6                                                                          0x303038e8
14555 #define cfgNBIF_GFX_ADDR_LUT_7                                                                          0x303038ec
14556 #define cfgNBIF_GFX_ADDR_LUT_8                                                                          0x303038f0
14557 #define cfgNBIF_GFX_ADDR_LUT_9                                                                          0x303038f4
14558 #define cfgNBIF_GFX_ADDR_LUT_10                                                                         0x303038f8
14559 #define cfgNBIF_GFX_ADDR_LUT_11                                                                         0x303038fc
14560 #define cfgNBIF_GFX_ADDR_LUT_12                                                                         0x30303900
14561 #define cfgNBIF_GFX_ADDR_LUT_13                                                                         0x30303904
14562 #define cfgNBIF_GFX_ADDR_LUT_14                                                                         0x30303908
14563 #define cfgNBIF_GFX_ADDR_LUT_15                                                                         0x3030390c
14564 #define cfgREMAP_HDP_MEM_FLUSH_CNTL                                                                     0x30303934
14565 #define cfgREMAP_HDP_REG_FLUSH_CNTL                                                                     0x30303938
14566 #define cfgBIF_RB_CNTL                                                                                  0x3030393c
14567 #define cfgBIF_RB_BASE                                                                                  0x30303940
14568 #define cfgBIF_RB_RPTR                                                                                  0x30303944
14569 #define cfgBIF_RB_WPTR                                                                                  0x30303948
14570 #define cfgBIF_RB_WPTR_ADDR_HI                                                                          0x3030394c
14571 #define cfgBIF_RB_WPTR_ADDR_LO                                                                          0x30303950
14572 #define cfgMAILBOX_INDEX                                                                                0x30303954
14573 #define cfgBIF_MP1_INTR_CTRL                                                                            0x30303988
14574 #define cfgBIF_UVD_GPUIOV_CFG_SIZE                                                                      0x3030398c
14575 #define cfgBIF_VCE_GPUIOV_CFG_SIZE                                                                      0x30303990
14576 #define cfgBIF_GFX_SDMA_GPUIOV_CFG_SIZE                                                                 0x30303994
14577 #define cfgBIF_PERSTB_PAD_CNTL                                                                          0x303039a0
14578 #define cfgBIF_PX_EN_PAD_CNTL                                                                           0x303039a4
14579 #define cfgBIF_REFPADKIN_PAD_CNTL                                                                       0x303039a8
14580 #define cfgBIF_CLKREQB_PAD_CNTL                                                                         0x303039ac
14581 #define cfgBIF_PWRBRK_PAD_CNTL                                                                          0x303039b0
14582 #define cfgBIF_WAKEB_PAD_CNTL                                                                           0x303039b4
14583 #define cfgBIF_VAUX_PRESENT_PAD_CNTL                                                                    0x303039b8
14584 
14585 
14586 // addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1
14587 // base address: 0x30300000
14588 #define cfgBIF_BX_PF_BIF_BME_STATUS                                                                     0x3030382c
14589 #define cfgBIF_BX_PF_BIF_ATOMIC_ERR_LOG                                                                 0x30303830
14590 #define cfgBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                               0x3030384c
14591 #define cfgBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                                0x30303850
14592 #define cfgBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL                                                    0x30303854
14593 #define cfgBIF_BX_PF_HDP_REG_COHERENCY_FLUSH_CNTL                                                       0x30303858
14594 #define cfgBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL                                                       0x3030385c
14595 #define cfgBIF_BX_PF_GPU_HDP_FLUSH_REQ                                                                  0x30303898
14596 #define cfgBIF_BX_PF_GPU_HDP_FLUSH_DONE                                                                 0x3030389c
14597 #define cfgBIF_BX_PF_BIF_TRANS_PENDING                                                                  0x303038a0
14598 #define cfgBIF_BX_PF_NBIF_GFX_ADDR_LUT_BYPASS                                                           0x303038c8
14599 #define cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0                                                             0x30303958
14600 #define cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1                                                             0x3030395c
14601 #define cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2                                                             0x30303960
14602 #define cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3                                                             0x30303964
14603 #define cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0                                                             0x30303968
14604 #define cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW1                                                             0x3030396c
14605 #define cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2                                                             0x30303970
14606 #define cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW3                                                             0x30303974
14607 #define cfgBIF_BX_PF_MAILBOX_CONTROL                                                                    0x30303978
14608 #define cfgBIF_BX_PF_MAILBOX_INT_CNTL                                                                   0x3030397c
14609 #define cfgBIF_BX_PF_BIF_VMHV_MAILBOX                                                                   0x30303980
14610 
14611 
14612 // addressBlock: nbio_nbif0_gdc_GDCDEC
14613 // base address: 0x30300000
14614 #define cfgA2S_CNTL_CL0                                                                                 0x30303ac0
14615 #define cfgA2S_CNTL_CL1                                                                                 0x30303ac4
14616 #define cfgA2S_CNTL3_CL0                                                                                0x30303b00
14617 #define cfgA2S_CNTL3_CL1                                                                                0x30303b04
14618 #define cfgA2S_CNTL_SW0                                                                                 0x30303b40
14619 #define cfgA2S_CNTL_SW1                                                                                 0x30303b44
14620 #define cfgA2S_CNTL_SW2                                                                                 0x30303b48
14621 #define cfgA2S_CPLBUF_ALLOC_CNTL                                                                        0x30303b70
14622 #define cfgA2S_TAG_ALLOC_0                                                                              0x30303b74
14623 #define cfgA2S_TAG_ALLOC_1                                                                              0x30303b78
14624 #define cfgA2S_MISC_CNTL                                                                                0x30303b84
14625 #define cfgNGDC_SDP_PORT_CTRL                                                                           0x30303b88
14626 #define cfgSHUB_REGS_IF_CTL                                                                             0x30303b8c
14627 #define cfgNGDC_MGCG_CTRL                                                                               0x30303ba8
14628 #define cfgNGDC_RESERVED_0                                                                              0x30303bac
14629 #define cfgNGDC_RESERVED_1                                                                              0x30303bb0
14630 #define cfgNGDC_SDP_PORT_CTRL_SOCCLK                                                                    0x30303bb4
14631 #define cfgBIF_SDMA0_DOORBELL_RANGE                                                                     0x30303bc0
14632 #define cfgBIF_SDMA1_DOORBELL_RANGE                                                                     0x30303bc4
14633 #define cfgBIF_IH_DOORBELL_RANGE                                                                        0x30303bc8
14634 #define cfgBIF_MMSCH0_DOORBELL_RANGE                                                                    0x30303bcc
14635 #define cfgBIF_ACV_DOORBELL_RANGE                                                                       0x30303bd0
14636 #define cfgBIF_DOORBELL_FENCE_CNTL                                                                      0x30303bf8
14637 #define cfgS2A_MISC_CNTL                                                                                0x30303bfc
14638 #define cfgNGDC_PG_MISC_CTRL                                                                            0x30303c40
14639 #define cfgNGDC_PGMST_CTRL                                                                              0x30303c44
14640 #define cfgNGDC_PGSLV_CTRL                                                                              0x30303c48
14641 
14642 
14643 // addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFDEC2
14644 // base address: 0x30300000
14645 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO                                                          0x30342000
14646 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI                                                          0x30342004
14647 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA                                                         0x30342008
14648 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL                                                          0x3034200c
14649 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO                                                          0x30342010
14650 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI                                                          0x30342014
14651 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA                                                         0x30342018
14652 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL                                                          0x3034201c
14653 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO                                                          0x30342020
14654 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI                                                          0x30342024
14655 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA                                                         0x30342028
14656 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL                                                          0x3034202c
14657 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO                                                          0x30342030
14658 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI                                                          0x30342034
14659 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA                                                         0x30342038
14660 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL                                                          0x3034203c
14661 #define cfgRCC_DEV0_EPF0_GFXMSIX_PBA                                                                    0x30343000
14662 
14663 #endif