root/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_offset.h

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   1 /*
   2  * Copyright (C) 2019  Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  */
  21 #ifndef _smuio_11_0_0_OFFSET_HEADER
  22 #define _smuio_11_0_0_OFFSET_HEADER
  23 
  24 
  25 
  26 // addressBlock: smuio_smuio_SmuSmuioDec
  27 // base address: 0x5a000
  28 #define mmSMUSVI0_TEL_PLANE0                                                                           0x0004
  29 #define mmSMUSVI0_TEL_PLANE0_BASE_IDX                                                                  0
  30 #define mmSMUIO_MCM_CONFIG                                                                             0x0024
  31 #define mmSMUIO_MCM_CONFIG_BASE_IDX                                                                    0
  32 #define mmCKSVII2C_IC_CON                                                                              0x0040
  33 #define mmCKSVII2C_IC_CON_BASE_IDX                                                                     0
  34 #define mmCKSVII2C_IC_TAR                                                                              0x0041
  35 #define mmCKSVII2C_IC_TAR_BASE_IDX                                                                     0
  36 #define mmCKSVII2C_IC_SAR                                                                              0x0042
  37 #define mmCKSVII2C_IC_SAR_BASE_IDX                                                                     0
  38 #define mmCKSVII2C_IC_HS_MADDR                                                                         0x0043
  39 #define mmCKSVII2C_IC_HS_MADDR_BASE_IDX                                                                0
  40 #define mmCKSVII2C_IC_DATA_CMD                                                                         0x0044
  41 #define mmCKSVII2C_IC_DATA_CMD_BASE_IDX                                                                0
  42 #define mmCKSVII2C_IC_SS_SCL_HCNT                                                                      0x0045
  43 #define mmCKSVII2C_IC_SS_SCL_HCNT_BASE_IDX                                                             0
  44 #define mmCKSVII2C_IC_SS_SCL_LCNT                                                                      0x0046
  45 #define mmCKSVII2C_IC_SS_SCL_LCNT_BASE_IDX                                                             0
  46 #define mmCKSVII2C_IC_FS_SCL_HCNT                                                                      0x0047
  47 #define mmCKSVII2C_IC_FS_SCL_HCNT_BASE_IDX                                                             0
  48 #define mmCKSVII2C_IC_FS_SCL_LCNT                                                                      0x0048
  49 #define mmCKSVII2C_IC_FS_SCL_LCNT_BASE_IDX                                                             0
  50 #define mmCKSVII2C_IC_HS_SCL_HCNT                                                                      0x0049
  51 #define mmCKSVII2C_IC_HS_SCL_HCNT_BASE_IDX                                                             0
  52 #define mmCKSVII2C_IC_HS_SCL_LCNT                                                                      0x004a
  53 #define mmCKSVII2C_IC_HS_SCL_LCNT_BASE_IDX                                                             0
  54 #define mmCKSVII2C_IC_INTR_STAT                                                                        0x004b
  55 #define mmCKSVII2C_IC_INTR_STAT_BASE_IDX                                                               0
  56 #define mmCKSVII2C_IC_INTR_MASK                                                                        0x004c
  57 #define mmCKSVII2C_IC_INTR_MASK_BASE_IDX                                                               0
  58 #define mmCKSVII2C_IC_RAW_INTR_STAT                                                                    0x004d
  59 #define mmCKSVII2C_IC_RAW_INTR_STAT_BASE_IDX                                                           0
  60 #define mmCKSVII2C_IC_RX_TL                                                                            0x004e
  61 #define mmCKSVII2C_IC_RX_TL_BASE_IDX                                                                   0
  62 #define mmCKSVII2C_IC_TX_TL                                                                            0x004f
  63 #define mmCKSVII2C_IC_TX_TL_BASE_IDX                                                                   0
  64 #define mmCKSVII2C_IC_CLR_INTR                                                                         0x0050
  65 #define mmCKSVII2C_IC_CLR_INTR_BASE_IDX                                                                0
  66 #define mmCKSVII2C_IC_CLR_RX_UNDER                                                                     0x0051
  67 #define mmCKSVII2C_IC_CLR_RX_UNDER_BASE_IDX                                                            0
  68 #define mmCKSVII2C_IC_CLR_RX_OVER                                                                      0x0052
  69 #define mmCKSVII2C_IC_CLR_RX_OVER_BASE_IDX                                                             0
  70 #define mmCKSVII2C_IC_CLR_TX_OVER                                                                      0x0053
  71 #define mmCKSVII2C_IC_CLR_TX_OVER_BASE_IDX                                                             0
  72 #define mmCKSVII2C_IC_CLR_RD_REQ                                                                       0x0054
  73 #define mmCKSVII2C_IC_CLR_RD_REQ_BASE_IDX                                                              0
  74 #define mmCKSVII2C_IC_CLR_TX_ABRT                                                                      0x0055
  75 #define mmCKSVII2C_IC_CLR_TX_ABRT_BASE_IDX                                                             0
  76 #define mmCKSVII2C_IC_CLR_RX_DONE                                                                      0x0056
  77 #define mmCKSVII2C_IC_CLR_RX_DONE_BASE_IDX                                                             0
  78 #define mmCKSVII2C_IC_CLR_ACTIVITY                                                                     0x0057
  79 #define mmCKSVII2C_IC_CLR_ACTIVITY_BASE_IDX                                                            0
  80 #define mmCKSVII2C_IC_CLR_STOP_DET                                                                     0x0058
  81 #define mmCKSVII2C_IC_CLR_STOP_DET_BASE_IDX                                                            0
  82 #define mmCKSVII2C_IC_CLR_START_DET                                                                    0x0059
  83 #define mmCKSVII2C_IC_CLR_START_DET_BASE_IDX                                                           0
  84 #define mmCKSVII2C_IC_CLR_GEN_CALL                                                                     0x005a
  85 #define mmCKSVII2C_IC_CLR_GEN_CALL_BASE_IDX                                                            0
  86 #define mmCKSVII2C_IC_ENABLE                                                                           0x005b
  87 #define mmCKSVII2C_IC_ENABLE_BASE_IDX                                                                  0
  88 #define mmCKSVII2C_IC_STATUS                                                                           0x005c
  89 #define mmCKSVII2C_IC_STATUS_BASE_IDX                                                                  0
  90 #define mmCKSVII2C_IC_TXFLR                                                                            0x005d
  91 #define mmCKSVII2C_IC_TXFLR_BASE_IDX                                                                   0
  92 #define mmCKSVII2C_IC_RXFLR                                                                            0x005e
  93 #define mmCKSVII2C_IC_RXFLR_BASE_IDX                                                                   0
  94 #define mmCKSVII2C_IC_SDA_HOLD                                                                         0x005f
  95 #define mmCKSVII2C_IC_SDA_HOLD_BASE_IDX                                                                0
  96 #define mmCKSVII2C_IC_TX_ABRT_SOURCE                                                                   0x0060
  97 #define mmCKSVII2C_IC_TX_ABRT_SOURCE_BASE_IDX                                                          0
  98 #define mmCKSVII2C_IC_SLV_DATA_NACK_ONLY                                                               0x0061
  99 #define mmCKSVII2C_IC_SLV_DATA_NACK_ONLY_BASE_IDX                                                      0
 100 #define mmCKSVII2C_IC_DMA_CR                                                                           0x0062
 101 #define mmCKSVII2C_IC_DMA_CR_BASE_IDX                                                                  0
 102 #define mmCKSVII2C_IC_DMA_TDLR                                                                         0x0063
 103 #define mmCKSVII2C_IC_DMA_TDLR_BASE_IDX                                                                0
 104 #define mmCKSVII2C_IC_DMA_RDLR                                                                         0x0064
 105 #define mmCKSVII2C_IC_DMA_RDLR_BASE_IDX                                                                0
 106 #define mmCKSVII2C_IC_SDA_SETUP                                                                        0x0065
 107 #define mmCKSVII2C_IC_SDA_SETUP_BASE_IDX                                                               0
 108 #define mmCKSVII2C_IC_ACK_GENERAL_CALL                                                                 0x0066
 109 #define mmCKSVII2C_IC_ACK_GENERAL_CALL_BASE_IDX                                                        0
 110 #define mmCKSVII2C_IC_ENABLE_STATUS                                                                    0x0067
 111 #define mmCKSVII2C_IC_ENABLE_STATUS_BASE_IDX                                                           0
 112 #define mmCKSVII2C_IC_FS_SPKLEN                                                                        0x0068
 113 #define mmCKSVII2C_IC_FS_SPKLEN_BASE_IDX                                                               0
 114 #define mmCKSVII2C_IC_HS_SPKLEN                                                                        0x0069
 115 #define mmCKSVII2C_IC_HS_SPKLEN_BASE_IDX                                                               0
 116 #define mmCKSVII2C_IC_CLR_RESTART_DET                                                                  0x006a
 117 #define mmCKSVII2C_IC_CLR_RESTART_DET_BASE_IDX                                                         0
 118 #define mmCKSVII2C_IC_COMP_PARAM_1                                                                     0x006b
 119 #define mmCKSVII2C_IC_COMP_PARAM_1_BASE_IDX                                                            0
 120 #define mmCKSVII2C_IC_COMP_VERSION                                                                     0x006c
 121 #define mmCKSVII2C_IC_COMP_VERSION_BASE_IDX                                                            0
 122 #define mmCKSVII2C_IC_COMP_TYPE                                                                        0x006d
 123 #define mmCKSVII2C_IC_COMP_TYPE_BASE_IDX                                                               0
 124 #define mmSMUIO_MP_RESET_INTR                                                                          0x00c1
 125 #define mmSMUIO_MP_RESET_INTR_BASE_IDX                                                                 0
 126 #define mmSMUIO_SOC_HALT                                                                               0x00c2
 127 #define mmSMUIO_SOC_HALT_BASE_IDX                                                                      0
 128 #define mmSMUIO_PWRMGT                                                                                 0x00c8
 129 #define mmSMUIO_PWRMGT_BASE_IDX                                                                        0
 130 #define mmROM_CNTL                                                                                     0x00e0
 131 #define mmROM_CNTL_BASE_IDX                                                                            0
 132 #define mmPAGE_MIRROR_CNTL                                                                             0x00e1
 133 #define mmPAGE_MIRROR_CNTL_BASE_IDX                                                                    0
 134 #define mmROM_STATUS                                                                                   0x00e2
 135 #define mmROM_STATUS_BASE_IDX                                                                          0
 136 #define mmCGTT_ROM_CLK_CTRL0                                                                           0x00e3
 137 #define mmCGTT_ROM_CLK_CTRL0_BASE_IDX                                                                  0
 138 #define mmROM_INDEX                                                                                    0x00e4
 139 #define mmROM_INDEX_BASE_IDX                                                                           0
 140 #define mmROM_DATA                                                                                     0x00e5
 141 #define mmROM_DATA_BASE_IDX                                                                            0
 142 #define mmROM_START                                                                                    0x00e6
 143 #define mmROM_START_BASE_IDX                                                                           0
 144 #define mmROM_SW_CNTL                                                                                  0x00e7
 145 #define mmROM_SW_CNTL_BASE_IDX                                                                         0
 146 #define mmROM_SW_STATUS                                                                                0x00e8
 147 #define mmROM_SW_STATUS_BASE_IDX                                                                       0
 148 #define mmROM_SW_COMMAND                                                                               0x00e9
 149 #define mmROM_SW_COMMAND_BASE_IDX                                                                      0
 150 #define mmROM_SW_DATA_1                                                                                0x00ea
 151 #define mmROM_SW_DATA_1_BASE_IDX                                                                       0
 152 #define mmROM_SW_DATA_2                                                                                0x00eb
 153 #define mmROM_SW_DATA_2_BASE_IDX                                                                       0
 154 #define mmROM_SW_DATA_3                                                                                0x00ec
 155 #define mmROM_SW_DATA_3_BASE_IDX                                                                       0
 156 #define mmROM_SW_DATA_4                                                                                0x00ed
 157 #define mmROM_SW_DATA_4_BASE_IDX                                                                       0
 158 #define mmROM_SW_DATA_5                                                                                0x00ee
 159 #define mmROM_SW_DATA_5_BASE_IDX                                                                       0
 160 #define mmROM_SW_DATA_6                                                                                0x00ef
 161 #define mmROM_SW_DATA_6_BASE_IDX                                                                       0
 162 #define mmROM_SW_DATA_7                                                                                0x00f0
 163 #define mmROM_SW_DATA_7_BASE_IDX                                                                       0
 164 #define mmROM_SW_DATA_8                                                                                0x00f1
 165 #define mmROM_SW_DATA_8_BASE_IDX                                                                       0
 166 #define mmROM_SW_DATA_9                                                                                0x00f2
 167 #define mmROM_SW_DATA_9_BASE_IDX                                                                       0
 168 #define mmROM_SW_DATA_10                                                                               0x00f3
 169 #define mmROM_SW_DATA_10_BASE_IDX                                                                      0
 170 #define mmROM_SW_DATA_11                                                                               0x00f4
 171 #define mmROM_SW_DATA_11_BASE_IDX                                                                      0
 172 #define mmROM_SW_DATA_12                                                                               0x00f5
 173 #define mmROM_SW_DATA_12_BASE_IDX                                                                      0
 174 #define mmROM_SW_DATA_13                                                                               0x00f6
 175 #define mmROM_SW_DATA_13_BASE_IDX                                                                      0
 176 #define mmROM_SW_DATA_14                                                                               0x00f7
 177 #define mmROM_SW_DATA_14_BASE_IDX                                                                      0
 178 #define mmROM_SW_DATA_15                                                                               0x00f8
 179 #define mmROM_SW_DATA_15_BASE_IDX                                                                      0
 180 #define mmROM_SW_DATA_16                                                                               0x00f9
 181 #define mmROM_SW_DATA_16_BASE_IDX                                                                      0
 182 #define mmROM_SW_DATA_17                                                                               0x00fa
 183 #define mmROM_SW_DATA_17_BASE_IDX                                                                      0
 184 #define mmROM_SW_DATA_18                                                                               0x00fb
 185 #define mmROM_SW_DATA_18_BASE_IDX                                                                      0
 186 #define mmROM_SW_DATA_19                                                                               0x00fc
 187 #define mmROM_SW_DATA_19_BASE_IDX                                                                      0
 188 #define mmROM_SW_DATA_20                                                                               0x00fd
 189 #define mmROM_SW_DATA_20_BASE_IDX                                                                      0
 190 #define mmROM_SW_DATA_21                                                                               0x00fe
 191 #define mmROM_SW_DATA_21_BASE_IDX                                                                      0
 192 #define mmROM_SW_DATA_22                                                                               0x00ff
 193 #define mmROM_SW_DATA_22_BASE_IDX                                                                      0
 194 #define mmROM_SW_DATA_23                                                                               0x0100
 195 #define mmROM_SW_DATA_23_BASE_IDX                                                                      0
 196 #define mmROM_SW_DATA_24                                                                               0x0101
 197 #define mmROM_SW_DATA_24_BASE_IDX                                                                      0
 198 #define mmROM_SW_DATA_25                                                                               0x0102
 199 #define mmROM_SW_DATA_25_BASE_IDX                                                                      0
 200 #define mmROM_SW_DATA_26                                                                               0x0103
 201 #define mmROM_SW_DATA_26_BASE_IDX                                                                      0
 202 #define mmROM_SW_DATA_27                                                                               0x0104
 203 #define mmROM_SW_DATA_27_BASE_IDX                                                                      0
 204 #define mmROM_SW_DATA_28                                                                               0x0105
 205 #define mmROM_SW_DATA_28_BASE_IDX                                                                      0
 206 #define mmROM_SW_DATA_29                                                                               0x0106
 207 #define mmROM_SW_DATA_29_BASE_IDX                                                                      0
 208 #define mmROM_SW_DATA_30                                                                               0x0107
 209 #define mmROM_SW_DATA_30_BASE_IDX                                                                      0
 210 #define mmROM_SW_DATA_31                                                                               0x0108
 211 #define mmROM_SW_DATA_31_BASE_IDX                                                                      0
 212 #define mmROM_SW_DATA_32                                                                               0x0109
 213 #define mmROM_SW_DATA_32_BASE_IDX                                                                      0
 214 #define mmROM_SW_DATA_33                                                                               0x010a
 215 #define mmROM_SW_DATA_33_BASE_IDX                                                                      0
 216 #define mmROM_SW_DATA_34                                                                               0x010b
 217 #define mmROM_SW_DATA_34_BASE_IDX                                                                      0
 218 #define mmROM_SW_DATA_35                                                                               0x010c
 219 #define mmROM_SW_DATA_35_BASE_IDX                                                                      0
 220 #define mmROM_SW_DATA_36                                                                               0x010d
 221 #define mmROM_SW_DATA_36_BASE_IDX                                                                      0
 222 #define mmROM_SW_DATA_37                                                                               0x010e
 223 #define mmROM_SW_DATA_37_BASE_IDX                                                                      0
 224 #define mmROM_SW_DATA_38                                                                               0x010f
 225 #define mmROM_SW_DATA_38_BASE_IDX                                                                      0
 226 #define mmROM_SW_DATA_39                                                                               0x0110
 227 #define mmROM_SW_DATA_39_BASE_IDX                                                                      0
 228 #define mmROM_SW_DATA_40                                                                               0x0111
 229 #define mmROM_SW_DATA_40_BASE_IDX                                                                      0
 230 #define mmROM_SW_DATA_41                                                                               0x0112
 231 #define mmROM_SW_DATA_41_BASE_IDX                                                                      0
 232 #define mmROM_SW_DATA_42                                                                               0x0113
 233 #define mmROM_SW_DATA_42_BASE_IDX                                                                      0
 234 #define mmROM_SW_DATA_43                                                                               0x0114
 235 #define mmROM_SW_DATA_43_BASE_IDX                                                                      0
 236 #define mmROM_SW_DATA_44                                                                               0x0115
 237 #define mmROM_SW_DATA_44_BASE_IDX                                                                      0
 238 #define mmROM_SW_DATA_45                                                                               0x0116
 239 #define mmROM_SW_DATA_45_BASE_IDX                                                                      0
 240 #define mmROM_SW_DATA_46                                                                               0x0117
 241 #define mmROM_SW_DATA_46_BASE_IDX                                                                      0
 242 #define mmROM_SW_DATA_47                                                                               0x0118
 243 #define mmROM_SW_DATA_47_BASE_IDX                                                                      0
 244 #define mmROM_SW_DATA_48                                                                               0x0119
 245 #define mmROM_SW_DATA_48_BASE_IDX                                                                      0
 246 #define mmROM_SW_DATA_49                                                                               0x011a
 247 #define mmROM_SW_DATA_49_BASE_IDX                                                                      0
 248 #define mmROM_SW_DATA_50                                                                               0x011b
 249 #define mmROM_SW_DATA_50_BASE_IDX                                                                      0
 250 #define mmROM_SW_DATA_51                                                                               0x011c
 251 #define mmROM_SW_DATA_51_BASE_IDX                                                                      0
 252 #define mmROM_SW_DATA_52                                                                               0x011d
 253 #define mmROM_SW_DATA_52_BASE_IDX                                                                      0
 254 #define mmROM_SW_DATA_53                                                                               0x011e
 255 #define mmROM_SW_DATA_53_BASE_IDX                                                                      0
 256 #define mmROM_SW_DATA_54                                                                               0x011f
 257 #define mmROM_SW_DATA_54_BASE_IDX                                                                      0
 258 #define mmROM_SW_DATA_55                                                                               0x0120
 259 #define mmROM_SW_DATA_55_BASE_IDX                                                                      0
 260 #define mmROM_SW_DATA_56                                                                               0x0121
 261 #define mmROM_SW_DATA_56_BASE_IDX                                                                      0
 262 #define mmROM_SW_DATA_57                                                                               0x0122
 263 #define mmROM_SW_DATA_57_BASE_IDX                                                                      0
 264 #define mmROM_SW_DATA_58                                                                               0x0123
 265 #define mmROM_SW_DATA_58_BASE_IDX                                                                      0
 266 #define mmROM_SW_DATA_59                                                                               0x0124
 267 #define mmROM_SW_DATA_59_BASE_IDX                                                                      0
 268 #define mmROM_SW_DATA_60                                                                               0x0125
 269 #define mmROM_SW_DATA_60_BASE_IDX                                                                      0
 270 #define mmROM_SW_DATA_61                                                                               0x0126
 271 #define mmROM_SW_DATA_61_BASE_IDX                                                                      0
 272 #define mmROM_SW_DATA_62                                                                               0x0127
 273 #define mmROM_SW_DATA_62_BASE_IDX                                                                      0
 274 #define mmROM_SW_DATA_63                                                                               0x0128
 275 #define mmROM_SW_DATA_63_BASE_IDX                                                                      0
 276 #define mmROM_SW_DATA_64                                                                               0x0129
 277 #define mmROM_SW_DATA_64_BASE_IDX                                                                      0
 278 #define mmSMU_GPIOPAD_SW_INT_STAT                                                                      0x0140
 279 #define mmSMU_GPIOPAD_SW_INT_STAT_BASE_IDX                                                             0
 280 #define mmSMU_GPIOPAD_MASK                                                                             0x0141
 281 #define mmSMU_GPIOPAD_MASK_BASE_IDX                                                                    0
 282 #define mmSMU_GPIOPAD_A                                                                                0x0142
 283 #define mmSMU_GPIOPAD_A_BASE_IDX                                                                       0
 284 #define mmSMU_GPIOPAD_TXIMPSEL                                                                         0x0143
 285 #define mmSMU_GPIOPAD_TXIMPSEL_BASE_IDX                                                                0
 286 #define mmSMU_GPIOPAD_EN                                                                               0x0144
 287 #define mmSMU_GPIOPAD_EN_BASE_IDX                                                                      0
 288 #define mmSMU_GPIOPAD_Y                                                                                0x0145
 289 #define mmSMU_GPIOPAD_Y_BASE_IDX                                                                       0
 290 #define mmSMU_GPIOPAD_RXEN                                                                             0x0146
 291 #define mmSMU_GPIOPAD_RXEN_BASE_IDX                                                                    0
 292 #define mmSMU_GPIOPAD_RCVR_SEL0                                                                        0x0147
 293 #define mmSMU_GPIOPAD_RCVR_SEL0_BASE_IDX                                                               0
 294 #define mmSMU_GPIOPAD_RCVR_SEL1                                                                        0x0148
 295 #define mmSMU_GPIOPAD_RCVR_SEL1_BASE_IDX                                                               0
 296 #define mmSMU_GPIOPAD_PU_EN                                                                            0x0149
 297 #define mmSMU_GPIOPAD_PU_EN_BASE_IDX                                                                   0
 298 #define mmSMU_GPIOPAD_PD_EN                                                                            0x014a
 299 #define mmSMU_GPIOPAD_PD_EN_BASE_IDX                                                                   0
 300 #define mmSMU_GPIOPAD_PINSTRAPS                                                                        0x014b
 301 #define mmSMU_GPIOPAD_PINSTRAPS_BASE_IDX                                                               0
 302 #define mmDFT_PINSTRAPS                                                                                0x014c
 303 #define mmDFT_PINSTRAPS_BASE_IDX                                                                       0
 304 #define mmSMU_GPIOPAD_INT_STAT_EN                                                                      0x014d
 305 #define mmSMU_GPIOPAD_INT_STAT_EN_BASE_IDX                                                             0
 306 #define mmSMU_GPIOPAD_INT_STAT                                                                         0x014e
 307 #define mmSMU_GPIOPAD_INT_STAT_BASE_IDX                                                                0
 308 #define mmSMU_GPIOPAD_INT_STAT_AK                                                                      0x014f
 309 #define mmSMU_GPIOPAD_INT_STAT_AK_BASE_IDX                                                             0
 310 #define mmSMU_GPIOPAD_INT_EN                                                                           0x0150
 311 #define mmSMU_GPIOPAD_INT_EN_BASE_IDX                                                                  0
 312 #define mmSMU_GPIOPAD_INT_TYPE                                                                         0x0151
 313 #define mmSMU_GPIOPAD_INT_TYPE_BASE_IDX                                                                0
 314 #define mmSMU_GPIOPAD_INT_POLARITY                                                                     0x0152
 315 #define mmSMU_GPIOPAD_INT_POLARITY_BASE_IDX                                                            0
 316 #define mmROM_CC_BIF_PINSTRAP                                                                          0x0153
 317 #define mmROM_CC_BIF_PINSTRAP_BASE_IDX                                                                 0
 318 #define mmIO_SMUIO_PINSTRAP                                                                            0x0154
 319 #define mmIO_SMUIO_PINSTRAP_BASE_IDX                                                                   0
 320 #define mmSMUIO_PCC_CONTROL                                                                            0x0155
 321 #define mmSMUIO_PCC_CONTROL_BASE_IDX                                                                   0
 322 #define mmSMUIO_PCC_GPIO_SELECT                                                                        0x0156
 323 #define mmSMUIO_PCC_GPIO_SELECT_BASE_IDX                                                               0
 324 #define mmSMUIO_GPIO_INT0_SELECT                                                                       0x0157
 325 #define mmSMUIO_GPIO_INT0_SELECT_BASE_IDX                                                              0
 326 #define mmSMUIO_GPIO_INT1_SELECT                                                                       0x0158
 327 #define mmSMUIO_GPIO_INT1_SELECT_BASE_IDX                                                              0
 328 #define mmSMUIO_GPIO_INT2_SELECT                                                                       0x0159
 329 #define mmSMUIO_GPIO_INT2_SELECT_BASE_IDX                                                              0
 330 #define mmSMUIO_GPIO_INT3_SELECT                                                                       0x015a
 331 #define mmSMUIO_GPIO_INT3_SELECT_BASE_IDX                                                              0
 332 #define mmSMU_GPIOPAD_MP_INT0_STAT                                                                     0x015b
 333 #define mmSMU_GPIOPAD_MP_INT0_STAT_BASE_IDX                                                            0
 334 #define mmSMU_GPIOPAD_MP_INT1_STAT                                                                     0x015c
 335 #define mmSMU_GPIOPAD_MP_INT1_STAT_BASE_IDX                                                            0
 336 #define mmSMU_GPIOPAD_MP_INT2_STAT                                                                     0x015d
 337 #define mmSMU_GPIOPAD_MP_INT2_STAT_BASE_IDX                                                            0
 338 #define mmSMU_GPIOPAD_MP_INT3_STAT                                                                     0x015e
 339 #define mmSMU_GPIOPAD_MP_INT3_STAT_BASE_IDX                                                            0
 340 #define mmSMIO_INDEX                                                                                   0x015f
 341 #define mmSMIO_INDEX_BASE_IDX                                                                          0
 342 #define mmS0_VID_SMIO_CNTL                                                                             0x0160
 343 #define mmS0_VID_SMIO_CNTL_BASE_IDX                                                                    0
 344 #define mmS1_VID_SMIO_CNTL                                                                             0x0161
 345 #define mmS1_VID_SMIO_CNTL_BASE_IDX                                                                    0
 346 #define mmOPEN_DRAIN_SELECT                                                                            0x0162
 347 #define mmOPEN_DRAIN_SELECT_BASE_IDX                                                                   0
 348 #define mmSMIO_ENABLE                                                                                  0x0163
 349 #define mmSMIO_ENABLE_BASE_IDX                                                                         0
 350 #define mmSMU_GPIOPAD_S0                                                                               0x0166
 351 #define mmSMU_GPIOPAD_S0_BASE_IDX                                                                      0
 352 #define mmSMU_GPIOPAD_S1                                                                               0x0167
 353 #define mmSMU_GPIOPAD_S1_BASE_IDX                                                                      0
 354 #define mmSMU_GPIOPAD_SCL_EN                                                                           0x0168
 355 #define mmSMU_GPIOPAD_SCL_EN_BASE_IDX                                                                  0
 356 #define mmSMU_GPIOPAD_SDA_EN                                                                           0x0169
 357 #define mmSMU_GPIOPAD_SDA_EN_BASE_IDX                                                                  0
 358 #define mmSMU_GPIOPAD_SCHMEN                                                                           0x016a
 359 #define mmSMU_GPIOPAD_SCHMEN_BASE_IDX                                                                  0
 360 
 361 
 362 // addressBlock: smuio_smuio_pwr_SmuSmuioDec
 363 // base address: 0x5a800
 364 #define mmIP_DISCOVERY_VERSION                                                                         0x0000
 365 #define mmIP_DISCOVERY_VERSION_BASE_IDX                                                                1
 366 #define mmSOC_GAP_PWROK                                                                                0x00f8
 367 #define mmSOC_GAP_PWROK_BASE_IDX                                                                       1
 368 #define mmGFX_GAP_PWROK                                                                                0x00f9
 369 #define mmGFX_GAP_PWROK_BASE_IDX                                                                       1
 370 #define mmPWROK_REFCLK_GAP_CYCLES                                                                      0x00fa
 371 #define mmPWROK_REFCLK_GAP_CYCLES_BASE_IDX                                                             1
 372 #define mmGOLDEN_TSC_INCREMENT_UPPER                                                                   0x0100
 373 #define mmGOLDEN_TSC_INCREMENT_UPPER_BASE_IDX                                                          1
 374 #define mmGOLDEN_TSC_INCREMENT_LOWER                                                                   0x0101
 375 #define mmGOLDEN_TSC_INCREMENT_LOWER_BASE_IDX                                                          1
 376 #define mmGOLDEN_TSC_COUNT_UPPER                                                                       0x0102
 377 #define mmGOLDEN_TSC_COUNT_UPPER_BASE_IDX                                                              1
 378 #define mmGOLDEN_TSC_COUNT_LOWER                                                                       0x0103
 379 #define mmGOLDEN_TSC_COUNT_LOWER_BASE_IDX                                                              1
 380 #define mmSOC_GOLDEN_TSC_SHADOW_UPPER                                                                  0x0104
 381 #define mmSOC_GOLDEN_TSC_SHADOW_UPPER_BASE_IDX                                                         1
 382 #define mmSOC_GOLDEN_TSC_SHADOW_LOWER                                                                  0x0105
 383 #define mmSOC_GOLDEN_TSC_SHADOW_LOWER_BASE_IDX                                                         1
 384 #define mmGFX_GOLDEN_TSC_SHADOW_UPPER                                                                  0x0106
 385 #define mmGFX_GOLDEN_TSC_SHADOW_UPPER_BASE_IDX                                                         1
 386 #define mmGFX_GOLDEN_TSC_SHADOW_LOWER                                                                  0x0107
 387 #define mmGFX_GOLDEN_TSC_SHADOW_LOWER_BASE_IDX                                                         1
 388 #define mmPWR_VIRT_RESET_REQ                                                                           0x0108
 389 #define mmPWR_VIRT_RESET_REQ_BASE_IDX                                                                  1
 390 #define mmSCRATCH_REGISTER0                                                                            0x0110
 391 #define mmSCRATCH_REGISTER0_BASE_IDX                                                                   1
 392 #define mmSCRATCH_REGISTER1                                                                            0x0111
 393 #define mmSCRATCH_REGISTER1_BASE_IDX                                                                   1
 394 #define mmSCRATCH_REGISTER2                                                                            0x0112
 395 #define mmSCRATCH_REGISTER2_BASE_IDX                                                                   1
 396 #define mmSCRATCH_REGISTER3                                                                            0x0113
 397 #define mmSCRATCH_REGISTER3_BASE_IDX                                                                   1
 398 #define mmSCRATCH_REGISTER4                                                                            0x0114
 399 #define mmSCRATCH_REGISTER4_BASE_IDX                                                                   1
 400 #define mmSCRATCH_REGISTER5                                                                            0x0115
 401 #define mmSCRATCH_REGISTER5_BASE_IDX                                                                   1
 402 #define mmSCRATCH_REGISTER6                                                                            0x0116
 403 #define mmSCRATCH_REGISTER6_BASE_IDX                                                                   1
 404 #define mmSCRATCH_REGISTER7                                                                            0x0117
 405 #define mmSCRATCH_REGISTER7_BASE_IDX                                                                   1
 406 #define mmPWR_DISP_TIMER_CONTROL                                                                       0x012c
 407 #define mmPWR_DISP_TIMER_CONTROL_BASE_IDX                                                              1
 408 #define mmPWR_DISP_TIMER2_CONTROL                                                                      0x012e
 409 #define mmPWR_DISP_TIMER2_CONTROL_BASE_IDX                                                             1
 410 #define mmPWR_DISP_TIMER_GLOBAL_CONTROL                                                                0x0130
 411 #define mmPWR_DISP_TIMER_GLOBAL_CONTROL_BASE_IDX                                                       1
 412 #define mmPWR_IH_CONTROL                                                                               0x0131
 413 #define mmPWR_IH_CONTROL_BASE_IDX                                                                      1
 414 
 415 #endif
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