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24 #ifndef OSS_2_4_D_H
25 #define OSS_2_4_D_H
26
27 #define mmIH_VMID_0_LUT 0xe00
28 #define mmIH_VMID_1_LUT 0xe01
29 #define mmIH_VMID_2_LUT 0xe02
30 #define mmIH_VMID_3_LUT 0xe03
31 #define mmIH_VMID_4_LUT 0xe04
32 #define mmIH_VMID_5_LUT 0xe05
33 #define mmIH_VMID_6_LUT 0xe06
34 #define mmIH_VMID_7_LUT 0xe07
35 #define mmIH_VMID_8_LUT 0xe08
36 #define mmIH_VMID_9_LUT 0xe09
37 #define mmIH_VMID_10_LUT 0xe0a
38 #define mmIH_VMID_11_LUT 0xe0b
39 #define mmIH_VMID_12_LUT 0xe0c
40 #define mmIH_VMID_13_LUT 0xe0d
41 #define mmIH_VMID_14_LUT 0xe0e
42 #define mmIH_VMID_15_LUT 0xe0f
43 #define mmIH_RB_CNTL 0xe30
44 #define mmIH_RB_BASE 0xe31
45 #define mmIH_RB_RPTR 0xe32
46 #define mmIH_RB_WPTR 0xe33
47 #define mmIH_RB_WPTR_ADDR_HI 0xe34
48 #define mmIH_RB_WPTR_ADDR_LO 0xe35
49 #define mmIH_CNTL 0xe36
50 #define mmIH_LEVEL_STATUS 0xe37
51 #define mmIH_STATUS 0xe38
52 #define mmIH_PERFMON_CNTL 0xe39
53 #define mmIH_PERFCOUNTER0_RESULT 0xe3a
54 #define mmIH_PERFCOUNTER1_RESULT 0xe3b
55 #define mmIH_DSM_MATCH_VALUE_BIT_31_0 0xe3d
56 #define mmIH_DSM_MATCH_VALUE_BIT_63_32 0xe3e
57 #define mmIH_DSM_MATCH_VALUE_BIT_95_64 0xe3f
58 #define mmIH_DSM_MATCH_FIELD_CONTROL 0xe40
59 #define mmIH_DSM_MATCH_DATA_CONTROL 0xe41
60 #define mmIH_VERSION 0xe42
61 #define mmSEM_MCIF_CONFIG 0xf90
62 #define mmSDMA_CONFIG 0xf91
63 #define mmSDMA1_CONFIG 0xf92
64 #define mmUVD_CONFIG 0xf93
65 #define mmVCE_CONFIG 0xf94
66 #define mmACP_CONFIG 0xf95
67 #define mmCPG_CONFIG 0xf96
68 #define mmCPC1_CONFIG 0xf97
69 #define mmCPC2_CONFIG 0xf98
70 #define mmSEM_STATUS 0xf99
71 #define mmSEM_EDC_CONFIG 0xf9a
72 #define mmSEM_MAILBOX_CLIENTCONFIG 0xf9b
73 #define mmSEM_MAILBOX 0xf9c
74 #define mmSEM_MAILBOX_CONTROL 0xf9d
75 #define mmSEM_CHICKEN_BITS 0xf9e
76 #define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA 0xf9f
77 #define mmSRBM_CNTL 0x390
78 #define mmSRBM_GFX_CNTL 0x391
79 #define mmSRBM_READ_CNTL 0x392
80 #define mmSRBM_STATUS2 0x393
81 #define mmSRBM_STATUS 0x394
82 #define mmSRBM_STATUS3 0x395
83 #define mmSRBM_SOFT_RESET 0x398
84 #define mmSRBM_DEBUG_CNTL 0x399
85 #define mmSRBM_DEBUG_DATA 0x39a
86 #define mmSRBM_CHIP_REVISION 0x39b
87 #define mmCC_SYS_RB_REDUNDANCY 0x39f
88 #define mmCC_SYS_RB_BACKEND_DISABLE 0x3a0
89 #define mmGC_USER_SYS_RB_BACKEND_DISABLE 0x3a1
90 #define mmSRBM_MC_CLKEN_CNTL 0x3b3
91 #define mmSRBM_SYS_CLKEN_CNTL 0x3b4
92 #define mmSRBM_VCE_CLKEN_CNTL 0x3b5
93 #define mmSRBM_UVD_CLKEN_CNTL 0x3b6
94 #define mmSRBM_SDMA_CLKEN_CNTL 0x3b7
95 #define mmSRBM_SAM_CLKEN_CNTL 0x3b8
96 #define mmSRBM_ISP_CLKEN_CNTL 0x3b9
97 #define mmSRBM_DEBUG 0x3a4
98 #define mmSRBM_DEBUG_SNAPSHOT 0x3a5
99 #define mmSRBM_DEBUG_SNAPSHOT2 0x3ad
100 #define mmSRBM_READ_ERROR 0x3a6
101 #define mmSRBM_READ_ERROR2 0x3ae
102 #define mmSRBM_INT_CNTL 0x3a8
103 #define mmSRBM_INT_STATUS 0x3a9
104 #define mmSRBM_INT_ACK 0x3aa
105 #define mmSRBM_FIREWALL_ERROR_SRC 0x3ab
106 #define mmSRBM_FIREWALL_ERROR_ADDR 0x3ac
107 #define mmSRBM_DSM_TRIG_CNTL0 0x3af
108 #define mmSRBM_DSM_TRIG_CNTL1 0x3b0
109 #define mmSRBM_DSM_TRIG_MASK0 0x3b1
110 #define mmSRBM_DSM_TRIG_MASK1 0x3b2
111 #define mmSRBM_PERFMON_CNTL 0x7c00
112 #define mmSRBM_PERFCOUNTER0_SELECT 0x7c01
113 #define mmSRBM_PERFCOUNTER1_SELECT 0x7c02
114 #define mmSRBM_PERFCOUNTER0_LO 0x7c03
115 #define mmSRBM_PERFCOUNTER0_HI 0x7c04
116 #define mmSRBM_PERFCOUNTER1_LO 0x7c05
117 #define mmSRBM_PERFCOUNTER1_HI 0x7c06
118 #define mmSRBM_CAM_INDEX 0xfe34
119 #define mmSRBM_CAM_DATA 0xfe35
120 #define mmSRBM_MC_DOMAIN_ADDR0 0xfa00
121 #define mmSRBM_MC_DOMAIN_ADDR1 0xfa01
122 #define mmSRBM_MC_DOMAIN_ADDR2 0xfa02
123 #define mmSRBM_MC_DOMAIN_ADDR3 0xfa03
124 #define mmSRBM_MC_DOMAIN_ADDR4 0xfa04
125 #define mmSRBM_MC_DOMAIN_ADDR5 0xfa05
126 #define mmSRBM_MC_DOMAIN_ADDR6 0xfa06
127 #define mmSRBM_SYS_DOMAIN_ADDR0 0xfa08
128 #define mmSRBM_SYS_DOMAIN_ADDR1 0xfa09
129 #define mmSRBM_SYS_DOMAIN_ADDR2 0xfa0a
130 #define mmSRBM_SYS_DOMAIN_ADDR3 0xfa0b
131 #define mmSRBM_SYS_DOMAIN_ADDR4 0xfa0c
132 #define mmSRBM_SYS_DOMAIN_ADDR5 0xfa0d
133 #define mmSRBM_SYS_DOMAIN_ADDR6 0xfa0e
134 #define mmSRBM_SDMA_DOMAIN_ADDR0 0xfa10
135 #define mmSRBM_SDMA_DOMAIN_ADDR1 0xfa11
136 #define mmSRBM_SDMA_DOMAIN_ADDR2 0xfa12
137 #define mmSRBM_SDMA_DOMAIN_ADDR3 0xfa13
138 #define mmSRBM_UVD_DOMAIN_ADDR0 0xfa14
139 #define mmSRBM_UVD_DOMAIN_ADDR1 0xfa15
140 #define mmSRBM_UVD_DOMAIN_ADDR2 0xfa16
141 #define mmSRBM_VCE_DOMAIN_ADDR0 0xfa18
142 #define mmSRBM_VCE_DOMAIN_ADDR1 0xfa19
143 #define mmSRBM_VCE_DOMAIN_ADDR2 0xfa1a
144 #define mmSRBM_SAM_DOMAIN_ADDR0 0xfa1c
145 #define mmSRBM_SAM_DOMAIN_ADDR1 0xfa1d
146 #define mmSRBM_SAM_DOMAIN_ADDR2 0xfa1e
147 #define mmSRBM_ISP_DOMAIN_ADDR0 0xfa20
148 #define mmSRBM_ISP_DOMAIN_ADDR1 0xfa21
149 #define mmSRBM_ISP_DOMAIN_ADDR2 0xfa22
150 #define mmSYS_GRBM_GFX_INDEX_SELECT 0xfa2c
151 #define mmSYS_GRBM_GFX_INDEX_DATA 0xfa2d
152 #define mmSRBM_GFX_CNTL_SELECT 0xfa2e
153 #define mmSRBM_GFX_CNTL_DATA 0xfa2f
154 #define mmSRBM_VF_ENABLE 0xfa30
155 #define mmSRBM_VIRT_CNTL 0xfa31
156 #define mmSRBM_VIRT_RESET_REQ 0xfa32
157 #define mmSDMA0_UCODE_ADDR 0x3400
158 #define mmSDMA0_UCODE_DATA 0x3401
159 #define mmSDMA0_POWER_CNTL 0x3402
160 #define mmSDMA0_CLK_CTRL 0x3403
161 #define mmSDMA0_CNTL 0x3404
162 #define mmSDMA0_CHICKEN_BITS 0x3405
163 #define mmSDMA0_TILING_CONFIG 0x3406
164 #define mmSDMA0_HASH 0x3407
165 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x3409
166 #define mmSDMA0_RB_RPTR_FETCH 0x340a
167 #define mmSDMA0_IB_OFFSET_FETCH 0x340b
168 #define mmSDMA0_PROGRAM 0x340c
169 #define mmSDMA0_STATUS_REG 0x340d
170 #define mmSDMA0_STATUS1_REG 0x340e
171 #define mmSDMA0_PERFMON_CNTL 0x9000
172 #define mmSDMA0_PERFCOUNTER0_RESULT 0x9001
173 #define mmSDMA0_PERFCOUNTER1_RESULT 0x9002
174 #define mmSDMA0_F32_CNTL 0x3412
175 #define mmSDMA0_FREEZE 0x3413
176 #define mmSDMA0_PHASE0_QUANTUM 0x3414
177 #define mmSDMA0_PHASE1_QUANTUM 0x3415
178 #define mmSDMA_POWER_GATING 0x3416
179 #define mmSDMA_PGFSM_CONFIG 0x3417
180 #define mmSDMA_PGFSM_WRITE 0x3418
181 #define mmSDMA_PGFSM_READ 0x3419
182 #define mmSDMA0_EDC_CONFIG 0x341a
183 #define mmSDMA0_BA_THRESHOLD 0x341b
184 #define mmSDMA0_ID 0x341c
185 #define mmSDMA0_VERSION 0x341d
186 #define mmSDMA0_STATUS2_REG 0x341e
187 #define mmSDMA0_GFX_RB_CNTL 0x3480
188 #define mmSDMA0_GFX_RB_BASE 0x3481
189 #define mmSDMA0_GFX_RB_BASE_HI 0x3482
190 #define mmSDMA0_GFX_RB_RPTR 0x3483
191 #define mmSDMA0_GFX_RB_WPTR 0x3484
192 #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x3485
193 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x3486
194 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x3487
195 #define mmSDMA0_GFX_RB_RPTR_ADDR_HI 0x3488
196 #define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x3489
197 #define mmSDMA0_GFX_IB_CNTL 0x348a
198 #define mmSDMA0_GFX_IB_RPTR 0x348b
199 #define mmSDMA0_GFX_IB_OFFSET 0x348c
200 #define mmSDMA0_GFX_IB_BASE_LO 0x348d
201 #define mmSDMA0_GFX_IB_BASE_HI 0x348e
202 #define mmSDMA0_GFX_IB_SIZE 0x348f
203 #define mmSDMA0_GFX_SKIP_CNTL 0x3490
204 #define mmSDMA0_GFX_CONTEXT_STATUS 0x3491
205 #define mmSDMA0_GFX_CONTEXT_CNTL 0x3493
206 #define mmSDMA0_GFX_VIRTUAL_ADDR 0x34a7
207 #define mmSDMA0_GFX_APE1_CNTL 0x34a8
208 #define mmSDMA0_GFX_WATERMARK 0x34aa
209 #define mmSDMA0_GFX_CSA_ADDR_LO 0x34ac
210 #define mmSDMA0_GFX_CSA_ADDR_HI 0x34ad
211 #define mmSDMA0_GFX_DUMMY_REG 0x34ae
212 #define mmSDMA0_GFX_IB_SUB_REMAIN 0x34af
213 #define mmSDMA0_GFX_PREEMPT 0x34b0
214 #define mmSDMA0_RLC0_RB_CNTL 0x3500
215 #define mmSDMA0_RLC0_RB_BASE 0x3501
216 #define mmSDMA0_RLC0_RB_BASE_HI 0x3502
217 #define mmSDMA0_RLC0_RB_RPTR 0x3503
218 #define mmSDMA0_RLC0_RB_WPTR 0x3504
219 #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x3505
220 #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x3506
221 #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x3507
222 #define mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0x3508
223 #define mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0x3509
224 #define mmSDMA0_RLC0_IB_CNTL 0x350a
225 #define mmSDMA0_RLC0_IB_RPTR 0x350b
226 #define mmSDMA0_RLC0_IB_OFFSET 0x350c
227 #define mmSDMA0_RLC0_IB_BASE_LO 0x350d
228 #define mmSDMA0_RLC0_IB_BASE_HI 0x350e
229 #define mmSDMA0_RLC0_IB_SIZE 0x350f
230 #define mmSDMA0_RLC0_SKIP_CNTL 0x3510
231 #define mmSDMA0_RLC0_CONTEXT_STATUS 0x3511
232 #define mmSDMA0_RLC0_DOORBELL 0x3512
233 #define mmSDMA0_RLC0_VIRTUAL_ADDR 0x3527
234 #define mmSDMA0_RLC0_APE1_CNTL 0x3528
235 #define mmSDMA0_RLC0_DOORBELL_LOG 0x3529
236 #define mmSDMA0_RLC0_WATERMARK 0x352a
237 #define mmSDMA0_RLC0_CSA_ADDR_LO 0x352c
238 #define mmSDMA0_RLC0_CSA_ADDR_HI 0x352d
239 #define mmSDMA0_RLC0_DUMMY_REG 0x352e
240 #define mmSDMA0_RLC0_IB_SUB_REMAIN 0x352f
241 #define mmSDMA0_RLC0_PREEMPT 0x3530
242 #define mmSDMA0_RLC1_RB_CNTL 0x3580
243 #define mmSDMA0_RLC1_RB_BASE 0x3581
244 #define mmSDMA0_RLC1_RB_BASE_HI 0x3582
245 #define mmSDMA0_RLC1_RB_RPTR 0x3583
246 #define mmSDMA0_RLC1_RB_WPTR 0x3584
247 #define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x3585
248 #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x3586
249 #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x3587
250 #define mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0x3588
251 #define mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0x3589
252 #define mmSDMA0_RLC1_IB_CNTL 0x358a
253 #define mmSDMA0_RLC1_IB_RPTR 0x358b
254 #define mmSDMA0_RLC1_IB_OFFSET 0x358c
255 #define mmSDMA0_RLC1_IB_BASE_LO 0x358d
256 #define mmSDMA0_RLC1_IB_BASE_HI 0x358e
257 #define mmSDMA0_RLC1_IB_SIZE 0x358f
258 #define mmSDMA0_RLC1_SKIP_CNTL 0x3590
259 #define mmSDMA0_RLC1_CONTEXT_STATUS 0x3591
260 #define mmSDMA0_RLC1_DOORBELL 0x3592
261 #define mmSDMA0_RLC1_VIRTUAL_ADDR 0x35a7
262 #define mmSDMA0_RLC1_APE1_CNTL 0x35a8
263 #define mmSDMA0_RLC1_DOORBELL_LOG 0x35a9
264 #define mmSDMA0_RLC1_WATERMARK 0x35aa
265 #define mmSDMA0_RLC1_CSA_ADDR_LO 0x35ac
266 #define mmSDMA0_RLC1_CSA_ADDR_HI 0x35ad
267 #define mmSDMA0_RLC1_DUMMY_REG 0x35ae
268 #define mmSDMA0_RLC1_IB_SUB_REMAIN 0x35af
269 #define mmSDMA0_RLC1_PREEMPT 0x35b0
270 #define mmSDMA1_UCODE_ADDR 0x3600
271 #define mmSDMA1_UCODE_DATA 0x3601
272 #define mmSDMA1_POWER_CNTL 0x3602
273 #define mmSDMA1_CLK_CTRL 0x3603
274 #define mmSDMA1_CNTL 0x3604
275 #define mmSDMA1_CHICKEN_BITS 0x3605
276 #define mmSDMA1_TILING_CONFIG 0x3606
277 #define mmSDMA1_HASH 0x3607
278 #define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x3609
279 #define mmSDMA1_RB_RPTR_FETCH 0x360a
280 #define mmSDMA1_IB_OFFSET_FETCH 0x360b
281 #define mmSDMA1_PROGRAM 0x360c
282 #define mmSDMA1_STATUS_REG 0x360d
283 #define mmSDMA1_STATUS1_REG 0x360e
284 #define mmSDMA1_PERFMON_CNTL 0x9010
285 #define mmSDMA1_PERFCOUNTER0_RESULT 0x9011
286 #define mmSDMA1_PERFCOUNTER1_RESULT 0x9012
287 #define mmSDMA1_F32_CNTL 0x3612
288 #define mmSDMA1_FREEZE 0x3613
289 #define mmSDMA1_PHASE0_QUANTUM 0x3614
290 #define mmSDMA1_PHASE1_QUANTUM 0x3615
291 #define mmSDMA1_EDC_CONFIG 0x361a
292 #define mmSDMA1_BA_THRESHOLD 0x361b
293 #define mmSDMA1_ID 0x361c
294 #define mmSDMA1_VERSION 0x361d
295 #define mmSDMA1_STATUS2_REG 0x361e
296 #define mmSDMA1_GFX_RB_CNTL 0x3680
297 #define mmSDMA1_GFX_RB_BASE 0x3681
298 #define mmSDMA1_GFX_RB_BASE_HI 0x3682
299 #define mmSDMA1_GFX_RB_RPTR 0x3683
300 #define mmSDMA1_GFX_RB_WPTR 0x3684
301 #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x3685
302 #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x3686
303 #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x3687
304 #define mmSDMA1_GFX_RB_RPTR_ADDR_HI 0x3688
305 #define mmSDMA1_GFX_RB_RPTR_ADDR_LO 0x3689
306 #define mmSDMA1_GFX_IB_CNTL 0x368a
307 #define mmSDMA1_GFX_IB_RPTR 0x368b
308 #define mmSDMA1_GFX_IB_OFFSET 0x368c
309 #define mmSDMA1_GFX_IB_BASE_LO 0x368d
310 #define mmSDMA1_GFX_IB_BASE_HI 0x368e
311 #define mmSDMA1_GFX_IB_SIZE 0x368f
312 #define mmSDMA1_GFX_SKIP_CNTL 0x3690
313 #define mmSDMA1_GFX_CONTEXT_STATUS 0x3691
314 #define mmSDMA1_GFX_CONTEXT_CNTL 0x3693
315 #define mmSDMA1_GFX_VIRTUAL_ADDR 0x36a7
316 #define mmSDMA1_GFX_APE1_CNTL 0x36a8
317 #define mmSDMA1_GFX_WATERMARK 0x36aa
318 #define mmSDMA1_GFX_CSA_ADDR_LO 0x36ac
319 #define mmSDMA1_GFX_CSA_ADDR_HI 0x36ad
320 #define mmSDMA1_GFX_DUMMY_REG 0x36ae
321 #define mmSDMA1_GFX_IB_SUB_REMAIN 0x36af
322 #define mmSDMA1_GFX_PREEMPT 0x36b0
323 #define mmSDMA1_RLC0_RB_CNTL 0x3700
324 #define mmSDMA1_RLC0_RB_BASE 0x3701
325 #define mmSDMA1_RLC0_RB_BASE_HI 0x3702
326 #define mmSDMA1_RLC0_RB_RPTR 0x3703
327 #define mmSDMA1_RLC0_RB_WPTR 0x3704
328 #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x3705
329 #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x3706
330 #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x3707
331 #define mmSDMA1_RLC0_RB_RPTR_ADDR_HI 0x3708
332 #define mmSDMA1_RLC0_RB_RPTR_ADDR_LO 0x3709
333 #define mmSDMA1_RLC0_IB_CNTL 0x370a
334 #define mmSDMA1_RLC0_IB_RPTR 0x370b
335 #define mmSDMA1_RLC0_IB_OFFSET 0x370c
336 #define mmSDMA1_RLC0_IB_BASE_LO 0x370d
337 #define mmSDMA1_RLC0_IB_BASE_HI 0x370e
338 #define mmSDMA1_RLC0_IB_SIZE 0x370f
339 #define mmSDMA1_RLC0_SKIP_CNTL 0x3710
340 #define mmSDMA1_RLC0_CONTEXT_STATUS 0x3711
341 #define mmSDMA1_RLC0_DOORBELL 0x3712
342 #define mmSDMA1_RLC0_VIRTUAL_ADDR 0x3727
343 #define mmSDMA1_RLC0_APE1_CNTL 0x3728
344 #define mmSDMA1_RLC0_DOORBELL_LOG 0x3729
345 #define mmSDMA1_RLC0_WATERMARK 0x372a
346 #define mmSDMA1_RLC0_CSA_ADDR_LO 0x372c
347 #define mmSDMA1_RLC0_CSA_ADDR_HI 0x372d
348 #define mmSDMA1_RLC0_DUMMY_REG 0x372e
349 #define mmSDMA1_RLC0_IB_SUB_REMAIN 0x372f
350 #define mmSDMA1_RLC0_PREEMPT 0x3730
351 #define mmSDMA1_RLC1_RB_CNTL 0x3780
352 #define mmSDMA1_RLC1_RB_BASE 0x3781
353 #define mmSDMA1_RLC1_RB_BASE_HI 0x3782
354 #define mmSDMA1_RLC1_RB_RPTR 0x3783
355 #define mmSDMA1_RLC1_RB_WPTR 0x3784
356 #define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x3785
357 #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x3786
358 #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x3787
359 #define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x3788
360 #define mmSDMA1_RLC1_RB_RPTR_ADDR_LO 0x3789
361 #define mmSDMA1_RLC1_IB_CNTL 0x378a
362 #define mmSDMA1_RLC1_IB_RPTR 0x378b
363 #define mmSDMA1_RLC1_IB_OFFSET 0x378c
364 #define mmSDMA1_RLC1_IB_BASE_LO 0x378d
365 #define mmSDMA1_RLC1_IB_BASE_HI 0x378e
366 #define mmSDMA1_RLC1_IB_SIZE 0x378f
367 #define mmSDMA1_RLC1_SKIP_CNTL 0x3790
368 #define mmSDMA1_RLC1_CONTEXT_STATUS 0x3791
369 #define mmSDMA1_RLC1_DOORBELL 0x3792
370 #define mmSDMA1_RLC1_VIRTUAL_ADDR 0x37a7
371 #define mmSDMA1_RLC1_APE1_CNTL 0x37a8
372 #define mmSDMA1_RLC1_DOORBELL_LOG 0x37a9
373 #define mmSDMA1_RLC1_WATERMARK 0x37aa
374 #define mmSDMA1_RLC1_CSA_ADDR_LO 0x37ac
375 #define mmSDMA1_RLC1_CSA_ADDR_HI 0x37ad
376 #define mmSDMA1_RLC1_DUMMY_REG 0x37ae
377 #define mmSDMA1_RLC1_IB_SUB_REMAIN 0x37af
378 #define mmSDMA1_RLC1_PREEMPT 0x37b0
379 #define mmHDP_HOST_PATH_CNTL 0xb00
380 #define mmHDP_NONSURFACE_BASE 0xb01
381 #define mmHDP_NONSURFACE_INFO 0xb02
382 #define mmHDP_NONSURFACE_SIZE 0xb03
383 #define mmHDP_NONSURF_FLAGS 0xbc9
384 #define mmHDP_NONSURF_FLAGS_CLR 0xbca
385 #define mmHDP_SW_SEMAPHORE 0xbcb
386 #define mmHDP_DEBUG0 0xbcc
387 #define mmHDP_DEBUG1 0xbcd
388 #define mmHDP_LAST_SURFACE_HIT 0xbce
389 #define mmHDP_TILING_CONFIG 0xbcf
390 #define mmHDP_SC_MULTI_CHIP_CNTL 0xbd0
391 #define mmHDP_OUTSTANDING_REQ 0xbd1
392 #define mmHDP_ADDR_CONFIG 0xbd2
393 #define mmHDP_MISC_CNTL 0xbd3
394 #define mmHDP_MEM_POWER_LS 0xbd4
395 #define mmHDP_NONSURFACE_PREFETCH 0xbd5
396 #define mmHDP_MEMIO_CNTL 0xbf6
397 #define mmHDP_MEMIO_ADDR 0xbf7
398 #define mmHDP_MEMIO_STATUS 0xbf8
399 #define mmHDP_MEMIO_WR_DATA 0xbf9
400 #define mmHDP_MEMIO_RD_DATA 0xbfa
401 #define mmHDP_XDP_DIRECT2HDP_FIRST 0xc00
402 #define mmHDP_XDP_D2H_FLUSH 0xc01
403 #define mmHDP_XDP_D2H_BAR_UPDATE 0xc02
404 #define mmHDP_XDP_D2H_RSVD_3 0xc03
405 #define mmHDP_XDP_D2H_RSVD_4 0xc04
406 #define mmHDP_XDP_D2H_RSVD_5 0xc05
407 #define mmHDP_XDP_D2H_RSVD_6 0xc06
408 #define mmHDP_XDP_D2H_RSVD_7 0xc07
409 #define mmHDP_XDP_D2H_RSVD_8 0xc08
410 #define mmHDP_XDP_D2H_RSVD_9 0xc09
411 #define mmHDP_XDP_D2H_RSVD_10 0xc0a
412 #define mmHDP_XDP_D2H_RSVD_11 0xc0b
413 #define mmHDP_XDP_D2H_RSVD_12 0xc0c
414 #define mmHDP_XDP_D2H_RSVD_13 0xc0d
415 #define mmHDP_XDP_D2H_RSVD_14 0xc0e
416 #define mmHDP_XDP_D2H_RSVD_15 0xc0f
417 #define mmHDP_XDP_D2H_RSVD_16 0xc10
418 #define mmHDP_XDP_D2H_RSVD_17 0xc11
419 #define mmHDP_XDP_D2H_RSVD_18 0xc12
420 #define mmHDP_XDP_D2H_RSVD_19 0xc13
421 #define mmHDP_XDP_D2H_RSVD_20 0xc14
422 #define mmHDP_XDP_D2H_RSVD_21 0xc15
423 #define mmHDP_XDP_D2H_RSVD_22 0xc16
424 #define mmHDP_XDP_D2H_RSVD_23 0xc17
425 #define mmHDP_XDP_D2H_RSVD_24 0xc18
426 #define mmHDP_XDP_D2H_RSVD_25 0xc19
427 #define mmHDP_XDP_D2H_RSVD_26 0xc1a
428 #define mmHDP_XDP_D2H_RSVD_27 0xc1b
429 #define mmHDP_XDP_D2H_RSVD_28 0xc1c
430 #define mmHDP_XDP_D2H_RSVD_29 0xc1d
431 #define mmHDP_XDP_D2H_RSVD_30 0xc1e
432 #define mmHDP_XDP_D2H_RSVD_31 0xc1f
433 #define mmHDP_XDP_D2H_RSVD_32 0xc20
434 #define mmHDP_XDP_D2H_RSVD_33 0xc21
435 #define mmHDP_XDP_D2H_RSVD_34 0xc22
436 #define mmHDP_XDP_DIRECT2HDP_LAST 0xc23
437 #define mmHDP_XDP_P2P_BAR_CFG 0xc24
438 #define mmHDP_XDP_P2P_MBX_OFFSET 0xc25
439 #define mmHDP_XDP_P2P_MBX_ADDR0 0xc26
440 #define mmHDP_XDP_P2P_MBX_ADDR1 0xc27
441 #define mmHDP_XDP_P2P_MBX_ADDR2 0xc28
442 #define mmHDP_XDP_P2P_MBX_ADDR3 0xc29
443 #define mmHDP_XDP_P2P_MBX_ADDR4 0xc2a
444 #define mmHDP_XDP_P2P_MBX_ADDR5 0xc2b
445 #define mmHDP_XDP_P2P_MBX_ADDR6 0xc2c
446 #define mmHDP_XDP_HDP_MBX_MC_CFG 0xc2d
447 #define mmHDP_XDP_HDP_MC_CFG 0xc2e
448 #define mmHDP_XDP_HST_CFG 0xc2f
449 #define mmHDP_XDP_SID_CFG 0xc30
450 #define mmHDP_XDP_HDP_IPH_CFG 0xc31
451 #define mmHDP_XDP_SRBM_CFG 0xc32
452 #define mmHDP_XDP_CGTT_BLK_CTRL 0xc33
453 #define mmHDP_XDP_P2P_BAR0 0xc34
454 #define mmHDP_XDP_P2P_BAR1 0xc35
455 #define mmHDP_XDP_P2P_BAR2 0xc36
456 #define mmHDP_XDP_P2P_BAR3 0xc37
457 #define mmHDP_XDP_P2P_BAR4 0xc38
458 #define mmHDP_XDP_P2P_BAR5 0xc39
459 #define mmHDP_XDP_P2P_BAR6 0xc3a
460 #define mmHDP_XDP_P2P_BAR7 0xc3b
461 #define mmHDP_XDP_FLUSH_ARMED_STS 0xc3c
462 #define mmHDP_XDP_FLUSH_CNTR0_STS 0xc3d
463 #define mmHDP_XDP_BUSY_STS 0xc3e
464 #define mmHDP_XDP_STICKY 0xc3f
465 #define mmHDP_XDP_CHKN 0xc40
466 #define mmHDP_XDP_DBG_ADDR 0xc41
467 #define mmHDP_XDP_DBG_DATA 0xc42
468 #define mmHDP_XDP_DBG_MASK 0xc43
469 #define mmHDP_XDP_BARS_ADDR_39_36 0xc44
470
471 #endif