root/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_enum.h

   1 /*
   2  * OSS_3_0 Register documentation
   3  *
   4  * Copyright (C) 2014  Advanced Micro Devices, Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included
  14  * in all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  20  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 
  24 #ifndef OSS_3_0_ENUM_H
  25 #define OSS_3_0_ENUM_H
  26 
  27 typedef enum IH_CLIENT_ID {
  28         DC_IH_SRC_ID_START                               = 0x1,
  29         DC_IH_SRC_ID_END                                 = 0x1f,
  30         VGA_IH_SRC_ID_START                              = 0x20,
  31         VGA_IH_SRC_ID_END                                = 0x27,
  32         CAP_IH_SRC_ID_START                              = 0x28,
  33         CAP_IH_SRC_ID_END                                = 0x2f,
  34         VIP_IH_SRC_ID_START                              = 0x30,
  35         VIP_IH_SRC_ID_END                                = 0x3f,
  36         ROM_IH_SRC_ID_START                              = 0x40,
  37         ROM_IH_SRC_ID_END                                = 0x5d,
  38         BIF_IH_SRC_ID_START                              = 0x5e,
  39         SAM_IH_SRC_ID_START                              = 0x5f,
  40         SRBM_IH_SRC_ID_START                             = 0x60,
  41         SRBM_IH_SRC_ID_END                               = 0x67,
  42         UVD_IH_SRC_ID_START                              = 0x72,
  43         UVD_IH_SRC_ID_END                                = 0x85,
  44         VMC_IH_SRC_ID_START                              = 0x86,
  45         VMC_IH_SRC_ID_END                                = 0x8f,
  46         RLC_IH_SRC_ID_START                              = 0x90,
  47         RLC_IH_SRC_ID_END                                = 0xf3,
  48         PDMA_IH_SRC_ID_START                             = 0xf4,
  49         PDMA_IH_SRC_ID_END                               = 0xf7,
  50         CG_IH_SRC_ID_START                               = 0xf8,
  51         CG_IH_SRC_ID_END                                 = 0xff,
  52 } IH_CLIENT_ID;
  53 typedef enum IH_PERF_SEL {
  54         IH_PERF_SEL_CYCLE                                = 0x0,
  55         IH_PERF_SEL_IDLE                                 = 0x1,
  56         IH_PERF_SEL_INPUT_IDLE                           = 0x2,
  57         IH_PERF_SEL_CLIENT0_IH_STALL                     = 0x3,
  58         IH_PERF_SEL_CLIENT1_IH_STALL                     = 0x4,
  59         IH_PERF_SEL_CLIENT2_IH_STALL                     = 0x5,
  60         IH_PERF_SEL_CLIENT3_IH_STALL                     = 0x6,
  61         IH_PERF_SEL_CLIENT4_IH_STALL                     = 0x7,
  62         IH_PERF_SEL_CLIENT5_IH_STALL                     = 0x8,
  63         IH_PERF_SEL_CLIENT6_IH_STALL                     = 0x9,
  64         IH_PERF_SEL_CLIENT7_IH_STALL                     = 0xa,
  65         IH_PERF_SEL_RB_IDLE                              = 0xb,
  66         IH_PERF_SEL_RB_FULL                              = 0xc,
  67         IH_PERF_SEL_RB_OVERFLOW                          = 0xd,
  68         IH_PERF_SEL_RB_WPTR_WRITEBACK                    = 0xe,
  69         IH_PERF_SEL_RB_WPTR_WRAP                         = 0xf,
  70         IH_PERF_SEL_RB_RPTR_WRAP                         = 0x10,
  71         IH_PERF_SEL_MC_WR_IDLE                           = 0x11,
  72         IH_PERF_SEL_MC_WR_COUNT                          = 0x12,
  73         IH_PERF_SEL_MC_WR_STALL                          = 0x13,
  74         IH_PERF_SEL_MC_WR_CLEAN_PENDING                  = 0x14,
  75         IH_PERF_SEL_MC_WR_CLEAN_STALL                    = 0x15,
  76         IH_PERF_SEL_BIF_RISING                           = 0x16,
  77         IH_PERF_SEL_BIF_FALLING                          = 0x17,
  78         IH_PERF_SEL_CLIENT8_IH_STALL                     = 0x18,
  79         IH_PERF_SEL_CLIENT9_IH_STALL                     = 0x19,
  80         IH_PERF_SEL_CLIENT10_IH_STALL                    = 0x1a,
  81         IH_PERF_SEL_CLIENT11_IH_STALL                    = 0x1b,
  82         IH_PERF_SEL_CLIENT12_IH_STALL                    = 0x1c,
  83         IH_PERF_SEL_CLIENT13_IH_STALL                    = 0x1d,
  84         IH_PERF_SEL_CLIENT14_IH_STALL                    = 0x1e,
  85         IH_PERF_SEL_CLIENT15_IH_STALL                    = 0x1f,
  86         IH_PERF_SEL_CLIENT16_IH_STALL                    = 0x20,
  87         IH_PERF_SEL_CLIENT17_IH_STALL                    = 0x21,
  88         IH_PERF_SEL_CLIENT18_IH_STALL                    = 0x22,
  89         IH_PERF_SEL_CLIENT19_IH_STALL                    = 0x23,
  90         IH_PERF_SEL_CLIENT20_IH_STALL                    = 0x24,
  91         IH_PERF_SEL_CLIENT21_IH_STALL                    = 0x25,
  92         IH_PERF_SEL_CLIENT22_IH_STALL                    = 0x26,
  93         IH_PERF_SEL_RB_FULL_VF0                          = 0x27,
  94         IH_PERF_SEL_RB_FULL_VF1                          = 0x28,
  95         IH_PERF_SEL_RB_FULL_VF2                          = 0x29,
  96         IH_PERF_SEL_RB_FULL_VF3                          = 0x2a,
  97         IH_PERF_SEL_RB_FULL_VF4                          = 0x2b,
  98         IH_PERF_SEL_RB_FULL_VF5                          = 0x2c,
  99         IH_PERF_SEL_RB_FULL_VF6                          = 0x2d,
 100         IH_PERF_SEL_RB_FULL_VF7                          = 0x2e,
 101         IH_PERF_SEL_RB_FULL_VF8                          = 0x2f,
 102         IH_PERF_SEL_RB_FULL_VF9                          = 0x30,
 103         IH_PERF_SEL_RB_FULL_VF10                         = 0x31,
 104         IH_PERF_SEL_RB_FULL_VF11                         = 0x32,
 105         IH_PERF_SEL_RB_FULL_VF12                         = 0x33,
 106         IH_PERF_SEL_RB_FULL_VF13                         = 0x34,
 107         IH_PERF_SEL_RB_FULL_VF14                         = 0x35,
 108         IH_PERF_SEL_RB_FULL_VF15                         = 0x36,
 109         IH_PERF_SEL_RB_OVERFLOW_VF0                      = 0x37,
 110         IH_PERF_SEL_RB_OVERFLOW_VF1                      = 0x38,
 111         IH_PERF_SEL_RB_OVERFLOW_VF2                      = 0x39,
 112         IH_PERF_SEL_RB_OVERFLOW_VF3                      = 0x3a,
 113         IH_PERF_SEL_RB_OVERFLOW_VF4                      = 0x3b,
 114         IH_PERF_SEL_RB_OVERFLOW_VF5                      = 0x3c,
 115         IH_PERF_SEL_RB_OVERFLOW_VF6                      = 0x3d,
 116         IH_PERF_SEL_RB_OVERFLOW_VF7                      = 0x3e,
 117         IH_PERF_SEL_RB_OVERFLOW_VF8                      = 0x3f,
 118         IH_PERF_SEL_RB_OVERFLOW_VF9                      = 0x40,
 119         IH_PERF_SEL_RB_OVERFLOW_VF10                     = 0x41,
 120         IH_PERF_SEL_RB_OVERFLOW_VF11                     = 0x42,
 121         IH_PERF_SEL_RB_OVERFLOW_VF12                     = 0x43,
 122         IH_PERF_SEL_RB_OVERFLOW_VF13                     = 0x44,
 123         IH_PERF_SEL_RB_OVERFLOW_VF14                     = 0x45,
 124         IH_PERF_SEL_RB_OVERFLOW_VF15                     = 0x46,
 125         IH_PERF_SEL_RB_WPTR_WRITEBACK_VF0                = 0x47,
 126         IH_PERF_SEL_RB_WPTR_WRITEBACK_VF1                = 0x48,
 127         IH_PERF_SEL_RB_WPTR_WRITEBACK_VF2                = 0x49,
 128         IH_PERF_SEL_RB_WPTR_WRITEBACK_VF3                = 0x4a,
 129         IH_PERF_SEL_RB_WPTR_WRITEBACK_VF4                = 0x4b,
 130         IH_PERF_SEL_RB_WPTR_WRITEBACK_VF5                = 0x4c,
 131         IH_PERF_SEL_RB_WPTR_WRITEBACK_VF6                = 0x4d,
 132         IH_PERF_SEL_RB_WPTR_WRITEBACK_VF7                = 0x4e,
 133         IH_PERF_SEL_RB_WPTR_WRITEBACK_VF8                = 0x4f,
 134         IH_PERF_SEL_RB_WPTR_WRITEBACK_VF9                = 0x50,
 135         IH_PERF_SEL_RB_WPTR_WRITEBACK_VF10               = 0x51,
 136         IH_PERF_SEL_RB_WPTR_WRITEBACK_VF11               = 0x52,
 137         IH_PERF_SEL_RB_WPTR_WRITEBACK_VF12               = 0x53,
 138         IH_PERF_SEL_RB_WPTR_WRITEBACK_VF13               = 0x54,
 139         IH_PERF_SEL_RB_WPTR_WRITEBACK_VF14               = 0x55,
 140         IH_PERF_SEL_RB_WPTR_WRITEBACK_VF15               = 0x56,
 141         IH_PERF_SEL_RB_WPTR_WRAP_VF0                     = 0x57,
 142         IH_PERF_SEL_RB_WPTR_WRAP_VF1                     = 0x58,
 143         IH_PERF_SEL_RB_WPTR_WRAP_VF2                     = 0x59,
 144         IH_PERF_SEL_RB_WPTR_WRAP_VF3                     = 0x5a,
 145         IH_PERF_SEL_RB_WPTR_WRAP_VF4                     = 0x5b,
 146         IH_PERF_SEL_RB_WPTR_WRAP_VF5                     = 0x5c,
 147         IH_PERF_SEL_RB_WPTR_WRAP_VF6                     = 0x5d,
 148         IH_PERF_SEL_RB_WPTR_WRAP_VF7                     = 0x5e,
 149         IH_PERF_SEL_RB_WPTR_WRAP_VF8                     = 0x5f,
 150         IH_PERF_SEL_RB_WPTR_WRAP_VF9                     = 0x60,
 151         IH_PERF_SEL_RB_WPTR_WRAP_VF10                    = 0x61,
 152         IH_PERF_SEL_RB_WPTR_WRAP_VF11                    = 0x62,
 153         IH_PERF_SEL_RB_WPTR_WRAP_VF12                    = 0x63,
 154         IH_PERF_SEL_RB_WPTR_WRAP_VF13                    = 0x64,
 155         IH_PERF_SEL_RB_WPTR_WRAP_VF14                    = 0x65,
 156         IH_PERF_SEL_RB_WPTR_WRAP_VF15                    = 0x66,
 157         IH_PERF_SEL_RB_RPTR_WRAP_VF0                     = 0x67,
 158         IH_PERF_SEL_RB_RPTR_WRAP_VF1                     = 0x68,
 159         IH_PERF_SEL_RB_RPTR_WRAP_VF2                     = 0x69,
 160         IH_PERF_SEL_RB_RPTR_WRAP_VF3                     = 0x6a,
 161         IH_PERF_SEL_RB_RPTR_WRAP_VF4                     = 0x6b,
 162         IH_PERF_SEL_RB_RPTR_WRAP_VF5                     = 0x6c,
 163         IH_PERF_SEL_RB_RPTR_WRAP_VF6                     = 0x6d,
 164         IH_PERF_SEL_RB_RPTR_WRAP_VF7                     = 0x6e,
 165         IH_PERF_SEL_RB_RPTR_WRAP_VF8                     = 0x6f,
 166         IH_PERF_SEL_RB_RPTR_WRAP_VF9                     = 0x70,
 167         IH_PERF_SEL_RB_RPTR_WRAP_VF10                    = 0x71,
 168         IH_PERF_SEL_RB_RPTR_WRAP_VF11                    = 0x72,
 169         IH_PERF_SEL_RB_RPTR_WRAP_VF12                    = 0x73,
 170         IH_PERF_SEL_RB_RPTR_WRAP_VF13                    = 0x74,
 171         IH_PERF_SEL_RB_RPTR_WRAP_VF14                    = 0x75,
 172         IH_PERF_SEL_RB_RPTR_WRAP_VF15                    = 0x76,
 173         IH_PERF_SEL_BIF_RISING_VF0                       = 0x77,
 174         IH_PERF_SEL_BIF_RISING_VF1                       = 0x78,
 175         IH_PERF_SEL_BIF_RISING_VF2                       = 0x79,
 176         IH_PERF_SEL_BIF_RISING_VF3                       = 0x7a,
 177         IH_PERF_SEL_BIF_RISING_VF4                       = 0x7b,
 178         IH_PERF_SEL_BIF_RISING_VF5                       = 0x7c,
 179         IH_PERF_SEL_BIF_RISING_VF6                       = 0x7d,
 180         IH_PERF_SEL_BIF_RISING_VF7                       = 0x7e,
 181         IH_PERF_SEL_BIF_RISING_VF8                       = 0x7f,
 182         IH_PERF_SEL_BIF_RISING_VF9                       = 0x80,
 183         IH_PERF_SEL_BIF_RISING_VF10                      = 0x81,
 184         IH_PERF_SEL_BIF_RISING_VF11                      = 0x82,
 185         IH_PERF_SEL_BIF_RISING_VF12                      = 0x83,
 186         IH_PERF_SEL_BIF_RISING_VF13                      = 0x84,
 187         IH_PERF_SEL_BIF_RISING_VF14                      = 0x85,
 188         IH_PERF_SEL_BIF_RISING_VF15                      = 0x86,
 189         IH_PERF_SEL_BIF_FALLING_VF0                      = 0x87,
 190         IH_PERF_SEL_BIF_FALLING_VF1                      = 0x88,
 191         IH_PERF_SEL_BIF_FALLING_VF2                      = 0x89,
 192         IH_PERF_SEL_BIF_FALLING_VF3                      = 0x8a,
 193         IH_PERF_SEL_BIF_FALLING_VF4                      = 0x8b,
 194         IH_PERF_SEL_BIF_FALLING_VF5                      = 0x8c,
 195         IH_PERF_SEL_BIF_FALLING_VF6                      = 0x8d,
 196         IH_PERF_SEL_BIF_FALLING_VF7                      = 0x8e,
 197         IH_PERF_SEL_BIF_FALLING_VF8                      = 0x8f,
 198         IH_PERF_SEL_BIF_FALLING_VF9                      = 0x90,
 199         IH_PERF_SEL_BIF_FALLING_VF10                     = 0x91,
 200         IH_PERF_SEL_BIF_FALLING_VF11                     = 0x92,
 201         IH_PERF_SEL_BIF_FALLING_VF12                     = 0x93,
 202         IH_PERF_SEL_BIF_FALLING_VF13                     = 0x94,
 203         IH_PERF_SEL_BIF_FALLING_VF14                     = 0x95,
 204         IH_PERF_SEL_BIF_FALLING_VF15                     = 0x96,
 205 } IH_PERF_SEL;
 206 typedef enum SRBM_PERFCOUNT1_SEL {
 207         SRBM_PERF_SEL_COUNT                              = 0x0,
 208         SRBM_PERF_SEL_BIF_BUSY                           = 0x1,
 209         SRBM_PERF_SEL_SDMA0_BUSY                         = 0x3,
 210         SRBM_PERF_SEL_IH_BUSY                            = 0x4,
 211         SRBM_PERF_SEL_MCB_BUSY                           = 0x5,
 212         SRBM_PERF_SEL_MCB_NON_DISPLAY_BUSY               = 0x6,
 213         SRBM_PERF_SEL_MCC_BUSY                           = 0x7,
 214         SRBM_PERF_SEL_MCD_BUSY                           = 0x8,
 215         SRBM_PERF_SEL_CHUB_BUSY                          = 0x9,
 216         SRBM_PERF_SEL_SEM_BUSY                           = 0xa,
 217         SRBM_PERF_SEL_UVD_BUSY                           = 0xb,
 218         SRBM_PERF_SEL_VMC_BUSY                           = 0xc,
 219         SRBM_PERF_SEL_ODE_BUSY                           = 0xd,
 220         SRBM_PERF_SEL_SDMA1_BUSY                         = 0xe,
 221         SRBM_PERF_SEL_SAMMSP_BUSY                        = 0xf,
 222         SRBM_PERF_SEL_VCE0_BUSY                          = 0x10,
 223         SRBM_PERF_SEL_XDMA_BUSY                          = 0x11,
 224         SRBM_PERF_SEL_ACP_BUSY                           = 0x12,
 225         SRBM_PERF_SEL_SDMA2_BUSY                         = 0x13,
 226         SRBM_PERF_SEL_SDMA3_BUSY                         = 0x14,
 227         SRBM_PERF_SEL_SAMSCP_BUSY                        = 0x15,
 228         SRBM_PERF_SEL_VMC1_BUSY                          = 0x16,
 229         SRBM_PERF_SEL_ISP_BUSY                           = 0x17,
 230         SRBM_PERF_SEL_VCE1_BUSY                          = 0x18,
 231         SRBM_PERF_SEL_GCATCL2_BUSY                       = 0x19,
 232         SRBM_PERF_SEL_OSATCL2_BUSY                       = 0x1a,
 233         SRBM_PERF_SEL_VP8_BUSY                           = 0x1b,
 234 } SRBM_PERFCOUNT1_SEL;
 235 typedef enum SYS_GRBM_GFX_INDEX_SEL {
 236         GRBM_GFX_INDEX_BIF                               = 0x0,
 237         GRBM_GFX_INDEX_SDMA0                             = 0x1,
 238         GRBM_GFX_INDEX_SDMA1                             = 0x2,
 239         RESEVERED0                                       = 0x3,
 240         GRBM_GFX_INDEX_UVD                               = 0x4,
 241         GRBM_GFX_INDEX_VCE0                              = 0x5,
 242         GRBM_GFX_INDEX_VCE1                              = 0x6,
 243         GRBM_GFX_INDEX_ACP                               = 0x7,
 244         GRBM_GFX_INDEX_SMU                               = 0x8,
 245         GRBM_GFX_INDEX_SAMMSP                            = 0x9,
 246         GRBM_GFX_INDEX_SAMSCP                            = 0xa,
 247         GRBM_GFX_INDEX_ISP                               = 0xb,
 248         GRBM_GFX_INDEX_TST                               = 0xc,
 249         GRBM_GFX_INDEX_SDMA2                             = 0xd,
 250         GRBM_GFX_INDEX_SDMA3                             = 0xe,
 251 } SYS_GRBM_GFX_INDEX_SEL;
 252 typedef enum SRBM_GFX_CNTL_SEL {
 253         SRBM_GFX_CNTL_BIF                                = 0x0,
 254         SRBM_GFX_CNTL_SDMA0                              = 0x1,
 255         SRBM_GFX_CNTL_SDMA1                              = 0x2,
 256         SRBM_GFX_CNTL_GRBM                               = 0x3,
 257         SRBM_GFX_CNTL_UVD                                = 0x4,
 258         SRBM_GFX_CNTL_VCE0                               = 0x5,
 259         SRBM_GFX_CNTL_VCE1                               = 0x6,
 260         SRBM_GFX_CNTL_ACP                                = 0x7,
 261         SRBM_GFX_CNTL_SMU                                = 0x8,
 262         SRBM_GFX_CNTL_SAMMSP                             = 0x9,
 263         SRBM_GFX_CNTL_SAMSCP                             = 0xa,
 264         SRBM_GFX_CNTL_ISP                                = 0xb,
 265         SRBM_GFX_CNTL_TST                                = 0xc,
 266         SRBM_GFX_CNTL_SDMA2                              = 0xd,
 267         SRBM_GFX_CNTL_SDMA3                              = 0xe,
 268 } SRBM_GFX_CNTL_SEL;
 269 typedef enum SDMA_PERF_SEL {
 270         SDMA_PERF_SEL_CYCLE                              = 0x0,
 271         SDMA_PERF_SEL_IDLE                               = 0x1,
 272         SDMA_PERF_SEL_REG_IDLE                           = 0x2,
 273         SDMA_PERF_SEL_RB_EMPTY                           = 0x3,
 274         SDMA_PERF_SEL_RB_FULL                            = 0x4,
 275         SDMA_PERF_SEL_RB_WPTR_WRAP                       = 0x5,
 276         SDMA_PERF_SEL_RB_RPTR_WRAP                       = 0x6,
 277         SDMA_PERF_SEL_RB_WPTR_POLL_READ                  = 0x7,
 278         SDMA_PERF_SEL_RB_RPTR_WB                         = 0x8,
 279         SDMA_PERF_SEL_RB_CMD_IDLE                        = 0x9,
 280         SDMA_PERF_SEL_RB_CMD_FULL                        = 0xa,
 281         SDMA_PERF_SEL_IB_CMD_IDLE                        = 0xb,
 282         SDMA_PERF_SEL_IB_CMD_FULL                        = 0xc,
 283         SDMA_PERF_SEL_EX_IDLE                            = 0xd,
 284         SDMA_PERF_SEL_SRBM_REG_SEND                      = 0xe,
 285         SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE          = 0xf,
 286         SDMA_PERF_SEL_MC_WR_IDLE                         = 0x10,
 287         SDMA_PERF_SEL_MC_WR_COUNT                        = 0x11,
 288         SDMA_PERF_SEL_MC_RD_IDLE                         = 0x12,
 289         SDMA_PERF_SEL_MC_RD_COUNT                        = 0x13,
 290         SDMA_PERF_SEL_MC_RD_RET_STALL                    = 0x14,
 291         SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE                 = 0x15,
 292         SDMA_PERF_SEL_SEM_IDLE                           = 0x18,
 293         SDMA_PERF_SEL_SEM_REQ_STALL                      = 0x19,
 294         SDMA_PERF_SEL_SEM_REQ_COUNT                      = 0x1a,
 295         SDMA_PERF_SEL_SEM_RESP_INCOMPLETE                = 0x1b,
 296         SDMA_PERF_SEL_SEM_RESP_FAIL                      = 0x1c,
 297         SDMA_PERF_SEL_SEM_RESP_PASS                      = 0x1d,
 298         SDMA_PERF_SEL_INT_IDLE                           = 0x1e,
 299         SDMA_PERF_SEL_INT_REQ_STALL                      = 0x1f,
 300         SDMA_PERF_SEL_INT_REQ_COUNT                      = 0x20,
 301         SDMA_PERF_SEL_INT_RESP_ACCEPTED                  = 0x21,
 302         SDMA_PERF_SEL_INT_RESP_RETRY                     = 0x22,
 303         SDMA_PERF_SEL_NUM_PACKET                         = 0x23,
 304         SDMA_PERF_SEL_CE_WREQ_IDLE                       = 0x25,
 305         SDMA_PERF_SEL_CE_WR_IDLE                         = 0x26,
 306         SDMA_PERF_SEL_CE_SPLIT_IDLE                      = 0x27,
 307         SDMA_PERF_SEL_CE_RREQ_IDLE                       = 0x28,
 308         SDMA_PERF_SEL_CE_OUT_IDLE                        = 0x29,
 309         SDMA_PERF_SEL_CE_IN_IDLE                         = 0x2a,
 310         SDMA_PERF_SEL_CE_DST_IDLE                        = 0x2b,
 311         SDMA_PERF_SEL_CE_AFIFO_FULL                      = 0x2e,
 312         SDMA_PERF_SEL_CE_INFO_FULL                       = 0x31,
 313         SDMA_PERF_SEL_CE_INFO1_FULL                      = 0x32,
 314         SDMA_PERF_SEL_CE_RD_STALL                        = 0x33,
 315         SDMA_PERF_SEL_CE_WR_STALL                        = 0x34,
 316         SDMA_PERF_SEL_GFX_SELECT                         = 0x35,
 317         SDMA_PERF_SEL_RLC0_SELECT                        = 0x36,
 318         SDMA_PERF_SEL_RLC1_SELECT                        = 0x37,
 319         SDMA_PERF_SEL_CTX_CHANGE                         = 0x38,
 320         SDMA_PERF_SEL_CTX_CHANGE_EXPIRED                 = 0x39,
 321         SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION               = 0x3a,
 322         SDMA_PERF_SEL_DOORBELL                           = 0x3b,
 323         SDMA_PERF_SEL_RD_BA_RTR                          = 0x3c,
 324         SDMA_PERF_SEL_WR_BA_RTR                          = 0x3d,
 325 } SDMA_PERF_SEL;
 326 typedef enum SurfaceEndian {
 327         ENDIAN_NONE                                      = 0x0,
 328         ENDIAN_8IN16                                     = 0x1,
 329         ENDIAN_8IN32                                     = 0x2,
 330         ENDIAN_8IN64                                     = 0x3,
 331 } SurfaceEndian;
 332 typedef enum ArrayMode {
 333         ARRAY_LINEAR_GENERAL                             = 0x0,
 334         ARRAY_LINEAR_ALIGNED                             = 0x1,
 335         ARRAY_1D_TILED_THIN1                             = 0x2,
 336         ARRAY_1D_TILED_THICK                             = 0x3,
 337         ARRAY_2D_TILED_THIN1                             = 0x4,
 338         ARRAY_PRT_TILED_THIN1                            = 0x5,
 339         ARRAY_PRT_2D_TILED_THIN1                         = 0x6,
 340         ARRAY_2D_TILED_THICK                             = 0x7,
 341         ARRAY_2D_TILED_XTHICK                            = 0x8,
 342         ARRAY_PRT_TILED_THICK                            = 0x9,
 343         ARRAY_PRT_2D_TILED_THICK                         = 0xa,
 344         ARRAY_PRT_3D_TILED_THIN1                         = 0xb,
 345         ARRAY_3D_TILED_THIN1                             = 0xc,
 346         ARRAY_3D_TILED_THICK                             = 0xd,
 347         ARRAY_3D_TILED_XTHICK                            = 0xe,
 348         ARRAY_PRT_3D_TILED_THICK                         = 0xf,
 349 } ArrayMode;
 350 typedef enum PipeTiling {
 351         CONFIG_1_PIPE                                    = 0x0,
 352         CONFIG_2_PIPE                                    = 0x1,
 353         CONFIG_4_PIPE                                    = 0x2,
 354         CONFIG_8_PIPE                                    = 0x3,
 355 } PipeTiling;
 356 typedef enum BankTiling {
 357         CONFIG_4_BANK                                    = 0x0,
 358         CONFIG_8_BANK                                    = 0x1,
 359 } BankTiling;
 360 typedef enum GroupInterleave {
 361         CONFIG_256B_GROUP                                = 0x0,
 362         CONFIG_512B_GROUP                                = 0x1,
 363 } GroupInterleave;
 364 typedef enum RowTiling {
 365         CONFIG_1KB_ROW                                   = 0x0,
 366         CONFIG_2KB_ROW                                   = 0x1,
 367         CONFIG_4KB_ROW                                   = 0x2,
 368         CONFIG_8KB_ROW                                   = 0x3,
 369         CONFIG_1KB_ROW_OPT                               = 0x4,
 370         CONFIG_2KB_ROW_OPT                               = 0x5,
 371         CONFIG_4KB_ROW_OPT                               = 0x6,
 372         CONFIG_8KB_ROW_OPT                               = 0x7,
 373 } RowTiling;
 374 typedef enum BankSwapBytes {
 375         CONFIG_128B_SWAPS                                = 0x0,
 376         CONFIG_256B_SWAPS                                = 0x1,
 377         CONFIG_512B_SWAPS                                = 0x2,
 378         CONFIG_1KB_SWAPS                                 = 0x3,
 379 } BankSwapBytes;
 380 typedef enum SampleSplitBytes {
 381         CONFIG_1KB_SPLIT                                 = 0x0,
 382         CONFIG_2KB_SPLIT                                 = 0x1,
 383         CONFIG_4KB_SPLIT                                 = 0x2,
 384         CONFIG_8KB_SPLIT                                 = 0x3,
 385 } SampleSplitBytes;
 386 typedef enum NumPipes {
 387         ADDR_CONFIG_1_PIPE                               = 0x0,
 388         ADDR_CONFIG_2_PIPE                               = 0x1,
 389         ADDR_CONFIG_4_PIPE                               = 0x2,
 390         ADDR_CONFIG_8_PIPE                               = 0x3,
 391 } NumPipes;
 392 typedef enum PipeInterleaveSize {
 393         ADDR_CONFIG_PIPE_INTERLEAVE_256B                 = 0x0,
 394         ADDR_CONFIG_PIPE_INTERLEAVE_512B                 = 0x1,
 395 } PipeInterleaveSize;
 396 typedef enum BankInterleaveSize {
 397         ADDR_CONFIG_BANK_INTERLEAVE_1                    = 0x0,
 398         ADDR_CONFIG_BANK_INTERLEAVE_2                    = 0x1,
 399         ADDR_CONFIG_BANK_INTERLEAVE_4                    = 0x2,
 400         ADDR_CONFIG_BANK_INTERLEAVE_8                    = 0x3,
 401 } BankInterleaveSize;
 402 typedef enum NumShaderEngines {
 403         ADDR_CONFIG_1_SHADER_ENGINE                      = 0x0,
 404         ADDR_CONFIG_2_SHADER_ENGINE                      = 0x1,
 405 } NumShaderEngines;
 406 typedef enum ShaderEngineTileSize {
 407         ADDR_CONFIG_SE_TILE_16                           = 0x0,
 408         ADDR_CONFIG_SE_TILE_32                           = 0x1,
 409 } ShaderEngineTileSize;
 410 typedef enum NumGPUs {
 411         ADDR_CONFIG_1_GPU                                = 0x0,
 412         ADDR_CONFIG_2_GPU                                = 0x1,
 413         ADDR_CONFIG_4_GPU                                = 0x2,
 414 } NumGPUs;
 415 typedef enum MultiGPUTileSize {
 416         ADDR_CONFIG_GPU_TILE_16                          = 0x0,
 417         ADDR_CONFIG_GPU_TILE_32                          = 0x1,
 418         ADDR_CONFIG_GPU_TILE_64                          = 0x2,
 419         ADDR_CONFIG_GPU_TILE_128                         = 0x3,
 420 } MultiGPUTileSize;
 421 typedef enum RowSize {
 422         ADDR_CONFIG_1KB_ROW                              = 0x0,
 423         ADDR_CONFIG_2KB_ROW                              = 0x1,
 424         ADDR_CONFIG_4KB_ROW                              = 0x2,
 425 } RowSize;
 426 typedef enum NumLowerPipes {
 427         ADDR_CONFIG_1_LOWER_PIPES                        = 0x0,
 428         ADDR_CONFIG_2_LOWER_PIPES                        = 0x1,
 429 } NumLowerPipes;
 430 typedef enum DebugBlockId {
 431         DBG_CLIENT_BLKID_RESERVED                        = 0x0,
 432         DBG_CLIENT_BLKID_dbg                             = 0x1,
 433         DBG_CLIENT_BLKID_scf2                            = 0x2,
 434         DBG_CLIENT_BLKID_mcd5                            = 0x3,
 435         DBG_CLIENT_BLKID_vmc                             = 0x4,
 436         DBG_CLIENT_BLKID_sx30                            = 0x5,
 437         DBG_CLIENT_BLKID_mcd2                            = 0x6,
 438         DBG_CLIENT_BLKID_bci1                            = 0x7,
 439         DBG_CLIENT_BLKID_xdma_dbg_client_wrapper         = 0x8,
 440         DBG_CLIENT_BLKID_mcc0                            = 0x9,
 441         DBG_CLIENT_BLKID_uvdf_0                          = 0xa,
 442         DBG_CLIENT_BLKID_uvdf_1                          = 0xb,
 443         DBG_CLIENT_BLKID_uvdf_2                          = 0xc,
 444         DBG_CLIENT_BLKID_uvdi_0                          = 0xd,
 445         DBG_CLIENT_BLKID_bci0                            = 0xe,
 446         DBG_CLIENT_BLKID_vcec0_0                         = 0xf,
 447         DBG_CLIENT_BLKID_cb100                           = 0x10,
 448         DBG_CLIENT_BLKID_cb001                           = 0x11,
 449         DBG_CLIENT_BLKID_mcd4                            = 0x12,
 450         DBG_CLIENT_BLKID_tmonw00                         = 0x13,
 451         DBG_CLIENT_BLKID_cb101                           = 0x14,
 452         DBG_CLIENT_BLKID_sx10                            = 0x15,
 453         DBG_CLIENT_BLKID_cb301                           = 0x16,
 454         DBG_CLIENT_BLKID_tmonw01                         = 0x17,
 455         DBG_CLIENT_BLKID_vcea0_0                         = 0x18,
 456         DBG_CLIENT_BLKID_vcea0_1                         = 0x19,
 457         DBG_CLIENT_BLKID_vcea0_2                         = 0x1a,
 458         DBG_CLIENT_BLKID_vcea0_3                         = 0x1b,
 459         DBG_CLIENT_BLKID_scf1                            = 0x1c,
 460         DBG_CLIENT_BLKID_sx20                            = 0x1d,
 461         DBG_CLIENT_BLKID_spim1                           = 0x1e,
 462         DBG_CLIENT_BLKID_pa10                            = 0x1f,
 463         DBG_CLIENT_BLKID_pa00                            = 0x20,
 464         DBG_CLIENT_BLKID_gmcon                           = 0x21,
 465         DBG_CLIENT_BLKID_mcb                             = 0x22,
 466         DBG_CLIENT_BLKID_vgt0                            = 0x23,
 467         DBG_CLIENT_BLKID_pc0                             = 0x24,
 468         DBG_CLIENT_BLKID_bci2                            = 0x25,
 469         DBG_CLIENT_BLKID_uvdb_0                          = 0x26,
 470         DBG_CLIENT_BLKID_spim3                           = 0x27,
 471         DBG_CLIENT_BLKID_cpc_0                           = 0x28,
 472         DBG_CLIENT_BLKID_cpc_1                           = 0x29,
 473         DBG_CLIENT_BLKID_uvdm_0                          = 0x2a,
 474         DBG_CLIENT_BLKID_uvdm_1                          = 0x2b,
 475         DBG_CLIENT_BLKID_uvdm_2                          = 0x2c,
 476         DBG_CLIENT_BLKID_uvdm_3                          = 0x2d,
 477         DBG_CLIENT_BLKID_cb000                           = 0x2e,
 478         DBG_CLIENT_BLKID_spim0                           = 0x2f,
 479         DBG_CLIENT_BLKID_mcc2                            = 0x30,
 480         DBG_CLIENT_BLKID_ds0                             = 0x31,
 481         DBG_CLIENT_BLKID_srbm                            = 0x32,
 482         DBG_CLIENT_BLKID_ih                              = 0x33,
 483         DBG_CLIENT_BLKID_sem                             = 0x34,
 484         DBG_CLIENT_BLKID_sdma_0                          = 0x35,
 485         DBG_CLIENT_BLKID_sdma_1                          = 0x36,
 486         DBG_CLIENT_BLKID_hdp                             = 0x37,
 487         DBG_CLIENT_BLKID_acp_0                           = 0x38,
 488         DBG_CLIENT_BLKID_acp_1                           = 0x39,
 489         DBG_CLIENT_BLKID_cb200                           = 0x3a,
 490         DBG_CLIENT_BLKID_scf3                            = 0x3b,
 491         DBG_CLIENT_BLKID_vceb1_0                         = 0x3c,
 492         DBG_CLIENT_BLKID_vcea1_0                         = 0x3d,
 493         DBG_CLIENT_BLKID_vcea1_1                         = 0x3e,
 494         DBG_CLIENT_BLKID_vcea1_2                         = 0x3f,
 495         DBG_CLIENT_BLKID_vcea1_3                         = 0x40,
 496         DBG_CLIENT_BLKID_bci3                            = 0x41,
 497         DBG_CLIENT_BLKID_mcd0                            = 0x42,
 498         DBG_CLIENT_BLKID_pa11                            = 0x43,
 499         DBG_CLIENT_BLKID_pa01                            = 0x44,
 500         DBG_CLIENT_BLKID_cb201                           = 0x45,
 501         DBG_CLIENT_BLKID_spim2                           = 0x46,
 502         DBG_CLIENT_BLKID_vgt2                            = 0x47,
 503         DBG_CLIENT_BLKID_pc2                             = 0x48,
 504         DBG_CLIENT_BLKID_smu_0                           = 0x49,
 505         DBG_CLIENT_BLKID_smu_1                           = 0x4a,
 506         DBG_CLIENT_BLKID_smu_2                           = 0x4b,
 507         DBG_CLIENT_BLKID_cb1                             = 0x4c,
 508         DBG_CLIENT_BLKID_ia0                             = 0x4d,
 509         DBG_CLIENT_BLKID_wd                              = 0x4e,
 510         DBG_CLIENT_BLKID_ia1                             = 0x4f,
 511         DBG_CLIENT_BLKID_vcec1_0                         = 0x50,
 512         DBG_CLIENT_BLKID_scf0                            = 0x51,
 513         DBG_CLIENT_BLKID_vgt1                            = 0x52,
 514         DBG_CLIENT_BLKID_pc1                             = 0x53,
 515         DBG_CLIENT_BLKID_cb0                             = 0x54,
 516         DBG_CLIENT_BLKID_gdc_one_0                       = 0x55,
 517         DBG_CLIENT_BLKID_gdc_one_1                       = 0x56,
 518         DBG_CLIENT_BLKID_gdc_one_2                       = 0x57,
 519         DBG_CLIENT_BLKID_gdc_one_3                       = 0x58,
 520         DBG_CLIENT_BLKID_gdc_one_4                       = 0x59,
 521         DBG_CLIENT_BLKID_gdc_one_5                       = 0x5a,
 522         DBG_CLIENT_BLKID_gdc_one_6                       = 0x5b,
 523         DBG_CLIENT_BLKID_gdc_one_7                       = 0x5c,
 524         DBG_CLIENT_BLKID_gdc_one_8                       = 0x5d,
 525         DBG_CLIENT_BLKID_gdc_one_9                       = 0x5e,
 526         DBG_CLIENT_BLKID_gdc_one_10                      = 0x5f,
 527         DBG_CLIENT_BLKID_gdc_one_11                      = 0x60,
 528         DBG_CLIENT_BLKID_gdc_one_12                      = 0x61,
 529         DBG_CLIENT_BLKID_gdc_one_13                      = 0x62,
 530         DBG_CLIENT_BLKID_gdc_one_14                      = 0x63,
 531         DBG_CLIENT_BLKID_gdc_one_15                      = 0x64,
 532         DBG_CLIENT_BLKID_gdc_one_16                      = 0x65,
 533         DBG_CLIENT_BLKID_gdc_one_17                      = 0x66,
 534         DBG_CLIENT_BLKID_gdc_one_18                      = 0x67,
 535         DBG_CLIENT_BLKID_gdc_one_19                      = 0x68,
 536         DBG_CLIENT_BLKID_gdc_one_20                      = 0x69,
 537         DBG_CLIENT_BLKID_gdc_one_21                      = 0x6a,
 538         DBG_CLIENT_BLKID_gdc_one_22                      = 0x6b,
 539         DBG_CLIENT_BLKID_gdc_one_23                      = 0x6c,
 540         DBG_CLIENT_BLKID_gdc_one_24                      = 0x6d,
 541         DBG_CLIENT_BLKID_gdc_one_25                      = 0x6e,
 542         DBG_CLIENT_BLKID_gdc_one_26                      = 0x6f,
 543         DBG_CLIENT_BLKID_gdc_one_27                      = 0x70,
 544         DBG_CLIENT_BLKID_gdc_one_28                      = 0x71,
 545         DBG_CLIENT_BLKID_gdc_one_29                      = 0x72,
 546         DBG_CLIENT_BLKID_gdc_one_30                      = 0x73,
 547         DBG_CLIENT_BLKID_gdc_one_31                      = 0x74,
 548         DBG_CLIENT_BLKID_gdc_one_32                      = 0x75,
 549         DBG_CLIENT_BLKID_gdc_one_33                      = 0x76,
 550         DBG_CLIENT_BLKID_gdc_one_34                      = 0x77,
 551         DBG_CLIENT_BLKID_gdc_one_35                      = 0x78,
 552         DBG_CLIENT_BLKID_vceb0_0                         = 0x79,
 553         DBG_CLIENT_BLKID_vgt3                            = 0x7a,
 554         DBG_CLIENT_BLKID_pc3                             = 0x7b,
 555         DBG_CLIENT_BLKID_mcd3                            = 0x7c,
 556         DBG_CLIENT_BLKID_uvdu_0                          = 0x7d,
 557         DBG_CLIENT_BLKID_uvdu_1                          = 0x7e,
 558         DBG_CLIENT_BLKID_uvdu_2                          = 0x7f,
 559         DBG_CLIENT_BLKID_uvdu_3                          = 0x80,
 560         DBG_CLIENT_BLKID_uvdu_4                          = 0x81,
 561         DBG_CLIENT_BLKID_uvdu_5                          = 0x82,
 562         DBG_CLIENT_BLKID_uvdu_6                          = 0x83,
 563         DBG_CLIENT_BLKID_cb300                           = 0x84,
 564         DBG_CLIENT_BLKID_mcd1                            = 0x85,
 565         DBG_CLIENT_BLKID_sx00                            = 0x86,
 566         DBG_CLIENT_BLKID_uvdc_0                          = 0x87,
 567         DBG_CLIENT_BLKID_uvdc_1                          = 0x88,
 568         DBG_CLIENT_BLKID_mcc3                            = 0x89,
 569         DBG_CLIENT_BLKID_cpg_0                           = 0x8a,
 570         DBG_CLIENT_BLKID_cpg_1                           = 0x8b,
 571         DBG_CLIENT_BLKID_gck                             = 0x8c,
 572         DBG_CLIENT_BLKID_mcc1                            = 0x8d,
 573         DBG_CLIENT_BLKID_cpf_0                           = 0x8e,
 574         DBG_CLIENT_BLKID_cpf_1                           = 0x8f,
 575         DBG_CLIENT_BLKID_rlc                             = 0x90,
 576         DBG_CLIENT_BLKID_grbm                            = 0x91,
 577         DBG_CLIENT_BLKID_sammsp                          = 0x92,
 578         DBG_CLIENT_BLKID_dci_pg                          = 0x93,
 579         DBG_CLIENT_BLKID_dci_0                           = 0x94,
 580         DBG_CLIENT_BLKID_dccg0_0                         = 0x95,
 581         DBG_CLIENT_BLKID_dccg0_1                         = 0x96,
 582         DBG_CLIENT_BLKID_dcfe01_0                        = 0x97,
 583         DBG_CLIENT_BLKID_dcfe02_0                        = 0x98,
 584         DBG_CLIENT_BLKID_dcfe03_0                        = 0x99,
 585         DBG_CLIENT_BLKID_dcfe04_0                        = 0x9a,
 586         DBG_CLIENT_BLKID_dcfe05_0                        = 0x9b,
 587         DBG_CLIENT_BLKID_dcfe06_0                        = 0x9c,
 588         DBG_CLIENT_BLKID_RESERVED_LAST                   = 0x9d,
 589 } DebugBlockId;
 590 typedef enum DebugBlockId_OLD {
 591         DBG_BLOCK_ID_RESERVED                            = 0x0,
 592         DBG_BLOCK_ID_DBG                                 = 0x1,
 593         DBG_BLOCK_ID_VMC                                 = 0x2,
 594         DBG_BLOCK_ID_PDMA                                = 0x3,
 595         DBG_BLOCK_ID_CG                                  = 0x4,
 596         DBG_BLOCK_ID_SRBM                                = 0x5,
 597         DBG_BLOCK_ID_GRBM                                = 0x6,
 598         DBG_BLOCK_ID_RLC                                 = 0x7,
 599         DBG_BLOCK_ID_CSC                                 = 0x8,
 600         DBG_BLOCK_ID_SEM                                 = 0x9,
 601         DBG_BLOCK_ID_IH                                  = 0xa,
 602         DBG_BLOCK_ID_SC                                  = 0xb,
 603         DBG_BLOCK_ID_SQ                                  = 0xc,
 604         DBG_BLOCK_ID_AVP                                 = 0xd,
 605         DBG_BLOCK_ID_GMCON                               = 0xe,
 606         DBG_BLOCK_ID_SMU                                 = 0xf,
 607         DBG_BLOCK_ID_DMA0                                = 0x10,
 608         DBG_BLOCK_ID_DMA1                                = 0x11,
 609         DBG_BLOCK_ID_SPIM                                = 0x12,
 610         DBG_BLOCK_ID_GDS                                 = 0x13,
 611         DBG_BLOCK_ID_SPIS                                = 0x14,
 612         DBG_BLOCK_ID_UNUSED0                             = 0x15,
 613         DBG_BLOCK_ID_PA0                                 = 0x16,
 614         DBG_BLOCK_ID_PA1                                 = 0x17,
 615         DBG_BLOCK_ID_CP0                                 = 0x18,
 616         DBG_BLOCK_ID_CP1                                 = 0x19,
 617         DBG_BLOCK_ID_CP2                                 = 0x1a,
 618         DBG_BLOCK_ID_UNUSED1                             = 0x1b,
 619         DBG_BLOCK_ID_UVDU                                = 0x1c,
 620         DBG_BLOCK_ID_UVDM                                = 0x1d,
 621         DBG_BLOCK_ID_VCE                                 = 0x1e,
 622         DBG_BLOCK_ID_UNUSED2                             = 0x1f,
 623         DBG_BLOCK_ID_VGT0                                = 0x20,
 624         DBG_BLOCK_ID_VGT1                                = 0x21,
 625         DBG_BLOCK_ID_IA                                  = 0x22,
 626         DBG_BLOCK_ID_UNUSED3                             = 0x23,
 627         DBG_BLOCK_ID_SCT0                                = 0x24,
 628         DBG_BLOCK_ID_SCT1                                = 0x25,
 629         DBG_BLOCK_ID_SPM0                                = 0x26,
 630         DBG_BLOCK_ID_SPM1                                = 0x27,
 631         DBG_BLOCK_ID_TCAA                                = 0x28,
 632         DBG_BLOCK_ID_TCAB                                = 0x29,
 633         DBG_BLOCK_ID_TCCA                                = 0x2a,
 634         DBG_BLOCK_ID_TCCB                                = 0x2b,
 635         DBG_BLOCK_ID_MCC0                                = 0x2c,
 636         DBG_BLOCK_ID_MCC1                                = 0x2d,
 637         DBG_BLOCK_ID_MCC2                                = 0x2e,
 638         DBG_BLOCK_ID_MCC3                                = 0x2f,
 639         DBG_BLOCK_ID_SX0                                 = 0x30,
 640         DBG_BLOCK_ID_SX1                                 = 0x31,
 641         DBG_BLOCK_ID_SX2                                 = 0x32,
 642         DBG_BLOCK_ID_SX3                                 = 0x33,
 643         DBG_BLOCK_ID_UNUSED4                             = 0x34,
 644         DBG_BLOCK_ID_UNUSED5                             = 0x35,
 645         DBG_BLOCK_ID_UNUSED6                             = 0x36,
 646         DBG_BLOCK_ID_UNUSED7                             = 0x37,
 647         DBG_BLOCK_ID_PC0                                 = 0x38,
 648         DBG_BLOCK_ID_PC1                                 = 0x39,
 649         DBG_BLOCK_ID_UNUSED8                             = 0x3a,
 650         DBG_BLOCK_ID_UNUSED9                             = 0x3b,
 651         DBG_BLOCK_ID_UNUSED10                            = 0x3c,
 652         DBG_BLOCK_ID_UNUSED11                            = 0x3d,
 653         DBG_BLOCK_ID_MCB                                 = 0x3e,
 654         DBG_BLOCK_ID_UNUSED12                            = 0x3f,
 655         DBG_BLOCK_ID_SCB0                                = 0x40,
 656         DBG_BLOCK_ID_SCB1                                = 0x41,
 657         DBG_BLOCK_ID_UNUSED13                            = 0x42,
 658         DBG_BLOCK_ID_UNUSED14                            = 0x43,
 659         DBG_BLOCK_ID_SCF0                                = 0x44,
 660         DBG_BLOCK_ID_SCF1                                = 0x45,
 661         DBG_BLOCK_ID_UNUSED15                            = 0x46,
 662         DBG_BLOCK_ID_UNUSED16                            = 0x47,
 663         DBG_BLOCK_ID_BCI0                                = 0x48,
 664         DBG_BLOCK_ID_BCI1                                = 0x49,
 665         DBG_BLOCK_ID_BCI2                                = 0x4a,
 666         DBG_BLOCK_ID_BCI3                                = 0x4b,
 667         DBG_BLOCK_ID_UNUSED17                            = 0x4c,
 668         DBG_BLOCK_ID_UNUSED18                            = 0x4d,
 669         DBG_BLOCK_ID_UNUSED19                            = 0x4e,
 670         DBG_BLOCK_ID_UNUSED20                            = 0x4f,
 671         DBG_BLOCK_ID_CB00                                = 0x50,
 672         DBG_BLOCK_ID_CB01                                = 0x51,
 673         DBG_BLOCK_ID_CB02                                = 0x52,
 674         DBG_BLOCK_ID_CB03                                = 0x53,
 675         DBG_BLOCK_ID_CB04                                = 0x54,
 676         DBG_BLOCK_ID_UNUSED21                            = 0x55,
 677         DBG_BLOCK_ID_UNUSED22                            = 0x56,
 678         DBG_BLOCK_ID_UNUSED23                            = 0x57,
 679         DBG_BLOCK_ID_CB10                                = 0x58,
 680         DBG_BLOCK_ID_CB11                                = 0x59,
 681         DBG_BLOCK_ID_CB12                                = 0x5a,
 682         DBG_BLOCK_ID_CB13                                = 0x5b,
 683         DBG_BLOCK_ID_CB14                                = 0x5c,
 684         DBG_BLOCK_ID_UNUSED24                            = 0x5d,
 685         DBG_BLOCK_ID_UNUSED25                            = 0x5e,
 686         DBG_BLOCK_ID_UNUSED26                            = 0x5f,
 687         DBG_BLOCK_ID_TCP0                                = 0x60,
 688         DBG_BLOCK_ID_TCP1                                = 0x61,
 689         DBG_BLOCK_ID_TCP2                                = 0x62,
 690         DBG_BLOCK_ID_TCP3                                = 0x63,
 691         DBG_BLOCK_ID_TCP4                                = 0x64,
 692         DBG_BLOCK_ID_TCP5                                = 0x65,
 693         DBG_BLOCK_ID_TCP6                                = 0x66,
 694         DBG_BLOCK_ID_TCP7                                = 0x67,
 695         DBG_BLOCK_ID_TCP8                                = 0x68,
 696         DBG_BLOCK_ID_TCP9                                = 0x69,
 697         DBG_BLOCK_ID_TCP10                               = 0x6a,
 698         DBG_BLOCK_ID_TCP11                               = 0x6b,
 699         DBG_BLOCK_ID_TCP12                               = 0x6c,
 700         DBG_BLOCK_ID_TCP13                               = 0x6d,
 701         DBG_BLOCK_ID_TCP14                               = 0x6e,
 702         DBG_BLOCK_ID_TCP15                               = 0x6f,
 703         DBG_BLOCK_ID_TCP16                               = 0x70,
 704         DBG_BLOCK_ID_TCP17                               = 0x71,
 705         DBG_BLOCK_ID_TCP18                               = 0x72,
 706         DBG_BLOCK_ID_TCP19                               = 0x73,
 707         DBG_BLOCK_ID_TCP20                               = 0x74,
 708         DBG_BLOCK_ID_TCP21                               = 0x75,
 709         DBG_BLOCK_ID_TCP22                               = 0x76,
 710         DBG_BLOCK_ID_TCP23                               = 0x77,
 711         DBG_BLOCK_ID_TCP_RESERVED0                       = 0x78,
 712         DBG_BLOCK_ID_TCP_RESERVED1                       = 0x79,
 713         DBG_BLOCK_ID_TCP_RESERVED2                       = 0x7a,
 714         DBG_BLOCK_ID_TCP_RESERVED3                       = 0x7b,
 715         DBG_BLOCK_ID_TCP_RESERVED4                       = 0x7c,
 716         DBG_BLOCK_ID_TCP_RESERVED5                       = 0x7d,
 717         DBG_BLOCK_ID_TCP_RESERVED6                       = 0x7e,
 718         DBG_BLOCK_ID_TCP_RESERVED7                       = 0x7f,
 719         DBG_BLOCK_ID_DB00                                = 0x80,
 720         DBG_BLOCK_ID_DB01                                = 0x81,
 721         DBG_BLOCK_ID_DB02                                = 0x82,
 722         DBG_BLOCK_ID_DB03                                = 0x83,
 723         DBG_BLOCK_ID_DB04                                = 0x84,
 724         DBG_BLOCK_ID_UNUSED27                            = 0x85,
 725         DBG_BLOCK_ID_UNUSED28                            = 0x86,
 726         DBG_BLOCK_ID_UNUSED29                            = 0x87,
 727         DBG_BLOCK_ID_DB10                                = 0x88,
 728         DBG_BLOCK_ID_DB11                                = 0x89,
 729         DBG_BLOCK_ID_DB12                                = 0x8a,
 730         DBG_BLOCK_ID_DB13                                = 0x8b,
 731         DBG_BLOCK_ID_DB14                                = 0x8c,
 732         DBG_BLOCK_ID_UNUSED30                            = 0x8d,
 733         DBG_BLOCK_ID_UNUSED31                            = 0x8e,
 734         DBG_BLOCK_ID_UNUSED32                            = 0x8f,
 735         DBG_BLOCK_ID_TCC0                                = 0x90,
 736         DBG_BLOCK_ID_TCC1                                = 0x91,
 737         DBG_BLOCK_ID_TCC2                                = 0x92,
 738         DBG_BLOCK_ID_TCC3                                = 0x93,
 739         DBG_BLOCK_ID_TCC4                                = 0x94,
 740         DBG_BLOCK_ID_TCC5                                = 0x95,
 741         DBG_BLOCK_ID_TCC6                                = 0x96,
 742         DBG_BLOCK_ID_TCC7                                = 0x97,
 743         DBG_BLOCK_ID_SPS00                               = 0x98,
 744         DBG_BLOCK_ID_SPS01                               = 0x99,
 745         DBG_BLOCK_ID_SPS02                               = 0x9a,
 746         DBG_BLOCK_ID_SPS10                               = 0x9b,
 747         DBG_BLOCK_ID_SPS11                               = 0x9c,
 748         DBG_BLOCK_ID_SPS12                               = 0x9d,
 749         DBG_BLOCK_ID_UNUSED33                            = 0x9e,
 750         DBG_BLOCK_ID_UNUSED34                            = 0x9f,
 751         DBG_BLOCK_ID_TA00                                = 0xa0,
 752         DBG_BLOCK_ID_TA01                                = 0xa1,
 753         DBG_BLOCK_ID_TA02                                = 0xa2,
 754         DBG_BLOCK_ID_TA03                                = 0xa3,
 755         DBG_BLOCK_ID_TA04                                = 0xa4,
 756         DBG_BLOCK_ID_TA05                                = 0xa5,
 757         DBG_BLOCK_ID_TA06                                = 0xa6,
 758         DBG_BLOCK_ID_TA07                                = 0xa7,
 759         DBG_BLOCK_ID_TA08                                = 0xa8,
 760         DBG_BLOCK_ID_TA09                                = 0xa9,
 761         DBG_BLOCK_ID_TA0A                                = 0xaa,
 762         DBG_BLOCK_ID_TA0B                                = 0xab,
 763         DBG_BLOCK_ID_UNUSED35                            = 0xac,
 764         DBG_BLOCK_ID_UNUSED36                            = 0xad,
 765         DBG_BLOCK_ID_UNUSED37                            = 0xae,
 766         DBG_BLOCK_ID_UNUSED38                            = 0xaf,
 767         DBG_BLOCK_ID_TA10                                = 0xb0,
 768         DBG_BLOCK_ID_TA11                                = 0xb1,
 769         DBG_BLOCK_ID_TA12                                = 0xb2,
 770         DBG_BLOCK_ID_TA13                                = 0xb3,
 771         DBG_BLOCK_ID_TA14                                = 0xb4,
 772         DBG_BLOCK_ID_TA15                                = 0xb5,
 773         DBG_BLOCK_ID_TA16                                = 0xb6,
 774         DBG_BLOCK_ID_TA17                                = 0xb7,
 775         DBG_BLOCK_ID_TA18                                = 0xb8,
 776         DBG_BLOCK_ID_TA19                                = 0xb9,
 777         DBG_BLOCK_ID_TA1A                                = 0xba,
 778         DBG_BLOCK_ID_TA1B                                = 0xbb,
 779         DBG_BLOCK_ID_UNUSED39                            = 0xbc,
 780         DBG_BLOCK_ID_UNUSED40                            = 0xbd,
 781         DBG_BLOCK_ID_UNUSED41                            = 0xbe,
 782         DBG_BLOCK_ID_UNUSED42                            = 0xbf,
 783         DBG_BLOCK_ID_TD00                                = 0xc0,
 784         DBG_BLOCK_ID_TD01                                = 0xc1,
 785         DBG_BLOCK_ID_TD02                                = 0xc2,
 786         DBG_BLOCK_ID_TD03                                = 0xc3,
 787         DBG_BLOCK_ID_TD04                                = 0xc4,
 788         DBG_BLOCK_ID_TD05                                = 0xc5,
 789         DBG_BLOCK_ID_TD06                                = 0xc6,
 790         DBG_BLOCK_ID_TD07                                = 0xc7,
 791         DBG_BLOCK_ID_TD08                                = 0xc8,
 792         DBG_BLOCK_ID_TD09                                = 0xc9,
 793         DBG_BLOCK_ID_TD0A                                = 0xca,
 794         DBG_BLOCK_ID_TD0B                                = 0xcb,
 795         DBG_BLOCK_ID_UNUSED43                            = 0xcc,
 796         DBG_BLOCK_ID_UNUSED44                            = 0xcd,
 797         DBG_BLOCK_ID_UNUSED45                            = 0xce,
 798         DBG_BLOCK_ID_UNUSED46                            = 0xcf,
 799         DBG_BLOCK_ID_TD10                                = 0xd0,
 800         DBG_BLOCK_ID_TD11                                = 0xd1,
 801         DBG_BLOCK_ID_TD12                                = 0xd2,
 802         DBG_BLOCK_ID_TD13                                = 0xd3,
 803         DBG_BLOCK_ID_TD14                                = 0xd4,
 804         DBG_BLOCK_ID_TD15                                = 0xd5,
 805         DBG_BLOCK_ID_TD16                                = 0xd6,
 806         DBG_BLOCK_ID_TD17                                = 0xd7,
 807         DBG_BLOCK_ID_TD18                                = 0xd8,
 808         DBG_BLOCK_ID_TD19                                = 0xd9,
 809         DBG_BLOCK_ID_TD1A                                = 0xda,
 810         DBG_BLOCK_ID_TD1B                                = 0xdb,
 811         DBG_BLOCK_ID_UNUSED47                            = 0xdc,
 812         DBG_BLOCK_ID_UNUSED48                            = 0xdd,
 813         DBG_BLOCK_ID_UNUSED49                            = 0xde,
 814         DBG_BLOCK_ID_UNUSED50                            = 0xdf,
 815         DBG_BLOCK_ID_MCD0                                = 0xe0,
 816         DBG_BLOCK_ID_MCD1                                = 0xe1,
 817         DBG_BLOCK_ID_MCD2                                = 0xe2,
 818         DBG_BLOCK_ID_MCD3                                = 0xe3,
 819         DBG_BLOCK_ID_MCD4                                = 0xe4,
 820         DBG_BLOCK_ID_MCD5                                = 0xe5,
 821         DBG_BLOCK_ID_UNUSED51                            = 0xe6,
 822         DBG_BLOCK_ID_UNUSED52                            = 0xe7,
 823 } DebugBlockId_OLD;
 824 typedef enum DebugBlockId_BY2 {
 825         DBG_BLOCK_ID_RESERVED_BY2                        = 0x0,
 826         DBG_BLOCK_ID_VMC_BY2                             = 0x1,
 827         DBG_BLOCK_ID_CG_BY2                              = 0x2,
 828         DBG_BLOCK_ID_GRBM_BY2                            = 0x3,
 829         DBG_BLOCK_ID_CSC_BY2                             = 0x4,
 830         DBG_BLOCK_ID_IH_BY2                              = 0x5,
 831         DBG_BLOCK_ID_SQ_BY2                              = 0x6,
 832         DBG_BLOCK_ID_GMCON_BY2                           = 0x7,
 833         DBG_BLOCK_ID_DMA0_BY2                            = 0x8,
 834         DBG_BLOCK_ID_SPIM_BY2                            = 0x9,
 835         DBG_BLOCK_ID_SPIS_BY2                            = 0xa,
 836         DBG_BLOCK_ID_PA0_BY2                             = 0xb,
 837         DBG_BLOCK_ID_CP0_BY2                             = 0xc,
 838         DBG_BLOCK_ID_CP2_BY2                             = 0xd,
 839         DBG_BLOCK_ID_UVDU_BY2                            = 0xe,
 840         DBG_BLOCK_ID_VCE_BY2                             = 0xf,
 841         DBG_BLOCK_ID_VGT0_BY2                            = 0x10,
 842         DBG_BLOCK_ID_IA_BY2                              = 0x11,
 843         DBG_BLOCK_ID_SCT0_BY2                            = 0x12,
 844         DBG_BLOCK_ID_SPM0_BY2                            = 0x13,
 845         DBG_BLOCK_ID_TCAA_BY2                            = 0x14,
 846         DBG_BLOCK_ID_TCCA_BY2                            = 0x15,
 847         DBG_BLOCK_ID_MCC0_BY2                            = 0x16,
 848         DBG_BLOCK_ID_MCC2_BY2                            = 0x17,
 849         DBG_BLOCK_ID_SX0_BY2                             = 0x18,
 850         DBG_BLOCK_ID_SX2_BY2                             = 0x19,
 851         DBG_BLOCK_ID_UNUSED4_BY2                         = 0x1a,
 852         DBG_BLOCK_ID_UNUSED6_BY2                         = 0x1b,
 853         DBG_BLOCK_ID_PC0_BY2                             = 0x1c,
 854         DBG_BLOCK_ID_UNUSED8_BY2                         = 0x1d,
 855         DBG_BLOCK_ID_UNUSED10_BY2                        = 0x1e,
 856         DBG_BLOCK_ID_MCB_BY2                             = 0x1f,
 857         DBG_BLOCK_ID_SCB0_BY2                            = 0x20,
 858         DBG_BLOCK_ID_UNUSED13_BY2                        = 0x21,
 859         DBG_BLOCK_ID_SCF0_BY2                            = 0x22,
 860         DBG_BLOCK_ID_UNUSED15_BY2                        = 0x23,
 861         DBG_BLOCK_ID_BCI0_BY2                            = 0x24,
 862         DBG_BLOCK_ID_BCI2_BY2                            = 0x25,
 863         DBG_BLOCK_ID_UNUSED17_BY2                        = 0x26,
 864         DBG_BLOCK_ID_UNUSED19_BY2                        = 0x27,
 865         DBG_BLOCK_ID_CB00_BY2                            = 0x28,
 866         DBG_BLOCK_ID_CB02_BY2                            = 0x29,
 867         DBG_BLOCK_ID_CB04_BY2                            = 0x2a,
 868         DBG_BLOCK_ID_UNUSED22_BY2                        = 0x2b,
 869         DBG_BLOCK_ID_CB10_BY2                            = 0x2c,
 870         DBG_BLOCK_ID_CB12_BY2                            = 0x2d,
 871         DBG_BLOCK_ID_CB14_BY2                            = 0x2e,
 872         DBG_BLOCK_ID_UNUSED25_BY2                        = 0x2f,
 873         DBG_BLOCK_ID_TCP0_BY2                            = 0x30,
 874         DBG_BLOCK_ID_TCP2_BY2                            = 0x31,
 875         DBG_BLOCK_ID_TCP4_BY2                            = 0x32,
 876         DBG_BLOCK_ID_TCP6_BY2                            = 0x33,
 877         DBG_BLOCK_ID_TCP8_BY2                            = 0x34,
 878         DBG_BLOCK_ID_TCP10_BY2                           = 0x35,
 879         DBG_BLOCK_ID_TCP12_BY2                           = 0x36,
 880         DBG_BLOCK_ID_TCP14_BY2                           = 0x37,
 881         DBG_BLOCK_ID_TCP16_BY2                           = 0x38,
 882         DBG_BLOCK_ID_TCP18_BY2                           = 0x39,
 883         DBG_BLOCK_ID_TCP20_BY2                           = 0x3a,
 884         DBG_BLOCK_ID_TCP22_BY2                           = 0x3b,
 885         DBG_BLOCK_ID_TCP_RESERVED0_BY2                   = 0x3c,
 886         DBG_BLOCK_ID_TCP_RESERVED2_BY2                   = 0x3d,
 887         DBG_BLOCK_ID_TCP_RESERVED4_BY2                   = 0x3e,
 888         DBG_BLOCK_ID_TCP_RESERVED6_BY2                   = 0x3f,
 889         DBG_BLOCK_ID_DB00_BY2                            = 0x40,
 890         DBG_BLOCK_ID_DB02_BY2                            = 0x41,
 891         DBG_BLOCK_ID_DB04_BY2                            = 0x42,
 892         DBG_BLOCK_ID_UNUSED28_BY2                        = 0x43,
 893         DBG_BLOCK_ID_DB10_BY2                            = 0x44,
 894         DBG_BLOCK_ID_DB12_BY2                            = 0x45,
 895         DBG_BLOCK_ID_DB14_BY2                            = 0x46,
 896         DBG_BLOCK_ID_UNUSED31_BY2                        = 0x47,
 897         DBG_BLOCK_ID_TCC0_BY2                            = 0x48,
 898         DBG_BLOCK_ID_TCC2_BY2                            = 0x49,
 899         DBG_BLOCK_ID_TCC4_BY2                            = 0x4a,
 900         DBG_BLOCK_ID_TCC6_BY2                            = 0x4b,
 901         DBG_BLOCK_ID_SPS00_BY2                           = 0x4c,
 902         DBG_BLOCK_ID_SPS02_BY2                           = 0x4d,
 903         DBG_BLOCK_ID_SPS11_BY2                           = 0x4e,
 904         DBG_BLOCK_ID_UNUSED33_BY2                        = 0x4f,
 905         DBG_BLOCK_ID_TA00_BY2                            = 0x50,
 906         DBG_BLOCK_ID_TA02_BY2                            = 0x51,
 907         DBG_BLOCK_ID_TA04_BY2                            = 0x52,
 908         DBG_BLOCK_ID_TA06_BY2                            = 0x53,
 909         DBG_BLOCK_ID_TA08_BY2                            = 0x54,
 910         DBG_BLOCK_ID_TA0A_BY2                            = 0x55,
 911         DBG_BLOCK_ID_UNUSED35_BY2                        = 0x56,
 912         DBG_BLOCK_ID_UNUSED37_BY2                        = 0x57,
 913         DBG_BLOCK_ID_TA10_BY2                            = 0x58,
 914         DBG_BLOCK_ID_TA12_BY2                            = 0x59,
 915         DBG_BLOCK_ID_TA14_BY2                            = 0x5a,
 916         DBG_BLOCK_ID_TA16_BY2                            = 0x5b,
 917         DBG_BLOCK_ID_TA18_BY2                            = 0x5c,
 918         DBG_BLOCK_ID_TA1A_BY2                            = 0x5d,
 919         DBG_BLOCK_ID_UNUSED39_BY2                        = 0x5e,
 920         DBG_BLOCK_ID_UNUSED41_BY2                        = 0x5f,
 921         DBG_BLOCK_ID_TD00_BY2                            = 0x60,
 922         DBG_BLOCK_ID_TD02_BY2                            = 0x61,
 923         DBG_BLOCK_ID_TD04_BY2                            = 0x62,
 924         DBG_BLOCK_ID_TD06_BY2                            = 0x63,
 925         DBG_BLOCK_ID_TD08_BY2                            = 0x64,
 926         DBG_BLOCK_ID_TD0A_BY2                            = 0x65,
 927         DBG_BLOCK_ID_UNUSED43_BY2                        = 0x66,
 928         DBG_BLOCK_ID_UNUSED45_BY2                        = 0x67,
 929         DBG_BLOCK_ID_TD10_BY2                            = 0x68,
 930         DBG_BLOCK_ID_TD12_BY2                            = 0x69,
 931         DBG_BLOCK_ID_TD14_BY2                            = 0x6a,
 932         DBG_BLOCK_ID_TD16_BY2                            = 0x6b,
 933         DBG_BLOCK_ID_TD18_BY2                            = 0x6c,
 934         DBG_BLOCK_ID_TD1A_BY2                            = 0x6d,
 935         DBG_BLOCK_ID_UNUSED47_BY2                        = 0x6e,
 936         DBG_BLOCK_ID_UNUSED49_BY2                        = 0x6f,
 937         DBG_BLOCK_ID_MCD0_BY2                            = 0x70,
 938         DBG_BLOCK_ID_MCD2_BY2                            = 0x71,
 939         DBG_BLOCK_ID_MCD4_BY2                            = 0x72,
 940         DBG_BLOCK_ID_UNUSED51_BY2                        = 0x73,
 941 } DebugBlockId_BY2;
 942 typedef enum DebugBlockId_BY4 {
 943         DBG_BLOCK_ID_RESERVED_BY4                        = 0x0,
 944         DBG_BLOCK_ID_CG_BY4                              = 0x1,
 945         DBG_BLOCK_ID_CSC_BY4                             = 0x2,
 946         DBG_BLOCK_ID_SQ_BY4                              = 0x3,
 947         DBG_BLOCK_ID_DMA0_BY4                            = 0x4,
 948         DBG_BLOCK_ID_SPIS_BY4                            = 0x5,
 949         DBG_BLOCK_ID_CP0_BY4                             = 0x6,
 950         DBG_BLOCK_ID_UVDU_BY4                            = 0x7,
 951         DBG_BLOCK_ID_VGT0_BY4                            = 0x8,
 952         DBG_BLOCK_ID_SCT0_BY4                            = 0x9,
 953         DBG_BLOCK_ID_TCAA_BY4                            = 0xa,
 954         DBG_BLOCK_ID_MCC0_BY4                            = 0xb,
 955         DBG_BLOCK_ID_SX0_BY4                             = 0xc,
 956         DBG_BLOCK_ID_UNUSED4_BY4                         = 0xd,
 957         DBG_BLOCK_ID_PC0_BY4                             = 0xe,
 958         DBG_BLOCK_ID_UNUSED10_BY4                        = 0xf,
 959         DBG_BLOCK_ID_SCB0_BY4                            = 0x10,
 960         DBG_BLOCK_ID_SCF0_BY4                            = 0x11,
 961         DBG_BLOCK_ID_BCI0_BY4                            = 0x12,
 962         DBG_BLOCK_ID_UNUSED17_BY4                        = 0x13,
 963         DBG_BLOCK_ID_CB00_BY4                            = 0x14,
 964         DBG_BLOCK_ID_CB04_BY4                            = 0x15,
 965         DBG_BLOCK_ID_CB10_BY4                            = 0x16,
 966         DBG_BLOCK_ID_CB14_BY4                            = 0x17,
 967         DBG_BLOCK_ID_TCP0_BY4                            = 0x18,
 968         DBG_BLOCK_ID_TCP4_BY4                            = 0x19,
 969         DBG_BLOCK_ID_TCP8_BY4                            = 0x1a,
 970         DBG_BLOCK_ID_TCP12_BY4                           = 0x1b,
 971         DBG_BLOCK_ID_TCP16_BY4                           = 0x1c,
 972         DBG_BLOCK_ID_TCP20_BY4                           = 0x1d,
 973         DBG_BLOCK_ID_TCP_RESERVED0_BY4                   = 0x1e,
 974         DBG_BLOCK_ID_TCP_RESERVED4_BY4                   = 0x1f,
 975         DBG_BLOCK_ID_DB_BY4                              = 0x20,
 976         DBG_BLOCK_ID_DB04_BY4                            = 0x21,
 977         DBG_BLOCK_ID_DB10_BY4                            = 0x22,
 978         DBG_BLOCK_ID_DB14_BY4                            = 0x23,
 979         DBG_BLOCK_ID_TCC0_BY4                            = 0x24,
 980         DBG_BLOCK_ID_TCC4_BY4                            = 0x25,
 981         DBG_BLOCK_ID_SPS00_BY4                           = 0x26,
 982         DBG_BLOCK_ID_SPS11_BY4                           = 0x27,
 983         DBG_BLOCK_ID_TA00_BY4                            = 0x28,
 984         DBG_BLOCK_ID_TA04_BY4                            = 0x29,
 985         DBG_BLOCK_ID_TA08_BY4                            = 0x2a,
 986         DBG_BLOCK_ID_UNUSED35_BY4                        = 0x2b,
 987         DBG_BLOCK_ID_TA10_BY4                            = 0x2c,
 988         DBG_BLOCK_ID_TA14_BY4                            = 0x2d,
 989         DBG_BLOCK_ID_TA18_BY4                            = 0x2e,
 990         DBG_BLOCK_ID_UNUSED39_BY4                        = 0x2f,
 991         DBG_BLOCK_ID_TD00_BY4                            = 0x30,
 992         DBG_BLOCK_ID_TD04_BY4                            = 0x31,
 993         DBG_BLOCK_ID_TD08_BY4                            = 0x32,
 994         DBG_BLOCK_ID_UNUSED43_BY4                        = 0x33,
 995         DBG_BLOCK_ID_TD10_BY4                            = 0x34,
 996         DBG_BLOCK_ID_TD14_BY4                            = 0x35,
 997         DBG_BLOCK_ID_TD18_BY4                            = 0x36,
 998         DBG_BLOCK_ID_UNUSED47_BY4                        = 0x37,
 999         DBG_BLOCK_ID_MCD0_BY4                            = 0x38,
1000         DBG_BLOCK_ID_MCD4_BY4                            = 0x39,
1001 } DebugBlockId_BY4;
1002 typedef enum DebugBlockId_BY8 {
1003         DBG_BLOCK_ID_RESERVED_BY8                        = 0x0,
1004         DBG_BLOCK_ID_CSC_BY8                             = 0x1,
1005         DBG_BLOCK_ID_DMA0_BY8                            = 0x2,
1006         DBG_BLOCK_ID_CP0_BY8                             = 0x3,
1007         DBG_BLOCK_ID_VGT0_BY8                            = 0x4,
1008         DBG_BLOCK_ID_TCAA_BY8                            = 0x5,
1009         DBG_BLOCK_ID_SX0_BY8                             = 0x6,
1010         DBG_BLOCK_ID_PC0_BY8                             = 0x7,
1011         DBG_BLOCK_ID_SCB0_BY8                            = 0x8,
1012         DBG_BLOCK_ID_BCI0_BY8                            = 0x9,
1013         DBG_BLOCK_ID_CB00_BY8                            = 0xa,
1014         DBG_BLOCK_ID_CB10_BY8                            = 0xb,
1015         DBG_BLOCK_ID_TCP0_BY8                            = 0xc,
1016         DBG_BLOCK_ID_TCP8_BY8                            = 0xd,
1017         DBG_BLOCK_ID_TCP16_BY8                           = 0xe,
1018         DBG_BLOCK_ID_TCP_RESERVED0_BY8                   = 0xf,
1019         DBG_BLOCK_ID_DB00_BY8                            = 0x10,
1020         DBG_BLOCK_ID_DB10_BY8                            = 0x11,
1021         DBG_BLOCK_ID_TCC0_BY8                            = 0x12,
1022         DBG_BLOCK_ID_SPS00_BY8                           = 0x13,
1023         DBG_BLOCK_ID_TA00_BY8                            = 0x14,
1024         DBG_BLOCK_ID_TA08_BY8                            = 0x15,
1025         DBG_BLOCK_ID_TA10_BY8                            = 0x16,
1026         DBG_BLOCK_ID_TA18_BY8                            = 0x17,
1027         DBG_BLOCK_ID_TD00_BY8                            = 0x18,
1028         DBG_BLOCK_ID_TD08_BY8                            = 0x19,
1029         DBG_BLOCK_ID_TD10_BY8                            = 0x1a,
1030         DBG_BLOCK_ID_TD18_BY8                            = 0x1b,
1031         DBG_BLOCK_ID_MCD0_BY8                            = 0x1c,
1032 } DebugBlockId_BY8;
1033 typedef enum DebugBlockId_BY16 {
1034         DBG_BLOCK_ID_RESERVED_BY16                       = 0x0,
1035         DBG_BLOCK_ID_DMA0_BY16                           = 0x1,
1036         DBG_BLOCK_ID_VGT0_BY16                           = 0x2,
1037         DBG_BLOCK_ID_SX0_BY16                            = 0x3,
1038         DBG_BLOCK_ID_SCB0_BY16                           = 0x4,
1039         DBG_BLOCK_ID_CB00_BY16                           = 0x5,
1040         DBG_BLOCK_ID_TCP0_BY16                           = 0x6,
1041         DBG_BLOCK_ID_TCP16_BY16                          = 0x7,
1042         DBG_BLOCK_ID_DB00_BY16                           = 0x8,
1043         DBG_BLOCK_ID_TCC0_BY16                           = 0x9,
1044         DBG_BLOCK_ID_TA00_BY16                           = 0xa,
1045         DBG_BLOCK_ID_TA10_BY16                           = 0xb,
1046         DBG_BLOCK_ID_TD00_BY16                           = 0xc,
1047         DBG_BLOCK_ID_TD10_BY16                           = 0xd,
1048         DBG_BLOCK_ID_MCD0_BY16                           = 0xe,
1049 } DebugBlockId_BY16;
1050 typedef enum ColorTransform {
1051         DCC_CT_AUTO                                      = 0x0,
1052         DCC_CT_NONE                                      = 0x1,
1053         ABGR_TO_A_BG_G_RB                                = 0x2,
1054         BGRA_TO_BG_G_RB_A                                = 0x3,
1055 } ColorTransform;
1056 typedef enum CompareRef {
1057         REF_NEVER                                        = 0x0,
1058         REF_LESS                                         = 0x1,
1059         REF_EQUAL                                        = 0x2,
1060         REF_LEQUAL                                       = 0x3,
1061         REF_GREATER                                      = 0x4,
1062         REF_NOTEQUAL                                     = 0x5,
1063         REF_GEQUAL                                       = 0x6,
1064         REF_ALWAYS                                       = 0x7,
1065 } CompareRef;
1066 typedef enum ReadSize {
1067         READ_256_BITS                                    = 0x0,
1068         READ_512_BITS                                    = 0x1,
1069 } ReadSize;
1070 typedef enum DepthFormat {
1071         DEPTH_INVALID                                    = 0x0,
1072         DEPTH_16                                         = 0x1,
1073         DEPTH_X8_24                                      = 0x2,
1074         DEPTH_8_24                                       = 0x3,
1075         DEPTH_X8_24_FLOAT                                = 0x4,
1076         DEPTH_8_24_FLOAT                                 = 0x5,
1077         DEPTH_32_FLOAT                                   = 0x6,
1078         DEPTH_X24_8_32_FLOAT                             = 0x7,
1079 } DepthFormat;
1080 typedef enum ZFormat {
1081         Z_INVALID                                        = 0x0,
1082         Z_16                                             = 0x1,
1083         Z_24                                             = 0x2,
1084         Z_32_FLOAT                                       = 0x3,
1085 } ZFormat;
1086 typedef enum StencilFormat {
1087         STENCIL_INVALID                                  = 0x0,
1088         STENCIL_8                                        = 0x1,
1089 } StencilFormat;
1090 typedef enum CmaskMode {
1091         CMASK_CLEAR_NONE                                 = 0x0,
1092         CMASK_CLEAR_ONE                                  = 0x1,
1093         CMASK_CLEAR_ALL                                  = 0x2,
1094         CMASK_ANY_EXPANDED                               = 0x3,
1095         CMASK_ALPHA0_FRAG1                               = 0x4,
1096         CMASK_ALPHA0_FRAG2                               = 0x5,
1097         CMASK_ALPHA0_FRAG4                               = 0x6,
1098         CMASK_ALPHA0_FRAGS                               = 0x7,
1099         CMASK_ALPHA1_FRAG1                               = 0x8,
1100         CMASK_ALPHA1_FRAG2                               = 0x9,
1101         CMASK_ALPHA1_FRAG4                               = 0xa,
1102         CMASK_ALPHA1_FRAGS                               = 0xb,
1103         CMASK_ALPHAX_FRAG1                               = 0xc,
1104         CMASK_ALPHAX_FRAG2                               = 0xd,
1105         CMASK_ALPHAX_FRAG4                               = 0xe,
1106         CMASK_ALPHAX_FRAGS                               = 0xf,
1107 } CmaskMode;
1108 typedef enum QuadExportFormat {
1109         EXPORT_UNUSED                                    = 0x0,
1110         EXPORT_32_R                                      = 0x1,
1111         EXPORT_32_GR                                     = 0x2,
1112         EXPORT_32_AR                                     = 0x3,
1113         EXPORT_FP16_ABGR                                 = 0x4,
1114         EXPORT_UNSIGNED16_ABGR                           = 0x5,
1115         EXPORT_SIGNED16_ABGR                             = 0x6,
1116         EXPORT_32_ABGR                                   = 0x7,
1117 } QuadExportFormat;
1118 typedef enum QuadExportFormatOld {
1119         EXPORT_4P_32BPC_ABGR                             = 0x0,
1120         EXPORT_4P_16BPC_ABGR                             = 0x1,
1121         EXPORT_4P_32BPC_GR                               = 0x2,
1122         EXPORT_4P_32BPC_AR                               = 0x3,
1123         EXPORT_2P_32BPC_ABGR                             = 0x4,
1124         EXPORT_8P_32BPC_R                                = 0x5,
1125 } QuadExportFormatOld;
1126 typedef enum ColorFormat {
1127         COLOR_INVALID                                    = 0x0,
1128         COLOR_8                                          = 0x1,
1129         COLOR_16                                         = 0x2,
1130         COLOR_8_8                                        = 0x3,
1131         COLOR_32                                         = 0x4,
1132         COLOR_16_16                                      = 0x5,
1133         COLOR_10_11_11                                   = 0x6,
1134         COLOR_11_11_10                                   = 0x7,
1135         COLOR_10_10_10_2                                 = 0x8,
1136         COLOR_2_10_10_10                                 = 0x9,
1137         COLOR_8_8_8_8                                    = 0xa,
1138         COLOR_32_32                                      = 0xb,
1139         COLOR_16_16_16_16                                = 0xc,
1140         COLOR_RESERVED_13                                = 0xd,
1141         COLOR_32_32_32_32                                = 0xe,
1142         COLOR_RESERVED_15                                = 0xf,
1143         COLOR_5_6_5                                      = 0x10,
1144         COLOR_1_5_5_5                                    = 0x11,
1145         COLOR_5_5_5_1                                    = 0x12,
1146         COLOR_4_4_4_4                                    = 0x13,
1147         COLOR_8_24                                       = 0x14,
1148         COLOR_24_8                                       = 0x15,
1149         COLOR_X24_8_32_FLOAT                             = 0x16,
1150         COLOR_RESERVED_23                                = 0x17,
1151 } ColorFormat;
1152 typedef enum SurfaceFormat {
1153         FMT_INVALID                                      = 0x0,
1154         FMT_8                                            = 0x1,
1155         FMT_16                                           = 0x2,
1156         FMT_8_8                                          = 0x3,
1157         FMT_32                                           = 0x4,
1158         FMT_16_16                                        = 0x5,
1159         FMT_10_11_11                                     = 0x6,
1160         FMT_11_11_10                                     = 0x7,
1161         FMT_10_10_10_2                                   = 0x8,
1162         FMT_2_10_10_10                                   = 0x9,
1163         FMT_8_8_8_8                                      = 0xa,
1164         FMT_32_32                                        = 0xb,
1165         FMT_16_16_16_16                                  = 0xc,
1166         FMT_32_32_32                                     = 0xd,
1167         FMT_32_32_32_32                                  = 0xe,
1168         FMT_RESERVED_4                                   = 0xf,
1169         FMT_5_6_5                                        = 0x10,
1170         FMT_1_5_5_5                                      = 0x11,
1171         FMT_5_5_5_1                                      = 0x12,
1172         FMT_4_4_4_4                                      = 0x13,
1173         FMT_8_24                                         = 0x14,
1174         FMT_24_8                                         = 0x15,
1175         FMT_X24_8_32_FLOAT                               = 0x16,
1176         FMT_RESERVED_33                                  = 0x17,
1177         FMT_11_11_10_FLOAT                               = 0x18,
1178         FMT_16_FLOAT                                     = 0x19,
1179         FMT_32_FLOAT                                     = 0x1a,
1180         FMT_16_16_FLOAT                                  = 0x1b,
1181         FMT_8_24_FLOAT                                   = 0x1c,
1182         FMT_24_8_FLOAT                                   = 0x1d,
1183         FMT_32_32_FLOAT                                  = 0x1e,
1184         FMT_10_11_11_FLOAT                               = 0x1f,
1185         FMT_16_16_16_16_FLOAT                            = 0x20,
1186         FMT_3_3_2                                        = 0x21,
1187         FMT_6_5_5                                        = 0x22,
1188         FMT_32_32_32_32_FLOAT                            = 0x23,
1189         FMT_RESERVED_36                                  = 0x24,
1190         FMT_1                                            = 0x25,
1191         FMT_1_REVERSED                                   = 0x26,
1192         FMT_GB_GR                                        = 0x27,
1193         FMT_BG_RG                                        = 0x28,
1194         FMT_32_AS_8                                      = 0x29,
1195         FMT_32_AS_8_8                                    = 0x2a,
1196         FMT_5_9_9_9_SHAREDEXP                            = 0x2b,
1197         FMT_8_8_8                                        = 0x2c,
1198         FMT_16_16_16                                     = 0x2d,
1199         FMT_16_16_16_FLOAT                               = 0x2e,
1200         FMT_4_4                                          = 0x2f,
1201         FMT_32_32_32_FLOAT                               = 0x30,
1202         FMT_BC1                                          = 0x31,
1203         FMT_BC2                                          = 0x32,
1204         FMT_BC3                                          = 0x33,
1205         FMT_BC4                                          = 0x34,
1206         FMT_BC5                                          = 0x35,
1207         FMT_BC6                                          = 0x36,
1208         FMT_BC7                                          = 0x37,
1209         FMT_32_AS_32_32_32_32                            = 0x38,
1210         FMT_APC3                                         = 0x39,
1211         FMT_APC4                                         = 0x3a,
1212         FMT_APC5                                         = 0x3b,
1213         FMT_APC6                                         = 0x3c,
1214         FMT_APC7                                         = 0x3d,
1215         FMT_CTX1                                         = 0x3e,
1216         FMT_RESERVED_63                                  = 0x3f,
1217 } SurfaceFormat;
1218 typedef enum BUF_DATA_FORMAT {
1219         BUF_DATA_FORMAT_INVALID                          = 0x0,
1220         BUF_DATA_FORMAT_8                                = 0x1,
1221         BUF_DATA_FORMAT_16                               = 0x2,
1222         BUF_DATA_FORMAT_8_8                              = 0x3,
1223         BUF_DATA_FORMAT_32                               = 0x4,
1224         BUF_DATA_FORMAT_16_16                            = 0x5,
1225         BUF_DATA_FORMAT_10_11_11                         = 0x6,
1226         BUF_DATA_FORMAT_11_11_10                         = 0x7,
1227         BUF_DATA_FORMAT_10_10_10_2                       = 0x8,
1228         BUF_DATA_FORMAT_2_10_10_10                       = 0x9,
1229         BUF_DATA_FORMAT_8_8_8_8                          = 0xa,
1230         BUF_DATA_FORMAT_32_32                            = 0xb,
1231         BUF_DATA_FORMAT_16_16_16_16                      = 0xc,
1232         BUF_DATA_FORMAT_32_32_32                         = 0xd,
1233         BUF_DATA_FORMAT_32_32_32_32                      = 0xe,
1234         BUF_DATA_FORMAT_RESERVED_15                      = 0xf,
1235 } BUF_DATA_FORMAT;
1236 typedef enum IMG_DATA_FORMAT {
1237         IMG_DATA_FORMAT_INVALID                          = 0x0,
1238         IMG_DATA_FORMAT_8                                = 0x1,
1239         IMG_DATA_FORMAT_16                               = 0x2,
1240         IMG_DATA_FORMAT_8_8                              = 0x3,
1241         IMG_DATA_FORMAT_32                               = 0x4,
1242         IMG_DATA_FORMAT_16_16                            = 0x5,
1243         IMG_DATA_FORMAT_10_11_11                         = 0x6,
1244         IMG_DATA_FORMAT_11_11_10                         = 0x7,
1245         IMG_DATA_FORMAT_10_10_10_2                       = 0x8,
1246         IMG_DATA_FORMAT_2_10_10_10                       = 0x9,
1247         IMG_DATA_FORMAT_8_8_8_8                          = 0xa,
1248         IMG_DATA_FORMAT_32_32                            = 0xb,
1249         IMG_DATA_FORMAT_16_16_16_16                      = 0xc,
1250         IMG_DATA_FORMAT_32_32_32                         = 0xd,
1251         IMG_DATA_FORMAT_32_32_32_32                      = 0xe,
1252         IMG_DATA_FORMAT_RESERVED_15                      = 0xf,
1253         IMG_DATA_FORMAT_5_6_5                            = 0x10,
1254         IMG_DATA_FORMAT_1_5_5_5                          = 0x11,
1255         IMG_DATA_FORMAT_5_5_5_1                          = 0x12,
1256         IMG_DATA_FORMAT_4_4_4_4                          = 0x13,
1257         IMG_DATA_FORMAT_8_24                             = 0x14,
1258         IMG_DATA_FORMAT_24_8                             = 0x15,
1259         IMG_DATA_FORMAT_X24_8_32                         = 0x16,
1260         IMG_DATA_FORMAT_RESERVED_23                      = 0x17,
1261         IMG_DATA_FORMAT_RESERVED_24                      = 0x18,
1262         IMG_DATA_FORMAT_RESERVED_25                      = 0x19,
1263         IMG_DATA_FORMAT_RESERVED_26                      = 0x1a,
1264         IMG_DATA_FORMAT_RESERVED_27                      = 0x1b,
1265         IMG_DATA_FORMAT_RESERVED_28                      = 0x1c,
1266         IMG_DATA_FORMAT_RESERVED_29                      = 0x1d,
1267         IMG_DATA_FORMAT_RESERVED_30                      = 0x1e,
1268         IMG_DATA_FORMAT_RESERVED_31                      = 0x1f,
1269         IMG_DATA_FORMAT_GB_GR                            = 0x20,
1270         IMG_DATA_FORMAT_BG_RG                            = 0x21,
1271         IMG_DATA_FORMAT_5_9_9_9                          = 0x22,
1272         IMG_DATA_FORMAT_BC1                              = 0x23,
1273         IMG_DATA_FORMAT_BC2                              = 0x24,
1274         IMG_DATA_FORMAT_BC3                              = 0x25,
1275         IMG_DATA_FORMAT_BC4                              = 0x26,
1276         IMG_DATA_FORMAT_BC5                              = 0x27,
1277         IMG_DATA_FORMAT_BC6                              = 0x28,
1278         IMG_DATA_FORMAT_BC7                              = 0x29,
1279         IMG_DATA_FORMAT_RESERVED_42                      = 0x2a,
1280         IMG_DATA_FORMAT_RESERVED_43                      = 0x2b,
1281         IMG_DATA_FORMAT_FMASK8_S2_F1                     = 0x2c,
1282         IMG_DATA_FORMAT_FMASK8_S4_F1                     = 0x2d,
1283         IMG_DATA_FORMAT_FMASK8_S8_F1                     = 0x2e,
1284         IMG_DATA_FORMAT_FMASK8_S2_F2                     = 0x2f,
1285         IMG_DATA_FORMAT_FMASK8_S4_F2                     = 0x30,
1286         IMG_DATA_FORMAT_FMASK8_S4_F4                     = 0x31,
1287         IMG_DATA_FORMAT_FMASK16_S16_F1                   = 0x32,
1288         IMG_DATA_FORMAT_FMASK16_S8_F2                    = 0x33,
1289         IMG_DATA_FORMAT_FMASK32_S16_F2                   = 0x34,
1290         IMG_DATA_FORMAT_FMASK32_S8_F4                    = 0x35,
1291         IMG_DATA_FORMAT_FMASK32_S8_F8                    = 0x36,
1292         IMG_DATA_FORMAT_FMASK64_S16_F4                   = 0x37,
1293         IMG_DATA_FORMAT_FMASK64_S16_F8                   = 0x38,
1294         IMG_DATA_FORMAT_4_4                              = 0x39,
1295         IMG_DATA_FORMAT_6_5_5                            = 0x3a,
1296         IMG_DATA_FORMAT_1                                = 0x3b,
1297         IMG_DATA_FORMAT_1_REVERSED                       = 0x3c,
1298         IMG_DATA_FORMAT_32_AS_8                          = 0x3d,
1299         IMG_DATA_FORMAT_32_AS_8_8                        = 0x3e,
1300         IMG_DATA_FORMAT_32_AS_32_32_32_32                = 0x3f,
1301 } IMG_DATA_FORMAT;
1302 typedef enum BUF_NUM_FORMAT {
1303         BUF_NUM_FORMAT_UNORM                             = 0x0,
1304         BUF_NUM_FORMAT_SNORM                             = 0x1,
1305         BUF_NUM_FORMAT_USCALED                           = 0x2,
1306         BUF_NUM_FORMAT_SSCALED                           = 0x3,
1307         BUF_NUM_FORMAT_UINT                              = 0x4,
1308         BUF_NUM_FORMAT_SINT                              = 0x5,
1309         BUF_NUM_FORMAT_RESERVED_6                        = 0x6,
1310         BUF_NUM_FORMAT_FLOAT                             = 0x7,
1311 } BUF_NUM_FORMAT;
1312 typedef enum IMG_NUM_FORMAT {
1313         IMG_NUM_FORMAT_UNORM                             = 0x0,
1314         IMG_NUM_FORMAT_SNORM                             = 0x1,
1315         IMG_NUM_FORMAT_USCALED                           = 0x2,
1316         IMG_NUM_FORMAT_SSCALED                           = 0x3,
1317         IMG_NUM_FORMAT_UINT                              = 0x4,
1318         IMG_NUM_FORMAT_SINT                              = 0x5,
1319         IMG_NUM_FORMAT_RESERVED_6                        = 0x6,
1320         IMG_NUM_FORMAT_FLOAT                             = 0x7,
1321         IMG_NUM_FORMAT_RESERVED_8                        = 0x8,
1322         IMG_NUM_FORMAT_SRGB                              = 0x9,
1323         IMG_NUM_FORMAT_RESERVED_10                       = 0xa,
1324         IMG_NUM_FORMAT_RESERVED_11                       = 0xb,
1325         IMG_NUM_FORMAT_RESERVED_12                       = 0xc,
1326         IMG_NUM_FORMAT_RESERVED_13                       = 0xd,
1327         IMG_NUM_FORMAT_RESERVED_14                       = 0xe,
1328         IMG_NUM_FORMAT_RESERVED_15                       = 0xf,
1329 } IMG_NUM_FORMAT;
1330 typedef enum TileType {
1331         ARRAY_COLOR_TILE                                 = 0x0,
1332         ARRAY_DEPTH_TILE                                 = 0x1,
1333 } TileType;
1334 typedef enum NonDispTilingOrder {
1335         ADDR_SURF_MICRO_TILING_DISPLAY                   = 0x0,
1336         ADDR_SURF_MICRO_TILING_NON_DISPLAY               = 0x1,
1337 } NonDispTilingOrder;
1338 typedef enum MicroTileMode {
1339         ADDR_SURF_DISPLAY_MICRO_TILING                   = 0x0,
1340         ADDR_SURF_THIN_MICRO_TILING                      = 0x1,
1341         ADDR_SURF_DEPTH_MICRO_TILING                     = 0x2,
1342         ADDR_SURF_ROTATED_MICRO_TILING                   = 0x3,
1343         ADDR_SURF_THICK_MICRO_TILING                     = 0x4,
1344 } MicroTileMode;
1345 typedef enum TileSplit {
1346         ADDR_SURF_TILE_SPLIT_64B                         = 0x0,
1347         ADDR_SURF_TILE_SPLIT_128B                        = 0x1,
1348         ADDR_SURF_TILE_SPLIT_256B                        = 0x2,
1349         ADDR_SURF_TILE_SPLIT_512B                        = 0x3,
1350         ADDR_SURF_TILE_SPLIT_1KB                         = 0x4,
1351         ADDR_SURF_TILE_SPLIT_2KB                         = 0x5,
1352         ADDR_SURF_TILE_SPLIT_4KB                         = 0x6,
1353 } TileSplit;
1354 typedef enum SampleSplit {
1355         ADDR_SURF_SAMPLE_SPLIT_1                         = 0x0,
1356         ADDR_SURF_SAMPLE_SPLIT_2                         = 0x1,
1357         ADDR_SURF_SAMPLE_SPLIT_4                         = 0x2,
1358         ADDR_SURF_SAMPLE_SPLIT_8                         = 0x3,
1359 } SampleSplit;
1360 typedef enum PipeConfig {
1361         ADDR_SURF_P2                                     = 0x0,
1362         ADDR_SURF_P2_RESERVED0                           = 0x1,
1363         ADDR_SURF_P2_RESERVED1                           = 0x2,
1364         ADDR_SURF_P2_RESERVED2                           = 0x3,
1365         ADDR_SURF_P4_8x16                                = 0x4,
1366         ADDR_SURF_P4_16x16                               = 0x5,
1367         ADDR_SURF_P4_16x32                               = 0x6,
1368         ADDR_SURF_P4_32x32                               = 0x7,
1369         ADDR_SURF_P8_16x16_8x16                          = 0x8,
1370         ADDR_SURF_P8_16x32_8x16                          = 0x9,
1371         ADDR_SURF_P8_32x32_8x16                          = 0xa,
1372         ADDR_SURF_P8_16x32_16x16                         = 0xb,
1373         ADDR_SURF_P8_32x32_16x16                         = 0xc,
1374         ADDR_SURF_P8_32x32_16x32                         = 0xd,
1375         ADDR_SURF_P8_32x64_32x32                         = 0xe,
1376         ADDR_SURF_P8_RESERVED0                           = 0xf,
1377         ADDR_SURF_P16_32x32_8x16                         = 0x10,
1378         ADDR_SURF_P16_32x32_16x16                        = 0x11,
1379 } PipeConfig;
1380 typedef enum NumBanks {
1381         ADDR_SURF_2_BANK                                 = 0x0,
1382         ADDR_SURF_4_BANK                                 = 0x1,
1383         ADDR_SURF_8_BANK                                 = 0x2,
1384         ADDR_SURF_16_BANK                                = 0x3,
1385 } NumBanks;
1386 typedef enum BankWidth {
1387         ADDR_SURF_BANK_WIDTH_1                           = 0x0,
1388         ADDR_SURF_BANK_WIDTH_2                           = 0x1,
1389         ADDR_SURF_BANK_WIDTH_4                           = 0x2,
1390         ADDR_SURF_BANK_WIDTH_8                           = 0x3,
1391 } BankWidth;
1392 typedef enum BankHeight {
1393         ADDR_SURF_BANK_HEIGHT_1                          = 0x0,
1394         ADDR_SURF_BANK_HEIGHT_2                          = 0x1,
1395         ADDR_SURF_BANK_HEIGHT_4                          = 0x2,
1396         ADDR_SURF_BANK_HEIGHT_8                          = 0x3,
1397 } BankHeight;
1398 typedef enum BankWidthHeight {
1399         ADDR_SURF_BANK_WH_1                              = 0x0,
1400         ADDR_SURF_BANK_WH_2                              = 0x1,
1401         ADDR_SURF_BANK_WH_4                              = 0x2,
1402         ADDR_SURF_BANK_WH_8                              = 0x3,
1403 } BankWidthHeight;
1404 typedef enum MacroTileAspect {
1405         ADDR_SURF_MACRO_ASPECT_1                         = 0x0,
1406         ADDR_SURF_MACRO_ASPECT_2                         = 0x1,
1407         ADDR_SURF_MACRO_ASPECT_4                         = 0x2,
1408         ADDR_SURF_MACRO_ASPECT_8                         = 0x3,
1409 } MacroTileAspect;
1410 typedef enum GATCL1RequestType {
1411         GATCL1_TYPE_NORMAL                               = 0x0,
1412         GATCL1_TYPE_SHOOTDOWN                            = 0x1,
1413         GATCL1_TYPE_BYPASS                               = 0x2,
1414 } GATCL1RequestType;
1415 typedef enum TCC_CACHE_POLICIES {
1416         TCC_CACHE_POLICY_LRU                             = 0x0,
1417         TCC_CACHE_POLICY_STREAM                          = 0x1,
1418 } TCC_CACHE_POLICIES;
1419 typedef enum MTYPE {
1420         MTYPE_NC_NV                                      = 0x0,
1421         MTYPE_NC                                         = 0x1,
1422         MTYPE_CC                                         = 0x2,
1423         MTYPE_UC                                         = 0x3,
1424 } MTYPE;
1425 typedef enum PERFMON_COUNTER_MODE {
1426         PERFMON_COUNTER_MODE_ACCUM                       = 0x0,
1427         PERFMON_COUNTER_MODE_ACTIVE_CYCLES               = 0x1,
1428         PERFMON_COUNTER_MODE_MAX                         = 0x2,
1429         PERFMON_COUNTER_MODE_DIRTY                       = 0x3,
1430         PERFMON_COUNTER_MODE_SAMPLE                      = 0x4,
1431         PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT    = 0x5,
1432         PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT     = 0x6,
1433         PERFMON_COUNTER_MODE_CYCLES_GE_HI                = 0x7,
1434         PERFMON_COUNTER_MODE_CYCLES_EQ_HI                = 0x8,
1435         PERFMON_COUNTER_MODE_INACTIVE_CYCLES             = 0x9,
1436         PERFMON_COUNTER_MODE_RESERVED                    = 0xf,
1437 } PERFMON_COUNTER_MODE;
1438 typedef enum PERFMON_SPM_MODE {
1439         PERFMON_SPM_MODE_OFF                             = 0x0,
1440         PERFMON_SPM_MODE_16BIT_CLAMP                     = 0x1,
1441         PERFMON_SPM_MODE_16BIT_NO_CLAMP                  = 0x2,
1442         PERFMON_SPM_MODE_32BIT_CLAMP                     = 0x3,
1443         PERFMON_SPM_MODE_32BIT_NO_CLAMP                  = 0x4,
1444         PERFMON_SPM_MODE_RESERVED_5                      = 0x5,
1445         PERFMON_SPM_MODE_RESERVED_6                      = 0x6,
1446         PERFMON_SPM_MODE_RESERVED_7                      = 0x7,
1447         PERFMON_SPM_MODE_TEST_MODE_0                     = 0x8,
1448         PERFMON_SPM_MODE_TEST_MODE_1                     = 0x9,
1449         PERFMON_SPM_MODE_TEST_MODE_2                     = 0xa,
1450 } PERFMON_SPM_MODE;
1451 typedef enum SurfaceTiling {
1452         ARRAY_LINEAR                                     = 0x0,
1453         ARRAY_TILED                                      = 0x1,
1454 } SurfaceTiling;
1455 typedef enum SurfaceArray {
1456         ARRAY_1D                                         = 0x0,
1457         ARRAY_2D                                         = 0x1,
1458         ARRAY_3D                                         = 0x2,
1459         ARRAY_3D_SLICE                                   = 0x3,
1460 } SurfaceArray;
1461 typedef enum ColorArray {
1462         ARRAY_2D_ALT_COLOR                               = 0x0,
1463         ARRAY_2D_COLOR                                   = 0x1,
1464         ARRAY_3D_SLICE_COLOR                             = 0x3,
1465 } ColorArray;
1466 typedef enum DepthArray {
1467         ARRAY_2D_ALT_DEPTH                               = 0x0,
1468         ARRAY_2D_DEPTH                                   = 0x1,
1469 } DepthArray;
1470 typedef enum ENUM_NUM_SIMD_PER_CU {
1471         NUM_SIMD_PER_CU                                  = 0x4,
1472 } ENUM_NUM_SIMD_PER_CU;
1473 typedef enum MEM_PWR_FORCE_CTRL {
1474         NO_FORCE_REQUEST                                 = 0x0,
1475         FORCE_LIGHT_SLEEP_REQUEST                        = 0x1,
1476         FORCE_DEEP_SLEEP_REQUEST                         = 0x2,
1477         FORCE_SHUT_DOWN_REQUEST                          = 0x3,
1478 } MEM_PWR_FORCE_CTRL;
1479 typedef enum MEM_PWR_FORCE_CTRL2 {
1480         NO_FORCE_REQ                                     = 0x0,
1481         FORCE_LIGHT_SLEEP_REQ                            = 0x1,
1482 } MEM_PWR_FORCE_CTRL2;
1483 typedef enum MEM_PWR_DIS_CTRL {
1484         ENABLE_MEM_PWR_CTRL                              = 0x0,
1485         DISABLE_MEM_PWR_CTRL                             = 0x1,
1486 } MEM_PWR_DIS_CTRL;
1487 typedef enum MEM_PWR_SEL_CTRL {
1488         DYNAMIC_SHUT_DOWN_ENABLE                         = 0x0,
1489         DYNAMIC_DEEP_SLEEP_ENABLE                        = 0x1,
1490         DYNAMIC_LIGHT_SLEEP_ENABLE                       = 0x2,
1491 } MEM_PWR_SEL_CTRL;
1492 typedef enum MEM_PWR_SEL_CTRL2 {
1493         DYNAMIC_DEEP_SLEEP_EN                            = 0x0,
1494         DYNAMIC_LIGHT_SLEEP_EN                           = 0x1,
1495 } MEM_PWR_SEL_CTRL2;
1496 
1497 #endif /* OSS_3_0_ENUM_H */