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21 #ifndef _osssys_4_0_OFFSET_HEADER
22 #define _osssys_4_0_OFFSET_HEADER
23
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26
27
28 #define mmIH_VMID_0_LUT 0x0000
29 #define mmIH_VMID_0_LUT_BASE_IDX 0
30 #define mmIH_VMID_1_LUT 0x0001
31 #define mmIH_VMID_1_LUT_BASE_IDX 0
32 #define mmIH_VMID_2_LUT 0x0002
33 #define mmIH_VMID_2_LUT_BASE_IDX 0
34 #define mmIH_VMID_3_LUT 0x0003
35 #define mmIH_VMID_3_LUT_BASE_IDX 0
36 #define mmIH_VMID_4_LUT 0x0004
37 #define mmIH_VMID_4_LUT_BASE_IDX 0
38 #define mmIH_VMID_5_LUT 0x0005
39 #define mmIH_VMID_5_LUT_BASE_IDX 0
40 #define mmIH_VMID_6_LUT 0x0006
41 #define mmIH_VMID_6_LUT_BASE_IDX 0
42 #define mmIH_VMID_7_LUT 0x0007
43 #define mmIH_VMID_7_LUT_BASE_IDX 0
44 #define mmIH_VMID_8_LUT 0x0008
45 #define mmIH_VMID_8_LUT_BASE_IDX 0
46 #define mmIH_VMID_9_LUT 0x0009
47 #define mmIH_VMID_9_LUT_BASE_IDX 0
48 #define mmIH_VMID_10_LUT 0x000a
49 #define mmIH_VMID_10_LUT_BASE_IDX 0
50 #define mmIH_VMID_11_LUT 0x000b
51 #define mmIH_VMID_11_LUT_BASE_IDX 0
52 #define mmIH_VMID_12_LUT 0x000c
53 #define mmIH_VMID_12_LUT_BASE_IDX 0
54 #define mmIH_VMID_13_LUT 0x000d
55 #define mmIH_VMID_13_LUT_BASE_IDX 0
56 #define mmIH_VMID_14_LUT 0x000e
57 #define mmIH_VMID_14_LUT_BASE_IDX 0
58 #define mmIH_VMID_15_LUT 0x000f
59 #define mmIH_VMID_15_LUT_BASE_IDX 0
60 #define mmIH_VMID_0_LUT_MM 0x0010
61 #define mmIH_VMID_0_LUT_MM_BASE_IDX 0
62 #define mmIH_VMID_1_LUT_MM 0x0011
63 #define mmIH_VMID_1_LUT_MM_BASE_IDX 0
64 #define mmIH_VMID_2_LUT_MM 0x0012
65 #define mmIH_VMID_2_LUT_MM_BASE_IDX 0
66 #define mmIH_VMID_3_LUT_MM 0x0013
67 #define mmIH_VMID_3_LUT_MM_BASE_IDX 0
68 #define mmIH_VMID_4_LUT_MM 0x0014
69 #define mmIH_VMID_4_LUT_MM_BASE_IDX 0
70 #define mmIH_VMID_5_LUT_MM 0x0015
71 #define mmIH_VMID_5_LUT_MM_BASE_IDX 0
72 #define mmIH_VMID_6_LUT_MM 0x0016
73 #define mmIH_VMID_6_LUT_MM_BASE_IDX 0
74 #define mmIH_VMID_7_LUT_MM 0x0017
75 #define mmIH_VMID_7_LUT_MM_BASE_IDX 0
76 #define mmIH_VMID_8_LUT_MM 0x0018
77 #define mmIH_VMID_8_LUT_MM_BASE_IDX 0
78 #define mmIH_VMID_9_LUT_MM 0x0019
79 #define mmIH_VMID_9_LUT_MM_BASE_IDX 0
80 #define mmIH_VMID_10_LUT_MM 0x001a
81 #define mmIH_VMID_10_LUT_MM_BASE_IDX 0
82 #define mmIH_VMID_11_LUT_MM 0x001b
83 #define mmIH_VMID_11_LUT_MM_BASE_IDX 0
84 #define mmIH_VMID_12_LUT_MM 0x001c
85 #define mmIH_VMID_12_LUT_MM_BASE_IDX 0
86 #define mmIH_VMID_13_LUT_MM 0x001d
87 #define mmIH_VMID_13_LUT_MM_BASE_IDX 0
88 #define mmIH_VMID_14_LUT_MM 0x001e
89 #define mmIH_VMID_14_LUT_MM_BASE_IDX 0
90 #define mmIH_VMID_15_LUT_MM 0x001f
91 #define mmIH_VMID_15_LUT_MM_BASE_IDX 0
92 #define mmIH_COOKIE_0 0x0020
93 #define mmIH_COOKIE_0_BASE_IDX 0
94 #define mmIH_COOKIE_1 0x0021
95 #define mmIH_COOKIE_1_BASE_IDX 0
96 #define mmIH_COOKIE_2 0x0022
97 #define mmIH_COOKIE_2_BASE_IDX 0
98 #define mmIH_COOKIE_3 0x0023
99 #define mmIH_COOKIE_3_BASE_IDX 0
100 #define mmIH_COOKIE_4 0x0024
101 #define mmIH_COOKIE_4_BASE_IDX 0
102 #define mmIH_COOKIE_5 0x0025
103 #define mmIH_COOKIE_5_BASE_IDX 0
104 #define mmIH_COOKIE_6 0x0026
105 #define mmIH_COOKIE_6_BASE_IDX 0
106 #define mmIH_COOKIE_7 0x0027
107 #define mmIH_COOKIE_7_BASE_IDX 0
108 #define mmIH_REGISTER_LAST_PART0 0x003f
109 #define mmIH_REGISTER_LAST_PART0_BASE_IDX 0
110 #define mmSEM_REQ_INPUT_0 0x0040
111 #define mmSEM_REQ_INPUT_0_BASE_IDX 0
112 #define mmSEM_REQ_INPUT_1 0x0041
113 #define mmSEM_REQ_INPUT_1_BASE_IDX 0
114 #define mmSEM_REQ_INPUT_2 0x0042
115 #define mmSEM_REQ_INPUT_2_BASE_IDX 0
116 #define mmSEM_REQ_INPUT_3 0x0043
117 #define mmSEM_REQ_INPUT_3_BASE_IDX 0
118 #define mmSEM_REGISTER_LAST_PART0 0x007f
119 #define mmSEM_REGISTER_LAST_PART0_BASE_IDX 0
120 #define mmIH_RB_CNTL 0x0080
121 #define mmIH_RB_CNTL_BASE_IDX 0
122 #define mmIH_RB_BASE 0x0081
123 #define mmIH_RB_BASE_BASE_IDX 0
124 #define mmIH_RB_BASE_HI 0x0082
125 #define mmIH_RB_BASE_HI_BASE_IDX 0
126 #define mmIH_RB_RPTR 0x0083
127 #define mmIH_RB_RPTR_BASE_IDX 0
128 #define mmIH_RB_WPTR 0x0084
129 #define mmIH_RB_WPTR_BASE_IDX 0
130 #define mmIH_RB_WPTR_ADDR_HI 0x0085
131 #define mmIH_RB_WPTR_ADDR_HI_BASE_IDX 0
132 #define mmIH_RB_WPTR_ADDR_LO 0x0086
133 #define mmIH_RB_WPTR_ADDR_LO_BASE_IDX 0
134 #define mmIH_DOORBELL_RPTR 0x0087
135 #define mmIH_DOORBELL_RPTR_BASE_IDX 0
136 #define mmIH_RB_CNTL_RING1 0x0088
137 #define mmIH_RB_CNTL_RING1_BASE_IDX 0
138 #define mmIH_RB_BASE_RING1 0x0089
139 #define mmIH_RB_BASE_RING1_BASE_IDX 0
140 #define mmIH_RB_BASE_HI_RING1 0x008a
141 #define mmIH_RB_BASE_HI_RING1_BASE_IDX 0
142 #define mmIH_RB_RPTR_RING1 0x008b
143 #define mmIH_RB_RPTR_RING1_BASE_IDX 0
144 #define mmIH_RB_WPTR_RING1 0x008c
145 #define mmIH_RB_WPTR_RING1_BASE_IDX 0
146 #define mmIH_DOORBELL_RPTR_RING1 0x008f
147 #define mmIH_DOORBELL_RPTR_RING1_BASE_IDX 0
148 #define mmIH_RB_CNTL_RING2 0x0090
149 #define mmIH_RB_CNTL_RING2_BASE_IDX 0
150 #define mmIH_RB_BASE_RING2 0x0091
151 #define mmIH_RB_BASE_RING2_BASE_IDX 0
152 #define mmIH_RB_BASE_HI_RING2 0x0092
153 #define mmIH_RB_BASE_HI_RING2_BASE_IDX 0
154 #define mmIH_RB_RPTR_RING2 0x0093
155 #define mmIH_RB_RPTR_RING2_BASE_IDX 0
156 #define mmIH_RB_WPTR_RING2 0x0094
157 #define mmIH_RB_WPTR_RING2_BASE_IDX 0
158 #define mmIH_DOORBELL_RPTR_RING2 0x0097
159 #define mmIH_DOORBELL_RPTR_RING2_BASE_IDX 0
160 #define mmIH_VERSION 0x0098
161 #define mmIH_VERSION_BASE_IDX 0
162 #define mmIH_CNTL 0x00c0
163 #define mmIH_CNTL_BASE_IDX 0
164 #define mmIH_CNTL2 0x00c1
165 #define mmIH_CNTL2_BASE_IDX 0
166 #define mmIH_STATUS 0x00c2
167 #define mmIH_STATUS_BASE_IDX 0
168 #define mmIH_PERFMON_CNTL 0x00c3
169 #define mmIH_PERFMON_CNTL_BASE_IDX 0
170 #define mmIH_PERFCOUNTER0_RESULT 0x00c4
171 #define mmIH_PERFCOUNTER0_RESULT_BASE_IDX 0
172 #define mmIH_PERFCOUNTER1_RESULT 0x00c5
173 #define mmIH_PERFCOUNTER1_RESULT_BASE_IDX 0
174 #define mmIH_DSM_MATCH_VALUE_BIT_31_0 0x00c7
175 #define mmIH_DSM_MATCH_VALUE_BIT_31_0_BASE_IDX 0
176 #define mmIH_DSM_MATCH_VALUE_BIT_63_32 0x00c8
177 #define mmIH_DSM_MATCH_VALUE_BIT_63_32_BASE_IDX 0
178 #define mmIH_DSM_MATCH_VALUE_BIT_95_64 0x00c9
179 #define mmIH_DSM_MATCH_VALUE_BIT_95_64_BASE_IDX 0
180 #define mmIH_DSM_MATCH_FIELD_CONTROL 0x00ca
181 #define mmIH_DSM_MATCH_FIELD_CONTROL_BASE_IDX 0
182 #define mmIH_DSM_MATCH_DATA_CONTROL 0x00cb
183 #define mmIH_DSM_MATCH_DATA_CONTROL_BASE_IDX 0
184 #define mmIH_DSM_MATCH_FCN_ID 0x00cc
185 #define mmIH_DSM_MATCH_FCN_ID_BASE_IDX 0
186 #define mmIH_LIMIT_INT_RATE_CNTL 0x00cd
187 #define mmIH_LIMIT_INT_RATE_CNTL_BASE_IDX 0
188 #define mmIH_VF_RB_STATUS 0x00ce
189 #define mmIH_VF_RB_STATUS_BASE_IDX 0
190 #define mmIH_VF_RB_STATUS2 0x00cf
191 #define mmIH_VF_RB_STATUS2_BASE_IDX 0
192 #define mmIH_VF_RB1_STATUS 0x00d0
193 #define mmIH_VF_RB1_STATUS_BASE_IDX 0
194 #define mmIH_VF_RB1_STATUS2 0x00d1
195 #define mmIH_VF_RB1_STATUS2_BASE_IDX 0
196 #define mmIH_VF_RB2_STATUS 0x00d2
197 #define mmIH_VF_RB2_STATUS_BASE_IDX 0
198 #define mmIH_VF_RB2_STATUS2 0x00d3
199 #define mmIH_VF_RB2_STATUS2_BASE_IDX 0
200 #define mmIH_INT_FLOOD_CNTL 0x00d5
201 #define mmIH_INT_FLOOD_CNTL_BASE_IDX 0
202 #define mmIH_RB0_INT_FLOOD_STATUS 0x00d6
203 #define mmIH_RB0_INT_FLOOD_STATUS_BASE_IDX 0
204 #define mmIH_RB1_INT_FLOOD_STATUS 0x00d7
205 #define mmIH_RB1_INT_FLOOD_STATUS_BASE_IDX 0
206 #define mmIH_RB2_INT_FLOOD_STATUS 0x00d8
207 #define mmIH_RB2_INT_FLOOD_STATUS_BASE_IDX 0
208 #define mmIH_INT_FLOOD_STATUS 0x00d9
209 #define mmIH_INT_FLOOD_STATUS_BASE_IDX 0
210 #define mmIH_STORM_CLIENT_LIST_CNTL 0x00da
211 #define mmIH_STORM_CLIENT_LIST_CNTL_BASE_IDX 0
212 #define mmIH_CLK_CTRL 0x00db
213 #define mmIH_CLK_CTRL_BASE_IDX 0
214 #define mmIH_INT_FLAGS 0x00dc
215 #define mmIH_INT_FLAGS_BASE_IDX 0
216 #define mmIH_LAST_INT_INFO0 0x00dd
217 #define mmIH_LAST_INT_INFO0_BASE_IDX 0
218 #define mmIH_LAST_INT_INFO1 0x00de
219 #define mmIH_LAST_INT_INFO1_BASE_IDX 0
220 #define mmIH_LAST_INT_INFO2 0x00df
221 #define mmIH_LAST_INT_INFO2_BASE_IDX 0
222 #define mmIH_SCRATCH 0x00e0
223 #define mmIH_SCRATCH_BASE_IDX 0
224 #define mmIH_CLIENT_CREDIT_ERROR 0x00e1
225 #define mmIH_CLIENT_CREDIT_ERROR_BASE_IDX 0
226 #define mmIH_GPU_IOV_VIOLATION_LOG 0x00e2
227 #define mmIH_GPU_IOV_VIOLATION_LOG_BASE_IDX 0
228 #define mmIH_COOKIE_REC_VIOLATION_LOG 0x00e3
229 #define mmIH_COOKIE_REC_VIOLATION_LOG_BASE_IDX 0
230 #define mmIH_CREDIT_STATUS 0x00e4
231 #define mmIH_CREDIT_STATUS_BASE_IDX 0
232 #define mmIH_MMHUB_ERROR 0x00e5
233 #define mmIH_MMHUB_ERROR_BASE_IDX 0
234 #define mmIH_REGISTER_LAST_PART2 0x00ff
235 #define mmIH_REGISTER_LAST_PART2_BASE_IDX 0
236 #define mmSEM_CLK_CTRL 0x0100
237 #define mmSEM_CLK_CTRL_BASE_IDX 0
238 #define mmSEM_UTC_CREDIT 0x0101
239 #define mmSEM_UTC_CREDIT_BASE_IDX 0
240 #define mmSEM_UTC_CONFIG 0x0102
241 #define mmSEM_UTC_CONFIG_BASE_IDX 0
242 #define mmSEM_UTCL2_TRAN_EN_LUT 0x0103
243 #define mmSEM_UTCL2_TRAN_EN_LUT_BASE_IDX 0
244 #define mmSEM_MCIF_CONFIG 0x0104
245 #define mmSEM_MCIF_CONFIG_BASE_IDX 0
246 #define mmSEM_PERFMON_CNTL 0x0105
247 #define mmSEM_PERFMON_CNTL_BASE_IDX 0
248 #define mmSEM_PERFCOUNTER0_RESULT 0x0106
249 #define mmSEM_PERFCOUNTER0_RESULT_BASE_IDX 0
250 #define mmSEM_PERFCOUNTER1_RESULT 0x0107
251 #define mmSEM_PERFCOUNTER1_RESULT_BASE_IDX 0
252 #define mmSEM_STATUS 0x0108
253 #define mmSEM_STATUS_BASE_IDX 0
254 #define mmSEM_MAILBOX_CLIENTCONFIG 0x0109
255 #define mmSEM_MAILBOX_CLIENTCONFIG_BASE_IDX 0
256 #define mmSEM_MAILBOX 0x010a
257 #define mmSEM_MAILBOX_BASE_IDX 0
258 #define mmSEM_MAILBOX_CONTROL 0x010b
259 #define mmSEM_MAILBOX_CONTROL_BASE_IDX 0
260 #define mmSEM_CHICKEN_BITS 0x010c
261 #define mmSEM_CHICKEN_BITS_BASE_IDX 0
262 #define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA 0x010d
263 #define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA_BASE_IDX 0
264 #define mmSEM_GPU_IOV_VIOLATION_LOG 0x010e
265 #define mmSEM_GPU_IOV_VIOLATION_LOG_BASE_IDX 0
266 #define mmSEM_OUTSTANDING_THRESHOLD 0x010f
267 #define mmSEM_OUTSTANDING_THRESHOLD_BASE_IDX 0
268 #define mmSEM_REGISTER_LAST_PART2 0x017f
269 #define mmSEM_REGISTER_LAST_PART2_BASE_IDX 0
270 #define mmIH_ACTIVE_FCN_ID 0x0180
271 #define mmIH_ACTIVE_FCN_ID_BASE_IDX 0
272 #define mmIH_VIRT_RESET_REQ 0x0181
273 #define mmIH_VIRT_RESET_REQ_BASE_IDX 0
274 #define mmIH_CLIENT_CFG 0x0184
275 #define mmIH_CLIENT_CFG_BASE_IDX 0
276 #define mmIH_CLIENT_CFG_INDEX 0x0188
277 #define mmIH_CLIENT_CFG_INDEX_BASE_IDX 0
278 #define mmIH_CLIENT_CFG_DATA 0x0189
279 #define mmIH_CLIENT_CFG_DATA_BASE_IDX 0
280 #define mmIH_CID_REMAP_INDEX 0x018a
281 #define mmIH_CID_REMAP_INDEX_BASE_IDX 0
282 #define mmIH_CID_REMAP_DATA 0x018b
283 #define mmIH_CID_REMAP_DATA_BASE_IDX 0
284 #define mmIH_CHICKEN 0x018c
285 #define mmIH_CHICKEN_BASE_IDX 0
286 #define mmIH_MMHUB_CNTL 0x018d
287 #define mmIH_MMHUB_CNTL_BASE_IDX 0
288 #define mmIH_REGISTER_LAST_PART1 0x019f
289 #define mmIH_REGISTER_LAST_PART1_BASE_IDX 0
290 #define mmSEM_ACTIVE_FCN_ID 0x01a0
291 #define mmSEM_ACTIVE_FCN_ID_BASE_IDX 0
292 #define mmSEM_VIRT_RESET_REQ 0x01a1
293 #define mmSEM_VIRT_RESET_REQ_BASE_IDX 0
294 #define mmSEM_RESP_SDMA0 0x01a4
295 #define mmSEM_RESP_SDMA0_BASE_IDX 0
296 #define mmSEM_RESP_SDMA1 0x01a5
297 #define mmSEM_RESP_SDMA1_BASE_IDX 0
298 #define mmSEM_RESP_UVD 0x01a6
299 #define mmSEM_RESP_UVD_BASE_IDX 0
300 #define mmSEM_RESP_VCE_0 0x01a7
301 #define mmSEM_RESP_VCE_0_BASE_IDX 0
302 #define mmSEM_RESP_ACP 0x01a8
303 #define mmSEM_RESP_ACP_BASE_IDX 0
304 #define mmSEM_RESP_ISP 0x01a9
305 #define mmSEM_RESP_ISP_BASE_IDX 0
306 #define mmSEM_RESP_VCE_1 0x01aa
307 #define mmSEM_RESP_VCE_1_BASE_IDX 0
308 #define mmSEM_RESP_VP8 0x01ab
309 #define mmSEM_RESP_VP8_BASE_IDX 0
310 #define mmSEM_RESP_GC 0x01ac
311 #define mmSEM_RESP_GC_BASE_IDX 0
312 #define mmSEM_CID_REMAP_INDEX 0x01b0
313 #define mmSEM_CID_REMAP_INDEX_BASE_IDX 0
314 #define mmSEM_CID_REMAP_DATA 0x01b1
315 #define mmSEM_CID_REMAP_DATA_BASE_IDX 0
316 #define mmSEM_ATOMIC_OP_LUT 0x01b2
317 #define mmSEM_ATOMIC_OP_LUT_BASE_IDX 0
318 #define mmSEM_EDC_CONFIG 0x01b3
319 #define mmSEM_EDC_CONFIG_BASE_IDX 0
320 #define mmSEM_CHICKEN_BITS2 0x01b4
321 #define mmSEM_CHICKEN_BITS2_BASE_IDX 0
322 #define mmSEM_MMHUB_CNTL 0x01b5
323 #define mmSEM_MMHUB_CNTL_BASE_IDX 0
324 #define mmSEM_REGISTER_LAST_PART1 0x01bf
325 #define mmSEM_REGISTER_LAST_PART1_BASE_IDX 0
326
327 #endif