root/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h

INCLUDED FROM

   1 /*
   2  * Copyright (C) 2019  Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  */
  21 
  22 #ifndef _vcn_2_5_OFFSET_HEADER
  23 #define _vcn_2_5_OFFSET_HEADER
  24 
  25 // addressBlock: uvd0_mmsch_dec
  26 // base address: 0x1e000
  27 
  28 
  29 // addressBlock: uvd0_jpegnpdec
  30 // base address: 0x1e200
  31 #define mmUVD_JPEG_CNTL                                                                                0x0080
  32 #define mmUVD_JPEG_CNTL_BASE_IDX                                                                       0
  33 #define mmUVD_JPEG_RB_BASE                                                                             0x0081
  34 #define mmUVD_JPEG_RB_BASE_BASE_IDX                                                                    0
  35 #define mmUVD_JPEG_RB_WPTR                                                                             0x0082
  36 #define mmUVD_JPEG_RB_WPTR_BASE_IDX                                                                    0
  37 #define mmUVD_JPEG_RB_RPTR                                                                             0x0083
  38 #define mmUVD_JPEG_RB_RPTR_BASE_IDX                                                                    0
  39 #define mmUVD_JPEG_RB_SIZE                                                                             0x0084
  40 #define mmUVD_JPEG_RB_SIZE_BASE_IDX                                                                    0
  41 #define mmUVD_JPEG_DEC_SCRATCH0                                                                        0x0089
  42 #define mmUVD_JPEG_DEC_SCRATCH0_BASE_IDX                                                               0
  43 #define mmUVD_JPEG_INT_EN                                                                              0x008a
  44 #define mmUVD_JPEG_INT_EN_BASE_IDX                                                                     0
  45 #define mmUVD_JPEG_INT_STAT                                                                            0x008b
  46 #define mmUVD_JPEG_INT_STAT_BASE_IDX                                                                   0
  47 #define mmUVD_JPEG_PITCH                                                                               0x009f
  48 #define mmUVD_JPEG_PITCH_BASE_IDX                                                                      0
  49 #define mmUVD_JPEG_UV_PITCH                                                                            0x00a0
  50 #define mmUVD_JPEG_UV_PITCH_BASE_IDX                                                                   0
  51 #define mmJPEG_DEC_Y_GFX8_TILING_SURFACE                                                               0x00a1
  52 #define mmJPEG_DEC_Y_GFX8_TILING_SURFACE_BASE_IDX                                                      0
  53 #define mmJPEG_DEC_UV_GFX8_TILING_SURFACE                                                              0x00a2
  54 #define mmJPEG_DEC_UV_GFX8_TILING_SURFACE_BASE_IDX                                                     0
  55 #define mmJPEG_DEC_GFX8_ADDR_CONFIG                                                                    0x00a3
  56 #define mmJPEG_DEC_GFX8_ADDR_CONFIG_BASE_IDX                                                           0
  57 #define mmJPEG_DEC_Y_GFX10_TILING_SURFACE                                                              0x00a4
  58 #define mmJPEG_DEC_Y_GFX10_TILING_SURFACE_BASE_IDX                                                     0
  59 #define mmJPEG_DEC_UV_GFX10_TILING_SURFACE                                                             0x00a5
  60 #define mmJPEG_DEC_UV_GFX10_TILING_SURFACE_BASE_IDX                                                    0
  61 #define mmJPEG_DEC_GFX10_ADDR_CONFIG                                                                   0x00a6
  62 #define mmJPEG_DEC_GFX10_ADDR_CONFIG_BASE_IDX                                                          0
  63 #define mmJPEG_DEC_ADDR_MODE                                                                           0x00a7
  64 #define mmJPEG_DEC_ADDR_MODE_BASE_IDX                                                                  0
  65 #define mmUVD_JPEG_GPCOM_CMD                                                                           0x00a9
  66 #define mmUVD_JPEG_GPCOM_CMD_BASE_IDX                                                                  0
  67 #define mmUVD_JPEG_GPCOM_DATA0                                                                         0x00aa
  68 #define mmUVD_JPEG_GPCOM_DATA0_BASE_IDX                                                                0
  69 #define mmUVD_JPEG_GPCOM_DATA1                                                                         0x00ab
  70 #define mmUVD_JPEG_GPCOM_DATA1_BASE_IDX                                                                0
  71 #define mmUVD_JPEG_SCRATCH1                                                                            0x00ae
  72 #define mmUVD_JPEG_SCRATCH1_BASE_IDX                                                                   0
  73 #define mmUVD_JPEG_DEC_SOFT_RST                                                                        0x00af
  74 #define mmUVD_JPEG_DEC_SOFT_RST_BASE_IDX                                                               0
  75 
  76 
  77 // addressBlock: uvd0_uvd_jpeg_enc_dec
  78 // base address: 0x1e300
  79 #define mmUVD_JPEG_ENC_INT_EN                                                                          0x00c1
  80 #define mmUVD_JPEG_ENC_INT_EN_BASE_IDX                                                                 0
  81 #define mmUVD_JPEG_ENC_INT_STATUS                                                                      0x00c2
  82 #define mmUVD_JPEG_ENC_INT_STATUS_BASE_IDX                                                             0
  83 #define mmUVD_JPEG_ENC_ENGINE_CNTL                                                                     0x00c5
  84 #define mmUVD_JPEG_ENC_ENGINE_CNTL_BASE_IDX                                                            0
  85 #define mmUVD_JPEG_ENC_SCRATCH1                                                                        0x00ce
  86 #define mmUVD_JPEG_ENC_SCRATCH1_BASE_IDX                                                               0
  87 
  88 
  89 // addressBlock: uvd0_uvd_jpeg_enc_sclk_dec
  90 // base address: 0x1e380
  91 #define mmUVD_JPEG_ENC_STATUS                                                                          0x00e5
  92 #define mmUVD_JPEG_ENC_STATUS_BASE_IDX                                                                 0
  93 #define mmUVD_JPEG_ENC_PITCH                                                                           0x00e6
  94 #define mmUVD_JPEG_ENC_PITCH_BASE_IDX                                                                  0
  95 #define mmUVD_JPEG_ENC_LUMA_BASE                                                                       0x00e7
  96 #define mmUVD_JPEG_ENC_LUMA_BASE_BASE_IDX                                                              0
  97 #define mmUVD_JPEG_ENC_CHROMAU_BASE                                                                    0x00e8
  98 #define mmUVD_JPEG_ENC_CHROMAU_BASE_BASE_IDX                                                           0
  99 #define mmUVD_JPEG_ENC_CHROMAV_BASE                                                                    0x00e9
 100 #define mmUVD_JPEG_ENC_CHROMAV_BASE_BASE_IDX                                                           0
 101 #define mmJPEG_ENC_Y_GFX10_TILING_SURFACE                                                              0x00ea
 102 #define mmJPEG_ENC_Y_GFX10_TILING_SURFACE_BASE_IDX                                                     0
 103 #define mmJPEG_ENC_UV_GFX10_TILING_SURFACE                                                             0x00eb
 104 #define mmJPEG_ENC_UV_GFX10_TILING_SURFACE_BASE_IDX                                                    0
 105 #define mmJPEG_ENC_GFX10_ADDR_CONFIG                                                                   0x00ec
 106 #define mmJPEG_ENC_GFX10_ADDR_CONFIG_BASE_IDX                                                          0
 107 #define mmJPEG_ENC_ADDR_MODE                                                                           0x00ed
 108 #define mmJPEG_ENC_ADDR_MODE_BASE_IDX                                                                  0
 109 #define mmUVD_JPEG_ENC_GPCOM_CMD                                                                       0x00ee
 110 #define mmUVD_JPEG_ENC_GPCOM_CMD_BASE_IDX                                                              0
 111 #define mmUVD_JPEG_ENC_GPCOM_DATA0                                                                     0x00ef
 112 #define mmUVD_JPEG_ENC_GPCOM_DATA0_BASE_IDX                                                            0
 113 #define mmUVD_JPEG_ENC_GPCOM_DATA1                                                                     0x00f0
 114 #define mmUVD_JPEG_ENC_GPCOM_DATA1_BASE_IDX                                                            0
 115 #define mmUVD_JPEG_ENC_CGC_CNTL                                                                        0x00f5
 116 #define mmUVD_JPEG_ENC_CGC_CNTL_BASE_IDX                                                               0
 117 #define mmUVD_JPEG_ENC_SCRATCH0                                                                        0x00f6
 118 #define mmUVD_JPEG_ENC_SCRATCH0_BASE_IDX                                                               0
 119 #define mmUVD_JPEG_ENC_SOFT_RST                                                                        0x00f7
 120 #define mmUVD_JPEG_ENC_SOFT_RST_BASE_IDX                                                               0
 121 
 122 
 123 // addressBlock: uvd0_uvd_jrbc_dec
 124 // base address: 0x1e400
 125 #define mmUVD_JRBC_RB_WPTR                                                                             0x0100
 126 #define mmUVD_JRBC_RB_WPTR_BASE_IDX                                                                    0
 127 #define mmUVD_JRBC_RB_CNTL                                                                             0x0101
 128 #define mmUVD_JRBC_RB_CNTL_BASE_IDX                                                                    0
 129 #define mmUVD_JRBC_IB_SIZE                                                                             0x0102
 130 #define mmUVD_JRBC_IB_SIZE_BASE_IDX                                                                    0
 131 #define mmUVD_JRBC_URGENT_CNTL                                                                         0x0103
 132 #define mmUVD_JRBC_URGENT_CNTL_BASE_IDX                                                                0
 133 #define mmUVD_JRBC_RB_REF_DATA                                                                         0x0104
 134 #define mmUVD_JRBC_RB_REF_DATA_BASE_IDX                                                                0
 135 #define mmUVD_JRBC_RB_COND_RD_TIMER                                                                    0x0105
 136 #define mmUVD_JRBC_RB_COND_RD_TIMER_BASE_IDX                                                           0
 137 #define mmUVD_JRBC_SOFT_RESET                                                                          0x0108
 138 #define mmUVD_JRBC_SOFT_RESET_BASE_IDX                                                                 0
 139 #define mmUVD_JRBC_STATUS                                                                              0x0109
 140 #define mmUVD_JRBC_STATUS_BASE_IDX                                                                     0
 141 #define mmUVD_JRBC_RB_RPTR                                                                             0x010a
 142 #define mmUVD_JRBC_RB_RPTR_BASE_IDX                                                                    0
 143 #define mmUVD_JRBC_RB_BUF_STATUS                                                                       0x010b
 144 #define mmUVD_JRBC_RB_BUF_STATUS_BASE_IDX                                                              0
 145 #define mmUVD_JRBC_IB_BUF_STATUS                                                                       0x010c
 146 #define mmUVD_JRBC_IB_BUF_STATUS_BASE_IDX                                                              0
 147 #define mmUVD_JRBC_IB_SIZE_UPDATE                                                                      0x010d
 148 #define mmUVD_JRBC_IB_SIZE_UPDATE_BASE_IDX                                                             0
 149 #define mmUVD_JRBC_IB_COND_RD_TIMER                                                                    0x010e
 150 #define mmUVD_JRBC_IB_COND_RD_TIMER_BASE_IDX                                                           0
 151 #define mmUVD_JRBC_IB_REF_DATA                                                                         0x010f
 152 #define mmUVD_JRBC_IB_REF_DATA_BASE_IDX                                                                0
 153 #define mmUVD_JPEG_PREEMPT_CMD                                                                         0x0110
 154 #define mmUVD_JPEG_PREEMPT_CMD_BASE_IDX                                                                0
 155 #define mmUVD_JPEG_PREEMPT_FENCE_DATA0                                                                 0x0111
 156 #define mmUVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX                                                        0
 157 #define mmUVD_JPEG_PREEMPT_FENCE_DATA1                                                                 0x0112
 158 #define mmUVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX                                                        0
 159 #define mmUVD_JRBC_RB_SIZE                                                                             0x0113
 160 #define mmUVD_JRBC_RB_SIZE_BASE_IDX                                                                    0
 161 #define mmUVD_JRBC_SCRATCH0                                                                            0x0114
 162 #define mmUVD_JRBC_SCRATCH0_BASE_IDX                                                                   0
 163 
 164 
 165 // addressBlock: uvd0_uvd_jrbc_enc_dec
 166 // base address: 0x1e480
 167 #define mmUVD_JRBC_ENC_RB_WPTR                                                                         0x0120
 168 #define mmUVD_JRBC_ENC_RB_WPTR_BASE_IDX                                                                0
 169 #define mmUVD_JRBC_ENC_RB_CNTL                                                                         0x0121
 170 #define mmUVD_JRBC_ENC_RB_CNTL_BASE_IDX                                                                0
 171 #define mmUVD_JRBC_ENC_IB_SIZE                                                                         0x0122
 172 #define mmUVD_JRBC_ENC_IB_SIZE_BASE_IDX                                                                0
 173 #define mmUVD_JRBC_ENC_URGENT_CNTL                                                                     0x0123
 174 #define mmUVD_JRBC_ENC_URGENT_CNTL_BASE_IDX                                                            0
 175 #define mmUVD_JRBC_ENC_RB_REF_DATA                                                                     0x0124
 176 #define mmUVD_JRBC_ENC_RB_REF_DATA_BASE_IDX                                                            0
 177 #define mmUVD_JRBC_ENC_RB_COND_RD_TIMER                                                                0x0125
 178 #define mmUVD_JRBC_ENC_RB_COND_RD_TIMER_BASE_IDX                                                       0
 179 #define mmUVD_JRBC_ENC_SOFT_RESET                                                                      0x0128
 180 #define mmUVD_JRBC_ENC_SOFT_RESET_BASE_IDX                                                             0
 181 #define mmUVD_JRBC_ENC_STATUS                                                                          0x0129
 182 #define mmUVD_JRBC_ENC_STATUS_BASE_IDX                                                                 0
 183 #define mmUVD_JRBC_ENC_RB_RPTR                                                                         0x012a
 184 #define mmUVD_JRBC_ENC_RB_RPTR_BASE_IDX                                                                0
 185 #define mmUVD_JRBC_ENC_RB_BUF_STATUS                                                                   0x012b
 186 #define mmUVD_JRBC_ENC_RB_BUF_STATUS_BASE_IDX                                                          0
 187 #define mmUVD_JRBC_ENC_IB_BUF_STATUS                                                                   0x012c
 188 #define mmUVD_JRBC_ENC_IB_BUF_STATUS_BASE_IDX                                                          0
 189 #define mmUVD_JRBC_ENC_IB_SIZE_UPDATE                                                                  0x012d
 190 #define mmUVD_JRBC_ENC_IB_SIZE_UPDATE_BASE_IDX                                                         0
 191 #define mmUVD_JRBC_ENC_IB_COND_RD_TIMER                                                                0x012e
 192 #define mmUVD_JRBC_ENC_IB_COND_RD_TIMER_BASE_IDX                                                       0
 193 #define mmUVD_JRBC_ENC_IB_REF_DATA                                                                     0x012f
 194 #define mmUVD_JRBC_ENC_IB_REF_DATA_BASE_IDX                                                            0
 195 #define mmUVD_JPEG_ENC_PREEMPT_CMD                                                                     0x0130
 196 #define mmUVD_JPEG_ENC_PREEMPT_CMD_BASE_IDX                                                            0
 197 #define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA0                                                             0x0131
 198 #define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA0_BASE_IDX                                                    0
 199 #define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA1                                                             0x0132
 200 #define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA1_BASE_IDX                                                    0
 201 #define mmUVD_JRBC_ENC_RB_SIZE                                                                         0x0133
 202 #define mmUVD_JRBC_ENC_RB_SIZE_BASE_IDX                                                                0
 203 #define mmUVD_JRBC_ENC_SCRATCH0                                                                        0x0134
 204 #define mmUVD_JRBC_ENC_SCRATCH0_BASE_IDX                                                               0
 205 
 206 
 207 // addressBlock: uvd0_uvd_jmi_dec
 208 // base address: 0x1e500
 209 #define mmUVD_JMI_CTRL                                                                                 0x0145
 210 #define mmUVD_JMI_CTRL_BASE_IDX                                                                        0
 211 #define mmUVD_LMI_JRBC_CTRL                                                                            0x0146
 212 #define mmUVD_LMI_JRBC_CTRL_BASE_IDX                                                                   0
 213 #define mmUVD_LMI_JPEG_CTRL                                                                            0x0147
 214 #define mmUVD_LMI_JPEG_CTRL_BASE_IDX                                                                   0
 215 #define mmUVD_JMI_EJRBC_CTRL                                                                           0x0148
 216 #define mmUVD_JMI_EJRBC_CTRL_BASE_IDX                                                                  0
 217 #define mmUVD_LMI_EJPEG_CTRL                                                                           0x0149
 218 #define mmUVD_LMI_EJPEG_CTRL_BASE_IDX                                                                  0
 219 #define mmUVD_LMI_JRBC_IB_VMID                                                                         0x014f
 220 #define mmUVD_LMI_JRBC_IB_VMID_BASE_IDX                                                                0
 221 #define mmUVD_LMI_JRBC_RB_VMID                                                                         0x0150
 222 #define mmUVD_LMI_JRBC_RB_VMID_BASE_IDX                                                                0
 223 #define mmUVD_LMI_JPEG_VMID                                                                            0x0151
 224 #define mmUVD_LMI_JPEG_VMID_BASE_IDX                                                                   0
 225 #define mmUVD_JMI_ENC_JRBC_IB_VMID                                                                     0x0152
 226 #define mmUVD_JMI_ENC_JRBC_IB_VMID_BASE_IDX                                                            0
 227 #define mmUVD_JMI_ENC_JRBC_RB_VMID                                                                     0x0153
 228 #define mmUVD_JMI_ENC_JRBC_RB_VMID_BASE_IDX                                                            0
 229 #define mmUVD_JMI_ENC_JPEG_VMID                                                                        0x0154
 230 #define mmUVD_JMI_ENC_JPEG_VMID_BASE_IDX                                                               0
 231 #define mmUVD_JMI_PERFMON_CTRL                                                                         0x015c
 232 #define mmUVD_JMI_PERFMON_CTRL_BASE_IDX                                                                0
 233 #define mmUVD_JMI_PERFMON_COUNT_LO                                                                     0x015d
 234 #define mmUVD_JMI_PERFMON_COUNT_LO_BASE_IDX                                                            0
 235 #define mmUVD_JMI_PERFMON_COUNT_HI                                                                     0x015e
 236 #define mmUVD_JMI_PERFMON_COUNT_HI_BASE_IDX                                                            0
 237 #define mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW                                                              0x0160
 238 #define mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX                                                     0
 239 #define mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH                                                             0x0161
 240 #define mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX                                                    0
 241 #define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW                                                             0x0162
 242 #define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX                                                    0
 243 #define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH                                                            0x0163
 244 #define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX                                                   0
 245 #define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW                                                     0x0164
 246 #define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX                                            0
 247 #define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH                                                    0x0165
 248 #define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX                                           0
 249 #define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW                                                                0x0166
 250 #define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX                                                       0
 251 #define mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH                                                               0x0167
 252 #define mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX                                                      0
 253 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW                                                                0x0168
 254 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX                                                       0
 255 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH                                                               0x0169
 256 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX                                                      0
 257 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW                                                         0x016a
 258 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX                                                0
 259 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH                                                        0x016b
 260 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX                                               0
 261 #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW                                                         0x016c
 262 #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX                                                0
 263 #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH                                                        0x016d
 264 #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX                                               0
 265 #define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW                                                         0x016e
 266 #define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX                                                0
 267 #define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH                                                        0x016f
 268 #define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX                                               0
 269 #define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW                                                         0x0170
 270 #define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW_BASE_IDX                                                0
 271 #define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH                                                        0x0171
 272 #define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX                                               0
 273 #define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW                                                    0x017a
 274 #define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX                                           0
 275 #define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH                                                   0x017b
 276 #define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX                                          0
 277 #define mmUVD_LMI_EJRBC_RB_64BIT_BAR_LOW                                                               0x017c
 278 #define mmUVD_LMI_EJRBC_RB_64BIT_BAR_LOW_BASE_IDX                                                      0
 279 #define mmUVD_LMI_EJRBC_RB_64BIT_BAR_HIGH                                                              0x017d
 280 #define mmUVD_LMI_EJRBC_RB_64BIT_BAR_HIGH_BASE_IDX                                                     0
 281 #define mmUVD_LMI_EJRBC_IB_64BIT_BAR_LOW                                                               0x017e
 282 #define mmUVD_LMI_EJRBC_IB_64BIT_BAR_LOW_BASE_IDX                                                      0
 283 #define mmUVD_LMI_EJRBC_IB_64BIT_BAR_HIGH                                                              0x017f
 284 #define mmUVD_LMI_EJRBC_IB_64BIT_BAR_HIGH_BASE_IDX                                                     0
 285 #define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW                                                        0x0180
 286 #define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX                                               0
 287 #define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH                                                       0x0181
 288 #define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX                                              0
 289 #define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW                                                        0x0182
 290 #define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX                                               0
 291 #define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH                                                       0x0183
 292 #define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX                                              0
 293 #define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW                                                        0x0184
 294 #define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX                                               0
 295 #define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH                                                       0x0185
 296 #define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX                                              0
 297 #define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW                                                        0x0186
 298 #define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW_BASE_IDX                                               0
 299 #define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH                                                       0x0187
 300 #define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX                                              0
 301 #define mmUVD_LMI_JPEG_PREEMPT_VMID                                                                    0x0188
 302 #define mmUVD_LMI_JPEG_PREEMPT_VMID_BASE_IDX                                                           0
 303 #define mmUVD_LMI_ENC_JPEG_PREEMPT_VMID                                                                0x0189
 304 #define mmUVD_LMI_ENC_JPEG_PREEMPT_VMID_BASE_IDX                                                       0
 305 #define mmUVD_LMI_JPEG2_VMID                                                                           0x018a
 306 #define mmUVD_LMI_JPEG2_VMID_BASE_IDX                                                                  0
 307 #define mmUVD_LMI_JPEG2_READ_64BIT_BAR_LOW                                                             0x018b
 308 #define mmUVD_LMI_JPEG2_READ_64BIT_BAR_LOW_BASE_IDX                                                    0
 309 #define mmUVD_LMI_JPEG2_READ_64BIT_BAR_HIGH                                                            0x018c
 310 #define mmUVD_LMI_JPEG2_READ_64BIT_BAR_HIGH_BASE_IDX                                                   0
 311 #define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW                                                            0x018d
 312 #define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW_BASE_IDX                                                   0
 313 #define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH                                                           0x018e
 314 #define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH_BASE_IDX                                                  0
 315 #define mmUVD_LMI_JPEG_CTRL2                                                                           0x018f
 316 #define mmUVD_LMI_JPEG_CTRL2_BASE_IDX                                                                  0
 317 #define mmUVD_JMI_DEC_SWAP_CNTL                                                                        0x0190
 318 #define mmUVD_JMI_DEC_SWAP_CNTL_BASE_IDX                                                               0
 319 #define mmUVD_JMI_ENC_SWAP_CNTL                                                                        0x0191
 320 #define mmUVD_JMI_ENC_SWAP_CNTL_BASE_IDX                                                               0
 321 #define mmUVD_JMI_CNTL                                                                                 0x0192
 322 #define mmUVD_JMI_CNTL_BASE_IDX                                                                        0
 323 #define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_LOW                                                             0x019a
 324 #define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_LOW_BASE_IDX                                                    0
 325 #define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH                                                            0x019b
 326 #define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH_BASE_IDX                                                   0
 327 #define mmUVD_JMI_DEC_SWAP_CNTL2                                                                       0x019c
 328 #define mmUVD_JMI_DEC_SWAP_CNTL2_BASE_IDX                                                              0
 329 
 330 
 331 // addressBlock: uvd0_uvd_jpeg_common_dec
 332 // base address: 0x1e700
 333 #define mmJPEG_SOFT_RESET_STATUS                                                                       0x01c0
 334 #define mmJPEG_SOFT_RESET_STATUS_BASE_IDX                                                              0
 335 #define mmJPEG_SYS_INT_EN                                                                              0x01c1
 336 #define mmJPEG_SYS_INT_EN_BASE_IDX                                                                     0
 337 #define mmJPEG_SYS_INT_STATUS                                                                          0x01c2
 338 #define mmJPEG_SYS_INT_STATUS_BASE_IDX                                                                 0
 339 #define mmJPEG_SYS_INT_ACK                                                                             0x01c3
 340 #define mmJPEG_SYS_INT_ACK_BASE_IDX                                                                    0
 341 #define mmJPEG_MASTINT_EN                                                                              0x01c8
 342 #define mmJPEG_MASTINT_EN_BASE_IDX                                                                     0
 343 #define mmJPEG_IH_CTRL                                                                                 0x01c9
 344 #define mmJPEG_IH_CTRL_BASE_IDX                                                                        0
 345 #define mmJRBBM_ARB_CTRL                                                                               0x01cb
 346 #define mmJRBBM_ARB_CTRL_BASE_IDX                                                                      0
 347 
 348 
 349 // addressBlock: uvd0_uvd_jpeg_common_sclk_dec
 350 // base address: 0x1e780
 351 #define mmJPEG_CGC_GATE                                                                                0x01e0
 352 #define mmJPEG_CGC_GATE_BASE_IDX                                                                       0
 353 #define mmJPEG_CGC_CTRL                                                                                0x01e1
 354 #define mmJPEG_CGC_CTRL_BASE_IDX                                                                       0
 355 #define mmJPEG_CGC_STATUS                                                                              0x01e2
 356 #define mmJPEG_CGC_STATUS_BASE_IDX                                                                     0
 357 #define mmJPEG_COMN_CGC_MEM_CTRL                                                                       0x01e3
 358 #define mmJPEG_COMN_CGC_MEM_CTRL_BASE_IDX                                                              0
 359 #define mmJPEG_DEC_CGC_MEM_CTRL                                                                        0x01e4
 360 #define mmJPEG_DEC_CGC_MEM_CTRL_BASE_IDX                                                               0
 361 #define mmJPEG2_DEC_CGC_MEM_CTRL                                                                       0x01e5
 362 #define mmJPEG2_DEC_CGC_MEM_CTRL_BASE_IDX                                                              0
 363 #define mmJPEG_ENC_CGC_MEM_CTRL                                                                        0x01e6
 364 #define mmJPEG_ENC_CGC_MEM_CTRL_BASE_IDX                                                               0
 365 #define mmJPEG_SOFT_RESET2                                                                             0x01e7
 366 #define mmJPEG_SOFT_RESET2_BASE_IDX                                                                    0
 367 #define mmJPEG_PERF_BANK_CONF                                                                          0x01e8
 368 #define mmJPEG_PERF_BANK_CONF_BASE_IDX                                                                 0
 369 #define mmJPEG_PERF_BANK_EVENT_SEL                                                                     0x01e9
 370 #define mmJPEG_PERF_BANK_EVENT_SEL_BASE_IDX                                                            0
 371 #define mmJPEG_PERF_BANK_COUNT0                                                                        0x01ea
 372 #define mmJPEG_PERF_BANK_COUNT0_BASE_IDX                                                               0
 373 #define mmJPEG_PERF_BANK_COUNT1                                                                        0x01eb
 374 #define mmJPEG_PERF_BANK_COUNT1_BASE_IDX                                                               0
 375 #define mmJPEG_PERF_BANK_COUNT2                                                                        0x01ec
 376 #define mmJPEG_PERF_BANK_COUNT2_BASE_IDX                                                               0
 377 #define mmJPEG_PERF_BANK_COUNT3                                                                        0x01ed
 378 #define mmJPEG_PERF_BANK_COUNT3_BASE_IDX                                                               0
 379 
 380 
 381 // addressBlock: uvd0_uvd_pg_dec
 382 // base address: 0x1f800
 383 #define mmUVD_PGFSM_CONFIG                                                                             0x0000
 384 #define mmUVD_PGFSM_CONFIG_BASE_IDX                                                                    1
 385 #define mmUVD_PGFSM_STATUS                                                                             0x0001
 386 #define mmUVD_PGFSM_STATUS_BASE_IDX                                                                    1
 387 #define mmUVD_POWER_STATUS                                                                             0x0004
 388 #define mmUVD_POWER_STATUS_BASE_IDX                                                                    1
 389 #define mmUVD_PG_IND_INDEX                                                                             0x0005
 390 #define mmUVD_PG_IND_INDEX_BASE_IDX                                                                    1
 391 #define mmUVD_PG_IND_DATA                                                                              0x0006
 392 #define mmUVD_PG_IND_DATA_BASE_IDX                                                                     1
 393 #define mmCC_UVD_HARVESTING                                                                            0x0007
 394 #define mmCC_UVD_HARVESTING_BASE_IDX                                                                   1
 395 #define mmUVD_JPEG_POWER_STATUS                                                                        0x000a
 396 #define mmUVD_JPEG_POWER_STATUS_BASE_IDX                                                               1
 397 #define mmUVD_DPG_LMA_CTL                                                                              0x0011
 398 #define mmUVD_DPG_LMA_CTL_BASE_IDX                                                                     1
 399 #define mmUVD_DPG_LMA_DATA                                                                             0x0012
 400 #define mmUVD_DPG_LMA_DATA_BASE_IDX                                                                    1
 401 #define mmUVD_DPG_LMA_MASK                                                                             0x0013
 402 #define mmUVD_DPG_LMA_MASK_BASE_IDX                                                                    1
 403 #define mmUVD_DPG_PAUSE                                                                                0x0014
 404 #define mmUVD_DPG_PAUSE_BASE_IDX                                                                       1
 405 #define mmUVD_SCRATCH1                                                                                 0x0015
 406 #define mmUVD_SCRATCH1_BASE_IDX                                                                        1
 407 #define mmUVD_SCRATCH2                                                                                 0x0016
 408 #define mmUVD_SCRATCH2_BASE_IDX                                                                        1
 409 #define mmUVD_SCRATCH3                                                                                 0x0017
 410 #define mmUVD_SCRATCH3_BASE_IDX                                                                        1
 411 #define mmUVD_SCRATCH4                                                                                 0x0018
 412 #define mmUVD_SCRATCH4_BASE_IDX                                                                        1
 413 #define mmUVD_SCRATCH5                                                                                 0x0019
 414 #define mmUVD_SCRATCH5_BASE_IDX                                                                        1
 415 #define mmUVD_SCRATCH6                                                                                 0x001a
 416 #define mmUVD_SCRATCH6_BASE_IDX                                                                        1
 417 #define mmUVD_SCRATCH7                                                                                 0x001b
 418 #define mmUVD_SCRATCH7_BASE_IDX                                                                        1
 419 #define mmUVD_SCRATCH8                                                                                 0x001c
 420 #define mmUVD_SCRATCH8_BASE_IDX                                                                        1
 421 #define mmUVD_SCRATCH9                                                                                 0x001d
 422 #define mmUVD_SCRATCH9_BASE_IDX                                                                        1
 423 #define mmUVD_SCRATCH10                                                                                0x001e
 424 #define mmUVD_SCRATCH10_BASE_IDX                                                                       1
 425 #define mmUVD_SCRATCH11                                                                                0x001f
 426 #define mmUVD_SCRATCH11_BASE_IDX                                                                       1
 427 #define mmUVD_SCRATCH12                                                                                0x0020
 428 #define mmUVD_SCRATCH12_BASE_IDX                                                                       1
 429 #define mmUVD_SCRATCH13                                                                                0x0021
 430 #define mmUVD_SCRATCH13_BASE_IDX                                                                       1
 431 #define mmUVD_SCRATCH14                                                                                0x0022
 432 #define mmUVD_SCRATCH14_BASE_IDX                                                                       1
 433 #define mmUVD_FREE_COUNTER_REG                                                                         0x0024
 434 #define mmUVD_FREE_COUNTER_REG_BASE_IDX                                                                1
 435 #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW                                                         0x0025
 436 #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX                                                1
 437 #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH                                                        0x0026
 438 #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX                                               1
 439 #define mmUVD_DPG_VCPU_CACHE_OFFSET0                                                                   0x0027
 440 #define mmUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX                                                          1
 441 #define mmUVD_DPG_LMI_VCPU_CACHE_VMID                                                                  0x0028
 442 #define mmUVD_DPG_LMI_VCPU_CACHE_VMID_BASE_IDX                                                         1
 443 #define mmUVD_PF_STATUS                                                                                0x0039
 444 #define mmUVD_PF_STATUS_BASE_IDX                                                                       1
 445 #define mmUVD_DPG_CLK_EN_VCPU_REPORT                                                                   0x003c
 446 #define mmUVD_DPG_CLK_EN_VCPU_REPORT_BASE_IDX                                                          1
 447 #define mmUVD_GFX8_ADDR_CONFIG                                                                         0x0049
 448 #define mmUVD_GFX8_ADDR_CONFIG_BASE_IDX                                                                1
 449 #define mmUVD_GFX10_ADDR_CONFIG                                                                        0x004a
 450 #define mmUVD_GFX10_ADDR_CONFIG_BASE_IDX                                                               1
 451 #define mmUVD_GPCNT2_CNTL                                                                              0x004b
 452 #define mmUVD_GPCNT2_CNTL_BASE_IDX                                                                     1
 453 #define mmUVD_GPCNT2_TARGET_LOWER                                                                      0x004c
 454 #define mmUVD_GPCNT2_TARGET_LOWER_BASE_IDX                                                             1
 455 #define mmUVD_GPCNT2_STATUS_LOWER                                                                      0x004d
 456 #define mmUVD_GPCNT2_STATUS_LOWER_BASE_IDX                                                             1
 457 #define mmUVD_GPCNT2_TARGET_UPPER                                                                      0x004e
 458 #define mmUVD_GPCNT2_TARGET_UPPER_BASE_IDX                                                             1
 459 #define mmUVD_GPCNT2_STATUS_UPPER                                                                      0x004f
 460 #define mmUVD_GPCNT2_STATUS_UPPER_BASE_IDX                                                             1
 461 #define mmUVD_GPCNT3_CNTL                                                                              0x0050
 462 #define mmUVD_GPCNT3_CNTL_BASE_IDX                                                                     1
 463 #define mmUVD_GPCNT3_TARGET_LOWER                                                                      0x0051
 464 #define mmUVD_GPCNT3_TARGET_LOWER_BASE_IDX                                                             1
 465 #define mmUVD_GPCNT3_STATUS_LOWER                                                                      0x0052
 466 #define mmUVD_GPCNT3_STATUS_LOWER_BASE_IDX                                                             1
 467 #define mmUVD_GPCNT3_TARGET_UPPER                                                                      0x0053
 468 #define mmUVD_GPCNT3_TARGET_UPPER_BASE_IDX                                                             1
 469 #define mmUVD_GPCNT3_STATUS_UPPER                                                                      0x0054
 470 #define mmUVD_GPCNT3_STATUS_UPPER_BASE_IDX                                                             1
 471 
 472 
 473 // addressBlock: uvd0_uvddec
 474 // base address: 0x1fa00
 475 #define mmUVD_STATUS                                                                                   0x0080
 476 #define mmUVD_STATUS_BASE_IDX                                                                          1
 477 #define mmUVD_ENC_PIPE_BUSY                                                                            0x0081
 478 #define mmUVD_ENC_PIPE_BUSY_BASE_IDX                                                                   1
 479 #define mmUVD_SOFT_RESET                                                                               0x0084
 480 #define mmUVD_SOFT_RESET_BASE_IDX                                                                      1
 481 #define mmUVD_SOFT_RESET2                                                                              0x0085
 482 #define mmUVD_SOFT_RESET2_BASE_IDX                                                                     1
 483 #define mmUVD_MMSCH_SOFT_RESET                                                                         0x0086
 484 #define mmUVD_MMSCH_SOFT_RESET_BASE_IDX                                                                1
 485 #define mmUVD_CGC_GATE                                                                                 0x0088
 486 #define mmUVD_CGC_GATE_BASE_IDX                                                                        1
 487 #define mmUVD_CGC_STATUS                                                                               0x0089
 488 #define mmUVD_CGC_STATUS_BASE_IDX                                                                      1
 489 #define mmUVD_CGC_CTRL                                                                                 0x008a
 490 #define mmUVD_CGC_CTRL_BASE_IDX                                                                        1
 491 #define mmUVD_CGC_UDEC_STATUS                                                                          0x008b
 492 #define mmUVD_CGC_UDEC_STATUS_BASE_IDX                                                                 1
 493 #define mmUVD_SUVD_CGC_GATE                                                                            0x008c
 494 #define mmUVD_SUVD_CGC_GATE_BASE_IDX                                                                   1
 495 #define mmUVD_SUVD_CGC_STATUS                                                                          0x008d
 496 #define mmUVD_SUVD_CGC_STATUS_BASE_IDX                                                                 1
 497 #define mmUVD_SUVD_CGC_CTRL                                                                            0x008e
 498 #define mmUVD_SUVD_CGC_CTRL_BASE_IDX                                                                   1
 499 #define mmUVD_GPCOM_VCPU_CMD                                                                           0x008f
 500 #define mmUVD_GPCOM_VCPU_CMD_BASE_IDX                                                                  1
 501 #define mmUVD_GPCOM_VCPU_DATA0                                                                         0x0090
 502 #define mmUVD_GPCOM_VCPU_DATA0_BASE_IDX                                                                1
 503 #define mmUVD_GPCOM_VCPU_DATA1                                                                         0x0091
 504 #define mmUVD_GPCOM_VCPU_DATA1_BASE_IDX                                                                1
 505 #define mmUVD_GPCOM_SYS_CMD                                                                            0x0092
 506 #define mmUVD_GPCOM_SYS_CMD_BASE_IDX                                                                   1
 507 #define mmUVD_GPCOM_SYS_DATA0                                                                          0x0093
 508 #define mmUVD_GPCOM_SYS_DATA0_BASE_IDX                                                                 1
 509 #define mmUVD_GPCOM_SYS_DATA1                                                                          0x0094
 510 #define mmUVD_GPCOM_SYS_DATA1_BASE_IDX                                                                 1
 511 #define mmUVD_VCPU_INT_EN                                                                              0x0095
 512 #define mmUVD_VCPU_INT_EN_BASE_IDX                                                                     1
 513 #define mmUVD_VCPU_INT_ACK                                                                             0x0097
 514 #define mmUVD_VCPU_INT_ACK_BASE_IDX                                                                    1
 515 #define mmUVD_VCPU_INT_ROUTE                                                                           0x0098
 516 #define mmUVD_VCPU_INT_ROUTE_BASE_IDX                                                                  1
 517 #define mmUVD_ENC_VCPU_INT_EN                                                                          0x009e
 518 #define mmUVD_ENC_VCPU_INT_EN_BASE_IDX                                                                 1
 519 #define mmUVD_ENC_VCPU_INT_ACK                                                                         0x00a0
 520 #define mmUVD_ENC_VCPU_INT_ACK_BASE_IDX                                                                1
 521 #define mmUVD_MASTINT_EN                                                                               0x00a1
 522 #define mmUVD_MASTINT_EN_BASE_IDX                                                                      1
 523 #define mmUVD_SYS_INT_EN                                                                               0x00a2
 524 #define mmUVD_SYS_INT_EN_BASE_IDX                                                                      1
 525 #define mmUVD_SYS_INT_STATUS                                                                           0x00a3
 526 #define mmUVD_SYS_INT_STATUS_BASE_IDX                                                                  1
 527 #define mmUVD_SYS_INT_ACK                                                                              0x00a4
 528 #define mmUVD_SYS_INT_ACK_BASE_IDX                                                                     1
 529 #define mmUVD_JOB_DONE                                                                                 0x00a5
 530 #define mmUVD_JOB_DONE_BASE_IDX                                                                        1
 531 #define mmUVD_CBUF_ID                                                                                  0x00a6
 532 #define mmUVD_CBUF_ID_BASE_IDX                                                                         1
 533 #define mmUVD_CONTEXT_ID                                                                               0x00a7
 534 #define mmUVD_CONTEXT_ID_BASE_IDX                                                                      1
 535 #define mmUVD_CONTEXT_ID2                                                                              0x00a8
 536 #define mmUVD_CONTEXT_ID2_BASE_IDX                                                                     1
 537 #define mmUVD_NO_OP                                                                                    0x00a9
 538 #define mmUVD_NO_OP_BASE_IDX                                                                           1
 539 #define mmUVD_RB_BASE_LO                                                                               0x00aa
 540 #define mmUVD_RB_BASE_LO_BASE_IDX                                                                      1
 541 #define mmUVD_RB_BASE_HI                                                                               0x00ab
 542 #define mmUVD_RB_BASE_HI_BASE_IDX                                                                      1
 543 #define mmUVD_RB_SIZE                                                                                  0x00ac
 544 #define mmUVD_RB_SIZE_BASE_IDX                                                                         1
 545 #define mmUVD_RB_RPTR                                                                                  0x00ad
 546 #define mmUVD_RB_RPTR_BASE_IDX                                                                         1
 547 #define mmUVD_RB_WPTR                                                                                  0x00ae
 548 #define mmUVD_RB_WPTR_BASE_IDX                                                                         1
 549 #define mmUVD_RB_BASE_LO2                                                                              0x00af
 550 #define mmUVD_RB_BASE_LO2_BASE_IDX                                                                     1
 551 #define mmUVD_RB_BASE_HI2                                                                              0x00b0
 552 #define mmUVD_RB_BASE_HI2_BASE_IDX                                                                     1
 553 #define mmUVD_RB_SIZE2                                                                                 0x00b1
 554 #define mmUVD_RB_SIZE2_BASE_IDX                                                                        1
 555 #define mmUVD_RB_RPTR2                                                                                 0x00b2
 556 #define mmUVD_RB_RPTR2_BASE_IDX                                                                        1
 557 #define mmUVD_RB_WPTR2                                                                                 0x00b3
 558 #define mmUVD_RB_WPTR2_BASE_IDX                                                                        1
 559 #define mmUVD_RB_BASE_LO3                                                                              0x00b4
 560 #define mmUVD_RB_BASE_LO3_BASE_IDX                                                                     1
 561 #define mmUVD_RB_BASE_HI3                                                                              0x00b5
 562 #define mmUVD_RB_BASE_HI3_BASE_IDX                                                                     1
 563 #define mmUVD_RB_SIZE3                                                                                 0x00b6
 564 #define mmUVD_RB_SIZE3_BASE_IDX                                                                        1
 565 #define mmUVD_RB_RPTR3                                                                                 0x00b7
 566 #define mmUVD_RB_RPTR3_BASE_IDX                                                                        1
 567 #define mmUVD_RB_WPTR3                                                                                 0x00b8
 568 #define mmUVD_RB_WPTR3_BASE_IDX                                                                        1
 569 #define mmUVD_RB_BASE_LO4                                                                              0x00b9
 570 #define mmUVD_RB_BASE_LO4_BASE_IDX                                                                     1
 571 #define mmUVD_RB_BASE_HI4                                                                              0x00ba
 572 #define mmUVD_RB_BASE_HI4_BASE_IDX                                                                     1
 573 #define mmUVD_RB_SIZE4                                                                                 0x00bb
 574 #define mmUVD_RB_SIZE4_BASE_IDX                                                                        1
 575 #define mmUVD_RB_RPTR4                                                                                 0x00bc
 576 #define mmUVD_RB_RPTR4_BASE_IDX                                                                        1
 577 #define mmUVD_RB_WPTR4                                                                                 0x00bd
 578 #define mmUVD_RB_WPTR4_BASE_IDX                                                                        1
 579 #define mmUVD_OUT_RB_BASE_LO                                                                           0x00be
 580 #define mmUVD_OUT_RB_BASE_LO_BASE_IDX                                                                  1
 581 #define mmUVD_OUT_RB_BASE_HI                                                                           0x00bf
 582 #define mmUVD_OUT_RB_BASE_HI_BASE_IDX                                                                  1
 583 #define mmUVD_OUT_RB_SIZE                                                                              0x00c0
 584 #define mmUVD_OUT_RB_SIZE_BASE_IDX                                                                     1
 585 #define mmUVD_OUT_RB_RPTR                                                                              0x00c1
 586 #define mmUVD_OUT_RB_RPTR_BASE_IDX                                                                     1
 587 #define mmUVD_OUT_RB_WPTR                                                                              0x00c2
 588 #define mmUVD_OUT_RB_WPTR_BASE_IDX                                                                     1
 589 #define mmUVD_RB_ARB_CTRL                                                                              0x00c6
 590 #define mmUVD_RB_ARB_CTRL_BASE_IDX                                                                     1
 591 #define mmUVD_CTX_INDEX                                                                                0x00c7
 592 #define mmUVD_CTX_INDEX_BASE_IDX                                                                       1
 593 #define mmUVD_CTX_DATA                                                                                 0x00c8
 594 #define mmUVD_CTX_DATA_BASE_IDX                                                                        1
 595 #define mmUVD_CXW_WR                                                                                   0x00c9
 596 #define mmUVD_CXW_WR_BASE_IDX                                                                          1
 597 #define mmUVD_CXW_WR_INT_ID                                                                            0x00ca
 598 #define mmUVD_CXW_WR_INT_ID_BASE_IDX                                                                   1
 599 #define mmUVD_CXW_WR_INT_CTX_ID                                                                        0x00cb
 600 #define mmUVD_CXW_WR_INT_CTX_ID_BASE_IDX                                                               1
 601 #define mmUVD_CXW_INT_ID                                                                               0x00cc
 602 #define mmUVD_CXW_INT_ID_BASE_IDX                                                                      1
 603 #define mmUVD_TOP_CTRL                                                                                 0x00cf
 604 #define mmUVD_TOP_CTRL_BASE_IDX                                                                        1
 605 #define mmUVD_YBASE                                                                                    0x00d0
 606 #define mmUVD_YBASE_BASE_IDX                                                                           1
 607 #define mmUVD_UVBASE                                                                                   0x00d1
 608 #define mmUVD_UVBASE_BASE_IDX                                                                          1
 609 #define mmUVD_PITCH                                                                                    0x00d2
 610 #define mmUVD_PITCH_BASE_IDX                                                                           1
 611 #define mmUVD_WIDTH                                                                                    0x00d3
 612 #define mmUVD_WIDTH_BASE_IDX                                                                           1
 613 #define mmUVD_HEIGHT                                                                                   0x00d4
 614 #define mmUVD_HEIGHT_BASE_IDX                                                                          1
 615 #define mmUVD_PICCOUNT                                                                                 0x00d5
 616 #define mmUVD_PICCOUNT_BASE_IDX                                                                        1
 617 #define mmUVD_SCRATCH_NP                                                                               0x00db
 618 #define mmUVD_SCRATCH_NP_BASE_IDX                                                                      1
 619 #define mmUVD_VERSION                                                                                  0x00dd
 620 #define mmUVD_VERSION_BASE_IDX                                                                         1
 621 #define mmUVD_GP_SCRATCH0                                                                              0x00de
 622 #define mmUVD_GP_SCRATCH0_BASE_IDX                                                                     1
 623 #define mmUVD_GP_SCRATCH1                                                                              0x00df
 624 #define mmUVD_GP_SCRATCH1_BASE_IDX                                                                     1
 625 #define mmUVD_GP_SCRATCH2                                                                              0x00e0
 626 #define mmUVD_GP_SCRATCH2_BASE_IDX                                                                     1
 627 #define mmUVD_GP_SCRATCH3                                                                              0x00e1
 628 #define mmUVD_GP_SCRATCH3_BASE_IDX                                                                     1
 629 #define mmUVD_GP_SCRATCH4                                                                              0x00e2
 630 #define mmUVD_GP_SCRATCH4_BASE_IDX                                                                     1
 631 #define mmUVD_GP_SCRATCH5                                                                              0x00e3
 632 #define mmUVD_GP_SCRATCH5_BASE_IDX                                                                     1
 633 #define mmUVD_GP_SCRATCH6                                                                              0x00e4
 634 #define mmUVD_GP_SCRATCH6_BASE_IDX                                                                     1
 635 #define mmUVD_GP_SCRATCH7                                                                              0x00e5
 636 #define mmUVD_GP_SCRATCH7_BASE_IDX                                                                     1
 637 #define mmUVD_GP_SCRATCH8                                                                              0x00e6
 638 #define mmUVD_GP_SCRATCH8_BASE_IDX                                                                     1
 639 #define mmUVD_GP_SCRATCH9                                                                              0x00e7
 640 #define mmUVD_GP_SCRATCH9_BASE_IDX                                                                     1
 641 #define mmUVD_GP_SCRATCH10                                                                             0x00e8
 642 #define mmUVD_GP_SCRATCH10_BASE_IDX                                                                    1
 643 #define mmUVD_GP_SCRATCH11                                                                             0x00e9
 644 #define mmUVD_GP_SCRATCH11_BASE_IDX                                                                    1
 645 #define mmUVD_GP_SCRATCH12                                                                             0x00ea
 646 #define mmUVD_GP_SCRATCH12_BASE_IDX                                                                    1
 647 #define mmUVD_GP_SCRATCH13                                                                             0x00eb
 648 #define mmUVD_GP_SCRATCH13_BASE_IDX                                                                    1
 649 #define mmUVD_GP_SCRATCH14                                                                             0x00ec
 650 #define mmUVD_GP_SCRATCH14_BASE_IDX                                                                    1
 651 #define mmUVD_GP_SCRATCH15                                                                             0x00ed
 652 #define mmUVD_GP_SCRATCH15_BASE_IDX                                                                    1
 653 #define mmUVD_GP_SCRATCH16                                                                             0x00ee
 654 #define mmUVD_GP_SCRATCH16_BASE_IDX                                                                    1
 655 #define mmUVD_GP_SCRATCH17                                                                             0x00ef
 656 #define mmUVD_GP_SCRATCH17_BASE_IDX                                                                    1
 657 #define mmUVD_GP_SCRATCH18                                                                             0x00f0
 658 #define mmUVD_GP_SCRATCH18_BASE_IDX                                                                    1
 659 #define mmUVD_GP_SCRATCH19                                                                             0x00f1
 660 #define mmUVD_GP_SCRATCH19_BASE_IDX                                                                    1
 661 #define mmUVD_GP_SCRATCH20                                                                             0x00f2
 662 #define mmUVD_GP_SCRATCH20_BASE_IDX                                                                    1
 663 #define mmUVD_GP_SCRATCH21                                                                             0x00f3
 664 #define mmUVD_GP_SCRATCH21_BASE_IDX                                                                    1
 665 #define mmUVD_GP_SCRATCH22                                                                             0x00f4
 666 #define mmUVD_GP_SCRATCH22_BASE_IDX                                                                    1
 667 #define mmUVD_GP_SCRATCH23                                                                             0x00f5
 668 #define mmUVD_GP_SCRATCH23_BASE_IDX                                                                    1
 669 
 670 
 671 // addressBlock: uvd0_ecpudec
 672 // base address: 0x1fd00
 673 #define mmUVD_VCPU_CACHE_OFFSET0                                                                       0x0140
 674 #define mmUVD_VCPU_CACHE_OFFSET0_BASE_IDX                                                              1
 675 #define mmUVD_VCPU_CACHE_SIZE0                                                                         0x0141
 676 #define mmUVD_VCPU_CACHE_SIZE0_BASE_IDX                                                                1
 677 #define mmUVD_VCPU_CACHE_OFFSET1                                                                       0x0142
 678 #define mmUVD_VCPU_CACHE_OFFSET1_BASE_IDX                                                              1
 679 #define mmUVD_VCPU_CACHE_SIZE1                                                                         0x0143
 680 #define mmUVD_VCPU_CACHE_SIZE1_BASE_IDX                                                                1
 681 #define mmUVD_VCPU_CACHE_OFFSET2                                                                       0x0144
 682 #define mmUVD_VCPU_CACHE_OFFSET2_BASE_IDX                                                              1
 683 #define mmUVD_VCPU_CACHE_SIZE2                                                                         0x0145
 684 #define mmUVD_VCPU_CACHE_SIZE2_BASE_IDX                                                                1
 685 #define mmUVD_VCPU_CACHE_OFFSET3                                                                       0x0146
 686 #define mmUVD_VCPU_CACHE_OFFSET3_BASE_IDX                                                              1
 687 #define mmUVD_VCPU_CACHE_SIZE3                                                                         0x0147
 688 #define mmUVD_VCPU_CACHE_SIZE3_BASE_IDX                                                                1
 689 #define mmUVD_VCPU_CACHE_OFFSET4                                                                       0x0148
 690 #define mmUVD_VCPU_CACHE_OFFSET4_BASE_IDX                                                              1
 691 #define mmUVD_VCPU_CACHE_SIZE4                                                                         0x0149
 692 #define mmUVD_VCPU_CACHE_SIZE4_BASE_IDX                                                                1
 693 #define mmUVD_VCPU_CACHE_OFFSET5                                                                       0x014a
 694 #define mmUVD_VCPU_CACHE_OFFSET5_BASE_IDX                                                              1
 695 #define mmUVD_VCPU_CACHE_SIZE5                                                                         0x014b
 696 #define mmUVD_VCPU_CACHE_SIZE5_BASE_IDX                                                                1
 697 #define mmUVD_VCPU_CACHE_OFFSET6                                                                       0x014c
 698 #define mmUVD_VCPU_CACHE_OFFSET6_BASE_IDX                                                              1
 699 #define mmUVD_VCPU_CACHE_SIZE6                                                                         0x014d
 700 #define mmUVD_VCPU_CACHE_SIZE6_BASE_IDX                                                                1
 701 #define mmUVD_VCPU_CACHE_OFFSET7                                                                       0x014e
 702 #define mmUVD_VCPU_CACHE_OFFSET7_BASE_IDX                                                              1
 703 #define mmUVD_VCPU_CACHE_SIZE7                                                                         0x014f
 704 #define mmUVD_VCPU_CACHE_SIZE7_BASE_IDX                                                                1
 705 #define mmUVD_VCPU_CACHE_OFFSET8                                                                       0x0150
 706 #define mmUVD_VCPU_CACHE_OFFSET8_BASE_IDX                                                              1
 707 #define mmUVD_VCPU_CACHE_SIZE8                                                                         0x0151
 708 #define mmUVD_VCPU_CACHE_SIZE8_BASE_IDX                                                                1
 709 #define mmUVD_VCPU_NONCACHE_OFFSET0                                                                    0x0152
 710 #define mmUVD_VCPU_NONCACHE_OFFSET0_BASE_IDX                                                           1
 711 #define mmUVD_VCPU_NONCACHE_SIZE0                                                                      0x0153
 712 #define mmUVD_VCPU_NONCACHE_SIZE0_BASE_IDX                                                             1
 713 #define mmUVD_VCPU_NONCACHE_OFFSET1                                                                    0x0154
 714 #define mmUVD_VCPU_NONCACHE_OFFSET1_BASE_IDX                                                           1
 715 #define mmUVD_VCPU_NONCACHE_SIZE1                                                                      0x0155
 716 #define mmUVD_VCPU_NONCACHE_SIZE1_BASE_IDX                                                             1
 717 #define mmUVD_VCPU_CNTL                                                                                0x0156
 718 #define mmUVD_VCPU_CNTL_BASE_IDX                                                                       1
 719 #define mmUVD_VCPU_PRID                                                                                0x0157
 720 #define mmUVD_VCPU_PRID_BASE_IDX                                                                       1
 721 #define mmUVD_VCPU_TRCE                                                                                0x0158
 722 #define mmUVD_VCPU_TRCE_BASE_IDX                                                                       1
 723 #define mmUVD_VCPU_TRCE_RD                                                                             0x0159
 724 #define mmUVD_VCPU_TRCE_RD_BASE_IDX                                                                    1
 725 
 726 
 727 // addressBlock: uvd0_uvd_mpcdec
 728 // base address: 0x20310
 729 #define mmUVD_MP_SWAP_CNTL                                                                             0x02c4
 730 #define mmUVD_MP_SWAP_CNTL_BASE_IDX                                                                    1
 731 #define mmUVD_MP_SWAP_CNTL2                                                                            0x02c5
 732 #define mmUVD_MP_SWAP_CNTL2_BASE_IDX                                                                   1
 733 #define mmUVD_MPC_LUMA_SRCH                                                                            0x02c6
 734 #define mmUVD_MPC_LUMA_SRCH_BASE_IDX                                                                   1
 735 #define mmUVD_MPC_LUMA_HIT                                                                             0x02c7
 736 #define mmUVD_MPC_LUMA_HIT_BASE_IDX                                                                    1
 737 #define mmUVD_MPC_LUMA_HITPEND                                                                         0x02c8
 738 #define mmUVD_MPC_LUMA_HITPEND_BASE_IDX                                                                1
 739 #define mmUVD_MPC_CHROMA_SRCH                                                                          0x02c9
 740 #define mmUVD_MPC_CHROMA_SRCH_BASE_IDX                                                                 1
 741 #define mmUVD_MPC_CHROMA_HIT                                                                           0x02ca
 742 #define mmUVD_MPC_CHROMA_HIT_BASE_IDX                                                                  1
 743 #define mmUVD_MPC_CHROMA_HITPEND                                                                       0x02cb
 744 #define mmUVD_MPC_CHROMA_HITPEND_BASE_IDX                                                              1
 745 #define mmUVD_MPC_CNTL                                                                                 0x02cc
 746 #define mmUVD_MPC_CNTL_BASE_IDX                                                                        1
 747 #define mmUVD_MPC_PITCH                                                                                0x02cd
 748 #define mmUVD_MPC_PITCH_BASE_IDX                                                                       1
 749 #define mmUVD_MPC_SET_MUXA0                                                                            0x02ce
 750 #define mmUVD_MPC_SET_MUXA0_BASE_IDX                                                                   1
 751 #define mmUVD_MPC_SET_MUXA1                                                                            0x02cf
 752 #define mmUVD_MPC_SET_MUXA1_BASE_IDX                                                                   1
 753 #define mmUVD_MPC_SET_MUXB0                                                                            0x02d0
 754 #define mmUVD_MPC_SET_MUXB0_BASE_IDX                                                                   1
 755 #define mmUVD_MPC_SET_MUXB1                                                                            0x02d1
 756 #define mmUVD_MPC_SET_MUXB1_BASE_IDX                                                                   1
 757 #define mmUVD_MPC_SET_MUX                                                                              0x02d2
 758 #define mmUVD_MPC_SET_MUX_BASE_IDX                                                                     1
 759 #define mmUVD_MPC_SET_ALU                                                                              0x02d3
 760 #define mmUVD_MPC_SET_ALU_BASE_IDX                                                                     1
 761 #define mmUVD_MPC_PERF0                                                                                0x02d4
 762 #define mmUVD_MPC_PERF0_BASE_IDX                                                                       1
 763 #define mmUVD_MPC_PERF1                                                                                0x02d5
 764 #define mmUVD_MPC_PERF1_BASE_IDX                                                                       1
 765 
 766 
 767 // addressBlock: uvd0_uvd_rbcdec
 768 // base address: 0x20370
 769 #define mmUVD_RBC_IB_SIZE                                                                              0x02dc
 770 #define mmUVD_RBC_IB_SIZE_BASE_IDX                                                                     1
 771 #define mmUVD_RBC_IB_SIZE_UPDATE                                                                       0x02dd
 772 #define mmUVD_RBC_IB_SIZE_UPDATE_BASE_IDX                                                              1
 773 #define mmUVD_RBC_RB_CNTL                                                                              0x02de
 774 #define mmUVD_RBC_RB_CNTL_BASE_IDX                                                                     1
 775 #define mmUVD_RBC_RB_RPTR_ADDR                                                                         0x02df
 776 #define mmUVD_RBC_RB_RPTR_ADDR_BASE_IDX                                                                1
 777 #define mmUVD_RBC_RB_RPTR                                                                              0x02e0
 778 #define mmUVD_RBC_RB_RPTR_BASE_IDX                                                                     1
 779 #define mmUVD_RBC_RB_WPTR                                                                              0x02e1
 780 #define mmUVD_RBC_RB_WPTR_BASE_IDX                                                                     1
 781 #define mmUVD_RBC_VCPU_ACCESS                                                                          0x02e2
 782 #define mmUVD_RBC_VCPU_ACCESS_BASE_IDX                                                                 1
 783 #define mmUVD_RBC_READ_REQ_URGENT_CNTL                                                                 0x02e5
 784 #define mmUVD_RBC_READ_REQ_URGENT_CNTL_BASE_IDX                                                        1
 785 #define mmUVD_RBC_RB_WPTR_CNTL                                                                         0x02e6
 786 #define mmUVD_RBC_RB_WPTR_CNTL_BASE_IDX                                                                1
 787 #define mmUVD_RBC_WPTR_STATUS                                                                          0x02e7
 788 #define mmUVD_RBC_WPTR_STATUS_BASE_IDX                                                                 1
 789 #define mmUVD_RBC_WPTR_POLL_CNTL                                                                       0x02e8
 790 #define mmUVD_RBC_WPTR_POLL_CNTL_BASE_IDX                                                              1
 791 #define mmUVD_RBC_WPTR_POLL_ADDR                                                                       0x02e9
 792 #define mmUVD_RBC_WPTR_POLL_ADDR_BASE_IDX                                                              1
 793 #define mmUVD_SEMA_CMD                                                                                 0x02ea
 794 #define mmUVD_SEMA_CMD_BASE_IDX                                                                        1
 795 #define mmUVD_SEMA_ADDR_LOW                                                                            0x02eb
 796 #define mmUVD_SEMA_ADDR_LOW_BASE_IDX                                                                   1
 797 #define mmUVD_SEMA_ADDR_HIGH                                                                           0x02ec
 798 #define mmUVD_SEMA_ADDR_HIGH_BASE_IDX                                                                  1
 799 #define mmUVD_ENGINE_CNTL                                                                              0x02ed
 800 #define mmUVD_ENGINE_CNTL_BASE_IDX                                                                     1
 801 #define mmUVD_SEMA_TIMEOUT_STATUS                                                                      0x02ee
 802 #define mmUVD_SEMA_TIMEOUT_STATUS_BASE_IDX                                                             1
 803 #define mmUVD_SEMA_CNTL                                                                                0x02ef
 804 #define mmUVD_SEMA_CNTL_BASE_IDX                                                                       1
 805 #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL                                                      0x02f0
 806 #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX                                             1
 807 #define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL                                                             0x02f1
 808 #define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL_BASE_IDX                                                    1
 809 #define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL                                                        0x02f2
 810 #define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX                                               1
 811 #define mmUVD_JOB_START                                                                                0x02f3
 812 #define mmUVD_JOB_START_BASE_IDX                                                                       1
 813 #define mmUVD_RBC_BUF_STATUS                                                                           0x02f4
 814 #define mmUVD_RBC_BUF_STATUS_BASE_IDX                                                                  1
 815 
 816 
 817 // addressBlock: uvd0_uvdgendec
 818 // base address: 0x20470
 819 #define mmUVD_LCM_CGC_CNTRL                                                                            0x033f
 820 #define mmUVD_LCM_CGC_CNTRL_BASE_IDX                                                                   1
 821 #define mmUVD_MIF_CURR_UV_ADDR_CONFIG                                                                  0x03a0
 822 #define mmUVD_MIF_CURR_UV_ADDR_CONFIG_BASE_IDX                                                         1
 823 #define mmUVD_MIF_REF_UV_ADDR_CONFIG                                                                   0x03a1
 824 #define mmUVD_MIF_REF_UV_ADDR_CONFIG_BASE_IDX                                                          1
 825 #define mmUVD_MIF_RECON1_UV_ADDR_CONFIG                                                                0x03a2
 826 #define mmUVD_MIF_RECON1_UV_ADDR_CONFIG_BASE_IDX                                                       1
 827 #define mmUVD_MIF_CURR_ADDR_CONFIG                                                                     0x03ae
 828 #define mmUVD_MIF_CURR_ADDR_CONFIG_BASE_IDX                                                            1
 829 #define mmUVD_MIF_REF_ADDR_CONFIG                                                                      0x03af
 830 #define mmUVD_MIF_REF_ADDR_CONFIG_BASE_IDX                                                             1
 831 #define mmUVD_MIF_RECON1_ADDR_CONFIG                                                                   0x03e1
 832 #define mmUVD_MIF_RECON1_ADDR_CONFIG_BASE_IDX                                                          1
 833 
 834 
 835 // addressBlock: uvd0_lmi_adpdec
 836 // base address: 0x20870
 837 #define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW                                                                 0x0432
 838 #define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW_BASE_IDX                                                        1
 839 #define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH                                                                0x0433
 840 #define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH_BASE_IDX                                                       1
 841 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW                                                                 0x0434
 842 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_BASE_IDX                                                        1
 843 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH                                                                0x0435
 844 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_BASE_IDX                                                       1
 845 #define mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW                                                               0x0438
 846 #define mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW_BASE_IDX                                                      1
 847 #define mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH                                                              0x0439
 848 #define mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH_BASE_IDX                                                     1
 849 #define mmUVD_LMI_VCPU_NC1_64BIT_BAR_LOW                                                               0x043a
 850 #define mmUVD_LMI_VCPU_NC1_64BIT_BAR_LOW_BASE_IDX                                                      1
 851 #define mmUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH                                                              0x043b
 852 #define mmUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH_BASE_IDX                                                     1
 853 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW                                                             0x043c
 854 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX                                                    1
 855 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH                                                            0x043d
 856 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX                                                   1
 857 #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW                                                            0x0468
 858 #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_BASE_IDX                                                   1
 859 #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH                                                           0x0469
 860 #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_BASE_IDX                                                  1
 861 #define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW                                                            0x046a
 862 #define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW_BASE_IDX                                                   1
 863 #define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH                                                           0x046b
 864 #define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH_BASE_IDX                                                  1
 865 #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW                                                            0x046c
 866 #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_BASE_IDX                                                   1
 867 #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH                                                           0x046d
 868 #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_BASE_IDX                                                  1
 869 #define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW                                                            0x046e
 870 #define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW_BASE_IDX                                                   1
 871 #define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH                                                           0x046f
 872 #define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH_BASE_IDX                                                  1
 873 #define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW                                                            0x0470
 874 #define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW_BASE_IDX                                                   1
 875 #define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH                                                           0x0471
 876 #define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH_BASE_IDX                                                  1
 877 #define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW                                                            0x0472
 878 #define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW_BASE_IDX                                                   1
 879 #define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH                                                           0x0473
 880 #define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH_BASE_IDX                                                  1
 881 #define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW                                                            0x0474
 882 #define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW_BASE_IDX                                                   1
 883 #define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH                                                           0x0475
 884 #define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH_BASE_IDX                                                  1
 885 #define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW                                                            0x0476
 886 #define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW_BASE_IDX                                                   1
 887 #define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH                                                           0x0477
 888 #define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH_BASE_IDX                                                  1
 889 #define mmUVD_LMI_SPH_64BIT_BAR_HIGH                                                                   0x047c
 890 #define mmUVD_LMI_SPH_64BIT_BAR_HIGH_BASE_IDX                                                          1
 891 #define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW                                                              0x047d
 892 #define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW_BASE_IDX                                                     1
 893 #define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH                                                             0x047e
 894 #define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH_BASE_IDX                                                    1
 895 #define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW                                                              0x047f
 896 #define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW_BASE_IDX                                                     1
 897 #define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH                                                             0x0480
 898 #define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH_BASE_IDX                                                    1
 899 #define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW                                                              0x0481
 900 #define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW_BASE_IDX                                                     1
 901 #define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH                                                             0x0482
 902 #define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH_BASE_IDX                                                    1
 903 #define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW                                                              0x0483
 904 #define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW_BASE_IDX                                                     1
 905 #define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH                                                             0x0484
 906 #define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH_BASE_IDX                                                    1
 907 #define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW                                                              0x0485
 908 #define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW_BASE_IDX                                                     1
 909 #define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH                                                             0x0486
 910 #define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH_BASE_IDX                                                    1
 911 #define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW                                                              0x0487
 912 #define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW_BASE_IDX                                                     1
 913 #define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH                                                             0x0488
 914 #define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH_BASE_IDX                                                    1
 915 #define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW                                                              0x0489
 916 #define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW_BASE_IDX                                                     1
 917 #define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH                                                             0x048a
 918 #define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH_BASE_IDX                                                    1
 919 #define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW                                                              0x048b
 920 #define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW_BASE_IDX                                                     1
 921 #define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH                                                             0x048c
 922 #define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH_BASE_IDX                                                    1
 923 #define mmUVD_LMI_MMSCH_NC_VMID                                                                        0x048d
 924 #define mmUVD_LMI_MMSCH_NC_VMID_BASE_IDX                                                               1
 925 #define mmUVD_LMI_MMSCH_CTRL                                                                           0x048e
 926 #define mmUVD_LMI_MMSCH_CTRL_BASE_IDX                                                                  1
 927 #define mmUVD_LMI_ARB_CTRL2                                                                            0x049a
 928 #define mmUVD_LMI_ARB_CTRL2_BASE_IDX                                                                   1
 929 #define mmUVD_LMI_VCPU_CACHE_VMIDS_MULTI                                                               0x049f
 930 #define mmUVD_LMI_VCPU_CACHE_VMIDS_MULTI_BASE_IDX                                                      1
 931 #define mmUVD_LMI_VCPU_NC_VMIDS_MULTI                                                                  0x04a0
 932 #define mmUVD_LMI_VCPU_NC_VMIDS_MULTI_BASE_IDX                                                         1
 933 #define mmUVD_LMI_LAT_CTRL                                                                             0x04a1
 934 #define mmUVD_LMI_LAT_CTRL_BASE_IDX                                                                    1
 935 #define mmUVD_LMI_LAT_CNTR                                                                             0x04a2
 936 #define mmUVD_LMI_LAT_CNTR_BASE_IDX                                                                    1
 937 #define mmUVD_LMI_AVG_LAT_CNTR                                                                         0x04a3
 938 #define mmUVD_LMI_AVG_LAT_CNTR_BASE_IDX                                                                1
 939 #define mmUVD_LMI_SPH                                                                                  0x04a4
 940 #define mmUVD_LMI_SPH_BASE_IDX                                                                         1
 941 #define mmUVD_LMI_VCPU_CACHE_VMID                                                                      0x04a5
 942 #define mmUVD_LMI_VCPU_CACHE_VMID_BASE_IDX                                                             1
 943 #define mmUVD_LMI_CTRL2                                                                                0x04a6
 944 #define mmUVD_LMI_CTRL2_BASE_IDX                                                                       1
 945 #define mmUVD_LMI_URGENT_CTRL                                                                          0x04a7
 946 #define mmUVD_LMI_URGENT_CTRL_BASE_IDX                                                                 1
 947 #define mmUVD_LMI_CTRL                                                                                 0x04a8
 948 #define mmUVD_LMI_CTRL_BASE_IDX                                                                        1
 949 #define mmUVD_LMI_STATUS                                                                               0x04a9
 950 #define mmUVD_LMI_STATUS_BASE_IDX                                                                      1
 951 #define mmUVD_LMI_PERFMON_CTRL                                                                         0x04ac
 952 #define mmUVD_LMI_PERFMON_CTRL_BASE_IDX                                                                1
 953 #define mmUVD_LMI_PERFMON_COUNT_LO                                                                     0x04ad
 954 #define mmUVD_LMI_PERFMON_COUNT_LO_BASE_IDX                                                            1
 955 #define mmUVD_LMI_PERFMON_COUNT_HI                                                                     0x04ae
 956 #define mmUVD_LMI_PERFMON_COUNT_HI_BASE_IDX                                                            1
 957 #define mmUVD_LMI_RBC_RB_VMID                                                                          0x04b0
 958 #define mmUVD_LMI_RBC_RB_VMID_BASE_IDX                                                                 1
 959 #define mmUVD_LMI_RBC_IB_VMID                                                                          0x04b1
 960 #define mmUVD_LMI_RBC_IB_VMID_BASE_IDX                                                                 1
 961 #define mmUVD_LMI_MC_CREDITS                                                                           0x04b2
 962 #define mmUVD_LMI_MC_CREDITS_BASE_IDX                                                                  1
 963 
 964 
 965 // addressBlock: uvd0_uvdnpdec
 966 // base address: 0x20bd0
 967 #define mmMDM_DMA_CMD                                                                                  0x06f4
 968 #define mmMDM_DMA_CMD_BASE_IDX                                                                         1
 969 #define mmMDM_DMA_STATUS                                                                               0x06f5
 970 #define mmMDM_DMA_STATUS_BASE_IDX                                                                      1
 971 #define mmMDM_DMA_CTL                                                                                  0x06f6
 972 #define mmMDM_DMA_CTL_BASE_IDX                                                                         1
 973 #define mmMDM_ENC_PIPE_BUSY                                                                            0x06f7
 974 #define mmMDM_ENC_PIPE_BUSY_BASE_IDX                                                                   1
 975 #define mmMDM_WIG_PIPE_BUSY                                                                            0x06f9
 976 #define mmMDM_WIG_PIPE_BUSY_BASE_IDX                                                                   1
 977 
 978 
 979 #endif