root/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

INCLUDED FROM

   1 /*
   2  * Copyright (C) 2017  Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  */
  21 #ifndef _vcn_1_0_SH_MASK_HEADER
  22 #define _vcn_1_0_SH_MASK_HEADER
  23 
  24 
  25 // addressBlock: uvd_uvd_pg_dec
  26 //UVD_PGFSM_CONFIG
  27 #define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT                                                              0x0
  28 #define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT                                                              0x2
  29 #define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT                                                              0x4
  30 #define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT                                                              0x6
  31 #define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT                                                              0x8
  32 #define UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT                                                             0xa
  33 #define UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT                                                             0xc
  34 #define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT                                                             0xe
  35 #define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT                                                             0x10
  36 #define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT                                                              0x12
  37 #define UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT                                                              0x14
  38 #define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG_MASK                                                                0x00000003L
  39 #define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG_MASK                                                                0x0000000CL
  40 #define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG_MASK                                                                0x00000030L
  41 #define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG_MASK                                                                0x000000C0L
  42 #define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG_MASK                                                                0x00000300L
  43 #define UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG_MASK                                                               0x00000C00L
  44 #define UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG_MASK                                                               0x00003000L
  45 #define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG_MASK                                                               0x0000C000L
  46 #define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG_MASK                                                               0x00030000L
  47 #define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG_MASK                                                                0x000C0000L
  48 #define UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG_MASK                                                                0x00300000L
  49 //UVD_PGFSM_STATUS
  50 #define UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT                                                              0x0
  51 #define UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT                                                              0x2
  52 #define UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT                                                              0x4
  53 #define UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT                                                              0x6
  54 #define UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT                                                              0x8
  55 #define UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT                                                             0xa
  56 #define UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT                                                             0xc
  57 #define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT                                                             0xe
  58 #define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT                                                             0x10
  59 #define UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT                                                              0x12
  60 #define UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT                                                              0x14
  61 #define UVD_PGFSM_STATUS__UVDM_PWR_STATUS_MASK                                                                0x00000003L
  62 #define UVD_PGFSM_STATUS__UVDU_PWR_STATUS_MASK                                                                0x0000000CL
  63 #define UVD_PGFSM_STATUS__UVDF_PWR_STATUS_MASK                                                                0x00000030L
  64 #define UVD_PGFSM_STATUS__UVDC_PWR_STATUS_MASK                                                                0x000000C0L
  65 #define UVD_PGFSM_STATUS__UVDB_PWR_STATUS_MASK                                                                0x00000300L
  66 #define UVD_PGFSM_STATUS__UVDIL_PWR_STATUS_MASK                                                               0x00000C00L
  67 #define UVD_PGFSM_STATUS__UVDIR_PWR_STATUS_MASK                                                               0x00003000L
  68 #define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS_MASK                                                               0x0000C000L
  69 #define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS_MASK                                                               0x00030000L
  70 #define UVD_PGFSM_STATUS__UVDE_PWR_STATUS_MASK                                                                0x000C0000L
  71 #define UVD_PGFSM_STATUS__UVDW_PWR_STATUS_MASK                                                                0x00300000L
  72 //UVD_POWER_STATUS
  73 #define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT                                                             0x0
  74 #define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT                                                                  0x2
  75 #define UVD_POWER_STATUS__UVD_CG_MODE__SHIFT                                                                  0x4
  76 #define UVD_POWER_STATUS__UVD_PG_EN__SHIFT                                                                    0x8
  77 #define UVD_POWER_STATUS__RBC_SNOOP_DIS__SHIFT                                                                0x9
  78 #define UVD_POWER_STATUS__JRBC_SNOOP_DIS__SHIFT                                                               0xa
  79 #define UVD_POWER_STATUS__SW_RB_SNOOP_DIS__SHIFT                                                              0xb
  80 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK                                                               0x00000003L
  81 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK                                                                    0x00000004L
  82 #define UVD_POWER_STATUS__UVD_CG_MODE_MASK                                                                    0x00000030L
  83 #define UVD_POWER_STATUS__UVD_PG_EN_MASK                                                                      0x00000100L
  84 #define UVD_POWER_STATUS__RBC_SNOOP_DIS_MASK                                                                  0x00000200L
  85 #define UVD_POWER_STATUS__JRBC_SNOOP_DIS_MASK                                                                 0x00000400L
  86 #define UVD_POWER_STATUS__SW_RB_SNOOP_DIS_MASK                                                                0x00000800L
  87 //CC_UVD_HARVESTING
  88 #define CC_UVD_HARVESTING__UVD_DISABLE__SHIFT                                                                 0x1
  89 #define CC_UVD_HARVESTING__UVD_DISABLE_MASK                                                                   0x00000002L
  90 //UVD_DPG_LMA_CTL
  91 #define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT                                                                    0x0
  92 #define UVD_DPG_LMA_CTL__MASK_EN__SHIFT                                                                       0x1
  93 #define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT__SHIFT                                                           0x2
  94 #define UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT                                                                      0x4
  95 #define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT                                                               0x10
  96 #define UVD_DPG_LMA_CTL__READ_WRITE_MASK                                                                      0x00000001L
  97 #define UVD_DPG_LMA_CTL__MASK_EN_MASK                                                                         0x00000002L
  98 #define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT_MASK                                                             0x00000004L
  99 #define UVD_DPG_LMA_CTL__SRAM_SEL_MASK                                                                        0x00000010L
 100 #define UVD_DPG_LMA_CTL__READ_WRITE_ADDR_MASK                                                                 0xFFFF0000L
 101 //UVD_DPG_PAUSE
 102 #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ__SHIFT                                                              0x0
 103 #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK__SHIFT                                                              0x1
 104 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ__SHIFT                                                                0x2
 105 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK__SHIFT                                                                0x3
 106 #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK                                                                0x00000001L
 107 #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK                                                                0x00000002L
 108 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK                                                                  0x00000004L
 109 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK                                                                  0x00000008L
 110 //UVD_SCRATCH1
 111 #define UVD_SCRATCH1__SCRATCH1_DATA__SHIFT                                                                    0x0
 112 #define UVD_SCRATCH1__SCRATCH1_DATA_MASK                                                                      0xFFFFFFFFL
 113 //UVD_SCRATCH2
 114 #define UVD_SCRATCH2__SCRATCH2_DATA__SHIFT                                                                    0x0
 115 #define UVD_SCRATCH2__SCRATCH2_DATA_MASK                                                                      0xFFFFFFFFL
 116 //UVD_SCRATCH3
 117 #define UVD_SCRATCH3__SCRATCH3_DATA__SHIFT                                                                    0x0
 118 #define UVD_SCRATCH3__SCRATCH3_DATA_MASK                                                                      0xFFFFFFFFL
 119 //UVD_SCRATCH4
 120 #define UVD_SCRATCH4__SCRATCH4_DATA__SHIFT                                                                    0x0
 121 #define UVD_SCRATCH4__SCRATCH4_DATA_MASK                                                                      0xFFFFFFFFL
 122 //UVD_SCRATCH5
 123 #define UVD_SCRATCH5__SCRATCH5_DATA__SHIFT                                                                    0x0
 124 #define UVD_SCRATCH5__SCRATCH5_DATA_MASK                                                                      0xFFFFFFFFL
 125 //UVD_SCRATCH6
 126 #define UVD_SCRATCH6__SCRATCH6_DATA__SHIFT                                                                    0x0
 127 #define UVD_SCRATCH6__SCRATCH6_DATA_MASK                                                                      0xFFFFFFFFL
 128 //UVD_SCRATCH7
 129 #define UVD_SCRATCH7__SCRATCH7_DATA__SHIFT                                                                    0x0
 130 #define UVD_SCRATCH7__SCRATCH7_DATA_MASK                                                                      0xFFFFFFFFL
 131 //UVD_SCRATCH8
 132 #define UVD_SCRATCH8__SCRATCH8_DATA__SHIFT                                                                    0x0
 133 #define UVD_SCRATCH8__SCRATCH8_DATA_MASK                                                                      0xFFFFFFFFL
 134 //UVD_SCRATCH9
 135 #define UVD_SCRATCH9__SCRATCH9_DATA__SHIFT                                                                    0x0
 136 #define UVD_SCRATCH9__SCRATCH9_DATA_MASK                                                                      0xFFFFFFFFL
 137 //UVD_SCRATCH10
 138 #define UVD_SCRATCH10__SCRATCH10_DATA__SHIFT                                                                  0x0
 139 #define UVD_SCRATCH10__SCRATCH10_DATA_MASK                                                                    0xFFFFFFFFL
 140 //UVD_SCRATCH11
 141 #define UVD_SCRATCH11__SCRATCH11_DATA__SHIFT                                                                  0x0
 142 #define UVD_SCRATCH11__SCRATCH11_DATA_MASK                                                                    0xFFFFFFFFL
 143 //UVD_SCRATCH12
 144 #define UVD_SCRATCH12__SCRATCH12_DATA__SHIFT                                                                  0x0
 145 #define UVD_SCRATCH12__SCRATCH12_DATA_MASK                                                                    0xFFFFFFFFL
 146 //UVD_SCRATCH13
 147 #define UVD_SCRATCH13__SCRATCH13_DATA__SHIFT                                                                  0x0
 148 #define UVD_SCRATCH13__SCRATCH13_DATA_MASK                                                                    0xFFFFFFFFL
 149 //UVD_SCRATCH14
 150 #define UVD_SCRATCH14__SCRATCH14_DATA__SHIFT                                                                  0x0
 151 #define UVD_SCRATCH14__SCRATCH14_DATA_MASK                                                                    0xFFFFFFFFL
 152 //UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW
 153 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                0x0
 154 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK                                                  0xFFFFFFFFL
 155 //UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH
 156 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                              0x0
 157 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK                                                0xFFFFFFFFL
 158 //UVD_DPG_VCPU_CACHE_OFFSET0
 159 #define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT                                                      0x0
 160 #define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK                                                        0x01FFFFFFL
 161 
 162 
 163 // addressBlock: uvd_uvdgendec
 164 //UVD_LCM_CGC_CNTRL
 165 #define UVD_LCM_CGC_CNTRL__FORCE_OFF__SHIFT                                                                   0x12
 166 #define UVD_LCM_CGC_CNTRL__FORCE_ON__SHIFT                                                                    0x13
 167 #define UVD_LCM_CGC_CNTRL__OFF_DELAY__SHIFT                                                                   0x14
 168 #define UVD_LCM_CGC_CNTRL__ON_DELAY__SHIFT                                                                    0x1c
 169 #define UVD_LCM_CGC_CNTRL__FORCE_OFF_MASK                                                                     0x00040000L
 170 #define UVD_LCM_CGC_CNTRL__FORCE_ON_MASK                                                                      0x00080000L
 171 #define UVD_LCM_CGC_CNTRL__OFF_DELAY_MASK                                                                     0x0FF00000L
 172 #define UVD_LCM_CGC_CNTRL__ON_DELAY_MASK                                                                      0xF0000000L
 173 
 174 
 175 // addressBlock: uvd_uvdnpdec
 176 //UVD_JPEG_CNTL
 177 #define UVD_JPEG_CNTL__SOFT_RESET__SHIFT                                                                      0x0
 178 #define UVD_JPEG_CNTL__REQUEST_EN__SHIFT                                                                      0x1
 179 #define UVD_JPEG_CNTL__ERR_RST_EN__SHIFT                                                                      0x2
 180 #define UVD_JPEG_CNTL__HUFF_SPEED_EN__SHIFT                                                                   0x3
 181 #define UVD_JPEG_CNTL__HUFF_SPEED_STATUS__SHIFT                                                               0x4
 182 #define UVD_JPEG_CNTL__DBG_MUX_SEL__SHIFT                                                                     0x8
 183 #define UVD_JPEG_CNTL__SOFT_RESET_MASK                                                                        0x00000001L
 184 #define UVD_JPEG_CNTL__REQUEST_EN_MASK                                                                        0x00000002L
 185 #define UVD_JPEG_CNTL__ERR_RST_EN_MASK                                                                        0x00000004L
 186 #define UVD_JPEG_CNTL__HUFF_SPEED_EN_MASK                                                                     0x00000008L
 187 #define UVD_JPEG_CNTL__HUFF_SPEED_STATUS_MASK                                                                 0x00000010L
 188 #define UVD_JPEG_CNTL__DBG_MUX_SEL_MASK                                                                       0x00007F00L
 189 //UVD_JPEG_RB_BASE
 190 #define UVD_JPEG_RB_BASE__RB_BYTE_OFF__SHIFT                                                                  0x0
 191 #define UVD_JPEG_RB_BASE__RB_BASE__SHIFT                                                                      0x6
 192 #define UVD_JPEG_RB_BASE__RB_BYTE_OFF_MASK                                                                    0x0000003FL
 193 #define UVD_JPEG_RB_BASE__RB_BASE_MASK                                                                        0xFFFFFFC0L
 194 //UVD_JPEG_RB_WPTR
 195 #define UVD_JPEG_RB_WPTR__RB_WPTR__SHIFT                                                                      0x4
 196 #define UVD_JPEG_RB_WPTR__RB_WPTR_MASK                                                                        0x3FFFFFF0L
 197 //UVD_JPEG_RB_RPTR
 198 #define UVD_JPEG_RB_RPTR__RB_RPTR__SHIFT                                                                      0x4
 199 #define UVD_JPEG_RB_RPTR__RB_RPTR_MASK                                                                        0x3FFFFFF0L
 200 //UVD_JPEG_RB_SIZE
 201 #define UVD_JPEG_RB_SIZE__RB_SIZE__SHIFT                                                                      0x4
 202 #define UVD_JPEG_RB_SIZE__RB_SIZE_MASK                                                                        0x3FFFFFF0L
 203 //UVD_JPEG_ADDR_CONFIG
 204 #define UVD_JPEG_ADDR_CONFIG__NUM_PIPES__SHIFT                                                                0x0
 205 #define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                     0x3
 206 #define UVD_JPEG_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                     0x6
 207 #define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT                                                     0x8
 208 #define UVD_JPEG_ADDR_CONFIG__NUM_BANKS__SHIFT                                                                0xc
 209 #define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT                                                  0x10
 210 #define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT                                                       0x13
 211 #define UVD_JPEG_ADDR_CONFIG__NUM_GPUS__SHIFT                                                                 0x15
 212 #define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT                                                      0x18
 213 #define UVD_JPEG_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT                                                            0x1a
 214 #define UVD_JPEG_ADDR_CONFIG__ROW_SIZE__SHIFT                                                                 0x1c
 215 #define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT                                                          0x1e
 216 #define UVD_JPEG_ADDR_CONFIG__SE_ENABLE__SHIFT                                                                0x1f
 217 #define UVD_JPEG_ADDR_CONFIG__NUM_PIPES_MASK                                                                  0x00000007L
 218 #define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                       0x00000038L
 219 #define UVD_JPEG_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                       0x000000C0L
 220 #define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK                                                       0x00000700L
 221 #define UVD_JPEG_ADDR_CONFIG__NUM_BANKS_MASK                                                                  0x00007000L
 222 #define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK                                                    0x00070000L
 223 #define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK                                                         0x00180000L
 224 #define UVD_JPEG_ADDR_CONFIG__NUM_GPUS_MASK                                                                   0x00E00000L
 225 #define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK                                                        0x03000000L
 226 #define UVD_JPEG_ADDR_CONFIG__NUM_RB_PER_SE_MASK                                                              0x0C000000L
 227 #define UVD_JPEG_ADDR_CONFIG__ROW_SIZE_MASK                                                                   0x30000000L
 228 #define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES_MASK                                                            0x40000000L
 229 #define UVD_JPEG_ADDR_CONFIG__SE_ENABLE_MASK                                                                  0x80000000L
 230 //UVD_JPEG_GPCOM_CMD
 231 #define UVD_JPEG_GPCOM_CMD__CMD_SEND__SHIFT                                                                   0x0
 232 #define UVD_JPEG_GPCOM_CMD__CMD__SHIFT                                                                        0x1
 233 #define UVD_JPEG_GPCOM_CMD__CMD_SOURCE__SHIFT                                                                 0x1f
 234 #define UVD_JPEG_GPCOM_CMD__CMD_SEND_MASK                                                                     0x00000001L
 235 #define UVD_JPEG_GPCOM_CMD__CMD_MASK                                                                          0x7FFFFFFEL
 236 #define UVD_JPEG_GPCOM_CMD__CMD_SOURCE_MASK                                                                   0x80000000L
 237 //UVD_JPEG_GPCOM_DATA0
 238 #define UVD_JPEG_GPCOM_DATA0__DATA0__SHIFT                                                                    0x0
 239 #define UVD_JPEG_GPCOM_DATA0__DATA0_MASK                                                                      0xFFFFFFFFL
 240 //UVD_JPEG_GPCOM_DATA1
 241 #define UVD_JPEG_GPCOM_DATA1__DATA1__SHIFT                                                                    0x0
 242 #define UVD_JPEG_GPCOM_DATA1__DATA1_MASK                                                                      0xFFFFFFFFL
 243 //UVD_JPEG_JRB_BASE_LO
 244 #define UVD_JPEG_JRB_BASE_LO__JRB_BASE_LO__SHIFT                                                              0x6
 245 #define UVD_JPEG_JRB_BASE_LO__JRB_BASE_LO_MASK                                                                0xFFFFFFC0L
 246 //UVD_JPEG_JRB_BASE_HI
 247 #define UVD_JPEG_JRB_BASE_HI__JRB_BASE_HI__SHIFT                                                              0x0
 248 #define UVD_JPEG_JRB_BASE_HI__JRB_BASE_HI_MASK                                                                0xFFFFFFFFL
 249 //UVD_JPEG_JRB_SIZE
 250 #define UVD_JPEG_JRB_SIZE__JRB_SIZE__SHIFT                                                                    0x4
 251 #define UVD_JPEG_JRB_SIZE__JRB_SIZE_MASK                                                                      0x007FFFF0L
 252 //UVD_JPEG_JRB_RPTR
 253 #define UVD_JPEG_JRB_RPTR__JRB_RPTR__SHIFT                                                                    0x4
 254 #define UVD_JPEG_JRB_RPTR__JRB_RPTR_MASK                                                                      0x007FFFF0L
 255 //UVD_JPEG_JRB_WPTR
 256 #define UVD_JPEG_JRB_WPTR__JRB_WPTR__SHIFT                                                                    0x4
 257 #define UVD_JPEG_JRB_WPTR__JRB_WPTR_MASK                                                                      0x007FFFF0L
 258 //UVD_JPEG_UV_ADDR_CONFIG
 259 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_PIPES__SHIFT                                                             0x0
 260 #define UVD_JPEG_UV_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                  0x3
 261 #define UVD_JPEG_UV_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                  0x6
 262 #define UVD_JPEG_UV_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT                                                  0x8
 263 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_BANKS__SHIFT                                                             0xc
 264 #define UVD_JPEG_UV_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT                                               0x10
 265 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT                                                    0x13
 266 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_GPUS__SHIFT                                                              0x15
 267 #define UVD_JPEG_UV_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT                                                   0x18
 268 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT                                                         0x1a
 269 #define UVD_JPEG_UV_ADDR_CONFIG__ROW_SIZE__SHIFT                                                              0x1c
 270 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT                                                       0x1e
 271 #define UVD_JPEG_UV_ADDR_CONFIG__SE_ENABLE__SHIFT                                                             0x1f
 272 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_PIPES_MASK                                                               0x00000007L
 273 #define UVD_JPEG_UV_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                    0x00000038L
 274 #define UVD_JPEG_UV_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                    0x000000C0L
 275 #define UVD_JPEG_UV_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK                                                    0x00000700L
 276 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_BANKS_MASK                                                               0x00007000L
 277 #define UVD_JPEG_UV_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK                                                 0x00070000L
 278 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK                                                      0x00180000L
 279 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_GPUS_MASK                                                                0x00E00000L
 280 #define UVD_JPEG_UV_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK                                                     0x03000000L
 281 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_RB_PER_SE_MASK                                                           0x0C000000L
 282 #define UVD_JPEG_UV_ADDR_CONFIG__ROW_SIZE_MASK                                                                0x30000000L
 283 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_LOWER_PIPES_MASK                                                         0x40000000L
 284 #define UVD_JPEG_UV_ADDR_CONFIG__SE_ENABLE_MASK                                                               0x80000000L
 285 //UVD_SEMA_ADDR_LOW
 286 #define UVD_SEMA_ADDR_LOW__ADDR_26_3__SHIFT                                                                   0x0
 287 #define UVD_SEMA_ADDR_LOW__ADDR_26_3_MASK                                                                     0x00FFFFFFL
 288 //UVD_SEMA_ADDR_HIGH
 289 #define UVD_SEMA_ADDR_HIGH__ADDR_47_27__SHIFT                                                                 0x0
 290 #define UVD_SEMA_ADDR_HIGH__ADDR_47_27_MASK                                                                   0x001FFFFFL
 291 //UVD_SEMA_CMD
 292 #define UVD_SEMA_CMD__REQ_CMD__SHIFT                                                                          0x0
 293 #define UVD_SEMA_CMD__WR_PHASE__SHIFT                                                                         0x4
 294 #define UVD_SEMA_CMD__MODE__SHIFT                                                                             0x6
 295 #define UVD_SEMA_CMD__VMID_EN__SHIFT                                                                          0x7
 296 #define UVD_SEMA_CMD__VMID__SHIFT                                                                             0x8
 297 #define UVD_SEMA_CMD__REQ_CMD_MASK                                                                            0x0000000FL
 298 #define UVD_SEMA_CMD__WR_PHASE_MASK                                                                           0x00000030L
 299 #define UVD_SEMA_CMD__MODE_MASK                                                                               0x00000040L
 300 #define UVD_SEMA_CMD__VMID_EN_MASK                                                                            0x00000080L
 301 #define UVD_SEMA_CMD__VMID_MASK                                                                               0x00000F00L
 302 //UVD_GPCOM_VCPU_CMD
 303 #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT                                                                   0x0
 304 #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT                                                                        0x1
 305 #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT                                                                 0x1f
 306 #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK                                                                     0x00000001L
 307 #define UVD_GPCOM_VCPU_CMD__CMD_MASK                                                                          0x7FFFFFFEL
 308 #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK                                                                   0x80000000L
 309 //UVD_GPCOM_VCPU_DATA0
 310 #define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT                                                                    0x0
 311 #define UVD_GPCOM_VCPU_DATA0__DATA0_MASK                                                                      0xFFFFFFFFL
 312 //UVD_GPCOM_VCPU_DATA1
 313 #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT                                                                    0x0
 314 #define UVD_GPCOM_VCPU_DATA1__DATA1_MASK                                                                      0xFFFFFFFFL
 315 //UVD_ENGINE_CNTL
 316 #define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x1
 317 #define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0
 318 #define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x2
 319 #define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1
 320 //UVD_UDEC_DBW_UV_ADDR_CONFIG
 321 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_PIPES__SHIFT                                                         0x0
 322 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                              0x3
 323 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                              0x6
 324 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT                                              0x8
 325 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_BANKS__SHIFT                                                         0xc
 326 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT                                           0x10
 327 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT                                                0x13
 328 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_GPUS__SHIFT                                                          0x15
 329 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT                                               0x18
 330 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT                                                     0x1a
 331 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__ROW_SIZE__SHIFT                                                          0x1c
 332 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT                                                   0x1e
 333 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__SE_ENABLE__SHIFT                                                         0x1f
 334 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_PIPES_MASK                                                           0x00000007L
 335 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                0x00000038L
 336 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                0x000000C0L
 337 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK                                                0x00000700L
 338 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_BANKS_MASK                                                           0x00007000L
 339 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK                                             0x00070000L
 340 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK                                                  0x00180000L
 341 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_GPUS_MASK                                                            0x00E00000L
 342 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK                                                 0x03000000L
 343 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_RB_PER_SE_MASK                                                       0x0C000000L
 344 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__ROW_SIZE_MASK                                                            0x30000000L
 345 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_LOWER_PIPES_MASK                                                     0x40000000L
 346 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__SE_ENABLE_MASK                                                           0x80000000L
 347 //UVD_UDEC_ADDR_CONFIG
 348 #define UVD_UDEC_ADDR_CONFIG__NUM_PIPES__SHIFT                                                                0x0
 349 #define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                     0x3
 350 #define UVD_UDEC_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                     0x6
 351 #define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT                                                     0x8
 352 #define UVD_UDEC_ADDR_CONFIG__NUM_BANKS__SHIFT                                                                0xc
 353 #define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT                                                  0x10
 354 #define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT                                                       0x13
 355 #define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT                                                                 0x15
 356 #define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT                                                      0x18
 357 #define UVD_UDEC_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT                                                            0x1a
 358 #define UVD_UDEC_ADDR_CONFIG__ROW_SIZE__SHIFT                                                                 0x1c
 359 #define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT                                                          0x1e
 360 #define UVD_UDEC_ADDR_CONFIG__SE_ENABLE__SHIFT                                                                0x1f
 361 #define UVD_UDEC_ADDR_CONFIG__NUM_PIPES_MASK                                                                  0x00000007L
 362 #define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                       0x00000038L
 363 #define UVD_UDEC_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                       0x000000C0L
 364 #define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK                                                       0x00000700L
 365 #define UVD_UDEC_ADDR_CONFIG__NUM_BANKS_MASK                                                                  0x00007000L
 366 #define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK                                                    0x00070000L
 367 #define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK                                                         0x00180000L
 368 #define UVD_UDEC_ADDR_CONFIG__NUM_GPUS_MASK                                                                   0x00E00000L
 369 #define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK                                                        0x03000000L
 370 #define UVD_UDEC_ADDR_CONFIG__NUM_RB_PER_SE_MASK                                                              0x0C000000L
 371 #define UVD_UDEC_ADDR_CONFIG__ROW_SIZE_MASK                                                                   0x30000000L
 372 #define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES_MASK                                                            0x40000000L
 373 #define UVD_UDEC_ADDR_CONFIG__SE_ENABLE_MASK                                                                  0x80000000L
 374 //UVD_UDEC_DB_ADDR_CONFIG
 375 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES__SHIFT                                                             0x0
 376 #define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                  0x3
 377 #define UVD_UDEC_DB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                  0x6
 378 #define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT                                                  0x8
 379 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_BANKS__SHIFT                                                             0xc
 380 #define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT                                               0x10
 381 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT                                                    0x13
 382 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT                                                              0x15
 383 #define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT                                                   0x18
 384 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT                                                         0x1a
 385 #define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE__SHIFT                                                              0x1c
 386 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT                                                       0x1e
 387 #define UVD_UDEC_DB_ADDR_CONFIG__SE_ENABLE__SHIFT                                                             0x1f
 388 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES_MASK                                                               0x00000007L
 389 #define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                    0x00000038L
 390 #define UVD_UDEC_DB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                    0x000000C0L
 391 #define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK                                                    0x00000700L
 392 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_BANKS_MASK                                                               0x00007000L
 393 #define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK                                                 0x00070000L
 394 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK                                                      0x00180000L
 395 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS_MASK                                                                0x00E00000L
 396 #define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK                                                     0x03000000L
 397 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_RB_PER_SE_MASK                                                           0x0C000000L
 398 #define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE_MASK                                                                0x30000000L
 399 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK                                                         0x40000000L
 400 #define UVD_UDEC_DB_ADDR_CONFIG__SE_ENABLE_MASK                                                               0x80000000L
 401 //UVD_UDEC_DBW_ADDR_CONFIG
 402 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0
 403 #define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                 0x3
 404 #define UVD_UDEC_DBW_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0x6
 405 #define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT                                                 0x8
 406 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_BANKS__SHIFT                                                            0xc
 407 #define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT                                              0x10
 408 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT                                                   0x13
 409 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT                                                             0x15
 410 #define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT                                                  0x18
 411 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT                                                        0x1a
 412 #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE__SHIFT                                                             0x1c
 413 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT                                                      0x1e
 414 #define UVD_UDEC_DBW_ADDR_CONFIG__SE_ENABLE__SHIFT                                                            0x1f
 415 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L
 416 #define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                   0x00000038L
 417 #define UVD_UDEC_DBW_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x000000C0L
 418 #define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK                                                   0x00000700L
 419 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_BANKS_MASK                                                              0x00007000L
 420 #define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK                                                0x00070000L
 421 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK                                                     0x00180000L
 422 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK                                                               0x00E00000L
 423 #define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK                                                    0x03000000L
 424 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_RB_PER_SE_MASK                                                          0x0C000000L
 425 #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK                                                               0x30000000L
 426 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES_MASK                                                        0x40000000L
 427 #define UVD_UDEC_DBW_ADDR_CONFIG__SE_ENABLE_MASK                                                              0x80000000L
 428 //UVD_SUVD_CGC_GATE
 429 #define UVD_SUVD_CGC_GATE__SRE__SHIFT                                                                         0x0
 430 #define UVD_SUVD_CGC_GATE__SIT__SHIFT                                                                         0x1
 431 #define UVD_SUVD_CGC_GATE__SMP__SHIFT                                                                         0x2
 432 #define UVD_SUVD_CGC_GATE__SCM__SHIFT                                                                         0x3
 433 #define UVD_SUVD_CGC_GATE__SDB__SHIFT                                                                         0x4
 434 #define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT                                                                    0x5
 435 #define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT                                                                    0x6
 436 #define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT                                                                    0x7
 437 #define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT                                                                    0x8
 438 #define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT                                                                    0x9
 439 #define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT                                                                    0xa
 440 #define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT                                                                    0xb
 441 #define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT                                                                    0xc
 442 #define UVD_SUVD_CGC_GATE__SCLR__SHIFT                                                                        0xd
 443 #define UVD_SUVD_CGC_GATE__UVD_SC__SHIFT                                                                      0xe
 444 #define UVD_SUVD_CGC_GATE__ENT__SHIFT                                                                         0xf
 445 #define UVD_SUVD_CGC_GATE__IME__SHIFT                                                                         0x10
 446 #define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT                                                                0x11
 447 #define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT                                                                0x12
 448 #define UVD_SUVD_CGC_GATE__SITE__SHIFT                                                                        0x13
 449 #define UVD_SUVD_CGC_GATE__SRE_VP9__SHIFT                                                                     0x14
 450 #define UVD_SUVD_CGC_GATE__SCM_VP9__SHIFT                                                                     0x15
 451 #define UVD_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT                                                                 0x16
 452 #define UVD_SUVD_CGC_GATE__SDB_VP9__SHIFT                                                                     0x17
 453 #define UVD_SUVD_CGC_GATE__IME_HEVC__SHIFT                                                                    0x18
 454 #define UVD_SUVD_CGC_GATE__SRE_MASK                                                                           0x00000001L
 455 #define UVD_SUVD_CGC_GATE__SIT_MASK                                                                           0x00000002L
 456 #define UVD_SUVD_CGC_GATE__SMP_MASK                                                                           0x00000004L
 457 #define UVD_SUVD_CGC_GATE__SCM_MASK                                                                           0x00000008L
 458 #define UVD_SUVD_CGC_GATE__SDB_MASK                                                                           0x00000010L
 459 #define UVD_SUVD_CGC_GATE__SRE_H264_MASK                                                                      0x00000020L
 460 #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK                                                                      0x00000040L
 461 #define UVD_SUVD_CGC_GATE__SIT_H264_MASK                                                                      0x00000080L
 462 #define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK                                                                      0x00000100L
 463 #define UVD_SUVD_CGC_GATE__SCM_H264_MASK                                                                      0x00000200L
 464 #define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK                                                                      0x00000400L
 465 #define UVD_SUVD_CGC_GATE__SDB_H264_MASK                                                                      0x00000800L
 466 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK                                                                      0x00001000L
 467 #define UVD_SUVD_CGC_GATE__SCLR_MASK                                                                          0x00002000L
 468 #define UVD_SUVD_CGC_GATE__UVD_SC_MASK                                                                        0x00004000L
 469 #define UVD_SUVD_CGC_GATE__ENT_MASK                                                                           0x00008000L
 470 #define UVD_SUVD_CGC_GATE__IME_MASK                                                                           0x00010000L
 471 #define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK                                                                  0x00020000L
 472 #define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK                                                                  0x00040000L
 473 #define UVD_SUVD_CGC_GATE__SITE_MASK                                                                          0x00080000L
 474 #define UVD_SUVD_CGC_GATE__SRE_VP9_MASK                                                                       0x00100000L
 475 #define UVD_SUVD_CGC_GATE__SCM_VP9_MASK                                                                       0x00200000L
 476 #define UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK                                                                   0x00400000L
 477 #define UVD_SUVD_CGC_GATE__SDB_VP9_MASK                                                                       0x00800000L
 478 #define UVD_SUVD_CGC_GATE__IME_HEVC_MASK                                                                      0x01000000L
 479 //UVD_SUVD_CGC_STATUS
 480 #define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT                                                                  0x0
 481 #define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT                                                                  0x1
 482 #define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT                                                                  0x2
 483 #define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT                                                                  0x3
 484 #define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT                                                                  0x4
 485 #define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT                                                                  0x5
 486 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT                                                             0x6
 487 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT                                                             0x7
 488 #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT                                                             0x8
 489 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT                                                             0x9
 490 #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT                                                             0xa
 491 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT                                                             0xb
 492 #define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT                                                             0xc
 493 #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT                                                             0xd
 494 #define UVD_SUVD_CGC_STATUS__SCLR_DCLK__SHIFT                                                                 0xe
 495 #define UVD_SUVD_CGC_STATUS__UVD_SC__SHIFT                                                                    0xf
 496 #define UVD_SUVD_CGC_STATUS__ENT_DCLK__SHIFT                                                                  0x10
 497 #define UVD_SUVD_CGC_STATUS__IME_DCLK__SHIFT                                                                  0x11
 498 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK__SHIFT                                                         0x12
 499 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK__SHIFT                                                         0x13
 500 #define UVD_SUVD_CGC_STATUS__SITE_DCLK__SHIFT                                                                 0x14
 501 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK__SHIFT                                                            0x15
 502 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK__SHIFT                                                        0x16
 503 #define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK__SHIFT                                                              0x17
 504 #define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK__SHIFT                                                              0x18
 505 #define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK__SHIFT                                                          0x19
 506 #define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK__SHIFT                                                              0x1a
 507 #define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK__SHIFT                                                             0x1b
 508 #define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK                                                                    0x00000001L
 509 #define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK                                                                    0x00000002L
 510 #define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK                                                                    0x00000004L
 511 #define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK                                                                    0x00000008L
 512 #define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK                                                                    0x00000010L
 513 #define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK                                                                    0x00000020L
 514 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK                                                               0x00000040L
 515 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK                                                               0x00000080L
 516 #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK                                                               0x00000100L
 517 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK                                                               0x00000200L
 518 #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK                                                               0x00000400L
 519 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK                                                               0x00000800L
 520 #define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK                                                               0x00001000L
 521 #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK                                                               0x00002000L
 522 #define UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK                                                                   0x00004000L
 523 #define UVD_SUVD_CGC_STATUS__UVD_SC_MASK                                                                      0x00008000L
 524 #define UVD_SUVD_CGC_STATUS__ENT_DCLK_MASK                                                                    0x00010000L
 525 #define UVD_SUVD_CGC_STATUS__IME_DCLK_MASK                                                                    0x00020000L
 526 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK_MASK                                                           0x00040000L
 527 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK_MASK                                                           0x00080000L
 528 #define UVD_SUVD_CGC_STATUS__SITE_DCLK_MASK                                                                   0x00100000L
 529 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK_MASK                                                              0x00200000L
 530 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK_MASK                                                          0x00400000L
 531 #define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK_MASK                                                                0x00800000L
 532 #define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK_MASK                                                                0x01000000L
 533 #define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK_MASK                                                            0x02000000L
 534 #define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK_MASK                                                                0x04000000L
 535 #define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK_MASK                                                               0x08000000L
 536 //UVD_SUVD_CGC_CTRL
 537 #define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT                                                                    0x0
 538 #define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT                                                                    0x1
 539 #define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT                                                                    0x2
 540 #define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT                                                                    0x3
 541 #define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT                                                                    0x4
 542 #define UVD_SUVD_CGC_CTRL__SCLR_MODE__SHIFT                                                                   0x5
 543 #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT                                                                 0x6
 544 #define UVD_SUVD_CGC_CTRL__ENT_MODE__SHIFT                                                                    0x7
 545 #define UVD_SUVD_CGC_CTRL__IME_MODE__SHIFT                                                                    0x8
 546 #define UVD_SUVD_CGC_CTRL__SITE_MODE__SHIFT                                                                   0x9
 547 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK                                                                      0x00000001L
 548 #define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK                                                                      0x00000002L
 549 #define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK                                                                      0x00000004L
 550 #define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK                                                                      0x00000008L
 551 #define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK                                                                      0x00000010L
 552 #define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK                                                                     0x00000020L
 553 #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK                                                                   0x00000040L
 554 #define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK                                                                      0x00000080L
 555 #define UVD_SUVD_CGC_CTRL__IME_MODE_MASK                                                                      0x00000100L
 556 #define UVD_SUVD_CGC_CTRL__SITE_MODE_MASK                                                                     0x00000200L
 557 //UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW
 558 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                   0x0
 559 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0_MASK                                                     0xFFFFFFFFL
 560 //UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH
 561 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                 0x0
 562 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32_MASK                                                   0xFFFFFFFFL
 563 //UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW
 564 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                   0x0
 565 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0_MASK                                                     0xFFFFFFFFL
 566 //UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH
 567 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                 0x0
 568 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32_MASK                                                   0xFFFFFFFFL
 569 //UVD_NO_OP
 570 #define UVD_NO_OP__NO_OP__SHIFT                                                                               0x0
 571 #define UVD_NO_OP__NO_OP_MASK                                                                                 0xFFFFFFFFL
 572 //UVD_VERSION
 573 #define UVD_VERSION__MINOR_VERSION__SHIFT                                                                     0x0
 574 #define UVD_VERSION__MAJOR_VERSION__SHIFT                                                                     0x10
 575 #define UVD_VERSION__MINOR_VERSION_MASK                                                                       0x0000FFFFL
 576 #define UVD_VERSION__MAJOR_VERSION_MASK                                                                       0xFFFF0000L
 577 //UVD_GP_SCRATCH8
 578 #define UVD_GP_SCRATCH8__DATA__SHIFT                                                                          0x0
 579 #define UVD_GP_SCRATCH8__DATA_MASK                                                                            0xFFFFFFFFL
 580 //UVD_GP_SCRATCH9
 581 #define UVD_GP_SCRATCH9__DATA__SHIFT                                                                          0x0
 582 #define UVD_GP_SCRATCH9__DATA_MASK                                                                            0xFFFFFFFFL
 583 //UVD_GP_SCRATCH10
 584 #define UVD_GP_SCRATCH10__DATA__SHIFT                                                                         0x0
 585 #define UVD_GP_SCRATCH10__DATA_MASK                                                                           0xFFFFFFFFL
 586 //UVD_GP_SCRATCH11
 587 #define UVD_GP_SCRATCH11__DATA__SHIFT                                                                         0x0
 588 #define UVD_GP_SCRATCH11__DATA_MASK                                                                           0xFFFFFFFFL
 589 //UVD_GP_SCRATCH12
 590 #define UVD_GP_SCRATCH12__DATA__SHIFT                                                                         0x0
 591 #define UVD_GP_SCRATCH12__DATA_MASK                                                                           0xFFFFFFFFL
 592 //UVD_GP_SCRATCH13
 593 #define UVD_GP_SCRATCH13__DATA__SHIFT                                                                         0x0
 594 #define UVD_GP_SCRATCH13__DATA_MASK                                                                           0xFFFFFFFFL
 595 //UVD_GP_SCRATCH14
 596 #define UVD_GP_SCRATCH14__DATA__SHIFT                                                                         0x0
 597 #define UVD_GP_SCRATCH14__DATA_MASK                                                                           0xFFFFFFFFL
 598 //UVD_GP_SCRATCH15
 599 #define UVD_GP_SCRATCH15__DATA__SHIFT                                                                         0x0
 600 #define UVD_GP_SCRATCH15__DATA_MASK                                                                           0xFFFFFFFFL
 601 //UVD_GP_SCRATCH16
 602 #define UVD_GP_SCRATCH16__DATA__SHIFT                                                                         0x0
 603 #define UVD_GP_SCRATCH16__DATA_MASK                                                                           0xFFFFFFFFL
 604 //UVD_GP_SCRATCH17
 605 #define UVD_GP_SCRATCH17__DATA__SHIFT                                                                         0x0
 606 #define UVD_GP_SCRATCH17__DATA_MASK                                                                           0xFFFFFFFFL
 607 //UVD_GP_SCRATCH18
 608 #define UVD_GP_SCRATCH18__DATA__SHIFT                                                                         0x0
 609 #define UVD_GP_SCRATCH18__DATA_MASK                                                                           0xFFFFFFFFL
 610 //UVD_GP_SCRATCH19
 611 #define UVD_GP_SCRATCH19__DATA__SHIFT                                                                         0x0
 612 #define UVD_GP_SCRATCH19__DATA_MASK                                                                           0xFFFFFFFFL
 613 //UVD_GP_SCRATCH20
 614 #define UVD_GP_SCRATCH20__DATA__SHIFT                                                                         0x0
 615 #define UVD_GP_SCRATCH20__DATA_MASK                                                                           0xFFFFFFFFL
 616 //UVD_GP_SCRATCH21
 617 #define UVD_GP_SCRATCH21__DATA__SHIFT                                                                         0x0
 618 #define UVD_GP_SCRATCH21__DATA_MASK                                                                           0xFFFFFFFFL
 619 //UVD_GP_SCRATCH22
 620 #define UVD_GP_SCRATCH22__DATA__SHIFT                                                                         0x0
 621 #define UVD_GP_SCRATCH22__DATA_MASK                                                                           0xFFFFFFFFL
 622 //UVD_GP_SCRATCH23
 623 #define UVD_GP_SCRATCH23__DATA__SHIFT                                                                         0x0
 624 #define UVD_GP_SCRATCH23__DATA_MASK                                                                           0xFFFFFFFFL
 625 //UVD_RB_BASE_LO2
 626 #define UVD_RB_BASE_LO2__RB_BASE_LO__SHIFT                                                                    0x6
 627 #define UVD_RB_BASE_LO2__RB_BASE_LO_MASK                                                                      0xFFFFFFC0L
 628 //UVD_RB_BASE_HI2
 629 #define UVD_RB_BASE_HI2__RB_BASE_HI__SHIFT                                                                    0x0
 630 #define UVD_RB_BASE_HI2__RB_BASE_HI_MASK                                                                      0xFFFFFFFFL
 631 //UVD_RB_SIZE2
 632 #define UVD_RB_SIZE2__RB_SIZE__SHIFT                                                                          0x4
 633 #define UVD_RB_SIZE2__RB_SIZE_MASK                                                                            0x007FFFF0L
 634 //UVD_RB_RPTR2
 635 #define UVD_RB_RPTR2__RB_RPTR__SHIFT                                                                          0x4
 636 #define UVD_RB_RPTR2__RB_RPTR_MASK                                                                            0x007FFFF0L
 637 //UVD_RB_WPTR2
 638 #define UVD_RB_WPTR2__RB_WPTR__SHIFT                                                                          0x4
 639 #define UVD_RB_WPTR2__RB_WPTR_MASK                                                                            0x007FFFF0L
 640 //UVD_RB_BASE_LO
 641 #define UVD_RB_BASE_LO__RB_BASE_LO__SHIFT                                                                     0x6
 642 #define UVD_RB_BASE_LO__RB_BASE_LO_MASK                                                                       0xFFFFFFC0L
 643 //UVD_RB_BASE_HI
 644 #define UVD_RB_BASE_HI__RB_BASE_HI__SHIFT                                                                     0x0
 645 #define UVD_RB_BASE_HI__RB_BASE_HI_MASK                                                                       0xFFFFFFFFL
 646 //UVD_RB_SIZE
 647 #define UVD_RB_SIZE__RB_SIZE__SHIFT                                                                           0x4
 648 #define UVD_RB_SIZE__RB_SIZE_MASK                                                                             0x007FFFF0L
 649 //UVD_RB_RPTR
 650 #define UVD_RB_RPTR__RB_RPTR__SHIFT                                                                           0x4
 651 #define UVD_RB_RPTR__RB_RPTR_MASK                                                                             0x007FFFF0L
 652 //UVD_RB_WPTR
 653 #define UVD_RB_WPTR__RB_WPTR__SHIFT                                                                           0x4
 654 #define UVD_RB_WPTR__RB_WPTR_MASK                                                                             0x007FFFF0L
 655 //UVD_RB_WPTR4
 656 #define UVD_RB_WPTR4__RB_WPTR__SHIFT                                                                          0x4
 657 #define UVD_RB_WPTR4__RB_WPTR_MASK                                                                            0x007FFFF0L
 658 //UVD_JRBC_RB_RPTR
 659 #define UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT                                                                      0x4
 660 #define UVD_JRBC_RB_RPTR__RB_RPTR_MASK                                                                        0x007FFFF0L
 661 //UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH
 662 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                  0x0
 663 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK                                                    0xFFFFFFFFL
 664 //UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW
 665 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                    0x0
 666 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK                                                      0xFFFFFFFFL
 667 //UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH
 668 #define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                    0x0
 669 #define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK                                                      0xFFFFFFFFL
 670 //UVD_LMI_VCPU_NC1_64BIT_BAR_LOW
 671 #define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                      0x0
 672 #define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0_MASK                                                        0xFFFFFFFFL
 673 //UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH
 674 #define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                    0x0
 675 #define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK                                                      0xFFFFFFFFL
 676 //UVD_LMI_VCPU_NC0_64BIT_BAR_LOW
 677 #define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                      0x0
 678 #define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0_MASK                                                        0xFFFFFFFFL
 679 //UVD_LMI_LBSI_64BIT_BAR_HIGH
 680 #define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                        0x0
 681 #define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32_MASK                                                          0xFFFFFFFFL
 682 //UVD_LMI_LBSI_64BIT_BAR_LOW
 683 #define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                          0x0
 684 #define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0_MASK                                                            0xFFFFFFFFL
 685 //UVD_LMI_RBC_IB_64BIT_BAR_HIGH
 686 #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                      0x0
 687 #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK                                                        0xFFFFFFFFL
 688 //UVD_LMI_RBC_IB_64BIT_BAR_LOW
 689 #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                        0x0
 690 #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK                                                          0xFFFFFFFFL
 691 //UVD_LMI_RBC_RB_64BIT_BAR_HIGH
 692 #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                      0x0
 693 #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK                                                        0xFFFFFFFFL
 694 //UVD_LMI_RBC_RB_64BIT_BAR_LOW
 695 #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                        0x0
 696 #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK                                                          0xFFFFFFFFL
 697 
 698 
 699 // addressBlock: uvd_uvddec
 700 //UVD_SEMA_CNTL
 701 #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT                                                                    0x0
 702 #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT                                                               0x1
 703 #define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK                                                                      0x00000001L
 704 #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK                                                                 0x00000002L
 705 //UVD_LMI_JRBC_RB_64BIT_BAR_LOW
 706 #define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                       0x0
 707 #define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK                                                         0xFFFFFFFFL
 708 //UVD_LMI_JRBC_RB_64BIT_BAR_HIGH
 709 #define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                     0x0
 710 #define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK                                                       0xFFFFFFFFL
 711 //UVD_LMI_JRBC_IB_64BIT_BAR_LOW
 712 #define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                       0x0
 713 #define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK                                                         0xFFFFFFFFL
 714 //UVD_LMI_JRBC_IB_64BIT_BAR_HIGH
 715 #define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                     0x0
 716 #define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK                                                       0xFFFFFFFFL
 717 //UVD_LMI_JRBC_IB_VMID
 718 #define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID__SHIFT                                                               0x0
 719 #define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID__SHIFT                                                               0x4
 720 #define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID_MASK                                                                 0x0000000FL
 721 #define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID_MASK                                                                 0x000000F0L
 722 //UVD_JRBC_RB_WPTR
 723 #define UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT                                                                      0x4
 724 #define UVD_JRBC_RB_WPTR__RB_WPTR_MASK                                                                        0x007FFFF0L
 725 //UVD_JRBC_RB_CNTL
 726 #define UVD_JRBC_RB_CNTL__RB_NO_FETCH__SHIFT                                                                  0x0
 727 #define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT                                                                0x1
 728 #define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT                                                           0x4
 729 #define UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK                                                                    0x00000001L
 730 #define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK                                                                  0x00000002L
 731 #define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK                                                             0x0007FFF0L
 732 //UVD_JRBC_IB_SIZE
 733 #define UVD_JRBC_IB_SIZE__IB_SIZE__SHIFT                                                                      0x4
 734 #define UVD_JRBC_IB_SIZE__IB_SIZE_MASK                                                                        0x007FFFF0L
 735 //UVD_JRBC_LMI_SWAP_CNTL
 736 #define UVD_JRBC_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT                                                             0x0
 737 #define UVD_JRBC_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT                                                             0x2
 738 #define UVD_JRBC_LMI_SWAP_CNTL__RB_MC_SWAP_MASK                                                               0x00000003L
 739 #define UVD_JRBC_LMI_SWAP_CNTL__IB_MC_SWAP_MASK                                                               0x0000000CL
 740 //UVD_JRBC_SOFT_RESET
 741 #define UVD_JRBC_SOFT_RESET__RESET__SHIFT                                                                     0x0
 742 #define UVD_JRBC_SOFT_RESET__VCLK_RESET_STATUS__SHIFT                                                         0x10
 743 #define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT                                                         0x11
 744 #define UVD_JRBC_SOFT_RESET__RESET_MASK                                                                       0x00000001L
 745 #define UVD_JRBC_SOFT_RESET__VCLK_RESET_STATUS_MASK                                                           0x00010000L
 746 #define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS_MASK                                                           0x00020000L
 747 //UVD_JRBC_STATUS
 748 #define UVD_JRBC_STATUS__RB_JOB_DONE__SHIFT                                                                   0x0
 749 #define UVD_JRBC_STATUS__IB_JOB_DONE__SHIFT                                                                   0x1
 750 #define UVD_JRBC_STATUS__RB_ILLEGAL_CMD__SHIFT                                                                0x2
 751 #define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT                                                        0x3
 752 #define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT                                                             0x4
 753 #define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT                                                             0x5
 754 #define UVD_JRBC_STATUS__IB_ILLEGAL_CMD__SHIFT                                                                0x6
 755 #define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT                                                        0x7
 756 #define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT                                                             0x8
 757 #define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT                                                             0x9
 758 #define UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT                                                                0xa
 759 #define UVD_JRBC_STATUS__PREEMPT_STATUS__SHIFT                                                                0xb
 760 #define UVD_JRBC_STATUS__IB_TRAP_STATUS__SHIFT                                                                0xc
 761 #define UVD_JRBC_STATUS__INT_EN__SHIFT                                                                        0x10
 762 #define UVD_JRBC_STATUS__INT_ACK__SHIFT                                                                       0x11
 763 #define UVD_JRBC_STATUS__RB_JOB_DONE_MASK                                                                     0x00000001L
 764 #define UVD_JRBC_STATUS__IB_JOB_DONE_MASK                                                                     0x00000002L
 765 #define UVD_JRBC_STATUS__RB_ILLEGAL_CMD_MASK                                                                  0x00000004L
 766 #define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK                                                          0x00000008L
 767 #define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK                                                               0x00000010L
 768 #define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT_MASK                                                               0x00000020L
 769 #define UVD_JRBC_STATUS__IB_ILLEGAL_CMD_MASK                                                                  0x00000040L
 770 #define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK                                                          0x00000080L
 771 #define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT_MASK                                                               0x00000100L
 772 #define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT_MASK                                                               0x00000200L
 773 #define UVD_JRBC_STATUS__RB_TRAP_STATUS_MASK                                                                  0x00000400L
 774 #define UVD_JRBC_STATUS__PREEMPT_STATUS_MASK                                                                  0x00000800L
 775 #define UVD_JRBC_STATUS__IB_TRAP_STATUS_MASK                                                                  0x00001000L
 776 #define UVD_JRBC_STATUS__INT_EN_MASK                                                                          0x00010000L
 777 #define UVD_JRBC_STATUS__INT_ACK_MASK                                                                         0x00020000L
 778 //UVD_RB_RPTR3
 779 #define UVD_RB_RPTR3__RB_RPTR__SHIFT                                                                          0x4
 780 #define UVD_RB_RPTR3__RB_RPTR_MASK                                                                            0x007FFFF0L
 781 //UVD_RB_WPTR3
 782 #define UVD_RB_WPTR3__RB_WPTR__SHIFT                                                                          0x4
 783 #define UVD_RB_WPTR3__RB_WPTR_MASK                                                                            0x007FFFF0L
 784 //UVD_RB_BASE_LO3
 785 #define UVD_RB_BASE_LO3__RB_BASE_LO__SHIFT                                                                    0x6
 786 #define UVD_RB_BASE_LO3__RB_BASE_LO_MASK                                                                      0xFFFFFFC0L
 787 //UVD_RB_BASE_HI3
 788 #define UVD_RB_BASE_HI3__RB_BASE_HI__SHIFT                                                                    0x0
 789 #define UVD_RB_BASE_HI3__RB_BASE_HI_MASK                                                                      0xFFFFFFFFL
 790 //UVD_RB_SIZE3
 791 #define UVD_RB_SIZE3__RB_SIZE__SHIFT                                                                          0x4
 792 #define UVD_RB_SIZE3__RB_SIZE_MASK                                                                            0x007FFFF0L
 793 //JPEG_CGC_GATE
 794 #define JPEG_CGC_GATE__JPEG__SHIFT                                                                            0x14
 795 #define JPEG_CGC_GATE__JPEG2__SHIFT                                                                           0x15
 796 #define JPEG_CGC_GATE__JPEG_MASK                                                                              0x00100000L
 797 #define JPEG_CGC_GATE__JPEG2_MASK                                                                             0x00200000L
 798 //UVD_CTX_INDEX
 799 #define UVD_CTX_INDEX__INDEX__SHIFT                                                                           0x0
 800 #define UVD_CTX_INDEX__INDEX_MASK                                                                             0x000001FFL
 801 //UVD_CTX_DATA
 802 #define UVD_CTX_DATA__DATA__SHIFT                                                                             0x0
 803 #define UVD_CTX_DATA__DATA_MASK                                                                               0xFFFFFFFFL
 804 //UVD_CGC_GATE
 805 #define UVD_CGC_GATE__SYS__SHIFT                                                                              0x0
 806 #define UVD_CGC_GATE__UDEC__SHIFT                                                                             0x1
 807 #define UVD_CGC_GATE__MPEG2__SHIFT                                                                            0x2
 808 #define UVD_CGC_GATE__REGS__SHIFT                                                                             0x3
 809 #define UVD_CGC_GATE__RBC__SHIFT                                                                              0x4
 810 #define UVD_CGC_GATE__LMI_MC__SHIFT                                                                           0x5
 811 #define UVD_CGC_GATE__LMI_UMC__SHIFT                                                                          0x6
 812 #define UVD_CGC_GATE__IDCT__SHIFT                                                                             0x7
 813 #define UVD_CGC_GATE__MPRD__SHIFT                                                                             0x8
 814 #define UVD_CGC_GATE__MPC__SHIFT                                                                              0x9
 815 #define UVD_CGC_GATE__LBSI__SHIFT                                                                             0xa
 816 #define UVD_CGC_GATE__LRBBM__SHIFT                                                                            0xb
 817 #define UVD_CGC_GATE__UDEC_RE__SHIFT                                                                          0xc
 818 #define UVD_CGC_GATE__UDEC_CM__SHIFT                                                                          0xd
 819 #define UVD_CGC_GATE__UDEC_IT__SHIFT                                                                          0xe
 820 #define UVD_CGC_GATE__UDEC_DB__SHIFT                                                                          0xf
 821 #define UVD_CGC_GATE__UDEC_MP__SHIFT                                                                          0x10
 822 #define UVD_CGC_GATE__WCB__SHIFT                                                                              0x11
 823 #define UVD_CGC_GATE__VCPU__SHIFT                                                                             0x12
 824 #define UVD_CGC_GATE__SCPU__SHIFT                                                                             0x13
 825 #define UVD_CGC_GATE__SYS_MASK                                                                                0x00000001L
 826 #define UVD_CGC_GATE__UDEC_MASK                                                                               0x00000002L
 827 #define UVD_CGC_GATE__MPEG2_MASK                                                                              0x00000004L
 828 #define UVD_CGC_GATE__REGS_MASK                                                                               0x00000008L
 829 #define UVD_CGC_GATE__RBC_MASK                                                                                0x00000010L
 830 #define UVD_CGC_GATE__LMI_MC_MASK                                                                             0x00000020L
 831 #define UVD_CGC_GATE__LMI_UMC_MASK                                                                            0x00000040L
 832 #define UVD_CGC_GATE__IDCT_MASK                                                                               0x00000080L
 833 #define UVD_CGC_GATE__MPRD_MASK                                                                               0x00000100L
 834 #define UVD_CGC_GATE__MPC_MASK                                                                                0x00000200L
 835 #define UVD_CGC_GATE__LBSI_MASK                                                                               0x00000400L
 836 #define UVD_CGC_GATE__LRBBM_MASK                                                                              0x00000800L
 837 #define UVD_CGC_GATE__UDEC_RE_MASK                                                                            0x00001000L
 838 #define UVD_CGC_GATE__UDEC_CM_MASK                                                                            0x00002000L
 839 #define UVD_CGC_GATE__UDEC_IT_MASK                                                                            0x00004000L
 840 #define UVD_CGC_GATE__UDEC_DB_MASK                                                                            0x00008000L
 841 #define UVD_CGC_GATE__UDEC_MP_MASK                                                                            0x00010000L
 842 #define UVD_CGC_GATE__WCB_MASK                                                                                0x00020000L
 843 #define UVD_CGC_GATE__VCPU_MASK                                                                               0x00040000L
 844 #define UVD_CGC_GATE__SCPU_MASK                                                                               0x00080000L
 845 //UVD_CGC_STATUS
 846 #define UVD_CGC_STATUS__SYS_SCLK__SHIFT                                                                       0x0
 847 #define UVD_CGC_STATUS__SYS_DCLK__SHIFT                                                                       0x1
 848 #define UVD_CGC_STATUS__SYS_VCLK__SHIFT                                                                       0x2
 849 #define UVD_CGC_STATUS__UDEC_SCLK__SHIFT                                                                      0x3
 850 #define UVD_CGC_STATUS__UDEC_DCLK__SHIFT                                                                      0x4
 851 #define UVD_CGC_STATUS__UDEC_VCLK__SHIFT                                                                      0x5
 852 #define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT                                                                     0x6
 853 #define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT                                                                     0x7
 854 #define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT                                                                     0x8
 855 #define UVD_CGC_STATUS__REGS_SCLK__SHIFT                                                                      0x9
 856 #define UVD_CGC_STATUS__REGS_VCLK__SHIFT                                                                      0xa
 857 #define UVD_CGC_STATUS__RBC_SCLK__SHIFT                                                                       0xb
 858 #define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT                                                                    0xc
 859 #define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT                                                                   0xd
 860 #define UVD_CGC_STATUS__IDCT_SCLK__SHIFT                                                                      0xe
 861 #define UVD_CGC_STATUS__IDCT_VCLK__SHIFT                                                                      0xf
 862 #define UVD_CGC_STATUS__MPRD_SCLK__SHIFT                                                                      0x10
 863 #define UVD_CGC_STATUS__MPRD_DCLK__SHIFT                                                                      0x11
 864 #define UVD_CGC_STATUS__MPRD_VCLK__SHIFT                                                                      0x12
 865 #define UVD_CGC_STATUS__MPC_SCLK__SHIFT                                                                       0x13
 866 #define UVD_CGC_STATUS__MPC_DCLK__SHIFT                                                                       0x14
 867 #define UVD_CGC_STATUS__LBSI_SCLK__SHIFT                                                                      0x15
 868 #define UVD_CGC_STATUS__LBSI_VCLK__SHIFT                                                                      0x16
 869 #define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT                                                                     0x17
 870 #define UVD_CGC_STATUS__WCB_SCLK__SHIFT                                                                       0x18
 871 #define UVD_CGC_STATUS__VCPU_SCLK__SHIFT                                                                      0x19
 872 #define UVD_CGC_STATUS__VCPU_VCLK__SHIFT                                                                      0x1a
 873 #define UVD_CGC_STATUS__SCPU_SCLK__SHIFT                                                                      0x1b
 874 #define UVD_CGC_STATUS__SCPU_VCLK__SHIFT                                                                      0x1c
 875 #define UVD_CGC_STATUS__ALL_ENC_ACTIVE__SHIFT                                                                 0x1d
 876 #define UVD_CGC_STATUS__JPEG_ACTIVE__SHIFT                                                                    0x1e
 877 #define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT                                                                 0x1f
 878 #define UVD_CGC_STATUS__SYS_SCLK_MASK                                                                         0x00000001L
 879 #define UVD_CGC_STATUS__SYS_DCLK_MASK                                                                         0x00000002L
 880 #define UVD_CGC_STATUS__SYS_VCLK_MASK                                                                         0x00000004L
 881 #define UVD_CGC_STATUS__UDEC_SCLK_MASK                                                                        0x00000008L
 882 #define UVD_CGC_STATUS__UDEC_DCLK_MASK                                                                        0x00000010L
 883 #define UVD_CGC_STATUS__UDEC_VCLK_MASK                                                                        0x00000020L
 884 #define UVD_CGC_STATUS__MPEG2_SCLK_MASK                                                                       0x00000040L
 885 #define UVD_CGC_STATUS__MPEG2_DCLK_MASK                                                                       0x00000080L
 886 #define UVD_CGC_STATUS__MPEG2_VCLK_MASK                                                                       0x00000100L
 887 #define UVD_CGC_STATUS__REGS_SCLK_MASK                                                                        0x00000200L
 888 #define UVD_CGC_STATUS__REGS_VCLK_MASK                                                                        0x00000400L
 889 #define UVD_CGC_STATUS__RBC_SCLK_MASK                                                                         0x00000800L
 890 #define UVD_CGC_STATUS__LMI_MC_SCLK_MASK                                                                      0x00001000L
 891 #define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK                                                                     0x00002000L
 892 #define UVD_CGC_STATUS__IDCT_SCLK_MASK                                                                        0x00004000L
 893 #define UVD_CGC_STATUS__IDCT_VCLK_MASK                                                                        0x00008000L
 894 #define UVD_CGC_STATUS__MPRD_SCLK_MASK                                                                        0x00010000L
 895 #define UVD_CGC_STATUS__MPRD_DCLK_MASK                                                                        0x00020000L
 896 #define UVD_CGC_STATUS__MPRD_VCLK_MASK                                                                        0x00040000L
 897 #define UVD_CGC_STATUS__MPC_SCLK_MASK                                                                         0x00080000L
 898 #define UVD_CGC_STATUS__MPC_DCLK_MASK                                                                         0x00100000L
 899 #define UVD_CGC_STATUS__LBSI_SCLK_MASK                                                                        0x00200000L
 900 #define UVD_CGC_STATUS__LBSI_VCLK_MASK                                                                        0x00400000L
 901 #define UVD_CGC_STATUS__LRBBM_SCLK_MASK                                                                       0x00800000L
 902 #define UVD_CGC_STATUS__WCB_SCLK_MASK                                                                         0x01000000L
 903 #define UVD_CGC_STATUS__VCPU_SCLK_MASK                                                                        0x02000000L
 904 #define UVD_CGC_STATUS__VCPU_VCLK_MASK                                                                        0x04000000L
 905 #define UVD_CGC_STATUS__SCPU_SCLK_MASK                                                                        0x08000000L
 906 #define UVD_CGC_STATUS__SCPU_VCLK_MASK                                                                        0x10000000L
 907 #define UVD_CGC_STATUS__ALL_ENC_ACTIVE_MASK                                                                   0x20000000L
 908 #define UVD_CGC_STATUS__JPEG_ACTIVE_MASK                                                                      0x40000000L
 909 #define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK                                                                   0x80000000L
 910 //UVD_CGC_CTRL
 911 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT                                                                   0x0
 912 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT                                                               0x2
 913 #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT                                                                    0x6
 914 #define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT                                                                     0xb
 915 #define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT                                                                     0xc
 916 #define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT                                                                     0xd
 917 #define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT                                                                     0xe
 918 #define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT                                                                     0xf
 919 #define UVD_CGC_CTRL__SYS_MODE__SHIFT                                                                         0x10
 920 #define UVD_CGC_CTRL__UDEC_MODE__SHIFT                                                                        0x11
 921 #define UVD_CGC_CTRL__MPEG2_MODE__SHIFT                                                                       0x12
 922 #define UVD_CGC_CTRL__REGS_MODE__SHIFT                                                                        0x13
 923 #define UVD_CGC_CTRL__RBC_MODE__SHIFT                                                                         0x14
 924 #define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT                                                                      0x15
 925 #define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT                                                                     0x16
 926 #define UVD_CGC_CTRL__IDCT_MODE__SHIFT                                                                        0x17
 927 #define UVD_CGC_CTRL__MPRD_MODE__SHIFT                                                                        0x18
 928 #define UVD_CGC_CTRL__MPC_MODE__SHIFT                                                                         0x19
 929 #define UVD_CGC_CTRL__LBSI_MODE__SHIFT                                                                        0x1a
 930 #define UVD_CGC_CTRL__LRBBM_MODE__SHIFT                                                                       0x1b
 931 #define UVD_CGC_CTRL__WCB_MODE__SHIFT                                                                         0x1c
 932 #define UVD_CGC_CTRL__VCPU_MODE__SHIFT                                                                        0x1d
 933 #define UVD_CGC_CTRL__SCPU_MODE__SHIFT                                                                        0x1e
 934 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK                                                                     0x00000001L
 935 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK                                                                 0x0000003CL
 936 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK                                                                      0x000007C0L
 937 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK                                                                       0x00000800L
 938 #define UVD_CGC_CTRL__UDEC_CM_MODE_MASK                                                                       0x00001000L
 939 #define UVD_CGC_CTRL__UDEC_IT_MODE_MASK                                                                       0x00002000L
 940 #define UVD_CGC_CTRL__UDEC_DB_MODE_MASK                                                                       0x00004000L
 941 #define UVD_CGC_CTRL__UDEC_MP_MODE_MASK                                                                       0x00008000L
 942 #define UVD_CGC_CTRL__SYS_MODE_MASK                                                                           0x00010000L
 943 #define UVD_CGC_CTRL__UDEC_MODE_MASK                                                                          0x00020000L
 944 #define UVD_CGC_CTRL__MPEG2_MODE_MASK                                                                         0x00040000L
 945 #define UVD_CGC_CTRL__REGS_MODE_MASK                                                                          0x00080000L
 946 #define UVD_CGC_CTRL__RBC_MODE_MASK                                                                           0x00100000L
 947 #define UVD_CGC_CTRL__LMI_MC_MODE_MASK                                                                        0x00200000L
 948 #define UVD_CGC_CTRL__LMI_UMC_MODE_MASK                                                                       0x00400000L
 949 #define UVD_CGC_CTRL__IDCT_MODE_MASK                                                                          0x00800000L
 950 #define UVD_CGC_CTRL__MPRD_MODE_MASK                                                                          0x01000000L
 951 #define UVD_CGC_CTRL__MPC_MODE_MASK                                                                           0x02000000L
 952 #define UVD_CGC_CTRL__LBSI_MODE_MASK                                                                          0x04000000L
 953 #define UVD_CGC_CTRL__LRBBM_MODE_MASK                                                                         0x08000000L
 954 #define UVD_CGC_CTRL__WCB_MODE_MASK                                                                           0x10000000L
 955 #define UVD_CGC_CTRL__VCPU_MODE_MASK                                                                          0x20000000L
 956 #define UVD_CGC_CTRL__SCPU_MODE_MASK                                                                          0x40000000L
 957 //UVD_GP_SCRATCH0
 958 #define UVD_GP_SCRATCH0__DATA__SHIFT                                                                          0x0
 959 #define UVD_GP_SCRATCH0__DATA_MASK                                                                            0xFFFFFFFFL
 960 //UVD_GP_SCRATCH1
 961 #define UVD_GP_SCRATCH1__DATA__SHIFT                                                                          0x0
 962 #define UVD_GP_SCRATCH1__DATA_MASK                                                                            0xFFFFFFFFL
 963 //UVD_GP_SCRATCH2
 964 #define UVD_GP_SCRATCH2__DATA__SHIFT                                                                          0x0
 965 #define UVD_GP_SCRATCH2__DATA_MASK                                                                            0xFFFFFFFFL
 966 //UVD_GP_SCRATCH3
 967 #define UVD_GP_SCRATCH3__DATA__SHIFT                                                                          0x0
 968 #define UVD_GP_SCRATCH3__DATA_MASK                                                                            0xFFFFFFFFL
 969 //UVD_GP_SCRATCH4
 970 #define UVD_GP_SCRATCH4__DATA__SHIFT                                                                          0x0
 971 #define UVD_GP_SCRATCH4__DATA_MASK                                                                            0xFFFFFFFFL
 972 //UVD_GP_SCRATCH5
 973 #define UVD_GP_SCRATCH5__DATA__SHIFT                                                                          0x0
 974 #define UVD_GP_SCRATCH5__DATA_MASK                                                                            0xFFFFFFFFL
 975 //UVD_GP_SCRATCH6
 976 #define UVD_GP_SCRATCH6__DATA__SHIFT                                                                          0x0
 977 #define UVD_GP_SCRATCH6__DATA_MASK                                                                            0xFFFFFFFFL
 978 //UVD_GP_SCRATCH7
 979 #define UVD_GP_SCRATCH7__DATA__SHIFT                                                                          0x0
 980 #define UVD_GP_SCRATCH7__DATA_MASK                                                                            0xFFFFFFFFL
 981 //UVD_LMI_VCPU_CACHE_VMID
 982 #define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT                                                       0x0
 983 #define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK                                                         0x0000000FL
 984 //UVD_LMI_CTRL2
 985 #define UVD_LMI_CTRL2__SPH_DIS__SHIFT                                                                         0x0
 986 #define UVD_LMI_CTRL2__STALL_ARB__SHIFT                                                                       0x1
 987 #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT                                                               0x2
 988 #define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT                                                                 0x3
 989 #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT                                                           0x7
 990 #define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT                                                                   0x8
 991 #define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT                                                                  0x9
 992 #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT                                                                 0xb
 993 #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT                                                          0x11
 994 #define UVD_LMI_CTRL2__SPH_DIS_MASK                                                                           0x00000001L
 995 #define UVD_LMI_CTRL2__STALL_ARB_MASK                                                                         0x00000002L
 996 #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK                                                                 0x00000004L
 997 #define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK                                                                   0x00000008L
 998 #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK                                                             0x00000080L
 999 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK                                                                     0x00000100L
1000 #define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK                                                                    0x00000600L
1001 #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK                                                                   0x00001800L
1002 #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK                                                            0x01FE0000L
1003 //UVD_MASTINT_EN
1004 #define UVD_MASTINT_EN__OVERRUN_RST__SHIFT                                                                    0x0
1005 #define UVD_MASTINT_EN__VCPU_EN__SHIFT                                                                        0x1
1006 #define UVD_MASTINT_EN__SYS_EN__SHIFT                                                                         0x2
1007 #define UVD_MASTINT_EN__INT_OVERRUN__SHIFT                                                                    0x4
1008 #define UVD_MASTINT_EN__OVERRUN_RST_MASK                                                                      0x00000001L
1009 #define UVD_MASTINT_EN__VCPU_EN_MASK                                                                          0x00000002L
1010 #define UVD_MASTINT_EN__SYS_EN_MASK                                                                           0x00000004L
1011 #define UVD_MASTINT_EN__INT_OVERRUN_MASK                                                                      0x007FFFF0L
1012 //UVD_SYS_INT_EN
1013 #define UVD_SYS_INT_EN__UVD_JRBC_EN__SHIFT                                                                    0x4
1014 #define UVD_SYS_INT_EN__UVD_JRBC_EN_MASK                                                                      0x00000010L
1015 //JPEG_CGC_CTRL
1016 #define JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT                                                                  0x0
1017 #define JPEG_CGC_CTRL__JPEG2_MODE__SHIFT                                                                      0x1
1018 #define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT                                                              0x2
1019 #define JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT                                                                   0x6
1020 #define JPEG_CGC_CTRL__JPEG_MODE__SHIFT                                                                       0x1f
1021 #define JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK                                                                    0x00000001L
1022 #define JPEG_CGC_CTRL__JPEG2_MODE_MASK                                                                        0x00000002L
1023 #define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK                                                                0x0000003CL
1024 #define JPEG_CGC_CTRL__CLK_OFF_DELAY_MASK                                                                     0x000007C0L
1025 #define JPEG_CGC_CTRL__JPEG_MODE_MASK                                                                         0x80000000L
1026 //UVD_LMI_CTRL
1027 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT                                                                0x0
1028 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT                                                             0x8
1029 #define UVD_LMI_CTRL__REQ_MODE__SHIFT                                                                         0x9
1030 #define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT                                                                 0xb
1031 #define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT                                                                   0xc
1032 #define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT                                                                0xd
1033 #define UVD_LMI_CTRL__CRC_RESET__SHIFT                                                                        0xe
1034 #define UVD_LMI_CTRL__CRC_SEL__SHIFT                                                                          0xf
1035 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT                                                           0x15
1036 #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT                                                             0x16
1037 #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT                                                          0x17
1038 #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT                                                          0x18
1039 #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT                                                          0x19
1040 #define UVD_LMI_CTRL__RFU__SHIFT                                                                              0x1b
1041 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK                                                                  0x000000FFL
1042 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK                                                               0x00000100L
1043 #define UVD_LMI_CTRL__REQ_MODE_MASK                                                                           0x00000200L
1044 #define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK                                                                   0x00000800L
1045 #define UVD_LMI_CTRL__MASK_MC_URGENT_MASK                                                                     0x00001000L
1046 #define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK                                                                  0x00002000L
1047 #define UVD_LMI_CTRL__CRC_RESET_MASK                                                                          0x00004000L
1048 #define UVD_LMI_CTRL__CRC_SEL_MASK                                                                            0x000F8000L
1049 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK                                                             0x00200000L
1050 #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK                                                               0x00400000L
1051 #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK                                                            0x00800000L
1052 #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK                                                            0x01000000L
1053 #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK                                                            0x02000000L
1054 #define UVD_LMI_CTRL__RFU_MASK                                                                                0xF8000000L
1055 //UVD_LMI_STATUS
1056 #define UVD_LMI_STATUS__READ_CLEAN__SHIFT                                                                     0x0
1057 #define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT                                                                    0x1
1058 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT                                                                0x2
1059 #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT                                                           0x3
1060 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT                                                            0x6
1061 #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT                                                             0x9
1062 #define UVD_LMI_STATUS__READ_CLEAN_MASK                                                                       0x00000001L
1063 #define UVD_LMI_STATUS__WRITE_CLEAN_MASK                                                                      0x00000002L
1064 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK                                                                  0x00000004L
1065 #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK                                                             0x00000008L
1066 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK                                                              0x00000040L
1067 #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK                                                               0x00000200L
1068 //UVD_LMI_SWAP_CNTL
1069 #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT                                                                  0x0
1070 #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT                                                                  0x2
1071 #define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT                                                             0x4
1072 #define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT                                                              0x6
1073 #define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT                                                              0x8
1074 #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT                                                                  0xa
1075 #define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT                                                                  0xc
1076 #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT                                                                0xe
1077 #define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT                                                                0x10
1078 #define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT                                                                 0x12
1079 #define UVD_LMI_SWAP_CNTL__ACAP_MC_SWAP__SHIFT                                                                0x14
1080 #define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT                                                            0x16
1081 #define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT                                                                 0x18
1082 #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT                                                               0x1a
1083 #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT                                                                  0x1c
1084 #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT                                                                  0x1e
1085 #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK                                                                    0x00000003L
1086 #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK                                                                    0x0000000CL
1087 #define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK                                                               0x00000030L
1088 #define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK                                                                0x000000C0L
1089 #define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK                                                                0x00000300L
1090 #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK                                                                    0x00000C00L
1091 #define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK                                                                    0x00003000L
1092 #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK                                                                  0x0000C000L
1093 #define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK                                                                  0x00030000L
1094 #define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK                                                                   0x000C0000L
1095 #define UVD_LMI_SWAP_CNTL__ACAP_MC_SWAP_MASK                                                                  0x00300000L
1096 #define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK                                                              0x00C00000L
1097 #define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK                                                                   0x03000000L
1098 #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK                                                                 0x0C000000L
1099 #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK                                                                    0x30000000L
1100 #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK                                                                    0xC0000000L
1101 //UVD_MPC_CNTL
1102 #define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT                                                                 0x3
1103 #define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK                                                                   0x00000038L
1104 //UVD_MPC_SET_MUXA0
1105 #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT                                                                      0x0
1106 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT                                                                      0x6
1107 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT                                                                      0xc
1108 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT                                                                      0x12
1109 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT                                                                      0x18
1110 #define UVD_MPC_SET_MUXA0__VARA_0_MASK                                                                        0x0000003FL
1111 #define UVD_MPC_SET_MUXA0__VARA_1_MASK                                                                        0x00000FC0L
1112 #define UVD_MPC_SET_MUXA0__VARA_2_MASK                                                                        0x0003F000L
1113 #define UVD_MPC_SET_MUXA0__VARA_3_MASK                                                                        0x00FC0000L
1114 #define UVD_MPC_SET_MUXA0__VARA_4_MASK                                                                        0x3F000000L
1115 //UVD_MPC_SET_MUXA1
1116 #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT                                                                      0x0
1117 #define UVD_MPC_SET_MUXA1__VARA_6__SHIFT                                                                      0x6
1118 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT                                                                      0xc
1119 #define UVD_MPC_SET_MUXA1__VARA_5_MASK                                                                        0x0000003FL
1120 #define UVD_MPC_SET_MUXA1__VARA_6_MASK                                                                        0x00000FC0L
1121 #define UVD_MPC_SET_MUXA1__VARA_7_MASK                                                                        0x0003F000L
1122 //UVD_MPC_SET_MUXB0
1123 #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT                                                                      0x0
1124 #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT                                                                      0x6
1125 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT                                                                      0xc
1126 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT                                                                      0x12
1127 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT                                                                      0x18
1128 #define UVD_MPC_SET_MUXB0__VARB_0_MASK                                                                        0x0000003FL
1129 #define UVD_MPC_SET_MUXB0__VARB_1_MASK                                                                        0x00000FC0L
1130 #define UVD_MPC_SET_MUXB0__VARB_2_MASK                                                                        0x0003F000L
1131 #define UVD_MPC_SET_MUXB0__VARB_3_MASK                                                                        0x00FC0000L
1132 #define UVD_MPC_SET_MUXB0__VARB_4_MASK                                                                        0x3F000000L
1133 //UVD_MPC_SET_MUXB1
1134 #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT                                                                      0x0
1135 #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT                                                                      0x6
1136 #define UVD_MPC_SET_MUXB1__VARB_7__SHIFT                                                                      0xc
1137 #define UVD_MPC_SET_MUXB1__VARB_5_MASK                                                                        0x0000003FL
1138 #define UVD_MPC_SET_MUXB1__VARB_6_MASK                                                                        0x00000FC0L
1139 #define UVD_MPC_SET_MUXB1__VARB_7_MASK                                                                        0x0003F000L
1140 //UVD_MPC_SET_MUX
1141 #define UVD_MPC_SET_MUX__SET_0__SHIFT                                                                         0x0
1142 #define UVD_MPC_SET_MUX__SET_1__SHIFT                                                                         0x3
1143 #define UVD_MPC_SET_MUX__SET_2__SHIFT                                                                         0x6
1144 #define UVD_MPC_SET_MUX__SET_0_MASK                                                                           0x00000007L
1145 #define UVD_MPC_SET_MUX__SET_1_MASK                                                                           0x00000038L
1146 #define UVD_MPC_SET_MUX__SET_2_MASK                                                                           0x000001C0L
1147 //UVD_MPC_SET_ALU
1148 #define UVD_MPC_SET_ALU__FUNCT__SHIFT                                                                         0x0
1149 #define UVD_MPC_SET_ALU__OPERAND__SHIFT                                                                       0x4
1150 #define UVD_MPC_SET_ALU__FUNCT_MASK                                                                           0x00000007L
1151 #define UVD_MPC_SET_ALU__OPERAND_MASK                                                                         0x00000FF0L
1152 //UVD_GPCOM_SYS_CMD
1153 #define UVD_GPCOM_SYS_CMD__CMD_SEND__SHIFT                                                                    0x0
1154 #define UVD_GPCOM_SYS_CMD__CMD__SHIFT                                                                         0x1
1155 #define UVD_GPCOM_SYS_CMD__CMD_SOURCE__SHIFT                                                                  0x1f
1156 #define UVD_GPCOM_SYS_CMD__CMD_SEND_MASK                                                                      0x00000001L
1157 #define UVD_GPCOM_SYS_CMD__CMD_MASK                                                                           0x7FFFFFFEL
1158 #define UVD_GPCOM_SYS_CMD__CMD_SOURCE_MASK                                                                    0x80000000L
1159 //UVD_GPCOM_SYS_DATA0
1160 #define UVD_GPCOM_SYS_DATA0__DATA0__SHIFT                                                                     0x0
1161 #define UVD_GPCOM_SYS_DATA0__DATA0_MASK                                                                       0xFFFFFFFFL
1162 //UVD_GPCOM_SYS_DATA1
1163 #define UVD_GPCOM_SYS_DATA1__DATA1__SHIFT                                                                     0x0
1164 #define UVD_GPCOM_SYS_DATA1__DATA1_MASK                                                                       0xFFFFFFFFL
1165 //UVD_VCPU_CACHE_OFFSET0
1166 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT                                                          0x0
1167 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK                                                            0x001FFFFFL
1168 //UVD_VCPU_CACHE_SIZE0
1169 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT                                                              0x0
1170 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK                                                                0x001FFFFFL
1171 //UVD_VCPU_CACHE_OFFSET1
1172 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT                                                          0x0
1173 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK                                                            0x001FFFFFL
1174 //UVD_VCPU_CACHE_SIZE1
1175 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT                                                              0x0
1176 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK                                                                0x001FFFFFL
1177 //UVD_VCPU_CACHE_OFFSET2
1178 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT                                                          0x0
1179 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK                                                            0x001FFFFFL
1180 //UVD_VCPU_CACHE_SIZE2
1181 #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT                                                              0x0
1182 #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK                                                                0x001FFFFFL
1183 //UVD_VCPU_CNTL
1184 #define UVD_VCPU_CNTL__CLK_EN__SHIFT                                                                          0x9
1185 #define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP__SHIFT                                                         0x11
1186 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT                                                                 0x14
1187 #define UVD_VCPU_CNTL__CLK_EN_MASK                                                                            0x00000200L
1188 #define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK                                                           0x00020000L
1189 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK                                                                   0x0FF00000L
1190 //UVD_SOFT_RESET
1191 #define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT                                                                 0x0
1192 #define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT                                                                0x1
1193 #define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT                                                                 0x2
1194 #define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT                                                                0x3
1195 #define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT                                                                0x4
1196 #define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT                                                                 0x5
1197 #define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT                                                                 0x6
1198 #define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT                                                                 0x7
1199 #define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT                                                                 0x8
1200 #define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT                                                                  0xa
1201 #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT                                                             0xd
1202 #define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT                                                                 0xe
1203 #define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT                                                                 0xf
1204 #define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT                                                                 0x10
1205 #define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT                                                                0x11
1206 #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT                                                         0x12
1207 #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT                                                         0x13
1208 #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT                                                         0x14
1209 #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT                                                         0x15
1210 #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT                                                          0x16
1211 #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT                                                          0x1a
1212 #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT                                                          0x1b
1213 #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT                                                         0x1c
1214 #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT                                                         0x1d
1215 #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT                                                           0x1e
1216 #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT                                                          0x1f
1217 #define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK                                                                   0x00000001L
1218 #define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK                                                                  0x00000002L
1219 #define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK                                                                   0x00000004L
1220 #define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK                                                                  0x00000008L
1221 #define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK                                                                  0x00000010L
1222 #define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK                                                                   0x00000020L
1223 #define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK                                                                   0x00000040L
1224 #define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK                                                                   0x00000080L
1225 #define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK                                                                   0x00000100L
1226 #define UVD_SOFT_RESET__IH_SOFT_RESET_MASK                                                                    0x00000400L
1227 #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK                                                               0x00002000L
1228 #define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK                                                                   0x00004000L
1229 #define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK                                                                   0x00008000L
1230 #define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK                                                                   0x00010000L
1231 #define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK                                                                  0x00020000L
1232 #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK                                                           0x00040000L
1233 #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK                                                           0x00080000L
1234 #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK                                                           0x00100000L
1235 #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK                                                           0x00200000L
1236 #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK                                                            0x00400000L
1237 #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK                                                            0x04000000L
1238 #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK                                                            0x08000000L
1239 #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK                                                           0x10000000L
1240 #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK                                                           0x20000000L
1241 #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK                                                             0x40000000L
1242 #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK                                                            0x80000000L
1243 //UVD_LMI_RBC_IB_VMID
1244 #define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT                                                                   0x0
1245 #define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK                                                                     0x0000000FL
1246 //UVD_RBC_IB_SIZE
1247 #define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT                                                                       0x4
1248 #define UVD_RBC_IB_SIZE__IB_SIZE_MASK                                                                         0x007FFFF0L
1249 //UVD_RBC_RB_RPTR
1250 #define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT                                                                       0x4
1251 #define UVD_RBC_RB_RPTR__RB_RPTR_MASK                                                                         0x007FFFF0L
1252 //UVD_RBC_RB_WPTR
1253 #define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT                                                                       0x4
1254 #define UVD_RBC_RB_WPTR__RB_WPTR_MASK                                                                         0x007FFFF0L
1255 //UVD_RBC_RB_WPTR_CNTL
1256 #define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER__SHIFT                                                       0x0
1257 #define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK                                                         0x00007FFFL
1258 //UVD_RBC_WPTR_STATUS
1259 #define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE__SHIFT                                                            0x4
1260 #define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE_MASK                                                              0x007FFFF0L
1261 //UVD_RBC_RB_CNTL
1262 #define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT                                                                      0x0
1263 #define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT                                                                      0x8
1264 #define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT                                                                   0x10
1265 #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT                                                               0x14
1266 #define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT                                                                  0x18
1267 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT                                                                 0x1c
1268 #define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK                                                                        0x0000001FL
1269 #define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK                                                                        0x00001F00L
1270 #define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK                                                                     0x00010000L
1271 #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK                                                                 0x00100000L
1272 #define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK                                                                    0x01000000L
1273 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK                                                                   0x10000000L
1274 //UVD_RBC_RB_RPTR_ADDR
1275 #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT                                                             0x0
1276 #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK                                                               0xFFFFFFFFL
1277 //UVD_STATUS
1278 #define UVD_STATUS__RBC_BUSY__SHIFT                                                                           0x0
1279 #define UVD_STATUS__VCPU_REPORT__SHIFT                                                                        0x1
1280 #define UVD_STATUS__AVP_BUSY__SHIFT                                                                           0x8
1281 #define UVD_STATUS__IDCT_BUSY__SHIFT                                                                          0x9
1282 #define UVD_STATUS__IDCT_CTL_ACK__SHIFT                                                                       0xb
1283 #define UVD_STATUS__UVD_CTL_ACK__SHIFT                                                                        0xc
1284 #define UVD_STATUS__AVP_BLOCK_ACK__SHIFT                                                                      0xd
1285 #define UVD_STATUS__IDCT_BLOCK_ACK__SHIFT                                                                     0xe
1286 #define UVD_STATUS__UVD_BLOCK_ACK__SHIFT                                                                      0xf
1287 #define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT                                                                   0x10
1288 #define UVD_STATUS__SYS_GPCOM_REQ__SHIFT                                                                      0x1f
1289 #define UVD_STATUS__RBC_BUSY_MASK                                                                             0x00000001L
1290 #define UVD_STATUS__VCPU_REPORT_MASK                                                                          0x000000FEL
1291 #define UVD_STATUS__AVP_BUSY_MASK                                                                             0x00000100L
1292 #define UVD_STATUS__IDCT_BUSY_MASK                                                                            0x00000200L
1293 #define UVD_STATUS__IDCT_CTL_ACK_MASK                                                                         0x00000800L
1294 #define UVD_STATUS__UVD_CTL_ACK_MASK                                                                          0x00001000L
1295 #define UVD_STATUS__AVP_BLOCK_ACK_MASK                                                                        0x00002000L
1296 #define UVD_STATUS__IDCT_BLOCK_ACK_MASK                                                                       0x00004000L
1297 #define UVD_STATUS__UVD_BLOCK_ACK_MASK                                                                        0x00008000L
1298 #define UVD_STATUS__RBC_ACCESS_GPCOM_MASK                                                                     0x00010000L
1299 #define UVD_STATUS__SYS_GPCOM_REQ_MASK                                                                        0x80000000L
1300 //UVD_SEMA_TIMEOUT_STATUS
1301 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT                                0x0
1302 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT                                     0x1
1303 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT                              0x2
1304 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT                                               0x3
1305 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK                                  0x00000001L
1306 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK                                       0x00000002L
1307 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK                                0x00000004L
1308 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK                                                 0x00000008L
1309 //UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL
1310 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT                                      0x0
1311 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT                                   0x1
1312 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT                                            0x18
1313 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK                                        0x00000001L
1314 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK                                     0x001FFFFEL
1315 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK                                              0x07000000L
1316 //UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL
1317 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT                                                0x0
1318 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT                                             0x1
1319 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT                                                 0x18
1320 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK                                                  0x00000001L
1321 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK                                               0x001FFFFEL
1322 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK                                                   0x07000000L
1323 //UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL
1324 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT                                  0x0
1325 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT                               0x1
1326 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT                                          0x18
1327 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK                                    0x00000001L
1328 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK                                 0x001FFFFEL
1329 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK                                            0x07000000L
1330 //UVD_CONTEXT_ID
1331 #define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT                                                                     0x0
1332 #define UVD_CONTEXT_ID__CONTEXT_ID_MASK                                                                       0xFFFFFFFFL
1333 //UVD_CONTEXT_ID2
1334 #define UVD_CONTEXT_ID2__CONTEXT_ID2__SHIFT                                                                   0x0
1335 #define UVD_CONTEXT_ID2__CONTEXT_ID2_MASK                                                                     0xFFFFFFFFL
1336 //UVD_RBC_WPTR_POLL_CNTL
1337 #define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ__SHIFT                                                              0x0
1338 #define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                        0x10
1339 #define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ_MASK                                                                0x0000FFFFL
1340 #define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                          0xFFFF0000L
1341 //UVD_RBC_WPTR_POLL_ADDR
1342 #define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR__SHIFT                                                              0x2
1343 #define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR_MASK                                                                0xFFFFFFFCL
1344 //UVD_RB_BASE_LO4
1345 #define UVD_RB_BASE_LO4__RB_BASE_LO__SHIFT                                                                    0x6
1346 #define UVD_RB_BASE_LO4__RB_BASE_LO_MASK                                                                      0xFFFFFFC0L
1347 //UVD_RB_BASE_HI4
1348 #define UVD_RB_BASE_HI4__RB_BASE_HI__SHIFT                                                                    0x0
1349 #define UVD_RB_BASE_HI4__RB_BASE_HI_MASK                                                                      0xFFFFFFFFL
1350 //UVD_RB_SIZE4
1351 #define UVD_RB_SIZE4__RB_SIZE__SHIFT                                                                          0x4
1352 #define UVD_RB_SIZE4__RB_SIZE_MASK                                                                            0x007FFFF0L
1353 //UVD_RB_RPTR4
1354 #define UVD_RB_RPTR4__RB_RPTR__SHIFT                                                                          0x4
1355 #define UVD_RB_RPTR4__RB_RPTR_MASK                                                                            0x007FFFF0L
1356 
1357 
1358 #endif