drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_sh

/* [<][>][^][v][top][bottom][index][help] */
   1 /*
   2  * Copyright (C) 2019  Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  */
  21 #ifndef _umc_6_1_1_SH_MASK_HEADER
  22 #define _umc_6_1_1_SH_MASK_HEADER
  23 
  24 //UMCCH0_0_EccErrCntSel
  25 #define UMCCH0_0_EccErrCntSel__EccErrCntCsSel__SHIFT                                                          0x0
  26 #define UMCCH0_0_EccErrCntSel__EccErrInt__SHIFT                                                               0xc
  27 #define UMCCH0_0_EccErrCntSel__EccErrCntEn__SHIFT                                                             0xf
  28 #define UMCCH0_0_EccErrCntSel__EccErrCntCsSel_MASK                                                            0x0000000FL
  29 #define UMCCH0_0_EccErrCntSel__EccErrInt_MASK                                                                 0x00003000L
  30 #define UMCCH0_0_EccErrCntSel__EccErrCntEn_MASK                                                               0x00008000L
  31 //UMCCH0_0_EccErrCnt
  32 #define UMCCH0_0_EccErrCnt__EccErrCnt__SHIFT                                                                  0x0
  33 #define UMCCH0_0_EccErrCnt__EccErrCnt_MASK                                                                    0x0000FFFFL
  34 //MCA_UMC_UMC0_MCUMC_STATUST0
  35 #define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCode__SHIFT                                                         0x0
  36 #define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCodeExt__SHIFT                                                      0x10
  37 #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV0__SHIFT                                                           0x16
  38 #define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreId__SHIFT                                                         0x20
  39 #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV1__SHIFT                                                           0x26
  40 #define MCA_UMC_UMC0_MCUMC_STATUST0__Scrub__SHIFT                                                             0x28
  41 #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV2__SHIFT                                                           0x29
  42 #define MCA_UMC_UMC0_MCUMC_STATUST0__Poison__SHIFT                                                            0x2b
  43 #define MCA_UMC_UMC0_MCUMC_STATUST0__Deferred__SHIFT                                                          0x2c
  44 #define MCA_UMC_UMC0_MCUMC_STATUST0__UECC__SHIFT                                                              0x2d
  45 #define MCA_UMC_UMC0_MCUMC_STATUST0__CECC__SHIFT                                                              0x2e
  46 #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV3__SHIFT                                                           0x2f
  47 #define MCA_UMC_UMC0_MCUMC_STATUST0__Transparent__SHIFT                                                       0x34
  48 #define MCA_UMC_UMC0_MCUMC_STATUST0__SyndV__SHIFT                                                             0x35
  49 #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV4__SHIFT                                                           0x36
  50 #define MCA_UMC_UMC0_MCUMC_STATUST0__TCC__SHIFT                                                               0x37
  51 #define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreIdVal__SHIFT                                                      0x38
  52 #define MCA_UMC_UMC0_MCUMC_STATUST0__PCC__SHIFT                                                               0x39
  53 #define MCA_UMC_UMC0_MCUMC_STATUST0__AddrV__SHIFT                                                             0x3a
  54 #define MCA_UMC_UMC0_MCUMC_STATUST0__MiscV__SHIFT                                                             0x3b
  55 #define MCA_UMC_UMC0_MCUMC_STATUST0__En__SHIFT                                                                0x3c
  56 #define MCA_UMC_UMC0_MCUMC_STATUST0__UC__SHIFT                                                                0x3d
  57 #define MCA_UMC_UMC0_MCUMC_STATUST0__Overflow__SHIFT                                                          0x3e
  58 #define MCA_UMC_UMC0_MCUMC_STATUST0__Val__SHIFT                                                               0x3f
  59 #define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCode_MASK                                                           0x000000000000FFFFL
  60 #define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCodeExt_MASK                                                        0x00000000003F0000L
  61 #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV0_MASK                                                             0x00000000FFC00000L
  62 #define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreId_MASK                                                           0x0000003F00000000L
  63 #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV1_MASK                                                             0x000000C000000000L
  64 #define MCA_UMC_UMC0_MCUMC_STATUST0__Scrub_MASK                                                               0x0000010000000000L
  65 #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV2_MASK                                                             0x0000060000000000L
  66 #define MCA_UMC_UMC0_MCUMC_STATUST0__Poison_MASK                                                              0x0000080000000000L
  67 #define MCA_UMC_UMC0_MCUMC_STATUST0__Deferred_MASK                                                            0x0000100000000000L
  68 #define MCA_UMC_UMC0_MCUMC_STATUST0__UECC_MASK                                                                0x0000200000000000L
  69 #define MCA_UMC_UMC0_MCUMC_STATUST0__CECC_MASK                                                                0x0000400000000000L
  70 #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV3_MASK                                                             0x000F800000000000L
  71 #define MCA_UMC_UMC0_MCUMC_STATUST0__Transparent_MASK                                                         0x0010000000000000L
  72 #define MCA_UMC_UMC0_MCUMC_STATUST0__SyndV_MASK                                                               0x0020000000000000L
  73 #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV4_MASK                                                             0x0040000000000000L
  74 #define MCA_UMC_UMC0_MCUMC_STATUST0__TCC_MASK                                                                 0x0080000000000000L
  75 #define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreIdVal_MASK                                                        0x0100000000000000L
  76 #define MCA_UMC_UMC0_MCUMC_STATUST0__PCC_MASK                                                                 0x0200000000000000L
  77 #define MCA_UMC_UMC0_MCUMC_STATUST0__AddrV_MASK                                                               0x0400000000000000L
  78 #define MCA_UMC_UMC0_MCUMC_STATUST0__MiscV_MASK                                                               0x0800000000000000L
  79 #define MCA_UMC_UMC0_MCUMC_STATUST0__En_MASK                                                                  0x1000000000000000L
  80 #define MCA_UMC_UMC0_MCUMC_STATUST0__UC_MASK                                                                  0x2000000000000000L
  81 #define MCA_UMC_UMC0_MCUMC_STATUST0__Overflow_MASK                                                            0x4000000000000000L
  82 #define MCA_UMC_UMC0_MCUMC_STATUST0__Val_MASK                                                                 0x8000000000000000L
  83 //MCA_UMC_UMC0_MCUMC_ADDRT0
  84 #define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr__SHIFT                                                           0x0
  85 #define MCA_UMC_UMC0_MCUMC_ADDRT0__LSB__SHIFT                                                                 0x38
  86 #define MCA_UMC_UMC0_MCUMC_ADDRT0__Reserved__SHIFT                                                            0x3e
  87 #define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr_MASK                                                             0x00FFFFFFFFFFFFFFL
  88 #define MCA_UMC_UMC0_MCUMC_ADDRT0__LSB_MASK                                                                   0x3F00000000000000L
  89 #define MCA_UMC_UMC0_MCUMC_ADDRT0__Reserved_MASK                                                              0xC000000000000000L
  90 
  91 #endif
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_sh_mask.h

INCLUDED FROM
