root/drivers/gpu/drm/amd/include/asic_reg/sdma2/sdma2_4_2_2_sh_mask.h

INCLUDED FROM

   1 /*
   2  * Copyright (C) 2018  Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  */
  21 #ifndef _sdma2_4_2_2_SH_MASK_HEADER
  22 #define _sdma2_4_2_2_SH_MASK_HEADER
  23 
  24 
  25 // addressBlock: sdma2_sdma2dec
  26 //SDMA2_UCODE_ADDR
  27 #define SDMA2_UCODE_ADDR__VALUE__SHIFT                                                                        0x0
  28 #define SDMA2_UCODE_ADDR__VALUE_MASK                                                                          0x00001FFFL
  29 //SDMA2_UCODE_DATA
  30 #define SDMA2_UCODE_DATA__VALUE__SHIFT                                                                        0x0
  31 #define SDMA2_UCODE_DATA__VALUE_MASK                                                                          0xFFFFFFFFL
  32 //SDMA2_VM_CNTL
  33 #define SDMA2_VM_CNTL__CMD__SHIFT                                                                             0x0
  34 #define SDMA2_VM_CNTL__CMD_MASK                                                                               0x0000000FL
  35 //SDMA2_VM_CTX_LO
  36 #define SDMA2_VM_CTX_LO__ADDR__SHIFT                                                                          0x2
  37 #define SDMA2_VM_CTX_LO__ADDR_MASK                                                                            0xFFFFFFFCL
  38 //SDMA2_VM_CTX_HI
  39 #define SDMA2_VM_CTX_HI__ADDR__SHIFT                                                                          0x0
  40 #define SDMA2_VM_CTX_HI__ADDR_MASK                                                                            0xFFFFFFFFL
  41 //SDMA2_ACTIVE_FCN_ID
  42 #define SDMA2_ACTIVE_FCN_ID__VFID__SHIFT                                                                      0x0
  43 #define SDMA2_ACTIVE_FCN_ID__RESERVED__SHIFT                                                                  0x4
  44 #define SDMA2_ACTIVE_FCN_ID__VF__SHIFT                                                                        0x1f
  45 #define SDMA2_ACTIVE_FCN_ID__VFID_MASK                                                                        0x0000000FL
  46 #define SDMA2_ACTIVE_FCN_ID__RESERVED_MASK                                                                    0x7FFFFFF0L
  47 #define SDMA2_ACTIVE_FCN_ID__VF_MASK                                                                          0x80000000L
  48 //SDMA2_VM_CTX_CNTL
  49 #define SDMA2_VM_CTX_CNTL__PRIV__SHIFT                                                                        0x0
  50 #define SDMA2_VM_CTX_CNTL__VMID__SHIFT                                                                        0x4
  51 #define SDMA2_VM_CTX_CNTL__PRIV_MASK                                                                          0x00000001L
  52 #define SDMA2_VM_CTX_CNTL__VMID_MASK                                                                          0x000000F0L
  53 //SDMA2_VIRT_RESET_REQ
  54 #define SDMA2_VIRT_RESET_REQ__VF__SHIFT                                                                       0x0
  55 #define SDMA2_VIRT_RESET_REQ__PF__SHIFT                                                                       0x1f
  56 #define SDMA2_VIRT_RESET_REQ__VF_MASK                                                                         0x0000FFFFL
  57 #define SDMA2_VIRT_RESET_REQ__PF_MASK                                                                         0x80000000L
  58 //SDMA2_VF_ENABLE
  59 #define SDMA2_VF_ENABLE__VF_ENABLE__SHIFT                                                                     0x0
  60 #define SDMA2_VF_ENABLE__VF_ENABLE_MASK                                                                       0x00000001L
  61 //SDMA2_CONTEXT_REG_TYPE0
  62 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_CNTL__SHIFT                                                     0x0
  63 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_BASE__SHIFT                                                     0x1
  64 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_BASE_HI__SHIFT                                                  0x2
  65 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR__SHIFT                                                     0x3
  66 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_HI__SHIFT                                                  0x4
  67 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_WPTR__SHIFT                                                     0x5
  68 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_WPTR_HI__SHIFT                                                  0x6
  69 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_WPTR_POLL_CNTL__SHIFT                                           0x7
  70 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_ADDR_HI__SHIFT                                             0x8
  71 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_ADDR_LO__SHIFT                                             0x9
  72 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_CNTL__SHIFT                                                     0xa
  73 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_RPTR__SHIFT                                                     0xb
  74 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_OFFSET__SHIFT                                                   0xc
  75 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_BASE_LO__SHIFT                                                  0xd
  76 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_BASE_HI__SHIFT                                                  0xe
  77 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_SIZE__SHIFT                                                     0xf
  78 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_SKIP_CNTL__SHIFT                                                   0x10
  79 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_CONTEXT_STATUS__SHIFT                                              0x11
  80 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_DOORBELL__SHIFT                                                    0x12
  81 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_CONTEXT_CNTL__SHIFT                                                0x13
  82 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_CNTL_MASK                                                       0x00000001L
  83 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_BASE_MASK                                                       0x00000002L
  84 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_BASE_HI_MASK                                                    0x00000004L
  85 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_MASK                                                       0x00000008L
  86 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_HI_MASK                                                    0x00000010L
  87 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_WPTR_MASK                                                       0x00000020L
  88 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_WPTR_HI_MASK                                                    0x00000040L
  89 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_WPTR_POLL_CNTL_MASK                                             0x00000080L
  90 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_ADDR_HI_MASK                                               0x00000100L
  91 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_ADDR_LO_MASK                                               0x00000200L
  92 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_CNTL_MASK                                                       0x00000400L
  93 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_RPTR_MASK                                                       0x00000800L
  94 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_OFFSET_MASK                                                     0x00001000L
  95 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_BASE_LO_MASK                                                    0x00002000L
  96 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_BASE_HI_MASK                                                    0x00004000L
  97 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_SIZE_MASK                                                       0x00008000L
  98 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_SKIP_CNTL_MASK                                                     0x00010000L
  99 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_CONTEXT_STATUS_MASK                                                0x00020000L
 100 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_DOORBELL_MASK                                                      0x00040000L
 101 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_CONTEXT_CNTL_MASK                                                  0x00080000L
 102 //SDMA2_CONTEXT_REG_TYPE1
 103 #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_STATUS__SHIFT                                                      0x8
 104 #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_DOORBELL_LOG__SHIFT                                                0x9
 105 #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_WATERMARK__SHIFT                                                   0xa
 106 #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_DOORBELL_OFFSET__SHIFT                                             0xb
 107 #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_CSA_ADDR_LO__SHIFT                                                 0xc
 108 #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_CSA_ADDR_HI__SHIFT                                                 0xd
 109 #define SDMA2_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT                                                             0xe
 110 #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_IB_SUB_REMAIN__SHIFT                                               0xf
 111 #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_PREEMPT__SHIFT                                                     0x10
 112 #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_DUMMY_REG__SHIFT                                                   0x11
 113 #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT                                        0x12
 114 #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT                                        0x13
 115 #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_RB_AQL_CNTL__SHIFT                                                 0x14
 116 #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_MINOR_PTR_UPDATE__SHIFT                                            0x15
 117 #define SDMA2_CONTEXT_REG_TYPE1__RESERVED__SHIFT                                                              0x16
 118 #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_STATUS_MASK                                                        0x00000100L
 119 #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_DOORBELL_LOG_MASK                                                  0x00000200L
 120 #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_WATERMARK_MASK                                                     0x00000400L
 121 #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_DOORBELL_OFFSET_MASK                                               0x00000800L
 122 #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_CSA_ADDR_LO_MASK                                                   0x00001000L
 123 #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_CSA_ADDR_HI_MASK                                                   0x00002000L
 124 #define SDMA2_CONTEXT_REG_TYPE1__VOID_REG2_MASK                                                               0x00004000L
 125 #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_IB_SUB_REMAIN_MASK                                                 0x00008000L
 126 #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_PREEMPT_MASK                                                       0x00010000L
 127 #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_DUMMY_REG_MASK                                                     0x00020000L
 128 #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_RB_WPTR_POLL_ADDR_HI_MASK                                          0x00040000L
 129 #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_RB_WPTR_POLL_ADDR_LO_MASK                                          0x00080000L
 130 #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_RB_AQL_CNTL_MASK                                                   0x00100000L
 131 #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_MINOR_PTR_UPDATE_MASK                                              0x00200000L
 132 #define SDMA2_CONTEXT_REG_TYPE1__RESERVED_MASK                                                                0xFFC00000L
 133 //SDMA2_CONTEXT_REG_TYPE2
 134 #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA0__SHIFT                                                0x0
 135 #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA1__SHIFT                                                0x1
 136 #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA2__SHIFT                                                0x2
 137 #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA3__SHIFT                                                0x3
 138 #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA4__SHIFT                                                0x4
 139 #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA5__SHIFT                                                0x5
 140 #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA6__SHIFT                                                0x6
 141 #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA7__SHIFT                                                0x7
 142 #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA8__SHIFT                                                0x8
 143 #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_CNTL__SHIFT                                                 0x9
 144 #define SDMA2_CONTEXT_REG_TYPE2__RESERVED__SHIFT                                                              0xa
 145 #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA0_MASK                                                  0x00000001L
 146 #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA1_MASK                                                  0x00000002L
 147 #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA2_MASK                                                  0x00000004L
 148 #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA3_MASK                                                  0x00000008L
 149 #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA4_MASK                                                  0x00000010L
 150 #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA5_MASK                                                  0x00000020L
 151 #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA6_MASK                                                  0x00000040L
 152 #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA7_MASK                                                  0x00000080L
 153 #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA8_MASK                                                  0x00000100L
 154 #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_CNTL_MASK                                                   0x00000200L
 155 #define SDMA2_CONTEXT_REG_TYPE2__RESERVED_MASK                                                                0xFFFFFC00L
 156 //SDMA2_CONTEXT_REG_TYPE3
 157 #define SDMA2_CONTEXT_REG_TYPE3__RESERVED__SHIFT                                                              0x0
 158 #define SDMA2_CONTEXT_REG_TYPE3__RESERVED_MASK                                                                0xFFFFFFFFL
 159 //SDMA2_PUB_REG_TYPE0
 160 #define SDMA2_PUB_REG_TYPE0__SDMA2_UCODE_ADDR__SHIFT                                                          0x0
 161 #define SDMA2_PUB_REG_TYPE0__SDMA2_UCODE_DATA__SHIFT                                                          0x1
 162 #define SDMA2_PUB_REG_TYPE0__RESERVED3__SHIFT                                                                 0x3
 163 #define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CNTL__SHIFT                                                             0x4
 164 #define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CTX_LO__SHIFT                                                           0x5
 165 #define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CTX_HI__SHIFT                                                           0x6
 166 #define SDMA2_PUB_REG_TYPE0__SDMA2_ACTIVE_FCN_ID__SHIFT                                                       0x7
 167 #define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CTX_CNTL__SHIFT                                                         0x8
 168 #define SDMA2_PUB_REG_TYPE0__SDMA2_VIRT_RESET_REQ__SHIFT                                                      0x9
 169 #define SDMA2_PUB_REG_TYPE0__RESERVED10__SHIFT                                                                0xa
 170 #define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE0__SHIFT                                                   0xb
 171 #define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE1__SHIFT                                                   0xc
 172 #define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE2__SHIFT                                                   0xd
 173 #define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE3__SHIFT                                                   0xe
 174 #define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE0__SHIFT                                                       0xf
 175 #define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE1__SHIFT                                                       0x10
 176 #define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE2__SHIFT                                                       0x11
 177 #define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE3__SHIFT                                                       0x12
 178 #define SDMA2_PUB_REG_TYPE0__SDMA2_MMHUB_CNTL__SHIFT                                                          0x13
 179 #define SDMA2_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT                                           0x15
 180 #define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_GROUP_BOUNDARY__SHIFT                                              0x19
 181 #define SDMA2_PUB_REG_TYPE0__SDMA2_POWER_CNTL__SHIFT                                                          0x1a
 182 #define SDMA2_PUB_REG_TYPE0__SDMA2_CLK_CTRL__SHIFT                                                            0x1b
 183 #define SDMA2_PUB_REG_TYPE0__SDMA2_CNTL__SHIFT                                                                0x1c
 184 #define SDMA2_PUB_REG_TYPE0__SDMA2_CHICKEN_BITS__SHIFT                                                        0x1d
 185 #define SDMA2_PUB_REG_TYPE0__SDMA2_GB_ADDR_CONFIG__SHIFT                                                      0x1e
 186 #define SDMA2_PUB_REG_TYPE0__SDMA2_GB_ADDR_CONFIG_READ__SHIFT                                                 0x1f
 187 #define SDMA2_PUB_REG_TYPE0__SDMA2_UCODE_ADDR_MASK                                                            0x00000001L
 188 #define SDMA2_PUB_REG_TYPE0__SDMA2_UCODE_DATA_MASK                                                            0x00000002L
 189 #define SDMA2_PUB_REG_TYPE0__RESERVED3_MASK                                                                   0x00000008L
 190 #define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CNTL_MASK                                                               0x00000010L
 191 #define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CTX_LO_MASK                                                             0x00000020L
 192 #define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CTX_HI_MASK                                                             0x00000040L
 193 #define SDMA2_PUB_REG_TYPE0__SDMA2_ACTIVE_FCN_ID_MASK                                                         0x00000080L
 194 #define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CTX_CNTL_MASK                                                           0x00000100L
 195 #define SDMA2_PUB_REG_TYPE0__SDMA2_VIRT_RESET_REQ_MASK                                                        0x00000200L
 196 #define SDMA2_PUB_REG_TYPE0__RESERVED10_MASK                                                                  0x00000400L
 197 #define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE0_MASK                                                     0x00000800L
 198 #define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE1_MASK                                                     0x00001000L
 199 #define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE2_MASK                                                     0x00002000L
 200 #define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE3_MASK                                                     0x00004000L
 201 #define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE0_MASK                                                         0x00008000L
 202 #define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE1_MASK                                                         0x00010000L
 203 #define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE2_MASK                                                         0x00020000L
 204 #define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE3_MASK                                                         0x00040000L
 205 #define SDMA2_PUB_REG_TYPE0__SDMA2_MMHUB_CNTL_MASK                                                            0x00080000L
 206 #define SDMA2_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK                                             0x01E00000L
 207 #define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_GROUP_BOUNDARY_MASK                                                0x02000000L
 208 #define SDMA2_PUB_REG_TYPE0__SDMA2_POWER_CNTL_MASK                                                            0x04000000L
 209 #define SDMA2_PUB_REG_TYPE0__SDMA2_CLK_CTRL_MASK                                                              0x08000000L
 210 #define SDMA2_PUB_REG_TYPE0__SDMA2_CNTL_MASK                                                                  0x10000000L
 211 #define SDMA2_PUB_REG_TYPE0__SDMA2_CHICKEN_BITS_MASK                                                          0x20000000L
 212 #define SDMA2_PUB_REG_TYPE0__SDMA2_GB_ADDR_CONFIG_MASK                                                        0x40000000L
 213 #define SDMA2_PUB_REG_TYPE0__SDMA2_GB_ADDR_CONFIG_READ_MASK                                                   0x80000000L
 214 //SDMA2_PUB_REG_TYPE1
 215 #define SDMA2_PUB_REG_TYPE1__SDMA2_RB_RPTR_FETCH_HI__SHIFT                                                    0x0
 216 #define SDMA2_PUB_REG_TYPE1__SDMA2_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT                                            0x1
 217 #define SDMA2_PUB_REG_TYPE1__SDMA2_RB_RPTR_FETCH__SHIFT                                                       0x2
 218 #define SDMA2_PUB_REG_TYPE1__SDMA2_IB_OFFSET_FETCH__SHIFT                                                     0x3
 219 #define SDMA2_PUB_REG_TYPE1__SDMA2_PROGRAM__SHIFT                                                             0x4
 220 #define SDMA2_PUB_REG_TYPE1__SDMA2_STATUS_REG__SHIFT                                                          0x5
 221 #define SDMA2_PUB_REG_TYPE1__SDMA2_STATUS1_REG__SHIFT                                                         0x6
 222 #define SDMA2_PUB_REG_TYPE1__SDMA2_RD_BURST_CNTL__SHIFT                                                       0x7
 223 #define SDMA2_PUB_REG_TYPE1__SDMA2_HBM_PAGE_CONFIG__SHIFT                                                     0x8
 224 #define SDMA2_PUB_REG_TYPE1__SDMA2_UCODE_CHECKSUM__SHIFT                                                      0x9
 225 #define SDMA2_PUB_REG_TYPE1__SDMA2_F32_CNTL__SHIFT                                                            0xa
 226 #define SDMA2_PUB_REG_TYPE1__SDMA2_FREEZE__SHIFT                                                              0xb
 227 #define SDMA2_PUB_REG_TYPE1__SDMA2_PHASE0_QUANTUM__SHIFT                                                      0xc
 228 #define SDMA2_PUB_REG_TYPE1__SDMA2_PHASE1_QUANTUM__SHIFT                                                      0xd
 229 #define SDMA2_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT                                                         0xe
 230 #define SDMA2_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT                                                         0xf
 231 #define SDMA2_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT                                                          0x10
 232 #define SDMA2_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT                                                           0x11
 233 #define SDMA2_PUB_REG_TYPE1__SDMA2_EDC_CONFIG__SHIFT                                                          0x12
 234 #define SDMA2_PUB_REG_TYPE1__SDMA2_BA_THRESHOLD__SHIFT                                                        0x13
 235 #define SDMA2_PUB_REG_TYPE1__SDMA2_ID__SHIFT                                                                  0x14
 236 #define SDMA2_PUB_REG_TYPE1__SDMA2_VERSION__SHIFT                                                             0x15
 237 #define SDMA2_PUB_REG_TYPE1__SDMA2_EDC_COUNTER__SHIFT                                                         0x16
 238 #define SDMA2_PUB_REG_TYPE1__SDMA2_EDC_COUNTER_CLEAR__SHIFT                                                   0x17
 239 #define SDMA2_PUB_REG_TYPE1__SDMA2_STATUS2_REG__SHIFT                                                         0x18
 240 #define SDMA2_PUB_REG_TYPE1__SDMA2_ATOMIC_CNTL__SHIFT                                                         0x19
 241 #define SDMA2_PUB_REG_TYPE1__SDMA2_ATOMIC_PREOP_LO__SHIFT                                                     0x1a
 242 #define SDMA2_PUB_REG_TYPE1__SDMA2_ATOMIC_PREOP_HI__SHIFT                                                     0x1b
 243 #define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_CNTL__SHIFT                                                          0x1c
 244 #define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_WATERMK__SHIFT                                                       0x1d
 245 #define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_RD_STATUS__SHIFT                                                     0x1e
 246 #define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_WR_STATUS__SHIFT                                                     0x1f
 247 #define SDMA2_PUB_REG_TYPE1__SDMA2_RB_RPTR_FETCH_HI_MASK                                                      0x00000001L
 248 #define SDMA2_PUB_REG_TYPE1__SDMA2_SEM_WAIT_FAIL_TIMER_CNTL_MASK                                              0x00000002L
 249 #define SDMA2_PUB_REG_TYPE1__SDMA2_RB_RPTR_FETCH_MASK                                                         0x00000004L
 250 #define SDMA2_PUB_REG_TYPE1__SDMA2_IB_OFFSET_FETCH_MASK                                                       0x00000008L
 251 #define SDMA2_PUB_REG_TYPE1__SDMA2_PROGRAM_MASK                                                               0x00000010L
 252 #define SDMA2_PUB_REG_TYPE1__SDMA2_STATUS_REG_MASK                                                            0x00000020L
 253 #define SDMA2_PUB_REG_TYPE1__SDMA2_STATUS1_REG_MASK                                                           0x00000040L
 254 #define SDMA2_PUB_REG_TYPE1__SDMA2_RD_BURST_CNTL_MASK                                                         0x00000080L
 255 #define SDMA2_PUB_REG_TYPE1__SDMA2_HBM_PAGE_CONFIG_MASK                                                       0x00000100L
 256 #define SDMA2_PUB_REG_TYPE1__SDMA2_UCODE_CHECKSUM_MASK                                                        0x00000200L
 257 #define SDMA2_PUB_REG_TYPE1__SDMA2_F32_CNTL_MASK                                                              0x00000400L
 258 #define SDMA2_PUB_REG_TYPE1__SDMA2_FREEZE_MASK                                                                0x00000800L
 259 #define SDMA2_PUB_REG_TYPE1__SDMA2_PHASE0_QUANTUM_MASK                                                        0x00001000L
 260 #define SDMA2_PUB_REG_TYPE1__SDMA2_PHASE1_QUANTUM_MASK                                                        0x00002000L
 261 #define SDMA2_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK                                                           0x00004000L
 262 #define SDMA2_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK                                                           0x00008000L
 263 #define SDMA2_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK                                                            0x00010000L
 264 #define SDMA2_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK                                                             0x00020000L
 265 #define SDMA2_PUB_REG_TYPE1__SDMA2_EDC_CONFIG_MASK                                                            0x00040000L
 266 #define SDMA2_PUB_REG_TYPE1__SDMA2_BA_THRESHOLD_MASK                                                          0x00080000L
 267 #define SDMA2_PUB_REG_TYPE1__SDMA2_ID_MASK                                                                    0x00100000L
 268 #define SDMA2_PUB_REG_TYPE1__SDMA2_VERSION_MASK                                                               0x00200000L
 269 #define SDMA2_PUB_REG_TYPE1__SDMA2_EDC_COUNTER_MASK                                                           0x00400000L
 270 #define SDMA2_PUB_REG_TYPE1__SDMA2_EDC_COUNTER_CLEAR_MASK                                                     0x00800000L
 271 #define SDMA2_PUB_REG_TYPE1__SDMA2_STATUS2_REG_MASK                                                           0x01000000L
 272 #define SDMA2_PUB_REG_TYPE1__SDMA2_ATOMIC_CNTL_MASK                                                           0x02000000L
 273 #define SDMA2_PUB_REG_TYPE1__SDMA2_ATOMIC_PREOP_LO_MASK                                                       0x04000000L
 274 #define SDMA2_PUB_REG_TYPE1__SDMA2_ATOMIC_PREOP_HI_MASK                                                       0x08000000L
 275 #define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_CNTL_MASK                                                            0x10000000L
 276 #define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_WATERMK_MASK                                                         0x20000000L
 277 #define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_RD_STATUS_MASK                                                       0x40000000L
 278 #define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_WR_STATUS_MASK                                                       0x80000000L
 279 //SDMA2_PUB_REG_TYPE2
 280 #define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_INV0__SHIFT                                                          0x0
 281 #define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_INV1__SHIFT                                                          0x1
 282 #define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_INV2__SHIFT                                                          0x2
 283 #define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_RD_XNACK0__SHIFT                                                     0x3
 284 #define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_RD_XNACK1__SHIFT                                                     0x4
 285 #define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_WR_XNACK0__SHIFT                                                     0x5
 286 #define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_WR_XNACK1__SHIFT                                                     0x6
 287 #define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_TIMEOUT__SHIFT                                                       0x7
 288 #define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_PAGE__SHIFT                                                          0x8
 289 #define SDMA2_PUB_REG_TYPE2__SDMA2_POWER_CNTL_IDLE__SHIFT                                                     0x9
 290 #define SDMA2_PUB_REG_TYPE2__SDMA2_RELAX_ORDERING_LUT__SHIFT                                                  0xa
 291 #define SDMA2_PUB_REG_TYPE2__SDMA2_CHICKEN_BITS_2__SHIFT                                                      0xb
 292 #define SDMA2_PUB_REG_TYPE2__SDMA2_STATUS3_REG__SHIFT                                                         0xc
 293 #define SDMA2_PUB_REG_TYPE2__SDMA2_PHYSICAL_ADDR_LO__SHIFT                                                    0xd
 294 #define SDMA2_PUB_REG_TYPE2__SDMA2_PHYSICAL_ADDR_HI__SHIFT                                                    0xe
 295 #define SDMA2_PUB_REG_TYPE2__SDMA2_PHASE2_QUANTUM__SHIFT                                                      0xf
 296 #define SDMA2_PUB_REG_TYPE2__SDMA2_ERROR_LOG__SHIFT                                                           0x10
 297 #define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG0__SHIFT                                                      0x11
 298 #define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG1__SHIFT                                                      0x12
 299 #define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG2__SHIFT                                                      0x13
 300 #define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG3__SHIFT                                                      0x14
 301 #define SDMA2_PUB_REG_TYPE2__SDMA2_F32_COUNTER__SHIFT                                                         0x15
 302 #define SDMA2_PUB_REG_TYPE2__SDMA2_UNBREAKABLE__SHIFT                                                         0x16
 303 #define SDMA2_PUB_REG_TYPE2__SDMA2_PERFMON_CNTL__SHIFT                                                        0x17
 304 #define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCOUNTER0_RESULT__SHIFT                                                 0x18
 305 #define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCOUNTER1_RESULT__SHIFT                                                 0x19
 306 #define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT                                         0x1a
 307 #define SDMA2_PUB_REG_TYPE2__SDMA2_CRD_CNTL__SHIFT                                                            0x1b
 308 #define SDMA2_PUB_REG_TYPE2__RESERVED28__SHIFT                                                                0x1c
 309 #define SDMA2_PUB_REG_TYPE2__SDMA2_GPU_IOV_VIOLATION_LOG__SHIFT                                               0x1d
 310 #define SDMA2_PUB_REG_TYPE2__SDMA2_ULV_CNTL__SHIFT                                                            0x1e
 311 #define SDMA2_PUB_REG_TYPE2__RESERVED__SHIFT                                                                  0x1f
 312 #define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_INV0_MASK                                                            0x00000001L
 313 #define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_INV1_MASK                                                            0x00000002L
 314 #define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_INV2_MASK                                                            0x00000004L
 315 #define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_RD_XNACK0_MASK                                                       0x00000008L
 316 #define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_RD_XNACK1_MASK                                                       0x00000010L
 317 #define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_WR_XNACK0_MASK                                                       0x00000020L
 318 #define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_WR_XNACK1_MASK                                                       0x00000040L
 319 #define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_TIMEOUT_MASK                                                         0x00000080L
 320 #define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_PAGE_MASK                                                            0x00000100L
 321 #define SDMA2_PUB_REG_TYPE2__SDMA2_POWER_CNTL_IDLE_MASK                                                       0x00000200L
 322 #define SDMA2_PUB_REG_TYPE2__SDMA2_RELAX_ORDERING_LUT_MASK                                                    0x00000400L
 323 #define SDMA2_PUB_REG_TYPE2__SDMA2_CHICKEN_BITS_2_MASK                                                        0x00000800L
 324 #define SDMA2_PUB_REG_TYPE2__SDMA2_STATUS3_REG_MASK                                                           0x00001000L
 325 #define SDMA2_PUB_REG_TYPE2__SDMA2_PHYSICAL_ADDR_LO_MASK                                                      0x00002000L
 326 #define SDMA2_PUB_REG_TYPE2__SDMA2_PHYSICAL_ADDR_HI_MASK                                                      0x00004000L
 327 #define SDMA2_PUB_REG_TYPE2__SDMA2_PHASE2_QUANTUM_MASK                                                        0x00008000L
 328 #define SDMA2_PUB_REG_TYPE2__SDMA2_ERROR_LOG_MASK                                                             0x00010000L
 329 #define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG0_MASK                                                        0x00020000L
 330 #define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG1_MASK                                                        0x00040000L
 331 #define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG2_MASK                                                        0x00080000L
 332 #define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG3_MASK                                                        0x00100000L
 333 #define SDMA2_PUB_REG_TYPE2__SDMA2_F32_COUNTER_MASK                                                           0x00200000L
 334 #define SDMA2_PUB_REG_TYPE2__SDMA2_UNBREAKABLE_MASK                                                           0x00400000L
 335 #define SDMA2_PUB_REG_TYPE2__SDMA2_PERFMON_CNTL_MASK                                                          0x00800000L
 336 #define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCOUNTER0_RESULT_MASK                                                   0x01000000L
 337 #define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCOUNTER1_RESULT_MASK                                                   0x02000000L
 338 #define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCOUNTER_TAG_DELAY_RANGE_MASK                                           0x04000000L
 339 #define SDMA2_PUB_REG_TYPE2__SDMA2_CRD_CNTL_MASK                                                              0x08000000L
 340 #define SDMA2_PUB_REG_TYPE2__RESERVED28_MASK                                                                  0x10000000L
 341 #define SDMA2_PUB_REG_TYPE2__SDMA2_GPU_IOV_VIOLATION_LOG_MASK                                                 0x20000000L
 342 #define SDMA2_PUB_REG_TYPE2__SDMA2_ULV_CNTL_MASK                                                              0x40000000L
 343 #define SDMA2_PUB_REG_TYPE2__RESERVED_MASK                                                                    0x80000000L
 344 //SDMA2_PUB_REG_TYPE3
 345 #define SDMA2_PUB_REG_TYPE3__SDMA2_EA_DBIT_ADDR_DATA__SHIFT                                                   0x0
 346 #define SDMA2_PUB_REG_TYPE3__SDMA2_EA_DBIT_ADDR_INDEX__SHIFT                                                  0x1
 347 #define SDMA2_PUB_REG_TYPE3__SDMA2_GPU_IOV_VIOLATION_LOG2__SHIFT                                              0x2
 348 #define SDMA2_PUB_REG_TYPE3__RESERVED__SHIFT                                                                  0x3
 349 #define SDMA2_PUB_REG_TYPE3__SDMA2_EA_DBIT_ADDR_DATA_MASK                                                     0x00000001L
 350 #define SDMA2_PUB_REG_TYPE3__SDMA2_EA_DBIT_ADDR_INDEX_MASK                                                    0x00000002L
 351 #define SDMA2_PUB_REG_TYPE3__SDMA2_GPU_IOV_VIOLATION_LOG2_MASK                                                0x00000004L
 352 #define SDMA2_PUB_REG_TYPE3__RESERVED_MASK                                                                    0xFFFFFFF8L
 353 //SDMA2_MMHUB_CNTL
 354 #define SDMA2_MMHUB_CNTL__UNIT_ID__SHIFT                                                                      0x0
 355 #define SDMA2_MMHUB_CNTL__UNIT_ID_MASK                                                                        0x0000003FL
 356 //SDMA2_CONTEXT_GROUP_BOUNDARY
 357 #define SDMA2_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT                                                         0x0
 358 #define SDMA2_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK                                                           0xFFFFFFFFL
 359 //SDMA2_POWER_CNTL
 360 #define SDMA2_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT                                                           0x8
 361 #define SDMA2_POWER_CNTL__MEM_POWER_LS_EN__SHIFT                                                              0x9
 362 #define SDMA2_POWER_CNTL__MEM_POWER_DS_EN__SHIFT                                                              0xa
 363 #define SDMA2_POWER_CNTL__MEM_POWER_SD_EN__SHIFT                                                              0xb
 364 #define SDMA2_POWER_CNTL__MEM_POWER_DELAY__SHIFT                                                              0xc
 365 #define SDMA2_POWER_CNTL__MEM_POWER_OVERRIDE_MASK                                                             0x00000100L
 366 #define SDMA2_POWER_CNTL__MEM_POWER_LS_EN_MASK                                                                0x00000200L
 367 #define SDMA2_POWER_CNTL__MEM_POWER_DS_EN_MASK                                                                0x00000400L
 368 #define SDMA2_POWER_CNTL__MEM_POWER_SD_EN_MASK                                                                0x00000800L
 369 #define SDMA2_POWER_CNTL__MEM_POWER_DELAY_MASK                                                                0x003FF000L
 370 //SDMA2_CLK_CTRL
 371 #define SDMA2_CLK_CTRL__ON_DELAY__SHIFT                                                                       0x0
 372 #define SDMA2_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                                 0x4
 373 #define SDMA2_CLK_CTRL__RESERVED__SHIFT                                                                       0xc
 374 #define SDMA2_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                                 0x18
 375 #define SDMA2_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                                 0x19
 376 #define SDMA2_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                                 0x1a
 377 #define SDMA2_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                                 0x1b
 378 #define SDMA2_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                                 0x1c
 379 #define SDMA2_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                                 0x1d
 380 #define SDMA2_CLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                                 0x1e
 381 #define SDMA2_CLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                                 0x1f
 382 #define SDMA2_CLK_CTRL__ON_DELAY_MASK                                                                         0x0000000FL
 383 #define SDMA2_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                   0x00000FF0L
 384 #define SDMA2_CLK_CTRL__RESERVED_MASK                                                                         0x00FFF000L
 385 #define SDMA2_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                                   0x01000000L
 386 #define SDMA2_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                                   0x02000000L
 387 #define SDMA2_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                                   0x04000000L
 388 #define SDMA2_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                                   0x08000000L
 389 #define SDMA2_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                                   0x10000000L
 390 #define SDMA2_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                                   0x20000000L
 391 #define SDMA2_CLK_CTRL__SOFT_OVERRIDE1_MASK                                                                   0x40000000L
 392 #define SDMA2_CLK_CTRL__SOFT_OVERRIDE0_MASK                                                                   0x80000000L
 393 //SDMA2_CNTL
 394 #define SDMA2_CNTL__TRAP_ENABLE__SHIFT                                                                        0x0
 395 #define SDMA2_CNTL__UTC_L1_ENABLE__SHIFT                                                                      0x1
 396 #define SDMA2_CNTL__SEM_WAIT_INT_ENABLE__SHIFT                                                                0x2
 397 #define SDMA2_CNTL__DATA_SWAP_ENABLE__SHIFT                                                                   0x3
 398 #define SDMA2_CNTL__FENCE_SWAP_ENABLE__SHIFT                                                                  0x4
 399 #define SDMA2_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                              0x5
 400 #define SDMA2_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT                                                          0x11
 401 #define SDMA2_CNTL__AUTO_CTXSW_ENABLE__SHIFT                                                                  0x12
 402 #define SDMA2_CNTL__CTXEMPTY_INT_ENABLE__SHIFT                                                                0x1c
 403 #define SDMA2_CNTL__FROZEN_INT_ENABLE__SHIFT                                                                  0x1d
 404 #define SDMA2_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT                                                              0x1e
 405 #define SDMA2_CNTL__TRAP_ENABLE_MASK                                                                          0x00000001L
 406 #define SDMA2_CNTL__UTC_L1_ENABLE_MASK                                                                        0x00000002L
 407 #define SDMA2_CNTL__SEM_WAIT_INT_ENABLE_MASK                                                                  0x00000004L
 408 #define SDMA2_CNTL__DATA_SWAP_ENABLE_MASK                                                                     0x00000008L
 409 #define SDMA2_CNTL__FENCE_SWAP_ENABLE_MASK                                                                    0x00000010L
 410 #define SDMA2_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                                0x00000020L
 411 #define SDMA2_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK                                                            0x00020000L
 412 #define SDMA2_CNTL__AUTO_CTXSW_ENABLE_MASK                                                                    0x00040000L
 413 #define SDMA2_CNTL__CTXEMPTY_INT_ENABLE_MASK                                                                  0x10000000L
 414 #define SDMA2_CNTL__FROZEN_INT_ENABLE_MASK                                                                    0x20000000L
 415 #define SDMA2_CNTL__IB_PREEMPT_INT_ENABLE_MASK                                                                0x40000000L
 416 //SDMA2_CHICKEN_BITS
 417 #define SDMA2_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT                                                     0x0
 418 #define SDMA2_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT                                                 0x1
 419 #define SDMA2_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT                                        0x2
 420 #define SDMA2_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT                                                         0x8
 421 #define SDMA2_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT                                                     0xa
 422 #define SDMA2_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT                                                        0x10
 423 #define SDMA2_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT                                                           0x11
 424 #define SDMA2_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT                                                         0x14
 425 #define SDMA2_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT                                                           0x17
 426 #define SDMA2_CHICKEN_BITS__TIME_BASED_QOS__SHIFT                                                             0x19
 427 #define SDMA2_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT                                                         0x1a
 428 #define SDMA2_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT                                                         0x1c
 429 #define SDMA2_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT                                                         0x1e
 430 #define SDMA2_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK                                                       0x00000001L
 431 #define SDMA2_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK                                                   0x00000002L
 432 #define SDMA2_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK                                          0x00000004L
 433 #define SDMA2_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK                                                           0x00000300L
 434 #define SDMA2_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK                                                       0x00001C00L
 435 #define SDMA2_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK                                                          0x00010000L
 436 #define SDMA2_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK                                                             0x00020000L
 437 #define SDMA2_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK                                                           0x00100000L
 438 #define SDMA2_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK                                                             0x00800000L
 439 #define SDMA2_CHICKEN_BITS__TIME_BASED_QOS_MASK                                                               0x02000000L
 440 #define SDMA2_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK                                                           0x0C000000L
 441 #define SDMA2_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK                                                           0x30000000L
 442 #define SDMA2_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK                                                           0xC0000000L
 443 //SDMA2_GB_ADDR_CONFIG
 444 #define SDMA2_GB_ADDR_CONFIG__NUM_PIPES__SHIFT                                                                0x0
 445 #define SDMA2_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                     0x3
 446 #define SDMA2_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT                                                     0x8
 447 #define SDMA2_GB_ADDR_CONFIG__NUM_BANKS__SHIFT                                                                0xc
 448 #define SDMA2_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT                                                       0x13
 449 #define SDMA2_GB_ADDR_CONFIG__NUM_PIPES_MASK                                                                  0x00000007L
 450 #define SDMA2_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                       0x00000038L
 451 #define SDMA2_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK                                                       0x00000700L
 452 #define SDMA2_GB_ADDR_CONFIG__NUM_BANKS_MASK                                                                  0x00007000L
 453 #define SDMA2_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK                                                         0x00180000L
 454 //SDMA2_GB_ADDR_CONFIG_READ
 455 #define SDMA2_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT                                                           0x0
 456 #define SDMA2_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT                                                0x3
 457 #define SDMA2_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT                                                0x8
 458 #define SDMA2_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT                                                           0xc
 459 #define SDMA2_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT                                                  0x13
 460 #define SDMA2_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK                                                             0x00000007L
 461 #define SDMA2_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK                                                  0x00000038L
 462 #define SDMA2_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK                                                  0x00000700L
 463 #define SDMA2_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK                                                             0x00007000L
 464 #define SDMA2_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK                                                    0x00180000L
 465 //SDMA2_RB_RPTR_FETCH_HI
 466 #define SDMA2_RB_RPTR_FETCH_HI__OFFSET__SHIFT                                                                 0x0
 467 #define SDMA2_RB_RPTR_FETCH_HI__OFFSET_MASK                                                                   0xFFFFFFFFL
 468 //SDMA2_SEM_WAIT_FAIL_TIMER_CNTL
 469 #define SDMA2_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT                                                          0x0
 470 #define SDMA2_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK                                                            0xFFFFFFFFL
 471 //SDMA2_RB_RPTR_FETCH
 472 #define SDMA2_RB_RPTR_FETCH__OFFSET__SHIFT                                                                    0x2
 473 #define SDMA2_RB_RPTR_FETCH__OFFSET_MASK                                                                      0xFFFFFFFCL
 474 //SDMA2_IB_OFFSET_FETCH
 475 #define SDMA2_IB_OFFSET_FETCH__OFFSET__SHIFT                                                                  0x2
 476 #define SDMA2_IB_OFFSET_FETCH__OFFSET_MASK                                                                    0x003FFFFCL
 477 //SDMA2_PROGRAM
 478 #define SDMA2_PROGRAM__STREAM__SHIFT                                                                          0x0
 479 #define SDMA2_PROGRAM__STREAM_MASK                                                                            0xFFFFFFFFL
 480 //SDMA2_STATUS_REG
 481 #define SDMA2_STATUS_REG__IDLE__SHIFT                                                                         0x0
 482 #define SDMA2_STATUS_REG__REG_IDLE__SHIFT                                                                     0x1
 483 #define SDMA2_STATUS_REG__RB_EMPTY__SHIFT                                                                     0x2
 484 #define SDMA2_STATUS_REG__RB_FULL__SHIFT                                                                      0x3
 485 #define SDMA2_STATUS_REG__RB_CMD_IDLE__SHIFT                                                                  0x4
 486 #define SDMA2_STATUS_REG__RB_CMD_FULL__SHIFT                                                                  0x5
 487 #define SDMA2_STATUS_REG__IB_CMD_IDLE__SHIFT                                                                  0x6
 488 #define SDMA2_STATUS_REG__IB_CMD_FULL__SHIFT                                                                  0x7
 489 #define SDMA2_STATUS_REG__BLOCK_IDLE__SHIFT                                                                   0x8
 490 #define SDMA2_STATUS_REG__INSIDE_IB__SHIFT                                                                    0x9
 491 #define SDMA2_STATUS_REG__EX_IDLE__SHIFT                                                                      0xa
 492 #define SDMA2_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT                                                    0xb
 493 #define SDMA2_STATUS_REG__PACKET_READY__SHIFT                                                                 0xc
 494 #define SDMA2_STATUS_REG__MC_WR_IDLE__SHIFT                                                                   0xd
 495 #define SDMA2_STATUS_REG__SRBM_IDLE__SHIFT                                                                    0xe
 496 #define SDMA2_STATUS_REG__CONTEXT_EMPTY__SHIFT                                                                0xf
 497 #define SDMA2_STATUS_REG__DELTA_RPTR_FULL__SHIFT                                                              0x10
 498 #define SDMA2_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT                                                              0x11
 499 #define SDMA2_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT                                                              0x12
 500 #define SDMA2_STATUS_REG__MC_RD_IDLE__SHIFT                                                                   0x13
 501 #define SDMA2_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT                                                             0x14
 502 #define SDMA2_STATUS_REG__MC_RD_RET_STALL__SHIFT                                                              0x15
 503 #define SDMA2_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT                                                           0x16
 504 #define SDMA2_STATUS_REG__PREV_CMD_IDLE__SHIFT                                                                0x19
 505 #define SDMA2_STATUS_REG__SEM_IDLE__SHIFT                                                                     0x1a
 506 #define SDMA2_STATUS_REG__SEM_REQ_STALL__SHIFT                                                                0x1b
 507 #define SDMA2_STATUS_REG__SEM_RESP_STATE__SHIFT                                                               0x1c
 508 #define SDMA2_STATUS_REG__INT_IDLE__SHIFT                                                                     0x1e
 509 #define SDMA2_STATUS_REG__INT_REQ_STALL__SHIFT                                                                0x1f
 510 #define SDMA2_STATUS_REG__IDLE_MASK                                                                           0x00000001L
 511 #define SDMA2_STATUS_REG__REG_IDLE_MASK                                                                       0x00000002L
 512 #define SDMA2_STATUS_REG__RB_EMPTY_MASK                                                                       0x00000004L
 513 #define SDMA2_STATUS_REG__RB_FULL_MASK                                                                        0x00000008L
 514 #define SDMA2_STATUS_REG__RB_CMD_IDLE_MASK                                                                    0x00000010L
 515 #define SDMA2_STATUS_REG__RB_CMD_FULL_MASK                                                                    0x00000020L
 516 #define SDMA2_STATUS_REG__IB_CMD_IDLE_MASK                                                                    0x00000040L
 517 #define SDMA2_STATUS_REG__IB_CMD_FULL_MASK                                                                    0x00000080L
 518 #define SDMA2_STATUS_REG__BLOCK_IDLE_MASK                                                                     0x00000100L
 519 #define SDMA2_STATUS_REG__INSIDE_IB_MASK                                                                      0x00000200L
 520 #define SDMA2_STATUS_REG__EX_IDLE_MASK                                                                        0x00000400L
 521 #define SDMA2_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK                                                      0x00000800L
 522 #define SDMA2_STATUS_REG__PACKET_READY_MASK                                                                   0x00001000L
 523 #define SDMA2_STATUS_REG__MC_WR_IDLE_MASK                                                                     0x00002000L
 524 #define SDMA2_STATUS_REG__SRBM_IDLE_MASK                                                                      0x00004000L
 525 #define SDMA2_STATUS_REG__CONTEXT_EMPTY_MASK                                                                  0x00008000L
 526 #define SDMA2_STATUS_REG__DELTA_RPTR_FULL_MASK                                                                0x00010000L
 527 #define SDMA2_STATUS_REG__RB_MC_RREQ_IDLE_MASK                                                                0x00020000L
 528 #define SDMA2_STATUS_REG__IB_MC_RREQ_IDLE_MASK                                                                0x00040000L
 529 #define SDMA2_STATUS_REG__MC_RD_IDLE_MASK                                                                     0x00080000L
 530 #define SDMA2_STATUS_REG__DELTA_RPTR_EMPTY_MASK                                                               0x00100000L
 531 #define SDMA2_STATUS_REG__MC_RD_RET_STALL_MASK                                                                0x00200000L
 532 #define SDMA2_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK                                                             0x00400000L
 533 #define SDMA2_STATUS_REG__PREV_CMD_IDLE_MASK                                                                  0x02000000L
 534 #define SDMA2_STATUS_REG__SEM_IDLE_MASK                                                                       0x04000000L
 535 #define SDMA2_STATUS_REG__SEM_REQ_STALL_MASK                                                                  0x08000000L
 536 #define SDMA2_STATUS_REG__SEM_RESP_STATE_MASK                                                                 0x30000000L
 537 #define SDMA2_STATUS_REG__INT_IDLE_MASK                                                                       0x40000000L
 538 #define SDMA2_STATUS_REG__INT_REQ_STALL_MASK                                                                  0x80000000L
 539 //SDMA2_STATUS1_REG
 540 #define SDMA2_STATUS1_REG__CE_WREQ_IDLE__SHIFT                                                                0x0
 541 #define SDMA2_STATUS1_REG__CE_WR_IDLE__SHIFT                                                                  0x1
 542 #define SDMA2_STATUS1_REG__CE_SPLIT_IDLE__SHIFT                                                               0x2
 543 #define SDMA2_STATUS1_REG__CE_RREQ_IDLE__SHIFT                                                                0x3
 544 #define SDMA2_STATUS1_REG__CE_OUT_IDLE__SHIFT                                                                 0x4
 545 #define SDMA2_STATUS1_REG__CE_IN_IDLE__SHIFT                                                                  0x5
 546 #define SDMA2_STATUS1_REG__CE_DST_IDLE__SHIFT                                                                 0x6
 547 #define SDMA2_STATUS1_REG__CE_CMD_IDLE__SHIFT                                                                 0x9
 548 #define SDMA2_STATUS1_REG__CE_AFIFO_FULL__SHIFT                                                               0xa
 549 #define SDMA2_STATUS1_REG__CE_INFO_FULL__SHIFT                                                                0xd
 550 #define SDMA2_STATUS1_REG__CE_INFO1_FULL__SHIFT                                                               0xe
 551 #define SDMA2_STATUS1_REG__EX_START__SHIFT                                                                    0xf
 552 #define SDMA2_STATUS1_REG__CE_RD_STALL__SHIFT                                                                 0x11
 553 #define SDMA2_STATUS1_REG__CE_WR_STALL__SHIFT                                                                 0x12
 554 #define SDMA2_STATUS1_REG__CE_WREQ_IDLE_MASK                                                                  0x00000001L
 555 #define SDMA2_STATUS1_REG__CE_WR_IDLE_MASK                                                                    0x00000002L
 556 #define SDMA2_STATUS1_REG__CE_SPLIT_IDLE_MASK                                                                 0x00000004L
 557 #define SDMA2_STATUS1_REG__CE_RREQ_IDLE_MASK                                                                  0x00000008L
 558 #define SDMA2_STATUS1_REG__CE_OUT_IDLE_MASK                                                                   0x00000010L
 559 #define SDMA2_STATUS1_REG__CE_IN_IDLE_MASK                                                                    0x00000020L
 560 #define SDMA2_STATUS1_REG__CE_DST_IDLE_MASK                                                                   0x00000040L
 561 #define SDMA2_STATUS1_REG__CE_CMD_IDLE_MASK                                                                   0x00000200L
 562 #define SDMA2_STATUS1_REG__CE_AFIFO_FULL_MASK                                                                 0x00000400L
 563 #define SDMA2_STATUS1_REG__CE_INFO_FULL_MASK                                                                  0x00002000L
 564 #define SDMA2_STATUS1_REG__CE_INFO1_FULL_MASK                                                                 0x00004000L
 565 #define SDMA2_STATUS1_REG__EX_START_MASK                                                                      0x00008000L
 566 #define SDMA2_STATUS1_REG__CE_RD_STALL_MASK                                                                   0x00020000L
 567 #define SDMA2_STATUS1_REG__CE_WR_STALL_MASK                                                                   0x00040000L
 568 //SDMA2_RD_BURST_CNTL
 569 #define SDMA2_RD_BURST_CNTL__RD_BURST__SHIFT                                                                  0x0
 570 #define SDMA2_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT                                                       0x2
 571 #define SDMA2_RD_BURST_CNTL__RD_BURST_MASK                                                                    0x00000003L
 572 #define SDMA2_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK                                                         0x0000000CL
 573 //SDMA2_HBM_PAGE_CONFIG
 574 #define SDMA2_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT                                                      0x0
 575 #define SDMA2_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK                                                        0x00000001L
 576 //SDMA2_UCODE_CHECKSUM
 577 #define SDMA2_UCODE_CHECKSUM__DATA__SHIFT                                                                     0x0
 578 #define SDMA2_UCODE_CHECKSUM__DATA_MASK                                                                       0xFFFFFFFFL
 579 //SDMA2_F32_CNTL
 580 #define SDMA2_F32_CNTL__HALT__SHIFT                                                                           0x0
 581 #define SDMA2_F32_CNTL__STEP__SHIFT                                                                           0x1
 582 #define SDMA2_F32_CNTL__HALT_MASK                                                                             0x00000001L
 583 #define SDMA2_F32_CNTL__STEP_MASK                                                                             0x00000002L
 584 //SDMA2_FREEZE
 585 #define SDMA2_FREEZE__PREEMPT__SHIFT                                                                          0x0
 586 #define SDMA2_FREEZE__FREEZE__SHIFT                                                                           0x4
 587 #define SDMA2_FREEZE__FROZEN__SHIFT                                                                           0x5
 588 #define SDMA2_FREEZE__F32_FREEZE__SHIFT                                                                       0x6
 589 #define SDMA2_FREEZE__PREEMPT_MASK                                                                            0x00000001L
 590 #define SDMA2_FREEZE__FREEZE_MASK                                                                             0x00000010L
 591 #define SDMA2_FREEZE__FROZEN_MASK                                                                             0x00000020L
 592 #define SDMA2_FREEZE__F32_FREEZE_MASK                                                                         0x00000040L
 593 //SDMA2_PHASE0_QUANTUM
 594 #define SDMA2_PHASE0_QUANTUM__UNIT__SHIFT                                                                     0x0
 595 #define SDMA2_PHASE0_QUANTUM__VALUE__SHIFT                                                                    0x8
 596 #define SDMA2_PHASE0_QUANTUM__PREFER__SHIFT                                                                   0x1e
 597 #define SDMA2_PHASE0_QUANTUM__UNIT_MASK                                                                       0x0000000FL
 598 #define SDMA2_PHASE0_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
 599 #define SDMA2_PHASE0_QUANTUM__PREFER_MASK                                                                     0x40000000L
 600 //SDMA2_PHASE1_QUANTUM
 601 #define SDMA2_PHASE1_QUANTUM__UNIT__SHIFT                                                                     0x0
 602 #define SDMA2_PHASE1_QUANTUM__VALUE__SHIFT                                                                    0x8
 603 #define SDMA2_PHASE1_QUANTUM__PREFER__SHIFT                                                                   0x1e
 604 #define SDMA2_PHASE1_QUANTUM__UNIT_MASK                                                                       0x0000000FL
 605 #define SDMA2_PHASE1_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
 606 #define SDMA2_PHASE1_QUANTUM__PREFER_MASK                                                                     0x40000000L
 607 //SDMA2_EDC_CONFIG
 608 #define SDMA2_EDC_CONFIG__DIS_EDC__SHIFT                                                                      0x1
 609 #define SDMA2_EDC_CONFIG__ECC_INT_ENABLE__SHIFT                                                               0x2
 610 #define SDMA2_EDC_CONFIG__DIS_EDC_MASK                                                                        0x00000002L
 611 #define SDMA2_EDC_CONFIG__ECC_INT_ENABLE_MASK                                                                 0x00000004L
 612 //SDMA2_BA_THRESHOLD
 613 #define SDMA2_BA_THRESHOLD__READ_THRES__SHIFT                                                                 0x0
 614 #define SDMA2_BA_THRESHOLD__WRITE_THRES__SHIFT                                                                0x10
 615 #define SDMA2_BA_THRESHOLD__READ_THRES_MASK                                                                   0x000003FFL
 616 #define SDMA2_BA_THRESHOLD__WRITE_THRES_MASK                                                                  0x03FF0000L
 617 //SDMA2_ID
 618 #define SDMA2_ID__DEVICE_ID__SHIFT                                                                            0x0
 619 #define SDMA2_ID__DEVICE_ID_MASK                                                                              0x000000FFL
 620 //SDMA2_VERSION
 621 #define SDMA2_VERSION__MINVER__SHIFT                                                                          0x0
 622 #define SDMA2_VERSION__MAJVER__SHIFT                                                                          0x8
 623 #define SDMA2_VERSION__REV__SHIFT                                                                             0x10
 624 #define SDMA2_VERSION__MINVER_MASK                                                                            0x0000007FL
 625 #define SDMA2_VERSION__MAJVER_MASK                                                                            0x00007F00L
 626 #define SDMA2_VERSION__REV_MASK                                                                               0x003F0000L
 627 //SDMA2_EDC_COUNTER
 628 #define SDMA2_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT                                                          0x0
 629 #define SDMA2_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT                                                         0x2
 630 #define SDMA2_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT                                                         0x3
 631 #define SDMA2_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT                                                      0x4
 632 #define SDMA2_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT                                                   0x5
 633 #define SDMA2_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT                                                      0x6
 634 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT                                                    0x7
 635 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT                                                    0x8
 636 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT                                                    0x9
 637 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT                                                    0xa
 638 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT                                                    0xb
 639 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT                                                    0xc
 640 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT                                                    0xd
 641 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT                                                    0xe
 642 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT                                                    0xf
 643 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT                                                    0x10
 644 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT                                                   0x11
 645 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT                                                   0x12
 646 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT                                                   0x13
 647 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT                                                   0x14
 648 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT                                                   0x15
 649 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT                                                   0x16
 650 #define SDMA2_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT                                                      0x17
 651 #define SDMA2_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT                                                    0x18
 652 #define SDMA2_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK                                                            0x00000001L
 653 #define SDMA2_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK                                                           0x00000004L
 654 #define SDMA2_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK                                                           0x00000008L
 655 #define SDMA2_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK                                                        0x00000010L
 656 #define SDMA2_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK                                                     0x00000020L
 657 #define SDMA2_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK                                                        0x00000040L
 658 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK                                                      0x00000080L
 659 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK                                                      0x00000100L
 660 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK                                                      0x00000200L
 661 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK                                                      0x00000400L
 662 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK                                                      0x00000800L
 663 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK                                                      0x00001000L
 664 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK                                                      0x00002000L
 665 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK                                                      0x00004000L
 666 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK                                                      0x00008000L
 667 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK                                                      0x00010000L
 668 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK                                                     0x00020000L
 669 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK                                                     0x00040000L
 670 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK                                                     0x00080000L
 671 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK                                                     0x00100000L
 672 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK                                                     0x00200000L
 673 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK                                                     0x00400000L
 674 #define SDMA2_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK                                                        0x00800000L
 675 #define SDMA2_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK                                                      0x01000000L
 676 //SDMA2_EDC_COUNTER_CLEAR
 677 #define SDMA2_EDC_COUNTER_CLEAR__DUMMY__SHIFT                                                                 0x0
 678 #define SDMA2_EDC_COUNTER_CLEAR__DUMMY_MASK                                                                   0x00000001L
 679 //SDMA2_STATUS2_REG
 680 #define SDMA2_STATUS2_REG__ID__SHIFT                                                                          0x0
 681 #define SDMA2_STATUS2_REG__F32_INSTR_PTR__SHIFT                                                               0x3
 682 #define SDMA2_STATUS2_REG__CMD_OP__SHIFT                                                                      0x10
 683 #define SDMA2_STATUS2_REG__ID_MASK                                                                            0x00000007L
 684 #define SDMA2_STATUS2_REG__F32_INSTR_PTR_MASK                                                                 0x0000FFF8L
 685 #define SDMA2_STATUS2_REG__CMD_OP_MASK                                                                        0xFFFF0000L
 686 //SDMA2_ATOMIC_CNTL
 687 #define SDMA2_ATOMIC_CNTL__LOOP_TIMER__SHIFT                                                                  0x0
 688 #define SDMA2_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT                                                       0x1f
 689 #define SDMA2_ATOMIC_CNTL__LOOP_TIMER_MASK                                                                    0x7FFFFFFFL
 690 #define SDMA2_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK                                                         0x80000000L
 691 //SDMA2_ATOMIC_PREOP_LO
 692 #define SDMA2_ATOMIC_PREOP_LO__DATA__SHIFT                                                                    0x0
 693 #define SDMA2_ATOMIC_PREOP_LO__DATA_MASK                                                                      0xFFFFFFFFL
 694 //SDMA2_ATOMIC_PREOP_HI
 695 #define SDMA2_ATOMIC_PREOP_HI__DATA__SHIFT                                                                    0x0
 696 #define SDMA2_ATOMIC_PREOP_HI__DATA_MASK                                                                      0xFFFFFFFFL
 697 //SDMA2_UTCL1_CNTL
 698 #define SDMA2_UTCL1_CNTL__REDO_ENABLE__SHIFT                                                                  0x0
 699 #define SDMA2_UTCL1_CNTL__REDO_DELAY__SHIFT                                                                   0x1
 700 #define SDMA2_UTCL1_CNTL__REDO_WATERMK__SHIFT                                                                 0xb
 701 #define SDMA2_UTCL1_CNTL__INVACK_DELAY__SHIFT                                                                 0xe
 702 #define SDMA2_UTCL1_CNTL__REQL2_CREDIT__SHIFT                                                                 0x18
 703 #define SDMA2_UTCL1_CNTL__VADDR_WATERMK__SHIFT                                                                0x1d
 704 #define SDMA2_UTCL1_CNTL__REDO_ENABLE_MASK                                                                    0x00000001L
 705 #define SDMA2_UTCL1_CNTL__REDO_DELAY_MASK                                                                     0x000007FEL
 706 #define SDMA2_UTCL1_CNTL__REDO_WATERMK_MASK                                                                   0x00003800L
 707 #define SDMA2_UTCL1_CNTL__INVACK_DELAY_MASK                                                                   0x00FFC000L
 708 #define SDMA2_UTCL1_CNTL__REQL2_CREDIT_MASK                                                                   0x1F000000L
 709 #define SDMA2_UTCL1_CNTL__VADDR_WATERMK_MASK                                                                  0xE0000000L
 710 //SDMA2_UTCL1_WATERMK
 711 #define SDMA2_UTCL1_WATERMK__REQMC_WATERMK__SHIFT                                                             0x0
 712 #define SDMA2_UTCL1_WATERMK__REQPG_WATERMK__SHIFT                                                             0x9
 713 #define SDMA2_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT                                                            0x11
 714 #define SDMA2_UTCL1_WATERMK__XNACK_WATERMK__SHIFT                                                             0x19
 715 #define SDMA2_UTCL1_WATERMK__REQMC_WATERMK_MASK                                                               0x000001FFL
 716 #define SDMA2_UTCL1_WATERMK__REQPG_WATERMK_MASK                                                               0x0001FE00L
 717 #define SDMA2_UTCL1_WATERMK__INVREQ_WATERMK_MASK                                                              0x01FE0000L
 718 #define SDMA2_UTCL1_WATERMK__XNACK_WATERMK_MASK                                                               0xFE000000L
 719 //SDMA2_UTCL1_RD_STATUS
 720 #define SDMA2_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT                                                0x0
 721 #define SDMA2_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT                                                     0x1
 722 #define SDMA2_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT                                                      0x2
 723 #define SDMA2_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT                                                   0x3
 724 #define SDMA2_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT                                               0x4
 725 #define SDMA2_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT                                                    0x5
 726 #define SDMA2_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT                                                 0x6
 727 #define SDMA2_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT                                                   0x7
 728 #define SDMA2_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT                                                  0x8
 729 #define SDMA2_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT                                                 0x9
 730 #define SDMA2_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT                                                      0xa
 731 #define SDMA2_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT                                                       0xb
 732 #define SDMA2_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT                                                    0xc
 733 #define SDMA2_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT                                                0xd
 734 #define SDMA2_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT                                                     0xe
 735 #define SDMA2_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT                                                  0xf
 736 #define SDMA2_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT                                                    0x10
 737 #define SDMA2_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT                                                   0x11
 738 #define SDMA2_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT                                                              0x12
 739 #define SDMA2_UTCL1_RD_STATUS__PAGE_NULL__SHIFT                                                               0x13
 740 #define SDMA2_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT                                                              0x14
 741 #define SDMA2_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT                                                             0x15
 742 #define SDMA2_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT                                                          0x16
 743 #define SDMA2_UTCL1_RD_STATUS__MERGE_STATE__SHIFT                                                             0x1a
 744 #define SDMA2_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT                                                             0x1d
 745 #define SDMA2_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT                                                            0x1e
 746 #define SDMA2_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT                                                             0x1f
 747 #define SDMA2_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK                                                  0x00000001L
 748 #define SDMA2_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK                                                       0x00000002L
 749 #define SDMA2_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK                                                        0x00000004L
 750 #define SDMA2_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK                                                     0x00000008L
 751 #define SDMA2_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK                                                 0x00000010L
 752 #define SDMA2_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK                                                      0x00000020L
 753 #define SDMA2_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK                                                   0x00000040L
 754 #define SDMA2_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK                                                     0x00000080L
 755 #define SDMA2_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK                                                    0x00000100L
 756 #define SDMA2_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK                                                   0x00000200L
 757 #define SDMA2_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK                                                        0x00000400L
 758 #define SDMA2_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK                                                         0x00000800L
 759 #define SDMA2_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK                                                      0x00001000L
 760 #define SDMA2_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK                                                  0x00002000L
 761 #define SDMA2_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK                                                       0x00004000L
 762 #define SDMA2_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK                                                    0x00008000L
 763 #define SDMA2_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK                                                      0x00010000L
 764 #define SDMA2_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK                                                     0x00020000L
 765 #define SDMA2_UTCL1_RD_STATUS__PAGE_FAULT_MASK                                                                0x00040000L
 766 #define SDMA2_UTCL1_RD_STATUS__PAGE_NULL_MASK                                                                 0x00080000L
 767 #define SDMA2_UTCL1_RD_STATUS__REQL2_IDLE_MASK                                                                0x00100000L
 768 #define SDMA2_UTCL1_RD_STATUS__CE_L1_STALL_MASK                                                               0x00200000L
 769 #define SDMA2_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK                                                            0x03C00000L
 770 #define SDMA2_UTCL1_RD_STATUS__MERGE_STATE_MASK                                                               0x1C000000L
 771 #define SDMA2_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK                                                               0x20000000L
 772 #define SDMA2_UTCL1_RD_STATUS__WPTR_POLLING_MASK                                                              0x40000000L
 773 #define SDMA2_UTCL1_RD_STATUS__INVREQ_SIZE_MASK                                                               0x80000000L
 774 //SDMA2_UTCL1_WR_STATUS
 775 #define SDMA2_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT                                                0x0
 776 #define SDMA2_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT                                                     0x1
 777 #define SDMA2_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT                                                      0x2
 778 #define SDMA2_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT                                                   0x3
 779 #define SDMA2_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT                                               0x4
 780 #define SDMA2_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT                                                    0x5
 781 #define SDMA2_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT                                                 0x6
 782 #define SDMA2_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT                                                   0x7
 783 #define SDMA2_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT                                                  0x8
 784 #define SDMA2_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT                                                 0x9
 785 #define SDMA2_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT                                                      0xa
 786 #define SDMA2_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT                                                       0xb
 787 #define SDMA2_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT                                                    0xc
 788 #define SDMA2_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT                                                0xd
 789 #define SDMA2_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT                                                     0xe
 790 #define SDMA2_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT                                                  0xf
 791 #define SDMA2_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT                                                    0x10
 792 #define SDMA2_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT                                                   0x11
 793 #define SDMA2_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT                                                              0x12
 794 #define SDMA2_UTCL1_WR_STATUS__PAGE_NULL__SHIFT                                                               0x13
 795 #define SDMA2_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT                                                              0x14
 796 #define SDMA2_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT                                                              0x15
 797 #define SDMA2_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT                                                          0x16
 798 #define SDMA2_UTCL1_WR_STATUS__MERGE_STATE__SHIFT                                                             0x19
 799 #define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT                                                    0x1c
 800 #define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT                                                     0x1d
 801 #define SDMA2_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT                                                   0x1e
 802 #define SDMA2_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT                                                    0x1f
 803 #define SDMA2_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK                                                  0x00000001L
 804 #define SDMA2_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK                                                       0x00000002L
 805 #define SDMA2_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK                                                        0x00000004L
 806 #define SDMA2_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK                                                     0x00000008L
 807 #define SDMA2_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK                                                 0x00000010L
 808 #define SDMA2_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK                                                      0x00000020L
 809 #define SDMA2_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK                                                   0x00000040L
 810 #define SDMA2_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK                                                     0x00000080L
 811 #define SDMA2_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK                                                    0x00000100L
 812 #define SDMA2_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK                                                   0x00000200L
 813 #define SDMA2_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK                                                        0x00000400L
 814 #define SDMA2_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK                                                         0x00000800L
 815 #define SDMA2_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK                                                      0x00001000L
 816 #define SDMA2_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK                                                  0x00002000L
 817 #define SDMA2_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK                                                       0x00004000L
 818 #define SDMA2_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK                                                    0x00008000L
 819 #define SDMA2_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK                                                      0x00010000L
 820 #define SDMA2_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK                                                     0x00020000L
 821 #define SDMA2_UTCL1_WR_STATUS__PAGE_FAULT_MASK                                                                0x00040000L
 822 #define SDMA2_UTCL1_WR_STATUS__PAGE_NULL_MASK                                                                 0x00080000L
 823 #define SDMA2_UTCL1_WR_STATUS__REQL2_IDLE_MASK                                                                0x00100000L
 824 #define SDMA2_UTCL1_WR_STATUS__F32_WR_RTR_MASK                                                                0x00200000L
 825 #define SDMA2_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK                                                            0x01C00000L
 826 #define SDMA2_UTCL1_WR_STATUS__MERGE_STATE_MASK                                                               0x0E000000L
 827 #define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK                                                      0x10000000L
 828 #define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK                                                       0x20000000L
 829 #define SDMA2_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK                                                     0x40000000L
 830 #define SDMA2_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK                                                      0x80000000L
 831 //SDMA2_UTCL1_INV0
 832 #define SDMA2_UTCL1_INV0__INV_MIDDLE__SHIFT                                                                   0x0
 833 #define SDMA2_UTCL1_INV0__RD_TIMEOUT__SHIFT                                                                   0x1
 834 #define SDMA2_UTCL1_INV0__WR_TIMEOUT__SHIFT                                                                   0x2
 835 #define SDMA2_UTCL1_INV0__RD_IN_INVADR__SHIFT                                                                 0x3
 836 #define SDMA2_UTCL1_INV0__WR_IN_INVADR__SHIFT                                                                 0x4
 837 #define SDMA2_UTCL1_INV0__PAGE_NULL_SW__SHIFT                                                                 0x5
 838 #define SDMA2_UTCL1_INV0__XNACK_IS_INVADR__SHIFT                                                              0x6
 839 #define SDMA2_UTCL1_INV0__INVREQ_ENABLE__SHIFT                                                                0x7
 840 #define SDMA2_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT                                                              0x8
 841 #define SDMA2_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT                                                              0x9
 842 #define SDMA2_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT                                                               0xa
 843 #define SDMA2_UTCL1_INV0__INV_FLUSHTYPE__SHIFT                                                                0xb
 844 #define SDMA2_UTCL1_INV0__INV_VMID_VEC__SHIFT                                                                 0xc
 845 #define SDMA2_UTCL1_INV0__INV_ADDR_HI__SHIFT                                                                  0x1c
 846 #define SDMA2_UTCL1_INV0__INV_MIDDLE_MASK                                                                     0x00000001L
 847 #define SDMA2_UTCL1_INV0__RD_TIMEOUT_MASK                                                                     0x00000002L
 848 #define SDMA2_UTCL1_INV0__WR_TIMEOUT_MASK                                                                     0x00000004L
 849 #define SDMA2_UTCL1_INV0__RD_IN_INVADR_MASK                                                                   0x00000008L
 850 #define SDMA2_UTCL1_INV0__WR_IN_INVADR_MASK                                                                   0x00000010L
 851 #define SDMA2_UTCL1_INV0__PAGE_NULL_SW_MASK                                                                   0x00000020L
 852 #define SDMA2_UTCL1_INV0__XNACK_IS_INVADR_MASK                                                                0x00000040L
 853 #define SDMA2_UTCL1_INV0__INVREQ_ENABLE_MASK                                                                  0x00000080L
 854 #define SDMA2_UTCL1_INV0__NACK_TIMEOUT_SW_MASK                                                                0x00000100L
 855 #define SDMA2_UTCL1_INV0__NFLUSH_INV_IDLE_MASK                                                                0x00000200L
 856 #define SDMA2_UTCL1_INV0__FLUSH_INV_IDLE_MASK                                                                 0x00000400L
 857 #define SDMA2_UTCL1_INV0__INV_FLUSHTYPE_MASK                                                                  0x00000800L
 858 #define SDMA2_UTCL1_INV0__INV_VMID_VEC_MASK                                                                   0x0FFFF000L
 859 #define SDMA2_UTCL1_INV0__INV_ADDR_HI_MASK                                                                    0xF0000000L
 860 //SDMA2_UTCL1_INV1
 861 #define SDMA2_UTCL1_INV1__INV_ADDR_LO__SHIFT                                                                  0x0
 862 #define SDMA2_UTCL1_INV1__INV_ADDR_LO_MASK                                                                    0xFFFFFFFFL
 863 //SDMA2_UTCL1_INV2
 864 #define SDMA2_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT                                                          0x0
 865 #define SDMA2_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK                                                            0xFFFFFFFFL
 866 //SDMA2_UTCL1_RD_XNACK0
 867 #define SDMA2_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT                                                           0x0
 868 #define SDMA2_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK                                                             0xFFFFFFFFL
 869 //SDMA2_UTCL1_RD_XNACK1
 870 #define SDMA2_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT                                                           0x0
 871 #define SDMA2_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT                                                              0x4
 872 #define SDMA2_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT                                                            0x8
 873 #define SDMA2_UTCL1_RD_XNACK1__IS_XNACK__SHIFT                                                                0x1a
 874 #define SDMA2_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK                                                             0x0000000FL
 875 #define SDMA2_UTCL1_RD_XNACK1__XNACK_VMID_MASK                                                                0x000000F0L
 876 #define SDMA2_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK                                                              0x03FFFF00L
 877 #define SDMA2_UTCL1_RD_XNACK1__IS_XNACK_MASK                                                                  0x0C000000L
 878 //SDMA2_UTCL1_WR_XNACK0
 879 #define SDMA2_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT                                                           0x0
 880 #define SDMA2_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK                                                             0xFFFFFFFFL
 881 //SDMA2_UTCL1_WR_XNACK1
 882 #define SDMA2_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT                                                           0x0
 883 #define SDMA2_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT                                                              0x4
 884 #define SDMA2_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT                                                            0x8
 885 #define SDMA2_UTCL1_WR_XNACK1__IS_XNACK__SHIFT                                                                0x1a
 886 #define SDMA2_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK                                                             0x0000000FL
 887 #define SDMA2_UTCL1_WR_XNACK1__XNACK_VMID_MASK                                                                0x000000F0L
 888 #define SDMA2_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK                                                              0x03FFFF00L
 889 #define SDMA2_UTCL1_WR_XNACK1__IS_XNACK_MASK                                                                  0x0C000000L
 890 //SDMA2_UTCL1_TIMEOUT
 891 #define SDMA2_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT                                                            0x0
 892 #define SDMA2_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT                                                            0x10
 893 #define SDMA2_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK                                                              0x0000FFFFL
 894 #define SDMA2_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK                                                              0xFFFF0000L
 895 //SDMA2_UTCL1_PAGE
 896 #define SDMA2_UTCL1_PAGE__VM_HOLE__SHIFT                                                                      0x0
 897 #define SDMA2_UTCL1_PAGE__REQ_TYPE__SHIFT                                                                     0x1
 898 #define SDMA2_UTCL1_PAGE__USE_MTYPE__SHIFT                                                                    0x6
 899 #define SDMA2_UTCL1_PAGE__USE_PT_SNOOP__SHIFT                                                                 0x9
 900 #define SDMA2_UTCL1_PAGE__VM_HOLE_MASK                                                                        0x00000001L
 901 #define SDMA2_UTCL1_PAGE__REQ_TYPE_MASK                                                                       0x0000001EL
 902 #define SDMA2_UTCL1_PAGE__USE_MTYPE_MASK                                                                      0x000001C0L
 903 #define SDMA2_UTCL1_PAGE__USE_PT_SNOOP_MASK                                                                   0x00000200L
 904 //SDMA2_POWER_CNTL_IDLE
 905 #define SDMA2_POWER_CNTL_IDLE__DELAY0__SHIFT                                                                  0x0
 906 #define SDMA2_POWER_CNTL_IDLE__DELAY1__SHIFT                                                                  0x10
 907 #define SDMA2_POWER_CNTL_IDLE__DELAY2__SHIFT                                                                  0x18
 908 #define SDMA2_POWER_CNTL_IDLE__DELAY0_MASK                                                                    0x0000FFFFL
 909 #define SDMA2_POWER_CNTL_IDLE__DELAY1_MASK                                                                    0x00FF0000L
 910 #define SDMA2_POWER_CNTL_IDLE__DELAY2_MASK                                                                    0xFF000000L
 911 //SDMA2_RELAX_ORDERING_LUT
 912 #define SDMA2_RELAX_ORDERING_LUT__RESERVED0__SHIFT                                                            0x0
 913 #define SDMA2_RELAX_ORDERING_LUT__COPY__SHIFT                                                                 0x1
 914 #define SDMA2_RELAX_ORDERING_LUT__WRITE__SHIFT                                                                0x2
 915 #define SDMA2_RELAX_ORDERING_LUT__RESERVED3__SHIFT                                                            0x3
 916 #define SDMA2_RELAX_ORDERING_LUT__RESERVED4__SHIFT                                                            0x4
 917 #define SDMA2_RELAX_ORDERING_LUT__FENCE__SHIFT                                                                0x5
 918 #define SDMA2_RELAX_ORDERING_LUT__RESERVED76__SHIFT                                                           0x6
 919 #define SDMA2_RELAX_ORDERING_LUT__POLL_MEM__SHIFT                                                             0x8
 920 #define SDMA2_RELAX_ORDERING_LUT__COND_EXE__SHIFT                                                             0x9
 921 #define SDMA2_RELAX_ORDERING_LUT__ATOMIC__SHIFT                                                               0xa
 922 #define SDMA2_RELAX_ORDERING_LUT__CONST_FILL__SHIFT                                                           0xb
 923 #define SDMA2_RELAX_ORDERING_LUT__PTEPDE__SHIFT                                                               0xc
 924 #define SDMA2_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT                                                            0xd
 925 #define SDMA2_RELAX_ORDERING_LUT__RESERVED__SHIFT                                                             0xe
 926 #define SDMA2_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT                                                         0x1b
 927 #define SDMA2_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT                                                             0x1c
 928 #define SDMA2_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT                                                            0x1d
 929 #define SDMA2_RELAX_ORDERING_LUT__IB_FETCH__SHIFT                                                             0x1e
 930 #define SDMA2_RELAX_ORDERING_LUT__RB_FETCH__SHIFT                                                             0x1f
 931 #define SDMA2_RELAX_ORDERING_LUT__RESERVED0_MASK                                                              0x00000001L
 932 #define SDMA2_RELAX_ORDERING_LUT__COPY_MASK                                                                   0x00000002L
 933 #define SDMA2_RELAX_ORDERING_LUT__WRITE_MASK                                                                  0x00000004L
 934 #define SDMA2_RELAX_ORDERING_LUT__RESERVED3_MASK                                                              0x00000008L
 935 #define SDMA2_RELAX_ORDERING_LUT__RESERVED4_MASK                                                              0x00000010L
 936 #define SDMA2_RELAX_ORDERING_LUT__FENCE_MASK                                                                  0x00000020L
 937 #define SDMA2_RELAX_ORDERING_LUT__RESERVED76_MASK                                                             0x000000C0L
 938 #define SDMA2_RELAX_ORDERING_LUT__POLL_MEM_MASK                                                               0x00000100L
 939 #define SDMA2_RELAX_ORDERING_LUT__COND_EXE_MASK                                                               0x00000200L
 940 #define SDMA2_RELAX_ORDERING_LUT__ATOMIC_MASK                                                                 0x00000400L
 941 #define SDMA2_RELAX_ORDERING_LUT__CONST_FILL_MASK                                                             0x00000800L
 942 #define SDMA2_RELAX_ORDERING_LUT__PTEPDE_MASK                                                                 0x00001000L
 943 #define SDMA2_RELAX_ORDERING_LUT__TIMESTAMP_MASK                                                              0x00002000L
 944 #define SDMA2_RELAX_ORDERING_LUT__RESERVED_MASK                                                               0x07FFC000L
 945 #define SDMA2_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK                                                           0x08000000L
 946 #define SDMA2_RELAX_ORDERING_LUT__RPTR_WRB_MASK                                                               0x10000000L
 947 #define SDMA2_RELAX_ORDERING_LUT__WPTR_POLL_MASK                                                              0x20000000L
 948 #define SDMA2_RELAX_ORDERING_LUT__IB_FETCH_MASK                                                               0x40000000L
 949 #define SDMA2_RELAX_ORDERING_LUT__RB_FETCH_MASK                                                               0x80000000L
 950 //SDMA2_CHICKEN_BITS_2
 951 #define SDMA2_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT                                                       0x0
 952 #define SDMA2_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK                                                         0x0000000FL
 953 //SDMA2_STATUS3_REG
 954 #define SDMA2_STATUS3_REG__CMD_OP_STATUS__SHIFT                                                               0x0
 955 #define SDMA2_STATUS3_REG__PREV_VM_CMD__SHIFT                                                                 0x10
 956 #define SDMA2_STATUS3_REG__EXCEPTION_IDLE__SHIFT                                                              0x14
 957 #define SDMA2_STATUS3_REG__QUEUE_ID_MATCH__SHIFT                                                              0x15
 958 #define SDMA2_STATUS3_REG__INT_QUEUE_ID__SHIFT                                                                0x16
 959 #define SDMA2_STATUS3_REG__CMD_OP_STATUS_MASK                                                                 0x0000FFFFL
 960 #define SDMA2_STATUS3_REG__PREV_VM_CMD_MASK                                                                   0x000F0000L
 961 #define SDMA2_STATUS3_REG__EXCEPTION_IDLE_MASK                                                                0x00100000L
 962 #define SDMA2_STATUS3_REG__QUEUE_ID_MATCH_MASK                                                                0x00200000L
 963 #define SDMA2_STATUS3_REG__INT_QUEUE_ID_MASK                                                                  0x03C00000L
 964 //SDMA2_PHYSICAL_ADDR_LO
 965 #define SDMA2_PHYSICAL_ADDR_LO__D_VALID__SHIFT                                                                0x0
 966 #define SDMA2_PHYSICAL_ADDR_LO__DIRTY__SHIFT                                                                  0x1
 967 #define SDMA2_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT                                                              0x2
 968 #define SDMA2_PHYSICAL_ADDR_LO__ADDR__SHIFT                                                                   0xc
 969 #define SDMA2_PHYSICAL_ADDR_LO__D_VALID_MASK                                                                  0x00000001L
 970 #define SDMA2_PHYSICAL_ADDR_LO__DIRTY_MASK                                                                    0x00000002L
 971 #define SDMA2_PHYSICAL_ADDR_LO__PHY_VALID_MASK                                                                0x00000004L
 972 #define SDMA2_PHYSICAL_ADDR_LO__ADDR_MASK                                                                     0xFFFFF000L
 973 //SDMA2_PHYSICAL_ADDR_HI
 974 #define SDMA2_PHYSICAL_ADDR_HI__ADDR__SHIFT                                                                   0x0
 975 #define SDMA2_PHYSICAL_ADDR_HI__ADDR_MASK                                                                     0x0000FFFFL
 976 //SDMA2_PHASE2_QUANTUM
 977 #define SDMA2_PHASE2_QUANTUM__UNIT__SHIFT                                                                     0x0
 978 #define SDMA2_PHASE2_QUANTUM__VALUE__SHIFT                                                                    0x8
 979 #define SDMA2_PHASE2_QUANTUM__PREFER__SHIFT                                                                   0x1e
 980 #define SDMA2_PHASE2_QUANTUM__UNIT_MASK                                                                       0x0000000FL
 981 #define SDMA2_PHASE2_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
 982 #define SDMA2_PHASE2_QUANTUM__PREFER_MASK                                                                     0x40000000L
 983 //SDMA2_ERROR_LOG
 984 #define SDMA2_ERROR_LOG__OVERRIDE__SHIFT                                                                      0x0
 985 #define SDMA2_ERROR_LOG__STATUS__SHIFT                                                                        0x10
 986 #define SDMA2_ERROR_LOG__OVERRIDE_MASK                                                                        0x0000FFFFL
 987 #define SDMA2_ERROR_LOG__STATUS_MASK                                                                          0xFFFF0000L
 988 //SDMA2_PUB_DUMMY_REG0
 989 #define SDMA2_PUB_DUMMY_REG0__VALUE__SHIFT                                                                    0x0
 990 #define SDMA2_PUB_DUMMY_REG0__VALUE_MASK                                                                      0xFFFFFFFFL
 991 //SDMA2_PUB_DUMMY_REG1
 992 #define SDMA2_PUB_DUMMY_REG1__VALUE__SHIFT                                                                    0x0
 993 #define SDMA2_PUB_DUMMY_REG1__VALUE_MASK                                                                      0xFFFFFFFFL
 994 //SDMA2_PUB_DUMMY_REG2
 995 #define SDMA2_PUB_DUMMY_REG2__VALUE__SHIFT                                                                    0x0
 996 #define SDMA2_PUB_DUMMY_REG2__VALUE_MASK                                                                      0xFFFFFFFFL
 997 //SDMA2_PUB_DUMMY_REG3
 998 #define SDMA2_PUB_DUMMY_REG3__VALUE__SHIFT                                                                    0x0
 999 #define SDMA2_PUB_DUMMY_REG3__VALUE_MASK                                                                      0xFFFFFFFFL
1000 //SDMA2_F32_COUNTER
1001 #define SDMA2_F32_COUNTER__VALUE__SHIFT                                                                       0x0
1002 #define SDMA2_F32_COUNTER__VALUE_MASK                                                                         0xFFFFFFFFL
1003 //SDMA2_UNBREAKABLE
1004 #define SDMA2_UNBREAKABLE__VALUE__SHIFT                                                                       0x0
1005 #define SDMA2_UNBREAKABLE__VALUE_MASK                                                                         0x00000001L
1006 //SDMA2_PERFMON_CNTL
1007 #define SDMA2_PERFMON_CNTL__PERF_ENABLE0__SHIFT                                                               0x0
1008 #define SDMA2_PERFMON_CNTL__PERF_CLEAR0__SHIFT                                                                0x1
1009 #define SDMA2_PERFMON_CNTL__PERF_SEL0__SHIFT                                                                  0x2
1010 #define SDMA2_PERFMON_CNTL__PERF_ENABLE1__SHIFT                                                               0xa
1011 #define SDMA2_PERFMON_CNTL__PERF_CLEAR1__SHIFT                                                                0xb
1012 #define SDMA2_PERFMON_CNTL__PERF_SEL1__SHIFT                                                                  0xc
1013 #define SDMA2_PERFMON_CNTL__PERF_ENABLE0_MASK                                                                 0x00000001L
1014 #define SDMA2_PERFMON_CNTL__PERF_CLEAR0_MASK                                                                  0x00000002L
1015 #define SDMA2_PERFMON_CNTL__PERF_SEL0_MASK                                                                    0x000003FCL
1016 #define SDMA2_PERFMON_CNTL__PERF_ENABLE1_MASK                                                                 0x00000400L
1017 #define SDMA2_PERFMON_CNTL__PERF_CLEAR1_MASK                                                                  0x00000800L
1018 #define SDMA2_PERFMON_CNTL__PERF_SEL1_MASK                                                                    0x000FF000L
1019 //SDMA2_PERFCOUNTER0_RESULT
1020 #define SDMA2_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT                                                          0x0
1021 #define SDMA2_PERFCOUNTER0_RESULT__PERF_COUNT_MASK                                                            0xFFFFFFFFL
1022 //SDMA2_PERFCOUNTER1_RESULT
1023 #define SDMA2_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT                                                          0x0
1024 #define SDMA2_PERFCOUNTER1_RESULT__PERF_COUNT_MASK                                                            0xFFFFFFFFL
1025 //SDMA2_PERFCOUNTER_TAG_DELAY_RANGE
1026 #define SDMA2_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT                                                   0x0
1027 #define SDMA2_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT                                                  0xe
1028 #define SDMA2_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT                                                   0x1c
1029 #define SDMA2_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK                                                     0x00003FFFL
1030 #define SDMA2_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK                                                    0x0FFFC000L
1031 #define SDMA2_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK                                                     0x10000000L
1032 //SDMA2_CRD_CNTL
1033 #define SDMA2_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT                                                                0x7
1034 #define SDMA2_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT                                                                0xd
1035 #define SDMA2_CRD_CNTL__MC_WRREQ_CREDIT_MASK                                                                  0x00001F80L
1036 #define SDMA2_CRD_CNTL__MC_RDREQ_CREDIT_MASK                                                                  0x0007E000L
1037 //SDMA2_GPU_IOV_VIOLATION_LOG
1038 #define SDMA2_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT                                                  0x0
1039 #define SDMA2_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT                                         0x1
1040 #define SDMA2_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT                                                           0x2
1041 #define SDMA2_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT                                                   0x14
1042 #define SDMA2_GPU_IOV_VIOLATION_LOG__VF__SHIFT                                                                0x15
1043 #define SDMA2_GPU_IOV_VIOLATION_LOG__VFID__SHIFT                                                              0x16
1044 #define SDMA2_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK                                                    0x00000001L
1045 #define SDMA2_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK                                           0x00000002L
1046 #define SDMA2_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK                                                             0x000FFFFCL
1047 #define SDMA2_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK                                                     0x00100000L
1048 #define SDMA2_GPU_IOV_VIOLATION_LOG__VF_MASK                                                                  0x00200000L
1049 #define SDMA2_GPU_IOV_VIOLATION_LOG__VFID_MASK                                                                0x03C00000L
1050 //SDMA2_ULV_CNTL
1051 #define SDMA2_ULV_CNTL__HYSTERESIS__SHIFT                                                                     0x0
1052 #define SDMA2_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT                                                              0x1b
1053 #define SDMA2_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT                                                               0x1c
1054 #define SDMA2_ULV_CNTL__ENTER_ULV_INT__SHIFT                                                                  0x1d
1055 #define SDMA2_ULV_CNTL__EXIT_ULV_INT__SHIFT                                                                   0x1e
1056 #define SDMA2_ULV_CNTL__ULV_STATUS__SHIFT                                                                     0x1f
1057 #define SDMA2_ULV_CNTL__HYSTERESIS_MASK                                                                       0x0000001FL
1058 #define SDMA2_ULV_CNTL__ENTER_ULV_INT_CLR_MASK                                                                0x08000000L
1059 #define SDMA2_ULV_CNTL__EXIT_ULV_INT_CLR_MASK                                                                 0x10000000L
1060 #define SDMA2_ULV_CNTL__ENTER_ULV_INT_MASK                                                                    0x20000000L
1061 #define SDMA2_ULV_CNTL__EXIT_ULV_INT_MASK                                                                     0x40000000L
1062 #define SDMA2_ULV_CNTL__ULV_STATUS_MASK                                                                       0x80000000L
1063 //SDMA2_EA_DBIT_ADDR_DATA
1064 #define SDMA2_EA_DBIT_ADDR_DATA__VALUE__SHIFT                                                                 0x0
1065 #define SDMA2_EA_DBIT_ADDR_DATA__VALUE_MASK                                                                   0xFFFFFFFFL
1066 //SDMA2_EA_DBIT_ADDR_INDEX
1067 #define SDMA2_EA_DBIT_ADDR_INDEX__VALUE__SHIFT                                                                0x0
1068 #define SDMA2_EA_DBIT_ADDR_INDEX__VALUE_MASK                                                                  0x00000007L
1069 //SDMA2_GPU_IOV_VIOLATION_LOG2
1070 #define SDMA2_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT                                                     0x0
1071 #define SDMA2_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK                                                       0x000000FFL
1072 //SDMA2_GFX_RB_CNTL
1073 #define SDMA2_GFX_RB_CNTL__RB_ENABLE__SHIFT                                                                   0x0
1074 #define SDMA2_GFX_RB_CNTL__RB_SIZE__SHIFT                                                                     0x1
1075 #define SDMA2_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                              0x9
1076 #define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                       0xc
1077 #define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                  0xd
1078 #define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                        0x10
1079 #define SDMA2_GFX_RB_CNTL__RB_PRIV__SHIFT                                                                     0x17
1080 #define SDMA2_GFX_RB_CNTL__RB_VMID__SHIFT                                                                     0x18
1081 #define SDMA2_GFX_RB_CNTL__RB_ENABLE_MASK                                                                     0x00000001L
1082 #define SDMA2_GFX_RB_CNTL__RB_SIZE_MASK                                                                       0x0000003EL
1083 #define SDMA2_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK                                                                0x00000200L
1084 #define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                         0x00001000L
1085 #define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                    0x00002000L
1086 #define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                          0x001F0000L
1087 #define SDMA2_GFX_RB_CNTL__RB_PRIV_MASK                                                                       0x00800000L
1088 #define SDMA2_GFX_RB_CNTL__RB_VMID_MASK                                                                       0x0F000000L
1089 //SDMA2_GFX_RB_BASE
1090 #define SDMA2_GFX_RB_BASE__ADDR__SHIFT                                                                        0x0
1091 #define SDMA2_GFX_RB_BASE__ADDR_MASK                                                                          0xFFFFFFFFL
1092 //SDMA2_GFX_RB_BASE_HI
1093 #define SDMA2_GFX_RB_BASE_HI__ADDR__SHIFT                                                                     0x0
1094 #define SDMA2_GFX_RB_BASE_HI__ADDR_MASK                                                                       0x00FFFFFFL
1095 //SDMA2_GFX_RB_RPTR
1096 #define SDMA2_GFX_RB_RPTR__OFFSET__SHIFT                                                                      0x0
1097 #define SDMA2_GFX_RB_RPTR__OFFSET_MASK                                                                        0xFFFFFFFFL
1098 //SDMA2_GFX_RB_RPTR_HI
1099 #define SDMA2_GFX_RB_RPTR_HI__OFFSET__SHIFT                                                                   0x0
1100 #define SDMA2_GFX_RB_RPTR_HI__OFFSET_MASK                                                                     0xFFFFFFFFL
1101 //SDMA2_GFX_RB_WPTR
1102 #define SDMA2_GFX_RB_WPTR__OFFSET__SHIFT                                                                      0x0
1103 #define SDMA2_GFX_RB_WPTR__OFFSET_MASK                                                                        0xFFFFFFFFL
1104 //SDMA2_GFX_RB_WPTR_HI
1105 #define SDMA2_GFX_RB_WPTR_HI__OFFSET__SHIFT                                                                   0x0
1106 #define SDMA2_GFX_RB_WPTR_HI__OFFSET_MASK                                                                     0xFFFFFFFFL
1107 //SDMA2_GFX_RB_WPTR_POLL_CNTL
1108 #define SDMA2_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                            0x0
1109 #define SDMA2_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                       0x1
1110 #define SDMA2_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                   0x2
1111 #define SDMA2_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                         0x4
1112 #define SDMA2_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                   0x10
1113 #define SDMA2_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                              0x00000001L
1114 #define SDMA2_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                         0x00000002L
1115 #define SDMA2_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                     0x00000004L
1116 #define SDMA2_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                           0x0000FFF0L
1117 #define SDMA2_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                     0xFFFF0000L
1118 //SDMA2_GFX_RB_RPTR_ADDR_HI
1119 #define SDMA2_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                                0x0
1120 #define SDMA2_GFX_RB_RPTR_ADDR_HI__ADDR_MASK                                                                  0xFFFFFFFFL
1121 //SDMA2_GFX_RB_RPTR_ADDR_LO
1122 #define SDMA2_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                        0x0
1123 #define SDMA2_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                                0x2
1124 #define SDMA2_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                          0x00000001L
1125 #define SDMA2_GFX_RB_RPTR_ADDR_LO__ADDR_MASK                                                                  0xFFFFFFFCL
1126 //SDMA2_GFX_IB_CNTL
1127 #define SDMA2_GFX_IB_CNTL__IB_ENABLE__SHIFT                                                                   0x0
1128 #define SDMA2_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                              0x4
1129 #define SDMA2_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                            0x8
1130 #define SDMA2_GFX_IB_CNTL__CMD_VMID__SHIFT                                                                    0x10
1131 #define SDMA2_GFX_IB_CNTL__IB_ENABLE_MASK                                                                     0x00000001L
1132 #define SDMA2_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK                                                                0x00000010L
1133 #define SDMA2_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                              0x00000100L
1134 #define SDMA2_GFX_IB_CNTL__CMD_VMID_MASK                                                                      0x000F0000L
1135 //SDMA2_GFX_IB_RPTR
1136 #define SDMA2_GFX_IB_RPTR__OFFSET__SHIFT                                                                      0x2
1137 #define SDMA2_GFX_IB_RPTR__OFFSET_MASK                                                                        0x003FFFFCL
1138 //SDMA2_GFX_IB_OFFSET
1139 #define SDMA2_GFX_IB_OFFSET__OFFSET__SHIFT                                                                    0x2
1140 #define SDMA2_GFX_IB_OFFSET__OFFSET_MASK                                                                      0x003FFFFCL
1141 //SDMA2_GFX_IB_BASE_LO
1142 #define SDMA2_GFX_IB_BASE_LO__ADDR__SHIFT                                                                     0x5
1143 #define SDMA2_GFX_IB_BASE_LO__ADDR_MASK                                                                       0xFFFFFFE0L
1144 //SDMA2_GFX_IB_BASE_HI
1145 #define SDMA2_GFX_IB_BASE_HI__ADDR__SHIFT                                                                     0x0
1146 #define SDMA2_GFX_IB_BASE_HI__ADDR_MASK                                                                       0xFFFFFFFFL
1147 //SDMA2_GFX_IB_SIZE
1148 #define SDMA2_GFX_IB_SIZE__SIZE__SHIFT                                                                        0x0
1149 #define SDMA2_GFX_IB_SIZE__SIZE_MASK                                                                          0x000FFFFFL
1150 //SDMA2_GFX_SKIP_CNTL
1151 #define SDMA2_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT                                                                0x0
1152 #define SDMA2_GFX_SKIP_CNTL__SKIP_COUNT_MASK                                                                  0x000FFFFFL
1153 //SDMA2_GFX_CONTEXT_STATUS
1154 #define SDMA2_GFX_CONTEXT_STATUS__SELECTED__SHIFT                                                             0x0
1155 #define SDMA2_GFX_CONTEXT_STATUS__IDLE__SHIFT                                                                 0x2
1156 #define SDMA2_GFX_CONTEXT_STATUS__EXPIRED__SHIFT                                                              0x3
1157 #define SDMA2_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT                                                            0x4
1158 #define SDMA2_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                           0x7
1159 #define SDMA2_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                          0x8
1160 #define SDMA2_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT                                                            0x9
1161 #define SDMA2_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                      0xa
1162 #define SDMA2_GFX_CONTEXT_STATUS__SELECTED_MASK                                                               0x00000001L
1163 #define SDMA2_GFX_CONTEXT_STATUS__IDLE_MASK                                                                   0x00000004L
1164 #define SDMA2_GFX_CONTEXT_STATUS__EXPIRED_MASK                                                                0x00000008L
1165 #define SDMA2_GFX_CONTEXT_STATUS__EXCEPTION_MASK                                                              0x00000070L
1166 #define SDMA2_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                             0x00000080L
1167 #define SDMA2_GFX_CONTEXT_STATUS__CTXSW_READY_MASK                                                            0x00000100L
1168 #define SDMA2_GFX_CONTEXT_STATUS__PREEMPTED_MASK                                                              0x00000200L
1169 #define SDMA2_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                        0x00000400L
1170 //SDMA2_GFX_DOORBELL
1171 #define SDMA2_GFX_DOORBELL__ENABLE__SHIFT                                                                     0x1c
1172 #define SDMA2_GFX_DOORBELL__CAPTURED__SHIFT                                                                   0x1e
1173 #define SDMA2_GFX_DOORBELL__ENABLE_MASK                                                                       0x10000000L
1174 #define SDMA2_GFX_DOORBELL__CAPTURED_MASK                                                                     0x40000000L
1175 //SDMA2_GFX_CONTEXT_CNTL
1176 #define SDMA2_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT                                                             0x10
1177 #define SDMA2_GFX_CONTEXT_CNTL__RESUME_CTX_MASK                                                               0x00010000L
1178 //SDMA2_GFX_STATUS
1179 #define SDMA2_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                       0x0
1180 #define SDMA2_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                          0x8
1181 #define SDMA2_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                         0x000000FFL
1182 #define SDMA2_GFX_STATUS__WPTR_UPDATE_PENDING_MASK                                                            0x00000100L
1183 //SDMA2_GFX_DOORBELL_LOG
1184 #define SDMA2_GFX_DOORBELL_LOG__BE_ERROR__SHIFT                                                               0x0
1185 #define SDMA2_GFX_DOORBELL_LOG__DATA__SHIFT                                                                   0x2
1186 #define SDMA2_GFX_DOORBELL_LOG__BE_ERROR_MASK                                                                 0x00000001L
1187 #define SDMA2_GFX_DOORBELL_LOG__DATA_MASK                                                                     0xFFFFFFFCL
1188 //SDMA2_GFX_WATERMARK
1189 #define SDMA2_GFX_WATERMARK__RD_OUTSTANDING__SHIFT                                                            0x0
1190 #define SDMA2_GFX_WATERMARK__WR_OUTSTANDING__SHIFT                                                            0x10
1191 #define SDMA2_GFX_WATERMARK__RD_OUTSTANDING_MASK                                                              0x00000FFFL
1192 #define SDMA2_GFX_WATERMARK__WR_OUTSTANDING_MASK                                                              0x03FF0000L
1193 //SDMA2_GFX_DOORBELL_OFFSET
1194 #define SDMA2_GFX_DOORBELL_OFFSET__OFFSET__SHIFT                                                              0x2
1195 #define SDMA2_GFX_DOORBELL_OFFSET__OFFSET_MASK                                                                0x0FFFFFFCL
1196 //SDMA2_GFX_CSA_ADDR_LO
1197 #define SDMA2_GFX_CSA_ADDR_LO__ADDR__SHIFT                                                                    0x2
1198 #define SDMA2_GFX_CSA_ADDR_LO__ADDR_MASK                                                                      0xFFFFFFFCL
1199 //SDMA2_GFX_CSA_ADDR_HI
1200 #define SDMA2_GFX_CSA_ADDR_HI__ADDR__SHIFT                                                                    0x0
1201 #define SDMA2_GFX_CSA_ADDR_HI__ADDR_MASK                                                                      0xFFFFFFFFL
1202 //SDMA2_GFX_IB_SUB_REMAIN
1203 #define SDMA2_GFX_IB_SUB_REMAIN__SIZE__SHIFT                                                                  0x0
1204 #define SDMA2_GFX_IB_SUB_REMAIN__SIZE_MASK                                                                    0x000FFFFFL
1205 //SDMA2_GFX_PREEMPT
1206 #define SDMA2_GFX_PREEMPT__IB_PREEMPT__SHIFT                                                                  0x0
1207 #define SDMA2_GFX_PREEMPT__IB_PREEMPT_MASK                                                                    0x00000001L
1208 //SDMA2_GFX_DUMMY_REG
1209 #define SDMA2_GFX_DUMMY_REG__DUMMY__SHIFT                                                                     0x0
1210 #define SDMA2_GFX_DUMMY_REG__DUMMY_MASK                                                                       0xFFFFFFFFL
1211 //SDMA2_GFX_RB_WPTR_POLL_ADDR_HI
1212 #define SDMA2_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                           0x0
1213 #define SDMA2_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                             0xFFFFFFFFL
1214 //SDMA2_GFX_RB_WPTR_POLL_ADDR_LO
1215 #define SDMA2_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                           0x2
1216 #define SDMA2_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                             0xFFFFFFFCL
1217 //SDMA2_GFX_RB_AQL_CNTL
1218 #define SDMA2_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                              0x0
1219 #define SDMA2_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                         0x1
1220 #define SDMA2_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                             0x8
1221 #define SDMA2_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK                                                                0x00000001L
1222 #define SDMA2_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                           0x000000FEL
1223 #define SDMA2_GFX_RB_AQL_CNTL__PACKET_STEP_MASK                                                               0x0000FF00L
1224 //SDMA2_GFX_MINOR_PTR_UPDATE
1225 #define SDMA2_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                             0x0
1226 #define SDMA2_GFX_MINOR_PTR_UPDATE__ENABLE_MASK                                                               0x00000001L
1227 //SDMA2_GFX_MIDCMD_DATA0
1228 #define SDMA2_GFX_MIDCMD_DATA0__DATA0__SHIFT                                                                  0x0
1229 #define SDMA2_GFX_MIDCMD_DATA0__DATA0_MASK                                                                    0xFFFFFFFFL
1230 //SDMA2_GFX_MIDCMD_DATA1
1231 #define SDMA2_GFX_MIDCMD_DATA1__DATA1__SHIFT                                                                  0x0
1232 #define SDMA2_GFX_MIDCMD_DATA1__DATA1_MASK                                                                    0xFFFFFFFFL
1233 //SDMA2_GFX_MIDCMD_DATA2
1234 #define SDMA2_GFX_MIDCMD_DATA2__DATA2__SHIFT                                                                  0x0
1235 #define SDMA2_GFX_MIDCMD_DATA2__DATA2_MASK                                                                    0xFFFFFFFFL
1236 //SDMA2_GFX_MIDCMD_DATA3
1237 #define SDMA2_GFX_MIDCMD_DATA3__DATA3__SHIFT                                                                  0x0
1238 #define SDMA2_GFX_MIDCMD_DATA3__DATA3_MASK                                                                    0xFFFFFFFFL
1239 //SDMA2_GFX_MIDCMD_DATA4
1240 #define SDMA2_GFX_MIDCMD_DATA4__DATA4__SHIFT                                                                  0x0
1241 #define SDMA2_GFX_MIDCMD_DATA4__DATA4_MASK                                                                    0xFFFFFFFFL
1242 //SDMA2_GFX_MIDCMD_DATA5
1243 #define SDMA2_GFX_MIDCMD_DATA5__DATA5__SHIFT                                                                  0x0
1244 #define SDMA2_GFX_MIDCMD_DATA5__DATA5_MASK                                                                    0xFFFFFFFFL
1245 //SDMA2_GFX_MIDCMD_DATA6
1246 #define SDMA2_GFX_MIDCMD_DATA6__DATA6__SHIFT                                                                  0x0
1247 #define SDMA2_GFX_MIDCMD_DATA6__DATA6_MASK                                                                    0xFFFFFFFFL
1248 //SDMA2_GFX_MIDCMD_DATA7
1249 #define SDMA2_GFX_MIDCMD_DATA7__DATA7__SHIFT                                                                  0x0
1250 #define SDMA2_GFX_MIDCMD_DATA7__DATA7_MASK                                                                    0xFFFFFFFFL
1251 //SDMA2_GFX_MIDCMD_DATA8
1252 #define SDMA2_GFX_MIDCMD_DATA8__DATA8__SHIFT                                                                  0x0
1253 #define SDMA2_GFX_MIDCMD_DATA8__DATA8_MASK                                                                    0xFFFFFFFFL
1254 //SDMA2_GFX_MIDCMD_CNTL
1255 #define SDMA2_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT                                                              0x0
1256 #define SDMA2_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT                                                               0x1
1257 #define SDMA2_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                             0x4
1258 #define SDMA2_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                           0x8
1259 #define SDMA2_GFX_MIDCMD_CNTL__DATA_VALID_MASK                                                                0x00000001L
1260 #define SDMA2_GFX_MIDCMD_CNTL__COPY_MODE_MASK                                                                 0x00000002L
1261 #define SDMA2_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK                                                               0x000000F0L
1262 #define SDMA2_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                             0x00000100L
1263 //SDMA2_PAGE_RB_CNTL
1264 #define SDMA2_PAGE_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
1265 #define SDMA2_PAGE_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
1266 #define SDMA2_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
1267 #define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
1268 #define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
1269 #define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
1270 #define SDMA2_PAGE_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
1271 #define SDMA2_PAGE_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
1272 #define SDMA2_PAGE_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
1273 #define SDMA2_PAGE_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
1274 #define SDMA2_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
1275 #define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
1276 #define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
1277 #define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
1278 #define SDMA2_PAGE_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
1279 #define SDMA2_PAGE_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
1280 //SDMA2_PAGE_RB_BASE
1281 #define SDMA2_PAGE_RB_BASE__ADDR__SHIFT                                                                       0x0
1282 #define SDMA2_PAGE_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
1283 //SDMA2_PAGE_RB_BASE_HI
1284 #define SDMA2_PAGE_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
1285 #define SDMA2_PAGE_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
1286 //SDMA2_PAGE_RB_RPTR
1287 #define SDMA2_PAGE_RB_RPTR__OFFSET__SHIFT                                                                     0x0
1288 #define SDMA2_PAGE_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
1289 //SDMA2_PAGE_RB_RPTR_HI
1290 #define SDMA2_PAGE_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
1291 #define SDMA2_PAGE_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
1292 //SDMA2_PAGE_RB_WPTR
1293 #define SDMA2_PAGE_RB_WPTR__OFFSET__SHIFT                                                                     0x0
1294 #define SDMA2_PAGE_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
1295 //SDMA2_PAGE_RB_WPTR_HI
1296 #define SDMA2_PAGE_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
1297 #define SDMA2_PAGE_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
1298 //SDMA2_PAGE_RB_WPTR_POLL_CNTL
1299 #define SDMA2_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
1300 #define SDMA2_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
1301 #define SDMA2_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
1302 #define SDMA2_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
1303 #define SDMA2_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
1304 #define SDMA2_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
1305 #define SDMA2_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
1306 #define SDMA2_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
1307 #define SDMA2_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
1308 #define SDMA2_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
1309 //SDMA2_PAGE_RB_RPTR_ADDR_HI
1310 #define SDMA2_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
1311 #define SDMA2_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
1312 //SDMA2_PAGE_RB_RPTR_ADDR_LO
1313 #define SDMA2_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
1314 #define SDMA2_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
1315 #define SDMA2_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
1316 #define SDMA2_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
1317 //SDMA2_PAGE_IB_CNTL
1318 #define SDMA2_PAGE_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
1319 #define SDMA2_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
1320 #define SDMA2_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
1321 #define SDMA2_PAGE_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
1322 #define SDMA2_PAGE_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
1323 #define SDMA2_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
1324 #define SDMA2_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
1325 #define SDMA2_PAGE_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
1326 //SDMA2_PAGE_IB_RPTR
1327 #define SDMA2_PAGE_IB_RPTR__OFFSET__SHIFT                                                                     0x2
1328 #define SDMA2_PAGE_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
1329 //SDMA2_PAGE_IB_OFFSET
1330 #define SDMA2_PAGE_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
1331 #define SDMA2_PAGE_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
1332 //SDMA2_PAGE_IB_BASE_LO
1333 #define SDMA2_PAGE_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
1334 #define SDMA2_PAGE_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
1335 //SDMA2_PAGE_IB_BASE_HI
1336 #define SDMA2_PAGE_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
1337 #define SDMA2_PAGE_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
1338 //SDMA2_PAGE_IB_SIZE
1339 #define SDMA2_PAGE_IB_SIZE__SIZE__SHIFT                                                                       0x0
1340 #define SDMA2_PAGE_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
1341 //SDMA2_PAGE_SKIP_CNTL
1342 #define SDMA2_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
1343 #define SDMA2_PAGE_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
1344 //SDMA2_PAGE_CONTEXT_STATUS
1345 #define SDMA2_PAGE_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
1346 #define SDMA2_PAGE_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
1347 #define SDMA2_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
1348 #define SDMA2_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
1349 #define SDMA2_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
1350 #define SDMA2_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
1351 #define SDMA2_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
1352 #define SDMA2_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
1353 #define SDMA2_PAGE_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
1354 #define SDMA2_PAGE_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
1355 #define SDMA2_PAGE_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
1356 #define SDMA2_PAGE_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
1357 #define SDMA2_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
1358 #define SDMA2_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
1359 #define SDMA2_PAGE_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
1360 #define SDMA2_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
1361 //SDMA2_PAGE_DOORBELL
1362 #define SDMA2_PAGE_DOORBELL__ENABLE__SHIFT                                                                    0x1c
1363 #define SDMA2_PAGE_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
1364 #define SDMA2_PAGE_DOORBELL__ENABLE_MASK                                                                      0x10000000L
1365 #define SDMA2_PAGE_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
1366 //SDMA2_PAGE_STATUS
1367 #define SDMA2_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
1368 #define SDMA2_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
1369 #define SDMA2_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
1370 #define SDMA2_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
1371 //SDMA2_PAGE_DOORBELL_LOG
1372 #define SDMA2_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
1373 #define SDMA2_PAGE_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
1374 #define SDMA2_PAGE_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
1375 #define SDMA2_PAGE_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
1376 //SDMA2_PAGE_WATERMARK
1377 #define SDMA2_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
1378 #define SDMA2_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
1379 #define SDMA2_PAGE_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
1380 #define SDMA2_PAGE_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
1381 //SDMA2_PAGE_DOORBELL_OFFSET
1382 #define SDMA2_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
1383 #define SDMA2_PAGE_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
1384 //SDMA2_PAGE_CSA_ADDR_LO
1385 #define SDMA2_PAGE_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
1386 #define SDMA2_PAGE_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
1387 //SDMA2_PAGE_CSA_ADDR_HI
1388 #define SDMA2_PAGE_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
1389 #define SDMA2_PAGE_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
1390 //SDMA2_PAGE_IB_SUB_REMAIN
1391 #define SDMA2_PAGE_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
1392 #define SDMA2_PAGE_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
1393 //SDMA2_PAGE_PREEMPT
1394 #define SDMA2_PAGE_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
1395 #define SDMA2_PAGE_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
1396 //SDMA2_PAGE_DUMMY_REG
1397 #define SDMA2_PAGE_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
1398 #define SDMA2_PAGE_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
1399 //SDMA2_PAGE_RB_WPTR_POLL_ADDR_HI
1400 #define SDMA2_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
1401 #define SDMA2_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
1402 //SDMA2_PAGE_RB_WPTR_POLL_ADDR_LO
1403 #define SDMA2_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
1404 #define SDMA2_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
1405 //SDMA2_PAGE_RB_AQL_CNTL
1406 #define SDMA2_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
1407 #define SDMA2_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
1408 #define SDMA2_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
1409 #define SDMA2_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
1410 #define SDMA2_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
1411 #define SDMA2_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
1412 //SDMA2_PAGE_MINOR_PTR_UPDATE
1413 #define SDMA2_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
1414 #define SDMA2_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
1415 //SDMA2_PAGE_MIDCMD_DATA0
1416 #define SDMA2_PAGE_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
1417 #define SDMA2_PAGE_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
1418 //SDMA2_PAGE_MIDCMD_DATA1
1419 #define SDMA2_PAGE_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
1420 #define SDMA2_PAGE_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
1421 //SDMA2_PAGE_MIDCMD_DATA2
1422 #define SDMA2_PAGE_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
1423 #define SDMA2_PAGE_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
1424 //SDMA2_PAGE_MIDCMD_DATA3
1425 #define SDMA2_PAGE_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
1426 #define SDMA2_PAGE_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
1427 //SDMA2_PAGE_MIDCMD_DATA4
1428 #define SDMA2_PAGE_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
1429 #define SDMA2_PAGE_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
1430 //SDMA2_PAGE_MIDCMD_DATA5
1431 #define SDMA2_PAGE_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
1432 #define SDMA2_PAGE_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
1433 //SDMA2_PAGE_MIDCMD_DATA6
1434 #define SDMA2_PAGE_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
1435 #define SDMA2_PAGE_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
1436 //SDMA2_PAGE_MIDCMD_DATA7
1437 #define SDMA2_PAGE_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
1438 #define SDMA2_PAGE_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
1439 //SDMA2_PAGE_MIDCMD_DATA8
1440 #define SDMA2_PAGE_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
1441 #define SDMA2_PAGE_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
1442 //SDMA2_PAGE_MIDCMD_CNTL
1443 #define SDMA2_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
1444 #define SDMA2_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
1445 #define SDMA2_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
1446 #define SDMA2_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
1447 #define SDMA2_PAGE_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
1448 #define SDMA2_PAGE_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
1449 #define SDMA2_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
1450 #define SDMA2_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
1451 //SDMA2_RLC0_RB_CNTL
1452 #define SDMA2_RLC0_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
1453 #define SDMA2_RLC0_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
1454 #define SDMA2_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
1455 #define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
1456 #define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
1457 #define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
1458 #define SDMA2_RLC0_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
1459 #define SDMA2_RLC0_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
1460 #define SDMA2_RLC0_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
1461 #define SDMA2_RLC0_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
1462 #define SDMA2_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
1463 #define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
1464 #define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
1465 #define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
1466 #define SDMA2_RLC0_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
1467 #define SDMA2_RLC0_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
1468 //SDMA2_RLC0_RB_BASE
1469 #define SDMA2_RLC0_RB_BASE__ADDR__SHIFT                                                                       0x0
1470 #define SDMA2_RLC0_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
1471 //SDMA2_RLC0_RB_BASE_HI
1472 #define SDMA2_RLC0_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
1473 #define SDMA2_RLC0_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
1474 //SDMA2_RLC0_RB_RPTR
1475 #define SDMA2_RLC0_RB_RPTR__OFFSET__SHIFT                                                                     0x0
1476 #define SDMA2_RLC0_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
1477 //SDMA2_RLC0_RB_RPTR_HI
1478 #define SDMA2_RLC0_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
1479 #define SDMA2_RLC0_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
1480 //SDMA2_RLC0_RB_WPTR
1481 #define SDMA2_RLC0_RB_WPTR__OFFSET__SHIFT                                                                     0x0
1482 #define SDMA2_RLC0_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
1483 //SDMA2_RLC0_RB_WPTR_HI
1484 #define SDMA2_RLC0_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
1485 #define SDMA2_RLC0_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
1486 //SDMA2_RLC0_RB_WPTR_POLL_CNTL
1487 #define SDMA2_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
1488 #define SDMA2_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
1489 #define SDMA2_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
1490 #define SDMA2_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
1491 #define SDMA2_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
1492 #define SDMA2_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
1493 #define SDMA2_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
1494 #define SDMA2_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
1495 #define SDMA2_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
1496 #define SDMA2_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
1497 //SDMA2_RLC0_RB_RPTR_ADDR_HI
1498 #define SDMA2_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
1499 #define SDMA2_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
1500 //SDMA2_RLC0_RB_RPTR_ADDR_LO
1501 #define SDMA2_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
1502 #define SDMA2_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
1503 #define SDMA2_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
1504 #define SDMA2_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
1505 //SDMA2_RLC0_IB_CNTL
1506 #define SDMA2_RLC0_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
1507 #define SDMA2_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
1508 #define SDMA2_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
1509 #define SDMA2_RLC0_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
1510 #define SDMA2_RLC0_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
1511 #define SDMA2_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
1512 #define SDMA2_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
1513 #define SDMA2_RLC0_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
1514 //SDMA2_RLC0_IB_RPTR
1515 #define SDMA2_RLC0_IB_RPTR__OFFSET__SHIFT                                                                     0x2
1516 #define SDMA2_RLC0_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
1517 //SDMA2_RLC0_IB_OFFSET
1518 #define SDMA2_RLC0_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
1519 #define SDMA2_RLC0_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
1520 //SDMA2_RLC0_IB_BASE_LO
1521 #define SDMA2_RLC0_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
1522 #define SDMA2_RLC0_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
1523 //SDMA2_RLC0_IB_BASE_HI
1524 #define SDMA2_RLC0_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
1525 #define SDMA2_RLC0_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
1526 //SDMA2_RLC0_IB_SIZE
1527 #define SDMA2_RLC0_IB_SIZE__SIZE__SHIFT                                                                       0x0
1528 #define SDMA2_RLC0_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
1529 //SDMA2_RLC0_SKIP_CNTL
1530 #define SDMA2_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
1531 #define SDMA2_RLC0_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
1532 //SDMA2_RLC0_CONTEXT_STATUS
1533 #define SDMA2_RLC0_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
1534 #define SDMA2_RLC0_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
1535 #define SDMA2_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
1536 #define SDMA2_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
1537 #define SDMA2_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
1538 #define SDMA2_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
1539 #define SDMA2_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
1540 #define SDMA2_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
1541 #define SDMA2_RLC0_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
1542 #define SDMA2_RLC0_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
1543 #define SDMA2_RLC0_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
1544 #define SDMA2_RLC0_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
1545 #define SDMA2_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
1546 #define SDMA2_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
1547 #define SDMA2_RLC0_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
1548 #define SDMA2_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
1549 //SDMA2_RLC0_DOORBELL
1550 #define SDMA2_RLC0_DOORBELL__ENABLE__SHIFT                                                                    0x1c
1551 #define SDMA2_RLC0_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
1552 #define SDMA2_RLC0_DOORBELL__ENABLE_MASK                                                                      0x10000000L
1553 #define SDMA2_RLC0_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
1554 //SDMA2_RLC0_STATUS
1555 #define SDMA2_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
1556 #define SDMA2_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
1557 #define SDMA2_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
1558 #define SDMA2_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
1559 //SDMA2_RLC0_DOORBELL_LOG
1560 #define SDMA2_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
1561 #define SDMA2_RLC0_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
1562 #define SDMA2_RLC0_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
1563 #define SDMA2_RLC0_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
1564 //SDMA2_RLC0_WATERMARK
1565 #define SDMA2_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
1566 #define SDMA2_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
1567 #define SDMA2_RLC0_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
1568 #define SDMA2_RLC0_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
1569 //SDMA2_RLC0_DOORBELL_OFFSET
1570 #define SDMA2_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
1571 #define SDMA2_RLC0_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
1572 //SDMA2_RLC0_CSA_ADDR_LO
1573 #define SDMA2_RLC0_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
1574 #define SDMA2_RLC0_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
1575 //SDMA2_RLC0_CSA_ADDR_HI
1576 #define SDMA2_RLC0_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
1577 #define SDMA2_RLC0_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
1578 //SDMA2_RLC0_IB_SUB_REMAIN
1579 #define SDMA2_RLC0_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
1580 #define SDMA2_RLC0_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
1581 //SDMA2_RLC0_PREEMPT
1582 #define SDMA2_RLC0_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
1583 #define SDMA2_RLC0_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
1584 //SDMA2_RLC0_DUMMY_REG
1585 #define SDMA2_RLC0_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
1586 #define SDMA2_RLC0_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
1587 //SDMA2_RLC0_RB_WPTR_POLL_ADDR_HI
1588 #define SDMA2_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
1589 #define SDMA2_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
1590 //SDMA2_RLC0_RB_WPTR_POLL_ADDR_LO
1591 #define SDMA2_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
1592 #define SDMA2_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
1593 //SDMA2_RLC0_RB_AQL_CNTL
1594 #define SDMA2_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
1595 #define SDMA2_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
1596 #define SDMA2_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
1597 #define SDMA2_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
1598 #define SDMA2_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
1599 #define SDMA2_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
1600 //SDMA2_RLC0_MINOR_PTR_UPDATE
1601 #define SDMA2_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
1602 #define SDMA2_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
1603 //SDMA2_RLC0_MIDCMD_DATA0
1604 #define SDMA2_RLC0_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
1605 #define SDMA2_RLC0_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
1606 //SDMA2_RLC0_MIDCMD_DATA1
1607 #define SDMA2_RLC0_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
1608 #define SDMA2_RLC0_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
1609 //SDMA2_RLC0_MIDCMD_DATA2
1610 #define SDMA2_RLC0_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
1611 #define SDMA2_RLC0_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
1612 //SDMA2_RLC0_MIDCMD_DATA3
1613 #define SDMA2_RLC0_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
1614 #define SDMA2_RLC0_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
1615 //SDMA2_RLC0_MIDCMD_DATA4
1616 #define SDMA2_RLC0_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
1617 #define SDMA2_RLC0_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
1618 //SDMA2_RLC0_MIDCMD_DATA5
1619 #define SDMA2_RLC0_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
1620 #define SDMA2_RLC0_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
1621 //SDMA2_RLC0_MIDCMD_DATA6
1622 #define SDMA2_RLC0_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
1623 #define SDMA2_RLC0_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
1624 //SDMA2_RLC0_MIDCMD_DATA7
1625 #define SDMA2_RLC0_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
1626 #define SDMA2_RLC0_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
1627 //SDMA2_RLC0_MIDCMD_DATA8
1628 #define SDMA2_RLC0_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
1629 #define SDMA2_RLC0_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
1630 //SDMA2_RLC0_MIDCMD_CNTL
1631 #define SDMA2_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
1632 #define SDMA2_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
1633 #define SDMA2_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
1634 #define SDMA2_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
1635 #define SDMA2_RLC0_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
1636 #define SDMA2_RLC0_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
1637 #define SDMA2_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
1638 #define SDMA2_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
1639 //SDMA2_RLC1_RB_CNTL
1640 #define SDMA2_RLC1_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
1641 #define SDMA2_RLC1_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
1642 #define SDMA2_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
1643 #define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
1644 #define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
1645 #define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
1646 #define SDMA2_RLC1_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
1647 #define SDMA2_RLC1_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
1648 #define SDMA2_RLC1_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
1649 #define SDMA2_RLC1_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
1650 #define SDMA2_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
1651 #define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
1652 #define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
1653 #define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
1654 #define SDMA2_RLC1_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
1655 #define SDMA2_RLC1_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
1656 //SDMA2_RLC1_RB_BASE
1657 #define SDMA2_RLC1_RB_BASE__ADDR__SHIFT                                                                       0x0
1658 #define SDMA2_RLC1_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
1659 //SDMA2_RLC1_RB_BASE_HI
1660 #define SDMA2_RLC1_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
1661 #define SDMA2_RLC1_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
1662 //SDMA2_RLC1_RB_RPTR
1663 #define SDMA2_RLC1_RB_RPTR__OFFSET__SHIFT                                                                     0x0
1664 #define SDMA2_RLC1_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
1665 //SDMA2_RLC1_RB_RPTR_HI
1666 #define SDMA2_RLC1_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
1667 #define SDMA2_RLC1_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
1668 //SDMA2_RLC1_RB_WPTR
1669 #define SDMA2_RLC1_RB_WPTR__OFFSET__SHIFT                                                                     0x0
1670 #define SDMA2_RLC1_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
1671 //SDMA2_RLC1_RB_WPTR_HI
1672 #define SDMA2_RLC1_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
1673 #define SDMA2_RLC1_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
1674 //SDMA2_RLC1_RB_WPTR_POLL_CNTL
1675 #define SDMA2_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
1676 #define SDMA2_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
1677 #define SDMA2_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
1678 #define SDMA2_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
1679 #define SDMA2_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
1680 #define SDMA2_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
1681 #define SDMA2_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
1682 #define SDMA2_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
1683 #define SDMA2_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
1684 #define SDMA2_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
1685 //SDMA2_RLC1_RB_RPTR_ADDR_HI
1686 #define SDMA2_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
1687 #define SDMA2_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
1688 //SDMA2_RLC1_RB_RPTR_ADDR_LO
1689 #define SDMA2_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
1690 #define SDMA2_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
1691 #define SDMA2_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
1692 #define SDMA2_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
1693 //SDMA2_RLC1_IB_CNTL
1694 #define SDMA2_RLC1_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
1695 #define SDMA2_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
1696 #define SDMA2_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
1697 #define SDMA2_RLC1_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
1698 #define SDMA2_RLC1_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
1699 #define SDMA2_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
1700 #define SDMA2_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
1701 #define SDMA2_RLC1_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
1702 //SDMA2_RLC1_IB_RPTR
1703 #define SDMA2_RLC1_IB_RPTR__OFFSET__SHIFT                                                                     0x2
1704 #define SDMA2_RLC1_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
1705 //SDMA2_RLC1_IB_OFFSET
1706 #define SDMA2_RLC1_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
1707 #define SDMA2_RLC1_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
1708 //SDMA2_RLC1_IB_BASE_LO
1709 #define SDMA2_RLC1_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
1710 #define SDMA2_RLC1_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
1711 //SDMA2_RLC1_IB_BASE_HI
1712 #define SDMA2_RLC1_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
1713 #define SDMA2_RLC1_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
1714 //SDMA2_RLC1_IB_SIZE
1715 #define SDMA2_RLC1_IB_SIZE__SIZE__SHIFT                                                                       0x0
1716 #define SDMA2_RLC1_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
1717 //SDMA2_RLC1_SKIP_CNTL
1718 #define SDMA2_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
1719 #define SDMA2_RLC1_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
1720 //SDMA2_RLC1_CONTEXT_STATUS
1721 #define SDMA2_RLC1_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
1722 #define SDMA2_RLC1_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
1723 #define SDMA2_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
1724 #define SDMA2_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
1725 #define SDMA2_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
1726 #define SDMA2_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
1727 #define SDMA2_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
1728 #define SDMA2_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
1729 #define SDMA2_RLC1_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
1730 #define SDMA2_RLC1_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
1731 #define SDMA2_RLC1_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
1732 #define SDMA2_RLC1_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
1733 #define SDMA2_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
1734 #define SDMA2_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
1735 #define SDMA2_RLC1_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
1736 #define SDMA2_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
1737 //SDMA2_RLC1_DOORBELL
1738 #define SDMA2_RLC1_DOORBELL__ENABLE__SHIFT                                                                    0x1c
1739 #define SDMA2_RLC1_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
1740 #define SDMA2_RLC1_DOORBELL__ENABLE_MASK                                                                      0x10000000L
1741 #define SDMA2_RLC1_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
1742 //SDMA2_RLC1_STATUS
1743 #define SDMA2_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
1744 #define SDMA2_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
1745 #define SDMA2_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
1746 #define SDMA2_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
1747 //SDMA2_RLC1_DOORBELL_LOG
1748 #define SDMA2_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
1749 #define SDMA2_RLC1_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
1750 #define SDMA2_RLC1_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
1751 #define SDMA2_RLC1_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
1752 //SDMA2_RLC1_WATERMARK
1753 #define SDMA2_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
1754 #define SDMA2_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
1755 #define SDMA2_RLC1_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
1756 #define SDMA2_RLC1_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
1757 //SDMA2_RLC1_DOORBELL_OFFSET
1758 #define SDMA2_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
1759 #define SDMA2_RLC1_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
1760 //SDMA2_RLC1_CSA_ADDR_LO
1761 #define SDMA2_RLC1_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
1762 #define SDMA2_RLC1_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
1763 //SDMA2_RLC1_CSA_ADDR_HI
1764 #define SDMA2_RLC1_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
1765 #define SDMA2_RLC1_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
1766 //SDMA2_RLC1_IB_SUB_REMAIN
1767 #define SDMA2_RLC1_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
1768 #define SDMA2_RLC1_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
1769 //SDMA2_RLC1_PREEMPT
1770 #define SDMA2_RLC1_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
1771 #define SDMA2_RLC1_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
1772 //SDMA2_RLC1_DUMMY_REG
1773 #define SDMA2_RLC1_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
1774 #define SDMA2_RLC1_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
1775 //SDMA2_RLC1_RB_WPTR_POLL_ADDR_HI
1776 #define SDMA2_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
1777 #define SDMA2_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
1778 //SDMA2_RLC1_RB_WPTR_POLL_ADDR_LO
1779 #define SDMA2_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
1780 #define SDMA2_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
1781 //SDMA2_RLC1_RB_AQL_CNTL
1782 #define SDMA2_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
1783 #define SDMA2_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
1784 #define SDMA2_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
1785 #define SDMA2_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
1786 #define SDMA2_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
1787 #define SDMA2_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
1788 //SDMA2_RLC1_MINOR_PTR_UPDATE
1789 #define SDMA2_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
1790 #define SDMA2_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
1791 //SDMA2_RLC1_MIDCMD_DATA0
1792 #define SDMA2_RLC1_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
1793 #define SDMA2_RLC1_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
1794 //SDMA2_RLC1_MIDCMD_DATA1
1795 #define SDMA2_RLC1_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
1796 #define SDMA2_RLC1_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
1797 //SDMA2_RLC1_MIDCMD_DATA2
1798 #define SDMA2_RLC1_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
1799 #define SDMA2_RLC1_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
1800 //SDMA2_RLC1_MIDCMD_DATA3
1801 #define SDMA2_RLC1_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
1802 #define SDMA2_RLC1_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
1803 //SDMA2_RLC1_MIDCMD_DATA4
1804 #define SDMA2_RLC1_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
1805 #define SDMA2_RLC1_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
1806 //SDMA2_RLC1_MIDCMD_DATA5
1807 #define SDMA2_RLC1_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
1808 #define SDMA2_RLC1_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
1809 //SDMA2_RLC1_MIDCMD_DATA6
1810 #define SDMA2_RLC1_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
1811 #define SDMA2_RLC1_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
1812 //SDMA2_RLC1_MIDCMD_DATA7
1813 #define SDMA2_RLC1_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
1814 #define SDMA2_RLC1_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
1815 //SDMA2_RLC1_MIDCMD_DATA8
1816 #define SDMA2_RLC1_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
1817 #define SDMA2_RLC1_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
1818 //SDMA2_RLC1_MIDCMD_CNTL
1819 #define SDMA2_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
1820 #define SDMA2_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
1821 #define SDMA2_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
1822 #define SDMA2_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
1823 #define SDMA2_RLC1_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
1824 #define SDMA2_RLC1_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
1825 #define SDMA2_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
1826 #define SDMA2_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
1827 //SDMA2_RLC2_RB_CNTL
1828 #define SDMA2_RLC2_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
1829 #define SDMA2_RLC2_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
1830 #define SDMA2_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
1831 #define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
1832 #define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
1833 #define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
1834 #define SDMA2_RLC2_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
1835 #define SDMA2_RLC2_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
1836 #define SDMA2_RLC2_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
1837 #define SDMA2_RLC2_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
1838 #define SDMA2_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
1839 #define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
1840 #define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
1841 #define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
1842 #define SDMA2_RLC2_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
1843 #define SDMA2_RLC2_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
1844 //SDMA2_RLC2_RB_BASE
1845 #define SDMA2_RLC2_RB_BASE__ADDR__SHIFT                                                                       0x0
1846 #define SDMA2_RLC2_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
1847 //SDMA2_RLC2_RB_BASE_HI
1848 #define SDMA2_RLC2_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
1849 #define SDMA2_RLC2_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
1850 //SDMA2_RLC2_RB_RPTR
1851 #define SDMA2_RLC2_RB_RPTR__OFFSET__SHIFT                                                                     0x0
1852 #define SDMA2_RLC2_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
1853 //SDMA2_RLC2_RB_RPTR_HI
1854 #define SDMA2_RLC2_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
1855 #define SDMA2_RLC2_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
1856 //SDMA2_RLC2_RB_WPTR
1857 #define SDMA2_RLC2_RB_WPTR__OFFSET__SHIFT                                                                     0x0
1858 #define SDMA2_RLC2_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
1859 //SDMA2_RLC2_RB_WPTR_HI
1860 #define SDMA2_RLC2_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
1861 #define SDMA2_RLC2_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
1862 //SDMA2_RLC2_RB_WPTR_POLL_CNTL
1863 #define SDMA2_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
1864 #define SDMA2_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
1865 #define SDMA2_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
1866 #define SDMA2_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
1867 #define SDMA2_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
1868 #define SDMA2_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
1869 #define SDMA2_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
1870 #define SDMA2_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
1871 #define SDMA2_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
1872 #define SDMA2_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
1873 //SDMA2_RLC2_RB_RPTR_ADDR_HI
1874 #define SDMA2_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
1875 #define SDMA2_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
1876 //SDMA2_RLC2_RB_RPTR_ADDR_LO
1877 #define SDMA2_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
1878 #define SDMA2_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
1879 #define SDMA2_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
1880 #define SDMA2_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
1881 //SDMA2_RLC2_IB_CNTL
1882 #define SDMA2_RLC2_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
1883 #define SDMA2_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
1884 #define SDMA2_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
1885 #define SDMA2_RLC2_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
1886 #define SDMA2_RLC2_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
1887 #define SDMA2_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
1888 #define SDMA2_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
1889 #define SDMA2_RLC2_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
1890 //SDMA2_RLC2_IB_RPTR
1891 #define SDMA2_RLC2_IB_RPTR__OFFSET__SHIFT                                                                     0x2
1892 #define SDMA2_RLC2_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
1893 //SDMA2_RLC2_IB_OFFSET
1894 #define SDMA2_RLC2_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
1895 #define SDMA2_RLC2_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
1896 //SDMA2_RLC2_IB_BASE_LO
1897 #define SDMA2_RLC2_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
1898 #define SDMA2_RLC2_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
1899 //SDMA2_RLC2_IB_BASE_HI
1900 #define SDMA2_RLC2_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
1901 #define SDMA2_RLC2_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
1902 //SDMA2_RLC2_IB_SIZE
1903 #define SDMA2_RLC2_IB_SIZE__SIZE__SHIFT                                                                       0x0
1904 #define SDMA2_RLC2_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
1905 //SDMA2_RLC2_SKIP_CNTL
1906 #define SDMA2_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
1907 #define SDMA2_RLC2_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
1908 //SDMA2_RLC2_CONTEXT_STATUS
1909 #define SDMA2_RLC2_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
1910 #define SDMA2_RLC2_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
1911 #define SDMA2_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
1912 #define SDMA2_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
1913 #define SDMA2_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
1914 #define SDMA2_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
1915 #define SDMA2_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
1916 #define SDMA2_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
1917 #define SDMA2_RLC2_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
1918 #define SDMA2_RLC2_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
1919 #define SDMA2_RLC2_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
1920 #define SDMA2_RLC2_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
1921 #define SDMA2_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
1922 #define SDMA2_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
1923 #define SDMA2_RLC2_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
1924 #define SDMA2_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
1925 //SDMA2_RLC2_DOORBELL
1926 #define SDMA2_RLC2_DOORBELL__ENABLE__SHIFT                                                                    0x1c
1927 #define SDMA2_RLC2_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
1928 #define SDMA2_RLC2_DOORBELL__ENABLE_MASK                                                                      0x10000000L
1929 #define SDMA2_RLC2_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
1930 //SDMA2_RLC2_STATUS
1931 #define SDMA2_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
1932 #define SDMA2_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
1933 #define SDMA2_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
1934 #define SDMA2_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
1935 //SDMA2_RLC2_DOORBELL_LOG
1936 #define SDMA2_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
1937 #define SDMA2_RLC2_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
1938 #define SDMA2_RLC2_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
1939 #define SDMA2_RLC2_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
1940 //SDMA2_RLC2_WATERMARK
1941 #define SDMA2_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
1942 #define SDMA2_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
1943 #define SDMA2_RLC2_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
1944 #define SDMA2_RLC2_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
1945 //SDMA2_RLC2_DOORBELL_OFFSET
1946 #define SDMA2_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
1947 #define SDMA2_RLC2_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
1948 //SDMA2_RLC2_CSA_ADDR_LO
1949 #define SDMA2_RLC2_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
1950 #define SDMA2_RLC2_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
1951 //SDMA2_RLC2_CSA_ADDR_HI
1952 #define SDMA2_RLC2_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
1953 #define SDMA2_RLC2_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
1954 //SDMA2_RLC2_IB_SUB_REMAIN
1955 #define SDMA2_RLC2_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
1956 #define SDMA2_RLC2_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
1957 //SDMA2_RLC2_PREEMPT
1958 #define SDMA2_RLC2_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
1959 #define SDMA2_RLC2_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
1960 //SDMA2_RLC2_DUMMY_REG
1961 #define SDMA2_RLC2_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
1962 #define SDMA2_RLC2_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
1963 //SDMA2_RLC2_RB_WPTR_POLL_ADDR_HI
1964 #define SDMA2_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
1965 #define SDMA2_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
1966 //SDMA2_RLC2_RB_WPTR_POLL_ADDR_LO
1967 #define SDMA2_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
1968 #define SDMA2_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
1969 //SDMA2_RLC2_RB_AQL_CNTL
1970 #define SDMA2_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
1971 #define SDMA2_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
1972 #define SDMA2_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
1973 #define SDMA2_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
1974 #define SDMA2_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
1975 #define SDMA2_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
1976 //SDMA2_RLC2_MINOR_PTR_UPDATE
1977 #define SDMA2_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
1978 #define SDMA2_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
1979 //SDMA2_RLC2_MIDCMD_DATA0
1980 #define SDMA2_RLC2_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
1981 #define SDMA2_RLC2_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
1982 //SDMA2_RLC2_MIDCMD_DATA1
1983 #define SDMA2_RLC2_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
1984 #define SDMA2_RLC2_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
1985 //SDMA2_RLC2_MIDCMD_DATA2
1986 #define SDMA2_RLC2_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
1987 #define SDMA2_RLC2_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
1988 //SDMA2_RLC2_MIDCMD_DATA3
1989 #define SDMA2_RLC2_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
1990 #define SDMA2_RLC2_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
1991 //SDMA2_RLC2_MIDCMD_DATA4
1992 #define SDMA2_RLC2_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
1993 #define SDMA2_RLC2_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
1994 //SDMA2_RLC2_MIDCMD_DATA5
1995 #define SDMA2_RLC2_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
1996 #define SDMA2_RLC2_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
1997 //SDMA2_RLC2_MIDCMD_DATA6
1998 #define SDMA2_RLC2_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
1999 #define SDMA2_RLC2_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
2000 //SDMA2_RLC2_MIDCMD_DATA7
2001 #define SDMA2_RLC2_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
2002 #define SDMA2_RLC2_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
2003 //SDMA2_RLC2_MIDCMD_DATA8
2004 #define SDMA2_RLC2_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
2005 #define SDMA2_RLC2_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
2006 //SDMA2_RLC2_MIDCMD_CNTL
2007 #define SDMA2_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
2008 #define SDMA2_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
2009 #define SDMA2_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
2010 #define SDMA2_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
2011 #define SDMA2_RLC2_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
2012 #define SDMA2_RLC2_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
2013 #define SDMA2_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
2014 #define SDMA2_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
2015 //SDMA2_RLC3_RB_CNTL
2016 #define SDMA2_RLC3_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
2017 #define SDMA2_RLC3_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
2018 #define SDMA2_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
2019 #define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
2020 #define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
2021 #define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
2022 #define SDMA2_RLC3_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
2023 #define SDMA2_RLC3_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
2024 #define SDMA2_RLC3_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
2025 #define SDMA2_RLC3_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
2026 #define SDMA2_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
2027 #define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
2028 #define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
2029 #define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
2030 #define SDMA2_RLC3_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
2031 #define SDMA2_RLC3_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
2032 //SDMA2_RLC3_RB_BASE
2033 #define SDMA2_RLC3_RB_BASE__ADDR__SHIFT                                                                       0x0
2034 #define SDMA2_RLC3_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
2035 //SDMA2_RLC3_RB_BASE_HI
2036 #define SDMA2_RLC3_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
2037 #define SDMA2_RLC3_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
2038 //SDMA2_RLC3_RB_RPTR
2039 #define SDMA2_RLC3_RB_RPTR__OFFSET__SHIFT                                                                     0x0
2040 #define SDMA2_RLC3_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
2041 //SDMA2_RLC3_RB_RPTR_HI
2042 #define SDMA2_RLC3_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
2043 #define SDMA2_RLC3_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
2044 //SDMA2_RLC3_RB_WPTR
2045 #define SDMA2_RLC3_RB_WPTR__OFFSET__SHIFT                                                                     0x0
2046 #define SDMA2_RLC3_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
2047 //SDMA2_RLC3_RB_WPTR_HI
2048 #define SDMA2_RLC3_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
2049 #define SDMA2_RLC3_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
2050 //SDMA2_RLC3_RB_WPTR_POLL_CNTL
2051 #define SDMA2_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
2052 #define SDMA2_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
2053 #define SDMA2_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
2054 #define SDMA2_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
2055 #define SDMA2_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
2056 #define SDMA2_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
2057 #define SDMA2_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
2058 #define SDMA2_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
2059 #define SDMA2_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
2060 #define SDMA2_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
2061 //SDMA2_RLC3_RB_RPTR_ADDR_HI
2062 #define SDMA2_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
2063 #define SDMA2_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
2064 //SDMA2_RLC3_RB_RPTR_ADDR_LO
2065 #define SDMA2_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
2066 #define SDMA2_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
2067 #define SDMA2_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
2068 #define SDMA2_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
2069 //SDMA2_RLC3_IB_CNTL
2070 #define SDMA2_RLC3_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
2071 #define SDMA2_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
2072 #define SDMA2_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
2073 #define SDMA2_RLC3_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
2074 #define SDMA2_RLC3_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
2075 #define SDMA2_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
2076 #define SDMA2_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
2077 #define SDMA2_RLC3_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
2078 //SDMA2_RLC3_IB_RPTR
2079 #define SDMA2_RLC3_IB_RPTR__OFFSET__SHIFT                                                                     0x2
2080 #define SDMA2_RLC3_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
2081 //SDMA2_RLC3_IB_OFFSET
2082 #define SDMA2_RLC3_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
2083 #define SDMA2_RLC3_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
2084 //SDMA2_RLC3_IB_BASE_LO
2085 #define SDMA2_RLC3_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
2086 #define SDMA2_RLC3_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
2087 //SDMA2_RLC3_IB_BASE_HI
2088 #define SDMA2_RLC3_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
2089 #define SDMA2_RLC3_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
2090 //SDMA2_RLC3_IB_SIZE
2091 #define SDMA2_RLC3_IB_SIZE__SIZE__SHIFT                                                                       0x0
2092 #define SDMA2_RLC3_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
2093 //SDMA2_RLC3_SKIP_CNTL
2094 #define SDMA2_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
2095 #define SDMA2_RLC3_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
2096 //SDMA2_RLC3_CONTEXT_STATUS
2097 #define SDMA2_RLC3_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
2098 #define SDMA2_RLC3_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
2099 #define SDMA2_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
2100 #define SDMA2_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
2101 #define SDMA2_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
2102 #define SDMA2_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
2103 #define SDMA2_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
2104 #define SDMA2_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
2105 #define SDMA2_RLC3_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
2106 #define SDMA2_RLC3_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
2107 #define SDMA2_RLC3_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
2108 #define SDMA2_RLC3_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
2109 #define SDMA2_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
2110 #define SDMA2_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
2111 #define SDMA2_RLC3_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
2112 #define SDMA2_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
2113 //SDMA2_RLC3_DOORBELL
2114 #define SDMA2_RLC3_DOORBELL__ENABLE__SHIFT                                                                    0x1c
2115 #define SDMA2_RLC3_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
2116 #define SDMA2_RLC3_DOORBELL__ENABLE_MASK                                                                      0x10000000L
2117 #define SDMA2_RLC3_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
2118 //SDMA2_RLC3_STATUS
2119 #define SDMA2_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
2120 #define SDMA2_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
2121 #define SDMA2_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
2122 #define SDMA2_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
2123 //SDMA2_RLC3_DOORBELL_LOG
2124 #define SDMA2_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
2125 #define SDMA2_RLC3_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
2126 #define SDMA2_RLC3_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
2127 #define SDMA2_RLC3_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
2128 //SDMA2_RLC3_WATERMARK
2129 #define SDMA2_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
2130 #define SDMA2_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
2131 #define SDMA2_RLC3_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
2132 #define SDMA2_RLC3_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
2133 //SDMA2_RLC3_DOORBELL_OFFSET
2134 #define SDMA2_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
2135 #define SDMA2_RLC3_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
2136 //SDMA2_RLC3_CSA_ADDR_LO
2137 #define SDMA2_RLC3_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
2138 #define SDMA2_RLC3_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
2139 //SDMA2_RLC3_CSA_ADDR_HI
2140 #define SDMA2_RLC3_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
2141 #define SDMA2_RLC3_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
2142 //SDMA2_RLC3_IB_SUB_REMAIN
2143 #define SDMA2_RLC3_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
2144 #define SDMA2_RLC3_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
2145 //SDMA2_RLC3_PREEMPT
2146 #define SDMA2_RLC3_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
2147 #define SDMA2_RLC3_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
2148 //SDMA2_RLC3_DUMMY_REG
2149 #define SDMA2_RLC3_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
2150 #define SDMA2_RLC3_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
2151 //SDMA2_RLC3_RB_WPTR_POLL_ADDR_HI
2152 #define SDMA2_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
2153 #define SDMA2_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
2154 //SDMA2_RLC3_RB_WPTR_POLL_ADDR_LO
2155 #define SDMA2_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
2156 #define SDMA2_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
2157 //SDMA2_RLC3_RB_AQL_CNTL
2158 #define SDMA2_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
2159 #define SDMA2_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
2160 #define SDMA2_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
2161 #define SDMA2_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
2162 #define SDMA2_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
2163 #define SDMA2_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
2164 //SDMA2_RLC3_MINOR_PTR_UPDATE
2165 #define SDMA2_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
2166 #define SDMA2_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
2167 //SDMA2_RLC3_MIDCMD_DATA0
2168 #define SDMA2_RLC3_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
2169 #define SDMA2_RLC3_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
2170 //SDMA2_RLC3_MIDCMD_DATA1
2171 #define SDMA2_RLC3_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
2172 #define SDMA2_RLC3_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
2173 //SDMA2_RLC3_MIDCMD_DATA2
2174 #define SDMA2_RLC3_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
2175 #define SDMA2_RLC3_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
2176 //SDMA2_RLC3_MIDCMD_DATA3
2177 #define SDMA2_RLC3_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
2178 #define SDMA2_RLC3_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
2179 //SDMA2_RLC3_MIDCMD_DATA4
2180 #define SDMA2_RLC3_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
2181 #define SDMA2_RLC3_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
2182 //SDMA2_RLC3_MIDCMD_DATA5
2183 #define SDMA2_RLC3_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
2184 #define SDMA2_RLC3_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
2185 //SDMA2_RLC3_MIDCMD_DATA6
2186 #define SDMA2_RLC3_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
2187 #define SDMA2_RLC3_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
2188 //SDMA2_RLC3_MIDCMD_DATA7
2189 #define SDMA2_RLC3_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
2190 #define SDMA2_RLC3_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
2191 //SDMA2_RLC3_MIDCMD_DATA8
2192 #define SDMA2_RLC3_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
2193 #define SDMA2_RLC3_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
2194 //SDMA2_RLC3_MIDCMD_CNTL
2195 #define SDMA2_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
2196 #define SDMA2_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
2197 #define SDMA2_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
2198 #define SDMA2_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
2199 #define SDMA2_RLC3_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
2200 #define SDMA2_RLC3_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
2201 #define SDMA2_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
2202 #define SDMA2_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
2203 //SDMA2_RLC4_RB_CNTL
2204 #define SDMA2_RLC4_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
2205 #define SDMA2_RLC4_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
2206 #define SDMA2_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
2207 #define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
2208 #define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
2209 #define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
2210 #define SDMA2_RLC4_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
2211 #define SDMA2_RLC4_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
2212 #define SDMA2_RLC4_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
2213 #define SDMA2_RLC4_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
2214 #define SDMA2_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
2215 #define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
2216 #define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
2217 #define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
2218 #define SDMA2_RLC4_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
2219 #define SDMA2_RLC4_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
2220 //SDMA2_RLC4_RB_BASE
2221 #define SDMA2_RLC4_RB_BASE__ADDR__SHIFT                                                                       0x0
2222 #define SDMA2_RLC4_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
2223 //SDMA2_RLC4_RB_BASE_HI
2224 #define SDMA2_RLC4_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
2225 #define SDMA2_RLC4_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
2226 //SDMA2_RLC4_RB_RPTR
2227 #define SDMA2_RLC4_RB_RPTR__OFFSET__SHIFT                                                                     0x0
2228 #define SDMA2_RLC4_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
2229 //SDMA2_RLC4_RB_RPTR_HI
2230 #define SDMA2_RLC4_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
2231 #define SDMA2_RLC4_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
2232 //SDMA2_RLC4_RB_WPTR
2233 #define SDMA2_RLC4_RB_WPTR__OFFSET__SHIFT                                                                     0x0
2234 #define SDMA2_RLC4_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
2235 //SDMA2_RLC4_RB_WPTR_HI
2236 #define SDMA2_RLC4_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
2237 #define SDMA2_RLC4_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
2238 //SDMA2_RLC4_RB_WPTR_POLL_CNTL
2239 #define SDMA2_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
2240 #define SDMA2_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
2241 #define SDMA2_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
2242 #define SDMA2_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
2243 #define SDMA2_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
2244 #define SDMA2_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
2245 #define SDMA2_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
2246 #define SDMA2_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
2247 #define SDMA2_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
2248 #define SDMA2_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
2249 //SDMA2_RLC4_RB_RPTR_ADDR_HI
2250 #define SDMA2_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
2251 #define SDMA2_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
2252 //SDMA2_RLC4_RB_RPTR_ADDR_LO
2253 #define SDMA2_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
2254 #define SDMA2_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
2255 #define SDMA2_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
2256 #define SDMA2_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
2257 //SDMA2_RLC4_IB_CNTL
2258 #define SDMA2_RLC4_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
2259 #define SDMA2_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
2260 #define SDMA2_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
2261 #define SDMA2_RLC4_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
2262 #define SDMA2_RLC4_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
2263 #define SDMA2_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
2264 #define SDMA2_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
2265 #define SDMA2_RLC4_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
2266 //SDMA2_RLC4_IB_RPTR
2267 #define SDMA2_RLC4_IB_RPTR__OFFSET__SHIFT                                                                     0x2
2268 #define SDMA2_RLC4_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
2269 //SDMA2_RLC4_IB_OFFSET
2270 #define SDMA2_RLC4_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
2271 #define SDMA2_RLC4_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
2272 //SDMA2_RLC4_IB_BASE_LO
2273 #define SDMA2_RLC4_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
2274 #define SDMA2_RLC4_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
2275 //SDMA2_RLC4_IB_BASE_HI
2276 #define SDMA2_RLC4_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
2277 #define SDMA2_RLC4_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
2278 //SDMA2_RLC4_IB_SIZE
2279 #define SDMA2_RLC4_IB_SIZE__SIZE__SHIFT                                                                       0x0
2280 #define SDMA2_RLC4_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
2281 //SDMA2_RLC4_SKIP_CNTL
2282 #define SDMA2_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
2283 #define SDMA2_RLC4_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
2284 //SDMA2_RLC4_CONTEXT_STATUS
2285 #define SDMA2_RLC4_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
2286 #define SDMA2_RLC4_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
2287 #define SDMA2_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
2288 #define SDMA2_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
2289 #define SDMA2_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
2290 #define SDMA2_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
2291 #define SDMA2_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
2292 #define SDMA2_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
2293 #define SDMA2_RLC4_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
2294 #define SDMA2_RLC4_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
2295 #define SDMA2_RLC4_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
2296 #define SDMA2_RLC4_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
2297 #define SDMA2_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
2298 #define SDMA2_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
2299 #define SDMA2_RLC4_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
2300 #define SDMA2_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
2301 //SDMA2_RLC4_DOORBELL
2302 #define SDMA2_RLC4_DOORBELL__ENABLE__SHIFT                                                                    0x1c
2303 #define SDMA2_RLC4_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
2304 #define SDMA2_RLC4_DOORBELL__ENABLE_MASK                                                                      0x10000000L
2305 #define SDMA2_RLC4_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
2306 //SDMA2_RLC4_STATUS
2307 #define SDMA2_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
2308 #define SDMA2_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
2309 #define SDMA2_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
2310 #define SDMA2_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
2311 //SDMA2_RLC4_DOORBELL_LOG
2312 #define SDMA2_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
2313 #define SDMA2_RLC4_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
2314 #define SDMA2_RLC4_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
2315 #define SDMA2_RLC4_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
2316 //SDMA2_RLC4_WATERMARK
2317 #define SDMA2_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
2318 #define SDMA2_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
2319 #define SDMA2_RLC4_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
2320 #define SDMA2_RLC4_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
2321 //SDMA2_RLC4_DOORBELL_OFFSET
2322 #define SDMA2_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
2323 #define SDMA2_RLC4_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
2324 //SDMA2_RLC4_CSA_ADDR_LO
2325 #define SDMA2_RLC4_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
2326 #define SDMA2_RLC4_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
2327 //SDMA2_RLC4_CSA_ADDR_HI
2328 #define SDMA2_RLC4_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
2329 #define SDMA2_RLC4_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
2330 //SDMA2_RLC4_IB_SUB_REMAIN
2331 #define SDMA2_RLC4_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
2332 #define SDMA2_RLC4_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
2333 //SDMA2_RLC4_PREEMPT
2334 #define SDMA2_RLC4_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
2335 #define SDMA2_RLC4_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
2336 //SDMA2_RLC4_DUMMY_REG
2337 #define SDMA2_RLC4_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
2338 #define SDMA2_RLC4_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
2339 //SDMA2_RLC4_RB_WPTR_POLL_ADDR_HI
2340 #define SDMA2_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
2341 #define SDMA2_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
2342 //SDMA2_RLC4_RB_WPTR_POLL_ADDR_LO
2343 #define SDMA2_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
2344 #define SDMA2_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
2345 //SDMA2_RLC4_RB_AQL_CNTL
2346 #define SDMA2_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
2347 #define SDMA2_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
2348 #define SDMA2_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
2349 #define SDMA2_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
2350 #define SDMA2_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
2351 #define SDMA2_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
2352 //SDMA2_RLC4_MINOR_PTR_UPDATE
2353 #define SDMA2_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
2354 #define SDMA2_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
2355 //SDMA2_RLC4_MIDCMD_DATA0
2356 #define SDMA2_RLC4_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
2357 #define SDMA2_RLC4_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
2358 //SDMA2_RLC4_MIDCMD_DATA1
2359 #define SDMA2_RLC4_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
2360 #define SDMA2_RLC4_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
2361 //SDMA2_RLC4_MIDCMD_DATA2
2362 #define SDMA2_RLC4_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
2363 #define SDMA2_RLC4_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
2364 //SDMA2_RLC4_MIDCMD_DATA3
2365 #define SDMA2_RLC4_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
2366 #define SDMA2_RLC4_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
2367 //SDMA2_RLC4_MIDCMD_DATA4
2368 #define SDMA2_RLC4_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
2369 #define SDMA2_RLC4_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
2370 //SDMA2_RLC4_MIDCMD_DATA5
2371 #define SDMA2_RLC4_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
2372 #define SDMA2_RLC4_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
2373 //SDMA2_RLC4_MIDCMD_DATA6
2374 #define SDMA2_RLC4_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
2375 #define SDMA2_RLC4_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
2376 //SDMA2_RLC4_MIDCMD_DATA7
2377 #define SDMA2_RLC4_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
2378 #define SDMA2_RLC4_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
2379 //SDMA2_RLC4_MIDCMD_DATA8
2380 #define SDMA2_RLC4_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
2381 #define SDMA2_RLC4_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
2382 //SDMA2_RLC4_MIDCMD_CNTL
2383 #define SDMA2_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
2384 #define SDMA2_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
2385 #define SDMA2_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
2386 #define SDMA2_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
2387 #define SDMA2_RLC4_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
2388 #define SDMA2_RLC4_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
2389 #define SDMA2_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
2390 #define SDMA2_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
2391 //SDMA2_RLC5_RB_CNTL
2392 #define SDMA2_RLC5_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
2393 #define SDMA2_RLC5_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
2394 #define SDMA2_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
2395 #define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
2396 #define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
2397 #define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
2398 #define SDMA2_RLC5_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
2399 #define SDMA2_RLC5_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
2400 #define SDMA2_RLC5_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
2401 #define SDMA2_RLC5_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
2402 #define SDMA2_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
2403 #define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
2404 #define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
2405 #define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
2406 #define SDMA2_RLC5_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
2407 #define SDMA2_RLC5_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
2408 //SDMA2_RLC5_RB_BASE
2409 #define SDMA2_RLC5_RB_BASE__ADDR__SHIFT                                                                       0x0
2410 #define SDMA2_RLC5_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
2411 //SDMA2_RLC5_RB_BASE_HI
2412 #define SDMA2_RLC5_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
2413 #define SDMA2_RLC5_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
2414 //SDMA2_RLC5_RB_RPTR
2415 #define SDMA2_RLC5_RB_RPTR__OFFSET__SHIFT                                                                     0x0
2416 #define SDMA2_RLC5_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
2417 //SDMA2_RLC5_RB_RPTR_HI
2418 #define SDMA2_RLC5_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
2419 #define SDMA2_RLC5_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
2420 //SDMA2_RLC5_RB_WPTR
2421 #define SDMA2_RLC5_RB_WPTR__OFFSET__SHIFT                                                                     0x0
2422 #define SDMA2_RLC5_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
2423 //SDMA2_RLC5_RB_WPTR_HI
2424 #define SDMA2_RLC5_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
2425 #define SDMA2_RLC5_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
2426 //SDMA2_RLC5_RB_WPTR_POLL_CNTL
2427 #define SDMA2_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
2428 #define SDMA2_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
2429 #define SDMA2_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
2430 #define SDMA2_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
2431 #define SDMA2_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
2432 #define SDMA2_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
2433 #define SDMA2_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
2434 #define SDMA2_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
2435 #define SDMA2_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
2436 #define SDMA2_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
2437 //SDMA2_RLC5_RB_RPTR_ADDR_HI
2438 #define SDMA2_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
2439 #define SDMA2_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
2440 //SDMA2_RLC5_RB_RPTR_ADDR_LO
2441 #define SDMA2_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
2442 #define SDMA2_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
2443 #define SDMA2_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
2444 #define SDMA2_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
2445 //SDMA2_RLC5_IB_CNTL
2446 #define SDMA2_RLC5_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
2447 #define SDMA2_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
2448 #define SDMA2_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
2449 #define SDMA2_RLC5_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
2450 #define SDMA2_RLC5_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
2451 #define SDMA2_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
2452 #define SDMA2_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
2453 #define SDMA2_RLC5_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
2454 //SDMA2_RLC5_IB_RPTR
2455 #define SDMA2_RLC5_IB_RPTR__OFFSET__SHIFT                                                                     0x2
2456 #define SDMA2_RLC5_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
2457 //SDMA2_RLC5_IB_OFFSET
2458 #define SDMA2_RLC5_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
2459 #define SDMA2_RLC5_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
2460 //SDMA2_RLC5_IB_BASE_LO
2461 #define SDMA2_RLC5_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
2462 #define SDMA2_RLC5_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
2463 //SDMA2_RLC5_IB_BASE_HI
2464 #define SDMA2_RLC5_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
2465 #define SDMA2_RLC5_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
2466 //SDMA2_RLC5_IB_SIZE
2467 #define SDMA2_RLC5_IB_SIZE__SIZE__SHIFT                                                                       0x0
2468 #define SDMA2_RLC5_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
2469 //SDMA2_RLC5_SKIP_CNTL
2470 #define SDMA2_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
2471 #define SDMA2_RLC5_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
2472 //SDMA2_RLC5_CONTEXT_STATUS
2473 #define SDMA2_RLC5_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
2474 #define SDMA2_RLC5_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
2475 #define SDMA2_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
2476 #define SDMA2_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
2477 #define SDMA2_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
2478 #define SDMA2_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
2479 #define SDMA2_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
2480 #define SDMA2_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
2481 #define SDMA2_RLC5_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
2482 #define SDMA2_RLC5_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
2483 #define SDMA2_RLC5_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
2484 #define SDMA2_RLC5_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
2485 #define SDMA2_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
2486 #define SDMA2_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
2487 #define SDMA2_RLC5_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
2488 #define SDMA2_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
2489 //SDMA2_RLC5_DOORBELL
2490 #define SDMA2_RLC5_DOORBELL__ENABLE__SHIFT                                                                    0x1c
2491 #define SDMA2_RLC5_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
2492 #define SDMA2_RLC5_DOORBELL__ENABLE_MASK                                                                      0x10000000L
2493 #define SDMA2_RLC5_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
2494 //SDMA2_RLC5_STATUS
2495 #define SDMA2_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
2496 #define SDMA2_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
2497 #define SDMA2_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
2498 #define SDMA2_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
2499 //SDMA2_RLC5_DOORBELL_LOG
2500 #define SDMA2_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
2501 #define SDMA2_RLC5_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
2502 #define SDMA2_RLC5_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
2503 #define SDMA2_RLC5_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
2504 //SDMA2_RLC5_WATERMARK
2505 #define SDMA2_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
2506 #define SDMA2_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
2507 #define SDMA2_RLC5_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
2508 #define SDMA2_RLC5_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
2509 //SDMA2_RLC5_DOORBELL_OFFSET
2510 #define SDMA2_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
2511 #define SDMA2_RLC5_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
2512 //SDMA2_RLC5_CSA_ADDR_LO
2513 #define SDMA2_RLC5_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
2514 #define SDMA2_RLC5_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
2515 //SDMA2_RLC5_CSA_ADDR_HI
2516 #define SDMA2_RLC5_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
2517 #define SDMA2_RLC5_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
2518 //SDMA2_RLC5_IB_SUB_REMAIN
2519 #define SDMA2_RLC5_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
2520 #define SDMA2_RLC5_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
2521 //SDMA2_RLC5_PREEMPT
2522 #define SDMA2_RLC5_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
2523 #define SDMA2_RLC5_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
2524 //SDMA2_RLC5_DUMMY_REG
2525 #define SDMA2_RLC5_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
2526 #define SDMA2_RLC5_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
2527 //SDMA2_RLC5_RB_WPTR_POLL_ADDR_HI
2528 #define SDMA2_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
2529 #define SDMA2_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
2530 //SDMA2_RLC5_RB_WPTR_POLL_ADDR_LO
2531 #define SDMA2_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
2532 #define SDMA2_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
2533 //SDMA2_RLC5_RB_AQL_CNTL
2534 #define SDMA2_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
2535 #define SDMA2_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
2536 #define SDMA2_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
2537 #define SDMA2_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
2538 #define SDMA2_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
2539 #define SDMA2_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
2540 //SDMA2_RLC5_MINOR_PTR_UPDATE
2541 #define SDMA2_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
2542 #define SDMA2_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
2543 //SDMA2_RLC5_MIDCMD_DATA0
2544 #define SDMA2_RLC5_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
2545 #define SDMA2_RLC5_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
2546 //SDMA2_RLC5_MIDCMD_DATA1
2547 #define SDMA2_RLC5_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
2548 #define SDMA2_RLC5_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
2549 //SDMA2_RLC5_MIDCMD_DATA2
2550 #define SDMA2_RLC5_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
2551 #define SDMA2_RLC5_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
2552 //SDMA2_RLC5_MIDCMD_DATA3
2553 #define SDMA2_RLC5_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
2554 #define SDMA2_RLC5_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
2555 //SDMA2_RLC5_MIDCMD_DATA4
2556 #define SDMA2_RLC5_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
2557 #define SDMA2_RLC5_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
2558 //SDMA2_RLC5_MIDCMD_DATA5
2559 #define SDMA2_RLC5_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
2560 #define SDMA2_RLC5_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
2561 //SDMA2_RLC5_MIDCMD_DATA6
2562 #define SDMA2_RLC5_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
2563 #define SDMA2_RLC5_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
2564 //SDMA2_RLC5_MIDCMD_DATA7
2565 #define SDMA2_RLC5_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
2566 #define SDMA2_RLC5_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
2567 //SDMA2_RLC5_MIDCMD_DATA8
2568 #define SDMA2_RLC5_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
2569 #define SDMA2_RLC5_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
2570 //SDMA2_RLC5_MIDCMD_CNTL
2571 #define SDMA2_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
2572 #define SDMA2_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
2573 #define SDMA2_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
2574 #define SDMA2_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
2575 #define SDMA2_RLC5_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
2576 #define SDMA2_RLC5_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
2577 #define SDMA2_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
2578 #define SDMA2_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
2579 //SDMA2_RLC6_RB_CNTL
2580 #define SDMA2_RLC6_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
2581 #define SDMA2_RLC6_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
2582 #define SDMA2_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
2583 #define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
2584 #define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
2585 #define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
2586 #define SDMA2_RLC6_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
2587 #define SDMA2_RLC6_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
2588 #define SDMA2_RLC6_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
2589 #define SDMA2_RLC6_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
2590 #define SDMA2_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
2591 #define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
2592 #define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
2593 #define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
2594 #define SDMA2_RLC6_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
2595 #define SDMA2_RLC6_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
2596 //SDMA2_RLC6_RB_BASE
2597 #define SDMA2_RLC6_RB_BASE__ADDR__SHIFT                                                                       0x0
2598 #define SDMA2_RLC6_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
2599 //SDMA2_RLC6_RB_BASE_HI
2600 #define SDMA2_RLC6_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
2601 #define SDMA2_RLC6_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
2602 //SDMA2_RLC6_RB_RPTR
2603 #define SDMA2_RLC6_RB_RPTR__OFFSET__SHIFT                                                                     0x0
2604 #define SDMA2_RLC6_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
2605 //SDMA2_RLC6_RB_RPTR_HI
2606 #define SDMA2_RLC6_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
2607 #define SDMA2_RLC6_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
2608 //SDMA2_RLC6_RB_WPTR
2609 #define SDMA2_RLC6_RB_WPTR__OFFSET__SHIFT                                                                     0x0
2610 #define SDMA2_RLC6_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
2611 //SDMA2_RLC6_RB_WPTR_HI
2612 #define SDMA2_RLC6_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
2613 #define SDMA2_RLC6_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
2614 //SDMA2_RLC6_RB_WPTR_POLL_CNTL
2615 #define SDMA2_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
2616 #define SDMA2_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
2617 #define SDMA2_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
2618 #define SDMA2_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
2619 #define SDMA2_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
2620 #define SDMA2_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
2621 #define SDMA2_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
2622 #define SDMA2_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
2623 #define SDMA2_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
2624 #define SDMA2_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
2625 //SDMA2_RLC6_RB_RPTR_ADDR_HI
2626 #define SDMA2_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
2627 #define SDMA2_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
2628 //SDMA2_RLC6_RB_RPTR_ADDR_LO
2629 #define SDMA2_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
2630 #define SDMA2_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
2631 #define SDMA2_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
2632 #define SDMA2_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
2633 //SDMA2_RLC6_IB_CNTL
2634 #define SDMA2_RLC6_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
2635 #define SDMA2_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
2636 #define SDMA2_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
2637 #define SDMA2_RLC6_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
2638 #define SDMA2_RLC6_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
2639 #define SDMA2_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
2640 #define SDMA2_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
2641 #define SDMA2_RLC6_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
2642 //SDMA2_RLC6_IB_RPTR
2643 #define SDMA2_RLC6_IB_RPTR__OFFSET__SHIFT                                                                     0x2
2644 #define SDMA2_RLC6_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
2645 //SDMA2_RLC6_IB_OFFSET
2646 #define SDMA2_RLC6_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
2647 #define SDMA2_RLC6_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
2648 //SDMA2_RLC6_IB_BASE_LO
2649 #define SDMA2_RLC6_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
2650 #define SDMA2_RLC6_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
2651 //SDMA2_RLC6_IB_BASE_HI
2652 #define SDMA2_RLC6_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
2653 #define SDMA2_RLC6_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
2654 //SDMA2_RLC6_IB_SIZE
2655 #define SDMA2_RLC6_IB_SIZE__SIZE__SHIFT                                                                       0x0
2656 #define SDMA2_RLC6_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
2657 //SDMA2_RLC6_SKIP_CNTL
2658 #define SDMA2_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
2659 #define SDMA2_RLC6_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
2660 //SDMA2_RLC6_CONTEXT_STATUS
2661 #define SDMA2_RLC6_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
2662 #define SDMA2_RLC6_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
2663 #define SDMA2_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
2664 #define SDMA2_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
2665 #define SDMA2_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
2666 #define SDMA2_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
2667 #define SDMA2_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
2668 #define SDMA2_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
2669 #define SDMA2_RLC6_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
2670 #define SDMA2_RLC6_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
2671 #define SDMA2_RLC6_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
2672 #define SDMA2_RLC6_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
2673 #define SDMA2_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
2674 #define SDMA2_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
2675 #define SDMA2_RLC6_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
2676 #define SDMA2_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
2677 //SDMA2_RLC6_DOORBELL
2678 #define SDMA2_RLC6_DOORBELL__ENABLE__SHIFT                                                                    0x1c
2679 #define SDMA2_RLC6_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
2680 #define SDMA2_RLC6_DOORBELL__ENABLE_MASK                                                                      0x10000000L
2681 #define SDMA2_RLC6_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
2682 //SDMA2_RLC6_STATUS
2683 #define SDMA2_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
2684 #define SDMA2_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
2685 #define SDMA2_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
2686 #define SDMA2_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
2687 //SDMA2_RLC6_DOORBELL_LOG
2688 #define SDMA2_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
2689 #define SDMA2_RLC6_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
2690 #define SDMA2_RLC6_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
2691 #define SDMA2_RLC6_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
2692 //SDMA2_RLC6_WATERMARK
2693 #define SDMA2_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
2694 #define SDMA2_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
2695 #define SDMA2_RLC6_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
2696 #define SDMA2_RLC6_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
2697 //SDMA2_RLC6_DOORBELL_OFFSET
2698 #define SDMA2_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
2699 #define SDMA2_RLC6_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
2700 //SDMA2_RLC6_CSA_ADDR_LO
2701 #define SDMA2_RLC6_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
2702 #define SDMA2_RLC6_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
2703 //SDMA2_RLC6_CSA_ADDR_HI
2704 #define SDMA2_RLC6_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
2705 #define SDMA2_RLC6_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
2706 //SDMA2_RLC6_IB_SUB_REMAIN
2707 #define SDMA2_RLC6_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
2708 #define SDMA2_RLC6_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
2709 //SDMA2_RLC6_PREEMPT
2710 #define SDMA2_RLC6_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
2711 #define SDMA2_RLC6_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
2712 //SDMA2_RLC6_DUMMY_REG
2713 #define SDMA2_RLC6_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
2714 #define SDMA2_RLC6_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
2715 //SDMA2_RLC6_RB_WPTR_POLL_ADDR_HI
2716 #define SDMA2_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
2717 #define SDMA2_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
2718 //SDMA2_RLC6_RB_WPTR_POLL_ADDR_LO
2719 #define SDMA2_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
2720 #define SDMA2_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
2721 //SDMA2_RLC6_RB_AQL_CNTL
2722 #define SDMA2_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
2723 #define SDMA2_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
2724 #define SDMA2_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
2725 #define SDMA2_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
2726 #define SDMA2_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
2727 #define SDMA2_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
2728 //SDMA2_RLC6_MINOR_PTR_UPDATE
2729 #define SDMA2_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
2730 #define SDMA2_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
2731 //SDMA2_RLC6_MIDCMD_DATA0
2732 #define SDMA2_RLC6_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
2733 #define SDMA2_RLC6_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
2734 //SDMA2_RLC6_MIDCMD_DATA1
2735 #define SDMA2_RLC6_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
2736 #define SDMA2_RLC6_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
2737 //SDMA2_RLC6_MIDCMD_DATA2
2738 #define SDMA2_RLC6_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
2739 #define SDMA2_RLC6_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
2740 //SDMA2_RLC6_MIDCMD_DATA3
2741 #define SDMA2_RLC6_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
2742 #define SDMA2_RLC6_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
2743 //SDMA2_RLC6_MIDCMD_DATA4
2744 #define SDMA2_RLC6_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
2745 #define SDMA2_RLC6_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
2746 //SDMA2_RLC6_MIDCMD_DATA5
2747 #define SDMA2_RLC6_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
2748 #define SDMA2_RLC6_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
2749 //SDMA2_RLC6_MIDCMD_DATA6
2750 #define SDMA2_RLC6_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
2751 #define SDMA2_RLC6_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
2752 //SDMA2_RLC6_MIDCMD_DATA7
2753 #define SDMA2_RLC6_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
2754 #define SDMA2_RLC6_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
2755 //SDMA2_RLC6_MIDCMD_DATA8
2756 #define SDMA2_RLC6_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
2757 #define SDMA2_RLC6_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
2758 //SDMA2_RLC6_MIDCMD_CNTL
2759 #define SDMA2_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
2760 #define SDMA2_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
2761 #define SDMA2_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
2762 #define SDMA2_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
2763 #define SDMA2_RLC6_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
2764 #define SDMA2_RLC6_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
2765 #define SDMA2_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
2766 #define SDMA2_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
2767 //SDMA2_RLC7_RB_CNTL
2768 #define SDMA2_RLC7_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
2769 #define SDMA2_RLC7_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
2770 #define SDMA2_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
2771 #define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
2772 #define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
2773 #define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
2774 #define SDMA2_RLC7_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
2775 #define SDMA2_RLC7_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
2776 #define SDMA2_RLC7_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
2777 #define SDMA2_RLC7_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
2778 #define SDMA2_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
2779 #define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
2780 #define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
2781 #define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
2782 #define SDMA2_RLC7_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
2783 #define SDMA2_RLC7_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
2784 //SDMA2_RLC7_RB_BASE
2785 #define SDMA2_RLC7_RB_BASE__ADDR__SHIFT                                                                       0x0
2786 #define SDMA2_RLC7_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
2787 //SDMA2_RLC7_RB_BASE_HI
2788 #define SDMA2_RLC7_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
2789 #define SDMA2_RLC7_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
2790 //SDMA2_RLC7_RB_RPTR
2791 #define SDMA2_RLC7_RB_RPTR__OFFSET__SHIFT                                                                     0x0
2792 #define SDMA2_RLC7_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
2793 //SDMA2_RLC7_RB_RPTR_HI
2794 #define SDMA2_RLC7_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
2795 #define SDMA2_RLC7_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
2796 //SDMA2_RLC7_RB_WPTR
2797 #define SDMA2_RLC7_RB_WPTR__OFFSET__SHIFT                                                                     0x0
2798 #define SDMA2_RLC7_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
2799 //SDMA2_RLC7_RB_WPTR_HI
2800 #define SDMA2_RLC7_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
2801 #define SDMA2_RLC7_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
2802 //SDMA2_RLC7_RB_WPTR_POLL_CNTL
2803 #define SDMA2_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
2804 #define SDMA2_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
2805 #define SDMA2_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
2806 #define SDMA2_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
2807 #define SDMA2_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
2808 #define SDMA2_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
2809 #define SDMA2_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
2810 #define SDMA2_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
2811 #define SDMA2_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
2812 #define SDMA2_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
2813 //SDMA2_RLC7_RB_RPTR_ADDR_HI
2814 #define SDMA2_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
2815 #define SDMA2_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
2816 //SDMA2_RLC7_RB_RPTR_ADDR_LO
2817 #define SDMA2_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
2818 #define SDMA2_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
2819 #define SDMA2_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
2820 #define SDMA2_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
2821 //SDMA2_RLC7_IB_CNTL
2822 #define SDMA2_RLC7_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
2823 #define SDMA2_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
2824 #define SDMA2_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
2825 #define SDMA2_RLC7_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
2826 #define SDMA2_RLC7_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
2827 #define SDMA2_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
2828 #define SDMA2_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
2829 #define SDMA2_RLC7_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
2830 //SDMA2_RLC7_IB_RPTR
2831 #define SDMA2_RLC7_IB_RPTR__OFFSET__SHIFT                                                                     0x2
2832 #define SDMA2_RLC7_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
2833 //SDMA2_RLC7_IB_OFFSET
2834 #define SDMA2_RLC7_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
2835 #define SDMA2_RLC7_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
2836 //SDMA2_RLC7_IB_BASE_LO
2837 #define SDMA2_RLC7_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
2838 #define SDMA2_RLC7_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
2839 //SDMA2_RLC7_IB_BASE_HI
2840 #define SDMA2_RLC7_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
2841 #define SDMA2_RLC7_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
2842 //SDMA2_RLC7_IB_SIZE
2843 #define SDMA2_RLC7_IB_SIZE__SIZE__SHIFT                                                                       0x0
2844 #define SDMA2_RLC7_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
2845 //SDMA2_RLC7_SKIP_CNTL
2846 #define SDMA2_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
2847 #define SDMA2_RLC7_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
2848 //SDMA2_RLC7_CONTEXT_STATUS
2849 #define SDMA2_RLC7_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
2850 #define SDMA2_RLC7_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
2851 #define SDMA2_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
2852 #define SDMA2_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
2853 #define SDMA2_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
2854 #define SDMA2_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
2855 #define SDMA2_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
2856 #define SDMA2_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
2857 #define SDMA2_RLC7_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
2858 #define SDMA2_RLC7_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
2859 #define SDMA2_RLC7_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
2860 #define SDMA2_RLC7_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
2861 #define SDMA2_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
2862 #define SDMA2_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
2863 #define SDMA2_RLC7_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
2864 #define SDMA2_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
2865 //SDMA2_RLC7_DOORBELL
2866 #define SDMA2_RLC7_DOORBELL__ENABLE__SHIFT                                                                    0x1c
2867 #define SDMA2_RLC7_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
2868 #define SDMA2_RLC7_DOORBELL__ENABLE_MASK                                                                      0x10000000L
2869 #define SDMA2_RLC7_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
2870 //SDMA2_RLC7_STATUS
2871 #define SDMA2_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
2872 #define SDMA2_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
2873 #define SDMA2_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
2874 #define SDMA2_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
2875 //SDMA2_RLC7_DOORBELL_LOG
2876 #define SDMA2_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
2877 #define SDMA2_RLC7_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
2878 #define SDMA2_RLC7_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
2879 #define SDMA2_RLC7_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
2880 //SDMA2_RLC7_WATERMARK
2881 #define SDMA2_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
2882 #define SDMA2_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
2883 #define SDMA2_RLC7_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
2884 #define SDMA2_RLC7_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
2885 //SDMA2_RLC7_DOORBELL_OFFSET
2886 #define SDMA2_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
2887 #define SDMA2_RLC7_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
2888 //SDMA2_RLC7_CSA_ADDR_LO
2889 #define SDMA2_RLC7_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
2890 #define SDMA2_RLC7_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
2891 //SDMA2_RLC7_CSA_ADDR_HI
2892 #define SDMA2_RLC7_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
2893 #define SDMA2_RLC7_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
2894 //SDMA2_RLC7_IB_SUB_REMAIN
2895 #define SDMA2_RLC7_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
2896 #define SDMA2_RLC7_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
2897 //SDMA2_RLC7_PREEMPT
2898 #define SDMA2_RLC7_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
2899 #define SDMA2_RLC7_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
2900 //SDMA2_RLC7_DUMMY_REG
2901 #define SDMA2_RLC7_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
2902 #define SDMA2_RLC7_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
2903 //SDMA2_RLC7_RB_WPTR_POLL_ADDR_HI
2904 #define SDMA2_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
2905 #define SDMA2_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
2906 //SDMA2_RLC7_RB_WPTR_POLL_ADDR_LO
2907 #define SDMA2_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
2908 #define SDMA2_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
2909 //SDMA2_RLC7_RB_AQL_CNTL
2910 #define SDMA2_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
2911 #define SDMA2_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
2912 #define SDMA2_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
2913 #define SDMA2_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
2914 #define SDMA2_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
2915 #define SDMA2_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
2916 //SDMA2_RLC7_MINOR_PTR_UPDATE
2917 #define SDMA2_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
2918 #define SDMA2_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
2919 //SDMA2_RLC7_MIDCMD_DATA0
2920 #define SDMA2_RLC7_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
2921 #define SDMA2_RLC7_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
2922 //SDMA2_RLC7_MIDCMD_DATA1
2923 #define SDMA2_RLC7_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
2924 #define SDMA2_RLC7_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
2925 //SDMA2_RLC7_MIDCMD_DATA2
2926 #define SDMA2_RLC7_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
2927 #define SDMA2_RLC7_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
2928 //SDMA2_RLC7_MIDCMD_DATA3
2929 #define SDMA2_RLC7_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
2930 #define SDMA2_RLC7_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
2931 //SDMA2_RLC7_MIDCMD_DATA4
2932 #define SDMA2_RLC7_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
2933 #define SDMA2_RLC7_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
2934 //SDMA2_RLC7_MIDCMD_DATA5
2935 #define SDMA2_RLC7_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
2936 #define SDMA2_RLC7_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
2937 //SDMA2_RLC7_MIDCMD_DATA6
2938 #define SDMA2_RLC7_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
2939 #define SDMA2_RLC7_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
2940 //SDMA2_RLC7_MIDCMD_DATA7
2941 #define SDMA2_RLC7_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
2942 #define SDMA2_RLC7_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
2943 //SDMA2_RLC7_MIDCMD_DATA8
2944 #define SDMA2_RLC7_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
2945 #define SDMA2_RLC7_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
2946 //SDMA2_RLC7_MIDCMD_CNTL
2947 #define SDMA2_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
2948 #define SDMA2_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
2949 #define SDMA2_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
2950 #define SDMA2_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
2951 #define SDMA2_RLC7_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
2952 #define SDMA2_RLC7_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
2953 #define SDMA2_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
2954 #define SDMA2_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
2955 
2956 #endif