drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh

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   1 /*
   2  *
   3  * Copyright (C) 2016 Advanced Micro Devices, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included
  13  * in all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  16  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  19  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  20  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22 
  23 #ifndef UVD_4_0_SH_MASK_H
  24 #define UVD_4_0_SH_MASK_H
  25 
  26 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x00000001L
  27 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x00000000
  28 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x00000002L
  29 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x00000001
  30 #define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x0000001cL
  31 #define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x00000002
  32 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003cL
  33 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x00000002
  34 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007c0L
  35 #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x00000006
  36 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L
  37 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x00000000
  38 #define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L
  39 #define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x00000017
  40 #define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L
  41 #define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x0000001a
  42 #define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L
  43 #define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x00000015
  44 #define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L
  45 #define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x00000016
  46 #define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L
  47 #define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x0000001b
  48 #define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L
  49 #define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x00000019
  50 #define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L
  51 #define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x00000012
  52 #define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L
  53 #define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x00000018
  54 #define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L
  55 #define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x00000014
  56 #define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L
  57 #define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x00000013
  58 #define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000L
  59 #define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x0000001e
  60 #define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L
  61 #define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x00000010
  62 #define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L
  63 #define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0x0000000c
  64 #define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L
  65 #define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0x0000000e
  66 #define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L
  67 #define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0x0000000d
  68 #define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L
  69 #define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x00000011
  70 #define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L
  71 #define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0x0000000f
  72 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L
  73 #define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0x0000000b
  74 #define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L
  75 #define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x0000001d
  76 #define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L
  77 #define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x0000001c
  78 #define UVD_CGC_GATE__IDCT_MASK 0x00000080L
  79 #define UVD_CGC_GATE__IDCT__SHIFT 0x00000007
  80 #define UVD_CGC_GATE__LBSI_MASK 0x00000400L
  81 #define UVD_CGC_GATE__LBSI__SHIFT 0x0000000a
  82 #define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L
  83 #define UVD_CGC_GATE__LMI_MC__SHIFT 0x00000005
  84 #define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L
  85 #define UVD_CGC_GATE__LMI_UMC__SHIFT 0x00000006
  86 #define UVD_CGC_GATE__LRBBM_MASK 0x00000800L
  87 #define UVD_CGC_GATE__LRBBM__SHIFT 0x0000000b
  88 #define UVD_CGC_GATE__MPC_MASK 0x00000200L
  89 #define UVD_CGC_GATE__MPC__SHIFT 0x00000009
  90 #define UVD_CGC_GATE__MPEG2_MASK 0x00000004L
  91 #define UVD_CGC_GATE__MPEG2__SHIFT 0x00000002
  92 #define UVD_CGC_GATE__MPRD_MASK 0x00000100L
  93 #define UVD_CGC_GATE__MPRD__SHIFT 0x00000008
  94 #define UVD_CGC_GATE__RBC_MASK 0x00000010L
  95 #define UVD_CGC_GATE__RBC__SHIFT 0x00000004
  96 #define UVD_CGC_GATE__REGS_MASK 0x00000008L
  97 #define UVD_CGC_GATE__REGS__SHIFT 0x00000003
  98 #define UVD_CGC_GATE__SCPU_MASK 0x00080000L
  99 #define UVD_CGC_GATE__SCPU__SHIFT 0x00000013
 100 #define UVD_CGC_GATE__SYS_MASK 0x00000001L
 101 #define UVD_CGC_GATE__SYS__SHIFT 0x00000000
 102 #define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L
 103 #define UVD_CGC_GATE__UDEC_CM__SHIFT 0x0000000d
 104 #define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L
 105 #define UVD_CGC_GATE__UDEC_DB__SHIFT 0x0000000f
 106 #define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L
 107 #define UVD_CGC_GATE__UDEC_IT__SHIFT 0x0000000e
 108 #define UVD_CGC_GATE__UDEC_MASK 0x00000002L
 109 #define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L
 110 #define UVD_CGC_GATE__UDEC_MP__SHIFT 0x00000010
 111 #define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L
 112 #define UVD_CGC_GATE__UDEC_RE__SHIFT 0x0000000c
 113 #define UVD_CGC_GATE__UDEC__SHIFT 0x00000001
 114 #define UVD_CGC_GATE__VCPU_MASK 0x00040000L
 115 #define UVD_CGC_GATE__VCPU__SHIFT 0x00000012
 116 #define UVD_CGC_GATE__WCB_MASK 0x00020000L
 117 #define UVD_CGC_GATE__WCB__SHIFT 0x00000011
 118 #define UVD_CGC_MEM_CTRL__LCM_LS_EN_MASK 0x00002000L
 119 #define UVD_CGC_MEM_CTRL__LCM_LS_EN__SHIFT 0x0000000d
 120 #define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN_MASK 0x00000001L
 121 #define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN__SHIFT 0x00000000
 122 #define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0x00f00000L
 123 #define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x00000014
 124 #define UVD_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0x000f0000L
 125 #define UVD_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x00000010
 126 #define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x00001000L
 127 #define UVD_CGC_MEM_CTRL__MIF_LS_EN__SHIFT 0x0000000c
 128 #define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x00000002L
 129 #define UVD_CGC_MEM_CTRL__MPC_LS_EN__SHIFT 0x00000001
 130 #define UVD_CGC_MEM_CTRL__MPRD_LS_EN_MASK 0x00000004L
 131 #define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x00000002
 132 #define UVD_CGC_MEM_CTRL__SCPU_LS_EN_MASK 0x00000800L
 133 #define UVD_CGC_MEM_CTRL__SCPU_LS_EN__SHIFT 0x0000000b
 134 #define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x00000200L
 135 #define UVD_CGC_MEM_CTRL__SYS_LS_EN__SHIFT 0x00000009
 136 #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x00000020L
 137 #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x00000005
 138 #define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x00000080L
 139 #define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN__SHIFT 0x00000007
 140 #define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN_MASK 0x00000040L
 141 #define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN__SHIFT 0x00000006
 142 #define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x00000100L
 143 #define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN__SHIFT 0x00000008
 144 #define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN_MASK 0x00000010L
 145 #define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN__SHIFT 0x00000004
 146 #define UVD_CGC_MEM_CTRL__VCPU_LS_EN_MASK 0x00000400L
 147 #define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0x0000000a
 148 #define UVD_CGC_MEM_CTRL__WCB_LS_EN_MASK 0x00000008L
 149 #define UVD_CGC_MEM_CTRL__WCB_LS_EN__SHIFT 0x00000003
 150 #define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x00004000L
 151 #define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0x0000000e
 152 #define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x00008000L
 153 #define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0x0000000f
 154 #define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x00200000L
 155 #define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x00000015
 156 #define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x00400000L
 157 #define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x00000016
 158 #define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x00001000L
 159 #define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0x0000000c
 160 #define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x00002000L
 161 #define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0x0000000d
 162 #define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x00800000L
 163 #define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x00000017
 164 #define UVD_CGC_STATUS__MPC_DCLK_MASK 0x00100000L
 165 #define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x00000014
 166 #define UVD_CGC_STATUS__MPC_SCLK_MASK 0x00080000L
 167 #define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x00000013
 168 #define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x00000080L
 169 #define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x00000007
 170 #define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x00000040L
 171 #define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x00000006
 172 #define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x00000100L
 173 #define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x00000008
 174 #define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x00020000L
 175 #define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x00000011
 176 #define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x00010000L
 177 #define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x00000010
 178 #define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x00040000L
 179 #define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x00000012
 180 #define UVD_CGC_STATUS__RBC_SCLK_MASK 0x00000800L
 181 #define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0x0000000b
 182 #define UVD_CGC_STATUS__REGS_SCLK_MASK 0x00000200L
 183 #define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x00000009
 184 #define UVD_CGC_STATUS__REGS_VCLK_MASK 0x00000400L
 185 #define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0x0000000a
 186 #define UVD_CGC_STATUS__SCPU_SCLK_MASK 0x08000000L
 187 #define UVD_CGC_STATUS__SCPU_SCLK__SHIFT 0x0000001b
 188 #define UVD_CGC_STATUS__SCPU_VCLK_MASK 0x10000000L
 189 #define UVD_CGC_STATUS__SCPU_VCLK__SHIFT 0x0000001c
 190 #define UVD_CGC_STATUS__SYS_DCLK_MASK 0x00000002L
 191 #define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x00000001
 192 #define UVD_CGC_STATUS__SYS_SCLK_MASK 0x00000001L
 193 #define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x00000000
 194 #define UVD_CGC_STATUS__SYS_VCLK_MASK 0x00000004L
 195 #define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x00000002
 196 #define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x00000010L
 197 #define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x00000004
 198 #define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x00000008L
 199 #define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x00000003
 200 #define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x00000020L
 201 #define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x00000005
 202 #define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x02000000L
 203 #define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x00000019
 204 #define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x04000000L
 205 #define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x0000001a
 206 #define UVD_CGC_STATUS__WCB_SCLK_MASK 0x01000000L
 207 #define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x00000018
 208 #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x00000010L
 209 #define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x00000004
 210 #define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x00000008L
 211 #define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x00000003
 212 #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x00000020L
 213 #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x00000005
 214 #define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x00000400L
 215 #define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0x0000000a
 216 #define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x00000200L
 217 #define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x00000009
 218 #define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x00000800L
 219 #define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0x0000000b
 220 #define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x00000080L
 221 #define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x00000007
 222 #define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x00000040L
 223 #define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x00000006
 224 #define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x00000100L
 225 #define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x00000008
 226 #define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x00002000L
 227 #define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0x0000000d
 228 #define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x00001000L
 229 #define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0x0000000c
 230 #define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x00004000L
 231 #define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0x0000000e
 232 #define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x00000002L
 233 #define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x00000001
 234 #define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x00000001L
 235 #define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x00000000
 236 #define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x00000004L
 237 #define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x00000002
 238 #define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xffffffffL
 239 #define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x00000000
 240 #define UVD_CTX_DATA__DATA_MASK 0xffffffffL
 241 #define UVD_CTX_DATA__DATA__SHIFT 0x00000000
 242 #define UVD_CTX_INDEX__INDEX_MASK 0x000001ffL
 243 #define UVD_CTX_INDEX__INDEX__SHIFT 0x00000000
 244 #define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x00000001L
 245 #define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x00000002L
 246 #define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x00000001
 247 #define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x00000000
 248 #define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7ffffffeL
 249 #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x00000001L
 250 #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x00000000
 251 #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x00000001
 252 #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000L
 253 #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x0000001f
 254 #define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xffffffffL
 255 #define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x00000000
 256 #define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xffffffffL
 257 #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x00000000
 258 #define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT_MASK 0x0000000fL
 259 #define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT__SHIFT 0x00000000
 260 #define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT_MASK 0x00000f00L
 261 #define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT__SHIFT 0x00000008
 262 #define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT_MASK 0x0000f000L
 263 #define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT__SHIFT 0x0000000c
 264 #define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT_MASK 0x000000f0L
 265 #define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT__SHIFT 0x00000004
 266 #define UVD_LMI_ADDR_EXT__CM_ADDR_EXT_MASK 0x000000f0L
 267 #define UVD_LMI_ADDR_EXT__CM_ADDR_EXT__SHIFT 0x00000004
 268 #define UVD_LMI_ADDR_EXT__IT_ADDR_EXT_MASK 0x00000f00L
 269 #define UVD_LMI_ADDR_EXT__IT_ADDR_EXT__SHIFT 0x00000008
 270 #define UVD_LMI_ADDR_EXT__MP_ADDR_EXT_MASK 0x00f00000L
 271 #define UVD_LMI_ADDR_EXT__MP_ADDR_EXT__SHIFT 0x00000014
 272 #define UVD_LMI_ADDR_EXT__RE_ADDR_EXT_MASK 0x000f0000L
 273 #define UVD_LMI_ADDR_EXT__RE_ADDR_EXT__SHIFT 0x00000010
 274 #define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT_MASK 0x0000000fL
 275 #define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT__SHIFT 0x00000000
 276 #define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT_MASK 0x0f000000L
 277 #define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT__SHIFT 0x00000018
 278 #define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT_MASK 0xf0000000L
 279 #define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT__SHIFT 0x0000001c
 280 #define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT_MASK 0x0000f000L
 281 #define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT__SHIFT 0x0000000c
 282 #define UVD_LMI_CACHE_CTRL__CM_EN_MASK 0x00000004L
 283 #define UVD_LMI_CACHE_CTRL__CM_EN__SHIFT 0x00000002
 284 #define UVD_LMI_CACHE_CTRL__CM_FLUSH_MASK 0x00000008L
 285 #define UVD_LMI_CACHE_CTRL__CM_FLUSH__SHIFT 0x00000003
 286 #define UVD_LMI_CACHE_CTRL__IT_EN_MASK 0x00000001L
 287 #define UVD_LMI_CACHE_CTRL__IT_EN__SHIFT 0x00000000
 288 #define UVD_LMI_CACHE_CTRL__IT_FLUSH_MASK 0x00000002L
 289 #define UVD_LMI_CACHE_CTRL__IT_FLUSH__SHIFT 0x00000001
 290 #define UVD_LMI_CACHE_CTRL__VCPU_EN_MASK 0x00000010L
 291 #define UVD_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x00000004
 292 #define UVD_LMI_CACHE_CTRL__VCPU_FLUSH_MASK 0x00000020L
 293 #define UVD_LMI_CACHE_CTRL__VCPU_FLUSH__SHIFT 0x00000005
 294 #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L
 295 #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x00000002
 296 #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x00000080L
 297 #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x00000007
 298 #define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x00000008L
 299 #define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x00000003
 300 #define UVD_LMI_CTRL2__MCIF_WR_WATERMARK_MASK 0x00000070L
 301 #define UVD_LMI_CTRL2__MCIF_WR_WATERMARK__SHIFT 0x00000004
 302 #define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x00000600L
 303 #define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x00000009
 304 #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x00001800L
 305 #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0x0000000b
 306 #define UVD_LMI_CTRL2__SPH_DIS_MASK 0x00000001L
 307 #define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x00000000
 308 #define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x00008000L
 309 #define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0x0000000f
 310 #define UVD_LMI_CTRL2__STALL_ARB_MASK 0x00000002L
 311 #define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x00000001
 312 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L
 313 #define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x00000008
 314 #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x00002000L
 315 #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0x0000000d
 316 #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x00004000L
 317 #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0x0000000e
 318 #define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000800L
 319 #define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0x0000000b
 320 #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x00400000L
 321 #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x00000016
 322 #define UVD_LMI_CTRL__CRC_RESET_MASK 0x00004000L
 323 #define UVD_LMI_CTRL__CRC_RESET__SHIFT 0x0000000e
 324 #define UVD_LMI_CTRL__CRC_SEL_MASK 0x000f8000L
 325 #define UVD_LMI_CTRL__CRC_SEL__SHIFT 0x0000000f
 326 #define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x00002000L
 327 #define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0x0000000d
 328 #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x00800000L
 329 #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x00000017
 330 #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x01000000L
 331 #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x00000018
 332 #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x00100000L
 333 #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x00000014
 334 #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x02000000L
 335 #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x00000019
 336 #define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x00001000L
 337 #define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0x0000000c
 338 #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x04000000L
 339 #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x0000001a
 340 #define UVD_LMI_CTRL__REQ_MODE_MASK 0x00000200L
 341 #define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x00000009
 342 #define UVD_LMI_CTRL__RFU_MASK 0xf8000000L
 343 #define UVD_LMI_CTRL__RFU_MASK 0xfc000000L
 344 #define UVD_LMI_CTRL__RFU__SHIFT 0x0000001a
 345 #define UVD_LMI_CTRL__RFU__SHIFT 0x0000001b
 346 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L
 347 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x00000015
 348 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L
 349 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x00000008
 350 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0x000000ffL
 351 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x00000000
 352 #define UVD_LMI_EXT40_ADDR__ADDR_MASK 0x000000ffL
 353 #define UVD_LMI_EXT40_ADDR__ADDR__SHIFT 0x00000000
 354 #define UVD_LMI_EXT40_ADDR__INDEX_MASK 0x001f0000L
 355 #define UVD_LMI_EXT40_ADDR__INDEX__SHIFT 0x00000010
 356 #define UVD_LMI_EXT40_ADDR__WRITE_ADDR_MASK 0x80000000L
 357 #define UVD_LMI_EXT40_ADDR__WRITE_ADDR__SHIFT 0x0000001f
 358 #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x00001000L
 359 #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0x0000000c
 360 #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x00002000L
 361 #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0x0000000d
 362 #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x00000080L
 363 #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x00000007
 364 #define UVD_LMI_STATUS__READ_CLEAN_MASK 0x00000001L
 365 #define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x00000100L
 366 #define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x00000008
 367 #define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x00000000
 368 #define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x00000800L
 369 #define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0x0000000b
 370 #define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x00000010L
 371 #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x00000200L
 372 #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x00000009
 373 #define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x00000004
 374 #define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x00000400L
 375 #define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0x0000000a
 376 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x00000020L
 377 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x00000040L
 378 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x00000006
 379 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x00000005
 380 #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x00000008L
 381 #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x00000003
 382 #define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x00000002L
 383 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x00000004L
 384 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x00000002
 385 #define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x00000001
 386 #define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP_MASK 0x00000003L
 387 #define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP__SHIFT 0x00000000
 388 #define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP_MASK 0x0000000cL
 389 #define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP__SHIFT 0x00000002
 390 #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK 0x00000c00L
 391 #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0x0000000a
 392 #define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK 0x000c0000L
 393 #define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x00000012
 394 #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK 0x0000c000L
 395 #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0x0000000e
 396 #define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x00030000L
 397 #define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK 0x03000000L
 398 #define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x00000010
 399 #define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x00000018
 400 #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000cL
 401 #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x00000002
 402 #define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK 0x00003000L
 403 #define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT 0x0000000c
 404 #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xc0000000L
 405 #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x0000001e
 406 #define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK 0x00c00000L
 407 #define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT 0x00000016
 408 #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L
 409 #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x00000000
 410 #define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x00000030L
 411 #define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x00000004
 412 #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0x0c000000L
 413 #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x0000001a
 414 #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000L
 415 #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x0000001c
 416 #define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0x000000c0L
 417 #define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x00000006
 418 #define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x00000300L
 419 #define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x00000008
 420 #define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x007ffff0L
 421 #define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x00000004
 422 #define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L
 423 #define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x00000000
 424 #define UVD_MASTINT_EN__SYS_EN_MASK 0x00000004L
 425 #define UVD_MASTINT_EN__SYS_EN__SHIFT 0x00000002
 426 #define UVD_MASTINT_EN__VCPU_EN_MASK 0x00000002L
 427 #define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x00000001
 428 #define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
 429 #define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008
 430 #define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
 431 #define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018
 432 #define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L
 433 #define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014
 434 #define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
 435 #define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e
 436 #define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
 437 #define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000
 438 #define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L
 439 #define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c
 440 #define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L
 441 #define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004
 442 #define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
 443 #define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c
 444 #define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
 445 #define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010
 446 #define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
 447 #define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008
 448 #define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
 449 #define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018
 450 #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L
 451 #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014
 452 #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
 453 #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e
 454 #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
 455 #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000
 456 #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L
 457 #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c
 458 #define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L
 459 #define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004
 460 #define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
 461 #define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c
 462 #define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
 463 #define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010
 464 #define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
 465 #define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008
 466 #define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
 467 #define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018
 468 #define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L
 469 #define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014
 470 #define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
 471 #define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e
 472 #define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
 473 #define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000
 474 #define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L
 475 #define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c
 476 #define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L
 477 #define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004
 478 #define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
 479 #define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c
 480 #define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
 481 #define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010
 482 #define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x00030000L
 483 #define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x00000010
 484 #define UVD_MPC_CNTL__DBG_MUX_MASK 0x00000700L
 485 #define UVD_MPC_CNTL__DBG_MUX__SHIFT 0x00000008
 486 #define UVD_MPC_CNTL__PERF_RST_MASK 0x00000040L
 487 #define UVD_MPC_CNTL__PERF_RST__SHIFT 0x00000006
 488 #define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L
 489 #define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x00000003
 490 #define UVD_MPC_CNTL__URGENT_EN_MASK 0x00040000L
 491 #define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x00000012
 492 #define UVD_MPC_SET_ALU__FUNCT_MASK 0x00000007L
 493 #define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x00000000
 494 #define UVD_MPC_SET_ALU__OPERAND_MASK 0x00000ff0L
 495 #define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x00000004
 496 #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x0000003fL
 497 #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x00000000
 498 #define UVD_MPC_SET_MUXA0__VARA_1_MASK 0x00000fc0L
 499 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x00000006
 500 #define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x0003f000L
 501 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0x0000000c
 502 #define UVD_MPC_SET_MUXA0__VARA_3_MASK 0x00fc0000L
 503 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x00000012
 504 #define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3f000000L
 505 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x00000018
 506 #define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x0000003fL
 507 #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x00000000
 508 #define UVD_MPC_SET_MUXA1__VARA_6_MASK 0x00000fc0L
 509 #define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x00000006
 510 #define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x0003f000L
 511 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0x0000000c
 512 #define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x0000003fL
 513 #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x00000000
 514 #define UVD_MPC_SET_MUXB0__VARB_1_MASK 0x00000fc0L
 515 #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x00000006
 516 #define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x0003f000L
 517 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0x0000000c
 518 #define UVD_MPC_SET_MUXB0__VARB_3_MASK 0x00fc0000L
 519 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x00000012
 520 #define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3f000000L
 521 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x00000018
 522 #define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x0000003fL
 523 #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x00000000
 524 #define UVD_MPC_SET_MUXB1__VARB_6_MASK 0x00000fc0L
 525 #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x00000006
 526 #define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x0003f000L
 527 #define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0x0000000c
 528 #define UVD_MPC_SET_MUX__SET_0_MASK 0x00000007L
 529 #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x00000000
 530 #define UVD_MPC_SET_MUX__SET_1_MASK 0x00000038L
 531 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x00000003
 532 #define UVD_MPC_SET_MUX__SET_2_MASK 0x000001c0L
 533 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x00000006
 534 #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x00000003L
 535 #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x00000000
 536 #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x00300000L
 537 #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x00000014
 538 #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0x00c00000L
 539 #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x00000016
 540 #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x03000000L
 541 #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x00000018
 542 #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0x0c000000L
 543 #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x0000001a
 544 #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000L
 545 #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x0000001c
 546 #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xc0000000L
 547 #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x0000001e
 548 #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0x0000000cL
 549 #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x00000002
 550 #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x00000030L
 551 #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x00000004
 552 #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0x000000c0L
 553 #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x00000006
 554 #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x00000300L
 555 #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x00000008
 556 #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0x00000c00L
 557 #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0x0000000a
 558 #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x00003000L
 559 #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0x0000000c
 560 #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0x0000c000L
 561 #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0x0000000e
 562 #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x00030000L
 563 #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x00000010
 564 #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0x000c0000L
 565 #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x00000012
 566 #define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK 0x000000ffL
 567 #define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR__SHIFT 0x00000000
 568 #define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK 0x00000400L
 569 #define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT__SHIFT 0x0000000a
 570 #define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT_MASK 0x00000800L
 571 #define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT__SHIFT 0x0000000b
 572 #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK 0x00000100L
 573 #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN__SHIFT 0x00000008
 574 #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK 0x00000200L
 575 #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP__SHIFT 0x00000009
 576 #define UVD_PGFSM_CONFIG__UVD_PGFSM_READ_MASK 0x00002000L
 577 #define UVD_PGFSM_CONFIG__UVD_PGFSM_READ__SHIFT 0x0000000d
 578 #define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR_MASK 0xf0000000L
 579 #define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR__SHIFT 0x0000001c
 580 #define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE_MASK 0x00001000L
 581 #define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE__SHIFT 0x0000000c
 582 #define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE_MASK 0x00ffffffL
 583 #define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE__SHIFT 0x00000000
 584 #define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE_MASK 0x00ffffffL
 585 #define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE__SHIFT 0x00000000
 586 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000001L
 587 #define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x00000000
 588 #define UVD_RBC_IB_BASE__IB_BASE_MASK 0xffffffc0L
 589 #define UVD_RBC_IB_BASE__IB_BASE__SHIFT 0x00000006
 590 #define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x007ffff0L
 591 #define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x00000004
 592 #define UVD_RBC_RB_BASE__RB_BASE_MASK 0xffffffc0L
 593 #define UVD_RBC_RB_BASE__RB_BASE__SHIFT 0x00000006
 594 #define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x00001f00L
 595 #define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x00000008
 596 #define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x0000001fL
 597 #define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x00000000
 598 #define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x00010000L
 599 #define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x00000010
 600 #define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x01000000L
 601 #define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x00000018
 602 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000L
 603 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x0000001c
 604 #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x00100000L
 605 #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x00000014
 606 #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xffffffffL
 607 #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000000
 608 #define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x007ffff0L
 609 #define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x00000004
 610 #define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x007ffff0L
 611 #define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x00000004
 612 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0x000fffffL
 613 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x00000000
 614 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0x000fffffL
 615 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x00000000
 616 #define UVD_SEMA_CMD__MODE_MASK 0x00000040L
 617 #define UVD_SEMA_CMD__MODE__SHIFT 0x00000006
 618 #define UVD_SEMA_CMD__REQ_CMD_MASK 0x0000000fL
 619 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x00000000
 620 #define UVD_SEMA_CMD__VMID_EN_MASK 0x00000080L
 621 #define UVD_SEMA_CMD__VMID_EN__SHIFT 0x00000007
 622 #define UVD_SEMA_CMD__VMID_MASK 0x00000f00L
 623 #define UVD_SEMA_CMD__VMID__SHIFT 0x00000008
 624 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x00000030L
 625 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x00000004
 626 #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x00000002L
 627 #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x00000001
 628 #define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x00000001L
 629 #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x00000000
 630 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L
 631 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x00000018
 632 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x001ffffeL
 633 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x00000001
 634 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x00000001L
 635 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x00000000
 636 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000004L
 637 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x00000002
 638 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x00000008L
 639 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x00000003
 640 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x00000002L
 641 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x00000001
 642 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000001L
 643 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x00000000
 644 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L
 645 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x00000018
 646 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x001ffffeL
 647 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x00000001
 648 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x00000001L
 649 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x00000000
 650 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L
 651 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x00000018
 652 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x001ffffeL
 653 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x00000001
 654 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x00000001L
 655 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x00000000
 656 #define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK 0x00000020L
 657 #define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT 0x00000005
 658 #define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x00000040L
 659 #define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x00000006
 660 #define UVD_SOFT_RESET__FWV_SOFT_RESET_MASK 0x00000200L
 661 #define UVD_SOFT_RESET__FWV_SOFT_RESET__SHIFT 0x00000009
 662 #define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x00001000L
 663 #define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0x0000000c
 664 #define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x00000400L
 665 #define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0x0000000a
 666 #define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x00000002L
 667 #define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x00000001
 668 #define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x00010000L
 669 #define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x00000010
 670 #define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x00000004L
 671 #define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x00000002
 672 #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x00002000L
 673 #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0x0000000d
 674 #define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x00008000L
 675 #define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0x0000000f
 676 #define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x00000100L
 677 #define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x00000008
 678 #define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x00000800L
 679 #define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0x0000000b
 680 #define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x00000001L
 681 #define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x00000000
 682 #define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x00004000L
 683 #define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0x0000000e
 684 #define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000080L
 685 #define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x00000007
 686 #define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x00000010L
 687 #define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x00000004
 688 #define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x00000008L
 689 #define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x00000003
 690 #define UVD_STATUS__RBC_BUSY_MASK 0x00000001L
 691 #define UVD_STATUS__RBC_BUSY__SHIFT 0x00000000
 692 #define UVD_STATUS__VCPU_REPORT_MASK 0x000000feL
 693 #define UVD_STATUS__VCPU_REPORT__SHIFT 0x00000001
 694 #define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
 695 #define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008
 696 #define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
 697 #define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018
 698 #define UVD_UDEC_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L
 699 #define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014
 700 #define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
 701 #define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e
 702 #define UVD_UDEC_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
 703 #define UVD_UDEC_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000
 704 #define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L
 705 #define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c
 706 #define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L
 707 #define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004
 708 #define UVD_UDEC_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
 709 #define UVD_UDEC_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c
 710 #define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
 711 #define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010
 712 #define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
 713 #define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008
 714 #define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
 715 #define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018
 716 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L
 717 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014
 718 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
 719 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e
 720 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
 721 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000
 722 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L
 723 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c
 724 #define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L
 725 #define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004
 726 #define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
 727 #define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c
 728 #define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
 729 #define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010
 730 #define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
 731 #define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008
 732 #define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
 733 #define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018
 734 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L
 735 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014
 736 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
 737 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e
 738 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
 739 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000
 740 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L
 741 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c
 742 #define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L
 743 #define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004
 744 #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
 745 #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c
 746 #define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
 747 #define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010
 748 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x01ffffffL
 749 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x00000000
 750 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x01ffffffL
 751 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x00000000
 752 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x01ffffffL
 753 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x00000000
 754 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x001fffffL
 755 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x00000000
 756 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x001fffffL
 757 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x00000000
 758 #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x001fffffL
 759 #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x00000000
 760 #define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x00000100L
 761 #define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x00000008
 762 #define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4_MASK 0x00000010L
 763 #define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4__SHIFT 0x00000004
 764 #define UVD_VCPU_CNTL__CABAC_MB_ACC_MASK 0x10000000L
 765 #define UVD_VCPU_CNTL__CABAC_MB_ACC__SHIFT 0x0000001c
 766 #define UVD_VCPU_CNTL__CLK_ACTIVE_MASK 0x00020000L
 767 #define UVD_VCPU_CNTL__CLK_ACTIVE__SHIFT 0x00000011
 768 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L
 769 #define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x00000009
 770 #define UVD_VCPU_CNTL__DBG_MUX_MASK 0x0000e000L
 771 #define UVD_VCPU_CNTL__DBG_MUX__SHIFT 0x0000000d
 772 #define UVD_VCPU_CNTL__ECPU_AM32_EN_MASK 0x20000000L
 773 #define UVD_VCPU_CNTL__ECPU_AM32_EN__SHIFT 0x0000001d
 774 #define UVD_VCPU_CNTL__IRQ_ERR_MASK 0x0000000fL
 775 #define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x00000000
 776 #define UVD_VCPU_CNTL__JTAG_EN_MASK 0x00010000L
 777 #define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x00000010
 778 #define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x00000020L
 779 #define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x00000005
 780 #define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x00000040L
 781 #define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x00000006
 782 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0x0ff00000L
 783 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x00000014
 784 #define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x00000080L
 785 #define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x00000007
 786 #define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x00040000L
 787 #define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x00000012
 788 #define UVD_VCPU_CNTL__TRCE_EN_MASK 0x00000400L
 789 #define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0x0000000a
 790 #define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x00001800L
 791 #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0x0000000b
 792 #define UVD_VCPU_CNTL__WMV9_EN_MASK 0x40000000L
 793 #define UVD_VCPU_CNTL__WMV9_EN__SHIFT 0x0000001e
 794 
 795 #endif
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h
