1 /*
2 * UVD_5_0 Register documentation
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #ifndef UVD_5_0_ENUM_H
25 #define UVD_5_0_ENUM_H
26
27 typedef enum UVDFirmwareCommand {
28 UVDFC_FENCE = 0x0,
29 UVDFC_TRAP = 0x1,
30 UVDFC_DECODED_ADDR = 0x2,
31 UVDFC_MBLOCK_ADDR = 0x3,
32 UVDFC_ITBUF_ADDR = 0x4,
33 UVDFC_DISPLAY_ADDR = 0x5,
34 UVDFC_EOD = 0x6,
35 UVDFC_DISPLAY_PITCH = 0x7,
36 UVDFC_DISPLAY_TILING = 0x8,
37 UVDFC_BITSTREAM_ADDR = 0x9,
38 UVDFC_BITSTREAM_SIZE = 0xa,
39 } UVDFirmwareCommand;
40 typedef enum SurfaceEndian {
41 ENDIAN_NONE = 0x0,
42 ENDIAN_8IN16 = 0x1,
43 ENDIAN_8IN32 = 0x2,
44 ENDIAN_8IN64 = 0x3,
45 } SurfaceEndian;
46 typedef enum ArrayMode {
47 ARRAY_LINEAR_GENERAL = 0x0,
48 ARRAY_LINEAR_ALIGNED = 0x1,
49 ARRAY_1D_TILED_THIN1 = 0x2,
50 ARRAY_1D_TILED_THICK = 0x3,
51 ARRAY_2D_TILED_THIN1 = 0x4,
52 ARRAY_PRT_TILED_THIN1 = 0x5,
53 ARRAY_PRT_2D_TILED_THIN1 = 0x6,
54 ARRAY_2D_TILED_THICK = 0x7,
55 ARRAY_2D_TILED_XTHICK = 0x8,
56 ARRAY_PRT_TILED_THICK = 0x9,
57 ARRAY_PRT_2D_TILED_THICK = 0xa,
58 ARRAY_PRT_3D_TILED_THIN1 = 0xb,
59 ARRAY_3D_TILED_THIN1 = 0xc,
60 ARRAY_3D_TILED_THICK = 0xd,
61 ARRAY_3D_TILED_XTHICK = 0xe,
62 ARRAY_PRT_3D_TILED_THICK = 0xf,
63 } ArrayMode;
64 typedef enum PipeTiling {
65 CONFIG_1_PIPE = 0x0,
66 CONFIG_2_PIPE = 0x1,
67 CONFIG_4_PIPE = 0x2,
68 CONFIG_8_PIPE = 0x3,
69 } PipeTiling;
70 typedef enum BankTiling {
71 CONFIG_4_BANK = 0x0,
72 CONFIG_8_BANK = 0x1,
73 } BankTiling;
74 typedef enum GroupInterleave {
75 CONFIG_256B_GROUP = 0x0,
76 CONFIG_512B_GROUP = 0x1,
77 } GroupInterleave;
78 typedef enum RowTiling {
79 CONFIG_1KB_ROW = 0x0,
80 CONFIG_2KB_ROW = 0x1,
81 CONFIG_4KB_ROW = 0x2,
82 CONFIG_8KB_ROW = 0x3,
83 CONFIG_1KB_ROW_OPT = 0x4,
84 CONFIG_2KB_ROW_OPT = 0x5,
85 CONFIG_4KB_ROW_OPT = 0x6,
86 CONFIG_8KB_ROW_OPT = 0x7,
87 } RowTiling;
88 typedef enum BankSwapBytes {
89 CONFIG_128B_SWAPS = 0x0,
90 CONFIG_256B_SWAPS = 0x1,
91 CONFIG_512B_SWAPS = 0x2,
92 CONFIG_1KB_SWAPS = 0x3,
93 } BankSwapBytes;
94 typedef enum SampleSplitBytes {
95 CONFIG_1KB_SPLIT = 0x0,
96 CONFIG_2KB_SPLIT = 0x1,
97 CONFIG_4KB_SPLIT = 0x2,
98 CONFIG_8KB_SPLIT = 0x3,
99 } SampleSplitBytes;
100 typedef enum NumPipes {
101 ADDR_CONFIG_1_PIPE = 0x0,
102 ADDR_CONFIG_2_PIPE = 0x1,
103 ADDR_CONFIG_4_PIPE = 0x2,
104 ADDR_CONFIG_8_PIPE = 0x3,
105 } NumPipes;
106 typedef enum PipeInterleaveSize {
107 ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
108 ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
109 } PipeInterleaveSize;
110 typedef enum BankInterleaveSize {
111 ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
112 ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
113 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
114 ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
115 } BankInterleaveSize;
116 typedef enum NumShaderEngines {
117 ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
118 ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
119 } NumShaderEngines;
120 typedef enum ShaderEngineTileSize {
121 ADDR_CONFIG_SE_TILE_16 = 0x0,
122 ADDR_CONFIG_SE_TILE_32 = 0x1,
123 } ShaderEngineTileSize;
124 typedef enum NumGPUs {
125 ADDR_CONFIG_1_GPU = 0x0,
126 ADDR_CONFIG_2_GPU = 0x1,
127 ADDR_CONFIG_4_GPU = 0x2,
128 } NumGPUs;
129 typedef enum MultiGPUTileSize {
130 ADDR_CONFIG_GPU_TILE_16 = 0x0,
131 ADDR_CONFIG_GPU_TILE_32 = 0x1,
132 ADDR_CONFIG_GPU_TILE_64 = 0x2,
133 ADDR_CONFIG_GPU_TILE_128 = 0x3,
134 } MultiGPUTileSize;
135 typedef enum RowSize {
136 ADDR_CONFIG_1KB_ROW = 0x0,
137 ADDR_CONFIG_2KB_ROW = 0x1,
138 ADDR_CONFIG_4KB_ROW = 0x2,
139 } RowSize;
140 typedef enum NumLowerPipes {
141 ADDR_CONFIG_1_LOWER_PIPES = 0x0,
142 ADDR_CONFIG_2_LOWER_PIPES = 0x1,
143 } NumLowerPipes;
144 typedef enum DebugBlockId {
145 DBG_CLIENT_BLKID_RESERVED = 0x0,
146 DBG_CLIENT_BLKID_dbg = 0x1,
147 DBG_CLIENT_BLKID_scf2 = 0x2,
148 DBG_CLIENT_BLKID_mcd5 = 0x3,
149 DBG_CLIENT_BLKID_vmc = 0x4,
150 DBG_CLIENT_BLKID_sx30 = 0x5,
151 DBG_CLIENT_BLKID_mcd2 = 0x6,
152 DBG_CLIENT_BLKID_bci1 = 0x7,
153 DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0x8,
154 DBG_CLIENT_BLKID_mcc0 = 0x9,
155 DBG_CLIENT_BLKID_uvdf_0 = 0xa,
156 DBG_CLIENT_BLKID_uvdf_1 = 0xb,
157 DBG_CLIENT_BLKID_uvdf_2 = 0xc,
158 DBG_CLIENT_BLKID_uvdi_0 = 0xd,
159 DBG_CLIENT_BLKID_bci0 = 0xe,
160 DBG_CLIENT_BLKID_vcec0_0 = 0xf,
161 DBG_CLIENT_BLKID_cb100 = 0x10,
162 DBG_CLIENT_BLKID_cb001 = 0x11,
163 DBG_CLIENT_BLKID_mcd4 = 0x12,
164 DBG_CLIENT_BLKID_tmonw00 = 0x13,
165 DBG_CLIENT_BLKID_cb101 = 0x14,
166 DBG_CLIENT_BLKID_sx10 = 0x15,
167 DBG_CLIENT_BLKID_cb301 = 0x16,
168 DBG_CLIENT_BLKID_tmonw01 = 0x17,
169 DBG_CLIENT_BLKID_vcea0_0 = 0x18,
170 DBG_CLIENT_BLKID_vcea0_1 = 0x19,
171 DBG_CLIENT_BLKID_vcea0_2 = 0x1a,
172 DBG_CLIENT_BLKID_vcea0_3 = 0x1b,
173 DBG_CLIENT_BLKID_scf1 = 0x1c,
174 DBG_CLIENT_BLKID_sx20 = 0x1d,
175 DBG_CLIENT_BLKID_spim1 = 0x1e,
176 DBG_CLIENT_BLKID_pa10 = 0x1f,
177 DBG_CLIENT_BLKID_pa00 = 0x20,
178 DBG_CLIENT_BLKID_gmcon = 0x21,
179 DBG_CLIENT_BLKID_mcb = 0x22,
180 DBG_CLIENT_BLKID_vgt0 = 0x23,
181 DBG_CLIENT_BLKID_pc0 = 0x24,
182 DBG_CLIENT_BLKID_bci2 = 0x25,
183 DBG_CLIENT_BLKID_uvdb_0 = 0x26,
184 DBG_CLIENT_BLKID_spim3 = 0x27,
185 DBG_CLIENT_BLKID_cpc_0 = 0x28,
186 DBG_CLIENT_BLKID_cpc_1 = 0x29,
187 DBG_CLIENT_BLKID_uvdm_0 = 0x2a,
188 DBG_CLIENT_BLKID_uvdm_1 = 0x2b,
189 DBG_CLIENT_BLKID_uvdm_2 = 0x2c,
190 DBG_CLIENT_BLKID_uvdm_3 = 0x2d,
191 DBG_CLIENT_BLKID_cb000 = 0x2e,
192 DBG_CLIENT_BLKID_spim0 = 0x2f,
193 DBG_CLIENT_BLKID_mcc2 = 0x30,
194 DBG_CLIENT_BLKID_ds0 = 0x31,
195 DBG_CLIENT_BLKID_srbm = 0x32,
196 DBG_CLIENT_BLKID_ih = 0x33,
197 DBG_CLIENT_BLKID_sem = 0x34,
198 DBG_CLIENT_BLKID_sdma_0 = 0x35,
199 DBG_CLIENT_BLKID_sdma_1 = 0x36,
200 DBG_CLIENT_BLKID_hdp = 0x37,
201 DBG_CLIENT_BLKID_acp_0 = 0x38,
202 DBG_CLIENT_BLKID_acp_1 = 0x39,
203 DBG_CLIENT_BLKID_cb200 = 0x3a,
204 DBG_CLIENT_BLKID_scf3 = 0x3b,
205 DBG_CLIENT_BLKID_vceb1_0 = 0x3c,
206 DBG_CLIENT_BLKID_vcea1_0 = 0x3d,
207 DBG_CLIENT_BLKID_vcea1_1 = 0x3e,
208 DBG_CLIENT_BLKID_vcea1_2 = 0x3f,
209 DBG_CLIENT_BLKID_vcea1_3 = 0x40,
210 DBG_CLIENT_BLKID_bci3 = 0x41,
211 DBG_CLIENT_BLKID_mcd0 = 0x42,
212 DBG_CLIENT_BLKID_pa11 = 0x43,
213 DBG_CLIENT_BLKID_pa01 = 0x44,
214 DBG_CLIENT_BLKID_cb201 = 0x45,
215 DBG_CLIENT_BLKID_spim2 = 0x46,
216 DBG_CLIENT_BLKID_vgt2 = 0x47,
217 DBG_CLIENT_BLKID_pc2 = 0x48,
218 DBG_CLIENT_BLKID_smu_0 = 0x49,
219 DBG_CLIENT_BLKID_smu_1 = 0x4a,
220 DBG_CLIENT_BLKID_smu_2 = 0x4b,
221 DBG_CLIENT_BLKID_cb1 = 0x4c,
222 DBG_CLIENT_BLKID_ia0 = 0x4d,
223 DBG_CLIENT_BLKID_wd = 0x4e,
224 DBG_CLIENT_BLKID_ia1 = 0x4f,
225 DBG_CLIENT_BLKID_vcec1_0 = 0x50,
226 DBG_CLIENT_BLKID_scf0 = 0x51,
227 DBG_CLIENT_BLKID_vgt1 = 0x52,
228 DBG_CLIENT_BLKID_pc1 = 0x53,
229 DBG_CLIENT_BLKID_cb0 = 0x54,
230 DBG_CLIENT_BLKID_gdc_one_0 = 0x55,
231 DBG_CLIENT_BLKID_gdc_one_1 = 0x56,
232 DBG_CLIENT_BLKID_gdc_one_2 = 0x57,
233 DBG_CLIENT_BLKID_gdc_one_3 = 0x58,
234 DBG_CLIENT_BLKID_gdc_one_4 = 0x59,
235 DBG_CLIENT_BLKID_gdc_one_5 = 0x5a,
236 DBG_CLIENT_BLKID_gdc_one_6 = 0x5b,
237 DBG_CLIENT_BLKID_gdc_one_7 = 0x5c,
238 DBG_CLIENT_BLKID_gdc_one_8 = 0x5d,
239 DBG_CLIENT_BLKID_gdc_one_9 = 0x5e,
240 DBG_CLIENT_BLKID_gdc_one_10 = 0x5f,
241 DBG_CLIENT_BLKID_gdc_one_11 = 0x60,
242 DBG_CLIENT_BLKID_gdc_one_12 = 0x61,
243 DBG_CLIENT_BLKID_gdc_one_13 = 0x62,
244 DBG_CLIENT_BLKID_gdc_one_14 = 0x63,
245 DBG_CLIENT_BLKID_gdc_one_15 = 0x64,
246 DBG_CLIENT_BLKID_gdc_one_16 = 0x65,
247 DBG_CLIENT_BLKID_gdc_one_17 = 0x66,
248 DBG_CLIENT_BLKID_gdc_one_18 = 0x67,
249 DBG_CLIENT_BLKID_gdc_one_19 = 0x68,
250 DBG_CLIENT_BLKID_gdc_one_20 = 0x69,
251 DBG_CLIENT_BLKID_gdc_one_21 = 0x6a,
252 DBG_CLIENT_BLKID_gdc_one_22 = 0x6b,
253 DBG_CLIENT_BLKID_gdc_one_23 = 0x6c,
254 DBG_CLIENT_BLKID_gdc_one_24 = 0x6d,
255 DBG_CLIENT_BLKID_gdc_one_25 = 0x6e,
256 DBG_CLIENT_BLKID_gdc_one_26 = 0x6f,
257 DBG_CLIENT_BLKID_gdc_one_27 = 0x70,
258 DBG_CLIENT_BLKID_gdc_one_28 = 0x71,
259 DBG_CLIENT_BLKID_gdc_one_29 = 0x72,
260 DBG_CLIENT_BLKID_gdc_one_30 = 0x73,
261 DBG_CLIENT_BLKID_gdc_one_31 = 0x74,
262 DBG_CLIENT_BLKID_gdc_one_32 = 0x75,
263 DBG_CLIENT_BLKID_gdc_one_33 = 0x76,
264 DBG_CLIENT_BLKID_gdc_one_34 = 0x77,
265 DBG_CLIENT_BLKID_gdc_one_35 = 0x78,
266 DBG_CLIENT_BLKID_vceb0_0 = 0x79,
267 DBG_CLIENT_BLKID_vgt3 = 0x7a,
268 DBG_CLIENT_BLKID_pc3 = 0x7b,
269 DBG_CLIENT_BLKID_mcd3 = 0x7c,
270 DBG_CLIENT_BLKID_uvdu_0 = 0x7d,
271 DBG_CLIENT_BLKID_uvdu_1 = 0x7e,
272 DBG_CLIENT_BLKID_uvdu_2 = 0x7f,
273 DBG_CLIENT_BLKID_uvdu_3 = 0x80,
274 DBG_CLIENT_BLKID_uvdu_4 = 0x81,
275 DBG_CLIENT_BLKID_uvdu_5 = 0x82,
276 DBG_CLIENT_BLKID_uvdu_6 = 0x83,
277 DBG_CLIENT_BLKID_cb300 = 0x84,
278 DBG_CLIENT_BLKID_mcd1 = 0x85,
279 DBG_CLIENT_BLKID_sx00 = 0x86,
280 DBG_CLIENT_BLKID_uvdc_0 = 0x87,
281 DBG_CLIENT_BLKID_uvdc_1 = 0x88,
282 DBG_CLIENT_BLKID_mcc3 = 0x89,
283 DBG_CLIENT_BLKID_cpg_0 = 0x8a,
284 DBG_CLIENT_BLKID_cpg_1 = 0x8b,
285 DBG_CLIENT_BLKID_gck = 0x8c,
286 DBG_CLIENT_BLKID_mcc1 = 0x8d,
287 DBG_CLIENT_BLKID_cpf_0 = 0x8e,
288 DBG_CLIENT_BLKID_cpf_1 = 0x8f,
289 DBG_CLIENT_BLKID_rlc = 0x90,
290 DBG_CLIENT_BLKID_grbm = 0x91,
291 DBG_CLIENT_BLKID_sammsp = 0x92,
292 DBG_CLIENT_BLKID_dci_pg = 0x93,
293 DBG_CLIENT_BLKID_dci_0 = 0x94,
294 DBG_CLIENT_BLKID_dccg0_0 = 0x95,
295 DBG_CLIENT_BLKID_dccg0_1 = 0x96,
296 DBG_CLIENT_BLKID_dcfe01_0 = 0x97,
297 DBG_CLIENT_BLKID_dcfe02_0 = 0x98,
298 DBG_CLIENT_BLKID_dcfe03_0 = 0x99,
299 DBG_CLIENT_BLKID_dcfe04_0 = 0x9a,
300 DBG_CLIENT_BLKID_dcfe05_0 = 0x9b,
301 DBG_CLIENT_BLKID_dcfe06_0 = 0x9c,
302 DBG_CLIENT_BLKID_RESERVED_LAST = 0x9d,
303 } DebugBlockId;
304 typedef enum DebugBlockId_OLD {
305 DBG_BLOCK_ID_RESERVED = 0x0,
306 DBG_BLOCK_ID_DBG = 0x1,
307 DBG_BLOCK_ID_VMC = 0x2,
308 DBG_BLOCK_ID_PDMA = 0x3,
309 DBG_BLOCK_ID_CG = 0x4,
310 DBG_BLOCK_ID_SRBM = 0x5,
311 DBG_BLOCK_ID_GRBM = 0x6,
312 DBG_BLOCK_ID_RLC = 0x7,
313 DBG_BLOCK_ID_CSC = 0x8,
314 DBG_BLOCK_ID_SEM = 0x9,
315 DBG_BLOCK_ID_IH = 0xa,
316 DBG_BLOCK_ID_SC = 0xb,
317 DBG_BLOCK_ID_SQ = 0xc,
318 DBG_BLOCK_ID_AVP = 0xd,
319 DBG_BLOCK_ID_GMCON = 0xe,
320 DBG_BLOCK_ID_SMU = 0xf,
321 DBG_BLOCK_ID_DMA0 = 0x10,
322 DBG_BLOCK_ID_DMA1 = 0x11,
323 DBG_BLOCK_ID_SPIM = 0x12,
324 DBG_BLOCK_ID_GDS = 0x13,
325 DBG_BLOCK_ID_SPIS = 0x14,
326 DBG_BLOCK_ID_UNUSED0 = 0x15,
327 DBG_BLOCK_ID_PA0 = 0x16,
328 DBG_BLOCK_ID_PA1 = 0x17,
329 DBG_BLOCK_ID_CP0 = 0x18,
330 DBG_BLOCK_ID_CP1 = 0x19,
331 DBG_BLOCK_ID_CP2 = 0x1a,
332 DBG_BLOCK_ID_UNUSED1 = 0x1b,
333 DBG_BLOCK_ID_UVDU = 0x1c,
334 DBG_BLOCK_ID_UVDM = 0x1d,
335 DBG_BLOCK_ID_VCE = 0x1e,
336 DBG_BLOCK_ID_UNUSED2 = 0x1f,
337 DBG_BLOCK_ID_VGT0 = 0x20,
338 DBG_BLOCK_ID_VGT1 = 0x21,
339 DBG_BLOCK_ID_IA = 0x22,
340 DBG_BLOCK_ID_UNUSED3 = 0x23,
341 DBG_BLOCK_ID_SCT0 = 0x24,
342 DBG_BLOCK_ID_SCT1 = 0x25,
343 DBG_BLOCK_ID_SPM0 = 0x26,
344 DBG_BLOCK_ID_SPM1 = 0x27,
345 DBG_BLOCK_ID_TCAA = 0x28,
346 DBG_BLOCK_ID_TCAB = 0x29,
347 DBG_BLOCK_ID_TCCA = 0x2a,
348 DBG_BLOCK_ID_TCCB = 0x2b,
349 DBG_BLOCK_ID_MCC0 = 0x2c,
350 DBG_BLOCK_ID_MCC1 = 0x2d,
351 DBG_BLOCK_ID_MCC2 = 0x2e,
352 DBG_BLOCK_ID_MCC3 = 0x2f,
353 DBG_BLOCK_ID_SX0 = 0x30,
354 DBG_BLOCK_ID_SX1 = 0x31,
355 DBG_BLOCK_ID_SX2 = 0x32,
356 DBG_BLOCK_ID_SX3 = 0x33,
357 DBG_BLOCK_ID_UNUSED4 = 0x34,
358 DBG_BLOCK_ID_UNUSED5 = 0x35,
359 DBG_BLOCK_ID_UNUSED6 = 0x36,
360 DBG_BLOCK_ID_UNUSED7 = 0x37,
361 DBG_BLOCK_ID_PC0 = 0x38,
362 DBG_BLOCK_ID_PC1 = 0x39,
363 DBG_BLOCK_ID_UNUSED8 = 0x3a,
364 DBG_BLOCK_ID_UNUSED9 = 0x3b,
365 DBG_BLOCK_ID_UNUSED10 = 0x3c,
366 DBG_BLOCK_ID_UNUSED11 = 0x3d,
367 DBG_BLOCK_ID_MCB = 0x3e,
368 DBG_BLOCK_ID_UNUSED12 = 0x3f,
369 DBG_BLOCK_ID_SCB0 = 0x40,
370 DBG_BLOCK_ID_SCB1 = 0x41,
371 DBG_BLOCK_ID_UNUSED13 = 0x42,
372 DBG_BLOCK_ID_UNUSED14 = 0x43,
373 DBG_BLOCK_ID_SCF0 = 0x44,
374 DBG_BLOCK_ID_SCF1 = 0x45,
375 DBG_BLOCK_ID_UNUSED15 = 0x46,
376 DBG_BLOCK_ID_UNUSED16 = 0x47,
377 DBG_BLOCK_ID_BCI0 = 0x48,
378 DBG_BLOCK_ID_BCI1 = 0x49,
379 DBG_BLOCK_ID_BCI2 = 0x4a,
380 DBG_BLOCK_ID_BCI3 = 0x4b,
381 DBG_BLOCK_ID_UNUSED17 = 0x4c,
382 DBG_BLOCK_ID_UNUSED18 = 0x4d,
383 DBG_BLOCK_ID_UNUSED19 = 0x4e,
384 DBG_BLOCK_ID_UNUSED20 = 0x4f,
385 DBG_BLOCK_ID_CB00 = 0x50,
386 DBG_BLOCK_ID_CB01 = 0x51,
387 DBG_BLOCK_ID_CB02 = 0x52,
388 DBG_BLOCK_ID_CB03 = 0x53,
389 DBG_BLOCK_ID_CB04 = 0x54,
390 DBG_BLOCK_ID_UNUSED21 = 0x55,
391 DBG_BLOCK_ID_UNUSED22 = 0x56,
392 DBG_BLOCK_ID_UNUSED23 = 0x57,
393 DBG_BLOCK_ID_CB10 = 0x58,
394 DBG_BLOCK_ID_CB11 = 0x59,
395 DBG_BLOCK_ID_CB12 = 0x5a,
396 DBG_BLOCK_ID_CB13 = 0x5b,
397 DBG_BLOCK_ID_CB14 = 0x5c,
398 DBG_BLOCK_ID_UNUSED24 = 0x5d,
399 DBG_BLOCK_ID_UNUSED25 = 0x5e,
400 DBG_BLOCK_ID_UNUSED26 = 0x5f,
401 DBG_BLOCK_ID_TCP0 = 0x60,
402 DBG_BLOCK_ID_TCP1 = 0x61,
403 DBG_BLOCK_ID_TCP2 = 0x62,
404 DBG_BLOCK_ID_TCP3 = 0x63,
405 DBG_BLOCK_ID_TCP4 = 0x64,
406 DBG_BLOCK_ID_TCP5 = 0x65,
407 DBG_BLOCK_ID_TCP6 = 0x66,
408 DBG_BLOCK_ID_TCP7 = 0x67,
409 DBG_BLOCK_ID_TCP8 = 0x68,
410 DBG_BLOCK_ID_TCP9 = 0x69,
411 DBG_BLOCK_ID_TCP10 = 0x6a,
412 DBG_BLOCK_ID_TCP11 = 0x6b,
413 DBG_BLOCK_ID_TCP12 = 0x6c,
414 DBG_BLOCK_ID_TCP13 = 0x6d,
415 DBG_BLOCK_ID_TCP14 = 0x6e,
416 DBG_BLOCK_ID_TCP15 = 0x6f,
417 DBG_BLOCK_ID_TCP16 = 0x70,
418 DBG_BLOCK_ID_TCP17 = 0x71,
419 DBG_BLOCK_ID_TCP18 = 0x72,
420 DBG_BLOCK_ID_TCP19 = 0x73,
421 DBG_BLOCK_ID_TCP20 = 0x74,
422 DBG_BLOCK_ID_TCP21 = 0x75,
423 DBG_BLOCK_ID_TCP22 = 0x76,
424 DBG_BLOCK_ID_TCP23 = 0x77,
425 DBG_BLOCK_ID_TCP_RESERVED0 = 0x78,
426 DBG_BLOCK_ID_TCP_RESERVED1 = 0x79,
427 DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a,
428 DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b,
429 DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c,
430 DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d,
431 DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e,
432 DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f,
433 DBG_BLOCK_ID_DB00 = 0x80,
434 DBG_BLOCK_ID_DB01 = 0x81,
435 DBG_BLOCK_ID_DB02 = 0x82,
436 DBG_BLOCK_ID_DB03 = 0x83,
437 DBG_BLOCK_ID_DB04 = 0x84,
438 DBG_BLOCK_ID_UNUSED27 = 0x85,
439 DBG_BLOCK_ID_UNUSED28 = 0x86,
440 DBG_BLOCK_ID_UNUSED29 = 0x87,
441 DBG_BLOCK_ID_DB10 = 0x88,
442 DBG_BLOCK_ID_DB11 = 0x89,
443 DBG_BLOCK_ID_DB12 = 0x8a,
444 DBG_BLOCK_ID_DB13 = 0x8b,
445 DBG_BLOCK_ID_DB14 = 0x8c,
446 DBG_BLOCK_ID_UNUSED30 = 0x8d,
447 DBG_BLOCK_ID_UNUSED31 = 0x8e,
448 DBG_BLOCK_ID_UNUSED32 = 0x8f,
449 DBG_BLOCK_ID_TCC0 = 0x90,
450 DBG_BLOCK_ID_TCC1 = 0x91,
451 DBG_BLOCK_ID_TCC2 = 0x92,
452 DBG_BLOCK_ID_TCC3 = 0x93,
453 DBG_BLOCK_ID_TCC4 = 0x94,
454 DBG_BLOCK_ID_TCC5 = 0x95,
455 DBG_BLOCK_ID_TCC6 = 0x96,
456 DBG_BLOCK_ID_TCC7 = 0x97,
457 DBG_BLOCK_ID_SPS00 = 0x98,
458 DBG_BLOCK_ID_SPS01 = 0x99,
459 DBG_BLOCK_ID_SPS02 = 0x9a,
460 DBG_BLOCK_ID_SPS10 = 0x9b,
461 DBG_BLOCK_ID_SPS11 = 0x9c,
462 DBG_BLOCK_ID_SPS12 = 0x9d,
463 DBG_BLOCK_ID_UNUSED33 = 0x9e,
464 DBG_BLOCK_ID_UNUSED34 = 0x9f,
465 DBG_BLOCK_ID_TA00 = 0xa0,
466 DBG_BLOCK_ID_TA01 = 0xa1,
467 DBG_BLOCK_ID_TA02 = 0xa2,
468 DBG_BLOCK_ID_TA03 = 0xa3,
469 DBG_BLOCK_ID_TA04 = 0xa4,
470 DBG_BLOCK_ID_TA05 = 0xa5,
471 DBG_BLOCK_ID_TA06 = 0xa6,
472 DBG_BLOCK_ID_TA07 = 0xa7,
473 DBG_BLOCK_ID_TA08 = 0xa8,
474 DBG_BLOCK_ID_TA09 = 0xa9,
475 DBG_BLOCK_ID_TA0A = 0xaa,
476 DBG_BLOCK_ID_TA0B = 0xab,
477 DBG_BLOCK_ID_UNUSED35 = 0xac,
478 DBG_BLOCK_ID_UNUSED36 = 0xad,
479 DBG_BLOCK_ID_UNUSED37 = 0xae,
480 DBG_BLOCK_ID_UNUSED38 = 0xaf,
481 DBG_BLOCK_ID_TA10 = 0xb0,
482 DBG_BLOCK_ID_TA11 = 0xb1,
483 DBG_BLOCK_ID_TA12 = 0xb2,
484 DBG_BLOCK_ID_TA13 = 0xb3,
485 DBG_BLOCK_ID_TA14 = 0xb4,
486 DBG_BLOCK_ID_TA15 = 0xb5,
487 DBG_BLOCK_ID_TA16 = 0xb6,
488 DBG_BLOCK_ID_TA17 = 0xb7,
489 DBG_BLOCK_ID_TA18 = 0xb8,
490 DBG_BLOCK_ID_TA19 = 0xb9,
491 DBG_BLOCK_ID_TA1A = 0xba,
492 DBG_BLOCK_ID_TA1B = 0xbb,
493 DBG_BLOCK_ID_UNUSED39 = 0xbc,
494 DBG_BLOCK_ID_UNUSED40 = 0xbd,
495 DBG_BLOCK_ID_UNUSED41 = 0xbe,
496 DBG_BLOCK_ID_UNUSED42 = 0xbf,
497 DBG_BLOCK_ID_TD00 = 0xc0,
498 DBG_BLOCK_ID_TD01 = 0xc1,
499 DBG_BLOCK_ID_TD02 = 0xc2,
500 DBG_BLOCK_ID_TD03 = 0xc3,
501 DBG_BLOCK_ID_TD04 = 0xc4,
502 DBG_BLOCK_ID_TD05 = 0xc5,
503 DBG_BLOCK_ID_TD06 = 0xc6,
504 DBG_BLOCK_ID_TD07 = 0xc7,
505 DBG_BLOCK_ID_TD08 = 0xc8,
506 DBG_BLOCK_ID_TD09 = 0xc9,
507 DBG_BLOCK_ID_TD0A = 0xca,
508 DBG_BLOCK_ID_TD0B = 0xcb,
509 DBG_BLOCK_ID_UNUSED43 = 0xcc,
510 DBG_BLOCK_ID_UNUSED44 = 0xcd,
511 DBG_BLOCK_ID_UNUSED45 = 0xce,
512 DBG_BLOCK_ID_UNUSED46 = 0xcf,
513 DBG_BLOCK_ID_TD10 = 0xd0,
514 DBG_BLOCK_ID_TD11 = 0xd1,
515 DBG_BLOCK_ID_TD12 = 0xd2,
516 DBG_BLOCK_ID_TD13 = 0xd3,
517 DBG_BLOCK_ID_TD14 = 0xd4,
518 DBG_BLOCK_ID_TD15 = 0xd5,
519 DBG_BLOCK_ID_TD16 = 0xd6,
520 DBG_BLOCK_ID_TD17 = 0xd7,
521 DBG_BLOCK_ID_TD18 = 0xd8,
522 DBG_BLOCK_ID_TD19 = 0xd9,
523 DBG_BLOCK_ID_TD1A = 0xda,
524 DBG_BLOCK_ID_TD1B = 0xdb,
525 DBG_BLOCK_ID_UNUSED47 = 0xdc,
526 DBG_BLOCK_ID_UNUSED48 = 0xdd,
527 DBG_BLOCK_ID_UNUSED49 = 0xde,
528 DBG_BLOCK_ID_UNUSED50 = 0xdf,
529 DBG_BLOCK_ID_MCD0 = 0xe0,
530 DBG_BLOCK_ID_MCD1 = 0xe1,
531 DBG_BLOCK_ID_MCD2 = 0xe2,
532 DBG_BLOCK_ID_MCD3 = 0xe3,
533 DBG_BLOCK_ID_MCD4 = 0xe4,
534 DBG_BLOCK_ID_MCD5 = 0xe5,
535 DBG_BLOCK_ID_UNUSED51 = 0xe6,
536 DBG_BLOCK_ID_UNUSED52 = 0xe7,
537 } DebugBlockId_OLD;
538 typedef enum DebugBlockId_BY2 {
539 DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
540 DBG_BLOCK_ID_VMC_BY2 = 0x1,
541 DBG_BLOCK_ID_CG_BY2 = 0x2,
542 DBG_BLOCK_ID_GRBM_BY2 = 0x3,
543 DBG_BLOCK_ID_CSC_BY2 = 0x4,
544 DBG_BLOCK_ID_IH_BY2 = 0x5,
545 DBG_BLOCK_ID_SQ_BY2 = 0x6,
546 DBG_BLOCK_ID_GMCON_BY2 = 0x7,
547 DBG_BLOCK_ID_DMA0_BY2 = 0x8,
548 DBG_BLOCK_ID_SPIM_BY2 = 0x9,
549 DBG_BLOCK_ID_SPIS_BY2 = 0xa,
550 DBG_BLOCK_ID_PA0_BY2 = 0xb,
551 DBG_BLOCK_ID_CP0_BY2 = 0xc,
552 DBG_BLOCK_ID_CP2_BY2 = 0xd,
553 DBG_BLOCK_ID_UVDU_BY2 = 0xe,
554 DBG_BLOCK_ID_VCE_BY2 = 0xf,
555 DBG_BLOCK_ID_VGT0_BY2 = 0x10,
556 DBG_BLOCK_ID_IA_BY2 = 0x11,
557 DBG_BLOCK_ID_SCT0_BY2 = 0x12,
558 DBG_BLOCK_ID_SPM0_BY2 = 0x13,
559 DBG_BLOCK_ID_TCAA_BY2 = 0x14,
560 DBG_BLOCK_ID_TCCA_BY2 = 0x15,
561 DBG_BLOCK_ID_MCC0_BY2 = 0x16,
562 DBG_BLOCK_ID_MCC2_BY2 = 0x17,
563 DBG_BLOCK_ID_SX0_BY2 = 0x18,
564 DBG_BLOCK_ID_SX2_BY2 = 0x19,
565 DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a,
566 DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b,
567 DBG_BLOCK_ID_PC0_BY2 = 0x1c,
568 DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d,
569 DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e,
570 DBG_BLOCK_ID_MCB_BY2 = 0x1f,
571 DBG_BLOCK_ID_SCB0_BY2 = 0x20,
572 DBG_BLOCK_ID_UNUSED13_BY2 = 0x21,
573 DBG_BLOCK_ID_SCF0_BY2 = 0x22,
574 DBG_BLOCK_ID_UNUSED15_BY2 = 0x23,
575 DBG_BLOCK_ID_BCI0_BY2 = 0x24,
576 DBG_BLOCK_ID_BCI2_BY2 = 0x25,
577 DBG_BLOCK_ID_UNUSED17_BY2 = 0x26,
578 DBG_BLOCK_ID_UNUSED19_BY2 = 0x27,
579 DBG_BLOCK_ID_CB00_BY2 = 0x28,
580 DBG_BLOCK_ID_CB02_BY2 = 0x29,
581 DBG_BLOCK_ID_CB04_BY2 = 0x2a,
582 DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b,
583 DBG_BLOCK_ID_CB10_BY2 = 0x2c,
584 DBG_BLOCK_ID_CB12_BY2 = 0x2d,
585 DBG_BLOCK_ID_CB14_BY2 = 0x2e,
586 DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f,
587 DBG_BLOCK_ID_TCP0_BY2 = 0x30,
588 DBG_BLOCK_ID_TCP2_BY2 = 0x31,
589 DBG_BLOCK_ID_TCP4_BY2 = 0x32,
590 DBG_BLOCK_ID_TCP6_BY2 = 0x33,
591 DBG_BLOCK_ID_TCP8_BY2 = 0x34,
592 DBG_BLOCK_ID_TCP10_BY2 = 0x35,
593 DBG_BLOCK_ID_TCP12_BY2 = 0x36,
594 DBG_BLOCK_ID_TCP14_BY2 = 0x37,
595 DBG_BLOCK_ID_TCP16_BY2 = 0x38,
596 DBG_BLOCK_ID_TCP18_BY2 = 0x39,
597 DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
598 DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
599 DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
600 DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
601 DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
602 DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
603 DBG_BLOCK_ID_DB00_BY2 = 0x40,
604 DBG_BLOCK_ID_DB02_BY2 = 0x41,
605 DBG_BLOCK_ID_DB04_BY2 = 0x42,
606 DBG_BLOCK_ID_UNUSED28_BY2 = 0x43,
607 DBG_BLOCK_ID_DB10_BY2 = 0x44,
608 DBG_BLOCK_ID_DB12_BY2 = 0x45,
609 DBG_BLOCK_ID_DB14_BY2 = 0x46,
610 DBG_BLOCK_ID_UNUSED31_BY2 = 0x47,
611 DBG_BLOCK_ID_TCC0_BY2 = 0x48,
612 DBG_BLOCK_ID_TCC2_BY2 = 0x49,
613 DBG_BLOCK_ID_TCC4_BY2 = 0x4a,
614 DBG_BLOCK_ID_TCC6_BY2 = 0x4b,
615 DBG_BLOCK_ID_SPS00_BY2 = 0x4c,
616 DBG_BLOCK_ID_SPS02_BY2 = 0x4d,
617 DBG_BLOCK_ID_SPS11_BY2 = 0x4e,
618 DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f,
619 DBG_BLOCK_ID_TA00_BY2 = 0x50,
620 DBG_BLOCK_ID_TA02_BY2 = 0x51,
621 DBG_BLOCK_ID_TA04_BY2 = 0x52,
622 DBG_BLOCK_ID_TA06_BY2 = 0x53,
623 DBG_BLOCK_ID_TA08_BY2 = 0x54,
624 DBG_BLOCK_ID_TA0A_BY2 = 0x55,
625 DBG_BLOCK_ID_UNUSED35_BY2 = 0x56,
626 DBG_BLOCK_ID_UNUSED37_BY2 = 0x57,
627 DBG_BLOCK_ID_TA10_BY2 = 0x58,
628 DBG_BLOCK_ID_TA12_BY2 = 0x59,
629 DBG_BLOCK_ID_TA14_BY2 = 0x5a,
630 DBG_BLOCK_ID_TA16_BY2 = 0x5b,
631 DBG_BLOCK_ID_TA18_BY2 = 0x5c,
632 DBG_BLOCK_ID_TA1A_BY2 = 0x5d,
633 DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e,
634 DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f,
635 DBG_BLOCK_ID_TD00_BY2 = 0x60,
636 DBG_BLOCK_ID_TD02_BY2 = 0x61,
637 DBG_BLOCK_ID_TD04_BY2 = 0x62,
638 DBG_BLOCK_ID_TD06_BY2 = 0x63,
639 DBG_BLOCK_ID_TD08_BY2 = 0x64,
640 DBG_BLOCK_ID_TD0A_BY2 = 0x65,
641 DBG_BLOCK_ID_UNUSED43_BY2 = 0x66,
642 DBG_BLOCK_ID_UNUSED45_BY2 = 0x67,
643 DBG_BLOCK_ID_TD10_BY2 = 0x68,
644 DBG_BLOCK_ID_TD12_BY2 = 0x69,
645 DBG_BLOCK_ID_TD14_BY2 = 0x6a,
646 DBG_BLOCK_ID_TD16_BY2 = 0x6b,
647 DBG_BLOCK_ID_TD18_BY2 = 0x6c,
648 DBG_BLOCK_ID_TD1A_BY2 = 0x6d,
649 DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e,
650 DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f,
651 DBG_BLOCK_ID_MCD0_BY2 = 0x70,
652 DBG_BLOCK_ID_MCD2_BY2 = 0x71,
653 DBG_BLOCK_ID_MCD4_BY2 = 0x72,
654 DBG_BLOCK_ID_UNUSED51_BY2 = 0x73,
655 } DebugBlockId_BY2;
656 typedef enum DebugBlockId_BY4 {
657 DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
658 DBG_BLOCK_ID_CG_BY4 = 0x1,
659 DBG_BLOCK_ID_CSC_BY4 = 0x2,
660 DBG_BLOCK_ID_SQ_BY4 = 0x3,
661 DBG_BLOCK_ID_DMA0_BY4 = 0x4,
662 DBG_BLOCK_ID_SPIS_BY4 = 0x5,
663 DBG_BLOCK_ID_CP0_BY4 = 0x6,
664 DBG_BLOCK_ID_UVDU_BY4 = 0x7,
665 DBG_BLOCK_ID_VGT0_BY4 = 0x8,
666 DBG_BLOCK_ID_SCT0_BY4 = 0x9,
667 DBG_BLOCK_ID_TCAA_BY4 = 0xa,
668 DBG_BLOCK_ID_MCC0_BY4 = 0xb,
669 DBG_BLOCK_ID_SX0_BY4 = 0xc,
670 DBG_BLOCK_ID_UNUSED4_BY4 = 0xd,
671 DBG_BLOCK_ID_PC0_BY4 = 0xe,
672 DBG_BLOCK_ID_UNUSED10_BY4 = 0xf,
673 DBG_BLOCK_ID_SCB0_BY4 = 0x10,
674 DBG_BLOCK_ID_SCF0_BY4 = 0x11,
675 DBG_BLOCK_ID_BCI0_BY4 = 0x12,
676 DBG_BLOCK_ID_UNUSED17_BY4 = 0x13,
677 DBG_BLOCK_ID_CB00_BY4 = 0x14,
678 DBG_BLOCK_ID_CB04_BY4 = 0x15,
679 DBG_BLOCK_ID_CB10_BY4 = 0x16,
680 DBG_BLOCK_ID_CB14_BY4 = 0x17,
681 DBG_BLOCK_ID_TCP0_BY4 = 0x18,
682 DBG_BLOCK_ID_TCP4_BY4 = 0x19,
683 DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
684 DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
685 DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
686 DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
687 DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
688 DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
689 DBG_BLOCK_ID_DB_BY4 = 0x20,
690 DBG_BLOCK_ID_DB04_BY4 = 0x21,
691 DBG_BLOCK_ID_DB10_BY4 = 0x22,
692 DBG_BLOCK_ID_DB14_BY4 = 0x23,
693 DBG_BLOCK_ID_TCC0_BY4 = 0x24,
694 DBG_BLOCK_ID_TCC4_BY4 = 0x25,
695 DBG_BLOCK_ID_SPS00_BY4 = 0x26,
696 DBG_BLOCK_ID_SPS11_BY4 = 0x27,
697 DBG_BLOCK_ID_TA00_BY4 = 0x28,
698 DBG_BLOCK_ID_TA04_BY4 = 0x29,
699 DBG_BLOCK_ID_TA08_BY4 = 0x2a,
700 DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b,
701 DBG_BLOCK_ID_TA10_BY4 = 0x2c,
702 DBG_BLOCK_ID_TA14_BY4 = 0x2d,
703 DBG_BLOCK_ID_TA18_BY4 = 0x2e,
704 DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f,
705 DBG_BLOCK_ID_TD00_BY4 = 0x30,
706 DBG_BLOCK_ID_TD04_BY4 = 0x31,
707 DBG_BLOCK_ID_TD08_BY4 = 0x32,
708 DBG_BLOCK_ID_UNUSED43_BY4 = 0x33,
709 DBG_BLOCK_ID_TD10_BY4 = 0x34,
710 DBG_BLOCK_ID_TD14_BY4 = 0x35,
711 DBG_BLOCK_ID_TD18_BY4 = 0x36,
712 DBG_BLOCK_ID_UNUSED47_BY4 = 0x37,
713 DBG_BLOCK_ID_MCD0_BY4 = 0x38,
714 DBG_BLOCK_ID_MCD4_BY4 = 0x39,
715 } DebugBlockId_BY4;
716 typedef enum DebugBlockId_BY8 {
717 DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
718 DBG_BLOCK_ID_CSC_BY8 = 0x1,
719 DBG_BLOCK_ID_DMA0_BY8 = 0x2,
720 DBG_BLOCK_ID_CP0_BY8 = 0x3,
721 DBG_BLOCK_ID_VGT0_BY8 = 0x4,
722 DBG_BLOCK_ID_TCAA_BY8 = 0x5,
723 DBG_BLOCK_ID_SX0_BY8 = 0x6,
724 DBG_BLOCK_ID_PC0_BY8 = 0x7,
725 DBG_BLOCK_ID_SCB0_BY8 = 0x8,
726 DBG_BLOCK_ID_BCI0_BY8 = 0x9,
727 DBG_BLOCK_ID_CB00_BY8 = 0xa,
728 DBG_BLOCK_ID_CB10_BY8 = 0xb,
729 DBG_BLOCK_ID_TCP0_BY8 = 0xc,
730 DBG_BLOCK_ID_TCP8_BY8 = 0xd,
731 DBG_BLOCK_ID_TCP16_BY8 = 0xe,
732 DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
733 DBG_BLOCK_ID_DB00_BY8 = 0x10,
734 DBG_BLOCK_ID_DB10_BY8 = 0x11,
735 DBG_BLOCK_ID_TCC0_BY8 = 0x12,
736 DBG_BLOCK_ID_SPS00_BY8 = 0x13,
737 DBG_BLOCK_ID_TA00_BY8 = 0x14,
738 DBG_BLOCK_ID_TA08_BY8 = 0x15,
739 DBG_BLOCK_ID_TA10_BY8 = 0x16,
740 DBG_BLOCK_ID_TA18_BY8 = 0x17,
741 DBG_BLOCK_ID_TD00_BY8 = 0x18,
742 DBG_BLOCK_ID_TD08_BY8 = 0x19,
743 DBG_BLOCK_ID_TD10_BY8 = 0x1a,
744 DBG_BLOCK_ID_TD18_BY8 = 0x1b,
745 DBG_BLOCK_ID_MCD0_BY8 = 0x1c,
746 } DebugBlockId_BY8;
747 typedef enum DebugBlockId_BY16 {
748 DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
749 DBG_BLOCK_ID_DMA0_BY16 = 0x1,
750 DBG_BLOCK_ID_VGT0_BY16 = 0x2,
751 DBG_BLOCK_ID_SX0_BY16 = 0x3,
752 DBG_BLOCK_ID_SCB0_BY16 = 0x4,
753 DBG_BLOCK_ID_CB00_BY16 = 0x5,
754 DBG_BLOCK_ID_TCP0_BY16 = 0x6,
755 DBG_BLOCK_ID_TCP16_BY16 = 0x7,
756 DBG_BLOCK_ID_DB00_BY16 = 0x8,
757 DBG_BLOCK_ID_TCC0_BY16 = 0x9,
758 DBG_BLOCK_ID_TA00_BY16 = 0xa,
759 DBG_BLOCK_ID_TA10_BY16 = 0xb,
760 DBG_BLOCK_ID_TD00_BY16 = 0xc,
761 DBG_BLOCK_ID_TD10_BY16 = 0xd,
762 DBG_BLOCK_ID_MCD0_BY16 = 0xe,
763 } DebugBlockId_BY16;
764 typedef enum ColorTransform {
765 DCC_CT_AUTO = 0x0,
766 DCC_CT_NONE = 0x1,
767 ABGR_TO_A_BG_G_RB = 0x2,
768 BGRA_TO_BG_G_RB_A = 0x3,
769 } ColorTransform;
770 typedef enum CompareRef {
771 REF_NEVER = 0x0,
772 REF_LESS = 0x1,
773 REF_EQUAL = 0x2,
774 REF_LEQUAL = 0x3,
775 REF_GREATER = 0x4,
776 REF_NOTEQUAL = 0x5,
777 REF_GEQUAL = 0x6,
778 REF_ALWAYS = 0x7,
779 } CompareRef;
780 typedef enum ReadSize {
781 READ_256_BITS = 0x0,
782 READ_512_BITS = 0x1,
783 } ReadSize;
784 typedef enum DepthFormat {
785 DEPTH_INVALID = 0x0,
786 DEPTH_16 = 0x1,
787 DEPTH_X8_24 = 0x2,
788 DEPTH_8_24 = 0x3,
789 DEPTH_X8_24_FLOAT = 0x4,
790 DEPTH_8_24_FLOAT = 0x5,
791 DEPTH_32_FLOAT = 0x6,
792 DEPTH_X24_8_32_FLOAT = 0x7,
793 } DepthFormat;
794 typedef enum ZFormat {
795 Z_INVALID = 0x0,
796 Z_16 = 0x1,
797 Z_24 = 0x2,
798 Z_32_FLOAT = 0x3,
799 } ZFormat;
800 typedef enum StencilFormat {
801 STENCIL_INVALID = 0x0,
802 STENCIL_8 = 0x1,
803 } StencilFormat;
804 typedef enum CmaskMode {
805 CMASK_CLEAR_NONE = 0x0,
806 CMASK_CLEAR_ONE = 0x1,
807 CMASK_CLEAR_ALL = 0x2,
808 CMASK_ANY_EXPANDED = 0x3,
809 CMASK_ALPHA0_FRAG1 = 0x4,
810 CMASK_ALPHA0_FRAG2 = 0x5,
811 CMASK_ALPHA0_FRAG4 = 0x6,
812 CMASK_ALPHA0_FRAGS = 0x7,
813 CMASK_ALPHA1_FRAG1 = 0x8,
814 CMASK_ALPHA1_FRAG2 = 0x9,
815 CMASK_ALPHA1_FRAG4 = 0xa,
816 CMASK_ALPHA1_FRAGS = 0xb,
817 CMASK_ALPHAX_FRAG1 = 0xc,
818 CMASK_ALPHAX_FRAG2 = 0xd,
819 CMASK_ALPHAX_FRAG4 = 0xe,
820 CMASK_ALPHAX_FRAGS = 0xf,
821 } CmaskMode;
822 typedef enum QuadExportFormat {
823 EXPORT_UNUSED = 0x0,
824 EXPORT_32_R = 0x1,
825 EXPORT_32_GR = 0x2,
826 EXPORT_32_AR = 0x3,
827 EXPORT_FP16_ABGR = 0x4,
828 EXPORT_UNSIGNED16_ABGR = 0x5,
829 EXPORT_SIGNED16_ABGR = 0x6,
830 EXPORT_32_ABGR = 0x7,
831 } QuadExportFormat;
832 typedef enum QuadExportFormatOld {
833 EXPORT_4P_32BPC_ABGR = 0x0,
834 EXPORT_4P_16BPC_ABGR = 0x1,
835 EXPORT_4P_32BPC_GR = 0x2,
836 EXPORT_4P_32BPC_AR = 0x3,
837 EXPORT_2P_32BPC_ABGR = 0x4,
838 EXPORT_8P_32BPC_R = 0x5,
839 } QuadExportFormatOld;
840 typedef enum ColorFormat {
841 COLOR_INVALID = 0x0,
842 COLOR_8 = 0x1,
843 COLOR_16 = 0x2,
844 COLOR_8_8 = 0x3,
845 COLOR_32 = 0x4,
846 COLOR_16_16 = 0x5,
847 COLOR_10_11_11 = 0x6,
848 COLOR_11_11_10 = 0x7,
849 COLOR_10_10_10_2 = 0x8,
850 COLOR_2_10_10_10 = 0x9,
851 COLOR_8_8_8_8 = 0xa,
852 COLOR_32_32 = 0xb,
853 COLOR_16_16_16_16 = 0xc,
854 COLOR_RESERVED_13 = 0xd,
855 COLOR_32_32_32_32 = 0xe,
856 COLOR_RESERVED_15 = 0xf,
857 COLOR_5_6_5 = 0x10,
858 COLOR_1_5_5_5 = 0x11,
859 COLOR_5_5_5_1 = 0x12,
860 COLOR_4_4_4_4 = 0x13,
861 COLOR_8_24 = 0x14,
862 COLOR_24_8 = 0x15,
863 COLOR_X24_8_32_FLOAT = 0x16,
864 COLOR_RESERVED_23 = 0x17,
865 } ColorFormat;
866 typedef enum SurfaceFormat {
867 FMT_INVALID = 0x0,
868 FMT_8 = 0x1,
869 FMT_16 = 0x2,
870 FMT_8_8 = 0x3,
871 FMT_32 = 0x4,
872 FMT_16_16 = 0x5,
873 FMT_10_11_11 = 0x6,
874 FMT_11_11_10 = 0x7,
875 FMT_10_10_10_2 = 0x8,
876 FMT_2_10_10_10 = 0x9,
877 FMT_8_8_8_8 = 0xa,
878 FMT_32_32 = 0xb,
879 FMT_16_16_16_16 = 0xc,
880 FMT_32_32_32 = 0xd,
881 FMT_32_32_32_32 = 0xe,
882 FMT_RESERVED_4 = 0xf,
883 FMT_5_6_5 = 0x10,
884 FMT_1_5_5_5 = 0x11,
885 FMT_5_5_5_1 = 0x12,
886 FMT_4_4_4_4 = 0x13,
887 FMT_8_24 = 0x14,
888 FMT_24_8 = 0x15,
889 FMT_X24_8_32_FLOAT = 0x16,
890 FMT_RESERVED_33 = 0x17,
891 FMT_11_11_10_FLOAT = 0x18,
892 FMT_16_FLOAT = 0x19,
893 FMT_32_FLOAT = 0x1a,
894 FMT_16_16_FLOAT = 0x1b,
895 FMT_8_24_FLOAT = 0x1c,
896 FMT_24_8_FLOAT = 0x1d,
897 FMT_32_32_FLOAT = 0x1e,
898 FMT_10_11_11_FLOAT = 0x1f,
899 FMT_16_16_16_16_FLOAT = 0x20,
900 FMT_3_3_2 = 0x21,
901 FMT_6_5_5 = 0x22,
902 FMT_32_32_32_32_FLOAT = 0x23,
903 FMT_RESERVED_36 = 0x24,
904 FMT_1 = 0x25,
905 FMT_1_REVERSED = 0x26,
906 FMT_GB_GR = 0x27,
907 FMT_BG_RG = 0x28,
908 FMT_32_AS_8 = 0x29,
909 FMT_32_AS_8_8 = 0x2a,
910 FMT_5_9_9_9_SHAREDEXP = 0x2b,
911 FMT_8_8_8 = 0x2c,
912 FMT_16_16_16 = 0x2d,
913 FMT_16_16_16_FLOAT = 0x2e,
914 FMT_4_4 = 0x2f,
915 FMT_32_32_32_FLOAT = 0x30,
916 FMT_BC1 = 0x31,
917 FMT_BC2 = 0x32,
918 FMT_BC3 = 0x33,
919 FMT_BC4 = 0x34,
920 FMT_BC5 = 0x35,
921 FMT_BC6 = 0x36,
922 FMT_BC7 = 0x37,
923 FMT_32_AS_32_32_32_32 = 0x38,
924 FMT_APC3 = 0x39,
925 FMT_APC4 = 0x3a,
926 FMT_APC5 = 0x3b,
927 FMT_APC6 = 0x3c,
928 FMT_APC7 = 0x3d,
929 FMT_CTX1 = 0x3e,
930 FMT_RESERVED_63 = 0x3f,
931 } SurfaceFormat;
932 typedef enum BUF_DATA_FORMAT {
933 BUF_DATA_FORMAT_INVALID = 0x0,
934 BUF_DATA_FORMAT_8 = 0x1,
935 BUF_DATA_FORMAT_16 = 0x2,
936 BUF_DATA_FORMAT_8_8 = 0x3,
937 BUF_DATA_FORMAT_32 = 0x4,
938 BUF_DATA_FORMAT_16_16 = 0x5,
939 BUF_DATA_FORMAT_10_11_11 = 0x6,
940 BUF_DATA_FORMAT_11_11_10 = 0x7,
941 BUF_DATA_FORMAT_10_10_10_2 = 0x8,
942 BUF_DATA_FORMAT_2_10_10_10 = 0x9,
943 BUF_DATA_FORMAT_8_8_8_8 = 0xa,
944 BUF_DATA_FORMAT_32_32 = 0xb,
945 BUF_DATA_FORMAT_16_16_16_16 = 0xc,
946 BUF_DATA_FORMAT_32_32_32 = 0xd,
947 BUF_DATA_FORMAT_32_32_32_32 = 0xe,
948 BUF_DATA_FORMAT_RESERVED_15 = 0xf,
949 } BUF_DATA_FORMAT;
950 typedef enum IMG_DATA_FORMAT {
951 IMG_DATA_FORMAT_INVALID = 0x0,
952 IMG_DATA_FORMAT_8 = 0x1,
953 IMG_DATA_FORMAT_16 = 0x2,
954 IMG_DATA_FORMAT_8_8 = 0x3,
955 IMG_DATA_FORMAT_32 = 0x4,
956 IMG_DATA_FORMAT_16_16 = 0x5,
957 IMG_DATA_FORMAT_10_11_11 = 0x6,
958 IMG_DATA_FORMAT_11_11_10 = 0x7,
959 IMG_DATA_FORMAT_10_10_10_2 = 0x8,
960 IMG_DATA_FORMAT_2_10_10_10 = 0x9,
961 IMG_DATA_FORMAT_8_8_8_8 = 0xa,
962 IMG_DATA_FORMAT_32_32 = 0xb,
963 IMG_DATA_FORMAT_16_16_16_16 = 0xc,
964 IMG_DATA_FORMAT_32_32_32 = 0xd,
965 IMG_DATA_FORMAT_32_32_32_32 = 0xe,
966 IMG_DATA_FORMAT_RESERVED_15 = 0xf,
967 IMG_DATA_FORMAT_5_6_5 = 0x10,
968 IMG_DATA_FORMAT_1_5_5_5 = 0x11,
969 IMG_DATA_FORMAT_5_5_5_1 = 0x12,
970 IMG_DATA_FORMAT_4_4_4_4 = 0x13,
971 IMG_DATA_FORMAT_8_24 = 0x14,
972 IMG_DATA_FORMAT_24_8 = 0x15,
973 IMG_DATA_FORMAT_X24_8_32 = 0x16,
974 IMG_DATA_FORMAT_RESERVED_23 = 0x17,
975 IMG_DATA_FORMAT_RESERVED_24 = 0x18,
976 IMG_DATA_FORMAT_RESERVED_25 = 0x19,
977 IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
978 IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
979 IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
980 IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
981 IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
982 IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
983 IMG_DATA_FORMAT_GB_GR = 0x20,
984 IMG_DATA_FORMAT_BG_RG = 0x21,
985 IMG_DATA_FORMAT_5_9_9_9 = 0x22,
986 IMG_DATA_FORMAT_BC1 = 0x23,
987 IMG_DATA_FORMAT_BC2 = 0x24,
988 IMG_DATA_FORMAT_BC3 = 0x25,
989 IMG_DATA_FORMAT_BC4 = 0x26,
990 IMG_DATA_FORMAT_BC5 = 0x27,
991 IMG_DATA_FORMAT_BC6 = 0x28,
992 IMG_DATA_FORMAT_BC7 = 0x29,
993 IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
994 IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
995 IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
996 IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
997 IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
998 IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
999 IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
1000 IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
1001 IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
1002 IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
1003 IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
1004 IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
1005 IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
1006 IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
1007 IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
1008 IMG_DATA_FORMAT_4_4 = 0x39,
1009 IMG_DATA_FORMAT_6_5_5 = 0x3a,
1010 IMG_DATA_FORMAT_1 = 0x3b,
1011 IMG_DATA_FORMAT_1_REVERSED = 0x3c,
1012 IMG_DATA_FORMAT_32_AS_8 = 0x3d,
1013 IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
1014 IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
1015 } IMG_DATA_FORMAT;
1016 typedef enum BUF_NUM_FORMAT {
1017 BUF_NUM_FORMAT_UNORM = 0x0,
1018 BUF_NUM_FORMAT_SNORM = 0x1,
1019 BUF_NUM_FORMAT_USCALED = 0x2,
1020 BUF_NUM_FORMAT_SSCALED = 0x3,
1021 BUF_NUM_FORMAT_UINT = 0x4,
1022 BUF_NUM_FORMAT_SINT = 0x5,
1023 BUF_NUM_FORMAT_RESERVED_6 = 0x6,
1024 BUF_NUM_FORMAT_FLOAT = 0x7,
1025 } BUF_NUM_FORMAT;
1026 typedef enum IMG_NUM_FORMAT {
1027 IMG_NUM_FORMAT_UNORM = 0x0,
1028 IMG_NUM_FORMAT_SNORM = 0x1,
1029 IMG_NUM_FORMAT_USCALED = 0x2,
1030 IMG_NUM_FORMAT_SSCALED = 0x3,
1031 IMG_NUM_FORMAT_UINT = 0x4,
1032 IMG_NUM_FORMAT_SINT = 0x5,
1033 IMG_NUM_FORMAT_RESERVED_6 = 0x6,
1034 IMG_NUM_FORMAT_FLOAT = 0x7,
1035 IMG_NUM_FORMAT_RESERVED_8 = 0x8,
1036 IMG_NUM_FORMAT_SRGB = 0x9,
1037 IMG_NUM_FORMAT_RESERVED_10 = 0xa,
1038 IMG_NUM_FORMAT_RESERVED_11 = 0xb,
1039 IMG_NUM_FORMAT_RESERVED_12 = 0xc,
1040 IMG_NUM_FORMAT_RESERVED_13 = 0xd,
1041 IMG_NUM_FORMAT_RESERVED_14 = 0xe,
1042 IMG_NUM_FORMAT_RESERVED_15 = 0xf,
1043 } IMG_NUM_FORMAT;
1044 typedef enum TileType {
1045 ARRAY_COLOR_TILE = 0x0,
1046 ARRAY_DEPTH_TILE = 0x1,
1047 } TileType;
1048 typedef enum NonDispTilingOrder {
1049 ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
1050 ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
1051 } NonDispTilingOrder;
1052 typedef enum MicroTileMode {
1053 ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
1054 ADDR_SURF_THIN_MICRO_TILING = 0x1,
1055 ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
1056 ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
1057 ADDR_SURF_THICK_MICRO_TILING = 0x4,
1058 } MicroTileMode;
1059 typedef enum TileSplit {
1060 ADDR_SURF_TILE_SPLIT_64B = 0x0,
1061 ADDR_SURF_TILE_SPLIT_128B = 0x1,
1062 ADDR_SURF_TILE_SPLIT_256B = 0x2,
1063 ADDR_SURF_TILE_SPLIT_512B = 0x3,
1064 ADDR_SURF_TILE_SPLIT_1KB = 0x4,
1065 ADDR_SURF_TILE_SPLIT_2KB = 0x5,
1066 ADDR_SURF_TILE_SPLIT_4KB = 0x6,
1067 } TileSplit;
1068 typedef enum SampleSplit {
1069 ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
1070 ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
1071 ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
1072 ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
1073 } SampleSplit;
1074 typedef enum PipeConfig {
1075 ADDR_SURF_P2 = 0x0,
1076 ADDR_SURF_P2_RESERVED0 = 0x1,
1077 ADDR_SURF_P2_RESERVED1 = 0x2,
1078 ADDR_SURF_P2_RESERVED2 = 0x3,
1079 ADDR_SURF_P4_8x16 = 0x4,
1080 ADDR_SURF_P4_16x16 = 0x5,
1081 ADDR_SURF_P4_16x32 = 0x6,
1082 ADDR_SURF_P4_32x32 = 0x7,
1083 ADDR_SURF_P8_16x16_8x16 = 0x8,
1084 ADDR_SURF_P8_16x32_8x16 = 0x9,
1085 ADDR_SURF_P8_32x32_8x16 = 0xa,
1086 ADDR_SURF_P8_16x32_16x16 = 0xb,
1087 ADDR_SURF_P8_32x32_16x16 = 0xc,
1088 ADDR_SURF_P8_32x32_16x32 = 0xd,
1089 ADDR_SURF_P8_32x64_32x32 = 0xe,
1090 ADDR_SURF_P8_RESERVED0 = 0xf,
1091 ADDR_SURF_P16_32x32_8x16 = 0x10,
1092 ADDR_SURF_P16_32x32_16x16 = 0x11,
1093 } PipeConfig;
1094 typedef enum NumBanks {
1095 ADDR_SURF_2_BANK = 0x0,
1096 ADDR_SURF_4_BANK = 0x1,
1097 ADDR_SURF_8_BANK = 0x2,
1098 ADDR_SURF_16_BANK = 0x3,
1099 } NumBanks;
1100 typedef enum BankWidth {
1101 ADDR_SURF_BANK_WIDTH_1 = 0x0,
1102 ADDR_SURF_BANK_WIDTH_2 = 0x1,
1103 ADDR_SURF_BANK_WIDTH_4 = 0x2,
1104 ADDR_SURF_BANK_WIDTH_8 = 0x3,
1105 } BankWidth;
1106 typedef enum BankHeight {
1107 ADDR_SURF_BANK_HEIGHT_1 = 0x0,
1108 ADDR_SURF_BANK_HEIGHT_2 = 0x1,
1109 ADDR_SURF_BANK_HEIGHT_4 = 0x2,
1110 ADDR_SURF_BANK_HEIGHT_8 = 0x3,
1111 } BankHeight;
1112 typedef enum BankWidthHeight {
1113 ADDR_SURF_BANK_WH_1 = 0x0,
1114 ADDR_SURF_BANK_WH_2 = 0x1,
1115 ADDR_SURF_BANK_WH_4 = 0x2,
1116 ADDR_SURF_BANK_WH_8 = 0x3,
1117 } BankWidthHeight;
1118 typedef enum MacroTileAspect {
1119 ADDR_SURF_MACRO_ASPECT_1 = 0x0,
1120 ADDR_SURF_MACRO_ASPECT_2 = 0x1,
1121 ADDR_SURF_MACRO_ASPECT_4 = 0x2,
1122 ADDR_SURF_MACRO_ASPECT_8 = 0x3,
1123 } MacroTileAspect;
1124 typedef enum GATCL1RequestType {
1125 GATCL1_TYPE_NORMAL = 0x0,
1126 GATCL1_TYPE_SHOOTDOWN = 0x1,
1127 GATCL1_TYPE_BYPASS = 0x2,
1128 } GATCL1RequestType;
1129 typedef enum TCC_CACHE_POLICIES {
1130 TCC_CACHE_POLICY_LRU = 0x0,
1131 TCC_CACHE_POLICY_STREAM = 0x1,
1132 } TCC_CACHE_POLICIES;
1133 typedef enum MTYPE {
1134 MTYPE_NC_NV = 0x0,
1135 MTYPE_NC = 0x1,
1136 MTYPE_CC = 0x2,
1137 MTYPE_UC = 0x3,
1138 } MTYPE;
1139 typedef enum PERFMON_COUNTER_MODE {
1140 PERFMON_COUNTER_MODE_ACCUM = 0x0,
1141 PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
1142 PERFMON_COUNTER_MODE_MAX = 0x2,
1143 PERFMON_COUNTER_MODE_DIRTY = 0x3,
1144 PERFMON_COUNTER_MODE_SAMPLE = 0x4,
1145 PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
1146 PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
1147 PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
1148 PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
1149 PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
1150 PERFMON_COUNTER_MODE_RESERVED = 0xf,
1151 } PERFMON_COUNTER_MODE;
1152 typedef enum PERFMON_SPM_MODE {
1153 PERFMON_SPM_MODE_OFF = 0x0,
1154 PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
1155 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
1156 PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
1157 PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
1158 PERFMON_SPM_MODE_RESERVED_5 = 0x5,
1159 PERFMON_SPM_MODE_RESERVED_6 = 0x6,
1160 PERFMON_SPM_MODE_RESERVED_7 = 0x7,
1161 PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
1162 PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
1163 PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
1164 } PERFMON_SPM_MODE;
1165 typedef enum SurfaceTiling {
1166 ARRAY_LINEAR = 0x0,
1167 ARRAY_TILED = 0x1,
1168 } SurfaceTiling;
1169 typedef enum SurfaceArray {
1170 ARRAY_1D = 0x0,
1171 ARRAY_2D = 0x1,
1172 ARRAY_3D = 0x2,
1173 ARRAY_3D_SLICE = 0x3,
1174 } SurfaceArray;
1175 typedef enum ColorArray {
1176 ARRAY_2D_ALT_COLOR = 0x0,
1177 ARRAY_2D_COLOR = 0x1,
1178 ARRAY_3D_SLICE_COLOR = 0x3,
1179 } ColorArray;
1180 typedef enum DepthArray {
1181 ARRAY_2D_ALT_DEPTH = 0x0,
1182 ARRAY_2D_DEPTH = 0x1,
1183 } DepthArray;
1184 typedef enum ENUM_NUM_SIMD_PER_CU {
1185 NUM_SIMD_PER_CU = 0x4,
1186 } ENUM_NUM_SIMD_PER_CU;
1187 typedef enum MEM_PWR_FORCE_CTRL {
1188 NO_FORCE_REQUEST = 0x0,
1189 FORCE_LIGHT_SLEEP_REQUEST = 0x1,
1190 FORCE_DEEP_SLEEP_REQUEST = 0x2,
1191 FORCE_SHUT_DOWN_REQUEST = 0x3,
1192 } MEM_PWR_FORCE_CTRL;
1193 typedef enum MEM_PWR_FORCE_CTRL2 {
1194 NO_FORCE_REQ = 0x0,
1195 FORCE_LIGHT_SLEEP_REQ = 0x1,
1196 } MEM_PWR_FORCE_CTRL2;
1197 typedef enum MEM_PWR_DIS_CTRL {
1198 ENABLE_MEM_PWR_CTRL = 0x0,
1199 DISABLE_MEM_PWR_CTRL = 0x1,
1200 } MEM_PWR_DIS_CTRL;
1201 typedef enum MEM_PWR_SEL_CTRL {
1202 DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
1203 DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
1204 DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
1205 } MEM_PWR_SEL_CTRL;
1206 typedef enum MEM_PWR_SEL_CTRL2 {
1207 DYNAMIC_DEEP_SLEEP_EN = 0x0,
1208 DYNAMIC_LIGHT_SLEEP_EN = 0x1,
1209 } MEM_PWR_SEL_CTRL2;
1210
1211 #endif /* UVD_5_0_ENUM_H */