drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0

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   1 /*
   2  * Copyright (C) 2017  Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  */
  21 #ifndef _sdma0_4_0_OFFSET_HEADER
  22 #define _sdma0_4_0_OFFSET_HEADER
  23 
  24 
  25 
  26 // addressBlock: sdma0_sdma0dec
  27 // base address:        0x4980
  28 #define mmSDMA0_UCODE_ADDR      0x0000
  29 #define mmSDMA0_UCODE_ADDR_BASE_IDX     0
  30 #define mmSDMA0_UCODE_DATA      0x0001
  31 #define mmSDMA0_UCODE_DATA_BASE_IDX     0
  32 #define mmSDMA0_VM_CNTL 0x0004
  33 #define mmSDMA0_VM_CNTL_BASE_IDX        0
  34 #define mmSDMA0_VM_CTX_LO       0x0005
  35 #define mmSDMA0_VM_CTX_LO_BASE_IDX      0
  36 #define mmSDMA0_VM_CTX_HI       0x0006
  37 #define mmSDMA0_VM_CTX_HI_BASE_IDX      0
  38 #define mmSDMA0_ACTIVE_FCN_ID   0x0007
  39 #define mmSDMA0_ACTIVE_FCN_ID_BASE_IDX  0
  40 #define mmSDMA0_VM_CTX_CNTL     0x0008
  41 #define mmSDMA0_VM_CTX_CNTL_BASE_IDX    0
  42 #define mmSDMA0_VIRT_RESET_REQ  0x0009
  43 #define mmSDMA0_VIRT_RESET_REQ_BASE_IDX 0
  44 #define mmSDMA0_VF_ENABLE       0x000a
  45 #define mmSDMA0_VF_ENABLE_BASE_IDX      0
  46 #define mmSDMA0_CONTEXT_REG_TYPE0       0x000b
  47 #define mmSDMA0_CONTEXT_REG_TYPE0_BASE_IDX      0
  48 #define mmSDMA0_CONTEXT_REG_TYPE1       0x000c
  49 #define mmSDMA0_CONTEXT_REG_TYPE1_BASE_IDX      0
  50 #define mmSDMA0_CONTEXT_REG_TYPE2       0x000d
  51 #define mmSDMA0_CONTEXT_REG_TYPE2_BASE_IDX      0
  52 #define mmSDMA0_CONTEXT_REG_TYPE3       0x000e
  53 #define mmSDMA0_CONTEXT_REG_TYPE3_BASE_IDX      0
  54 #define mmSDMA0_PUB_REG_TYPE0   0x000f
  55 #define mmSDMA0_PUB_REG_TYPE0_BASE_IDX  0
  56 #define mmSDMA0_PUB_REG_TYPE1   0x0010
  57 #define mmSDMA0_PUB_REG_TYPE1_BASE_IDX  0
  58 #define mmSDMA0_PUB_REG_TYPE2   0x0011
  59 #define mmSDMA0_PUB_REG_TYPE2_BASE_IDX  0
  60 #define mmSDMA0_PUB_REG_TYPE3   0x0012
  61 #define mmSDMA0_PUB_REG_TYPE3_BASE_IDX  0
  62 #define mmSDMA0_MMHUB_CNTL      0x0013
  63 #define mmSDMA0_MMHUB_CNTL_BASE_IDX     0
  64 #define mmSDMA0_CONTEXT_GROUP_BOUNDARY  0x0019
  65 #define mmSDMA0_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0
  66 #define mmSDMA0_POWER_CNTL      0x001a
  67 #define mmSDMA0_POWER_CNTL_BASE_IDX     0
  68 #define mmSDMA0_CLK_CTRL        0x001b
  69 #define mmSDMA0_CLK_CTRL_BASE_IDX       0
  70 #define mmSDMA0_CNTL    0x001c
  71 #define mmSDMA0_CNTL_BASE_IDX   0
  72 #define mmSDMA0_CHICKEN_BITS    0x001d
  73 #define mmSDMA0_CHICKEN_BITS_BASE_IDX   0
  74 #define mmSDMA0_GB_ADDR_CONFIG  0x001e
  75 #define mmSDMA0_GB_ADDR_CONFIG_BASE_IDX 0
  76 #define mmSDMA0_GB_ADDR_CONFIG_READ     0x001f
  77 #define mmSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX    0
  78 #define mmSDMA0_RB_RPTR_FETCH_HI        0x0020
  79 #define mmSDMA0_RB_RPTR_FETCH_HI_BASE_IDX       0
  80 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL        0x0021
  81 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX       0
  82 #define mmSDMA0_RB_RPTR_FETCH   0x0022
  83 #define mmSDMA0_RB_RPTR_FETCH_BASE_IDX  0
  84 #define mmSDMA0_IB_OFFSET_FETCH 0x0023
  85 #define mmSDMA0_IB_OFFSET_FETCH_BASE_IDX        0
  86 #define mmSDMA0_PROGRAM 0x0024
  87 #define mmSDMA0_PROGRAM_BASE_IDX        0
  88 #define mmSDMA0_STATUS_REG      0x0025
  89 #define mmSDMA0_STATUS_REG_BASE_IDX     0
  90 #define mmSDMA0_STATUS1_REG     0x0026
  91 #define mmSDMA0_STATUS1_REG_BASE_IDX    0
  92 #define mmSDMA0_RD_BURST_CNTL   0x0027
  93 #define mmSDMA0_RD_BURST_CNTL_BASE_IDX  0
  94 #define mmSDMA0_HBM_PAGE_CONFIG 0x0028
  95 #define mmSDMA0_HBM_PAGE_CONFIG_BASE_IDX        0
  96 #define mmSDMA0_UCODE_CHECKSUM  0x0029
  97 #define mmSDMA0_UCODE_CHECKSUM_BASE_IDX 0
  98 #define mmSDMA0_F32_CNTL        0x002a
  99 #define mmSDMA0_F32_CNTL_BASE_IDX       0
 100 #define mmSDMA0_FREEZE  0x002b
 101 #define mmSDMA0_FREEZE_BASE_IDX 0
 102 #define mmSDMA0_PHASE0_QUANTUM  0x002c
 103 #define mmSDMA0_PHASE0_QUANTUM_BASE_IDX 0
 104 #define mmSDMA0_PHASE1_QUANTUM  0x002d
 105 #define mmSDMA0_PHASE1_QUANTUM_BASE_IDX 0
 106 #define mmSDMA_POWER_GATING     0x002e
 107 #define mmSDMA_POWER_GATING_BASE_IDX    0
 108 #define mmSDMA_PGFSM_CONFIG     0x002f
 109 #define mmSDMA_PGFSM_CONFIG_BASE_IDX    0
 110 #define mmSDMA_PGFSM_WRITE      0x0030
 111 #define mmSDMA_PGFSM_WRITE_BASE_IDX     0
 112 #define mmSDMA_PGFSM_READ       0x0031
 113 #define mmSDMA_PGFSM_READ_BASE_IDX      0
 114 #define mmSDMA0_EDC_CONFIG      0x0032
 115 #define mmSDMA0_EDC_CONFIG_BASE_IDX     0
 116 #define mmSDMA0_BA_THRESHOLD    0x0033
 117 #define mmSDMA0_BA_THRESHOLD_BASE_IDX   0
 118 #define mmSDMA0_ID      0x0034
 119 #define mmSDMA0_ID_BASE_IDX     0
 120 #define mmSDMA0_VERSION 0x0035
 121 #define mmSDMA0_VERSION_BASE_IDX        0
 122 #define mmSDMA0_EDC_COUNTER     0x0036
 123 #define mmSDMA0_EDC_COUNTER_BASE_IDX    0
 124 #define mmSDMA0_EDC_COUNTER_CLEAR       0x0037
 125 #define mmSDMA0_EDC_COUNTER_CLEAR_BASE_IDX      0
 126 #define mmSDMA0_STATUS2_REG     0x0038
 127 #define mmSDMA0_STATUS2_REG_BASE_IDX    0
 128 #define mmSDMA0_ATOMIC_CNTL     0x0039
 129 #define mmSDMA0_ATOMIC_CNTL_BASE_IDX    0
 130 #define mmSDMA0_ATOMIC_PREOP_LO 0x003a
 131 #define mmSDMA0_ATOMIC_PREOP_LO_BASE_IDX        0
 132 #define mmSDMA0_ATOMIC_PREOP_HI 0x003b
 133 #define mmSDMA0_ATOMIC_PREOP_HI_BASE_IDX        0
 134 #define mmSDMA0_UTCL1_CNTL      0x003c
 135 #define mmSDMA0_UTCL1_CNTL_BASE_IDX     0
 136 #define mmSDMA0_UTCL1_WATERMK   0x003d
 137 #define mmSDMA0_UTCL1_WATERMK_BASE_IDX  0
 138 #define mmSDMA0_UTCL1_RD_STATUS 0x003e
 139 #define mmSDMA0_UTCL1_RD_STATUS_BASE_IDX        0
 140 #define mmSDMA0_UTCL1_WR_STATUS 0x003f
 141 #define mmSDMA0_UTCL1_WR_STATUS_BASE_IDX        0
 142 #define mmSDMA0_UTCL1_INV0      0x0040
 143 #define mmSDMA0_UTCL1_INV0_BASE_IDX     0
 144 #define mmSDMA0_UTCL1_INV1      0x0041
 145 #define mmSDMA0_UTCL1_INV1_BASE_IDX     0
 146 #define mmSDMA0_UTCL1_INV2      0x0042
 147 #define mmSDMA0_UTCL1_INV2_BASE_IDX     0
 148 #define mmSDMA0_UTCL1_RD_XNACK0 0x0043
 149 #define mmSDMA0_UTCL1_RD_XNACK0_BASE_IDX        0
 150 #define mmSDMA0_UTCL1_RD_XNACK1 0x0044
 151 #define mmSDMA0_UTCL1_RD_XNACK1_BASE_IDX        0
 152 #define mmSDMA0_UTCL1_WR_XNACK0 0x0045
 153 #define mmSDMA0_UTCL1_WR_XNACK0_BASE_IDX        0
 154 #define mmSDMA0_UTCL1_WR_XNACK1 0x0046
 155 #define mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX        0
 156 #define mmSDMA0_UTCL1_TIMEOUT   0x0047
 157 #define mmSDMA0_UTCL1_TIMEOUT_BASE_IDX  0
 158 #define mmSDMA0_UTCL1_PAGE      0x0048
 159 #define mmSDMA0_UTCL1_PAGE_BASE_IDX     0
 160 #define mmSDMA0_POWER_CNTL_IDLE 0x0049
 161 #define mmSDMA0_POWER_CNTL_IDLE_BASE_IDX        0
 162 #define mmSDMA0_RELAX_ORDERING_LUT      0x004a
 163 #define mmSDMA0_RELAX_ORDERING_LUT_BASE_IDX     0
 164 #define mmSDMA0_CHICKEN_BITS_2  0x004b
 165 #define mmSDMA0_CHICKEN_BITS_2_BASE_IDX 0
 166 #define mmSDMA0_STATUS3_REG     0x004c
 167 #define mmSDMA0_STATUS3_REG_BASE_IDX    0
 168 #define mmSDMA0_PHYSICAL_ADDR_LO        0x004d
 169 #define mmSDMA0_PHYSICAL_ADDR_LO_BASE_IDX       0
 170 #define mmSDMA0_PHYSICAL_ADDR_HI        0x004e
 171 #define mmSDMA0_PHYSICAL_ADDR_HI_BASE_IDX       0
 172 #define mmSDMA0_PHASE2_QUANTUM  0x004f
 173 #define mmSDMA0_PHASE2_QUANTUM_BASE_IDX 0
 174 #define mmSDMA0_ERROR_LOG       0x0050
 175 #define mmSDMA0_ERROR_LOG_BASE_IDX      0
 176 #define mmSDMA0_PUB_DUMMY_REG0  0x0051
 177 #define mmSDMA0_PUB_DUMMY_REG0_BASE_IDX 0
 178 #define mmSDMA0_PUB_DUMMY_REG1  0x0052
 179 #define mmSDMA0_PUB_DUMMY_REG1_BASE_IDX 0
 180 #define mmSDMA0_PUB_DUMMY_REG2  0x0053
 181 #define mmSDMA0_PUB_DUMMY_REG2_BASE_IDX 0
 182 #define mmSDMA0_PUB_DUMMY_REG3  0x0054
 183 #define mmSDMA0_PUB_DUMMY_REG3_BASE_IDX 0
 184 #define mmSDMA0_F32_COUNTER     0x0055
 185 #define mmSDMA0_F32_COUNTER_BASE_IDX    0
 186 #define mmSDMA0_UNBREAKABLE     0x0056
 187 #define mmSDMA0_UNBREAKABLE_BASE_IDX    0
 188 #define mmSDMA0_PERFMON_CNTL    0x0057
 189 #define mmSDMA0_PERFMON_CNTL_BASE_IDX   0
 190 #define mmSDMA0_PERFCOUNTER0_RESULT     0x0058
 191 #define mmSDMA0_PERFCOUNTER0_RESULT_BASE_IDX    0
 192 #define mmSDMA0_PERFCOUNTER1_RESULT     0x0059
 193 #define mmSDMA0_PERFCOUNTER1_RESULT_BASE_IDX    0
 194 #define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE     0x005a
 195 #define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX    0
 196 #define mmSDMA0_CRD_CNTL        0x005b
 197 #define mmSDMA0_CRD_CNTL_BASE_IDX       0
 198 #define mmSDMA0_MMHUB_TRUSTLVL  0x005c
 199 #define mmSDMA0_MMHUB_TRUSTLVL_BASE_IDX 0
 200 #define mmSDMA0_GPU_IOV_VIOLATION_LOG   0x005d
 201 #define mmSDMA0_GPU_IOV_VIOLATION_LOG_BASE_IDX  0
 202 #define mmSDMA0_ULV_CNTL        0x005e
 203 #define mmSDMA0_ULV_CNTL_BASE_IDX       0
 204 #define mmSDMA0_EA_DBIT_ADDR_DATA       0x0060
 205 #define mmSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX      0
 206 #define mmSDMA0_EA_DBIT_ADDR_INDEX      0x0061
 207 #define mmSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX     0
 208 #define mmSDMA0_GFX_RB_CNTL     0x0080
 209 #define mmSDMA0_GFX_RB_CNTL_BASE_IDX    0
 210 #define mmSDMA0_GFX_RB_BASE     0x0081
 211 #define mmSDMA0_GFX_RB_BASE_BASE_IDX    0
 212 #define mmSDMA0_GFX_RB_BASE_HI  0x0082
 213 #define mmSDMA0_GFX_RB_BASE_HI_BASE_IDX 0
 214 #define mmSDMA0_GFX_RB_RPTR     0x0083
 215 #define mmSDMA0_GFX_RB_RPTR_BASE_IDX    0
 216 #define mmSDMA0_GFX_RB_RPTR_HI  0x0084
 217 #define mmSDMA0_GFX_RB_RPTR_HI_BASE_IDX 0
 218 #define mmSDMA0_GFX_RB_WPTR     0x0085
 219 #define mmSDMA0_GFX_RB_WPTR_BASE_IDX    0
 220 #define mmSDMA0_GFX_RB_WPTR_HI  0x0086
 221 #define mmSDMA0_GFX_RB_WPTR_HI_BASE_IDX 0
 222 #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL   0x0087
 223 #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_BASE_IDX  0
 224 #define mmSDMA0_GFX_RB_RPTR_ADDR_HI     0x0088
 225 #define mmSDMA0_GFX_RB_RPTR_ADDR_HI_BASE_IDX    0
 226 #define mmSDMA0_GFX_RB_RPTR_ADDR_LO     0x0089
 227 #define mmSDMA0_GFX_RB_RPTR_ADDR_LO_BASE_IDX    0
 228 #define mmSDMA0_GFX_IB_CNTL     0x008a
 229 #define mmSDMA0_GFX_IB_CNTL_BASE_IDX    0
 230 #define mmSDMA0_GFX_IB_RPTR     0x008b
 231 #define mmSDMA0_GFX_IB_RPTR_BASE_IDX    0
 232 #define mmSDMA0_GFX_IB_OFFSET   0x008c
 233 #define mmSDMA0_GFX_IB_OFFSET_BASE_IDX  0
 234 #define mmSDMA0_GFX_IB_BASE_LO  0x008d
 235 #define mmSDMA0_GFX_IB_BASE_LO_BASE_IDX 0
 236 #define mmSDMA0_GFX_IB_BASE_HI  0x008e
 237 #define mmSDMA0_GFX_IB_BASE_HI_BASE_IDX 0
 238 #define mmSDMA0_GFX_IB_SIZE     0x008f
 239 #define mmSDMA0_GFX_IB_SIZE_BASE_IDX    0
 240 #define mmSDMA0_GFX_SKIP_CNTL   0x0090
 241 #define mmSDMA0_GFX_SKIP_CNTL_BASE_IDX  0
 242 #define mmSDMA0_GFX_CONTEXT_STATUS      0x0091
 243 #define mmSDMA0_GFX_CONTEXT_STATUS_BASE_IDX     0
 244 #define mmSDMA0_GFX_DOORBELL    0x0092
 245 #define mmSDMA0_GFX_DOORBELL_BASE_IDX   0
 246 #define mmSDMA0_GFX_CONTEXT_CNTL        0x0093
 247 #define mmSDMA0_GFX_CONTEXT_CNTL_BASE_IDX       0
 248 #define mmSDMA0_GFX_STATUS      0x00a8
 249 #define mmSDMA0_GFX_STATUS_BASE_IDX     0
 250 #define mmSDMA0_GFX_DOORBELL_LOG        0x00a9
 251 #define mmSDMA0_GFX_DOORBELL_LOG_BASE_IDX       0
 252 #define mmSDMA0_GFX_WATERMARK   0x00aa
 253 #define mmSDMA0_GFX_WATERMARK_BASE_IDX  0
 254 #define mmSDMA0_GFX_DOORBELL_OFFSET     0x00ab
 255 #define mmSDMA0_GFX_DOORBELL_OFFSET_BASE_IDX    0
 256 #define mmSDMA0_GFX_CSA_ADDR_LO 0x00ac
 257 #define mmSDMA0_GFX_CSA_ADDR_LO_BASE_IDX        0
 258 #define mmSDMA0_GFX_CSA_ADDR_HI 0x00ad
 259 #define mmSDMA0_GFX_CSA_ADDR_HI_BASE_IDX        0
 260 #define mmSDMA0_GFX_IB_SUB_REMAIN       0x00af
 261 #define mmSDMA0_GFX_IB_SUB_REMAIN_BASE_IDX      0
 262 #define mmSDMA0_GFX_PREEMPT     0x00b0
 263 #define mmSDMA0_GFX_PREEMPT_BASE_IDX    0
 264 #define mmSDMA0_GFX_DUMMY_REG   0x00b1
 265 #define mmSDMA0_GFX_DUMMY_REG_BASE_IDX  0
 266 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI        0x00b2
 267 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX       0
 268 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO        0x00b3
 269 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX       0
 270 #define mmSDMA0_GFX_RB_AQL_CNTL 0x00b4
 271 #define mmSDMA0_GFX_RB_AQL_CNTL_BASE_IDX        0
 272 #define mmSDMA0_GFX_MINOR_PTR_UPDATE    0x00b5
 273 #define mmSDMA0_GFX_MINOR_PTR_UPDATE_BASE_IDX   0
 274 #define mmSDMA0_GFX_MIDCMD_DATA0        0x00c0
 275 #define mmSDMA0_GFX_MIDCMD_DATA0_BASE_IDX       0
 276 #define mmSDMA0_GFX_MIDCMD_DATA1        0x00c1
 277 #define mmSDMA0_GFX_MIDCMD_DATA1_BASE_IDX       0
 278 #define mmSDMA0_GFX_MIDCMD_DATA2        0x00c2
 279 #define mmSDMA0_GFX_MIDCMD_DATA2_BASE_IDX       0
 280 #define mmSDMA0_GFX_MIDCMD_DATA3        0x00c3
 281 #define mmSDMA0_GFX_MIDCMD_DATA3_BASE_IDX       0
 282 #define mmSDMA0_GFX_MIDCMD_DATA4        0x00c4
 283 #define mmSDMA0_GFX_MIDCMD_DATA4_BASE_IDX       0
 284 #define mmSDMA0_GFX_MIDCMD_DATA5        0x00c5
 285 #define mmSDMA0_GFX_MIDCMD_DATA5_BASE_IDX       0
 286 #define mmSDMA0_GFX_MIDCMD_DATA6        0x00c6
 287 #define mmSDMA0_GFX_MIDCMD_DATA6_BASE_IDX       0
 288 #define mmSDMA0_GFX_MIDCMD_DATA7        0x00c7
 289 #define mmSDMA0_GFX_MIDCMD_DATA7_BASE_IDX       0
 290 #define mmSDMA0_GFX_MIDCMD_DATA8        0x00c8
 291 #define mmSDMA0_GFX_MIDCMD_DATA8_BASE_IDX       0
 292 #define mmSDMA0_GFX_MIDCMD_CNTL 0x00c9
 293 #define mmSDMA0_GFX_MIDCMD_CNTL_BASE_IDX        0
 294 #define mmSDMA0_PAGE_RB_CNTL    0x00e0
 295 #define mmSDMA0_PAGE_RB_CNTL_BASE_IDX   0
 296 #define mmSDMA0_PAGE_RB_BASE    0x00e1
 297 #define mmSDMA0_PAGE_RB_BASE_BASE_IDX   0
 298 #define mmSDMA0_PAGE_RB_BASE_HI 0x00e2
 299 #define mmSDMA0_PAGE_RB_BASE_HI_BASE_IDX        0
 300 #define mmSDMA0_PAGE_RB_RPTR    0x00e3
 301 #define mmSDMA0_PAGE_RB_RPTR_BASE_IDX   0
 302 #define mmSDMA0_PAGE_RB_RPTR_HI 0x00e4
 303 #define mmSDMA0_PAGE_RB_RPTR_HI_BASE_IDX        0
 304 #define mmSDMA0_PAGE_RB_WPTR    0x00e5
 305 #define mmSDMA0_PAGE_RB_WPTR_BASE_IDX   0
 306 #define mmSDMA0_PAGE_RB_WPTR_HI 0x00e6
 307 #define mmSDMA0_PAGE_RB_WPTR_HI_BASE_IDX        0
 308 #define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL  0x00e7
 309 #define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0
 310 #define mmSDMA0_PAGE_RB_RPTR_ADDR_HI    0x00e8
 311 #define mmSDMA0_PAGE_RB_RPTR_ADDR_HI_BASE_IDX   0
 312 #define mmSDMA0_PAGE_RB_RPTR_ADDR_LO    0x00e9
 313 #define mmSDMA0_PAGE_RB_RPTR_ADDR_LO_BASE_IDX   0
 314 #define mmSDMA0_PAGE_IB_CNTL    0x00ea
 315 #define mmSDMA0_PAGE_IB_CNTL_BASE_IDX   0
 316 #define mmSDMA0_PAGE_IB_RPTR    0x00eb
 317 #define mmSDMA0_PAGE_IB_RPTR_BASE_IDX   0
 318 #define mmSDMA0_PAGE_IB_OFFSET  0x00ec
 319 #define mmSDMA0_PAGE_IB_OFFSET_BASE_IDX 0
 320 #define mmSDMA0_PAGE_IB_BASE_LO 0x00ed
 321 #define mmSDMA0_PAGE_IB_BASE_LO_BASE_IDX        0
 322 #define mmSDMA0_PAGE_IB_BASE_HI 0x00ee
 323 #define mmSDMA0_PAGE_IB_BASE_HI_BASE_IDX        0
 324 #define mmSDMA0_PAGE_IB_SIZE    0x00ef
 325 #define mmSDMA0_PAGE_IB_SIZE_BASE_IDX   0
 326 #define mmSDMA0_PAGE_SKIP_CNTL  0x00f0
 327 #define mmSDMA0_PAGE_SKIP_CNTL_BASE_IDX 0
 328 #define mmSDMA0_PAGE_CONTEXT_STATUS     0x00f1
 329 #define mmSDMA0_PAGE_CONTEXT_STATUS_BASE_IDX    0
 330 #define mmSDMA0_PAGE_DOORBELL   0x00f2
 331 #define mmSDMA0_PAGE_DOORBELL_BASE_IDX  0
 332 #define mmSDMA0_PAGE_STATUS     0x0108
 333 #define mmSDMA0_PAGE_STATUS_BASE_IDX    0
 334 #define mmSDMA0_PAGE_DOORBELL_LOG       0x0109
 335 #define mmSDMA0_PAGE_DOORBELL_LOG_BASE_IDX      0
 336 #define mmSDMA0_PAGE_WATERMARK  0x010a
 337 #define mmSDMA0_PAGE_WATERMARK_BASE_IDX 0
 338 #define mmSDMA0_PAGE_DOORBELL_OFFSET    0x010b
 339 #define mmSDMA0_PAGE_DOORBELL_OFFSET_BASE_IDX   0
 340 #define mmSDMA0_PAGE_CSA_ADDR_LO        0x010c
 341 #define mmSDMA0_PAGE_CSA_ADDR_LO_BASE_IDX       0
 342 #define mmSDMA0_PAGE_CSA_ADDR_HI        0x010d
 343 #define mmSDMA0_PAGE_CSA_ADDR_HI_BASE_IDX       0
 344 #define mmSDMA0_PAGE_IB_SUB_REMAIN      0x010f
 345 #define mmSDMA0_PAGE_IB_SUB_REMAIN_BASE_IDX     0
 346 #define mmSDMA0_PAGE_PREEMPT    0x0110
 347 #define mmSDMA0_PAGE_PREEMPT_BASE_IDX   0
 348 #define mmSDMA0_PAGE_DUMMY_REG  0x0111
 349 #define mmSDMA0_PAGE_DUMMY_REG_BASE_IDX 0
 350 #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI       0x0112
 351 #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX      0
 352 #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO       0x0113
 353 #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX      0
 354 #define mmSDMA0_PAGE_RB_AQL_CNTL        0x0114
 355 #define mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX       0
 356 #define mmSDMA0_PAGE_MINOR_PTR_UPDATE   0x0115
 357 #define mmSDMA0_PAGE_MINOR_PTR_UPDATE_BASE_IDX  0
 358 #define mmSDMA0_PAGE_MIDCMD_DATA0       0x0120
 359 #define mmSDMA0_PAGE_MIDCMD_DATA0_BASE_IDX      0
 360 #define mmSDMA0_PAGE_MIDCMD_DATA1       0x0121
 361 #define mmSDMA0_PAGE_MIDCMD_DATA1_BASE_IDX      0
 362 #define mmSDMA0_PAGE_MIDCMD_DATA2       0x0122
 363 #define mmSDMA0_PAGE_MIDCMD_DATA2_BASE_IDX      0
 364 #define mmSDMA0_PAGE_MIDCMD_DATA3       0x0123
 365 #define mmSDMA0_PAGE_MIDCMD_DATA3_BASE_IDX      0
 366 #define mmSDMA0_PAGE_MIDCMD_DATA4       0x0124
 367 #define mmSDMA0_PAGE_MIDCMD_DATA4_BASE_IDX      0
 368 #define mmSDMA0_PAGE_MIDCMD_DATA5       0x0125
 369 #define mmSDMA0_PAGE_MIDCMD_DATA5_BASE_IDX      0
 370 #define mmSDMA0_PAGE_MIDCMD_DATA6       0x0126
 371 #define mmSDMA0_PAGE_MIDCMD_DATA6_BASE_IDX      0
 372 #define mmSDMA0_PAGE_MIDCMD_DATA7       0x0127
 373 #define mmSDMA0_PAGE_MIDCMD_DATA7_BASE_IDX      0
 374 #define mmSDMA0_PAGE_MIDCMD_DATA8       0x0128
 375 #define mmSDMA0_PAGE_MIDCMD_DATA8_BASE_IDX      0
 376 #define mmSDMA0_PAGE_MIDCMD_CNTL        0x0129
 377 #define mmSDMA0_PAGE_MIDCMD_CNTL_BASE_IDX       0
 378 #define mmSDMA0_RLC0_RB_CNTL    0x0140
 379 #define mmSDMA0_RLC0_RB_CNTL_BASE_IDX   0
 380 #define mmSDMA0_RLC0_RB_BASE    0x0141
 381 #define mmSDMA0_RLC0_RB_BASE_BASE_IDX   0
 382 #define mmSDMA0_RLC0_RB_BASE_HI 0x0142
 383 #define mmSDMA0_RLC0_RB_BASE_HI_BASE_IDX        0
 384 #define mmSDMA0_RLC0_RB_RPTR    0x0143
 385 #define mmSDMA0_RLC0_RB_RPTR_BASE_IDX   0
 386 #define mmSDMA0_RLC0_RB_RPTR_HI 0x0144
 387 #define mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX        0
 388 #define mmSDMA0_RLC0_RB_WPTR    0x0145
 389 #define mmSDMA0_RLC0_RB_WPTR_BASE_IDX   0
 390 #define mmSDMA0_RLC0_RB_WPTR_HI 0x0146
 391 #define mmSDMA0_RLC0_RB_WPTR_HI_BASE_IDX        0
 392 #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL  0x0147
 393 #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0
 394 #define mmSDMA0_RLC0_RB_RPTR_ADDR_HI    0x0148
 395 #define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_BASE_IDX   0
 396 #define mmSDMA0_RLC0_RB_RPTR_ADDR_LO    0x0149
 397 #define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_BASE_IDX   0
 398 #define mmSDMA0_RLC0_IB_CNTL    0x014a
 399 #define mmSDMA0_RLC0_IB_CNTL_BASE_IDX   0
 400 #define mmSDMA0_RLC0_IB_RPTR    0x014b
 401 #define mmSDMA0_RLC0_IB_RPTR_BASE_IDX   0
 402 #define mmSDMA0_RLC0_IB_OFFSET  0x014c
 403 #define mmSDMA0_RLC0_IB_OFFSET_BASE_IDX 0
 404 #define mmSDMA0_RLC0_IB_BASE_LO 0x014d
 405 #define mmSDMA0_RLC0_IB_BASE_LO_BASE_IDX        0
 406 #define mmSDMA0_RLC0_IB_BASE_HI 0x014e
 407 #define mmSDMA0_RLC0_IB_BASE_HI_BASE_IDX        0
 408 #define mmSDMA0_RLC0_IB_SIZE    0x014f
 409 #define mmSDMA0_RLC0_IB_SIZE_BASE_IDX   0
 410 #define mmSDMA0_RLC0_SKIP_CNTL  0x0150
 411 #define mmSDMA0_RLC0_SKIP_CNTL_BASE_IDX 0
 412 #define mmSDMA0_RLC0_CONTEXT_STATUS     0x0151
 413 #define mmSDMA0_RLC0_CONTEXT_STATUS_BASE_IDX    0
 414 #define mmSDMA0_RLC0_DOORBELL   0x0152
 415 #define mmSDMA0_RLC0_DOORBELL_BASE_IDX  0
 416 #define mmSDMA0_RLC0_STATUS     0x0168
 417 #define mmSDMA0_RLC0_STATUS_BASE_IDX    0
 418 #define mmSDMA0_RLC0_DOORBELL_LOG       0x0169
 419 #define mmSDMA0_RLC0_DOORBELL_LOG_BASE_IDX      0
 420 #define mmSDMA0_RLC0_WATERMARK  0x016a
 421 #define mmSDMA0_RLC0_WATERMARK_BASE_IDX 0
 422 #define mmSDMA0_RLC0_DOORBELL_OFFSET    0x016b
 423 #define mmSDMA0_RLC0_DOORBELL_OFFSET_BASE_IDX   0
 424 #define mmSDMA0_RLC0_CSA_ADDR_LO        0x016c
 425 #define mmSDMA0_RLC0_CSA_ADDR_LO_BASE_IDX       0
 426 #define mmSDMA0_RLC0_CSA_ADDR_HI        0x016d
 427 #define mmSDMA0_RLC0_CSA_ADDR_HI_BASE_IDX       0
 428 #define mmSDMA0_RLC0_IB_SUB_REMAIN      0x016f
 429 #define mmSDMA0_RLC0_IB_SUB_REMAIN_BASE_IDX     0
 430 #define mmSDMA0_RLC0_PREEMPT    0x0170
 431 #define mmSDMA0_RLC0_PREEMPT_BASE_IDX   0
 432 #define mmSDMA0_RLC0_DUMMY_REG  0x0171
 433 #define mmSDMA0_RLC0_DUMMY_REG_BASE_IDX 0
 434 #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI       0x0172
 435 #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX      0
 436 #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO       0x0173
 437 #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX      0
 438 #define mmSDMA0_RLC0_RB_AQL_CNTL        0x0174
 439 #define mmSDMA0_RLC0_RB_AQL_CNTL_BASE_IDX       0
 440 #define mmSDMA0_RLC0_MINOR_PTR_UPDATE   0x0175
 441 #define mmSDMA0_RLC0_MINOR_PTR_UPDATE_BASE_IDX  0
 442 #define mmSDMA0_RLC0_MIDCMD_DATA0       0x0180
 443 #define mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX      0
 444 #define mmSDMA0_RLC0_MIDCMD_DATA1       0x0181
 445 #define mmSDMA0_RLC0_MIDCMD_DATA1_BASE_IDX      0
 446 #define mmSDMA0_RLC0_MIDCMD_DATA2       0x0182
 447 #define mmSDMA0_RLC0_MIDCMD_DATA2_BASE_IDX      0
 448 #define mmSDMA0_RLC0_MIDCMD_DATA3       0x0183
 449 #define mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX      0
 450 #define mmSDMA0_RLC0_MIDCMD_DATA4       0x0184
 451 #define mmSDMA0_RLC0_MIDCMD_DATA4_BASE_IDX      0
 452 #define mmSDMA0_RLC0_MIDCMD_DATA5       0x0185
 453 #define mmSDMA0_RLC0_MIDCMD_DATA5_BASE_IDX      0
 454 #define mmSDMA0_RLC0_MIDCMD_DATA6       0x0186
 455 #define mmSDMA0_RLC0_MIDCMD_DATA6_BASE_IDX      0
 456 #define mmSDMA0_RLC0_MIDCMD_DATA7       0x0187
 457 #define mmSDMA0_RLC0_MIDCMD_DATA7_BASE_IDX      0
 458 #define mmSDMA0_RLC0_MIDCMD_DATA8       0x0188
 459 #define mmSDMA0_RLC0_MIDCMD_DATA8_BASE_IDX      0
 460 #define mmSDMA0_RLC0_MIDCMD_CNTL        0x0189
 461 #define mmSDMA0_RLC0_MIDCMD_CNTL_BASE_IDX       0
 462 #define mmSDMA0_RLC1_RB_CNTL    0x01a0
 463 #define mmSDMA0_RLC1_RB_CNTL_BASE_IDX   0
 464 #define mmSDMA0_RLC1_RB_BASE    0x01a1
 465 #define mmSDMA0_RLC1_RB_BASE_BASE_IDX   0
 466 #define mmSDMA0_RLC1_RB_BASE_HI 0x01a2
 467 #define mmSDMA0_RLC1_RB_BASE_HI_BASE_IDX        0
 468 #define mmSDMA0_RLC1_RB_RPTR    0x01a3
 469 #define mmSDMA0_RLC1_RB_RPTR_BASE_IDX   0
 470 #define mmSDMA0_RLC1_RB_RPTR_HI 0x01a4
 471 #define mmSDMA0_RLC1_RB_RPTR_HI_BASE_IDX        0
 472 #define mmSDMA0_RLC1_RB_WPTR    0x01a5
 473 #define mmSDMA0_RLC1_RB_WPTR_BASE_IDX   0
 474 #define mmSDMA0_RLC1_RB_WPTR_HI 0x01a6
 475 #define mmSDMA0_RLC1_RB_WPTR_HI_BASE_IDX        0
 476 #define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL  0x01a7
 477 #define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0
 478 #define mmSDMA0_RLC1_RB_RPTR_ADDR_HI    0x01a8
 479 #define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX   0
 480 #define mmSDMA0_RLC1_RB_RPTR_ADDR_LO    0x01a9
 481 #define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_BASE_IDX   0
 482 #define mmSDMA0_RLC1_IB_CNTL    0x01aa
 483 #define mmSDMA0_RLC1_IB_CNTL_BASE_IDX   0
 484 #define mmSDMA0_RLC1_IB_RPTR    0x01ab
 485 #define mmSDMA0_RLC1_IB_RPTR_BASE_IDX   0
 486 #define mmSDMA0_RLC1_IB_OFFSET  0x01ac
 487 #define mmSDMA0_RLC1_IB_OFFSET_BASE_IDX 0
 488 #define mmSDMA0_RLC1_IB_BASE_LO 0x01ad
 489 #define mmSDMA0_RLC1_IB_BASE_LO_BASE_IDX        0
 490 #define mmSDMA0_RLC1_IB_BASE_HI 0x01ae
 491 #define mmSDMA0_RLC1_IB_BASE_HI_BASE_IDX        0
 492 #define mmSDMA0_RLC1_IB_SIZE    0x01af
 493 #define mmSDMA0_RLC1_IB_SIZE_BASE_IDX   0
 494 #define mmSDMA0_RLC1_SKIP_CNTL  0x01b0
 495 #define mmSDMA0_RLC1_SKIP_CNTL_BASE_IDX 0
 496 #define mmSDMA0_RLC1_CONTEXT_STATUS     0x01b1
 497 #define mmSDMA0_RLC1_CONTEXT_STATUS_BASE_IDX    0
 498 #define mmSDMA0_RLC1_DOORBELL   0x01b2
 499 #define mmSDMA0_RLC1_DOORBELL_BASE_IDX  0
 500 #define mmSDMA0_RLC1_STATUS     0x01c8
 501 #define mmSDMA0_RLC1_STATUS_BASE_IDX    0
 502 #define mmSDMA0_RLC1_DOORBELL_LOG       0x01c9
 503 #define mmSDMA0_RLC1_DOORBELL_LOG_BASE_IDX      0
 504 #define mmSDMA0_RLC1_WATERMARK  0x01ca
 505 #define mmSDMA0_RLC1_WATERMARK_BASE_IDX 0
 506 #define mmSDMA0_RLC1_DOORBELL_OFFSET    0x01cb
 507 #define mmSDMA0_RLC1_DOORBELL_OFFSET_BASE_IDX   0
 508 #define mmSDMA0_RLC1_CSA_ADDR_LO        0x01cc
 509 #define mmSDMA0_RLC1_CSA_ADDR_LO_BASE_IDX       0
 510 #define mmSDMA0_RLC1_CSA_ADDR_HI        0x01cd
 511 #define mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX       0
 512 #define mmSDMA0_RLC1_IB_SUB_REMAIN      0x01cf
 513 #define mmSDMA0_RLC1_IB_SUB_REMAIN_BASE_IDX     0
 514 #define mmSDMA0_RLC1_PREEMPT    0x01d0
 515 #define mmSDMA0_RLC1_PREEMPT_BASE_IDX   0
 516 #define mmSDMA0_RLC1_DUMMY_REG  0x01d1
 517 #define mmSDMA0_RLC1_DUMMY_REG_BASE_IDX 0
 518 #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI       0x01d2
 519 #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX      0
 520 #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO       0x01d3
 521 #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX      0
 522 #define mmSDMA0_RLC1_RB_AQL_CNTL        0x01d4
 523 #define mmSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX       0
 524 #define mmSDMA0_RLC1_MINOR_PTR_UPDATE   0x01d5
 525 #define mmSDMA0_RLC1_MINOR_PTR_UPDATE_BASE_IDX  0
 526 #define mmSDMA0_RLC1_MIDCMD_DATA0       0x01e0
 527 #define mmSDMA0_RLC1_MIDCMD_DATA0_BASE_IDX      0
 528 #define mmSDMA0_RLC1_MIDCMD_DATA1       0x01e1
 529 #define mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX      0
 530 #define mmSDMA0_RLC1_MIDCMD_DATA2       0x01e2
 531 #define mmSDMA0_RLC1_MIDCMD_DATA2_BASE_IDX      0
 532 #define mmSDMA0_RLC1_MIDCMD_DATA3       0x01e3
 533 #define mmSDMA0_RLC1_MIDCMD_DATA3_BASE_IDX      0
 534 #define mmSDMA0_RLC1_MIDCMD_DATA4       0x01e4
 535 #define mmSDMA0_RLC1_MIDCMD_DATA4_BASE_IDX      0
 536 #define mmSDMA0_RLC1_MIDCMD_DATA5       0x01e5
 537 #define mmSDMA0_RLC1_MIDCMD_DATA5_BASE_IDX      0
 538 #define mmSDMA0_RLC1_MIDCMD_DATA6       0x01e6
 539 #define mmSDMA0_RLC1_MIDCMD_DATA6_BASE_IDX      0
 540 #define mmSDMA0_RLC1_MIDCMD_DATA7       0x01e7
 541 #define mmSDMA0_RLC1_MIDCMD_DATA7_BASE_IDX      0
 542 #define mmSDMA0_RLC1_MIDCMD_DATA8       0x01e8
 543 #define mmSDMA0_RLC1_MIDCMD_DATA8_BASE_IDX      0
 544 #define mmSDMA0_RLC1_MIDCMD_CNTL        0x01e9
 545 #define mmSDMA0_RLC1_MIDCMD_CNTL_BASE_IDX       0
 546 
 547 #endif
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h

INCLUDED FROM
