root/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

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   1 /*
   2  * Copyright (C) 2019  Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  */
  21 #ifndef _gc_10_1_0_SH_MASK_HEADER
  22 #define _gc_10_1_0_SH_MASK_HEADER
  23 
  24 
  25 // addressBlock: gc_sdma0_sdma0dec
  26 //SDMA0_DEC_START
  27 #define SDMA0_DEC_START__START__SHIFT                                                                         0x0
  28 #define SDMA0_DEC_START__START_MASK                                                                           0xFFFFFFFFL
  29 //SDMA0_PG_CNTL
  30 #define SDMA0_PG_CNTL__CMD__SHIFT                                                                             0x0
  31 #define SDMA0_PG_CNTL__STATUS__SHIFT                                                                          0x10
  32 #define SDMA0_PG_CNTL__CMD_MASK                                                                               0x0000000FL
  33 #define SDMA0_PG_CNTL__STATUS_MASK                                                                            0x000F0000L
  34 //SDMA0_PG_CTX_LO
  35 #define SDMA0_PG_CTX_LO__ADDR__SHIFT                                                                          0x0
  36 #define SDMA0_PG_CTX_LO__ADDR_MASK                                                                            0xFFFFFFFFL
  37 //SDMA0_PG_CTX_HI
  38 #define SDMA0_PG_CTX_HI__ADDR__SHIFT                                                                          0x0
  39 #define SDMA0_PG_CTX_HI__ADDR_MASK                                                                            0xFFFFFFFFL
  40 //SDMA0_PG_CTX_CNTL
  41 #define SDMA0_PG_CTX_CNTL__VMID__SHIFT                                                                        0x0
  42 #define SDMA0_PG_CTX_CNTL__VMID_MASK                                                                          0x0000000FL
  43 //SDMA0_POWER_CNTL
  44 #define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT                                                               0x0
  45 #define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT                                                          0x1
  46 #define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT                                                         0x2
  47 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT                                                   0x3
  48 #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT                                                           0x8
  49 #define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT                                                              0x9
  50 #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT                                                              0xa
  51 #define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT                                                              0xb
  52 #define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT                                                              0xc
  53 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT                                                  0x1a
  54 #define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK                                                                 0x00000001L
  55 #define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK                                                            0x00000002L
  56 #define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK                                                           0x00000004L
  57 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK                                                     0x000000F8L
  58 #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK                                                             0x00000100L
  59 #define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK                                                                0x00000200L
  60 #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK                                                                0x00000400L
  61 #define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK                                                                0x00000800L
  62 #define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK                                                                0x003FF000L
  63 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK                                                    0xFC000000L
  64 //SDMA0_CLK_CTRL
  65 #define SDMA0_CLK_CTRL__ON_DELAY__SHIFT                                                                       0x0
  66 #define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                                 0x4
  67 #define SDMA0_CLK_CTRL__RESERVED__SHIFT                                                                       0xc
  68 #define SDMA0_CLK_CTRL__UTCL1_FORCE_INV_RET_FIFO_FULL_EN__SHIFT                                               0x17
  69 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                                 0x18
  70 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                                 0x19
  71 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                                 0x1a
  72 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                                 0x1b
  73 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                                 0x1c
  74 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                                 0x1d
  75 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                                 0x1e
  76 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                                 0x1f
  77 #define SDMA0_CLK_CTRL__ON_DELAY_MASK                                                                         0x0000000FL
  78 #define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                   0x00000FF0L
  79 #define SDMA0_CLK_CTRL__RESERVED_MASK                                                                         0x007FF000L
  80 #define SDMA0_CLK_CTRL__UTCL1_FORCE_INV_RET_FIFO_FULL_EN_MASK                                                 0x00800000L
  81 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                                   0x01000000L
  82 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                                   0x02000000L
  83 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                                   0x04000000L
  84 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                                   0x08000000L
  85 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                                   0x10000000L
  86 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                                   0x20000000L
  87 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK                                                                   0x40000000L
  88 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK                                                                   0x80000000L
  89 //SDMA0_CNTL
  90 #define SDMA0_CNTL__TRAP_ENABLE__SHIFT                                                                        0x0
  91 #define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT                                                                      0x1
  92 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT                                                                0x2
  93 #define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT                                                                   0x3
  94 #define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT                                                                  0x4
  95 #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                              0x5
  96 #define SDMA0_CNTL__PAGE_INT_ENABLE__SHIFT                                                                    0x7
  97 #define SDMA0_CNTL__CH_PERFCNT_ENABLE__SHIFT                                                                  0x10
  98 #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT                                                          0x11
  99 #define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT                                                                  0x12
 100 #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT                                                                0x1c
 101 #define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT                                                                  0x1d
 102 #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT                                                              0x1e
 103 #define SDMA0_CNTL__TRAP_ENABLE_MASK                                                                          0x00000001L
 104 #define SDMA0_CNTL__UTC_L1_ENABLE_MASK                                                                        0x00000002L
 105 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK                                                                  0x00000004L
 106 #define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK                                                                     0x00000008L
 107 #define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK                                                                    0x00000010L
 108 #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                                0x00000020L
 109 #define SDMA0_CNTL__PAGE_INT_ENABLE_MASK                                                                      0x00000080L
 110 #define SDMA0_CNTL__CH_PERFCNT_ENABLE_MASK                                                                    0x00010000L
 111 #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK                                                            0x00020000L
 112 #define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK                                                                    0x00040000L
 113 #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK                                                                  0x10000000L
 114 #define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK                                                                    0x20000000L
 115 #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK                                                                0x40000000L
 116 //SDMA0_CHICKEN_BITS
 117 #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT                                                     0x0
 118 #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT                                                 0x1
 119 #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT                                        0x2
 120 #define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT                                                         0x8
 121 #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT                                                     0xa
 122 #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT                                                        0x10
 123 #define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT                                                           0x11
 124 #define SDMA0_CHICKEN_BITS__T2L_256B_ENABLE__SHIFT                                                            0x12
 125 #define SDMA0_CHICKEN_BITS__GCR_FGCG_ENABLE__SHIFT                                                            0x13
 126 #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT                                                         0x14
 127 #define SDMA0_CHICKEN_BITS__CH_FGCG_ENABLE__SHIFT                                                             0x15
 128 #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT                                                           0x17
 129 #define SDMA0_CHICKEN_BITS__UTCL1_FGCG_ENABLE__SHIFT                                                          0x18
 130 #define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT                                                             0x19
 131 #define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT                                                         0x1a
 132 #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT                                                         0x1c
 133 #define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT                                                         0x1e
 134 #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK                                                       0x00000001L
 135 #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK                                                   0x00000002L
 136 #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK                                          0x00000004L
 137 #define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK                                                           0x00000300L
 138 #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK                                                       0x00001C00L
 139 #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK                                                          0x00010000L
 140 #define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK                                                             0x00020000L
 141 #define SDMA0_CHICKEN_BITS__T2L_256B_ENABLE_MASK                                                              0x00040000L
 142 #define SDMA0_CHICKEN_BITS__GCR_FGCG_ENABLE_MASK                                                              0x00080000L
 143 #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK                                                           0x00100000L
 144 #define SDMA0_CHICKEN_BITS__CH_FGCG_ENABLE_MASK                                                               0x00200000L
 145 #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK                                                             0x00800000L
 146 #define SDMA0_CHICKEN_BITS__UTCL1_FGCG_ENABLE_MASK                                                            0x01000000L
 147 #define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK                                                               0x02000000L
 148 #define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK                                                           0x0C000000L
 149 #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK                                                           0x30000000L
 150 #define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK                                                           0xC0000000L
 151 //SDMA0_GB_ADDR_CONFIG
 152 #define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT                                                                0x0
 153 #define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                     0x3
 154 #define SDMA0_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                     0x6
 155 #define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT                                                     0x8
 156 #define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT                                                                0xc
 157 #define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT                                                       0x13
 158 #define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK                                                                  0x00000007L
 159 #define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                       0x00000038L
 160 #define SDMA0_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                       0x000000C0L
 161 #define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK                                                       0x00000700L
 162 #define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK                                                                  0x00007000L
 163 #define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK                                                         0x00180000L
 164 //SDMA0_GB_ADDR_CONFIG_READ
 165 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT                                                           0x0
 166 #define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT                                                0x3
 167 #define SDMA0_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT                                                0x6
 168 #define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT                                                0x8
 169 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT                                                           0xc
 170 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT                                                  0x13
 171 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK                                                             0x00000007L
 172 #define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK                                                  0x00000038L
 173 #define SDMA0_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK                                                  0x000000C0L
 174 #define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK                                                  0x00000700L
 175 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK                                                             0x00007000L
 176 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK                                                    0x00180000L
 177 //SDMA0_RB_RPTR_FETCH_HI
 178 #define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT                                                                 0x0
 179 #define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK                                                                   0xFFFFFFFFL
 180 //SDMA0_SEM_WAIT_FAIL_TIMER_CNTL
 181 #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT                                                          0x0
 182 #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK                                                            0xFFFFFFFFL
 183 //SDMA0_RB_RPTR_FETCH
 184 #define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT                                                                    0x2
 185 #define SDMA0_RB_RPTR_FETCH__OFFSET_MASK                                                                      0xFFFFFFFCL
 186 //SDMA0_IB_OFFSET_FETCH
 187 #define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT                                                                  0x2
 188 #define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK                                                                    0x003FFFFCL
 189 //SDMA0_PROGRAM
 190 #define SDMA0_PROGRAM__STREAM__SHIFT                                                                          0x0
 191 #define SDMA0_PROGRAM__STREAM_MASK                                                                            0xFFFFFFFFL
 192 //SDMA0_STATUS_REG
 193 #define SDMA0_STATUS_REG__IDLE__SHIFT                                                                         0x0
 194 #define SDMA0_STATUS_REG__REG_IDLE__SHIFT                                                                     0x1
 195 #define SDMA0_STATUS_REG__RB_EMPTY__SHIFT                                                                     0x2
 196 #define SDMA0_STATUS_REG__RB_FULL__SHIFT                                                                      0x3
 197 #define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT                                                                  0x4
 198 #define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT                                                                  0x5
 199 #define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT                                                                  0x6
 200 #define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT                                                                  0x7
 201 #define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT                                                                   0x8
 202 #define SDMA0_STATUS_REG__INSIDE_IB__SHIFT                                                                    0x9
 203 #define SDMA0_STATUS_REG__EX_IDLE__SHIFT                                                                      0xa
 204 #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT                                                    0xb
 205 #define SDMA0_STATUS_REG__PACKET_READY__SHIFT                                                                 0xc
 206 #define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT                                                                   0xd
 207 #define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT                                                                    0xe
 208 #define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT                                                                0xf
 209 #define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT                                                              0x10
 210 #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT                                                              0x11
 211 #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT                                                              0x12
 212 #define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT                                                                   0x13
 213 #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT                                                             0x14
 214 #define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT                                                              0x15
 215 #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT                                                           0x16
 216 #define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT                                                                0x19
 217 #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT                                                                     0x1a
 218 #define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT                                                                0x1b
 219 #define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT                                                               0x1c
 220 #define SDMA0_STATUS_REG__INT_IDLE__SHIFT                                                                     0x1e
 221 #define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT                                                                0x1f
 222 #define SDMA0_STATUS_REG__IDLE_MASK                                                                           0x00000001L
 223 #define SDMA0_STATUS_REG__REG_IDLE_MASK                                                                       0x00000002L
 224 #define SDMA0_STATUS_REG__RB_EMPTY_MASK                                                                       0x00000004L
 225 #define SDMA0_STATUS_REG__RB_FULL_MASK                                                                        0x00000008L
 226 #define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK                                                                    0x00000010L
 227 #define SDMA0_STATUS_REG__RB_CMD_FULL_MASK                                                                    0x00000020L
 228 #define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK                                                                    0x00000040L
 229 #define SDMA0_STATUS_REG__IB_CMD_FULL_MASK                                                                    0x00000080L
 230 #define SDMA0_STATUS_REG__BLOCK_IDLE_MASK                                                                     0x00000100L
 231 #define SDMA0_STATUS_REG__INSIDE_IB_MASK                                                                      0x00000200L
 232 #define SDMA0_STATUS_REG__EX_IDLE_MASK                                                                        0x00000400L
 233 #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK                                                      0x00000800L
 234 #define SDMA0_STATUS_REG__PACKET_READY_MASK                                                                   0x00001000L
 235 #define SDMA0_STATUS_REG__MC_WR_IDLE_MASK                                                                     0x00002000L
 236 #define SDMA0_STATUS_REG__SRBM_IDLE_MASK                                                                      0x00004000L
 237 #define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK                                                                  0x00008000L
 238 #define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK                                                                0x00010000L
 239 #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK                                                                0x00020000L
 240 #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK                                                                0x00040000L
 241 #define SDMA0_STATUS_REG__MC_RD_IDLE_MASK                                                                     0x00080000L
 242 #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK                                                               0x00100000L
 243 #define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK                                                                0x00200000L
 244 #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK                                                             0x00400000L
 245 #define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK                                                                  0x02000000L
 246 #define SDMA0_STATUS_REG__SEM_IDLE_MASK                                                                       0x04000000L
 247 #define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK                                                                  0x08000000L
 248 #define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK                                                                 0x30000000L
 249 #define SDMA0_STATUS_REG__INT_IDLE_MASK                                                                       0x40000000L
 250 #define SDMA0_STATUS_REG__INT_REQ_STALL_MASK                                                                  0x80000000L
 251 //SDMA0_STATUS1_REG
 252 #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT                                                                0x0
 253 #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT                                                                  0x1
 254 #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT                                                               0x2
 255 #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT                                                                0x3
 256 #define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT                                                                 0x4
 257 #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT                                                                  0x5
 258 #define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT                                                                 0x6
 259 #define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT                                                                 0x9
 260 #define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT                                                               0xa
 261 #define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT                                                                0xd
 262 #define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT                                                               0xe
 263 #define SDMA0_STATUS1_REG__EX_START__SHIFT                                                                    0xf
 264 #define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT                                                                 0x11
 265 #define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT                                                                 0x12
 266 #define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK                                                                  0x00000001L
 267 #define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK                                                                    0x00000002L
 268 #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK                                                                 0x00000004L
 269 #define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK                                                                  0x00000008L
 270 #define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK                                                                   0x00000010L
 271 #define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK                                                                    0x00000020L
 272 #define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK                                                                   0x00000040L
 273 #define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK                                                                   0x00000200L
 274 #define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK                                                                 0x00000400L
 275 #define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK                                                                  0x00002000L
 276 #define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK                                                                 0x00004000L
 277 #define SDMA0_STATUS1_REG__EX_START_MASK                                                                      0x00008000L
 278 #define SDMA0_STATUS1_REG__CE_RD_STALL_MASK                                                                   0x00020000L
 279 #define SDMA0_STATUS1_REG__CE_WR_STALL_MASK                                                                   0x00040000L
 280 //SDMA0_RD_BURST_CNTL
 281 #define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT                                                                  0x0
 282 #define SDMA0_RD_BURST_CNTL__RD_BURST_MASK                                                                    0x00000003L
 283 //SDMA0_HBM_PAGE_CONFIG
 284 #define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT                                                      0x0
 285 #define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK                                                        0x00000003L
 286 //SDMA0_UCODE_CHECKSUM
 287 #define SDMA0_UCODE_CHECKSUM__DATA__SHIFT                                                                     0x0
 288 #define SDMA0_UCODE_CHECKSUM__DATA_MASK                                                                       0xFFFFFFFFL
 289 //SDMA0_F32_CNTL
 290 #define SDMA0_F32_CNTL__HALT__SHIFT                                                                           0x0
 291 #define SDMA0_F32_CNTL__STEP__SHIFT                                                                           0x1
 292 #define SDMA0_F32_CNTL__CHECKSUM_CLR__SHIFT                                                                   0x8
 293 #define SDMA0_F32_CNTL__RESET__SHIFT                                                                          0x9
 294 #define SDMA0_F32_CNTL__HALT_MASK                                                                             0x00000001L
 295 #define SDMA0_F32_CNTL__STEP_MASK                                                                             0x00000002L
 296 #define SDMA0_F32_CNTL__CHECKSUM_CLR_MASK                                                                     0x00000100L
 297 #define SDMA0_F32_CNTL__RESET_MASK                                                                            0x00000200L
 298 //SDMA0_FREEZE
 299 #define SDMA0_FREEZE__PREEMPT__SHIFT                                                                          0x0
 300 #define SDMA0_FREEZE__FORCE_PREEMPT__SHIFT                                                                    0x1
 301 #define SDMA0_FREEZE__FREEZE__SHIFT                                                                           0x4
 302 #define SDMA0_FREEZE__FROZEN__SHIFT                                                                           0x5
 303 #define SDMA0_FREEZE__F32_FREEZE__SHIFT                                                                       0x6
 304 #define SDMA0_FREEZE__PREEMPT_MASK                                                                            0x00000001L
 305 #define SDMA0_FREEZE__FORCE_PREEMPT_MASK                                                                      0x00000002L
 306 #define SDMA0_FREEZE__FREEZE_MASK                                                                             0x00000010L
 307 #define SDMA0_FREEZE__FROZEN_MASK                                                                             0x00000020L
 308 #define SDMA0_FREEZE__F32_FREEZE_MASK                                                                         0x00000040L
 309 //SDMA0_PHASE0_QUANTUM
 310 #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT                                                                     0x0
 311 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT                                                                    0x8
 312 #define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT                                                                   0x1e
 313 #define SDMA0_PHASE0_QUANTUM__UNIT_MASK                                                                       0x0000000FL
 314 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
 315 #define SDMA0_PHASE0_QUANTUM__PREFER_MASK                                                                     0x40000000L
 316 //SDMA0_PHASE1_QUANTUM
 317 #define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT                                                                     0x0
 318 #define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT                                                                    0x8
 319 #define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT                                                                   0x1e
 320 #define SDMA0_PHASE1_QUANTUM__UNIT_MASK                                                                       0x0000000FL
 321 #define SDMA0_PHASE1_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
 322 #define SDMA0_PHASE1_QUANTUM__PREFER_MASK                                                                     0x40000000L
 323 //SDMA_POWER_GATING
 324 #define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT                                                   0x0
 325 #define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT                                                    0x1
 326 #define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT                                                         0x2
 327 #define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT                                                          0x3
 328 #define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT                                                              0x4
 329 #define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK                                                     0x00000001L
 330 #define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK                                                      0x00000002L
 331 #define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK                                                           0x00000004L
 332 #define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK                                                            0x00000008L
 333 #define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK                                                                0x00000030L
 334 //SDMA_PGFSM_CONFIG
 335 #define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT                                                                    0x0
 336 #define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT                                                                  0x8
 337 #define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT                                                                    0x9
 338 #define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT                                                                   0xa
 339 #define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT                                                                   0xb
 340 #define SDMA_PGFSM_CONFIG__WRITE__SHIFT                                                                       0xc
 341 #define SDMA_PGFSM_CONFIG__READ__SHIFT                                                                        0xd
 342 #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT                                                               0x1b
 343 #define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT                                                                    0x1c
 344 #define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK                                                                      0x000000FFL
 345 #define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK                                                                    0x00000100L
 346 #define SDMA_PGFSM_CONFIG__POWER_UP_MASK                                                                      0x00000200L
 347 #define SDMA_PGFSM_CONFIG__P1_SELECT_MASK                                                                     0x00000400L
 348 #define SDMA_PGFSM_CONFIG__P2_SELECT_MASK                                                                     0x00000800L
 349 #define SDMA_PGFSM_CONFIG__WRITE_MASK                                                                         0x00001000L
 350 #define SDMA_PGFSM_CONFIG__READ_MASK                                                                          0x00002000L
 351 #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK                                                                 0x08000000L
 352 #define SDMA_PGFSM_CONFIG__REG_ADDR_MASK                                                                      0xF0000000L
 353 //SDMA_PGFSM_WRITE
 354 #define SDMA_PGFSM_WRITE__VALUE__SHIFT                                                                        0x0
 355 #define SDMA_PGFSM_WRITE__VALUE_MASK                                                                          0xFFFFFFFFL
 356 //SDMA_PGFSM_READ
 357 #define SDMA_PGFSM_READ__VALUE__SHIFT                                                                         0x0
 358 #define SDMA_PGFSM_READ__VALUE_MASK                                                                           0x00FFFFFFL
 359 //SDMA0_EDC_CONFIG
 360 #define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT                                                                      0x1
 361 #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT                                                               0x2
 362 #define SDMA0_EDC_CONFIG__DIS_EDC_MASK                                                                        0x00000002L
 363 #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK                                                                 0x00000004L
 364 //SDMA0_BA_THRESHOLD
 365 #define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT                                                                 0x0
 366 #define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT                                                                0x10
 367 #define SDMA0_BA_THRESHOLD__READ_THRES_MASK                                                                   0x000003FFL
 368 #define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK                                                                  0x03FF0000L
 369 //SDMA0_ID
 370 #define SDMA0_ID__DEVICE_ID__SHIFT                                                                            0x0
 371 #define SDMA0_ID__DEVICE_ID_MASK                                                                              0x000000FFL
 372 //SDMA0_VERSION
 373 #define SDMA0_VERSION__MINVER__SHIFT                                                                          0x0
 374 #define SDMA0_VERSION__MAJVER__SHIFT                                                                          0x8
 375 #define SDMA0_VERSION__REV__SHIFT                                                                             0x10
 376 #define SDMA0_VERSION__MINVER_MASK                                                                            0x0000007FL
 377 #define SDMA0_VERSION__MAJVER_MASK                                                                            0x00007F00L
 378 #define SDMA0_VERSION__REV_MASK                                                                               0x003F0000L
 379 //SDMA0_EDC_COUNTER
 380 #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT                                                          0x0
 381 #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT                                                          0x1
 382 #define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT                                                         0x2
 383 #define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT                                                         0x3
 384 #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT                                                      0x4
 385 #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT                                                   0x5
 386 #define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT                                                      0x6
 387 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT                                                    0x7
 388 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT                                                    0x8
 389 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT                                                    0x9
 390 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT                                                    0xa
 391 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT                                                    0xb
 392 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT                                                    0xc
 393 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT                                                    0xd
 394 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT                                                    0xe
 395 #define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT                                                      0xf
 396 #define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT                                                    0x10
 397 #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK                                                            0x00000001L
 398 #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK                                                            0x00000002L
 399 #define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK                                                           0x00000004L
 400 #define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK                                                           0x00000008L
 401 #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK                                                        0x00000010L
 402 #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK                                                     0x00000020L
 403 #define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK                                                        0x00000040L
 404 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK                                                      0x00000080L
 405 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK                                                      0x00000100L
 406 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK                                                      0x00000200L
 407 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK                                                      0x00000400L
 408 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK                                                      0x00000800L
 409 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK                                                      0x00001000L
 410 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK                                                      0x00002000L
 411 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK                                                      0x00004000L
 412 #define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK                                                        0x00008000L
 413 #define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK                                                      0x00010000L
 414 //SDMA0_EDC_COUNTER_CLEAR
 415 #define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT                                                                 0x0
 416 #define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK                                                                   0x00000001L
 417 //SDMA0_STATUS2_REG
 418 #define SDMA0_STATUS2_REG__ID__SHIFT                                                                          0x0
 419 #define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT                                                               0x2
 420 #define SDMA0_STATUS2_REG__CMD_OP__SHIFT                                                                      0x10
 421 #define SDMA0_STATUS2_REG__ID_MASK                                                                            0x00000003L
 422 #define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK                                                                 0x00000FFCL
 423 #define SDMA0_STATUS2_REG__CMD_OP_MASK                                                                        0xFFFF0000L
 424 //SDMA0_ATOMIC_CNTL
 425 #define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT                                                                  0x0
 426 #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT                                                       0x1f
 427 #define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK                                                                    0x7FFFFFFFL
 428 #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK                                                         0x80000000L
 429 //SDMA0_ATOMIC_PREOP_LO
 430 #define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT                                                                    0x0
 431 #define SDMA0_ATOMIC_PREOP_LO__DATA_MASK                                                                      0xFFFFFFFFL
 432 //SDMA0_ATOMIC_PREOP_HI
 433 #define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT                                                                    0x0
 434 #define SDMA0_ATOMIC_PREOP_HI__DATA_MASK                                                                      0xFFFFFFFFL
 435 //SDMA0_UTCL1_CNTL
 436 #define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT                                                                  0x0
 437 #define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT                                                                   0x1
 438 #define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT                                                                 0x6
 439 #define SDMA0_UTCL1_CNTL__RESP_MODE__SHIFT                                                                    0x9
 440 #define SDMA0_UTCL1_CNTL__FORCE_INVALIDATION__SHIFT                                                           0xe
 441 #define SDMA0_UTCL1_CNTL__FORCE_INVREQ_HEAVY__SHIFT                                                           0xf
 442 #define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT                                                                 0x10
 443 #define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT                                                                 0x18
 444 #define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT                                                                0x1d
 445 #define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK                                                                    0x00000001L
 446 #define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK                                                                     0x0000003EL
 447 #define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK                                                                   0x000001C0L
 448 #define SDMA0_UTCL1_CNTL__RESP_MODE_MASK                                                                      0x00000E00L
 449 #define SDMA0_UTCL1_CNTL__FORCE_INVALIDATION_MASK                                                             0x00004000L
 450 #define SDMA0_UTCL1_CNTL__FORCE_INVREQ_HEAVY_MASK                                                             0x00008000L
 451 #define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK                                                                   0x00FF0000L
 452 #define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK                                                                   0x1F000000L
 453 #define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK                                                                  0xE0000000L
 454 //SDMA0_UTCL1_WATERMK
 455 #define SDMA0_UTCL1_WATERMK__REQMC_WATERMK__SHIFT                                                             0x0
 456 #define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT                                                             0xa
 457 #define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT                                                            0x12
 458 #define SDMA0_UTCL1_WATERMK__XNACK_WATERMK__SHIFT                                                             0x1a
 459 #define SDMA0_UTCL1_WATERMK__REQMC_WATERMK_MASK                                                               0x000003FFL
 460 #define SDMA0_UTCL1_WATERMK__REQPG_WATERMK_MASK                                                               0x0003FC00L
 461 #define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK                                                              0x03FC0000L
 462 #define SDMA0_UTCL1_WATERMK__XNACK_WATERMK_MASK                                                               0xFC000000L
 463 //SDMA0_UTCL1_RD_STATUS
 464 #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT                                                0x0
 465 #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT                                                 0x1
 466 #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT                                                     0x2
 467 #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT                                                      0x3
 468 #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT                                                      0x4
 469 #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT                                                       0x5
 470 #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT                                                   0x6
 471 #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT                                                    0x7
 472 #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT                                                    0x8
 473 #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT                                                     0x9
 474 #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT                                                 0xa
 475 #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT                                                  0xb
 476 #define SDMA0_UTCL1_RD_STATUS__REDO_ARR_EMPTY__SHIFT                                                          0xc
 477 #define SDMA0_UTCL1_RD_STATUS__REDO_ARR_FULL__SHIFT                                                           0xd
 478 #define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT                                                              0xe
 479 #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT                                                               0xf
 480 #define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT                                                              0x10
 481 #define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT                                                          0x11
 482 #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT                                                             0x15
 483 #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT                                                             0x18
 484 #define SDMA0_UTCL1_RD_STATUS__RD_XNACK_TIMEOUT__SHIFT                                                        0x19
 485 #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_SW__SHIFT                                                            0x1a
 486 #define SDMA0_UTCL1_RD_STATUS__HIT_CACHE__SHIFT                                                               0x1b
 487 #define SDMA0_UTCL1_RD_STATUS__RD_DCC_ENABLE__SHIFT                                                           0x1c
 488 #define SDMA0_UTCL1_RD_STATUS__NACK_TIMEOUT_SW__SHIFT                                                         0x1d
 489 #define SDMA0_UTCL1_RD_STATUS__DCC_PAGE_FAULT__SHIFT                                                          0x1e
 490 #define SDMA0_UTCL1_RD_STATUS__DCC_PAGE_NULL__SHIFT                                                           0x1f
 491 #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK                                                  0x00000001L
 492 #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK                                                   0x00000002L
 493 #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK                                                       0x00000004L
 494 #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK                                                        0x00000008L
 495 #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK                                                        0x00000010L
 496 #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK                                                         0x00000020L
 497 #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK                                                     0x00000040L
 498 #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK                                                      0x00000080L
 499 #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK                                                      0x00000100L
 500 #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK                                                       0x00000200L
 501 #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK                                                   0x00000400L
 502 #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK                                                    0x00000800L
 503 #define SDMA0_UTCL1_RD_STATUS__REDO_ARR_EMPTY_MASK                                                            0x00001000L
 504 #define SDMA0_UTCL1_RD_STATUS__REDO_ARR_FULL_MASK                                                             0x00002000L
 505 #define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK                                                                0x00004000L
 506 #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK                                                                 0x00008000L
 507 #define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK                                                                0x00010000L
 508 #define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK                                                            0x001E0000L
 509 #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK                                                               0x00E00000L
 510 #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK                                                               0x01000000L
 511 #define SDMA0_UTCL1_RD_STATUS__RD_XNACK_TIMEOUT_MASK                                                          0x02000000L
 512 #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_SW_MASK                                                              0x04000000L
 513 #define SDMA0_UTCL1_RD_STATUS__HIT_CACHE_MASK                                                                 0x08000000L
 514 #define SDMA0_UTCL1_RD_STATUS__RD_DCC_ENABLE_MASK                                                             0x10000000L
 515 #define SDMA0_UTCL1_RD_STATUS__NACK_TIMEOUT_SW_MASK                                                           0x20000000L
 516 #define SDMA0_UTCL1_RD_STATUS__DCC_PAGE_FAULT_MASK                                                            0x40000000L
 517 #define SDMA0_UTCL1_RD_STATUS__DCC_PAGE_NULL_MASK                                                             0x80000000L
 518 //SDMA0_UTCL1_WR_STATUS
 519 #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT                                                0x0
 520 #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT                                                 0x1
 521 #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT                                                     0x2
 522 #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT                                                      0x3
 523 #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT                                                      0x4
 524 #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT                                                       0x5
 525 #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT                                                   0x6
 526 #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT                                                    0x7
 527 #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT                                                    0x8
 528 #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT                                                     0x9
 529 #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT                                                 0xa
 530 #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT                                                  0xb
 531 #define SDMA0_UTCL1_WR_STATUS__REDO_ARR_EMPTY__SHIFT                                                          0xc
 532 #define SDMA0_UTCL1_WR_STATUS__REDO_ARR_FULL__SHIFT                                                           0xd
 533 #define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT                                                              0xe
 534 #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT                                                               0xf
 535 #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT                                                              0x10
 536 #define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT                                                          0x11
 537 #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT                                                             0x15
 538 #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT                                                              0x18
 539 #define SDMA0_UTCL1_WR_STATUS__WR_XNACK_TIMEOUT__SHIFT                                                        0x19
 540 #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_SW__SHIFT                                                            0x1a
 541 #define SDMA0_UTCL1_WR_STATUS__ATOMIC_OP__SHIFT                                                               0x1b
 542 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT                                                    0x1c
 543 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT                                                     0x1d
 544 #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT                                                   0x1e
 545 #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT                                                    0x1f
 546 #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK                                                  0x00000001L
 547 #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK                                                   0x00000002L
 548 #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK                                                       0x00000004L
 549 #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK                                                        0x00000008L
 550 #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK                                                        0x00000010L
 551 #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK                                                         0x00000020L
 552 #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK                                                     0x00000040L
 553 #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK                                                      0x00000080L
 554 #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK                                                      0x00000100L
 555 #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK                                                       0x00000200L
 556 #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK                                                   0x00000400L
 557 #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK                                                    0x00000800L
 558 #define SDMA0_UTCL1_WR_STATUS__REDO_ARR_EMPTY_MASK                                                            0x00001000L
 559 #define SDMA0_UTCL1_WR_STATUS__REDO_ARR_FULL_MASK                                                             0x00002000L
 560 #define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK                                                                0x00004000L
 561 #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK                                                                 0x00008000L
 562 #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK                                                                0x00010000L
 563 #define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK                                                            0x001E0000L
 564 #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK                                                               0x00E00000L
 565 #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK                                                                0x01000000L
 566 #define SDMA0_UTCL1_WR_STATUS__WR_XNACK_TIMEOUT_MASK                                                          0x02000000L
 567 #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_SW_MASK                                                              0x04000000L
 568 #define SDMA0_UTCL1_WR_STATUS__ATOMIC_OP_MASK                                                                 0x08000000L
 569 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK                                                      0x10000000L
 570 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK                                                       0x20000000L
 571 #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK                                                     0x40000000L
 572 #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK                                                      0x80000000L
 573 //SDMA0_UTCL1_INV0
 574 #define SDMA0_UTCL1_INV0__CPF_INVREQ_EN__SHIFT                                                                0x0
 575 #define SDMA0_UTCL1_INV0__GPUVM_INVREQ_EN__SHIFT                                                              0x1
 576 #define SDMA0_UTCL1_INV0__CPF_GPA_INVREQ__SHIFT                                                               0x2
 577 #define SDMA0_UTCL1_INV0__GPUVM_INVREQ_LOW__SHIFT                                                             0x3
 578 #define SDMA0_UTCL1_INV0__GPUVM_INVREQ_HIGH__SHIFT                                                            0x4
 579 #define SDMA0_UTCL1_INV0__INVREQ_SIZE__SHIFT                                                                  0x5
 580 #define SDMA0_UTCL1_INV0__INVREQ_IDLE__SHIFT                                                                  0xb
 581 #define SDMA0_UTCL1_INV0__VMINV_PEND_CNT__SHIFT                                                               0xc
 582 #define SDMA0_UTCL1_INV0__GPUVM_LO_INV_VMID__SHIFT                                                            0x10
 583 #define SDMA0_UTCL1_INV0__GPUVM_HI_INV_VMID__SHIFT                                                            0x14
 584 #define SDMA0_UTCL1_INV0__GPUVM_INV_MODE__SHIFT                                                               0x18
 585 #define SDMA0_UTCL1_INV0__INVREQ_IS_HEAVY__SHIFT                                                              0x1a
 586 #define SDMA0_UTCL1_INV0__INVREQ_FROM_CPF__SHIFT                                                              0x1b
 587 #define SDMA0_UTCL1_INV0__GPUVM_INVREQ_TAG__SHIFT                                                             0x1c
 588 #define SDMA0_UTCL1_INV0__CPF_INVREQ_EN_MASK                                                                  0x00000001L
 589 #define SDMA0_UTCL1_INV0__GPUVM_INVREQ_EN_MASK                                                                0x00000002L
 590 #define SDMA0_UTCL1_INV0__CPF_GPA_INVREQ_MASK                                                                 0x00000004L
 591 #define SDMA0_UTCL1_INV0__GPUVM_INVREQ_LOW_MASK                                                               0x00000008L
 592 #define SDMA0_UTCL1_INV0__GPUVM_INVREQ_HIGH_MASK                                                              0x00000010L
 593 #define SDMA0_UTCL1_INV0__INVREQ_SIZE_MASK                                                                    0x000007E0L
 594 #define SDMA0_UTCL1_INV0__INVREQ_IDLE_MASK                                                                    0x00000800L
 595 #define SDMA0_UTCL1_INV0__VMINV_PEND_CNT_MASK                                                                 0x0000F000L
 596 #define SDMA0_UTCL1_INV0__GPUVM_LO_INV_VMID_MASK                                                              0x000F0000L
 597 #define SDMA0_UTCL1_INV0__GPUVM_HI_INV_VMID_MASK                                                              0x00F00000L
 598 #define SDMA0_UTCL1_INV0__GPUVM_INV_MODE_MASK                                                                 0x03000000L
 599 #define SDMA0_UTCL1_INV0__INVREQ_IS_HEAVY_MASK                                                                0x04000000L
 600 #define SDMA0_UTCL1_INV0__INVREQ_FROM_CPF_MASK                                                                0x08000000L
 601 #define SDMA0_UTCL1_INV0__GPUVM_INVREQ_TAG_MASK                                                               0xF0000000L
 602 //SDMA0_UTCL1_INV1
 603 #define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT                                                                  0x0
 604 #define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK                                                                    0xFFFFFFFFL
 605 //SDMA0_UTCL1_INV2
 606 #define SDMA0_UTCL1_INV2__INV_VMID_VEC__SHIFT                                                                 0x0
 607 #define SDMA0_UTCL1_INV2__RESERVED__SHIFT                                                                     0x10
 608 #define SDMA0_UTCL1_INV2__INV_VMID_VEC_MASK                                                                   0x0000FFFFL
 609 #define SDMA0_UTCL1_INV2__RESERVED_MASK                                                                       0xFFFF0000L
 610 //SDMA0_UTCL1_RD_XNACK0
 611 #define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT                                                           0x0
 612 #define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK                                                             0xFFFFFFFFL
 613 //SDMA0_UTCL1_RD_XNACK1
 614 #define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT                                                           0x0
 615 #define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT                                                              0x4
 616 #define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT                                                            0x8
 617 #define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT                                                                0x1a
 618 #define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK                                                             0x0000000FL
 619 #define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK                                                                0x000000F0L
 620 #define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK                                                              0x03FFFF00L
 621 #define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK                                                                  0x0C000000L
 622 //SDMA0_UTCL1_WR_XNACK0
 623 #define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT                                                           0x0
 624 #define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK                                                             0xFFFFFFFFL
 625 //SDMA0_UTCL1_WR_XNACK1
 626 #define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT                                                           0x0
 627 #define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT                                                              0x4
 628 #define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT                                                            0x8
 629 #define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT                                                                0x1a
 630 #define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK                                                             0x0000000FL
 631 #define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK                                                                0x000000F0L
 632 #define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK                                                              0x03FFFF00L
 633 #define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK                                                                  0x0C000000L
 634 //SDMA0_UTCL1_TIMEOUT
 635 #define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT                                                            0x0
 636 #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT                                                            0x10
 637 #define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK                                                              0x0000FFFFL
 638 #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK                                                              0xFFFF0000L
 639 //SDMA0_UTCL1_PAGE
 640 #define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT                                                                      0x0
 641 #define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT                                                                     0x1
 642 #define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT                                                                    0x6
 643 #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT                                                                 0xa
 644 #define SDMA0_UTCL1_PAGE__USE_IO__SHIFT                                                                       0xb
 645 #define SDMA0_UTCL1_PAGE__RD_L2_POLICY__SHIFT                                                                 0xc
 646 #define SDMA0_UTCL1_PAGE__WR_L2_POLICY__SHIFT                                                                 0xe
 647 #define SDMA0_UTCL1_PAGE__DMA_PAGE_SIZE__SHIFT                                                                0x10
 648 #define SDMA0_UTCL1_PAGE__USE_BC__SHIFT                                                                       0x16
 649 #define SDMA0_UTCL1_PAGE__ADDR_IS_PA__SHIFT                                                                   0x17
 650 #define SDMA0_UTCL1_PAGE__VM_HOLE_MASK                                                                        0x00000001L
 651 #define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK                                                                       0x0000001EL
 652 #define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK                                                                      0x000003C0L
 653 #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK                                                                   0x00000400L
 654 #define SDMA0_UTCL1_PAGE__USE_IO_MASK                                                                         0x00000800L
 655 #define SDMA0_UTCL1_PAGE__RD_L2_POLICY_MASK                                                                   0x00003000L
 656 #define SDMA0_UTCL1_PAGE__WR_L2_POLICY_MASK                                                                   0x0000C000L
 657 #define SDMA0_UTCL1_PAGE__DMA_PAGE_SIZE_MASK                                                                  0x003F0000L
 658 #define SDMA0_UTCL1_PAGE__USE_BC_MASK                                                                         0x00400000L
 659 #define SDMA0_UTCL1_PAGE__ADDR_IS_PA_MASK                                                                     0x00800000L
 660 //SDMA0_POWER_CNTL_IDLE
 661 #define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT                                                                  0x0
 662 #define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT                                                                  0x10
 663 #define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT                                                                  0x18
 664 #define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK                                                                    0x0000FFFFL
 665 #define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK                                                                    0x00FF0000L
 666 #define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK                                                                    0xFF000000L
 667 //SDMA0_RELAX_ORDERING_LUT
 668 #define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT                                                            0x0
 669 #define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT                                                                 0x1
 670 #define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT                                                                0x2
 671 #define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT                                                            0x3
 672 #define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT                                                            0x4
 673 #define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT                                                                0x5
 674 #define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT                                                           0x6
 675 #define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT                                                             0x8
 676 #define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT                                                             0x9
 677 #define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT                                                               0xa
 678 #define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT                                                           0xb
 679 #define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT                                                               0xc
 680 #define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT                                                            0xd
 681 #define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT                                                             0xe
 682 #define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT                                                         0x1b
 683 #define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT                                                             0x1c
 684 #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT                                                            0x1d
 685 #define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT                                                             0x1e
 686 #define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT                                                             0x1f
 687 #define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK                                                              0x00000001L
 688 #define SDMA0_RELAX_ORDERING_LUT__COPY_MASK                                                                   0x00000002L
 689 #define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK                                                                  0x00000004L
 690 #define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK                                                              0x00000008L
 691 #define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK                                                              0x00000010L
 692 #define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK                                                                  0x00000020L
 693 #define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK                                                             0x000000C0L
 694 #define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK                                                               0x00000100L
 695 #define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK                                                               0x00000200L
 696 #define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK                                                                 0x00000400L
 697 #define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK                                                             0x00000800L
 698 #define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK                                                                 0x00001000L
 699 #define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK                                                              0x00002000L
 700 #define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK                                                               0x07FFC000L
 701 #define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK                                                           0x08000000L
 702 #define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK                                                               0x10000000L
 703 #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK                                                              0x20000000L
 704 #define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK                                                               0x40000000L
 705 #define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK                                                               0x80000000L
 706 //SDMA0_CHICKEN_BITS_2
 707 #define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT                                                       0x0
 708 #define SDMA0_CHICKEN_BITS_2__CE_BACKWARDS_SIZE_SEL__SHIFT                                                    0x4
 709 #define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK                                                         0x0000000FL
 710 #define SDMA0_CHICKEN_BITS_2__CE_BACKWARDS_SIZE_SEL_MASK                                                      0x00000010L
 711 //SDMA0_STATUS3_REG
 712 #define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT                                                               0x0
 713 #define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT                                                                 0x10
 714 #define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT                                                              0x14
 715 #define SDMA0_STATUS3_REG__AQL_PREV_CMD_IDLE__SHIFT                                                           0x15
 716 #define SDMA0_STATUS3_REG__TLBI_IDLE__SHIFT                                                                   0x16
 717 #define SDMA0_STATUS3_REG__GCR_IDLE__SHIFT                                                                    0x17
 718 #define SDMA0_STATUS3_REG__INVREQ_IDLE__SHIFT                                                                 0x18
 719 #define SDMA0_STATUS3_REG__QUEUE_ID_MATCH__SHIFT                                                              0x19
 720 #define SDMA0_STATUS3_REG__INT_QUEUE_ID__SHIFT                                                                0x1a
 721 #define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK                                                                 0x0000FFFFL
 722 #define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK                                                                   0x000F0000L
 723 #define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK                                                                0x00100000L
 724 #define SDMA0_STATUS3_REG__AQL_PREV_CMD_IDLE_MASK                                                             0x00200000L
 725 #define SDMA0_STATUS3_REG__TLBI_IDLE_MASK                                                                     0x00400000L
 726 #define SDMA0_STATUS3_REG__GCR_IDLE_MASK                                                                      0x00800000L
 727 #define SDMA0_STATUS3_REG__INVREQ_IDLE_MASK                                                                   0x01000000L
 728 #define SDMA0_STATUS3_REG__QUEUE_ID_MATCH_MASK                                                                0x02000000L
 729 #define SDMA0_STATUS3_REG__INT_QUEUE_ID_MASK                                                                  0x3C000000L
 730 //SDMA0_PHYSICAL_ADDR_LO
 731 #define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT                                                                0x0
 732 #define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT                                                                  0x1
 733 #define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT                                                              0x2
 734 #define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT                                                                   0xc
 735 #define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK                                                                  0x00000001L
 736 #define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK                                                                    0x00000002L
 737 #define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK                                                                0x00000004L
 738 #define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK                                                                     0xFFFFF000L
 739 //SDMA0_PHYSICAL_ADDR_HI
 740 #define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT                                                                   0x0
 741 #define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK                                                                     0x0000FFFFL
 742 //SDMA0_PHASE2_QUANTUM
 743 #define SDMA0_PHASE2_QUANTUM__UNIT__SHIFT                                                                     0x0
 744 #define SDMA0_PHASE2_QUANTUM__VALUE__SHIFT                                                                    0x8
 745 #define SDMA0_PHASE2_QUANTUM__PREFER__SHIFT                                                                   0x1e
 746 #define SDMA0_PHASE2_QUANTUM__UNIT_MASK                                                                       0x0000000FL
 747 #define SDMA0_PHASE2_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
 748 #define SDMA0_PHASE2_QUANTUM__PREFER_MASK                                                                     0x40000000L
 749 //SDMA0_F32_COUNTER
 750 #define SDMA0_F32_COUNTER__VALUE__SHIFT                                                                       0x0
 751 #define SDMA0_F32_COUNTER__VALUE_MASK                                                                         0xFFFFFFFFL
 752 //SDMA0_PERFMON_CNTL
 753 #define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT                                                               0x0
 754 #define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT                                                                0x1
 755 #define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT                                                                  0x2
 756 #define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT                                                               0xa
 757 #define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT                                                                0xb
 758 #define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT                                                                  0xc
 759 #define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK                                                                 0x00000001L
 760 #define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK                                                                  0x00000002L
 761 #define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK                                                                    0x000003FCL
 762 #define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK                                                                 0x00000400L
 763 #define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK                                                                  0x00000800L
 764 #define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK                                                                    0x000FF000L
 765 //SDMA0_PERFCOUNTER0_RESULT
 766 #define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT                                                          0x0
 767 #define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK                                                            0xFFFFFFFFL
 768 //SDMA0_PERFCOUNTER1_RESULT
 769 #define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT                                                          0x0
 770 #define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK                                                            0xFFFFFFFFL
 771 //SDMA0_PERFCOUNTER_TAG_DELAY_RANGE
 772 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT                                                   0x0
 773 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT                                                  0xe
 774 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT                                                   0x1c
 775 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK                                                     0x00003FFFL
 776 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK                                                    0x0FFFC000L
 777 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK                                                     0x10000000L
 778 //SDMA0_CRD_CNTL
 779 #define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT                                                                0x7
 780 #define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT                                                                0xd
 781 #define SDMA0_CRD_CNTL__CH_WRREQ_CREDIT__SHIFT                                                                0x13
 782 #define SDMA0_CRD_CNTL__CH_RDREQ_CREDIT__SHIFT                                                                0x19
 783 #define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK                                                                  0x00001F80L
 784 #define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK                                                                  0x0007E000L
 785 #define SDMA0_CRD_CNTL__CH_WRREQ_CREDIT_MASK                                                                  0x01F80000L
 786 #define SDMA0_CRD_CNTL__CH_RDREQ_CREDIT_MASK                                                                  0x7E000000L
 787 //SDMA0_GPU_IOV_VIOLATION_LOG
 788 //SDMA0_AQL_STATUS
 789 #define SDMA0_AQL_STATUS__COMPLETE_SIGNAL_EMPTY__SHIFT                                                        0x0
 790 #define SDMA0_AQL_STATUS__INVALID_CMD_EMPTY__SHIFT                                                            0x1
 791 #define SDMA0_AQL_STATUS__COMPLETE_SIGNAL_EMPTY_MASK                                                          0x00000001L
 792 #define SDMA0_AQL_STATUS__INVALID_CMD_EMPTY_MASK                                                              0x00000002L
 793 //SDMA0_EA_DBIT_ADDR_DATA
 794 #define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT                                                                 0x0
 795 #define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK                                                                   0xFFFFFFFFL
 796 //SDMA0_EA_DBIT_ADDR_INDEX
 797 #define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT                                                                0x0
 798 #define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK                                                                  0x00000007L
 799 //SDMA0_TLBI_GCR_CNTL
 800 #define SDMA0_TLBI_GCR_CNTL__TLBI_CMD_DW__SHIFT                                                               0x0
 801 #define SDMA0_TLBI_GCR_CNTL__GCR_CMD_DW__SHIFT                                                                0x4
 802 #define SDMA0_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE__SHIFT                                                           0x8
 803 #define SDMA0_TLBI_GCR_CNTL__TLBI_CREDIT__SHIFT                                                               0x10
 804 #define SDMA0_TLBI_GCR_CNTL__GCR_CREDIT__SHIFT                                                                0x18
 805 #define SDMA0_TLBI_GCR_CNTL__TLBI_CMD_DW_MASK                                                                 0x0000000FL
 806 #define SDMA0_TLBI_GCR_CNTL__GCR_CMD_DW_MASK                                                                  0x000000F0L
 807 #define SDMA0_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE_MASK                                                             0x00000F00L
 808 #define SDMA0_TLBI_GCR_CNTL__TLBI_CREDIT_MASK                                                                 0x00FF0000L
 809 #define SDMA0_TLBI_GCR_CNTL__GCR_CREDIT_MASK                                                                  0xFF000000L
 810 //SDMA0_TILING_CONFIG
 811 #define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                      0x4
 812 #define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                        0x00000070L
 813 //SDMA0_HASH
 814 #define SDMA0_HASH__CHANNEL_BITS__SHIFT                                                                       0x0
 815 #define SDMA0_HASH__BANK_BITS__SHIFT                                                                          0x4
 816 #define SDMA0_HASH__CHANNEL_XOR_COUNT__SHIFT                                                                  0x8
 817 #define SDMA0_HASH__BANK_XOR_COUNT__SHIFT                                                                     0xc
 818 #define SDMA0_HASH__CHANNEL_BITS_MASK                                                                         0x00000007L
 819 #define SDMA0_HASH__BANK_BITS_MASK                                                                            0x00000070L
 820 #define SDMA0_HASH__CHANNEL_XOR_COUNT_MASK                                                                    0x00000700L
 821 #define SDMA0_HASH__BANK_XOR_COUNT_MASK                                                                       0x00007000L
 822 //SDMA0_PERFCOUNTER0_SELECT
 823 #define SDMA0_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                            0x0
 824 #define SDMA0_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                           0xa
 825 #define SDMA0_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                           0x14
 826 #define SDMA0_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                          0x18
 827 #define SDMA0_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                           0x1c
 828 #define SDMA0_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                              0x000003FFL
 829 #define SDMA0_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
 830 #define SDMA0_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
 831 #define SDMA0_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                            0x0F000000L
 832 #define SDMA0_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                             0xF0000000L
 833 //SDMA0_PERFCOUNTER0_SELECT1
 834 #define SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                          0x0
 835 #define SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                          0xa
 836 #define SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                         0x18
 837 #define SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                         0x1c
 838 #define SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
 839 #define SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
 840 #define SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                           0x0F000000L
 841 #define SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                           0xF0000000L
 842 //SDMA0_PERFCOUNTER0_LO
 843 #define SDMA0_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
 844 #define SDMA0_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
 845 //SDMA0_PERFCOUNTER0_HI
 846 #define SDMA0_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
 847 #define SDMA0_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
 848 //SDMA0_PERFCOUNTER1_SELECT
 849 #define SDMA0_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                            0x0
 850 #define SDMA0_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                           0xa
 851 #define SDMA0_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                           0x14
 852 #define SDMA0_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                          0x18
 853 #define SDMA0_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                           0x1c
 854 #define SDMA0_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                              0x000003FFL
 855 #define SDMA0_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
 856 #define SDMA0_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
 857 #define SDMA0_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                            0x0F000000L
 858 #define SDMA0_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                             0xF0000000L
 859 //SDMA0_PERFCOUNTER1_SELECT1
 860 #define SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                          0x0
 861 #define SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                          0xa
 862 #define SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                         0x18
 863 #define SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                         0x1c
 864 #define SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
 865 #define SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
 866 #define SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                           0x0F000000L
 867 #define SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                           0xF0000000L
 868 //SDMA0_PERFCOUNTER1_LO
 869 #define SDMA0_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
 870 #define SDMA0_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
 871 //SDMA0_PERFCOUNTER1_HI
 872 #define SDMA0_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
 873 #define SDMA0_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
 874 //SDMA0_INT_STATUS
 875 #define SDMA0_INT_STATUS__DATA__SHIFT                                                                         0x0
 876 #define SDMA0_INT_STATUS__DATA_MASK                                                                           0xFFFFFFFFL
 877 //SDMA0_GPU_IOV_VIOLATION_LOG2
 878 #define SDMA0_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT                                                     0x0
 879 #define SDMA0_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK                                                       0x000003FFL
 880 //SDMA0_HOLE_ADDR_LO
 881 #define SDMA0_HOLE_ADDR_LO__VALUE__SHIFT                                                                      0x0
 882 #define SDMA0_HOLE_ADDR_LO__VALUE_MASK                                                                        0xFFFFFFFFL
 883 //SDMA0_HOLE_ADDR_HI
 884 #define SDMA0_HOLE_ADDR_HI__VALUE__SHIFT                                                                      0x0
 885 #define SDMA0_HOLE_ADDR_HI__VALUE_MASK                                                                        0xFFFFFFFFL
 886 //SDMA0_GFX_RB_CNTL
 887 #define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT                                                                   0x0
 888 #define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT                                                                     0x1
 889 #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                              0x9
 890 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                       0xc
 891 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                  0xd
 892 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                        0x10
 893 #define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT                                                                     0x17
 894 #define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT                                                                     0x18
 895 #define SDMA0_GFX_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                                0x1f
 896 #define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK                                                                     0x00000001L
 897 #define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK                                                                       0x0000003EL
 898 #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK                                                                0x00000200L
 899 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                         0x00001000L
 900 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                    0x00002000L
 901 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                          0x001F0000L
 902 #define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK                                                                       0x00800000L
 903 #define SDMA0_GFX_RB_CNTL__RB_VMID_MASK                                                                       0x0F000000L
 904 #define SDMA0_GFX_RB_CNTL__RPTR_WB_IDLE_MASK                                                                  0x80000000L
 905 //SDMA0_GFX_RB_BASE
 906 #define SDMA0_GFX_RB_BASE__ADDR__SHIFT                                                                        0x0
 907 #define SDMA0_GFX_RB_BASE__ADDR_MASK                                                                          0xFFFFFFFFL
 908 //SDMA0_GFX_RB_BASE_HI
 909 #define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT                                                                     0x0
 910 #define SDMA0_GFX_RB_BASE_HI__ADDR_MASK                                                                       0x00FFFFFFL
 911 //SDMA0_GFX_RB_RPTR
 912 #define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT                                                                      0x0
 913 #define SDMA0_GFX_RB_RPTR__OFFSET_MASK                                                                        0xFFFFFFFFL
 914 //SDMA0_GFX_RB_RPTR_HI
 915 #define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT                                                                   0x0
 916 #define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK                                                                     0xFFFFFFFFL
 917 //SDMA0_GFX_RB_WPTR
 918 #define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT                                                                      0x0
 919 #define SDMA0_GFX_RB_WPTR__OFFSET_MASK                                                                        0xFFFFFFFFL
 920 //SDMA0_GFX_RB_WPTR_HI
 921 #define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT                                                                   0x0
 922 #define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK                                                                     0xFFFFFFFFL
 923 //SDMA0_GFX_RB_WPTR_POLL_CNTL
 924 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                            0x0
 925 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                       0x1
 926 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                   0x2
 927 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                         0x4
 928 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                   0x10
 929 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                              0x00000001L
 930 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                         0x00000002L
 931 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                     0x00000004L
 932 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                           0x0000FFF0L
 933 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                     0xFFFF0000L
 934 //SDMA0_GFX_RB_RPTR_ADDR_HI
 935 #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                                0x0
 936 #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK                                                                  0xFFFFFFFFL
 937 //SDMA0_GFX_RB_RPTR_ADDR_LO
 938 #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                                0x2
 939 #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK                                                                  0xFFFFFFFCL
 940 //SDMA0_GFX_IB_CNTL
 941 #define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT                                                                   0x0
 942 #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                              0x4
 943 #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                            0x8
 944 #define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT                                                                    0x10
 945 #define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK                                                                     0x00000001L
 946 #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK                                                                0x00000010L
 947 #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                              0x00000100L
 948 #define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK                                                                      0x000F0000L
 949 //SDMA0_GFX_IB_RPTR
 950 #define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT                                                                      0x2
 951 #define SDMA0_GFX_IB_RPTR__OFFSET_MASK                                                                        0x003FFFFCL
 952 //SDMA0_GFX_IB_OFFSET
 953 #define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT                                                                    0x2
 954 #define SDMA0_GFX_IB_OFFSET__OFFSET_MASK                                                                      0x003FFFFCL
 955 //SDMA0_GFX_IB_BASE_LO
 956 #define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT                                                                     0x5
 957 #define SDMA0_GFX_IB_BASE_LO__ADDR_MASK                                                                       0xFFFFFFE0L
 958 //SDMA0_GFX_IB_BASE_HI
 959 #define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT                                                                     0x0
 960 #define SDMA0_GFX_IB_BASE_HI__ADDR_MASK                                                                       0xFFFFFFFFL
 961 //SDMA0_GFX_IB_SIZE
 962 #define SDMA0_GFX_IB_SIZE__SIZE__SHIFT                                                                        0x0
 963 #define SDMA0_GFX_IB_SIZE__SIZE_MASK                                                                          0x000FFFFFL
 964 //SDMA0_GFX_SKIP_CNTL
 965 #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT                                                                0x0
 966 #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK                                                                  0x000FFFFFL
 967 //SDMA0_GFX_CONTEXT_STATUS
 968 #define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT                                                             0x0
 969 #define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT                                                                 0x2
 970 #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT                                                              0x3
 971 #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT                                                            0x4
 972 #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                           0x7
 973 #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                          0x8
 974 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT                                                            0x9
 975 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                      0xa
 976 #define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK                                                               0x00000001L
 977 #define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK                                                                   0x00000004L
 978 #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK                                                                0x00000008L
 979 #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK                                                              0x00000070L
 980 #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                             0x00000080L
 981 #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK                                                            0x00000100L
 982 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK                                                              0x00000200L
 983 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                        0x00000400L
 984 //SDMA0_GFX_DOORBELL
 985 #define SDMA0_GFX_DOORBELL__ENABLE__SHIFT                                                                     0x1c
 986 #define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT                                                                   0x1e
 987 #define SDMA0_GFX_DOORBELL__ENABLE_MASK                                                                       0x10000000L
 988 #define SDMA0_GFX_DOORBELL__CAPTURED_MASK                                                                     0x40000000L
 989 //SDMA0_GFX_CONTEXT_CNTL
 990 #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT                                                             0x10
 991 #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK                                                               0x00010000L
 992 //SDMA0_GFX_STATUS
 993 #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                       0x0
 994 #define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                          0x8
 995 #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                         0x000000FFL
 996 #define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK                                                            0x00000100L
 997 //SDMA0_GFX_DOORBELL_LOG
 998 //SDMA0_GFX_WATERMARK
 999 #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT                                                            0x0
1000 #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT                                                            0x10
1001 #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK                                                              0x00000FFFL
1002 #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK                                                              0x03FF0000L
1003 //SDMA0_GFX_DOORBELL_OFFSET
1004 #define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT                                                              0x2
1005 #define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK                                                                0x0FFFFFFCL
1006 //SDMA0_GFX_CSA_ADDR_LO
1007 #define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT                                                                    0x2
1008 #define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK                                                                      0xFFFFFFFCL
1009 //SDMA0_GFX_CSA_ADDR_HI
1010 #define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT                                                                    0x0
1011 #define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK                                                                      0xFFFFFFFFL
1012 //SDMA0_GFX_IB_SUB_REMAIN
1013 #define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT                                                                  0x0
1014 #define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK                                                                    0x00003FFFL
1015 //SDMA0_GFX_PREEMPT
1016 #define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT                                                                  0x0
1017 #define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK                                                                    0x00000001L
1018 //SDMA0_GFX_DUMMY_REG
1019 #define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT                                                                     0x0
1020 #define SDMA0_GFX_DUMMY_REG__DUMMY_MASK                                                                       0xFFFFFFFFL
1021 //SDMA0_GFX_RB_WPTR_POLL_ADDR_HI
1022 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                           0x0
1023 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                             0xFFFFFFFFL
1024 //SDMA0_GFX_RB_WPTR_POLL_ADDR_LO
1025 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                           0x2
1026 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                             0xFFFFFFFCL
1027 //SDMA0_GFX_RB_AQL_CNTL
1028 #define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                              0x0
1029 #define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                         0x1
1030 #define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                             0x8
1031 #define SDMA0_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                   0x10
1032 #define SDMA0_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                             0x11
1033 #define SDMA0_GFX_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                          0x12
1034 #define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK                                                                0x00000001L
1035 #define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                           0x000000FEL
1036 #define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK                                                               0x0000FF00L
1037 #define SDMA0_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                     0x00010000L
1038 #define SDMA0_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                               0x00020000L
1039 #define SDMA0_GFX_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                            0x00040000L
1040 //SDMA0_GFX_MINOR_PTR_UPDATE
1041 #define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                             0x0
1042 #define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK                                                               0x00000001L
1043 //SDMA0_GFX_MIDCMD_DATA0
1044 #define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT                                                                  0x0
1045 #define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK                                                                    0xFFFFFFFFL
1046 //SDMA0_GFX_MIDCMD_DATA1
1047 #define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT                                                                  0x0
1048 #define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK                                                                    0xFFFFFFFFL
1049 //SDMA0_GFX_MIDCMD_DATA2
1050 #define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT                                                                  0x0
1051 #define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK                                                                    0xFFFFFFFFL
1052 //SDMA0_GFX_MIDCMD_DATA3
1053 #define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT                                                                  0x0
1054 #define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK                                                                    0xFFFFFFFFL
1055 //SDMA0_GFX_MIDCMD_DATA4
1056 #define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT                                                                  0x0
1057 #define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK                                                                    0xFFFFFFFFL
1058 //SDMA0_GFX_MIDCMD_DATA5
1059 #define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT                                                                  0x0
1060 #define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK                                                                    0xFFFFFFFFL
1061 //SDMA0_GFX_MIDCMD_DATA6
1062 #define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT                                                                  0x0
1063 #define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK                                                                    0xFFFFFFFFL
1064 //SDMA0_GFX_MIDCMD_DATA7
1065 #define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT                                                                  0x0
1066 #define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK                                                                    0xFFFFFFFFL
1067 //SDMA0_GFX_MIDCMD_DATA8
1068 #define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT                                                                  0x0
1069 #define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK                                                                    0xFFFFFFFFL
1070 //SDMA0_GFX_MIDCMD_CNTL
1071 #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT                                                              0x0
1072 #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT                                                               0x1
1073 #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                             0x4
1074 #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                           0x8
1075 #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK                                                                0x00000001L
1076 #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK                                                                 0x00000002L
1077 #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK                                                               0x000000F0L
1078 #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                             0x00000100L
1079 //SDMA0_PAGE_RB_CNTL
1080 #define SDMA0_PAGE_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
1081 #define SDMA0_PAGE_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
1082 #define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
1083 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
1084 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
1085 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
1086 #define SDMA0_PAGE_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
1087 #define SDMA0_PAGE_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
1088 #define SDMA0_PAGE_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
1089 #define SDMA0_PAGE_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
1090 #define SDMA0_PAGE_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
1091 #define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
1092 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
1093 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
1094 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
1095 #define SDMA0_PAGE_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
1096 #define SDMA0_PAGE_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
1097 #define SDMA0_PAGE_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
1098 //SDMA0_PAGE_RB_BASE
1099 #define SDMA0_PAGE_RB_BASE__ADDR__SHIFT                                                                       0x0
1100 #define SDMA0_PAGE_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
1101 //SDMA0_PAGE_RB_BASE_HI
1102 #define SDMA0_PAGE_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
1103 #define SDMA0_PAGE_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
1104 //SDMA0_PAGE_RB_RPTR
1105 #define SDMA0_PAGE_RB_RPTR__OFFSET__SHIFT                                                                     0x0
1106 #define SDMA0_PAGE_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
1107 //SDMA0_PAGE_RB_RPTR_HI
1108 #define SDMA0_PAGE_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
1109 #define SDMA0_PAGE_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
1110 //SDMA0_PAGE_RB_WPTR
1111 #define SDMA0_PAGE_RB_WPTR__OFFSET__SHIFT                                                                     0x0
1112 #define SDMA0_PAGE_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
1113 //SDMA0_PAGE_RB_WPTR_HI
1114 #define SDMA0_PAGE_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
1115 #define SDMA0_PAGE_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
1116 //SDMA0_PAGE_RB_WPTR_POLL_CNTL
1117 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
1118 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
1119 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
1120 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
1121 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
1122 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
1123 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
1124 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
1125 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
1126 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
1127 //SDMA0_PAGE_RB_RPTR_ADDR_HI
1128 #define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
1129 #define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
1130 //SDMA0_PAGE_RB_RPTR_ADDR_LO
1131 #define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
1132 #define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
1133 //SDMA0_PAGE_IB_CNTL
1134 #define SDMA0_PAGE_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
1135 #define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
1136 #define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
1137 #define SDMA0_PAGE_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
1138 #define SDMA0_PAGE_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
1139 #define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
1140 #define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
1141 #define SDMA0_PAGE_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
1142 //SDMA0_PAGE_IB_RPTR
1143 #define SDMA0_PAGE_IB_RPTR__OFFSET__SHIFT                                                                     0x2
1144 #define SDMA0_PAGE_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
1145 //SDMA0_PAGE_IB_OFFSET
1146 #define SDMA0_PAGE_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
1147 #define SDMA0_PAGE_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
1148 //SDMA0_PAGE_IB_BASE_LO
1149 #define SDMA0_PAGE_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
1150 #define SDMA0_PAGE_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
1151 //SDMA0_PAGE_IB_BASE_HI
1152 #define SDMA0_PAGE_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
1153 #define SDMA0_PAGE_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
1154 //SDMA0_PAGE_IB_SIZE
1155 #define SDMA0_PAGE_IB_SIZE__SIZE__SHIFT                                                                       0x0
1156 #define SDMA0_PAGE_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
1157 //SDMA0_PAGE_SKIP_CNTL
1158 #define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
1159 #define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
1160 //SDMA0_PAGE_CONTEXT_STATUS
1161 #define SDMA0_PAGE_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
1162 #define SDMA0_PAGE_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
1163 #define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
1164 #define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
1165 #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
1166 #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
1167 #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
1168 #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
1169 #define SDMA0_PAGE_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
1170 #define SDMA0_PAGE_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
1171 #define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
1172 #define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
1173 #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
1174 #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
1175 #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
1176 #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
1177 //SDMA0_PAGE_DOORBELL
1178 #define SDMA0_PAGE_DOORBELL__ENABLE__SHIFT                                                                    0x1c
1179 #define SDMA0_PAGE_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
1180 #define SDMA0_PAGE_DOORBELL__ENABLE_MASK                                                                      0x10000000L
1181 #define SDMA0_PAGE_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
1182 //SDMA0_PAGE_STATUS
1183 #define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
1184 #define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
1185 #define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
1186 #define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
1187 //SDMA0_PAGE_DOORBELL_LOG
1188 //SDMA0_PAGE_WATERMARK
1189 #define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
1190 #define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
1191 #define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
1192 #define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
1193 //SDMA0_PAGE_DOORBELL_OFFSET
1194 #define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
1195 #define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
1196 //SDMA0_PAGE_CSA_ADDR_LO
1197 #define SDMA0_PAGE_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
1198 #define SDMA0_PAGE_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
1199 //SDMA0_PAGE_CSA_ADDR_HI
1200 #define SDMA0_PAGE_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
1201 #define SDMA0_PAGE_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
1202 //SDMA0_PAGE_IB_SUB_REMAIN
1203 #define SDMA0_PAGE_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
1204 #define SDMA0_PAGE_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
1205 //SDMA0_PAGE_PREEMPT
1206 #define SDMA0_PAGE_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
1207 #define SDMA0_PAGE_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
1208 //SDMA0_PAGE_DUMMY_REG
1209 #define SDMA0_PAGE_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
1210 #define SDMA0_PAGE_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
1211 //SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI
1212 #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
1213 #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
1214 //SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO
1215 #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
1216 #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
1217 //SDMA0_PAGE_RB_AQL_CNTL
1218 #define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
1219 #define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
1220 #define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
1221 #define SDMA0_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
1222 #define SDMA0_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
1223 #define SDMA0_PAGE_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
1224 #define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
1225 #define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
1226 #define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
1227 #define SDMA0_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
1228 #define SDMA0_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
1229 #define SDMA0_PAGE_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
1230 //SDMA0_PAGE_MINOR_PTR_UPDATE
1231 #define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
1232 #define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
1233 //SDMA0_PAGE_MIDCMD_DATA0
1234 #define SDMA0_PAGE_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
1235 #define SDMA0_PAGE_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
1236 //SDMA0_PAGE_MIDCMD_DATA1
1237 #define SDMA0_PAGE_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
1238 #define SDMA0_PAGE_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
1239 //SDMA0_PAGE_MIDCMD_DATA2
1240 #define SDMA0_PAGE_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
1241 #define SDMA0_PAGE_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
1242 //SDMA0_PAGE_MIDCMD_DATA3
1243 #define SDMA0_PAGE_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
1244 #define SDMA0_PAGE_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
1245 //SDMA0_PAGE_MIDCMD_DATA4
1246 #define SDMA0_PAGE_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
1247 #define SDMA0_PAGE_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
1248 //SDMA0_PAGE_MIDCMD_DATA5
1249 #define SDMA0_PAGE_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
1250 #define SDMA0_PAGE_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
1251 //SDMA0_PAGE_MIDCMD_DATA6
1252 #define SDMA0_PAGE_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
1253 #define SDMA0_PAGE_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
1254 //SDMA0_PAGE_MIDCMD_DATA7
1255 #define SDMA0_PAGE_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
1256 #define SDMA0_PAGE_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
1257 //SDMA0_PAGE_MIDCMD_DATA8
1258 #define SDMA0_PAGE_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
1259 #define SDMA0_PAGE_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
1260 //SDMA0_PAGE_MIDCMD_CNTL
1261 #define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
1262 #define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
1263 #define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
1264 #define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
1265 #define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
1266 #define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
1267 #define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
1268 #define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
1269 //SDMA0_RLC0_RB_CNTL
1270 #define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
1271 #define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
1272 #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
1273 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
1274 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
1275 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
1276 #define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
1277 #define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
1278 #define SDMA0_RLC0_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
1279 #define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
1280 #define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
1281 #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
1282 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
1283 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
1284 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
1285 #define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
1286 #define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
1287 #define SDMA0_RLC0_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
1288 //SDMA0_RLC0_RB_BASE
1289 #define SDMA0_RLC0_RB_BASE__ADDR__SHIFT                                                                       0x0
1290 #define SDMA0_RLC0_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
1291 //SDMA0_RLC0_RB_BASE_HI
1292 #define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
1293 #define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
1294 //SDMA0_RLC0_RB_RPTR
1295 #define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT                                                                     0x0
1296 #define SDMA0_RLC0_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
1297 //SDMA0_RLC0_RB_RPTR_HI
1298 #define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
1299 #define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
1300 //SDMA0_RLC0_RB_WPTR
1301 #define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT                                                                     0x0
1302 #define SDMA0_RLC0_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
1303 //SDMA0_RLC0_RB_WPTR_HI
1304 #define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
1305 #define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
1306 //SDMA0_RLC0_RB_WPTR_POLL_CNTL
1307 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
1308 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
1309 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
1310 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
1311 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
1312 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
1313 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
1314 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
1315 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
1316 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
1317 //SDMA0_RLC0_RB_RPTR_ADDR_HI
1318 #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
1319 #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
1320 //SDMA0_RLC0_RB_RPTR_ADDR_LO
1321 #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
1322 #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
1323 //SDMA0_RLC0_IB_CNTL
1324 #define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
1325 #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
1326 #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
1327 #define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
1328 #define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
1329 #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
1330 #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
1331 #define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
1332 //SDMA0_RLC0_IB_RPTR
1333 #define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT                                                                     0x2
1334 #define SDMA0_RLC0_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
1335 //SDMA0_RLC0_IB_OFFSET
1336 #define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
1337 #define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
1338 //SDMA0_RLC0_IB_BASE_LO
1339 #define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
1340 #define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
1341 //SDMA0_RLC0_IB_BASE_HI
1342 #define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
1343 #define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
1344 //SDMA0_RLC0_IB_SIZE
1345 #define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT                                                                       0x0
1346 #define SDMA0_RLC0_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
1347 //SDMA0_RLC0_SKIP_CNTL
1348 #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
1349 #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
1350 //SDMA0_RLC0_CONTEXT_STATUS
1351 #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
1352 #define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
1353 #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
1354 #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
1355 #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
1356 #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
1357 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
1358 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
1359 #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
1360 #define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
1361 #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
1362 #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
1363 #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
1364 #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
1365 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
1366 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
1367 //SDMA0_RLC0_DOORBELL
1368 #define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT                                                                    0x1c
1369 #define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
1370 #define SDMA0_RLC0_DOORBELL__ENABLE_MASK                                                                      0x10000000L
1371 #define SDMA0_RLC0_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
1372 //SDMA0_RLC0_STATUS
1373 #define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
1374 #define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
1375 #define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
1376 #define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
1377 //SDMA0_RLC0_DOORBELL_LOG
1378 //SDMA0_RLC0_WATERMARK
1379 #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
1380 #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
1381 #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
1382 #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
1383 //SDMA0_RLC0_DOORBELL_OFFSET
1384 #define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
1385 #define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
1386 //SDMA0_RLC0_CSA_ADDR_LO
1387 #define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
1388 #define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
1389 //SDMA0_RLC0_CSA_ADDR_HI
1390 #define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
1391 #define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
1392 //SDMA0_RLC0_IB_SUB_REMAIN
1393 #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
1394 #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
1395 //SDMA0_RLC0_PREEMPT
1396 #define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
1397 #define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
1398 //SDMA0_RLC0_DUMMY_REG
1399 #define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
1400 #define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
1401 //SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI
1402 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
1403 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
1404 //SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO
1405 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
1406 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
1407 //SDMA0_RLC0_RB_AQL_CNTL
1408 #define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
1409 #define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
1410 #define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
1411 #define SDMA0_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
1412 #define SDMA0_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
1413 #define SDMA0_RLC0_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
1414 #define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
1415 #define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
1416 #define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
1417 #define SDMA0_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
1418 #define SDMA0_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
1419 #define SDMA0_RLC0_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
1420 //SDMA0_RLC0_MINOR_PTR_UPDATE
1421 #define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
1422 #define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
1423 //SDMA0_RLC0_MIDCMD_DATA0
1424 #define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
1425 #define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
1426 //SDMA0_RLC0_MIDCMD_DATA1
1427 #define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
1428 #define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
1429 //SDMA0_RLC0_MIDCMD_DATA2
1430 #define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
1431 #define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
1432 //SDMA0_RLC0_MIDCMD_DATA3
1433 #define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
1434 #define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
1435 //SDMA0_RLC0_MIDCMD_DATA4
1436 #define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
1437 #define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
1438 //SDMA0_RLC0_MIDCMD_DATA5
1439 #define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
1440 #define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
1441 //SDMA0_RLC0_MIDCMD_DATA6
1442 #define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
1443 #define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
1444 //SDMA0_RLC0_MIDCMD_DATA7
1445 #define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
1446 #define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
1447 //SDMA0_RLC0_MIDCMD_DATA8
1448 #define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
1449 #define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
1450 //SDMA0_RLC0_MIDCMD_CNTL
1451 #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
1452 #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
1453 #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
1454 #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
1455 #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
1456 #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
1457 #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
1458 #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
1459 //SDMA0_RLC1_RB_CNTL
1460 #define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
1461 #define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
1462 #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
1463 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
1464 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
1465 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
1466 #define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
1467 #define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
1468 #define SDMA0_RLC1_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
1469 #define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
1470 #define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
1471 #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
1472 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
1473 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
1474 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
1475 #define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
1476 #define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
1477 #define SDMA0_RLC1_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
1478 //SDMA0_RLC1_RB_BASE
1479 #define SDMA0_RLC1_RB_BASE__ADDR__SHIFT                                                                       0x0
1480 #define SDMA0_RLC1_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
1481 //SDMA0_RLC1_RB_BASE_HI
1482 #define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
1483 #define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
1484 //SDMA0_RLC1_RB_RPTR
1485 #define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT                                                                     0x0
1486 #define SDMA0_RLC1_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
1487 //SDMA0_RLC1_RB_RPTR_HI
1488 #define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
1489 #define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
1490 //SDMA0_RLC1_RB_WPTR
1491 #define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT                                                                     0x0
1492 #define SDMA0_RLC1_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
1493 //SDMA0_RLC1_RB_WPTR_HI
1494 #define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
1495 #define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
1496 //SDMA0_RLC1_RB_WPTR_POLL_CNTL
1497 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
1498 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
1499 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
1500 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
1501 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
1502 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
1503 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
1504 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
1505 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
1506 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
1507 //SDMA0_RLC1_RB_RPTR_ADDR_HI
1508 #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
1509 #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
1510 //SDMA0_RLC1_RB_RPTR_ADDR_LO
1511 #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
1512 #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
1513 //SDMA0_RLC1_IB_CNTL
1514 #define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
1515 #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
1516 #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
1517 #define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
1518 #define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
1519 #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
1520 #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
1521 #define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
1522 //SDMA0_RLC1_IB_RPTR
1523 #define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT                                                                     0x2
1524 #define SDMA0_RLC1_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
1525 //SDMA0_RLC1_IB_OFFSET
1526 #define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
1527 #define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
1528 //SDMA0_RLC1_IB_BASE_LO
1529 #define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
1530 #define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
1531 //SDMA0_RLC1_IB_BASE_HI
1532 #define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
1533 #define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
1534 //SDMA0_RLC1_IB_SIZE
1535 #define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT                                                                       0x0
1536 #define SDMA0_RLC1_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
1537 //SDMA0_RLC1_SKIP_CNTL
1538 #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
1539 #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
1540 //SDMA0_RLC1_CONTEXT_STATUS
1541 #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
1542 #define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
1543 #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
1544 #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
1545 #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
1546 #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
1547 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
1548 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
1549 #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
1550 #define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
1551 #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
1552 #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
1553 #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
1554 #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
1555 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
1556 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
1557 //SDMA0_RLC1_DOORBELL
1558 #define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT                                                                    0x1c
1559 #define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
1560 #define SDMA0_RLC1_DOORBELL__ENABLE_MASK                                                                      0x10000000L
1561 #define SDMA0_RLC1_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
1562 //SDMA0_RLC1_STATUS
1563 #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
1564 #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
1565 #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
1566 #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
1567 //SDMA0_RLC1_DOORBELL_LOG
1568 //SDMA0_RLC1_WATERMARK
1569 #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
1570 #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
1571 #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
1572 #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
1573 //SDMA0_RLC1_DOORBELL_OFFSET
1574 #define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
1575 #define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
1576 //SDMA0_RLC1_CSA_ADDR_LO
1577 #define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
1578 #define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
1579 //SDMA0_RLC1_CSA_ADDR_HI
1580 #define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
1581 #define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
1582 //SDMA0_RLC1_IB_SUB_REMAIN
1583 #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
1584 #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
1585 //SDMA0_RLC1_PREEMPT
1586 #define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
1587 #define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
1588 //SDMA0_RLC1_DUMMY_REG
1589 #define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
1590 #define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
1591 //SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI
1592 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
1593 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
1594 //SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO
1595 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
1596 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
1597 //SDMA0_RLC1_RB_AQL_CNTL
1598 #define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
1599 #define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
1600 #define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
1601 #define SDMA0_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
1602 #define SDMA0_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
1603 #define SDMA0_RLC1_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
1604 #define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
1605 #define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
1606 #define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
1607 #define SDMA0_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
1608 #define SDMA0_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
1609 #define SDMA0_RLC1_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
1610 //SDMA0_RLC1_MINOR_PTR_UPDATE
1611 #define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
1612 #define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
1613 //SDMA0_RLC1_MIDCMD_DATA0
1614 #define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
1615 #define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
1616 //SDMA0_RLC1_MIDCMD_DATA1
1617 #define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
1618 #define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
1619 //SDMA0_RLC1_MIDCMD_DATA2
1620 #define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
1621 #define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
1622 //SDMA0_RLC1_MIDCMD_DATA3
1623 #define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
1624 #define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
1625 //SDMA0_RLC1_MIDCMD_DATA4
1626 #define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
1627 #define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
1628 //SDMA0_RLC1_MIDCMD_DATA5
1629 #define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
1630 #define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
1631 //SDMA0_RLC1_MIDCMD_DATA6
1632 #define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
1633 #define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
1634 //SDMA0_RLC1_MIDCMD_DATA7
1635 #define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
1636 #define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
1637 //SDMA0_RLC1_MIDCMD_DATA8
1638 #define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
1639 #define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
1640 //SDMA0_RLC1_MIDCMD_CNTL
1641 #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
1642 #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
1643 #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
1644 #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
1645 #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
1646 #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
1647 #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
1648 #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
1649 //SDMA0_RLC2_RB_CNTL
1650 #define SDMA0_RLC2_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
1651 #define SDMA0_RLC2_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
1652 #define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
1653 #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
1654 #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
1655 #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
1656 #define SDMA0_RLC2_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
1657 #define SDMA0_RLC2_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
1658 #define SDMA0_RLC2_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
1659 #define SDMA0_RLC2_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
1660 #define SDMA0_RLC2_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
1661 #define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
1662 #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
1663 #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
1664 #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
1665 #define SDMA0_RLC2_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
1666 #define SDMA0_RLC2_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
1667 #define SDMA0_RLC2_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
1668 //SDMA0_RLC2_RB_BASE
1669 #define SDMA0_RLC2_RB_BASE__ADDR__SHIFT                                                                       0x0
1670 #define SDMA0_RLC2_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
1671 //SDMA0_RLC2_RB_BASE_HI
1672 #define SDMA0_RLC2_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
1673 #define SDMA0_RLC2_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
1674 //SDMA0_RLC2_RB_RPTR
1675 #define SDMA0_RLC2_RB_RPTR__OFFSET__SHIFT                                                                     0x0
1676 #define SDMA0_RLC2_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
1677 //SDMA0_RLC2_RB_RPTR_HI
1678 #define SDMA0_RLC2_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
1679 #define SDMA0_RLC2_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
1680 //SDMA0_RLC2_RB_WPTR
1681 #define SDMA0_RLC2_RB_WPTR__OFFSET__SHIFT                                                                     0x0
1682 #define SDMA0_RLC2_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
1683 //SDMA0_RLC2_RB_WPTR_HI
1684 #define SDMA0_RLC2_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
1685 #define SDMA0_RLC2_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
1686 //SDMA0_RLC2_RB_WPTR_POLL_CNTL
1687 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
1688 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
1689 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
1690 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
1691 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
1692 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
1693 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
1694 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
1695 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
1696 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
1697 //SDMA0_RLC2_RB_RPTR_ADDR_HI
1698 #define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
1699 #define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
1700 //SDMA0_RLC2_RB_RPTR_ADDR_LO
1701 #define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
1702 #define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
1703 //SDMA0_RLC2_IB_CNTL
1704 #define SDMA0_RLC2_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
1705 #define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
1706 #define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
1707 #define SDMA0_RLC2_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
1708 #define SDMA0_RLC2_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
1709 #define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
1710 #define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
1711 #define SDMA0_RLC2_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
1712 //SDMA0_RLC2_IB_RPTR
1713 #define SDMA0_RLC2_IB_RPTR__OFFSET__SHIFT                                                                     0x2
1714 #define SDMA0_RLC2_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
1715 //SDMA0_RLC2_IB_OFFSET
1716 #define SDMA0_RLC2_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
1717 #define SDMA0_RLC2_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
1718 //SDMA0_RLC2_IB_BASE_LO
1719 #define SDMA0_RLC2_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
1720 #define SDMA0_RLC2_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
1721 //SDMA0_RLC2_IB_BASE_HI
1722 #define SDMA0_RLC2_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
1723 #define SDMA0_RLC2_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
1724 //SDMA0_RLC2_IB_SIZE
1725 #define SDMA0_RLC2_IB_SIZE__SIZE__SHIFT                                                                       0x0
1726 #define SDMA0_RLC2_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
1727 //SDMA0_RLC2_SKIP_CNTL
1728 #define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
1729 #define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
1730 //SDMA0_RLC2_CONTEXT_STATUS
1731 #define SDMA0_RLC2_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
1732 #define SDMA0_RLC2_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
1733 #define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
1734 #define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
1735 #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
1736 #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
1737 #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
1738 #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
1739 #define SDMA0_RLC2_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
1740 #define SDMA0_RLC2_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
1741 #define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
1742 #define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
1743 #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
1744 #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
1745 #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
1746 #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
1747 //SDMA0_RLC2_DOORBELL
1748 #define SDMA0_RLC2_DOORBELL__ENABLE__SHIFT                                                                    0x1c
1749 #define SDMA0_RLC2_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
1750 #define SDMA0_RLC2_DOORBELL__ENABLE_MASK                                                                      0x10000000L
1751 #define SDMA0_RLC2_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
1752 //SDMA0_RLC2_STATUS
1753 #define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
1754 #define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
1755 #define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
1756 #define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
1757 //SDMA0_RLC2_DOORBELL_LOG
1758 //SDMA0_RLC2_WATERMARK
1759 #define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
1760 #define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
1761 #define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
1762 #define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
1763 //SDMA0_RLC2_DOORBELL_OFFSET
1764 #define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
1765 #define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
1766 //SDMA0_RLC2_CSA_ADDR_LO
1767 #define SDMA0_RLC2_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
1768 #define SDMA0_RLC2_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
1769 //SDMA0_RLC2_CSA_ADDR_HI
1770 #define SDMA0_RLC2_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
1771 #define SDMA0_RLC2_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
1772 //SDMA0_RLC2_IB_SUB_REMAIN
1773 #define SDMA0_RLC2_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
1774 #define SDMA0_RLC2_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
1775 //SDMA0_RLC2_PREEMPT
1776 #define SDMA0_RLC2_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
1777 #define SDMA0_RLC2_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
1778 //SDMA0_RLC2_DUMMY_REG
1779 #define SDMA0_RLC2_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
1780 #define SDMA0_RLC2_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
1781 //SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI
1782 #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
1783 #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
1784 //SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO
1785 #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
1786 #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
1787 //SDMA0_RLC2_RB_AQL_CNTL
1788 #define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
1789 #define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
1790 #define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
1791 #define SDMA0_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
1792 #define SDMA0_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
1793 #define SDMA0_RLC2_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
1794 #define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
1795 #define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
1796 #define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
1797 #define SDMA0_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
1798 #define SDMA0_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
1799 #define SDMA0_RLC2_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
1800 //SDMA0_RLC2_MINOR_PTR_UPDATE
1801 #define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
1802 #define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
1803 //SDMA0_RLC2_MIDCMD_DATA0
1804 #define SDMA0_RLC2_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
1805 #define SDMA0_RLC2_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
1806 //SDMA0_RLC2_MIDCMD_DATA1
1807 #define SDMA0_RLC2_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
1808 #define SDMA0_RLC2_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
1809 //SDMA0_RLC2_MIDCMD_DATA2
1810 #define SDMA0_RLC2_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
1811 #define SDMA0_RLC2_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
1812 //SDMA0_RLC2_MIDCMD_DATA3
1813 #define SDMA0_RLC2_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
1814 #define SDMA0_RLC2_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
1815 //SDMA0_RLC2_MIDCMD_DATA4
1816 #define SDMA0_RLC2_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
1817 #define SDMA0_RLC2_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
1818 //SDMA0_RLC2_MIDCMD_DATA5
1819 #define SDMA0_RLC2_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
1820 #define SDMA0_RLC2_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
1821 //SDMA0_RLC2_MIDCMD_DATA6
1822 #define SDMA0_RLC2_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
1823 #define SDMA0_RLC2_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
1824 //SDMA0_RLC2_MIDCMD_DATA7
1825 #define SDMA0_RLC2_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
1826 #define SDMA0_RLC2_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
1827 //SDMA0_RLC2_MIDCMD_DATA8
1828 #define SDMA0_RLC2_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
1829 #define SDMA0_RLC2_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
1830 //SDMA0_RLC2_MIDCMD_CNTL
1831 #define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
1832 #define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
1833 #define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
1834 #define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
1835 #define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
1836 #define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
1837 #define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
1838 #define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
1839 //SDMA0_RLC3_RB_CNTL
1840 #define SDMA0_RLC3_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
1841 #define SDMA0_RLC3_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
1842 #define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
1843 #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
1844 #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
1845 #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
1846 #define SDMA0_RLC3_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
1847 #define SDMA0_RLC3_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
1848 #define SDMA0_RLC3_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
1849 #define SDMA0_RLC3_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
1850 #define SDMA0_RLC3_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
1851 #define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
1852 #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
1853 #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
1854 #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
1855 #define SDMA0_RLC3_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
1856 #define SDMA0_RLC3_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
1857 #define SDMA0_RLC3_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
1858 //SDMA0_RLC3_RB_BASE
1859 #define SDMA0_RLC3_RB_BASE__ADDR__SHIFT                                                                       0x0
1860 #define SDMA0_RLC3_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
1861 //SDMA0_RLC3_RB_BASE_HI
1862 #define SDMA0_RLC3_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
1863 #define SDMA0_RLC3_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
1864 //SDMA0_RLC3_RB_RPTR
1865 #define SDMA0_RLC3_RB_RPTR__OFFSET__SHIFT                                                                     0x0
1866 #define SDMA0_RLC3_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
1867 //SDMA0_RLC3_RB_RPTR_HI
1868 #define SDMA0_RLC3_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
1869 #define SDMA0_RLC3_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
1870 //SDMA0_RLC3_RB_WPTR
1871 #define SDMA0_RLC3_RB_WPTR__OFFSET__SHIFT                                                                     0x0
1872 #define SDMA0_RLC3_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
1873 //SDMA0_RLC3_RB_WPTR_HI
1874 #define SDMA0_RLC3_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
1875 #define SDMA0_RLC3_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
1876 //SDMA0_RLC3_RB_WPTR_POLL_CNTL
1877 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
1878 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
1879 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
1880 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
1881 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
1882 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
1883 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
1884 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
1885 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
1886 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
1887 //SDMA0_RLC3_RB_RPTR_ADDR_HI
1888 #define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
1889 #define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
1890 //SDMA0_RLC3_RB_RPTR_ADDR_LO
1891 #define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
1892 #define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
1893 //SDMA0_RLC3_IB_CNTL
1894 #define SDMA0_RLC3_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
1895 #define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
1896 #define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
1897 #define SDMA0_RLC3_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
1898 #define SDMA0_RLC3_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
1899 #define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
1900 #define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
1901 #define SDMA0_RLC3_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
1902 //SDMA0_RLC3_IB_RPTR
1903 #define SDMA0_RLC3_IB_RPTR__OFFSET__SHIFT                                                                     0x2
1904 #define SDMA0_RLC3_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
1905 //SDMA0_RLC3_IB_OFFSET
1906 #define SDMA0_RLC3_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
1907 #define SDMA0_RLC3_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
1908 //SDMA0_RLC3_IB_BASE_LO
1909 #define SDMA0_RLC3_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
1910 #define SDMA0_RLC3_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
1911 //SDMA0_RLC3_IB_BASE_HI
1912 #define SDMA0_RLC3_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
1913 #define SDMA0_RLC3_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
1914 //SDMA0_RLC3_IB_SIZE
1915 #define SDMA0_RLC3_IB_SIZE__SIZE__SHIFT                                                                       0x0
1916 #define SDMA0_RLC3_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
1917 //SDMA0_RLC3_SKIP_CNTL
1918 #define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
1919 #define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
1920 //SDMA0_RLC3_CONTEXT_STATUS
1921 #define SDMA0_RLC3_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
1922 #define SDMA0_RLC3_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
1923 #define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
1924 #define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
1925 #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
1926 #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
1927 #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
1928 #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
1929 #define SDMA0_RLC3_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
1930 #define SDMA0_RLC3_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
1931 #define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
1932 #define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
1933 #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
1934 #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
1935 #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
1936 #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
1937 //SDMA0_RLC3_DOORBELL
1938 #define SDMA0_RLC3_DOORBELL__ENABLE__SHIFT                                                                    0x1c
1939 #define SDMA0_RLC3_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
1940 #define SDMA0_RLC3_DOORBELL__ENABLE_MASK                                                                      0x10000000L
1941 #define SDMA0_RLC3_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
1942 //SDMA0_RLC3_STATUS
1943 #define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
1944 #define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
1945 #define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
1946 #define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
1947 //SDMA0_RLC3_DOORBELL_LOG
1948 //SDMA0_RLC3_WATERMARK
1949 #define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
1950 #define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
1951 #define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
1952 #define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
1953 //SDMA0_RLC3_DOORBELL_OFFSET
1954 #define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
1955 #define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
1956 //SDMA0_RLC3_CSA_ADDR_LO
1957 #define SDMA0_RLC3_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
1958 #define SDMA0_RLC3_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
1959 //SDMA0_RLC3_CSA_ADDR_HI
1960 #define SDMA0_RLC3_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
1961 #define SDMA0_RLC3_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
1962 //SDMA0_RLC3_IB_SUB_REMAIN
1963 #define SDMA0_RLC3_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
1964 #define SDMA0_RLC3_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
1965 //SDMA0_RLC3_PREEMPT
1966 #define SDMA0_RLC3_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
1967 #define SDMA0_RLC3_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
1968 //SDMA0_RLC3_DUMMY_REG
1969 #define SDMA0_RLC3_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
1970 #define SDMA0_RLC3_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
1971 //SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI
1972 #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
1973 #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
1974 //SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO
1975 #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
1976 #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
1977 //SDMA0_RLC3_RB_AQL_CNTL
1978 #define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
1979 #define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
1980 #define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
1981 #define SDMA0_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
1982 #define SDMA0_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
1983 #define SDMA0_RLC3_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
1984 #define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
1985 #define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
1986 #define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
1987 #define SDMA0_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
1988 #define SDMA0_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
1989 #define SDMA0_RLC3_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
1990 //SDMA0_RLC3_MINOR_PTR_UPDATE
1991 #define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
1992 #define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
1993 //SDMA0_RLC3_MIDCMD_DATA0
1994 #define SDMA0_RLC3_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
1995 #define SDMA0_RLC3_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
1996 //SDMA0_RLC3_MIDCMD_DATA1
1997 #define SDMA0_RLC3_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
1998 #define SDMA0_RLC3_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
1999 //SDMA0_RLC3_MIDCMD_DATA2
2000 #define SDMA0_RLC3_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
2001 #define SDMA0_RLC3_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
2002 //SDMA0_RLC3_MIDCMD_DATA3
2003 #define SDMA0_RLC3_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
2004 #define SDMA0_RLC3_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
2005 //SDMA0_RLC3_MIDCMD_DATA4
2006 #define SDMA0_RLC3_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
2007 #define SDMA0_RLC3_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
2008 //SDMA0_RLC3_MIDCMD_DATA5
2009 #define SDMA0_RLC3_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
2010 #define SDMA0_RLC3_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
2011 //SDMA0_RLC3_MIDCMD_DATA6
2012 #define SDMA0_RLC3_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
2013 #define SDMA0_RLC3_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
2014 //SDMA0_RLC3_MIDCMD_DATA7
2015 #define SDMA0_RLC3_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
2016 #define SDMA0_RLC3_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
2017 //SDMA0_RLC3_MIDCMD_DATA8
2018 #define SDMA0_RLC3_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
2019 #define SDMA0_RLC3_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
2020 //SDMA0_RLC3_MIDCMD_CNTL
2021 #define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
2022 #define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
2023 #define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
2024 #define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
2025 #define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
2026 #define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
2027 #define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
2028 #define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
2029 //SDMA0_RLC4_RB_CNTL
2030 #define SDMA0_RLC4_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
2031 #define SDMA0_RLC4_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
2032 #define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
2033 #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
2034 #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
2035 #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
2036 #define SDMA0_RLC4_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
2037 #define SDMA0_RLC4_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
2038 #define SDMA0_RLC4_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
2039 #define SDMA0_RLC4_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
2040 #define SDMA0_RLC4_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
2041 #define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
2042 #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
2043 #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
2044 #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
2045 #define SDMA0_RLC4_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
2046 #define SDMA0_RLC4_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
2047 #define SDMA0_RLC4_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
2048 //SDMA0_RLC4_RB_BASE
2049 #define SDMA0_RLC4_RB_BASE__ADDR__SHIFT                                                                       0x0
2050 #define SDMA0_RLC4_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
2051 //SDMA0_RLC4_RB_BASE_HI
2052 #define SDMA0_RLC4_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
2053 #define SDMA0_RLC4_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
2054 //SDMA0_RLC4_RB_RPTR
2055 #define SDMA0_RLC4_RB_RPTR__OFFSET__SHIFT                                                                     0x0
2056 #define SDMA0_RLC4_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
2057 //SDMA0_RLC4_RB_RPTR_HI
2058 #define SDMA0_RLC4_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
2059 #define SDMA0_RLC4_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
2060 //SDMA0_RLC4_RB_WPTR
2061 #define SDMA0_RLC4_RB_WPTR__OFFSET__SHIFT                                                                     0x0
2062 #define SDMA0_RLC4_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
2063 //SDMA0_RLC4_RB_WPTR_HI
2064 #define SDMA0_RLC4_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
2065 #define SDMA0_RLC4_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
2066 //SDMA0_RLC4_RB_WPTR_POLL_CNTL
2067 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
2068 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
2069 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
2070 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
2071 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
2072 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
2073 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
2074 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
2075 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
2076 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
2077 //SDMA0_RLC4_RB_RPTR_ADDR_HI
2078 #define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
2079 #define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
2080 //SDMA0_RLC4_RB_RPTR_ADDR_LO
2081 #define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
2082 #define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
2083 //SDMA0_RLC4_IB_CNTL
2084 #define SDMA0_RLC4_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
2085 #define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
2086 #define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
2087 #define SDMA0_RLC4_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
2088 #define SDMA0_RLC4_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
2089 #define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
2090 #define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
2091 #define SDMA0_RLC4_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
2092 //SDMA0_RLC4_IB_RPTR
2093 #define SDMA0_RLC4_IB_RPTR__OFFSET__SHIFT                                                                     0x2
2094 #define SDMA0_RLC4_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
2095 //SDMA0_RLC4_IB_OFFSET
2096 #define SDMA0_RLC4_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
2097 #define SDMA0_RLC4_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
2098 //SDMA0_RLC4_IB_BASE_LO
2099 #define SDMA0_RLC4_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
2100 #define SDMA0_RLC4_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
2101 //SDMA0_RLC4_IB_BASE_HI
2102 #define SDMA0_RLC4_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
2103 #define SDMA0_RLC4_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
2104 //SDMA0_RLC4_IB_SIZE
2105 #define SDMA0_RLC4_IB_SIZE__SIZE__SHIFT                                                                       0x0
2106 #define SDMA0_RLC4_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
2107 //SDMA0_RLC4_SKIP_CNTL
2108 #define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
2109 #define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
2110 //SDMA0_RLC4_CONTEXT_STATUS
2111 #define SDMA0_RLC4_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
2112 #define SDMA0_RLC4_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
2113 #define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
2114 #define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
2115 #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
2116 #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
2117 #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
2118 #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
2119 #define SDMA0_RLC4_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
2120 #define SDMA0_RLC4_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
2121 #define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
2122 #define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
2123 #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
2124 #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
2125 #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
2126 #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
2127 //SDMA0_RLC4_DOORBELL
2128 #define SDMA0_RLC4_DOORBELL__ENABLE__SHIFT                                                                    0x1c
2129 #define SDMA0_RLC4_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
2130 #define SDMA0_RLC4_DOORBELL__ENABLE_MASK                                                                      0x10000000L
2131 #define SDMA0_RLC4_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
2132 //SDMA0_RLC4_STATUS
2133 #define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
2134 #define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
2135 #define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
2136 #define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
2137 //SDMA0_RLC4_DOORBELL_LOG
2138 //SDMA0_RLC4_WATERMARK
2139 #define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
2140 #define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
2141 #define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
2142 #define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
2143 //SDMA0_RLC4_DOORBELL_OFFSET
2144 #define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
2145 #define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
2146 //SDMA0_RLC4_CSA_ADDR_LO
2147 #define SDMA0_RLC4_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
2148 #define SDMA0_RLC4_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
2149 //SDMA0_RLC4_CSA_ADDR_HI
2150 #define SDMA0_RLC4_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
2151 #define SDMA0_RLC4_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
2152 //SDMA0_RLC4_IB_SUB_REMAIN
2153 #define SDMA0_RLC4_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
2154 #define SDMA0_RLC4_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
2155 //SDMA0_RLC4_PREEMPT
2156 #define SDMA0_RLC4_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
2157 #define SDMA0_RLC4_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
2158 //SDMA0_RLC4_DUMMY_REG
2159 #define SDMA0_RLC4_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
2160 #define SDMA0_RLC4_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
2161 //SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI
2162 #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
2163 #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
2164 //SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO
2165 #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
2166 #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
2167 //SDMA0_RLC4_RB_AQL_CNTL
2168 #define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
2169 #define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
2170 #define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
2171 #define SDMA0_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
2172 #define SDMA0_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
2173 #define SDMA0_RLC4_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
2174 #define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
2175 #define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
2176 #define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
2177 #define SDMA0_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
2178 #define SDMA0_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
2179 #define SDMA0_RLC4_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
2180 //SDMA0_RLC4_MINOR_PTR_UPDATE
2181 #define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
2182 #define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
2183 //SDMA0_RLC4_MIDCMD_DATA0
2184 #define SDMA0_RLC4_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
2185 #define SDMA0_RLC4_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
2186 //SDMA0_RLC4_MIDCMD_DATA1
2187 #define SDMA0_RLC4_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
2188 #define SDMA0_RLC4_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
2189 //SDMA0_RLC4_MIDCMD_DATA2
2190 #define SDMA0_RLC4_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
2191 #define SDMA0_RLC4_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
2192 //SDMA0_RLC4_MIDCMD_DATA3
2193 #define SDMA0_RLC4_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
2194 #define SDMA0_RLC4_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
2195 //SDMA0_RLC4_MIDCMD_DATA4
2196 #define SDMA0_RLC4_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
2197 #define SDMA0_RLC4_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
2198 //SDMA0_RLC4_MIDCMD_DATA5
2199 #define SDMA0_RLC4_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
2200 #define SDMA0_RLC4_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
2201 //SDMA0_RLC4_MIDCMD_DATA6
2202 #define SDMA0_RLC4_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
2203 #define SDMA0_RLC4_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
2204 //SDMA0_RLC4_MIDCMD_DATA7
2205 #define SDMA0_RLC4_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
2206 #define SDMA0_RLC4_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
2207 //SDMA0_RLC4_MIDCMD_DATA8
2208 #define SDMA0_RLC4_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
2209 #define SDMA0_RLC4_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
2210 //SDMA0_RLC4_MIDCMD_CNTL
2211 #define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
2212 #define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
2213 #define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
2214 #define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
2215 #define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
2216 #define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
2217 #define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
2218 #define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
2219 //SDMA0_RLC5_RB_CNTL
2220 #define SDMA0_RLC5_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
2221 #define SDMA0_RLC5_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
2222 #define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
2223 #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
2224 #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
2225 #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
2226 #define SDMA0_RLC5_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
2227 #define SDMA0_RLC5_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
2228 #define SDMA0_RLC5_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
2229 #define SDMA0_RLC5_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
2230 #define SDMA0_RLC5_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
2231 #define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
2232 #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
2233 #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
2234 #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
2235 #define SDMA0_RLC5_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
2236 #define SDMA0_RLC5_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
2237 #define SDMA0_RLC5_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
2238 //SDMA0_RLC5_RB_BASE
2239 #define SDMA0_RLC5_RB_BASE__ADDR__SHIFT                                                                       0x0
2240 #define SDMA0_RLC5_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
2241 //SDMA0_RLC5_RB_BASE_HI
2242 #define SDMA0_RLC5_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
2243 #define SDMA0_RLC5_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
2244 //SDMA0_RLC5_RB_RPTR
2245 #define SDMA0_RLC5_RB_RPTR__OFFSET__SHIFT                                                                     0x0
2246 #define SDMA0_RLC5_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
2247 //SDMA0_RLC5_RB_RPTR_HI
2248 #define SDMA0_RLC5_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
2249 #define SDMA0_RLC5_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
2250 //SDMA0_RLC5_RB_WPTR
2251 #define SDMA0_RLC5_RB_WPTR__OFFSET__SHIFT                                                                     0x0
2252 #define SDMA0_RLC5_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
2253 //SDMA0_RLC5_RB_WPTR_HI
2254 #define SDMA0_RLC5_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
2255 #define SDMA0_RLC5_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
2256 //SDMA0_RLC5_RB_WPTR_POLL_CNTL
2257 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
2258 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
2259 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
2260 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
2261 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
2262 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
2263 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
2264 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
2265 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
2266 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
2267 //SDMA0_RLC5_RB_RPTR_ADDR_HI
2268 #define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
2269 #define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
2270 //SDMA0_RLC5_RB_RPTR_ADDR_LO
2271 #define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
2272 #define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
2273 //SDMA0_RLC5_IB_CNTL
2274 #define SDMA0_RLC5_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
2275 #define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
2276 #define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
2277 #define SDMA0_RLC5_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
2278 #define SDMA0_RLC5_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
2279 #define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
2280 #define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
2281 #define SDMA0_RLC5_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
2282 //SDMA0_RLC5_IB_RPTR
2283 #define SDMA0_RLC5_IB_RPTR__OFFSET__SHIFT                                                                     0x2
2284 #define SDMA0_RLC5_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
2285 //SDMA0_RLC5_IB_OFFSET
2286 #define SDMA0_RLC5_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
2287 #define SDMA0_RLC5_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
2288 //SDMA0_RLC5_IB_BASE_LO
2289 #define SDMA0_RLC5_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
2290 #define SDMA0_RLC5_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
2291 //SDMA0_RLC5_IB_BASE_HI
2292 #define SDMA0_RLC5_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
2293 #define SDMA0_RLC5_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
2294 //SDMA0_RLC5_IB_SIZE
2295 #define SDMA0_RLC5_IB_SIZE__SIZE__SHIFT                                                                       0x0
2296 #define SDMA0_RLC5_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
2297 //SDMA0_RLC5_SKIP_CNTL
2298 #define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
2299 #define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
2300 //SDMA0_RLC5_CONTEXT_STATUS
2301 #define SDMA0_RLC5_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
2302 #define SDMA0_RLC5_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
2303 #define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
2304 #define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
2305 #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
2306 #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
2307 #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
2308 #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
2309 #define SDMA0_RLC5_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
2310 #define SDMA0_RLC5_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
2311 #define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
2312 #define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
2313 #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
2314 #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
2315 #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
2316 #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
2317 //SDMA0_RLC5_DOORBELL
2318 #define SDMA0_RLC5_DOORBELL__ENABLE__SHIFT                                                                    0x1c
2319 #define SDMA0_RLC5_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
2320 #define SDMA0_RLC5_DOORBELL__ENABLE_MASK                                                                      0x10000000L
2321 #define SDMA0_RLC5_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
2322 //SDMA0_RLC5_STATUS
2323 #define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
2324 #define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
2325 #define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
2326 #define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
2327 //SDMA0_RLC5_DOORBELL_LOG
2328 //SDMA0_RLC5_WATERMARK
2329 #define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
2330 #define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
2331 #define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
2332 #define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
2333 //SDMA0_RLC5_DOORBELL_OFFSET
2334 #define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
2335 #define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
2336 //SDMA0_RLC5_CSA_ADDR_LO
2337 #define SDMA0_RLC5_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
2338 #define SDMA0_RLC5_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
2339 //SDMA0_RLC5_CSA_ADDR_HI
2340 #define SDMA0_RLC5_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
2341 #define SDMA0_RLC5_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
2342 //SDMA0_RLC5_IB_SUB_REMAIN
2343 #define SDMA0_RLC5_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
2344 #define SDMA0_RLC5_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
2345 //SDMA0_RLC5_PREEMPT
2346 #define SDMA0_RLC5_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
2347 #define SDMA0_RLC5_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
2348 //SDMA0_RLC5_DUMMY_REG
2349 #define SDMA0_RLC5_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
2350 #define SDMA0_RLC5_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
2351 //SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI
2352 #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
2353 #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
2354 //SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO
2355 #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
2356 #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
2357 //SDMA0_RLC5_RB_AQL_CNTL
2358 #define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
2359 #define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
2360 #define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
2361 #define SDMA0_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
2362 #define SDMA0_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
2363 #define SDMA0_RLC5_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
2364 #define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
2365 #define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
2366 #define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
2367 #define SDMA0_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
2368 #define SDMA0_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
2369 #define SDMA0_RLC5_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
2370 //SDMA0_RLC5_MINOR_PTR_UPDATE
2371 #define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
2372 #define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
2373 //SDMA0_RLC5_MIDCMD_DATA0
2374 #define SDMA0_RLC5_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
2375 #define SDMA0_RLC5_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
2376 //SDMA0_RLC5_MIDCMD_DATA1
2377 #define SDMA0_RLC5_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
2378 #define SDMA0_RLC5_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
2379 //SDMA0_RLC5_MIDCMD_DATA2
2380 #define SDMA0_RLC5_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
2381 #define SDMA0_RLC5_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
2382 //SDMA0_RLC5_MIDCMD_DATA3
2383 #define SDMA0_RLC5_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
2384 #define SDMA0_RLC5_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
2385 //SDMA0_RLC5_MIDCMD_DATA4
2386 #define SDMA0_RLC5_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
2387 #define SDMA0_RLC5_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
2388 //SDMA0_RLC5_MIDCMD_DATA5
2389 #define SDMA0_RLC5_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
2390 #define SDMA0_RLC5_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
2391 //SDMA0_RLC5_MIDCMD_DATA6
2392 #define SDMA0_RLC5_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
2393 #define SDMA0_RLC5_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
2394 //SDMA0_RLC5_MIDCMD_DATA7
2395 #define SDMA0_RLC5_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
2396 #define SDMA0_RLC5_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
2397 //SDMA0_RLC5_MIDCMD_DATA8
2398 #define SDMA0_RLC5_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
2399 #define SDMA0_RLC5_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
2400 //SDMA0_RLC5_MIDCMD_CNTL
2401 #define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
2402 #define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
2403 #define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
2404 #define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
2405 #define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
2406 #define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
2407 #define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
2408 #define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
2409 //SDMA0_RLC6_RB_CNTL
2410 #define SDMA0_RLC6_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
2411 #define SDMA0_RLC6_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
2412 #define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
2413 #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
2414 #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
2415 #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
2416 #define SDMA0_RLC6_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
2417 #define SDMA0_RLC6_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
2418 #define SDMA0_RLC6_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
2419 #define SDMA0_RLC6_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
2420 #define SDMA0_RLC6_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
2421 #define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
2422 #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
2423 #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
2424 #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
2425 #define SDMA0_RLC6_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
2426 #define SDMA0_RLC6_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
2427 #define SDMA0_RLC6_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
2428 //SDMA0_RLC6_RB_BASE
2429 #define SDMA0_RLC6_RB_BASE__ADDR__SHIFT                                                                       0x0
2430 #define SDMA0_RLC6_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
2431 //SDMA0_RLC6_RB_BASE_HI
2432 #define SDMA0_RLC6_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
2433 #define SDMA0_RLC6_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
2434 //SDMA0_RLC6_RB_RPTR
2435 #define SDMA0_RLC6_RB_RPTR__OFFSET__SHIFT                                                                     0x0
2436 #define SDMA0_RLC6_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
2437 //SDMA0_RLC6_RB_RPTR_HI
2438 #define SDMA0_RLC6_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
2439 #define SDMA0_RLC6_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
2440 //SDMA0_RLC6_RB_WPTR
2441 #define SDMA0_RLC6_RB_WPTR__OFFSET__SHIFT                                                                     0x0
2442 #define SDMA0_RLC6_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
2443 //SDMA0_RLC6_RB_WPTR_HI
2444 #define SDMA0_RLC6_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
2445 #define SDMA0_RLC6_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
2446 //SDMA0_RLC6_RB_WPTR_POLL_CNTL
2447 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
2448 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
2449 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
2450 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
2451 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
2452 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
2453 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
2454 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
2455 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
2456 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
2457 //SDMA0_RLC6_RB_RPTR_ADDR_HI
2458 #define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
2459 #define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
2460 //SDMA0_RLC6_RB_RPTR_ADDR_LO
2461 #define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
2462 #define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
2463 //SDMA0_RLC6_IB_CNTL
2464 #define SDMA0_RLC6_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
2465 #define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
2466 #define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
2467 #define SDMA0_RLC6_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
2468 #define SDMA0_RLC6_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
2469 #define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
2470 #define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
2471 #define SDMA0_RLC6_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
2472 //SDMA0_RLC6_IB_RPTR
2473 #define SDMA0_RLC6_IB_RPTR__OFFSET__SHIFT                                                                     0x2
2474 #define SDMA0_RLC6_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
2475 //SDMA0_RLC6_IB_OFFSET
2476 #define SDMA0_RLC6_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
2477 #define SDMA0_RLC6_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
2478 //SDMA0_RLC6_IB_BASE_LO
2479 #define SDMA0_RLC6_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
2480 #define SDMA0_RLC6_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
2481 //SDMA0_RLC6_IB_BASE_HI
2482 #define SDMA0_RLC6_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
2483 #define SDMA0_RLC6_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
2484 //SDMA0_RLC6_IB_SIZE
2485 #define SDMA0_RLC6_IB_SIZE__SIZE__SHIFT                                                                       0x0
2486 #define SDMA0_RLC6_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
2487 //SDMA0_RLC6_SKIP_CNTL
2488 #define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
2489 #define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
2490 //SDMA0_RLC6_CONTEXT_STATUS
2491 #define SDMA0_RLC6_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
2492 #define SDMA0_RLC6_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
2493 #define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
2494 #define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
2495 #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
2496 #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
2497 #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
2498 #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
2499 #define SDMA0_RLC6_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
2500 #define SDMA0_RLC6_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
2501 #define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
2502 #define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
2503 #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
2504 #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
2505 #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
2506 #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
2507 //SDMA0_RLC6_DOORBELL
2508 #define SDMA0_RLC6_DOORBELL__ENABLE__SHIFT                                                                    0x1c
2509 #define SDMA0_RLC6_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
2510 #define SDMA0_RLC6_DOORBELL__ENABLE_MASK                                                                      0x10000000L
2511 #define SDMA0_RLC6_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
2512 //SDMA0_RLC6_STATUS
2513 #define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
2514 #define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
2515 #define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
2516 #define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
2517 //SDMA0_RLC6_DOORBELL_LOG
2518 //SDMA0_RLC6_WATERMARK
2519 #define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
2520 #define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
2521 #define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
2522 #define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
2523 //SDMA0_RLC6_DOORBELL_OFFSET
2524 #define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
2525 #define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
2526 //SDMA0_RLC6_CSA_ADDR_LO
2527 #define SDMA0_RLC6_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
2528 #define SDMA0_RLC6_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
2529 //SDMA0_RLC6_CSA_ADDR_HI
2530 #define SDMA0_RLC6_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
2531 #define SDMA0_RLC6_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
2532 //SDMA0_RLC6_IB_SUB_REMAIN
2533 #define SDMA0_RLC6_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
2534 #define SDMA0_RLC6_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
2535 //SDMA0_RLC6_PREEMPT
2536 #define SDMA0_RLC6_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
2537 #define SDMA0_RLC6_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
2538 //SDMA0_RLC6_DUMMY_REG
2539 #define SDMA0_RLC6_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
2540 #define SDMA0_RLC6_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
2541 //SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI
2542 #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
2543 #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
2544 //SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO
2545 #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
2546 #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
2547 //SDMA0_RLC6_RB_AQL_CNTL
2548 #define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
2549 #define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
2550 #define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
2551 #define SDMA0_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
2552 #define SDMA0_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
2553 #define SDMA0_RLC6_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
2554 #define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
2555 #define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
2556 #define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
2557 #define SDMA0_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
2558 #define SDMA0_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
2559 #define SDMA0_RLC6_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
2560 //SDMA0_RLC6_MINOR_PTR_UPDATE
2561 #define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
2562 #define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
2563 //SDMA0_RLC6_MIDCMD_DATA0
2564 #define SDMA0_RLC6_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
2565 #define SDMA0_RLC6_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
2566 //SDMA0_RLC6_MIDCMD_DATA1
2567 #define SDMA0_RLC6_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
2568 #define SDMA0_RLC6_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
2569 //SDMA0_RLC6_MIDCMD_DATA2
2570 #define SDMA0_RLC6_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
2571 #define SDMA0_RLC6_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
2572 //SDMA0_RLC6_MIDCMD_DATA3
2573 #define SDMA0_RLC6_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
2574 #define SDMA0_RLC6_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
2575 //SDMA0_RLC6_MIDCMD_DATA4
2576 #define SDMA0_RLC6_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
2577 #define SDMA0_RLC6_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
2578 //SDMA0_RLC6_MIDCMD_DATA5
2579 #define SDMA0_RLC6_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
2580 #define SDMA0_RLC6_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
2581 //SDMA0_RLC6_MIDCMD_DATA6
2582 #define SDMA0_RLC6_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
2583 #define SDMA0_RLC6_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
2584 //SDMA0_RLC6_MIDCMD_DATA7
2585 #define SDMA0_RLC6_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
2586 #define SDMA0_RLC6_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
2587 //SDMA0_RLC6_MIDCMD_DATA8
2588 #define SDMA0_RLC6_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
2589 #define SDMA0_RLC6_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
2590 //SDMA0_RLC6_MIDCMD_CNTL
2591 #define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
2592 #define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
2593 #define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
2594 #define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
2595 #define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
2596 #define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
2597 #define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
2598 #define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
2599 //SDMA0_RLC7_RB_CNTL
2600 #define SDMA0_RLC7_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
2601 #define SDMA0_RLC7_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
2602 #define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
2603 #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
2604 #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
2605 #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
2606 #define SDMA0_RLC7_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
2607 #define SDMA0_RLC7_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
2608 #define SDMA0_RLC7_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
2609 #define SDMA0_RLC7_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
2610 #define SDMA0_RLC7_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
2611 #define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
2612 #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
2613 #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
2614 #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
2615 #define SDMA0_RLC7_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
2616 #define SDMA0_RLC7_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
2617 #define SDMA0_RLC7_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
2618 //SDMA0_RLC7_RB_BASE
2619 #define SDMA0_RLC7_RB_BASE__ADDR__SHIFT                                                                       0x0
2620 #define SDMA0_RLC7_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
2621 //SDMA0_RLC7_RB_BASE_HI
2622 #define SDMA0_RLC7_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
2623 #define SDMA0_RLC7_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
2624 //SDMA0_RLC7_RB_RPTR
2625 #define SDMA0_RLC7_RB_RPTR__OFFSET__SHIFT                                                                     0x0
2626 #define SDMA0_RLC7_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
2627 //SDMA0_RLC7_RB_RPTR_HI
2628 #define SDMA0_RLC7_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
2629 #define SDMA0_RLC7_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
2630 //SDMA0_RLC7_RB_WPTR
2631 #define SDMA0_RLC7_RB_WPTR__OFFSET__SHIFT                                                                     0x0
2632 #define SDMA0_RLC7_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
2633 //SDMA0_RLC7_RB_WPTR_HI
2634 #define SDMA0_RLC7_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
2635 #define SDMA0_RLC7_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
2636 //SDMA0_RLC7_RB_WPTR_POLL_CNTL
2637 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
2638 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
2639 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
2640 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
2641 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
2642 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
2643 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
2644 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
2645 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
2646 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
2647 //SDMA0_RLC7_RB_RPTR_ADDR_HI
2648 #define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
2649 #define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
2650 //SDMA0_RLC7_RB_RPTR_ADDR_LO
2651 #define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
2652 #define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
2653 //SDMA0_RLC7_IB_CNTL
2654 #define SDMA0_RLC7_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
2655 #define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
2656 #define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
2657 #define SDMA0_RLC7_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
2658 #define SDMA0_RLC7_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
2659 #define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
2660 #define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
2661 #define SDMA0_RLC7_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
2662 //SDMA0_RLC7_IB_RPTR
2663 #define SDMA0_RLC7_IB_RPTR__OFFSET__SHIFT                                                                     0x2
2664 #define SDMA0_RLC7_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
2665 //SDMA0_RLC7_IB_OFFSET
2666 #define SDMA0_RLC7_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
2667 #define SDMA0_RLC7_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
2668 //SDMA0_RLC7_IB_BASE_LO
2669 #define SDMA0_RLC7_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
2670 #define SDMA0_RLC7_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
2671 //SDMA0_RLC7_IB_BASE_HI
2672 #define SDMA0_RLC7_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
2673 #define SDMA0_RLC7_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
2674 //SDMA0_RLC7_IB_SIZE
2675 #define SDMA0_RLC7_IB_SIZE__SIZE__SHIFT                                                                       0x0
2676 #define SDMA0_RLC7_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
2677 //SDMA0_RLC7_SKIP_CNTL
2678 #define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
2679 #define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
2680 //SDMA0_RLC7_CONTEXT_STATUS
2681 #define SDMA0_RLC7_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
2682 #define SDMA0_RLC7_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
2683 #define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
2684 #define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
2685 #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
2686 #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
2687 #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
2688 #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
2689 #define SDMA0_RLC7_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
2690 #define SDMA0_RLC7_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
2691 #define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
2692 #define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
2693 #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
2694 #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
2695 #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
2696 #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
2697 //SDMA0_RLC7_DOORBELL
2698 #define SDMA0_RLC7_DOORBELL__ENABLE__SHIFT                                                                    0x1c
2699 #define SDMA0_RLC7_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
2700 #define SDMA0_RLC7_DOORBELL__ENABLE_MASK                                                                      0x10000000L
2701 #define SDMA0_RLC7_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
2702 //SDMA0_RLC7_STATUS
2703 #define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
2704 #define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
2705 #define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
2706 #define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
2707 //SDMA0_RLC7_DOORBELL_LOG
2708 //SDMA0_RLC7_WATERMARK
2709 #define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
2710 #define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
2711 #define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
2712 #define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
2713 //SDMA0_RLC7_DOORBELL_OFFSET
2714 #define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
2715 #define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
2716 //SDMA0_RLC7_CSA_ADDR_LO
2717 #define SDMA0_RLC7_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
2718 #define SDMA0_RLC7_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
2719 //SDMA0_RLC7_CSA_ADDR_HI
2720 #define SDMA0_RLC7_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
2721 #define SDMA0_RLC7_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
2722 //SDMA0_RLC7_IB_SUB_REMAIN
2723 #define SDMA0_RLC7_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
2724 #define SDMA0_RLC7_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
2725 //SDMA0_RLC7_PREEMPT
2726 #define SDMA0_RLC7_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
2727 #define SDMA0_RLC7_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
2728 //SDMA0_RLC7_DUMMY_REG
2729 #define SDMA0_RLC7_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
2730 #define SDMA0_RLC7_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
2731 //SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI
2732 #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
2733 #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
2734 //SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO
2735 #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
2736 #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
2737 //SDMA0_RLC7_RB_AQL_CNTL
2738 #define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
2739 #define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
2740 #define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
2741 #define SDMA0_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
2742 #define SDMA0_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
2743 #define SDMA0_RLC7_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
2744 #define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
2745 #define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
2746 #define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
2747 #define SDMA0_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
2748 #define SDMA0_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
2749 #define SDMA0_RLC7_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
2750 //SDMA0_RLC7_MINOR_PTR_UPDATE
2751 #define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
2752 #define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
2753 //SDMA0_RLC7_MIDCMD_DATA0
2754 #define SDMA0_RLC7_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
2755 #define SDMA0_RLC7_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
2756 //SDMA0_RLC7_MIDCMD_DATA1
2757 #define SDMA0_RLC7_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
2758 #define SDMA0_RLC7_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
2759 //SDMA0_RLC7_MIDCMD_DATA2
2760 #define SDMA0_RLC7_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
2761 #define SDMA0_RLC7_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
2762 //SDMA0_RLC7_MIDCMD_DATA3
2763 #define SDMA0_RLC7_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
2764 #define SDMA0_RLC7_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
2765 //SDMA0_RLC7_MIDCMD_DATA4
2766 #define SDMA0_RLC7_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
2767 #define SDMA0_RLC7_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
2768 //SDMA0_RLC7_MIDCMD_DATA5
2769 #define SDMA0_RLC7_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
2770 #define SDMA0_RLC7_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
2771 //SDMA0_RLC7_MIDCMD_DATA6
2772 #define SDMA0_RLC7_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
2773 #define SDMA0_RLC7_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
2774 //SDMA0_RLC7_MIDCMD_DATA7
2775 #define SDMA0_RLC7_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
2776 #define SDMA0_RLC7_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
2777 //SDMA0_RLC7_MIDCMD_DATA8
2778 #define SDMA0_RLC7_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
2779 #define SDMA0_RLC7_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
2780 //SDMA0_RLC7_MIDCMD_CNTL
2781 #define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
2782 #define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
2783 #define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
2784 #define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
2785 #define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
2786 #define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
2787 #define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
2788 #define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
2789 
2790 
2791 // addressBlock: gc_sdma1_sdma1dec
2792 //SDMA1_DEC_START
2793 #define SDMA1_DEC_START__START__SHIFT                                                                         0x0
2794 #define SDMA1_DEC_START__START_MASK                                                                           0xFFFFFFFFL
2795 //SDMA1_PG_CNTL
2796 #define SDMA1_PG_CNTL__CMD__SHIFT                                                                             0x0
2797 #define SDMA1_PG_CNTL__STATUS__SHIFT                                                                          0x10
2798 #define SDMA1_PG_CNTL__CMD_MASK                                                                               0x0000000FL
2799 #define SDMA1_PG_CNTL__STATUS_MASK                                                                            0x000F0000L
2800 //SDMA1_PG_CTX_LO
2801 #define SDMA1_PG_CTX_LO__ADDR__SHIFT                                                                          0x0
2802 #define SDMA1_PG_CTX_LO__ADDR_MASK                                                                            0xFFFFFFFFL
2803 //SDMA1_PG_CTX_HI
2804 #define SDMA1_PG_CTX_HI__ADDR__SHIFT                                                                          0x0
2805 #define SDMA1_PG_CTX_HI__ADDR_MASK                                                                            0xFFFFFFFFL
2806 //SDMA1_PG_CTX_CNTL
2807 #define SDMA1_PG_CTX_CNTL__VMID__SHIFT                                                                        0x4
2808 #define SDMA1_PG_CTX_CNTL__VMID_MASK                                                                          0x000000F0L
2809 //SDMA1_POWER_CNTL
2810 #define SDMA1_POWER_CNTL__PG_CNTL_ENABLE__SHIFT                                                               0x0
2811 #define SDMA1_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT                                                          0x1
2812 #define SDMA1_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT                                                         0x2
2813 #define SDMA1_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT                                                   0x3
2814 #define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT                                                           0x8
2815 #define SDMA1_POWER_CNTL__MEM_POWER_LS_EN__SHIFT                                                              0x9
2816 #define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT                                                              0xa
2817 #define SDMA1_POWER_CNTL__MEM_POWER_SD_EN__SHIFT                                                              0xb
2818 #define SDMA1_POWER_CNTL__MEM_POWER_DELAY__SHIFT                                                              0xc
2819 #define SDMA1_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT                                                  0x1a
2820 #define SDMA1_POWER_CNTL__PG_CNTL_ENABLE_MASK                                                                 0x00000001L
2821 #define SDMA1_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK                                                            0x00000002L
2822 #define SDMA1_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK                                                           0x00000004L
2823 #define SDMA1_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK                                                     0x000000F8L
2824 #define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK                                                             0x00000100L
2825 #define SDMA1_POWER_CNTL__MEM_POWER_LS_EN_MASK                                                                0x00000200L
2826 #define SDMA1_POWER_CNTL__MEM_POWER_DS_EN_MASK                                                                0x00000400L
2827 #define SDMA1_POWER_CNTL__MEM_POWER_SD_EN_MASK                                                                0x00000800L
2828 #define SDMA1_POWER_CNTL__MEM_POWER_DELAY_MASK                                                                0x003FF000L
2829 #define SDMA1_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK                                                    0xFC000000L
2830 //SDMA1_CLK_CTRL
2831 #define SDMA1_CLK_CTRL__ON_DELAY__SHIFT                                                                       0x0
2832 #define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                                 0x4
2833 #define SDMA1_CLK_CTRL__RESERVED__SHIFT                                                                       0xc
2834 #define SDMA1_CLK_CTRL__UTCL1_FORCE_INV_RET_FIFO_FULL_EN__SHIFT                                               0x17
2835 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                                 0x18
2836 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                                 0x19
2837 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                                 0x1a
2838 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                                 0x1b
2839 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                                 0x1c
2840 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                                 0x1d
2841 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                                 0x1e
2842 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                                 0x1f
2843 #define SDMA1_CLK_CTRL__ON_DELAY_MASK                                                                         0x0000000FL
2844 #define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                   0x00000FF0L
2845 #define SDMA1_CLK_CTRL__RESERVED_MASK                                                                         0x007FF000L
2846 #define SDMA1_CLK_CTRL__UTCL1_FORCE_INV_RET_FIFO_FULL_EN_MASK                                                 0x00800000L
2847 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                                   0x01000000L
2848 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                                   0x02000000L
2849 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                                   0x04000000L
2850 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                                   0x08000000L
2851 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                                   0x10000000L
2852 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                                   0x20000000L
2853 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK                                                                   0x40000000L
2854 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK                                                                   0x80000000L
2855 //SDMA1_CNTL
2856 #define SDMA1_CNTL__TRAP_ENABLE__SHIFT                                                                        0x0
2857 #define SDMA1_CNTL__UTC_L1_ENABLE__SHIFT                                                                      0x1
2858 #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT                                                                0x2
2859 #define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT                                                                   0x3
2860 #define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT                                                                  0x4
2861 #define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                              0x5
2862 #define SDMA1_CNTL__PAGE_INT_ENABLE__SHIFT                                                                    0x7
2863 #define SDMA1_CNTL__CH_PERFCNT_ENABLE__SHIFT                                                                  0x10
2864 #define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT                                                          0x11
2865 #define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT                                                                  0x12
2866 #define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT                                                                0x1c
2867 #define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT                                                                  0x1d
2868 #define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT                                                              0x1e
2869 #define SDMA1_CNTL__TRAP_ENABLE_MASK                                                                          0x00000001L
2870 #define SDMA1_CNTL__UTC_L1_ENABLE_MASK                                                                        0x00000002L
2871 #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK                                                                  0x00000004L
2872 #define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK                                                                     0x00000008L
2873 #define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK                                                                    0x00000010L
2874 #define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                                0x00000020L
2875 #define SDMA1_CNTL__PAGE_INT_ENABLE_MASK                                                                      0x00000080L
2876 #define SDMA1_CNTL__CH_PERFCNT_ENABLE_MASK                                                                    0x00010000L
2877 #define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK                                                            0x00020000L
2878 #define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK                                                                    0x00040000L
2879 #define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK                                                                  0x10000000L
2880 #define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK                                                                    0x20000000L
2881 #define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK                                                                0x40000000L
2882 //SDMA1_CHICKEN_BITS
2883 #define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT                                                     0x0
2884 #define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT                                                 0x1
2885 #define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT                                        0x2
2886 #define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT                                                         0x8
2887 #define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT                                                     0xa
2888 #define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT                                                        0x10
2889 #define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT                                                           0x11
2890 #define SDMA1_CHICKEN_BITS__T2L_256B_ENABLE__SHIFT                                                            0x12
2891 #define SDMA1_CHICKEN_BITS__GCR_FGCG_ENABLE__SHIFT                                                            0x13
2892 #define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT                                                         0x14
2893 #define SDMA1_CHICKEN_BITS__CH_FGCG_ENABLE__SHIFT                                                             0x15
2894 #define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT                                                           0x17
2895 #define SDMA1_CHICKEN_BITS__UTCL1_FGCG_ENABLE__SHIFT                                                          0x18
2896 #define SDMA1_CHICKEN_BITS__TIME_BASED_QOS__SHIFT                                                             0x19
2897 #define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT                                                         0x1a
2898 #define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT                                                         0x1c
2899 #define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT                                                         0x1e
2900 #define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK                                                       0x00000001L
2901 #define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK                                                   0x00000002L
2902 #define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK                                          0x00000004L
2903 #define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK                                                           0x00000300L
2904 #define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK                                                       0x00001C00L
2905 #define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK                                                          0x00010000L
2906 #define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK                                                             0x00020000L
2907 #define SDMA1_CHICKEN_BITS__T2L_256B_ENABLE_MASK                                                              0x00040000L
2908 #define SDMA1_CHICKEN_BITS__GCR_FGCG_ENABLE_MASK                                                              0x00080000L
2909 #define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK                                                           0x00100000L
2910 #define SDMA1_CHICKEN_BITS__CH_FGCG_ENABLE_MASK                                                               0x00200000L
2911 #define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK                                                             0x00800000L
2912 #define SDMA1_CHICKEN_BITS__UTCL1_FGCG_ENABLE_MASK                                                            0x01000000L
2913 #define SDMA1_CHICKEN_BITS__TIME_BASED_QOS_MASK                                                               0x02000000L
2914 #define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK                                                           0x0C000000L
2915 #define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK                                                           0x30000000L
2916 #define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK                                                           0xC0000000L
2917 //SDMA1_GB_ADDR_CONFIG
2918 #define SDMA1_GB_ADDR_CONFIG__NUM_PIPES__SHIFT                                                                0x0
2919 #define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                     0x3
2920 #define SDMA1_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                     0x6
2921 #define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT                                                     0x8
2922 #define SDMA1_GB_ADDR_CONFIG__NUM_BANKS__SHIFT                                                                0xc
2923 #define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT                                                       0x13
2924 #define SDMA1_GB_ADDR_CONFIG__NUM_PIPES_MASK                                                                  0x00000007L
2925 #define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                       0x00000038L
2926 #define SDMA1_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                       0x000000C0L
2927 #define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK                                                       0x00000700L
2928 #define SDMA1_GB_ADDR_CONFIG__NUM_BANKS_MASK                                                                  0x00007000L
2929 #define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK                                                         0x00180000L
2930 //SDMA1_GB_ADDR_CONFIG_READ
2931 #define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT                                                           0x0
2932 #define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT                                                0x3
2933 #define SDMA1_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT                                                0x6
2934 #define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT                                                0x8
2935 #define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT                                                           0xc
2936 #define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT                                                  0x13
2937 #define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK                                                             0x00000007L
2938 #define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK                                                  0x00000038L
2939 #define SDMA1_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK                                                  0x000000C0L
2940 #define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK                                                  0x00000700L
2941 #define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK                                                             0x00007000L
2942 #define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK                                                    0x00180000L
2943 //SDMA1_RB_RPTR_FETCH_HI
2944 #define SDMA1_RB_RPTR_FETCH_HI__OFFSET__SHIFT                                                                 0x0
2945 #define SDMA1_RB_RPTR_FETCH_HI__OFFSET_MASK                                                                   0xFFFFFFFFL
2946 //SDMA1_SEM_WAIT_FAIL_TIMER_CNTL
2947 #define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT                                                          0x0
2948 #define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK                                                            0xFFFFFFFFL
2949 //SDMA1_RB_RPTR_FETCH
2950 #define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT                                                                    0x2
2951 #define SDMA1_RB_RPTR_FETCH__OFFSET_MASK                                                                      0xFFFFFFFCL
2952 //SDMA1_IB_OFFSET_FETCH
2953 #define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT                                                                  0x2
2954 #define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK                                                                    0x003FFFFCL
2955 //SDMA1_PROGRAM
2956 #define SDMA1_PROGRAM__STREAM__SHIFT                                                                          0x0
2957 #define SDMA1_PROGRAM__STREAM_MASK                                                                            0xFFFFFFFFL
2958 //SDMA1_STATUS_REG
2959 #define SDMA1_STATUS_REG__IDLE__SHIFT                                                                         0x0
2960 #define SDMA1_STATUS_REG__REG_IDLE__SHIFT                                                                     0x1
2961 #define SDMA1_STATUS_REG__RB_EMPTY__SHIFT                                                                     0x2
2962 #define SDMA1_STATUS_REG__RB_FULL__SHIFT                                                                      0x3
2963 #define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT                                                                  0x4
2964 #define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT                                                                  0x5
2965 #define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT                                                                  0x6
2966 #define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT                                                                  0x7
2967 #define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT                                                                   0x8
2968 #define SDMA1_STATUS_REG__INSIDE_IB__SHIFT                                                                    0x9
2969 #define SDMA1_STATUS_REG__EX_IDLE__SHIFT                                                                      0xa
2970 #define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT                                                    0xb
2971 #define SDMA1_STATUS_REG__PACKET_READY__SHIFT                                                                 0xc
2972 #define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT                                                                   0xd
2973 #define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT                                                                    0xe
2974 #define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT                                                                0xf
2975 #define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT                                                              0x10
2976 #define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT                                                              0x11
2977 #define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT                                                              0x12
2978 #define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT                                                                   0x13
2979 #define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT                                                             0x14
2980 #define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT                                                              0x15
2981 #define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT                                                           0x16
2982 #define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT                                                                0x19
2983 #define SDMA1_STATUS_REG__SEM_IDLE__SHIFT                                                                     0x1a
2984 #define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT                                                                0x1b
2985 #define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT                                                               0x1c
2986 #define SDMA1_STATUS_REG__INT_IDLE__SHIFT                                                                     0x1e
2987 #define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT                                                                0x1f
2988 #define SDMA1_STATUS_REG__IDLE_MASK                                                                           0x00000001L
2989 #define SDMA1_STATUS_REG__REG_IDLE_MASK                                                                       0x00000002L
2990 #define SDMA1_STATUS_REG__RB_EMPTY_MASK                                                                       0x00000004L
2991 #define SDMA1_STATUS_REG__RB_FULL_MASK                                                                        0x00000008L
2992 #define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK                                                                    0x00000010L
2993 #define SDMA1_STATUS_REG__RB_CMD_FULL_MASK                                                                    0x00000020L
2994 #define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK                                                                    0x00000040L
2995 #define SDMA1_STATUS_REG__IB_CMD_FULL_MASK                                                                    0x00000080L
2996 #define SDMA1_STATUS_REG__BLOCK_IDLE_MASK                                                                     0x00000100L
2997 #define SDMA1_STATUS_REG__INSIDE_IB_MASK                                                                      0x00000200L
2998 #define SDMA1_STATUS_REG__EX_IDLE_MASK                                                                        0x00000400L
2999 #define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK                                                      0x00000800L
3000 #define SDMA1_STATUS_REG__PACKET_READY_MASK                                                                   0x00001000L
3001 #define SDMA1_STATUS_REG__MC_WR_IDLE_MASK                                                                     0x00002000L
3002 #define SDMA1_STATUS_REG__SRBM_IDLE_MASK                                                                      0x00004000L
3003 #define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK                                                                  0x00008000L
3004 #define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK                                                                0x00010000L
3005 #define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK                                                                0x00020000L
3006 #define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK                                                                0x00040000L
3007 #define SDMA1_STATUS_REG__MC_RD_IDLE_MASK                                                                     0x00080000L
3008 #define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK                                                               0x00100000L
3009 #define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK                                                                0x00200000L
3010 #define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK                                                             0x00400000L
3011 #define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK                                                                  0x02000000L
3012 #define SDMA1_STATUS_REG__SEM_IDLE_MASK                                                                       0x04000000L
3013 #define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK                                                                  0x08000000L
3014 #define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK                                                                 0x30000000L
3015 #define SDMA1_STATUS_REG__INT_IDLE_MASK                                                                       0x40000000L
3016 #define SDMA1_STATUS_REG__INT_REQ_STALL_MASK                                                                  0x80000000L
3017 //SDMA1_STATUS1_REG
3018 #define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT                                                                0x0
3019 #define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT                                                                  0x1
3020 #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT                                                               0x2
3021 #define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT                                                                0x3
3022 #define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT                                                                 0x4
3023 #define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT                                                                  0x5
3024 #define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT                                                                 0x6
3025 #define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT                                                                 0x9
3026 #define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT                                                               0xa
3027 #define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT                                                                0xd
3028 #define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT                                                               0xe
3029 #define SDMA1_STATUS1_REG__EX_START__SHIFT                                                                    0xf
3030 #define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT                                                                 0x11
3031 #define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT                                                                 0x12
3032 #define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK                                                                  0x00000001L
3033 #define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK                                                                    0x00000002L
3034 #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK                                                                 0x00000004L
3035 #define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK                                                                  0x00000008L
3036 #define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK                                                                   0x00000010L
3037 #define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK                                                                    0x00000020L
3038 #define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK                                                                   0x00000040L
3039 #define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK                                                                   0x00000200L
3040 #define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK                                                                 0x00000400L
3041 #define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK                                                                  0x00002000L
3042 #define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK                                                                 0x00004000L
3043 #define SDMA1_STATUS1_REG__EX_START_MASK                                                                      0x00008000L
3044 #define SDMA1_STATUS1_REG__CE_RD_STALL_MASK                                                                   0x00020000L
3045 #define SDMA1_STATUS1_REG__CE_WR_STALL_MASK                                                                   0x00040000L
3046 //SDMA1_RD_BURST_CNTL
3047 #define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT                                                                  0x0
3048 #define SDMA1_RD_BURST_CNTL__RD_BURST_MASK                                                                    0x00000003L
3049 //SDMA1_HBM_PAGE_CONFIG
3050 #define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT                                                      0x0
3051 #define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK                                                        0x00000001L
3052 //SDMA1_UCODE_CHECKSUM
3053 #define SDMA1_UCODE_CHECKSUM__DATA__SHIFT                                                                     0x0
3054 #define SDMA1_UCODE_CHECKSUM__DATA_MASK                                                                       0xFFFFFFFFL
3055 //SDMA1_F32_CNTL
3056 #define SDMA1_F32_CNTL__HALT__SHIFT                                                                           0x0
3057 #define SDMA1_F32_CNTL__STEP__SHIFT                                                                           0x1
3058 #define SDMA1_F32_CNTL__CHECKSUM_CLR__SHIFT                                                                   0x8
3059 #define SDMA1_F32_CNTL__RESET__SHIFT                                                                          0x9
3060 #define SDMA1_F32_CNTL__HALT_MASK                                                                             0x00000001L
3061 #define SDMA1_F32_CNTL__STEP_MASK                                                                             0x00000002L
3062 #define SDMA1_F32_CNTL__CHECKSUM_CLR_MASK                                                                     0x00000100L
3063 #define SDMA1_F32_CNTL__RESET_MASK                                                                            0x00000200L
3064 //SDMA1_FREEZE
3065 #define SDMA1_FREEZE__PREEMPT__SHIFT                                                                          0x0
3066 #define SDMA1_FREEZE__FORCE_PREEMPT__SHIFT                                                                    0x1
3067 #define SDMA1_FREEZE__FREEZE__SHIFT                                                                           0x4
3068 #define SDMA1_FREEZE__FROZEN__SHIFT                                                                           0x5
3069 #define SDMA1_FREEZE__F32_FREEZE__SHIFT                                                                       0x6
3070 #define SDMA1_FREEZE__PREEMPT_MASK                                                                            0x00000001L
3071 #define SDMA1_FREEZE__FORCE_PREEMPT_MASK                                                                      0x00000002L
3072 #define SDMA1_FREEZE__FREEZE_MASK                                                                             0x00000010L
3073 #define SDMA1_FREEZE__FROZEN_MASK                                                                             0x00000020L
3074 #define SDMA1_FREEZE__F32_FREEZE_MASK                                                                         0x00000040L
3075 //SDMA1_PHASE0_QUANTUM
3076 #define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT                                                                     0x0
3077 #define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT                                                                    0x8
3078 #define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT                                                                   0x1e
3079 #define SDMA1_PHASE0_QUANTUM__UNIT_MASK                                                                       0x0000000FL
3080 #define SDMA1_PHASE0_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
3081 #define SDMA1_PHASE0_QUANTUM__PREFER_MASK                                                                     0x40000000L
3082 //SDMA1_PHASE1_QUANTUM
3083 #define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT                                                                     0x0
3084 #define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT                                                                    0x8
3085 #define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT                                                                   0x1e
3086 #define SDMA1_PHASE1_QUANTUM__UNIT_MASK                                                                       0x0000000FL
3087 #define SDMA1_PHASE1_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
3088 #define SDMA1_PHASE1_QUANTUM__PREFER_MASK                                                                     0x40000000L
3089 //SDMA1_EDC_CONFIG
3090 #define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT                                                                      0x1
3091 #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT                                                               0x2
3092 #define SDMA1_EDC_CONFIG__DIS_EDC_MASK                                                                        0x00000002L
3093 #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK                                                                 0x00000004L
3094 //SDMA1_BA_THRESHOLD
3095 #define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT                                                                 0x0
3096 #define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT                                                                0x10
3097 #define SDMA1_BA_THRESHOLD__READ_THRES_MASK                                                                   0x000003FFL
3098 #define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK                                                                  0x03FF0000L
3099 //SDMA1_ID
3100 #define SDMA1_ID__DEVICE_ID__SHIFT                                                                            0x0
3101 #define SDMA1_ID__DEVICE_ID_MASK                                                                              0x000000FFL
3102 //SDMA1_VERSION
3103 #define SDMA1_VERSION__MINVER__SHIFT                                                                          0x0
3104 #define SDMA1_VERSION__MAJVER__SHIFT                                                                          0x8
3105 #define SDMA1_VERSION__REV__SHIFT                                                                             0x10
3106 #define SDMA1_VERSION__MINVER_MASK                                                                            0x0000007FL
3107 #define SDMA1_VERSION__MAJVER_MASK                                                                            0x00007F00L
3108 #define SDMA1_VERSION__REV_MASK                                                                               0x003F0000L
3109 //SDMA1_EDC_COUNTER
3110 #define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT                                                          0x0
3111 #define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT                                                          0x1
3112 #define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT                                                         0x2
3113 #define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT                                                         0x3
3114 #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT                                                      0x4
3115 #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT                                                   0x5
3116 #define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT                                                      0x6
3117 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT                                                    0x7
3118 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT                                                    0x8
3119 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT                                                    0x9
3120 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT                                                    0xa
3121 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT                                                    0xb
3122 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT                                                    0xc
3123 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT                                                    0xd
3124 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT                                                    0xe
3125 #define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT                                                      0xf
3126 #define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT                                                    0x10
3127 #define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK                                                            0x00000001L
3128 #define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK                                                            0x00000002L
3129 #define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK                                                           0x00000004L
3130 #define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK                                                           0x00000008L
3131 #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK                                                        0x00000010L
3132 #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK                                                     0x00000020L
3133 #define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK                                                        0x00000040L
3134 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK                                                      0x00000080L
3135 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK                                                      0x00000100L
3136 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK                                                      0x00000200L
3137 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK                                                      0x00000400L
3138 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK                                                      0x00000800L
3139 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK                                                      0x00001000L
3140 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK                                                      0x00002000L
3141 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK                                                      0x00004000L
3142 #define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK                                                        0x00008000L
3143 #define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK                                                      0x00010000L
3144 //SDMA1_EDC_COUNTER_CLEAR
3145 #define SDMA1_EDC_COUNTER_CLEAR__DUMMY__SHIFT                                                                 0x0
3146 #define SDMA1_EDC_COUNTER_CLEAR__DUMMY_MASK                                                                   0x00000001L
3147 //SDMA1_STATUS2_REG
3148 #define SDMA1_STATUS2_REG__ID__SHIFT                                                                          0x0
3149 #define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT                                                               0x2
3150 #define SDMA1_STATUS2_REG__CMD_OP__SHIFT                                                                      0x10
3151 #define SDMA1_STATUS2_REG__ID_MASK                                                                            0x00000003L
3152 #define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK                                                                 0x00000FFCL
3153 #define SDMA1_STATUS2_REG__CMD_OP_MASK                                                                        0xFFFF0000L
3154 //SDMA1_ATOMIC_CNTL
3155 #define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT                                                                  0x0
3156 #define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT                                                       0x1f
3157 #define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK                                                                    0x7FFFFFFFL
3158 #define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK                                                         0x80000000L
3159 //SDMA1_ATOMIC_PREOP_LO
3160 #define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT                                                                    0x0
3161 #define SDMA1_ATOMIC_PREOP_LO__DATA_MASK                                                                      0xFFFFFFFFL
3162 //SDMA1_ATOMIC_PREOP_HI
3163 #define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT                                                                    0x0
3164 #define SDMA1_ATOMIC_PREOP_HI__DATA_MASK                                                                      0xFFFFFFFFL
3165 //SDMA1_UTCL1_CNTL
3166 #define SDMA1_UTCL1_CNTL__REDO_ENABLE__SHIFT                                                                  0x0
3167 #define SDMA1_UTCL1_CNTL__REDO_DELAY__SHIFT                                                                   0x1
3168 #define SDMA1_UTCL1_CNTL__REDO_WATERMK__SHIFT                                                                 0x6
3169 #define SDMA1_UTCL1_CNTL__RESP_MODE__SHIFT                                                                    0x9
3170 #define SDMA1_UTCL1_CNTL__FORCE_INVALIDATION__SHIFT                                                           0xe
3171 #define SDMA1_UTCL1_CNTL__FORCE_INVREQ_HEAVY__SHIFT                                                           0xf
3172 #define SDMA1_UTCL1_CNTL__INVACK_DELAY__SHIFT                                                                 0x10
3173 #define SDMA1_UTCL1_CNTL__REQL2_CREDIT__SHIFT                                                                 0x18
3174 #define SDMA1_UTCL1_CNTL__VADDR_WATERMK__SHIFT                                                                0x1d
3175 #define SDMA1_UTCL1_CNTL__REDO_ENABLE_MASK                                                                    0x00000001L
3176 #define SDMA1_UTCL1_CNTL__REDO_DELAY_MASK                                                                     0x0000003EL
3177 #define SDMA1_UTCL1_CNTL__REDO_WATERMK_MASK                                                                   0x000001C0L
3178 #define SDMA1_UTCL1_CNTL__RESP_MODE_MASK                                                                      0x00000E00L
3179 #define SDMA1_UTCL1_CNTL__FORCE_INVALIDATION_MASK                                                             0x00004000L
3180 #define SDMA1_UTCL1_CNTL__FORCE_INVREQ_HEAVY_MASK                                                             0x00008000L
3181 #define SDMA1_UTCL1_CNTL__INVACK_DELAY_MASK                                                                   0x00FF0000L
3182 #define SDMA1_UTCL1_CNTL__REQL2_CREDIT_MASK                                                                   0x1F000000L
3183 #define SDMA1_UTCL1_CNTL__VADDR_WATERMK_MASK                                                                  0xE0000000L
3184 //SDMA1_UTCL1_WATERMK
3185 #define SDMA1_UTCL1_WATERMK__REQMC_WATERMK__SHIFT                                                             0x0
3186 #define SDMA1_UTCL1_WATERMK__REQPG_WATERMK__SHIFT                                                             0xa
3187 #define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT                                                            0x12
3188 #define SDMA1_UTCL1_WATERMK__XNACK_WATERMK__SHIFT                                                             0x1a
3189 #define SDMA1_UTCL1_WATERMK__REQMC_WATERMK_MASK                                                               0x000003FFL
3190 #define SDMA1_UTCL1_WATERMK__REQPG_WATERMK_MASK                                                               0x0003FC00L
3191 #define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK_MASK                                                              0x03FC0000L
3192 #define SDMA1_UTCL1_WATERMK__XNACK_WATERMK_MASK                                                               0xFC000000L
3193 //SDMA1_UTCL1_RD_STATUS
3194 #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT                                                0x0
3195 #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT                                                 0x1
3196 #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT                                                     0x2
3197 #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT                                                      0x3
3198 #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT                                                      0x4
3199 #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT                                                       0x5
3200 #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT                                                   0x6
3201 #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT                                                    0x7
3202 #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT                                                    0x8
3203 #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT                                                     0x9
3204 #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT                                                 0xa
3205 #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT                                                  0xb
3206 #define SDMA1_UTCL1_RD_STATUS__REDO_ARR_EMPTY__SHIFT                                                          0xc
3207 #define SDMA1_UTCL1_RD_STATUS__REDO_ARR_FULL__SHIFT                                                           0xd
3208 #define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT                                                              0xe
3209 #define SDMA1_UTCL1_RD_STATUS__PAGE_NULL__SHIFT                                                               0xf
3210 #define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT                                                              0x10
3211 #define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT                                                          0x11
3212 #define SDMA1_UTCL1_RD_STATUS__MERGE_STATE__SHIFT                                                             0x15
3213 #define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT                                                             0x18
3214 #define SDMA1_UTCL1_RD_STATUS__RD_XNACK_TIMEOUT__SHIFT                                                        0x19
3215 #define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_SW__SHIFT                                                            0x1a
3216 #define SDMA1_UTCL1_RD_STATUS__HIT_CACHE__SHIFT                                                               0x1b
3217 #define SDMA1_UTCL1_RD_STATUS__RD_DCC_ENABLE__SHIFT                                                           0x1c
3218 #define SDMA1_UTCL1_RD_STATUS__NACK_TIMEOUT_SW__SHIFT                                                         0x1d
3219 #define SDMA1_UTCL1_RD_STATUS__DCC_PAGE_FAULT__SHIFT                                                          0x1e
3220 #define SDMA1_UTCL1_RD_STATUS__DCC_PAGE_NULL__SHIFT                                                           0x1f
3221 #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK                                                  0x00000001L
3222 #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK                                                   0x00000002L
3223 #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK                                                       0x00000004L
3224 #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK                                                        0x00000008L
3225 #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK                                                        0x00000010L
3226 #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK                                                         0x00000020L
3227 #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK                                                     0x00000040L
3228 #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK                                                      0x00000080L
3229 #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK                                                      0x00000100L
3230 #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK                                                       0x00000200L
3231 #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK                                                   0x00000400L
3232 #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK                                                    0x00000800L
3233 #define SDMA1_UTCL1_RD_STATUS__REDO_ARR_EMPTY_MASK                                                            0x00001000L
3234 #define SDMA1_UTCL1_RD_STATUS__REDO_ARR_FULL_MASK                                                             0x00002000L
3235 #define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT_MASK                                                                0x00004000L
3236 #define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_MASK                                                                 0x00008000L
3237 #define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE_MASK                                                                0x00010000L
3238 #define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK                                                            0x001E0000L
3239 #define SDMA1_UTCL1_RD_STATUS__MERGE_STATE_MASK                                                               0x00E00000L
3240 #define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK                                                               0x01000000L
3241 #define SDMA1_UTCL1_RD_STATUS__RD_XNACK_TIMEOUT_MASK                                                          0x02000000L
3242 #define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_SW_MASK                                                              0x04000000L
3243 #define SDMA1_UTCL1_RD_STATUS__HIT_CACHE_MASK                                                                 0x08000000L
3244 #define SDMA1_UTCL1_RD_STATUS__RD_DCC_ENABLE_MASK                                                             0x10000000L
3245 #define SDMA1_UTCL1_RD_STATUS__NACK_TIMEOUT_SW_MASK                                                           0x20000000L
3246 #define SDMA1_UTCL1_RD_STATUS__DCC_PAGE_FAULT_MASK                                                            0x40000000L
3247 #define SDMA1_UTCL1_RD_STATUS__DCC_PAGE_NULL_MASK                                                             0x80000000L
3248 //SDMA1_UTCL1_WR_STATUS
3249 #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT                                                0x0
3250 #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT                                                 0x1
3251 #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT                                                     0x2
3252 #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT                                                      0x3
3253 #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT                                                      0x4
3254 #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT                                                       0x5
3255 #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT                                                   0x6
3256 #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT                                                    0x7
3257 #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT                                                    0x8
3258 #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT                                                     0x9
3259 #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT                                                 0xa
3260 #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT                                                  0xb
3261 #define SDMA1_UTCL1_WR_STATUS__REDO_ARR_EMPTY__SHIFT                                                          0xc
3262 #define SDMA1_UTCL1_WR_STATUS__REDO_ARR_FULL__SHIFT                                                           0xd
3263 #define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT                                                              0xe
3264 #define SDMA1_UTCL1_WR_STATUS__PAGE_NULL__SHIFT                                                               0xf
3265 #define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT                                                              0x10
3266 #define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT                                                          0x11
3267 #define SDMA1_UTCL1_WR_STATUS__MERGE_STATE__SHIFT                                                             0x15
3268 #define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT                                                              0x18
3269 #define SDMA1_UTCL1_WR_STATUS__WR_XNACK_TIMEOUT__SHIFT                                                        0x19
3270 #define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_SW__SHIFT                                                            0x1a
3271 #define SDMA1_UTCL1_WR_STATUS__ATOMIC_OP__SHIFT                                                               0x1b
3272 #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT                                                    0x1c
3273 #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT                                                     0x1d
3274 #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT                                                   0x1e
3275 #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT                                                    0x1f
3276 #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK                                                  0x00000001L
3277 #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK                                                   0x00000002L
3278 #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK                                                       0x00000004L
3279 #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK                                                        0x00000008L
3280 #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK                                                        0x00000010L
3281 #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK                                                         0x00000020L
3282 #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK                                                     0x00000040L
3283 #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK                                                      0x00000080L
3284 #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK                                                      0x00000100L
3285 #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK                                                       0x00000200L
3286 #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK                                                   0x00000400L
3287 #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK                                                    0x00000800L
3288 #define SDMA1_UTCL1_WR_STATUS__REDO_ARR_EMPTY_MASK                                                            0x00001000L
3289 #define SDMA1_UTCL1_WR_STATUS__REDO_ARR_FULL_MASK                                                             0x00002000L
3290 #define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT_MASK                                                                0x00004000L
3291 #define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_MASK                                                                 0x00008000L
3292 #define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE_MASK                                                                0x00010000L
3293 #define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK                                                            0x001E0000L
3294 #define SDMA1_UTCL1_WR_STATUS__MERGE_STATE_MASK                                                               0x00E00000L
3295 #define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR_MASK                                                                0x01000000L
3296 #define SDMA1_UTCL1_WR_STATUS__WR_XNACK_TIMEOUT_MASK                                                          0x02000000L
3297 #define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_SW_MASK                                                              0x04000000L
3298 #define SDMA1_UTCL1_WR_STATUS__ATOMIC_OP_MASK                                                                 0x08000000L
3299 #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK                                                      0x10000000L
3300 #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK                                                       0x20000000L
3301 #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK                                                     0x40000000L
3302 #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK                                                      0x80000000L
3303 //SDMA1_UTCL1_INV0
3304 #define SDMA1_UTCL1_INV0__CPF_INVREQ_EN__SHIFT                                                                0x0
3305 #define SDMA1_UTCL1_INV0__GPUVM_INVREQ_EN__SHIFT                                                              0x1
3306 #define SDMA1_UTCL1_INV0__CPF_GPA_INVREQ__SHIFT                                                               0x2
3307 #define SDMA1_UTCL1_INV0__GPUVM_INVREQ_LOW__SHIFT                                                             0x3
3308 #define SDMA1_UTCL1_INV0__GPUVM_INVREQ_HIGH__SHIFT                                                            0x4
3309 #define SDMA1_UTCL1_INV0__INVREQ_SIZE__SHIFT                                                                  0x5
3310 #define SDMA1_UTCL1_INV0__INVREQ_IDLE__SHIFT                                                                  0xb
3311 #define SDMA1_UTCL1_INV0__VMINV_PEND_CNT__SHIFT                                                               0xc
3312 #define SDMA1_UTCL1_INV0__GPUVM_LO_INV_VMID__SHIFT                                                            0x10
3313 #define SDMA1_UTCL1_INV0__GPUVM_HI_INV_VMID__SHIFT                                                            0x14
3314 #define SDMA1_UTCL1_INV0__GPUVM_INV_MODE__SHIFT                                                               0x18
3315 #define SDMA1_UTCL1_INV0__INVREQ_IS_HEAVY__SHIFT                                                              0x1a
3316 #define SDMA1_UTCL1_INV0__INVREQ_FROM_CPF__SHIFT                                                              0x1b
3317 #define SDMA1_UTCL1_INV0__GPUVM_INVREQ_TAG__SHIFT                                                             0x1c
3318 #define SDMA1_UTCL1_INV0__CPF_INVREQ_EN_MASK                                                                  0x00000001L
3319 #define SDMA1_UTCL1_INV0__GPUVM_INVREQ_EN_MASK                                                                0x00000002L
3320 #define SDMA1_UTCL1_INV0__CPF_GPA_INVREQ_MASK                                                                 0x00000004L
3321 #define SDMA1_UTCL1_INV0__GPUVM_INVREQ_LOW_MASK                                                               0x00000008L
3322 #define SDMA1_UTCL1_INV0__GPUVM_INVREQ_HIGH_MASK                                                              0x00000010L
3323 #define SDMA1_UTCL1_INV0__INVREQ_SIZE_MASK                                                                    0x000007E0L
3324 #define SDMA1_UTCL1_INV0__INVREQ_IDLE_MASK                                                                    0x00000800L
3325 #define SDMA1_UTCL1_INV0__VMINV_PEND_CNT_MASK                                                                 0x0000F000L
3326 #define SDMA1_UTCL1_INV0__GPUVM_LO_INV_VMID_MASK                                                              0x000F0000L
3327 #define SDMA1_UTCL1_INV0__GPUVM_HI_INV_VMID_MASK                                                              0x00F00000L
3328 #define SDMA1_UTCL1_INV0__GPUVM_INV_MODE_MASK                                                                 0x03000000L
3329 #define SDMA1_UTCL1_INV0__INVREQ_IS_HEAVY_MASK                                                                0x04000000L
3330 #define SDMA1_UTCL1_INV0__INVREQ_FROM_CPF_MASK                                                                0x08000000L
3331 #define SDMA1_UTCL1_INV0__GPUVM_INVREQ_TAG_MASK                                                               0xF0000000L
3332 //SDMA1_UTCL1_INV1
3333 #define SDMA1_UTCL1_INV1__INV_ADDR_LO__SHIFT                                                                  0x0
3334 #define SDMA1_UTCL1_INV1__INV_ADDR_LO_MASK                                                                    0xFFFFFFFFL
3335 //SDMA1_UTCL1_INV2
3336 #define SDMA1_UTCL1_INV2__INV_VMID_VEC__SHIFT                                                                 0x0
3337 #define SDMA1_UTCL1_INV2__RESERVED__SHIFT                                                                     0x10
3338 #define SDMA1_UTCL1_INV2__INV_VMID_VEC_MASK                                                                   0x0000FFFFL
3339 #define SDMA1_UTCL1_INV2__RESERVED_MASK                                                                       0xFFFF0000L
3340 //SDMA1_UTCL1_RD_XNACK0
3341 #define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT                                                           0x0
3342 #define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK                                                             0xFFFFFFFFL
3343 //SDMA1_UTCL1_RD_XNACK1
3344 #define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT                                                           0x0
3345 #define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT                                                              0x4
3346 #define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT                                                            0x8
3347 #define SDMA1_UTCL1_RD_XNACK1__IS_XNACK__SHIFT                                                                0x1a
3348 #define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK                                                             0x0000000FL
3349 #define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID_MASK                                                                0x000000F0L
3350 #define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK                                                              0x03FFFF00L
3351 #define SDMA1_UTCL1_RD_XNACK1__IS_XNACK_MASK                                                                  0x0C000000L
3352 //SDMA1_UTCL1_WR_XNACK0
3353 #define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT                                                           0x0
3354 #define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK                                                             0xFFFFFFFFL
3355 //SDMA1_UTCL1_WR_XNACK1
3356 #define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT                                                           0x0
3357 #define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT                                                              0x4
3358 #define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT                                                            0x8
3359 #define SDMA1_UTCL1_WR_XNACK1__IS_XNACK__SHIFT                                                                0x1a
3360 #define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK                                                             0x0000000FL
3361 #define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID_MASK                                                                0x000000F0L
3362 #define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK                                                              0x03FFFF00L
3363 #define SDMA1_UTCL1_WR_XNACK1__IS_XNACK_MASK                                                                  0x0C000000L
3364 //SDMA1_UTCL1_TIMEOUT
3365 #define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT                                                            0x0
3366 #define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT                                                            0x10
3367 #define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK                                                              0x0000FFFFL
3368 #define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK                                                              0xFFFF0000L
3369 //SDMA1_UTCL1_PAGE
3370 #define SDMA1_UTCL1_PAGE__VM_HOLE__SHIFT                                                                      0x0
3371 #define SDMA1_UTCL1_PAGE__REQ_TYPE__SHIFT                                                                     0x1
3372 #define SDMA1_UTCL1_PAGE__USE_MTYPE__SHIFT                                                                    0x6
3373 #define SDMA1_UTCL1_PAGE__USE_PT_SNOOP__SHIFT                                                                 0xa
3374 #define SDMA1_UTCL1_PAGE__USE_IO__SHIFT                                                                       0xb
3375 #define SDMA1_UTCL1_PAGE__RD_L2_POLICY__SHIFT                                                                 0xc
3376 #define SDMA1_UTCL1_PAGE__WR_L2_POLICY__SHIFT                                                                 0xe
3377 #define SDMA1_UTCL1_PAGE__DMA_PAGE_SIZE__SHIFT                                                                0x10
3378 #define SDMA1_UTCL1_PAGE__USE_BC__SHIFT                                                                       0x16
3379 #define SDMA1_UTCL1_PAGE__ADDR_IS_PA__SHIFT                                                                   0x17
3380 #define SDMA1_UTCL1_PAGE__VM_HOLE_MASK                                                                        0x00000001L
3381 #define SDMA1_UTCL1_PAGE__REQ_TYPE_MASK                                                                       0x0000001EL
3382 #define SDMA1_UTCL1_PAGE__USE_MTYPE_MASK                                                                      0x000003C0L
3383 #define SDMA1_UTCL1_PAGE__USE_PT_SNOOP_MASK                                                                   0x00000400L
3384 #define SDMA1_UTCL1_PAGE__USE_IO_MASK                                                                         0x00000800L
3385 #define SDMA1_UTCL1_PAGE__RD_L2_POLICY_MASK                                                                   0x00003000L
3386 #define SDMA1_UTCL1_PAGE__WR_L2_POLICY_MASK                                                                   0x0000C000L
3387 #define SDMA1_UTCL1_PAGE__DMA_PAGE_SIZE_MASK                                                                  0x003F0000L
3388 #define SDMA1_UTCL1_PAGE__USE_BC_MASK                                                                         0x00400000L
3389 #define SDMA1_UTCL1_PAGE__ADDR_IS_PA_MASK                                                                     0x00800000L
3390 //SDMA1_POWER_CNTL_IDLE
3391 #define SDMA1_POWER_CNTL_IDLE__DELAY0__SHIFT                                                                  0x0
3392 #define SDMA1_POWER_CNTL_IDLE__DELAY1__SHIFT                                                                  0x10
3393 #define SDMA1_POWER_CNTL_IDLE__DELAY2__SHIFT                                                                  0x18
3394 #define SDMA1_POWER_CNTL_IDLE__DELAY0_MASK                                                                    0x0000FFFFL
3395 #define SDMA1_POWER_CNTL_IDLE__DELAY1_MASK                                                                    0x00FF0000L
3396 #define SDMA1_POWER_CNTL_IDLE__DELAY2_MASK                                                                    0xFF000000L
3397 //SDMA1_RELAX_ORDERING_LUT
3398 #define SDMA1_RELAX_ORDERING_LUT__RESERVED0__SHIFT                                                            0x0
3399 #define SDMA1_RELAX_ORDERING_LUT__COPY__SHIFT                                                                 0x1
3400 #define SDMA1_RELAX_ORDERING_LUT__WRITE__SHIFT                                                                0x2
3401 #define SDMA1_RELAX_ORDERING_LUT__RESERVED3__SHIFT                                                            0x3
3402 #define SDMA1_RELAX_ORDERING_LUT__RESERVED4__SHIFT                                                            0x4
3403 #define SDMA1_RELAX_ORDERING_LUT__FENCE__SHIFT                                                                0x5
3404 #define SDMA1_RELAX_ORDERING_LUT__RESERVED76__SHIFT                                                           0x6
3405 #define SDMA1_RELAX_ORDERING_LUT__POLL_MEM__SHIFT                                                             0x8
3406 #define SDMA1_RELAX_ORDERING_LUT__COND_EXE__SHIFT                                                             0x9
3407 #define SDMA1_RELAX_ORDERING_LUT__ATOMIC__SHIFT                                                               0xa
3408 #define SDMA1_RELAX_ORDERING_LUT__CONST_FILL__SHIFT                                                           0xb
3409 #define SDMA1_RELAX_ORDERING_LUT__PTEPDE__SHIFT                                                               0xc
3410 #define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT                                                            0xd
3411 #define SDMA1_RELAX_ORDERING_LUT__RESERVED__SHIFT                                                             0xe
3412 #define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT                                                         0x1b
3413 #define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT                                                             0x1c
3414 #define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT                                                            0x1d
3415 #define SDMA1_RELAX_ORDERING_LUT__IB_FETCH__SHIFT                                                             0x1e
3416 #define SDMA1_RELAX_ORDERING_LUT__RB_FETCH__SHIFT                                                             0x1f
3417 #define SDMA1_RELAX_ORDERING_LUT__RESERVED0_MASK                                                              0x00000001L
3418 #define SDMA1_RELAX_ORDERING_LUT__COPY_MASK                                                                   0x00000002L
3419 #define SDMA1_RELAX_ORDERING_LUT__WRITE_MASK                                                                  0x00000004L
3420 #define SDMA1_RELAX_ORDERING_LUT__RESERVED3_MASK                                                              0x00000008L
3421 #define SDMA1_RELAX_ORDERING_LUT__RESERVED4_MASK                                                              0x00000010L
3422 #define SDMA1_RELAX_ORDERING_LUT__FENCE_MASK                                                                  0x00000020L
3423 #define SDMA1_RELAX_ORDERING_LUT__RESERVED76_MASK                                                             0x000000C0L
3424 #define SDMA1_RELAX_ORDERING_LUT__POLL_MEM_MASK                                                               0x00000100L
3425 #define SDMA1_RELAX_ORDERING_LUT__COND_EXE_MASK                                                               0x00000200L
3426 #define SDMA1_RELAX_ORDERING_LUT__ATOMIC_MASK                                                                 0x00000400L
3427 #define SDMA1_RELAX_ORDERING_LUT__CONST_FILL_MASK                                                             0x00000800L
3428 #define SDMA1_RELAX_ORDERING_LUT__PTEPDE_MASK                                                                 0x00001000L
3429 #define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP_MASK                                                              0x00002000L
3430 #define SDMA1_RELAX_ORDERING_LUT__RESERVED_MASK                                                               0x07FFC000L
3431 #define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK                                                           0x08000000L
3432 #define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB_MASK                                                               0x10000000L
3433 #define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL_MASK                                                              0x20000000L
3434 #define SDMA1_RELAX_ORDERING_LUT__IB_FETCH_MASK                                                               0x40000000L
3435 #define SDMA1_RELAX_ORDERING_LUT__RB_FETCH_MASK                                                               0x80000000L
3436 //SDMA1_CHICKEN_BITS_2
3437 #define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT                                                       0x0
3438 #define SDMA1_CHICKEN_BITS_2__CE_BACKWARDS_SIZE_SEL__SHIFT                                                    0x4
3439 #define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK                                                         0x0000000FL
3440 #define SDMA1_CHICKEN_BITS_2__CE_BACKWARDS_SIZE_SEL_MASK                                                      0x00000010L
3441 //SDMA1_STATUS3_REG
3442 #define SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT                                                               0x0
3443 #define SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT                                                                 0x10
3444 #define SDMA1_STATUS3_REG__EXCEPTION_IDLE__SHIFT                                                              0x14
3445 #define SDMA1_STATUS3_REG__AQL_PREV_CMD_IDLE__SHIFT                                                           0x15
3446 #define SDMA1_STATUS3_REG__TLBI_IDLE__SHIFT                                                                   0x16
3447 #define SDMA1_STATUS3_REG__GCR_IDLE__SHIFT                                                                    0x17
3448 #define SDMA1_STATUS3_REG__INVREQ_IDLE__SHIFT                                                                 0x18
3449 #define SDMA1_STATUS3_REG__QUEUE_ID_MATCH__SHIFT                                                              0x19
3450 #define SDMA1_STATUS3_REG__INT_QUEUE_ID__SHIFT                                                                0x1a
3451 #define SDMA1_STATUS3_REG__CMD_OP_STATUS_MASK                                                                 0x0000FFFFL
3452 #define SDMA1_STATUS3_REG__PREV_VM_CMD_MASK                                                                   0x000F0000L
3453 #define SDMA1_STATUS3_REG__EXCEPTION_IDLE_MASK                                                                0x00100000L
3454 #define SDMA1_STATUS3_REG__AQL_PREV_CMD_IDLE_MASK                                                             0x00200000L
3455 #define SDMA1_STATUS3_REG__TLBI_IDLE_MASK                                                                     0x00400000L
3456 #define SDMA1_STATUS3_REG__GCR_IDLE_MASK                                                                      0x00800000L
3457 #define SDMA1_STATUS3_REG__INVREQ_IDLE_MASK                                                                   0x01000000L
3458 #define SDMA1_STATUS3_REG__QUEUE_ID_MATCH_MASK                                                                0x02000000L
3459 #define SDMA1_STATUS3_REG__INT_QUEUE_ID_MASK                                                                  0x3C000000L
3460 //SDMA1_PHYSICAL_ADDR_LO
3461 #define SDMA1_PHYSICAL_ADDR_LO__D_VALID__SHIFT                                                                0x0
3462 #define SDMA1_PHYSICAL_ADDR_LO__DIRTY__SHIFT                                                                  0x1
3463 #define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT                                                              0x2
3464 #define SDMA1_PHYSICAL_ADDR_LO__ADDR__SHIFT                                                                   0xc
3465 #define SDMA1_PHYSICAL_ADDR_LO__D_VALID_MASK                                                                  0x00000001L
3466 #define SDMA1_PHYSICAL_ADDR_LO__DIRTY_MASK                                                                    0x00000002L
3467 #define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID_MASK                                                                0x00000004L
3468 #define SDMA1_PHYSICAL_ADDR_LO__ADDR_MASK                                                                     0xFFFFF000L
3469 //SDMA1_PHYSICAL_ADDR_HI
3470 #define SDMA1_PHYSICAL_ADDR_HI__ADDR__SHIFT                                                                   0x0
3471 #define SDMA1_PHYSICAL_ADDR_HI__ADDR_MASK                                                                     0x0000FFFFL
3472 //SDMA1_PHASE2_QUANTUM
3473 #define SDMA1_PHASE2_QUANTUM__UNIT__SHIFT                                                                     0x0
3474 #define SDMA1_PHASE2_QUANTUM__VALUE__SHIFT                                                                    0x8
3475 #define SDMA1_PHASE2_QUANTUM__PREFER__SHIFT                                                                   0x1e
3476 #define SDMA1_PHASE2_QUANTUM__UNIT_MASK                                                                       0x0000000FL
3477 #define SDMA1_PHASE2_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
3478 #define SDMA1_PHASE2_QUANTUM__PREFER_MASK                                                                     0x40000000L
3479 //SDMA1_F32_COUNTER
3480 #define SDMA1_F32_COUNTER__VALUE__SHIFT                                                                       0x0
3481 #define SDMA1_F32_COUNTER__VALUE_MASK                                                                         0xFFFFFFFFL
3482 //SDMA1_PERFMON_CNTL
3483 #define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT                                                               0x0
3484 #define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT                                                                0x1
3485 #define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT                                                                  0x2
3486 #define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT                                                               0xa
3487 #define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT                                                                0xb
3488 #define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT                                                                  0xc
3489 #define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK                                                                 0x00000001L
3490 #define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK                                                                  0x00000002L
3491 #define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK                                                                    0x000003FCL
3492 #define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK                                                                 0x00000400L
3493 #define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK                                                                  0x00000800L
3494 #define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK                                                                    0x000FF000L
3495 //SDMA1_PERFCOUNTER0_RESULT
3496 #define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT                                                          0x0
3497 #define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK                                                            0xFFFFFFFFL
3498 //SDMA1_PERFCOUNTER1_RESULT
3499 #define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT                                                          0x0
3500 #define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK                                                            0xFFFFFFFFL
3501 //SDMA1_PERFCOUNTER_TAG_DELAY_RANGE
3502 #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT                                                   0x0
3503 #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT                                                  0xe
3504 #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT                                                   0x1c
3505 #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK                                                     0x00003FFFL
3506 #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK                                                    0x0FFFC000L
3507 #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK                                                     0x10000000L
3508 //SDMA1_CRD_CNTL
3509 #define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT                                                                0x7
3510 #define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT                                                                0xd
3511 #define SDMA1_CRD_CNTL__CH_WRREQ_CREDIT__SHIFT                                                                0x13
3512 #define SDMA1_CRD_CNTL__CH_RDREQ_CREDIT__SHIFT                                                                0x19
3513 #define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT_MASK                                                                  0x00001F80L
3514 #define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT_MASK                                                                  0x0007E000L
3515 #define SDMA1_CRD_CNTL__CH_WRREQ_CREDIT_MASK                                                                  0x01F80000L
3516 #define SDMA1_CRD_CNTL__CH_RDREQ_CREDIT_MASK                                                                  0x7E000000L
3517 //SDMA1_GPU_IOV_VIOLATION_LOG
3518 //SDMA1_AQL_STATUS
3519 #define SDMA1_AQL_STATUS__COMPLETE_SIGNAL_EMPTY__SHIFT                                                        0x0
3520 #define SDMA1_AQL_STATUS__INVALID_CMD_EMPTY__SHIFT                                                            0x1
3521 #define SDMA1_AQL_STATUS__COMPLETE_SIGNAL_EMPTY_MASK                                                          0x00000001L
3522 #define SDMA1_AQL_STATUS__INVALID_CMD_EMPTY_MASK                                                              0x00000002L
3523 //SDMA1_EA_DBIT_ADDR_DATA
3524 #define SDMA1_EA_DBIT_ADDR_DATA__VALUE__SHIFT                                                                 0x0
3525 #define SDMA1_EA_DBIT_ADDR_DATA__VALUE_MASK                                                                   0xFFFFFFFFL
3526 //SDMA1_EA_DBIT_ADDR_INDEX
3527 #define SDMA1_EA_DBIT_ADDR_INDEX__VALUE__SHIFT                                                                0x0
3528 #define SDMA1_EA_DBIT_ADDR_INDEX__VALUE_MASK                                                                  0x00000007L
3529 //SDMA1_TLBI_GCR_CNTL
3530 #define SDMA1_TLBI_GCR_CNTL__TLBI_CMD_DW__SHIFT                                                               0x0
3531 #define SDMA1_TLBI_GCR_CNTL__GCR_CMD_DW__SHIFT                                                                0x4
3532 #define SDMA1_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE__SHIFT                                                           0x8
3533 #define SDMA1_TLBI_GCR_CNTL__TLBI_CREDIT__SHIFT                                                               0x10
3534 #define SDMA1_TLBI_GCR_CNTL__GCR_CREDIT__SHIFT                                                                0x18
3535 #define SDMA1_TLBI_GCR_CNTL__TLBI_CMD_DW_MASK                                                                 0x0000000FL
3536 #define SDMA1_TLBI_GCR_CNTL__GCR_CMD_DW_MASK                                                                  0x000000F0L
3537 #define SDMA1_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE_MASK                                                             0x00000F00L
3538 #define SDMA1_TLBI_GCR_CNTL__TLBI_CREDIT_MASK                                                                 0x00FF0000L
3539 #define SDMA1_TLBI_GCR_CNTL__GCR_CREDIT_MASK                                                                  0xFF000000L
3540 //SDMA1_TILING_CONFIG
3541 #define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                      0x4
3542 #define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                        0x00000070L
3543 //SDMA1_HASH
3544 #define SDMA1_HASH__CHANNEL_BITS__SHIFT                                                                       0x0
3545 #define SDMA1_HASH__BANK_BITS__SHIFT                                                                          0x4
3546 #define SDMA1_HASH__CHANNEL_XOR_COUNT__SHIFT                                                                  0x8
3547 #define SDMA1_HASH__BANK_XOR_COUNT__SHIFT                                                                     0xc
3548 #define SDMA1_HASH__CHANNEL_BITS_MASK                                                                         0x00000007L
3549 #define SDMA1_HASH__BANK_BITS_MASK                                                                            0x00000070L
3550 #define SDMA1_HASH__CHANNEL_XOR_COUNT_MASK                                                                    0x00000700L
3551 #define SDMA1_HASH__BANK_XOR_COUNT_MASK                                                                       0x00007000L
3552 //SDMA1_PERFCOUNTER0_SELECT
3553 #define SDMA1_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                            0x0
3554 #define SDMA1_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                           0xa
3555 #define SDMA1_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                           0x14
3556 #define SDMA1_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                          0x18
3557 #define SDMA1_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                           0x1c
3558 #define SDMA1_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                              0x000003FFL
3559 #define SDMA1_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
3560 #define SDMA1_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
3561 #define SDMA1_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                            0x0F000000L
3562 #define SDMA1_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                             0xF0000000L
3563 //SDMA1_PERFCOUNTER0_SELECT1
3564 #define SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                          0x0
3565 #define SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                          0xa
3566 #define SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                         0x18
3567 #define SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                         0x1c
3568 #define SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
3569 #define SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
3570 #define SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                           0x0F000000L
3571 #define SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                           0xF0000000L
3572 //SDMA1_PERFCOUNTER0_LO
3573 #define SDMA1_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
3574 #define SDMA1_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
3575 //SDMA1_PERFCOUNTER0_HI
3576 #define SDMA1_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
3577 #define SDMA1_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
3578 //SDMA1_PERFCOUNTER1_SELECT
3579 #define SDMA1_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                            0x0
3580 #define SDMA1_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                           0xa
3581 #define SDMA1_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                           0x14
3582 #define SDMA1_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                          0x18
3583 #define SDMA1_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                           0x1c
3584 #define SDMA1_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                              0x000003FFL
3585 #define SDMA1_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
3586 #define SDMA1_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
3587 #define SDMA1_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                            0x0F000000L
3588 #define SDMA1_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                             0xF0000000L
3589 //SDMA1_PERFCOUNTER1_SELECT1
3590 #define SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                          0x0
3591 #define SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                          0xa
3592 #define SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                         0x18
3593 #define SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                         0x1c
3594 #define SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
3595 #define SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
3596 #define SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                           0x0F000000L
3597 #define SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                           0xF0000000L
3598 //SDMA1_PERFCOUNTER1_LO
3599 #define SDMA1_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
3600 #define SDMA1_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
3601 //SDMA1_PERFCOUNTER1_HI
3602 #define SDMA1_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
3603 #define SDMA1_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
3604 //SDMA1_INT_STATUS
3605 #define SDMA1_INT_STATUS__DATA__SHIFT                                                                         0x0
3606 #define SDMA1_INT_STATUS__DATA_MASK                                                                           0xFFFFFFFFL
3607 //SDMA1_GPU_IOV_VIOLATION_LOG2
3608 #define SDMA1_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT                                                     0x0
3609 #define SDMA1_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK                                                       0x000003FFL
3610 //SDMA1_HOLE_ADDR_LO
3611 #define SDMA1_HOLE_ADDR_LO__VALUE__SHIFT                                                                      0x0
3612 #define SDMA1_HOLE_ADDR_LO__VALUE_MASK                                                                        0xFFFFFFFFL
3613 //SDMA1_HOLE_ADDR_HI
3614 #define SDMA1_HOLE_ADDR_HI__VALUE__SHIFT                                                                      0x0
3615 #define SDMA1_HOLE_ADDR_HI__VALUE_MASK                                                                        0xFFFFFFFFL
3616 //SDMA1_GFX_RB_CNTL
3617 #define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT                                                                   0x0
3618 #define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT                                                                     0x1
3619 #define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                              0x9
3620 #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                       0xc
3621 #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                  0xd
3622 #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                        0x10
3623 #define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT                                                                     0x17
3624 #define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT                                                                     0x18
3625 #define SDMA1_GFX_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                                0x1f
3626 #define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK                                                                     0x00000001L
3627 #define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK                                                                       0x0000003EL
3628 #define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK                                                                0x00000200L
3629 #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                         0x00001000L
3630 #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                    0x00002000L
3631 #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                          0x001F0000L
3632 #define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK                                                                       0x00800000L
3633 #define SDMA1_GFX_RB_CNTL__RB_VMID_MASK                                                                       0x0F000000L
3634 #define SDMA1_GFX_RB_CNTL__RPTR_WB_IDLE_MASK                                                                  0x80000000L
3635 //SDMA1_GFX_RB_BASE
3636 #define SDMA1_GFX_RB_BASE__ADDR__SHIFT                                                                        0x0
3637 #define SDMA1_GFX_RB_BASE__ADDR_MASK                                                                          0xFFFFFFFFL
3638 //SDMA1_GFX_RB_BASE_HI
3639 #define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT                                                                     0x0
3640 #define SDMA1_GFX_RB_BASE_HI__ADDR_MASK                                                                       0x00FFFFFFL
3641 //SDMA1_GFX_RB_RPTR
3642 #define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT                                                                      0x0
3643 #define SDMA1_GFX_RB_RPTR__OFFSET_MASK                                                                        0xFFFFFFFFL
3644 //SDMA1_GFX_RB_RPTR_HI
3645 #define SDMA1_GFX_RB_RPTR_HI__OFFSET__SHIFT                                                                   0x0
3646 #define SDMA1_GFX_RB_RPTR_HI__OFFSET_MASK                                                                     0xFFFFFFFFL
3647 //SDMA1_GFX_RB_WPTR
3648 #define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT                                                                      0x0
3649 #define SDMA1_GFX_RB_WPTR__OFFSET_MASK                                                                        0xFFFFFFFFL
3650 //SDMA1_GFX_RB_WPTR_HI
3651 #define SDMA1_GFX_RB_WPTR_HI__OFFSET__SHIFT                                                                   0x0
3652 #define SDMA1_GFX_RB_WPTR_HI__OFFSET_MASK                                                                     0xFFFFFFFFL
3653 //SDMA1_GFX_RB_WPTR_POLL_CNTL
3654 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                            0x0
3655 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                       0x1
3656 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                   0x2
3657 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                         0x4
3658 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                   0x10
3659 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                              0x00000001L
3660 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                         0x00000002L
3661 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                     0x00000004L
3662 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                           0x0000FFF0L
3663 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                     0xFFFF0000L
3664 //SDMA1_GFX_RB_RPTR_ADDR_HI
3665 #define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                                0x0
3666 #define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK                                                                  0xFFFFFFFFL
3667 //SDMA1_GFX_RB_RPTR_ADDR_LO
3668 #define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                                0x2
3669 #define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK                                                                  0xFFFFFFFCL
3670 //SDMA1_GFX_IB_CNTL
3671 #define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT                                                                   0x0
3672 #define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                              0x4
3673 #define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                            0x8
3674 #define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT                                                                    0x10
3675 #define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK                                                                     0x00000001L
3676 #define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK                                                                0x00000010L
3677 #define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                              0x00000100L
3678 #define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK                                                                      0x000F0000L
3679 //SDMA1_GFX_IB_RPTR
3680 #define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT                                                                      0x2
3681 #define SDMA1_GFX_IB_RPTR__OFFSET_MASK                                                                        0x003FFFFCL
3682 //SDMA1_GFX_IB_OFFSET
3683 #define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT                                                                    0x2
3684 #define SDMA1_GFX_IB_OFFSET__OFFSET_MASK                                                                      0x003FFFFCL
3685 //SDMA1_GFX_IB_BASE_LO
3686 #define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT                                                                     0x5
3687 #define SDMA1_GFX_IB_BASE_LO__ADDR_MASK                                                                       0xFFFFFFE0L
3688 //SDMA1_GFX_IB_BASE_HI
3689 #define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT                                                                     0x0
3690 #define SDMA1_GFX_IB_BASE_HI__ADDR_MASK                                                                       0xFFFFFFFFL
3691 //SDMA1_GFX_IB_SIZE
3692 #define SDMA1_GFX_IB_SIZE__SIZE__SHIFT                                                                        0x0
3693 #define SDMA1_GFX_IB_SIZE__SIZE_MASK                                                                          0x000FFFFFL
3694 //SDMA1_GFX_SKIP_CNTL
3695 #define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT                                                                0x0
3696 #define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK                                                                  0x000FFFFFL
3697 //SDMA1_GFX_CONTEXT_STATUS
3698 #define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT                                                             0x0
3699 #define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT                                                                 0x2
3700 #define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT                                                              0x3
3701 #define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT                                                            0x4
3702 #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                           0x7
3703 #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                          0x8
3704 #define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT                                                            0x9
3705 #define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                      0xa
3706 #define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK                                                               0x00000001L
3707 #define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK                                                                   0x00000004L
3708 #define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK                                                                0x00000008L
3709 #define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK                                                              0x00000070L
3710 #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                             0x00000080L
3711 #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK                                                            0x00000100L
3712 #define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK                                                              0x00000200L
3713 #define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                        0x00000400L
3714 //SDMA1_GFX_DOORBELL
3715 #define SDMA1_GFX_DOORBELL__ENABLE__SHIFT                                                                     0x1c
3716 #define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT                                                                   0x1e
3717 #define SDMA1_GFX_DOORBELL__ENABLE_MASK                                                                       0x10000000L
3718 #define SDMA1_GFX_DOORBELL__CAPTURED_MASK                                                                     0x40000000L
3719 //SDMA1_GFX_CONTEXT_CNTL
3720 #define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT                                                             0x10
3721 #define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK                                                               0x00010000L
3722 //SDMA1_GFX_STATUS
3723 #define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                       0x0
3724 #define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                          0x8
3725 #define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                         0x000000FFL
3726 #define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING_MASK                                                            0x00000100L
3727 //SDMA1_GFX_DOORBELL_LOG
3728 //SDMA1_GFX_WATERMARK
3729 #define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT                                                            0x0
3730 #define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT                                                            0x10
3731 #define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK                                                              0x00000FFFL
3732 #define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK                                                              0x03FF0000L
3733 //SDMA1_GFX_DOORBELL_OFFSET
3734 #define SDMA1_GFX_DOORBELL_OFFSET__OFFSET__SHIFT                                                              0x2
3735 #define SDMA1_GFX_DOORBELL_OFFSET__OFFSET_MASK                                                                0x0FFFFFFCL
3736 //SDMA1_GFX_CSA_ADDR_LO
3737 #define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT                                                                    0x2
3738 #define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK                                                                      0xFFFFFFFCL
3739 //SDMA1_GFX_CSA_ADDR_HI
3740 #define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT                                                                    0x0
3741 #define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK                                                                      0xFFFFFFFFL
3742 //SDMA1_GFX_IB_SUB_REMAIN
3743 #define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT                                                                  0x0
3744 #define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK                                                                    0x00003FFFL
3745 //SDMA1_GFX_PREEMPT
3746 #define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT                                                                  0x0
3747 #define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK                                                                    0x00000001L
3748 //SDMA1_GFX_DUMMY_REG
3749 #define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT                                                                     0x0
3750 #define SDMA1_GFX_DUMMY_REG__DUMMY_MASK                                                                       0xFFFFFFFFL
3751 //SDMA1_GFX_RB_WPTR_POLL_ADDR_HI
3752 #define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                           0x0
3753 #define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                             0xFFFFFFFFL
3754 //SDMA1_GFX_RB_WPTR_POLL_ADDR_LO
3755 #define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                           0x2
3756 #define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                             0xFFFFFFFCL
3757 //SDMA1_GFX_RB_AQL_CNTL
3758 #define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                              0x0
3759 #define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                         0x1
3760 #define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                             0x8
3761 #define SDMA1_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                   0x10
3762 #define SDMA1_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                             0x11
3763 #define SDMA1_GFX_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                          0x12
3764 #define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK                                                                0x00000001L
3765 #define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                           0x000000FEL
3766 #define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP_MASK                                                               0x0000FF00L
3767 #define SDMA1_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                     0x00010000L
3768 #define SDMA1_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                               0x00020000L
3769 #define SDMA1_GFX_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                            0x00040000L
3770 //SDMA1_GFX_MINOR_PTR_UPDATE
3771 #define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                             0x0
3772 #define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE_MASK                                                               0x00000001L
3773 //SDMA1_GFX_MIDCMD_DATA0
3774 #define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT                                                                  0x0
3775 #define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK                                                                    0xFFFFFFFFL
3776 //SDMA1_GFX_MIDCMD_DATA1
3777 #define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT                                                                  0x0
3778 #define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK                                                                    0xFFFFFFFFL
3779 //SDMA1_GFX_MIDCMD_DATA2
3780 #define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT                                                                  0x0
3781 #define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK                                                                    0xFFFFFFFFL
3782 //SDMA1_GFX_MIDCMD_DATA3
3783 #define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT                                                                  0x0
3784 #define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK                                                                    0xFFFFFFFFL
3785 //SDMA1_GFX_MIDCMD_DATA4
3786 #define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT                                                                  0x0
3787 #define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK                                                                    0xFFFFFFFFL
3788 //SDMA1_GFX_MIDCMD_DATA5
3789 #define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT                                                                  0x0
3790 #define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK                                                                    0xFFFFFFFFL
3791 //SDMA1_GFX_MIDCMD_DATA6
3792 #define SDMA1_GFX_MIDCMD_DATA6__DATA6__SHIFT                                                                  0x0
3793 #define SDMA1_GFX_MIDCMD_DATA6__DATA6_MASK                                                                    0xFFFFFFFFL
3794 //SDMA1_GFX_MIDCMD_DATA7
3795 #define SDMA1_GFX_MIDCMD_DATA7__DATA7__SHIFT                                                                  0x0
3796 #define SDMA1_GFX_MIDCMD_DATA7__DATA7_MASK                                                                    0xFFFFFFFFL
3797 //SDMA1_GFX_MIDCMD_DATA8
3798 #define SDMA1_GFX_MIDCMD_DATA8__DATA8__SHIFT                                                                  0x0
3799 #define SDMA1_GFX_MIDCMD_DATA8__DATA8_MASK                                                                    0xFFFFFFFFL
3800 //SDMA1_GFX_MIDCMD_CNTL
3801 #define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT                                                              0x0
3802 #define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT                                                               0x1
3803 #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                             0x4
3804 #define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                           0x8
3805 #define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK                                                                0x00000001L
3806 #define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK                                                                 0x00000002L
3807 #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK                                                               0x000000F0L
3808 #define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                             0x00000100L
3809 //SDMA1_PAGE_RB_CNTL
3810 #define SDMA1_PAGE_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
3811 #define SDMA1_PAGE_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
3812 #define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
3813 #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
3814 #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
3815 #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
3816 #define SDMA1_PAGE_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
3817 #define SDMA1_PAGE_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
3818 #define SDMA1_PAGE_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
3819 #define SDMA1_PAGE_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
3820 #define SDMA1_PAGE_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
3821 #define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
3822 #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
3823 #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
3824 #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
3825 #define SDMA1_PAGE_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
3826 #define SDMA1_PAGE_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
3827 #define SDMA1_PAGE_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
3828 //SDMA1_PAGE_RB_BASE
3829 #define SDMA1_PAGE_RB_BASE__ADDR__SHIFT                                                                       0x0
3830 #define SDMA1_PAGE_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
3831 //SDMA1_PAGE_RB_BASE_HI
3832 #define SDMA1_PAGE_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
3833 #define SDMA1_PAGE_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
3834 //SDMA1_PAGE_RB_RPTR
3835 #define SDMA1_PAGE_RB_RPTR__OFFSET__SHIFT                                                                     0x0
3836 #define SDMA1_PAGE_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
3837 //SDMA1_PAGE_RB_RPTR_HI
3838 #define SDMA1_PAGE_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
3839 #define SDMA1_PAGE_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
3840 //SDMA1_PAGE_RB_WPTR
3841 #define SDMA1_PAGE_RB_WPTR__OFFSET__SHIFT                                                                     0x0
3842 #define SDMA1_PAGE_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
3843 //SDMA1_PAGE_RB_WPTR_HI
3844 #define SDMA1_PAGE_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
3845 #define SDMA1_PAGE_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
3846 //SDMA1_PAGE_RB_WPTR_POLL_CNTL
3847 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
3848 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
3849 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
3850 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
3851 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
3852 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
3853 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
3854 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
3855 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
3856 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
3857 //SDMA1_PAGE_RB_RPTR_ADDR_HI
3858 #define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
3859 #define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
3860 //SDMA1_PAGE_RB_RPTR_ADDR_LO
3861 #define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
3862 #define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
3863 //SDMA1_PAGE_IB_CNTL
3864 #define SDMA1_PAGE_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
3865 #define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
3866 #define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
3867 #define SDMA1_PAGE_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
3868 #define SDMA1_PAGE_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
3869 #define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
3870 #define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
3871 #define SDMA1_PAGE_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
3872 //SDMA1_PAGE_IB_RPTR
3873 #define SDMA1_PAGE_IB_RPTR__OFFSET__SHIFT                                                                     0x2
3874 #define SDMA1_PAGE_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
3875 //SDMA1_PAGE_IB_OFFSET
3876 #define SDMA1_PAGE_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
3877 #define SDMA1_PAGE_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
3878 //SDMA1_PAGE_IB_BASE_LO
3879 #define SDMA1_PAGE_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
3880 #define SDMA1_PAGE_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
3881 //SDMA1_PAGE_IB_BASE_HI
3882 #define SDMA1_PAGE_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
3883 #define SDMA1_PAGE_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
3884 //SDMA1_PAGE_IB_SIZE
3885 #define SDMA1_PAGE_IB_SIZE__SIZE__SHIFT                                                                       0x0
3886 #define SDMA1_PAGE_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
3887 //SDMA1_PAGE_SKIP_CNTL
3888 #define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
3889 #define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
3890 //SDMA1_PAGE_CONTEXT_STATUS
3891 #define SDMA1_PAGE_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
3892 #define SDMA1_PAGE_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
3893 #define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
3894 #define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
3895 #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
3896 #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
3897 #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
3898 #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
3899 #define SDMA1_PAGE_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
3900 #define SDMA1_PAGE_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
3901 #define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
3902 #define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
3903 #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
3904 #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
3905 #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
3906 #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
3907 //SDMA1_PAGE_DOORBELL
3908 #define SDMA1_PAGE_DOORBELL__ENABLE__SHIFT                                                                    0x1c
3909 #define SDMA1_PAGE_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
3910 #define SDMA1_PAGE_DOORBELL__ENABLE_MASK                                                                      0x10000000L
3911 #define SDMA1_PAGE_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
3912 //SDMA1_PAGE_STATUS
3913 #define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
3914 #define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
3915 #define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
3916 #define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
3917 //SDMA1_PAGE_DOORBELL_LOG
3918 //SDMA1_PAGE_WATERMARK
3919 #define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
3920 #define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
3921 #define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
3922 #define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
3923 //SDMA1_PAGE_DOORBELL_OFFSET
3924 #define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
3925 #define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
3926 //SDMA1_PAGE_CSA_ADDR_LO
3927 #define SDMA1_PAGE_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
3928 #define SDMA1_PAGE_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
3929 //SDMA1_PAGE_CSA_ADDR_HI
3930 #define SDMA1_PAGE_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
3931 #define SDMA1_PAGE_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
3932 //SDMA1_PAGE_IB_SUB_REMAIN
3933 #define SDMA1_PAGE_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
3934 #define SDMA1_PAGE_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
3935 //SDMA1_PAGE_PREEMPT
3936 #define SDMA1_PAGE_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
3937 #define SDMA1_PAGE_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
3938 //SDMA1_PAGE_DUMMY_REG
3939 #define SDMA1_PAGE_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
3940 #define SDMA1_PAGE_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
3941 //SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI
3942 #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
3943 #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
3944 //SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO
3945 #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
3946 #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
3947 //SDMA1_PAGE_RB_AQL_CNTL
3948 #define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
3949 #define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
3950 #define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
3951 #define SDMA1_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
3952 #define SDMA1_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
3953 #define SDMA1_PAGE_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
3954 #define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
3955 #define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
3956 #define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
3957 #define SDMA1_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
3958 #define SDMA1_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
3959 #define SDMA1_PAGE_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
3960 //SDMA1_PAGE_MINOR_PTR_UPDATE
3961 #define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
3962 #define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
3963 //SDMA1_PAGE_MIDCMD_DATA0
3964 #define SDMA1_PAGE_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
3965 #define SDMA1_PAGE_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
3966 //SDMA1_PAGE_MIDCMD_DATA1
3967 #define SDMA1_PAGE_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
3968 #define SDMA1_PAGE_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
3969 //SDMA1_PAGE_MIDCMD_DATA2
3970 #define SDMA1_PAGE_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
3971 #define SDMA1_PAGE_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
3972 //SDMA1_PAGE_MIDCMD_DATA3
3973 #define SDMA1_PAGE_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
3974 #define SDMA1_PAGE_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
3975 //SDMA1_PAGE_MIDCMD_DATA4
3976 #define SDMA1_PAGE_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
3977 #define SDMA1_PAGE_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
3978 //SDMA1_PAGE_MIDCMD_DATA5
3979 #define SDMA1_PAGE_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
3980 #define SDMA1_PAGE_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
3981 //SDMA1_PAGE_MIDCMD_DATA6
3982 #define SDMA1_PAGE_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
3983 #define SDMA1_PAGE_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
3984 //SDMA1_PAGE_MIDCMD_DATA7
3985 #define SDMA1_PAGE_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
3986 #define SDMA1_PAGE_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
3987 //SDMA1_PAGE_MIDCMD_DATA8
3988 #define SDMA1_PAGE_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
3989 #define SDMA1_PAGE_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
3990 //SDMA1_PAGE_MIDCMD_CNTL
3991 #define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
3992 #define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
3993 #define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
3994 #define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
3995 #define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
3996 #define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
3997 #define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
3998 #define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
3999 //SDMA1_RLC0_RB_CNTL
4000 #define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
4001 #define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
4002 #define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
4003 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
4004 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
4005 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
4006 #define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
4007 #define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
4008 #define SDMA1_RLC0_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
4009 #define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
4010 #define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
4011 #define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
4012 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
4013 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
4014 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
4015 #define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
4016 #define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
4017 #define SDMA1_RLC0_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
4018 //SDMA1_RLC0_RB_BASE
4019 #define SDMA1_RLC0_RB_BASE__ADDR__SHIFT                                                                       0x0
4020 #define SDMA1_RLC0_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
4021 //SDMA1_RLC0_RB_BASE_HI
4022 #define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
4023 #define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
4024 //SDMA1_RLC0_RB_RPTR
4025 #define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT                                                                     0x0
4026 #define SDMA1_RLC0_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
4027 //SDMA1_RLC0_RB_RPTR_HI
4028 #define SDMA1_RLC0_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
4029 #define SDMA1_RLC0_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
4030 //SDMA1_RLC0_RB_WPTR
4031 #define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT                                                                     0x0
4032 #define SDMA1_RLC0_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
4033 //SDMA1_RLC0_RB_WPTR_HI
4034 #define SDMA1_RLC0_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
4035 #define SDMA1_RLC0_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
4036 //SDMA1_RLC0_RB_WPTR_POLL_CNTL
4037 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
4038 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
4039 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
4040 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
4041 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
4042 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
4043 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
4044 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
4045 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
4046 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
4047 //SDMA1_RLC0_RB_RPTR_ADDR_HI
4048 #define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
4049 #define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
4050 //SDMA1_RLC0_RB_RPTR_ADDR_LO
4051 #define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
4052 #define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
4053 //SDMA1_RLC0_IB_CNTL
4054 #define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
4055 #define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
4056 #define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
4057 #define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
4058 #define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
4059 #define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
4060 #define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
4061 #define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
4062 //SDMA1_RLC0_IB_RPTR
4063 #define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT                                                                     0x2
4064 #define SDMA1_RLC0_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
4065 //SDMA1_RLC0_IB_OFFSET
4066 #define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
4067 #define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
4068 //SDMA1_RLC0_IB_BASE_LO
4069 #define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
4070 #define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
4071 //SDMA1_RLC0_IB_BASE_HI
4072 #define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
4073 #define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
4074 //SDMA1_RLC0_IB_SIZE
4075 #define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT                                                                       0x0
4076 #define SDMA1_RLC0_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
4077 //SDMA1_RLC0_SKIP_CNTL
4078 #define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
4079 #define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
4080 //SDMA1_RLC0_CONTEXT_STATUS
4081 #define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
4082 #define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
4083 #define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
4084 #define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
4085 #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
4086 #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
4087 #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
4088 #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
4089 #define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
4090 #define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
4091 #define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
4092 #define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
4093 #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
4094 #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
4095 #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
4096 #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
4097 //SDMA1_RLC0_DOORBELL
4098 #define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT                                                                    0x1c
4099 #define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
4100 #define SDMA1_RLC0_DOORBELL__ENABLE_MASK                                                                      0x10000000L
4101 #define SDMA1_RLC0_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
4102 //SDMA1_RLC0_STATUS
4103 #define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
4104 #define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
4105 #define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
4106 #define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
4107 //SDMA1_RLC0_DOORBELL_LOG
4108 //SDMA1_RLC0_WATERMARK
4109 #define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
4110 #define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
4111 #define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
4112 #define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
4113 //SDMA1_RLC0_DOORBELL_OFFSET
4114 #define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
4115 #define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
4116 //SDMA1_RLC0_CSA_ADDR_LO
4117 #define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
4118 #define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
4119 //SDMA1_RLC0_CSA_ADDR_HI
4120 #define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
4121 #define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
4122 //SDMA1_RLC0_IB_SUB_REMAIN
4123 #define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
4124 #define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
4125 //SDMA1_RLC0_PREEMPT
4126 #define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
4127 #define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
4128 //SDMA1_RLC0_DUMMY_REG
4129 #define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
4130 #define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
4131 //SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI
4132 #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
4133 #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
4134 //SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO
4135 #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
4136 #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
4137 //SDMA1_RLC0_RB_AQL_CNTL
4138 #define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
4139 #define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
4140 #define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
4141 #define SDMA1_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
4142 #define SDMA1_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
4143 #define SDMA1_RLC0_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
4144 #define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
4145 #define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
4146 #define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
4147 #define SDMA1_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
4148 #define SDMA1_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
4149 #define SDMA1_RLC0_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
4150 //SDMA1_RLC0_MINOR_PTR_UPDATE
4151 #define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
4152 #define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
4153 //SDMA1_RLC0_MIDCMD_DATA0
4154 #define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
4155 #define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
4156 //SDMA1_RLC0_MIDCMD_DATA1
4157 #define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
4158 #define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
4159 //SDMA1_RLC0_MIDCMD_DATA2
4160 #define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
4161 #define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
4162 //SDMA1_RLC0_MIDCMD_DATA3
4163 #define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
4164 #define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
4165 //SDMA1_RLC0_MIDCMD_DATA4
4166 #define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
4167 #define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
4168 //SDMA1_RLC0_MIDCMD_DATA5
4169 #define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
4170 #define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
4171 //SDMA1_RLC0_MIDCMD_DATA6
4172 #define SDMA1_RLC0_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
4173 #define SDMA1_RLC0_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
4174 //SDMA1_RLC0_MIDCMD_DATA7
4175 #define SDMA1_RLC0_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
4176 #define SDMA1_RLC0_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
4177 //SDMA1_RLC0_MIDCMD_DATA8
4178 #define SDMA1_RLC0_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
4179 #define SDMA1_RLC0_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
4180 //SDMA1_RLC0_MIDCMD_CNTL
4181 #define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
4182 #define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
4183 #define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
4184 #define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
4185 #define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
4186 #define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
4187 #define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
4188 #define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
4189 //SDMA1_RLC1_RB_CNTL
4190 #define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
4191 #define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
4192 #define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
4193 #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
4194 #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
4195 #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
4196 #define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
4197 #define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
4198 #define SDMA1_RLC1_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
4199 #define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
4200 #define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
4201 #define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
4202 #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
4203 #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
4204 #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
4205 #define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
4206 #define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
4207 #define SDMA1_RLC1_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
4208 //SDMA1_RLC1_RB_BASE
4209 #define SDMA1_RLC1_RB_BASE__ADDR__SHIFT                                                                       0x0
4210 #define SDMA1_RLC1_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
4211 //SDMA1_RLC1_RB_BASE_HI
4212 #define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
4213 #define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
4214 //SDMA1_RLC1_RB_RPTR
4215 #define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT                                                                     0x0
4216 #define SDMA1_RLC1_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
4217 //SDMA1_RLC1_RB_RPTR_HI
4218 #define SDMA1_RLC1_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
4219 #define SDMA1_RLC1_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
4220 //SDMA1_RLC1_RB_WPTR
4221 #define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT                                                                     0x0
4222 #define SDMA1_RLC1_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
4223 //SDMA1_RLC1_RB_WPTR_HI
4224 #define SDMA1_RLC1_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
4225 #define SDMA1_RLC1_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
4226 //SDMA1_RLC1_RB_WPTR_POLL_CNTL
4227 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
4228 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
4229 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
4230 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
4231 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
4232 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
4233 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
4234 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
4235 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
4236 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
4237 //SDMA1_RLC1_RB_RPTR_ADDR_HI
4238 #define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
4239 #define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
4240 //SDMA1_RLC1_RB_RPTR_ADDR_LO
4241 #define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
4242 #define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
4243 //SDMA1_RLC1_IB_CNTL
4244 #define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
4245 #define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
4246 #define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
4247 #define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
4248 #define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
4249 #define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
4250 #define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
4251 #define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
4252 //SDMA1_RLC1_IB_RPTR
4253 #define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT                                                                     0x2
4254 #define SDMA1_RLC1_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
4255 //SDMA1_RLC1_IB_OFFSET
4256 #define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
4257 #define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
4258 //SDMA1_RLC1_IB_BASE_LO
4259 #define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
4260 #define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
4261 //SDMA1_RLC1_IB_BASE_HI
4262 #define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
4263 #define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
4264 //SDMA1_RLC1_IB_SIZE
4265 #define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT                                                                       0x0
4266 #define SDMA1_RLC1_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
4267 //SDMA1_RLC1_SKIP_CNTL
4268 #define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
4269 #define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
4270 //SDMA1_RLC1_CONTEXT_STATUS
4271 #define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
4272 #define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
4273 #define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
4274 #define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
4275 #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
4276 #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
4277 #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
4278 #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
4279 #define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
4280 #define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
4281 #define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
4282 #define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
4283 #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
4284 #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
4285 #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
4286 #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
4287 //SDMA1_RLC1_DOORBELL
4288 #define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT                                                                    0x1c
4289 #define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
4290 #define SDMA1_RLC1_DOORBELL__ENABLE_MASK                                                                      0x10000000L
4291 #define SDMA1_RLC1_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
4292 //SDMA1_RLC1_STATUS
4293 #define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
4294 #define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
4295 #define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
4296 #define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
4297 //SDMA1_RLC1_DOORBELL_LOG
4298 //SDMA1_RLC1_WATERMARK
4299 #define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
4300 #define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
4301 #define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
4302 #define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
4303 //SDMA1_RLC1_DOORBELL_OFFSET
4304 #define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
4305 #define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
4306 //SDMA1_RLC1_CSA_ADDR_LO
4307 #define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
4308 #define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
4309 //SDMA1_RLC1_CSA_ADDR_HI
4310 #define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
4311 #define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
4312 //SDMA1_RLC1_IB_SUB_REMAIN
4313 #define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
4314 #define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
4315 //SDMA1_RLC1_PREEMPT
4316 #define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
4317 #define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
4318 //SDMA1_RLC1_DUMMY_REG
4319 #define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
4320 #define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
4321 //SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI
4322 #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
4323 #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
4324 //SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO
4325 #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
4326 #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
4327 //SDMA1_RLC1_RB_AQL_CNTL
4328 #define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
4329 #define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
4330 #define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
4331 #define SDMA1_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
4332 #define SDMA1_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
4333 #define SDMA1_RLC1_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
4334 #define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
4335 #define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
4336 #define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
4337 #define SDMA1_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
4338 #define SDMA1_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
4339 #define SDMA1_RLC1_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
4340 //SDMA1_RLC1_MINOR_PTR_UPDATE
4341 #define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
4342 #define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
4343 //SDMA1_RLC1_MIDCMD_DATA0
4344 #define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
4345 #define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
4346 //SDMA1_RLC1_MIDCMD_DATA1
4347 #define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
4348 #define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
4349 //SDMA1_RLC1_MIDCMD_DATA2
4350 #define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
4351 #define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
4352 //SDMA1_RLC1_MIDCMD_DATA3
4353 #define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
4354 #define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
4355 //SDMA1_RLC1_MIDCMD_DATA4
4356 #define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
4357 #define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
4358 //SDMA1_RLC1_MIDCMD_DATA5
4359 #define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
4360 #define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
4361 //SDMA1_RLC1_MIDCMD_DATA6
4362 #define SDMA1_RLC1_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
4363 #define SDMA1_RLC1_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
4364 //SDMA1_RLC1_MIDCMD_DATA7
4365 #define SDMA1_RLC1_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
4366 #define SDMA1_RLC1_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
4367 //SDMA1_RLC1_MIDCMD_DATA8
4368 #define SDMA1_RLC1_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
4369 #define SDMA1_RLC1_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
4370 //SDMA1_RLC1_MIDCMD_CNTL
4371 #define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
4372 #define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
4373 #define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
4374 #define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
4375 #define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
4376 #define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
4377 #define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
4378 #define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
4379 //SDMA1_RLC2_RB_CNTL
4380 #define SDMA1_RLC2_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
4381 #define SDMA1_RLC2_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
4382 #define SDMA1_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
4383 #define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
4384 #define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
4385 #define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
4386 #define SDMA1_RLC2_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
4387 #define SDMA1_RLC2_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
4388 #define SDMA1_RLC2_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
4389 #define SDMA1_RLC2_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
4390 #define SDMA1_RLC2_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
4391 #define SDMA1_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
4392 #define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
4393 #define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
4394 #define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
4395 #define SDMA1_RLC2_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
4396 #define SDMA1_RLC2_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
4397 #define SDMA1_RLC2_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
4398 //SDMA1_RLC2_RB_BASE
4399 #define SDMA1_RLC2_RB_BASE__ADDR__SHIFT                                                                       0x0
4400 #define SDMA1_RLC2_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
4401 //SDMA1_RLC2_RB_BASE_HI
4402 #define SDMA1_RLC2_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
4403 #define SDMA1_RLC2_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
4404 //SDMA1_RLC2_RB_RPTR
4405 #define SDMA1_RLC2_RB_RPTR__OFFSET__SHIFT                                                                     0x0
4406 #define SDMA1_RLC2_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
4407 //SDMA1_RLC2_RB_RPTR_HI
4408 #define SDMA1_RLC2_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
4409 #define SDMA1_RLC2_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
4410 //SDMA1_RLC2_RB_WPTR
4411 #define SDMA1_RLC2_RB_WPTR__OFFSET__SHIFT                                                                     0x0
4412 #define SDMA1_RLC2_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
4413 //SDMA1_RLC2_RB_WPTR_HI
4414 #define SDMA1_RLC2_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
4415 #define SDMA1_RLC2_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
4416 //SDMA1_RLC2_RB_WPTR_POLL_CNTL
4417 #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
4418 #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
4419 #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
4420 #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
4421 #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
4422 #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
4423 #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
4424 #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
4425 #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
4426 #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
4427 //SDMA1_RLC2_RB_RPTR_ADDR_HI
4428 #define SDMA1_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
4429 #define SDMA1_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
4430 //SDMA1_RLC2_RB_RPTR_ADDR_LO
4431 #define SDMA1_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
4432 #define SDMA1_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
4433 //SDMA1_RLC2_IB_CNTL
4434 #define SDMA1_RLC2_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
4435 #define SDMA1_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
4436 #define SDMA1_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
4437 #define SDMA1_RLC2_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
4438 #define SDMA1_RLC2_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
4439 #define SDMA1_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
4440 #define SDMA1_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
4441 #define SDMA1_RLC2_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
4442 //SDMA1_RLC2_IB_RPTR
4443 #define SDMA1_RLC2_IB_RPTR__OFFSET__SHIFT                                                                     0x2
4444 #define SDMA1_RLC2_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
4445 //SDMA1_RLC2_IB_OFFSET
4446 #define SDMA1_RLC2_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
4447 #define SDMA1_RLC2_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
4448 //SDMA1_RLC2_IB_BASE_LO
4449 #define SDMA1_RLC2_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
4450 #define SDMA1_RLC2_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
4451 //SDMA1_RLC2_IB_BASE_HI
4452 #define SDMA1_RLC2_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
4453 #define SDMA1_RLC2_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
4454 //SDMA1_RLC2_IB_SIZE
4455 #define SDMA1_RLC2_IB_SIZE__SIZE__SHIFT                                                                       0x0
4456 #define SDMA1_RLC2_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
4457 //SDMA1_RLC2_SKIP_CNTL
4458 #define SDMA1_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
4459 #define SDMA1_RLC2_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
4460 //SDMA1_RLC2_CONTEXT_STATUS
4461 #define SDMA1_RLC2_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
4462 #define SDMA1_RLC2_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
4463 #define SDMA1_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
4464 #define SDMA1_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
4465 #define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
4466 #define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
4467 #define SDMA1_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
4468 #define SDMA1_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
4469 #define SDMA1_RLC2_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
4470 #define SDMA1_RLC2_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
4471 #define SDMA1_RLC2_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
4472 #define SDMA1_RLC2_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
4473 #define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
4474 #define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
4475 #define SDMA1_RLC2_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
4476 #define SDMA1_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
4477 //SDMA1_RLC2_DOORBELL
4478 #define SDMA1_RLC2_DOORBELL__ENABLE__SHIFT                                                                    0x1c
4479 #define SDMA1_RLC2_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
4480 #define SDMA1_RLC2_DOORBELL__ENABLE_MASK                                                                      0x10000000L
4481 #define SDMA1_RLC2_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
4482 //SDMA1_RLC2_STATUS
4483 #define SDMA1_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
4484 #define SDMA1_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
4485 #define SDMA1_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
4486 #define SDMA1_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
4487 //SDMA1_RLC2_DOORBELL_LOG
4488 //SDMA1_RLC2_WATERMARK
4489 #define SDMA1_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
4490 #define SDMA1_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
4491 #define SDMA1_RLC2_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
4492 #define SDMA1_RLC2_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
4493 //SDMA1_RLC2_DOORBELL_OFFSET
4494 #define SDMA1_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
4495 #define SDMA1_RLC2_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
4496 //SDMA1_RLC2_CSA_ADDR_LO
4497 #define SDMA1_RLC2_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
4498 #define SDMA1_RLC2_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
4499 //SDMA1_RLC2_CSA_ADDR_HI
4500 #define SDMA1_RLC2_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
4501 #define SDMA1_RLC2_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
4502 //SDMA1_RLC2_IB_SUB_REMAIN
4503 #define SDMA1_RLC2_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
4504 #define SDMA1_RLC2_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
4505 //SDMA1_RLC2_PREEMPT
4506 #define SDMA1_RLC2_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
4507 #define SDMA1_RLC2_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
4508 //SDMA1_RLC2_DUMMY_REG
4509 #define SDMA1_RLC2_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
4510 #define SDMA1_RLC2_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
4511 //SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI
4512 #define SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
4513 #define SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
4514 //SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO
4515 #define SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
4516 #define SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
4517 //SDMA1_RLC2_RB_AQL_CNTL
4518 #define SDMA1_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
4519 #define SDMA1_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
4520 #define SDMA1_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
4521 #define SDMA1_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
4522 #define SDMA1_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
4523 #define SDMA1_RLC2_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
4524 #define SDMA1_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
4525 #define SDMA1_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
4526 #define SDMA1_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
4527 #define SDMA1_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
4528 #define SDMA1_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
4529 #define SDMA1_RLC2_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
4530 //SDMA1_RLC2_MINOR_PTR_UPDATE
4531 #define SDMA1_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
4532 #define SDMA1_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
4533 //SDMA1_RLC2_MIDCMD_DATA0
4534 #define SDMA1_RLC2_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
4535 #define SDMA1_RLC2_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
4536 //SDMA1_RLC2_MIDCMD_DATA1
4537 #define SDMA1_RLC2_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
4538 #define SDMA1_RLC2_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
4539 //SDMA1_RLC2_MIDCMD_DATA2
4540 #define SDMA1_RLC2_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
4541 #define SDMA1_RLC2_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
4542 //SDMA1_RLC2_MIDCMD_DATA3
4543 #define SDMA1_RLC2_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
4544 #define SDMA1_RLC2_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
4545 //SDMA1_RLC2_MIDCMD_DATA4
4546 #define SDMA1_RLC2_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
4547 #define SDMA1_RLC2_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
4548 //SDMA1_RLC2_MIDCMD_DATA5
4549 #define SDMA1_RLC2_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
4550 #define SDMA1_RLC2_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
4551 //SDMA1_RLC2_MIDCMD_DATA6
4552 #define SDMA1_RLC2_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
4553 #define SDMA1_RLC2_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
4554 //SDMA1_RLC2_MIDCMD_DATA7
4555 #define SDMA1_RLC2_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
4556 #define SDMA1_RLC2_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
4557 //SDMA1_RLC2_MIDCMD_DATA8
4558 #define SDMA1_RLC2_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
4559 #define SDMA1_RLC2_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
4560 //SDMA1_RLC2_MIDCMD_CNTL
4561 #define SDMA1_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
4562 #define SDMA1_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
4563 #define SDMA1_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
4564 #define SDMA1_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
4565 #define SDMA1_RLC2_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
4566 #define SDMA1_RLC2_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
4567 #define SDMA1_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
4568 #define SDMA1_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
4569 //SDMA1_RLC3_RB_CNTL
4570 #define SDMA1_RLC3_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
4571 #define SDMA1_RLC3_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
4572 #define SDMA1_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
4573 #define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
4574 #define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
4575 #define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
4576 #define SDMA1_RLC3_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
4577 #define SDMA1_RLC3_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
4578 #define SDMA1_RLC3_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
4579 #define SDMA1_RLC3_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
4580 #define SDMA1_RLC3_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
4581 #define SDMA1_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
4582 #define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
4583 #define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
4584 #define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
4585 #define SDMA1_RLC3_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
4586 #define SDMA1_RLC3_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
4587 #define SDMA1_RLC3_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
4588 //SDMA1_RLC3_RB_BASE
4589 #define SDMA1_RLC3_RB_BASE__ADDR__SHIFT                                                                       0x0
4590 #define SDMA1_RLC3_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
4591 //SDMA1_RLC3_RB_BASE_HI
4592 #define SDMA1_RLC3_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
4593 #define SDMA1_RLC3_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
4594 //SDMA1_RLC3_RB_RPTR
4595 #define SDMA1_RLC3_RB_RPTR__OFFSET__SHIFT                                                                     0x0
4596 #define SDMA1_RLC3_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
4597 //SDMA1_RLC3_RB_RPTR_HI
4598 #define SDMA1_RLC3_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
4599 #define SDMA1_RLC3_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
4600 //SDMA1_RLC3_RB_WPTR
4601 #define SDMA1_RLC3_RB_WPTR__OFFSET__SHIFT                                                                     0x0
4602 #define SDMA1_RLC3_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
4603 //SDMA1_RLC3_RB_WPTR_HI
4604 #define SDMA1_RLC3_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
4605 #define SDMA1_RLC3_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
4606 //SDMA1_RLC3_RB_WPTR_POLL_CNTL
4607 #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
4608 #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
4609 #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
4610 #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
4611 #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
4612 #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
4613 #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
4614 #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
4615 #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
4616 #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
4617 //SDMA1_RLC3_RB_RPTR_ADDR_HI
4618 #define SDMA1_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
4619 #define SDMA1_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
4620 //SDMA1_RLC3_RB_RPTR_ADDR_LO
4621 #define SDMA1_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
4622 #define SDMA1_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
4623 //SDMA1_RLC3_IB_CNTL
4624 #define SDMA1_RLC3_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
4625 #define SDMA1_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
4626 #define SDMA1_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
4627 #define SDMA1_RLC3_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
4628 #define SDMA1_RLC3_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
4629 #define SDMA1_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
4630 #define SDMA1_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
4631 #define SDMA1_RLC3_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
4632 //SDMA1_RLC3_IB_RPTR
4633 #define SDMA1_RLC3_IB_RPTR__OFFSET__SHIFT                                                                     0x2
4634 #define SDMA1_RLC3_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
4635 //SDMA1_RLC3_IB_OFFSET
4636 #define SDMA1_RLC3_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
4637 #define SDMA1_RLC3_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
4638 //SDMA1_RLC3_IB_BASE_LO
4639 #define SDMA1_RLC3_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
4640 #define SDMA1_RLC3_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
4641 //SDMA1_RLC3_IB_BASE_HI
4642 #define SDMA1_RLC3_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
4643 #define SDMA1_RLC3_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
4644 //SDMA1_RLC3_IB_SIZE
4645 #define SDMA1_RLC3_IB_SIZE__SIZE__SHIFT                                                                       0x0
4646 #define SDMA1_RLC3_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
4647 //SDMA1_RLC3_SKIP_CNTL
4648 #define SDMA1_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
4649 #define SDMA1_RLC3_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
4650 //SDMA1_RLC3_CONTEXT_STATUS
4651 #define SDMA1_RLC3_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
4652 #define SDMA1_RLC3_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
4653 #define SDMA1_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
4654 #define SDMA1_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
4655 #define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
4656 #define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
4657 #define SDMA1_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
4658 #define SDMA1_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
4659 #define SDMA1_RLC3_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
4660 #define SDMA1_RLC3_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
4661 #define SDMA1_RLC3_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
4662 #define SDMA1_RLC3_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
4663 #define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
4664 #define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
4665 #define SDMA1_RLC3_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
4666 #define SDMA1_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
4667 //SDMA1_RLC3_DOORBELL
4668 #define SDMA1_RLC3_DOORBELL__ENABLE__SHIFT                                                                    0x1c
4669 #define SDMA1_RLC3_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
4670 #define SDMA1_RLC3_DOORBELL__ENABLE_MASK                                                                      0x10000000L
4671 #define SDMA1_RLC3_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
4672 //SDMA1_RLC3_STATUS
4673 #define SDMA1_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
4674 #define SDMA1_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
4675 #define SDMA1_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
4676 #define SDMA1_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
4677 //SDMA1_RLC3_DOORBELL_LOG
4678 //SDMA1_RLC3_WATERMARK
4679 #define SDMA1_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
4680 #define SDMA1_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
4681 #define SDMA1_RLC3_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
4682 #define SDMA1_RLC3_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
4683 //SDMA1_RLC3_DOORBELL_OFFSET
4684 #define SDMA1_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
4685 #define SDMA1_RLC3_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
4686 //SDMA1_RLC3_CSA_ADDR_LO
4687 #define SDMA1_RLC3_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
4688 #define SDMA1_RLC3_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
4689 //SDMA1_RLC3_CSA_ADDR_HI
4690 #define SDMA1_RLC3_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
4691 #define SDMA1_RLC3_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
4692 //SDMA1_RLC3_IB_SUB_REMAIN
4693 #define SDMA1_RLC3_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
4694 #define SDMA1_RLC3_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
4695 //SDMA1_RLC3_PREEMPT
4696 #define SDMA1_RLC3_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
4697 #define SDMA1_RLC3_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
4698 //SDMA1_RLC3_DUMMY_REG
4699 #define SDMA1_RLC3_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
4700 #define SDMA1_RLC3_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
4701 //SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI
4702 #define SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
4703 #define SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
4704 //SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO
4705 #define SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
4706 #define SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
4707 //SDMA1_RLC3_RB_AQL_CNTL
4708 #define SDMA1_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
4709 #define SDMA1_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
4710 #define SDMA1_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
4711 #define SDMA1_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
4712 #define SDMA1_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
4713 #define SDMA1_RLC3_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
4714 #define SDMA1_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
4715 #define SDMA1_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
4716 #define SDMA1_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
4717 #define SDMA1_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
4718 #define SDMA1_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
4719 #define SDMA1_RLC3_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
4720 //SDMA1_RLC3_MINOR_PTR_UPDATE
4721 #define SDMA1_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
4722 #define SDMA1_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
4723 //SDMA1_RLC3_MIDCMD_DATA0
4724 #define SDMA1_RLC3_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
4725 #define SDMA1_RLC3_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
4726 //SDMA1_RLC3_MIDCMD_DATA1
4727 #define SDMA1_RLC3_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
4728 #define SDMA1_RLC3_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
4729 //SDMA1_RLC3_MIDCMD_DATA2
4730 #define SDMA1_RLC3_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
4731 #define SDMA1_RLC3_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
4732 //SDMA1_RLC3_MIDCMD_DATA3
4733 #define SDMA1_RLC3_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
4734 #define SDMA1_RLC3_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
4735 //SDMA1_RLC3_MIDCMD_DATA4
4736 #define SDMA1_RLC3_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
4737 #define SDMA1_RLC3_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
4738 //SDMA1_RLC3_MIDCMD_DATA5
4739 #define SDMA1_RLC3_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
4740 #define SDMA1_RLC3_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
4741 //SDMA1_RLC3_MIDCMD_DATA6
4742 #define SDMA1_RLC3_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
4743 #define SDMA1_RLC3_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
4744 //SDMA1_RLC3_MIDCMD_DATA7
4745 #define SDMA1_RLC3_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
4746 #define SDMA1_RLC3_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
4747 //SDMA1_RLC3_MIDCMD_DATA8
4748 #define SDMA1_RLC3_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
4749 #define SDMA1_RLC3_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
4750 //SDMA1_RLC3_MIDCMD_CNTL
4751 #define SDMA1_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
4752 #define SDMA1_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
4753 #define SDMA1_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
4754 #define SDMA1_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
4755 #define SDMA1_RLC3_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
4756 #define SDMA1_RLC3_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
4757 #define SDMA1_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
4758 #define SDMA1_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
4759 //SDMA1_RLC4_RB_CNTL
4760 #define SDMA1_RLC4_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
4761 #define SDMA1_RLC4_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
4762 #define SDMA1_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
4763 #define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
4764 #define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
4765 #define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
4766 #define SDMA1_RLC4_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
4767 #define SDMA1_RLC4_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
4768 #define SDMA1_RLC4_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
4769 #define SDMA1_RLC4_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
4770 #define SDMA1_RLC4_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
4771 #define SDMA1_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
4772 #define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
4773 #define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
4774 #define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
4775 #define SDMA1_RLC4_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
4776 #define SDMA1_RLC4_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
4777 #define SDMA1_RLC4_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
4778 //SDMA1_RLC4_RB_BASE
4779 #define SDMA1_RLC4_RB_BASE__ADDR__SHIFT                                                                       0x0
4780 #define SDMA1_RLC4_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
4781 //SDMA1_RLC4_RB_BASE_HI
4782 #define SDMA1_RLC4_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
4783 #define SDMA1_RLC4_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
4784 //SDMA1_RLC4_RB_RPTR
4785 #define SDMA1_RLC4_RB_RPTR__OFFSET__SHIFT                                                                     0x0
4786 #define SDMA1_RLC4_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
4787 //SDMA1_RLC4_RB_RPTR_HI
4788 #define SDMA1_RLC4_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
4789 #define SDMA1_RLC4_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
4790 //SDMA1_RLC4_RB_WPTR
4791 #define SDMA1_RLC4_RB_WPTR__OFFSET__SHIFT                                                                     0x0
4792 #define SDMA1_RLC4_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
4793 //SDMA1_RLC4_RB_WPTR_HI
4794 #define SDMA1_RLC4_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
4795 #define SDMA1_RLC4_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
4796 //SDMA1_RLC4_RB_WPTR_POLL_CNTL
4797 #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
4798 #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
4799 #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
4800 #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
4801 #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
4802 #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
4803 #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
4804 #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
4805 #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
4806 #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
4807 //SDMA1_RLC4_RB_RPTR_ADDR_HI
4808 #define SDMA1_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
4809 #define SDMA1_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
4810 //SDMA1_RLC4_RB_RPTR_ADDR_LO
4811 #define SDMA1_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
4812 #define SDMA1_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
4813 //SDMA1_RLC4_IB_CNTL
4814 #define SDMA1_RLC4_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
4815 #define SDMA1_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
4816 #define SDMA1_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
4817 #define SDMA1_RLC4_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
4818 #define SDMA1_RLC4_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
4819 #define SDMA1_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
4820 #define SDMA1_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
4821 #define SDMA1_RLC4_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
4822 //SDMA1_RLC4_IB_RPTR
4823 #define SDMA1_RLC4_IB_RPTR__OFFSET__SHIFT                                                                     0x2
4824 #define SDMA1_RLC4_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
4825 //SDMA1_RLC4_IB_OFFSET
4826 #define SDMA1_RLC4_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
4827 #define SDMA1_RLC4_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
4828 //SDMA1_RLC4_IB_BASE_LO
4829 #define SDMA1_RLC4_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
4830 #define SDMA1_RLC4_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
4831 //SDMA1_RLC4_IB_BASE_HI
4832 #define SDMA1_RLC4_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
4833 #define SDMA1_RLC4_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
4834 //SDMA1_RLC4_IB_SIZE
4835 #define SDMA1_RLC4_IB_SIZE__SIZE__SHIFT                                                                       0x0
4836 #define SDMA1_RLC4_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
4837 //SDMA1_RLC4_SKIP_CNTL
4838 #define SDMA1_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
4839 #define SDMA1_RLC4_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
4840 //SDMA1_RLC4_CONTEXT_STATUS
4841 #define SDMA1_RLC4_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
4842 #define SDMA1_RLC4_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
4843 #define SDMA1_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
4844 #define SDMA1_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
4845 #define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
4846 #define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
4847 #define SDMA1_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
4848 #define SDMA1_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
4849 #define SDMA1_RLC4_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
4850 #define SDMA1_RLC4_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
4851 #define SDMA1_RLC4_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
4852 #define SDMA1_RLC4_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
4853 #define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
4854 #define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
4855 #define SDMA1_RLC4_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
4856 #define SDMA1_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
4857 //SDMA1_RLC4_DOORBELL
4858 #define SDMA1_RLC4_DOORBELL__ENABLE__SHIFT                                                                    0x1c
4859 #define SDMA1_RLC4_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
4860 #define SDMA1_RLC4_DOORBELL__ENABLE_MASK                                                                      0x10000000L
4861 #define SDMA1_RLC4_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
4862 //SDMA1_RLC4_STATUS
4863 #define SDMA1_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
4864 #define SDMA1_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
4865 #define SDMA1_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
4866 #define SDMA1_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
4867 //SDMA1_RLC4_DOORBELL_LOG
4868 //SDMA1_RLC4_WATERMARK
4869 #define SDMA1_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
4870 #define SDMA1_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
4871 #define SDMA1_RLC4_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
4872 #define SDMA1_RLC4_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
4873 //SDMA1_RLC4_DOORBELL_OFFSET
4874 #define SDMA1_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
4875 #define SDMA1_RLC4_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
4876 //SDMA1_RLC4_CSA_ADDR_LO
4877 #define SDMA1_RLC4_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
4878 #define SDMA1_RLC4_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
4879 //SDMA1_RLC4_CSA_ADDR_HI
4880 #define SDMA1_RLC4_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
4881 #define SDMA1_RLC4_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
4882 //SDMA1_RLC4_IB_SUB_REMAIN
4883 #define SDMA1_RLC4_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
4884 #define SDMA1_RLC4_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
4885 //SDMA1_RLC4_PREEMPT
4886 #define SDMA1_RLC4_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
4887 #define SDMA1_RLC4_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
4888 //SDMA1_RLC4_DUMMY_REG
4889 #define SDMA1_RLC4_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
4890 #define SDMA1_RLC4_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
4891 //SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI
4892 #define SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
4893 #define SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
4894 //SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO
4895 #define SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
4896 #define SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
4897 //SDMA1_RLC4_RB_AQL_CNTL
4898 #define SDMA1_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
4899 #define SDMA1_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
4900 #define SDMA1_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
4901 #define SDMA1_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
4902 #define SDMA1_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
4903 #define SDMA1_RLC4_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
4904 #define SDMA1_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
4905 #define SDMA1_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
4906 #define SDMA1_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
4907 #define SDMA1_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
4908 #define SDMA1_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
4909 #define SDMA1_RLC4_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
4910 //SDMA1_RLC4_MINOR_PTR_UPDATE
4911 #define SDMA1_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
4912 #define SDMA1_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
4913 //SDMA1_RLC4_MIDCMD_DATA0
4914 #define SDMA1_RLC4_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
4915 #define SDMA1_RLC4_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
4916 //SDMA1_RLC4_MIDCMD_DATA1
4917 #define SDMA1_RLC4_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
4918 #define SDMA1_RLC4_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
4919 //SDMA1_RLC4_MIDCMD_DATA2
4920 #define SDMA1_RLC4_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
4921 #define SDMA1_RLC4_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
4922 //SDMA1_RLC4_MIDCMD_DATA3
4923 #define SDMA1_RLC4_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
4924 #define SDMA1_RLC4_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
4925 //SDMA1_RLC4_MIDCMD_DATA4
4926 #define SDMA1_RLC4_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
4927 #define SDMA1_RLC4_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
4928 //SDMA1_RLC4_MIDCMD_DATA5
4929 #define SDMA1_RLC4_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
4930 #define SDMA1_RLC4_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
4931 //SDMA1_RLC4_MIDCMD_DATA6
4932 #define SDMA1_RLC4_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
4933 #define SDMA1_RLC4_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
4934 //SDMA1_RLC4_MIDCMD_DATA7
4935 #define SDMA1_RLC4_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
4936 #define SDMA1_RLC4_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
4937 //SDMA1_RLC4_MIDCMD_DATA8
4938 #define SDMA1_RLC4_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
4939 #define SDMA1_RLC4_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
4940 //SDMA1_RLC4_MIDCMD_CNTL
4941 #define SDMA1_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
4942 #define SDMA1_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
4943 #define SDMA1_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
4944 #define SDMA1_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
4945 #define SDMA1_RLC4_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
4946 #define SDMA1_RLC4_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
4947 #define SDMA1_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
4948 #define SDMA1_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
4949 //SDMA1_RLC5_RB_CNTL
4950 #define SDMA1_RLC5_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
4951 #define SDMA1_RLC5_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
4952 #define SDMA1_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
4953 #define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
4954 #define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
4955 #define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
4956 #define SDMA1_RLC5_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
4957 #define SDMA1_RLC5_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
4958 #define SDMA1_RLC5_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
4959 #define SDMA1_RLC5_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
4960 #define SDMA1_RLC5_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
4961 #define SDMA1_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
4962 #define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
4963 #define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
4964 #define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
4965 #define SDMA1_RLC5_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
4966 #define SDMA1_RLC5_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
4967 #define SDMA1_RLC5_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
4968 //SDMA1_RLC5_RB_BASE
4969 #define SDMA1_RLC5_RB_BASE__ADDR__SHIFT                                                                       0x0
4970 #define SDMA1_RLC5_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
4971 //SDMA1_RLC5_RB_BASE_HI
4972 #define SDMA1_RLC5_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
4973 #define SDMA1_RLC5_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
4974 //SDMA1_RLC5_RB_RPTR
4975 #define SDMA1_RLC5_RB_RPTR__OFFSET__SHIFT                                                                     0x0
4976 #define SDMA1_RLC5_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
4977 //SDMA1_RLC5_RB_RPTR_HI
4978 #define SDMA1_RLC5_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
4979 #define SDMA1_RLC5_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
4980 //SDMA1_RLC5_RB_WPTR
4981 #define SDMA1_RLC5_RB_WPTR__OFFSET__SHIFT                                                                     0x0
4982 #define SDMA1_RLC5_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
4983 //SDMA1_RLC5_RB_WPTR_HI
4984 #define SDMA1_RLC5_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
4985 #define SDMA1_RLC5_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
4986 //SDMA1_RLC5_RB_WPTR_POLL_CNTL
4987 #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
4988 #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
4989 #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
4990 #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
4991 #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
4992 #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
4993 #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
4994 #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
4995 #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
4996 #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
4997 //SDMA1_RLC5_RB_RPTR_ADDR_HI
4998 #define SDMA1_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
4999 #define SDMA1_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
5000 //SDMA1_RLC5_RB_RPTR_ADDR_LO
5001 #define SDMA1_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
5002 #define SDMA1_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
5003 //SDMA1_RLC5_IB_CNTL
5004 #define SDMA1_RLC5_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
5005 #define SDMA1_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
5006 #define SDMA1_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
5007 #define SDMA1_RLC5_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
5008 #define SDMA1_RLC5_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
5009 #define SDMA1_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
5010 #define SDMA1_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
5011 #define SDMA1_RLC5_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
5012 //SDMA1_RLC5_IB_RPTR
5013 #define SDMA1_RLC5_IB_RPTR__OFFSET__SHIFT                                                                     0x2
5014 #define SDMA1_RLC5_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
5015 //SDMA1_RLC5_IB_OFFSET
5016 #define SDMA1_RLC5_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
5017 #define SDMA1_RLC5_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
5018 //SDMA1_RLC5_IB_BASE_LO
5019 #define SDMA1_RLC5_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
5020 #define SDMA1_RLC5_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
5021 //SDMA1_RLC5_IB_BASE_HI
5022 #define SDMA1_RLC5_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
5023 #define SDMA1_RLC5_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
5024 //SDMA1_RLC5_IB_SIZE
5025 #define SDMA1_RLC5_IB_SIZE__SIZE__SHIFT                                                                       0x0
5026 #define SDMA1_RLC5_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
5027 //SDMA1_RLC5_SKIP_CNTL
5028 #define SDMA1_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
5029 #define SDMA1_RLC5_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
5030 //SDMA1_RLC5_CONTEXT_STATUS
5031 #define SDMA1_RLC5_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
5032 #define SDMA1_RLC5_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
5033 #define SDMA1_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
5034 #define SDMA1_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
5035 #define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
5036 #define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
5037 #define SDMA1_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
5038 #define SDMA1_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
5039 #define SDMA1_RLC5_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
5040 #define SDMA1_RLC5_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
5041 #define SDMA1_RLC5_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
5042 #define SDMA1_RLC5_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
5043 #define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
5044 #define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
5045 #define SDMA1_RLC5_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
5046 #define SDMA1_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
5047 //SDMA1_RLC5_DOORBELL
5048 #define SDMA1_RLC5_DOORBELL__ENABLE__SHIFT                                                                    0x1c
5049 #define SDMA1_RLC5_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
5050 #define SDMA1_RLC5_DOORBELL__ENABLE_MASK                                                                      0x10000000L
5051 #define SDMA1_RLC5_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
5052 //SDMA1_RLC5_STATUS
5053 #define SDMA1_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
5054 #define SDMA1_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
5055 #define SDMA1_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
5056 #define SDMA1_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
5057 //SDMA1_RLC5_DOORBELL_LOG
5058 //SDMA1_RLC5_WATERMARK
5059 #define SDMA1_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
5060 #define SDMA1_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
5061 #define SDMA1_RLC5_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
5062 #define SDMA1_RLC5_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
5063 //SDMA1_RLC5_DOORBELL_OFFSET
5064 #define SDMA1_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
5065 #define SDMA1_RLC5_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
5066 //SDMA1_RLC5_CSA_ADDR_LO
5067 #define SDMA1_RLC5_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
5068 #define SDMA1_RLC5_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
5069 //SDMA1_RLC5_CSA_ADDR_HI
5070 #define SDMA1_RLC5_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
5071 #define SDMA1_RLC5_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
5072 //SDMA1_RLC5_IB_SUB_REMAIN
5073 #define SDMA1_RLC5_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
5074 #define SDMA1_RLC5_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
5075 //SDMA1_RLC5_PREEMPT
5076 #define SDMA1_RLC5_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
5077 #define SDMA1_RLC5_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
5078 //SDMA1_RLC5_DUMMY_REG
5079 #define SDMA1_RLC5_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
5080 #define SDMA1_RLC5_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
5081 //SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI
5082 #define SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
5083 #define SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
5084 //SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO
5085 #define SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
5086 #define SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
5087 //SDMA1_RLC5_RB_AQL_CNTL
5088 #define SDMA1_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
5089 #define SDMA1_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
5090 #define SDMA1_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
5091 #define SDMA1_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
5092 #define SDMA1_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
5093 #define SDMA1_RLC5_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
5094 #define SDMA1_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
5095 #define SDMA1_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
5096 #define SDMA1_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
5097 #define SDMA1_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
5098 #define SDMA1_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
5099 #define SDMA1_RLC5_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
5100 //SDMA1_RLC5_MINOR_PTR_UPDATE
5101 #define SDMA1_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
5102 #define SDMA1_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
5103 //SDMA1_RLC5_MIDCMD_DATA0
5104 #define SDMA1_RLC5_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
5105 #define SDMA1_RLC5_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
5106 //SDMA1_RLC5_MIDCMD_DATA1
5107 #define SDMA1_RLC5_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
5108 #define SDMA1_RLC5_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
5109 //SDMA1_RLC5_MIDCMD_DATA2
5110 #define SDMA1_RLC5_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
5111 #define SDMA1_RLC5_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
5112 //SDMA1_RLC5_MIDCMD_DATA3
5113 #define SDMA1_RLC5_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
5114 #define SDMA1_RLC5_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
5115 //SDMA1_RLC5_MIDCMD_DATA4
5116 #define SDMA1_RLC5_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
5117 #define SDMA1_RLC5_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
5118 //SDMA1_RLC5_MIDCMD_DATA5
5119 #define SDMA1_RLC5_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
5120 #define SDMA1_RLC5_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
5121 //SDMA1_RLC5_MIDCMD_DATA6
5122 #define SDMA1_RLC5_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
5123 #define SDMA1_RLC5_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
5124 //SDMA1_RLC5_MIDCMD_DATA7
5125 #define SDMA1_RLC5_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
5126 #define SDMA1_RLC5_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
5127 //SDMA1_RLC5_MIDCMD_DATA8
5128 #define SDMA1_RLC5_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
5129 #define SDMA1_RLC5_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
5130 //SDMA1_RLC5_MIDCMD_CNTL
5131 #define SDMA1_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
5132 #define SDMA1_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
5133 #define SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
5134 #define SDMA1_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
5135 #define SDMA1_RLC5_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
5136 #define SDMA1_RLC5_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
5137 #define SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
5138 #define SDMA1_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
5139 //SDMA1_RLC6_RB_CNTL
5140 #define SDMA1_RLC6_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
5141 #define SDMA1_RLC6_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
5142 #define SDMA1_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
5143 #define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
5144 #define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
5145 #define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
5146 #define SDMA1_RLC6_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
5147 #define SDMA1_RLC6_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
5148 #define SDMA1_RLC6_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
5149 #define SDMA1_RLC6_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
5150 #define SDMA1_RLC6_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
5151 #define SDMA1_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
5152 #define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
5153 #define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
5154 #define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
5155 #define SDMA1_RLC6_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
5156 #define SDMA1_RLC6_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
5157 #define SDMA1_RLC6_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
5158 //SDMA1_RLC6_RB_BASE
5159 #define SDMA1_RLC6_RB_BASE__ADDR__SHIFT                                                                       0x0
5160 #define SDMA1_RLC6_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
5161 //SDMA1_RLC6_RB_BASE_HI
5162 #define SDMA1_RLC6_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
5163 #define SDMA1_RLC6_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
5164 //SDMA1_RLC6_RB_RPTR
5165 #define SDMA1_RLC6_RB_RPTR__OFFSET__SHIFT                                                                     0x0
5166 #define SDMA1_RLC6_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
5167 //SDMA1_RLC6_RB_RPTR_HI
5168 #define SDMA1_RLC6_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
5169 #define SDMA1_RLC6_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
5170 //SDMA1_RLC6_RB_WPTR
5171 #define SDMA1_RLC6_RB_WPTR__OFFSET__SHIFT                                                                     0x0
5172 #define SDMA1_RLC6_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
5173 //SDMA1_RLC6_RB_WPTR_HI
5174 #define SDMA1_RLC6_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
5175 #define SDMA1_RLC6_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
5176 //SDMA1_RLC6_RB_WPTR_POLL_CNTL
5177 #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
5178 #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
5179 #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
5180 #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
5181 #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
5182 #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
5183 #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
5184 #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
5185 #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
5186 #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
5187 //SDMA1_RLC6_RB_RPTR_ADDR_HI
5188 #define SDMA1_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
5189 #define SDMA1_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
5190 //SDMA1_RLC6_RB_RPTR_ADDR_LO
5191 #define SDMA1_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
5192 #define SDMA1_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
5193 //SDMA1_RLC6_IB_CNTL
5194 #define SDMA1_RLC6_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
5195 #define SDMA1_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
5196 #define SDMA1_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
5197 #define SDMA1_RLC6_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
5198 #define SDMA1_RLC6_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
5199 #define SDMA1_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
5200 #define SDMA1_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
5201 #define SDMA1_RLC6_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
5202 //SDMA1_RLC6_IB_RPTR
5203 #define SDMA1_RLC6_IB_RPTR__OFFSET__SHIFT                                                                     0x2
5204 #define SDMA1_RLC6_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
5205 //SDMA1_RLC6_IB_OFFSET
5206 #define SDMA1_RLC6_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
5207 #define SDMA1_RLC6_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
5208 //SDMA1_RLC6_IB_BASE_LO
5209 #define SDMA1_RLC6_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
5210 #define SDMA1_RLC6_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
5211 //SDMA1_RLC6_IB_BASE_HI
5212 #define SDMA1_RLC6_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
5213 #define SDMA1_RLC6_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
5214 //SDMA1_RLC6_IB_SIZE
5215 #define SDMA1_RLC6_IB_SIZE__SIZE__SHIFT                                                                       0x0
5216 #define SDMA1_RLC6_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
5217 //SDMA1_RLC6_SKIP_CNTL
5218 #define SDMA1_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
5219 #define SDMA1_RLC6_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
5220 //SDMA1_RLC6_CONTEXT_STATUS
5221 #define SDMA1_RLC6_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
5222 #define SDMA1_RLC6_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
5223 #define SDMA1_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
5224 #define SDMA1_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
5225 #define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
5226 #define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
5227 #define SDMA1_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
5228 #define SDMA1_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
5229 #define SDMA1_RLC6_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
5230 #define SDMA1_RLC6_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
5231 #define SDMA1_RLC6_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
5232 #define SDMA1_RLC6_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
5233 #define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
5234 #define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
5235 #define SDMA1_RLC6_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
5236 #define SDMA1_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
5237 //SDMA1_RLC6_DOORBELL
5238 #define SDMA1_RLC6_DOORBELL__ENABLE__SHIFT                                                                    0x1c
5239 #define SDMA1_RLC6_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
5240 #define SDMA1_RLC6_DOORBELL__ENABLE_MASK                                                                      0x10000000L
5241 #define SDMA1_RLC6_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
5242 //SDMA1_RLC6_STATUS
5243 #define SDMA1_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
5244 #define SDMA1_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
5245 #define SDMA1_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
5246 #define SDMA1_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
5247 //SDMA1_RLC6_DOORBELL_LOG
5248 //SDMA1_RLC6_WATERMARK
5249 #define SDMA1_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
5250 #define SDMA1_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
5251 #define SDMA1_RLC6_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
5252 #define SDMA1_RLC6_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
5253 //SDMA1_RLC6_DOORBELL_OFFSET
5254 #define SDMA1_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
5255 #define SDMA1_RLC6_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
5256 //SDMA1_RLC6_CSA_ADDR_LO
5257 #define SDMA1_RLC6_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
5258 #define SDMA1_RLC6_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
5259 //SDMA1_RLC6_CSA_ADDR_HI
5260 #define SDMA1_RLC6_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
5261 #define SDMA1_RLC6_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
5262 //SDMA1_RLC6_IB_SUB_REMAIN
5263 #define SDMA1_RLC6_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
5264 #define SDMA1_RLC6_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
5265 //SDMA1_RLC6_PREEMPT
5266 #define SDMA1_RLC6_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
5267 #define SDMA1_RLC6_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
5268 //SDMA1_RLC6_DUMMY_REG
5269 #define SDMA1_RLC6_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
5270 #define SDMA1_RLC6_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
5271 //SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI
5272 #define SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
5273 #define SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
5274 //SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO
5275 #define SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
5276 #define SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
5277 //SDMA1_RLC6_RB_AQL_CNTL
5278 #define SDMA1_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
5279 #define SDMA1_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
5280 #define SDMA1_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
5281 #define SDMA1_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
5282 #define SDMA1_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
5283 #define SDMA1_RLC6_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
5284 #define SDMA1_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
5285 #define SDMA1_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
5286 #define SDMA1_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
5287 #define SDMA1_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
5288 #define SDMA1_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
5289 #define SDMA1_RLC6_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
5290 //SDMA1_RLC6_MINOR_PTR_UPDATE
5291 #define SDMA1_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
5292 #define SDMA1_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
5293 //SDMA1_RLC6_MIDCMD_DATA0
5294 #define SDMA1_RLC6_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
5295 #define SDMA1_RLC6_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
5296 //SDMA1_RLC6_MIDCMD_DATA1
5297 #define SDMA1_RLC6_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
5298 #define SDMA1_RLC6_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
5299 //SDMA1_RLC6_MIDCMD_DATA2
5300 #define SDMA1_RLC6_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
5301 #define SDMA1_RLC6_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
5302 //SDMA1_RLC6_MIDCMD_DATA3
5303 #define SDMA1_RLC6_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
5304 #define SDMA1_RLC6_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
5305 //SDMA1_RLC6_MIDCMD_DATA4
5306 #define SDMA1_RLC6_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
5307 #define SDMA1_RLC6_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
5308 //SDMA1_RLC6_MIDCMD_DATA5
5309 #define SDMA1_RLC6_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
5310 #define SDMA1_RLC6_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
5311 //SDMA1_RLC6_MIDCMD_DATA6
5312 #define SDMA1_RLC6_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
5313 #define SDMA1_RLC6_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
5314 //SDMA1_RLC6_MIDCMD_DATA7
5315 #define SDMA1_RLC6_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
5316 #define SDMA1_RLC6_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
5317 //SDMA1_RLC6_MIDCMD_DATA8
5318 #define SDMA1_RLC6_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
5319 #define SDMA1_RLC6_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
5320 //SDMA1_RLC6_MIDCMD_CNTL
5321 #define SDMA1_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
5322 #define SDMA1_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
5323 #define SDMA1_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
5324 #define SDMA1_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
5325 #define SDMA1_RLC6_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
5326 #define SDMA1_RLC6_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
5327 #define SDMA1_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
5328 #define SDMA1_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
5329 //SDMA1_RLC7_RB_CNTL
5330 #define SDMA1_RLC7_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
5331 #define SDMA1_RLC7_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
5332 #define SDMA1_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
5333 #define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
5334 #define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
5335 #define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
5336 #define SDMA1_RLC7_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
5337 #define SDMA1_RLC7_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
5338 #define SDMA1_RLC7_RB_CNTL__RPTR_WB_IDLE__SHIFT                                                               0x1f
5339 #define SDMA1_RLC7_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
5340 #define SDMA1_RLC7_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
5341 #define SDMA1_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
5342 #define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
5343 #define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
5344 #define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
5345 #define SDMA1_RLC7_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
5346 #define SDMA1_RLC7_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
5347 #define SDMA1_RLC7_RB_CNTL__RPTR_WB_IDLE_MASK                                                                 0x80000000L
5348 //SDMA1_RLC7_RB_BASE
5349 #define SDMA1_RLC7_RB_BASE__ADDR__SHIFT                                                                       0x0
5350 #define SDMA1_RLC7_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
5351 //SDMA1_RLC7_RB_BASE_HI
5352 #define SDMA1_RLC7_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
5353 #define SDMA1_RLC7_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
5354 //SDMA1_RLC7_RB_RPTR
5355 #define SDMA1_RLC7_RB_RPTR__OFFSET__SHIFT                                                                     0x0
5356 #define SDMA1_RLC7_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
5357 //SDMA1_RLC7_RB_RPTR_HI
5358 #define SDMA1_RLC7_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
5359 #define SDMA1_RLC7_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
5360 //SDMA1_RLC7_RB_WPTR
5361 #define SDMA1_RLC7_RB_WPTR__OFFSET__SHIFT                                                                     0x0
5362 #define SDMA1_RLC7_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
5363 //SDMA1_RLC7_RB_WPTR_HI
5364 #define SDMA1_RLC7_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
5365 #define SDMA1_RLC7_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
5366 //SDMA1_RLC7_RB_WPTR_POLL_CNTL
5367 #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
5368 #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
5369 #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
5370 #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
5371 #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
5372 #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
5373 #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
5374 #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
5375 #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
5376 #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
5377 //SDMA1_RLC7_RB_RPTR_ADDR_HI
5378 #define SDMA1_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
5379 #define SDMA1_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
5380 //SDMA1_RLC7_RB_RPTR_ADDR_LO
5381 #define SDMA1_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
5382 #define SDMA1_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
5383 //SDMA1_RLC7_IB_CNTL
5384 #define SDMA1_RLC7_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
5385 #define SDMA1_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
5386 #define SDMA1_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
5387 #define SDMA1_RLC7_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
5388 #define SDMA1_RLC7_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
5389 #define SDMA1_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
5390 #define SDMA1_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
5391 #define SDMA1_RLC7_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
5392 //SDMA1_RLC7_IB_RPTR
5393 #define SDMA1_RLC7_IB_RPTR__OFFSET__SHIFT                                                                     0x2
5394 #define SDMA1_RLC7_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
5395 //SDMA1_RLC7_IB_OFFSET
5396 #define SDMA1_RLC7_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
5397 #define SDMA1_RLC7_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
5398 //SDMA1_RLC7_IB_BASE_LO
5399 #define SDMA1_RLC7_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
5400 #define SDMA1_RLC7_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
5401 //SDMA1_RLC7_IB_BASE_HI
5402 #define SDMA1_RLC7_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
5403 #define SDMA1_RLC7_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
5404 //SDMA1_RLC7_IB_SIZE
5405 #define SDMA1_RLC7_IB_SIZE__SIZE__SHIFT                                                                       0x0
5406 #define SDMA1_RLC7_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
5407 //SDMA1_RLC7_SKIP_CNTL
5408 #define SDMA1_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
5409 #define SDMA1_RLC7_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
5410 //SDMA1_RLC7_CONTEXT_STATUS
5411 #define SDMA1_RLC7_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
5412 #define SDMA1_RLC7_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
5413 #define SDMA1_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
5414 #define SDMA1_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
5415 #define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
5416 #define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
5417 #define SDMA1_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
5418 #define SDMA1_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
5419 #define SDMA1_RLC7_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
5420 #define SDMA1_RLC7_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
5421 #define SDMA1_RLC7_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
5422 #define SDMA1_RLC7_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
5423 #define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
5424 #define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
5425 #define SDMA1_RLC7_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
5426 #define SDMA1_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
5427 //SDMA1_RLC7_DOORBELL
5428 #define SDMA1_RLC7_DOORBELL__ENABLE__SHIFT                                                                    0x1c
5429 #define SDMA1_RLC7_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
5430 #define SDMA1_RLC7_DOORBELL__ENABLE_MASK                                                                      0x10000000L
5431 #define SDMA1_RLC7_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
5432 //SDMA1_RLC7_STATUS
5433 #define SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
5434 #define SDMA1_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
5435 #define SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
5436 #define SDMA1_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
5437 //SDMA1_RLC7_DOORBELL_LOG
5438 //SDMA1_RLC7_WATERMARK
5439 #define SDMA1_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
5440 #define SDMA1_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
5441 #define SDMA1_RLC7_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
5442 #define SDMA1_RLC7_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
5443 //SDMA1_RLC7_DOORBELL_OFFSET
5444 #define SDMA1_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
5445 #define SDMA1_RLC7_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
5446 //SDMA1_RLC7_CSA_ADDR_LO
5447 #define SDMA1_RLC7_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
5448 #define SDMA1_RLC7_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
5449 //SDMA1_RLC7_CSA_ADDR_HI
5450 #define SDMA1_RLC7_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
5451 #define SDMA1_RLC7_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
5452 //SDMA1_RLC7_IB_SUB_REMAIN
5453 #define SDMA1_RLC7_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
5454 #define SDMA1_RLC7_IB_SUB_REMAIN__SIZE_MASK                                                                   0x00003FFFL
5455 //SDMA1_RLC7_PREEMPT
5456 #define SDMA1_RLC7_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
5457 #define SDMA1_RLC7_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
5458 //SDMA1_RLC7_DUMMY_REG
5459 #define SDMA1_RLC7_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
5460 #define SDMA1_RLC7_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
5461 //SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI
5462 #define SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
5463 #define SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
5464 //SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO
5465 #define SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
5466 #define SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
5467 //SDMA1_RLC7_RB_AQL_CNTL
5468 #define SDMA1_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
5469 #define SDMA1_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
5470 #define SDMA1_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
5471 #define SDMA1_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                  0x10
5472 #define SDMA1_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT                                            0x11
5473 #define SDMA1_RLC7_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT                                                         0x12
5474 #define SDMA1_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
5475 #define SDMA1_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
5476 #define SDMA1_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
5477 #define SDMA1_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                    0x00010000L
5478 #define SDMA1_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK                                              0x00020000L
5479 #define SDMA1_RLC7_RB_AQL_CNTL__OVERLAP_ENABLE_MASK                                                           0x00040000L
5480 //SDMA1_RLC7_MINOR_PTR_UPDATE
5481 #define SDMA1_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
5482 #define SDMA1_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
5483 //SDMA1_RLC7_MIDCMD_DATA0
5484 #define SDMA1_RLC7_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
5485 #define SDMA1_RLC7_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
5486 //SDMA1_RLC7_MIDCMD_DATA1
5487 #define SDMA1_RLC7_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
5488 #define SDMA1_RLC7_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
5489 //SDMA1_RLC7_MIDCMD_DATA2
5490 #define SDMA1_RLC7_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
5491 #define SDMA1_RLC7_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
5492 //SDMA1_RLC7_MIDCMD_DATA3
5493 #define SDMA1_RLC7_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
5494 #define SDMA1_RLC7_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
5495 //SDMA1_RLC7_MIDCMD_DATA4
5496 #define SDMA1_RLC7_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
5497 #define SDMA1_RLC7_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
5498 //SDMA1_RLC7_MIDCMD_DATA5
5499 #define SDMA1_RLC7_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
5500 #define SDMA1_RLC7_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
5501 //SDMA1_RLC7_MIDCMD_DATA6
5502 #define SDMA1_RLC7_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
5503 #define SDMA1_RLC7_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
5504 //SDMA1_RLC7_MIDCMD_DATA7
5505 #define SDMA1_RLC7_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
5506 #define SDMA1_RLC7_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
5507 //SDMA1_RLC7_MIDCMD_DATA8
5508 #define SDMA1_RLC7_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
5509 #define SDMA1_RLC7_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
5510 //SDMA1_RLC7_MIDCMD_CNTL
5511 #define SDMA1_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
5512 #define SDMA1_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
5513 #define SDMA1_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
5514 #define SDMA1_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
5515 #define SDMA1_RLC7_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
5516 #define SDMA1_RLC7_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
5517 #define SDMA1_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
5518 #define SDMA1_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
5519 
5520 
5521 // addressBlock: gc_grbmdec
5522 //GRBM_CNTL
5523 #define GRBM_CNTL__READ_TIMEOUT__SHIFT                                                                        0x0
5524 #define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT                                                                   0x1f
5525 #define GRBM_CNTL__READ_TIMEOUT_MASK                                                                          0x000000FFL
5526 #define GRBM_CNTL__REPORT_LAST_RDERR_MASK                                                                     0x80000000L
5527 //GRBM_SKEW_CNTL
5528 #define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT                                                             0x0
5529 #define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT                                                                     0x6
5530 #define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK                                                               0x0000003FL
5531 #define GRBM_SKEW_CNTL__SKEW_COUNT_MASK                                                                       0x00000FC0L
5532 //GRBM_STATUS2
5533 #define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT                                                           0x0
5534 #define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT                                                           0x4
5535 #define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT                                                           0x5
5536 #define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT                                                              0x6
5537 #define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT                                                              0x7
5538 #define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT                                                              0x8
5539 #define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT                                                              0x9
5540 #define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT                                                              0xa
5541 #define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT                                                              0xb
5542 #define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT                                                              0xc
5543 #define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT                                                              0xd
5544 #define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT                                                                   0xe
5545 #define GRBM_STATUS2__UTCL2_BUSY__SHIFT                                                                       0xf
5546 #define GRBM_STATUS2__EA_BUSY__SHIFT                                                                          0x10
5547 #define GRBM_STATUS2__RMI_BUSY__SHIFT                                                                         0x11
5548 #define GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT                                                                 0x12
5549 #define GRBM_STATUS2__CPF_RQ_PENDING__SHIFT                                                                   0x13
5550 #define GRBM_STATUS2__EA_LINK_BUSY__SHIFT                                                                     0x14
5551 #define GRBM_STATUS2__SDMA_BUSY__SHIFT                                                                        0x15
5552 #define GRBM_STATUS2__SDMA0_RQ_PENDING__SHIFT                                                                 0x16
5553 #define GRBM_STATUS2__SDMA1_RQ_PENDING__SHIFT                                                                 0x17
5554 #define GRBM_STATUS2__RLC_BUSY__SHIFT                                                                         0x18
5555 #define GRBM_STATUS2__TCP_BUSY__SHIFT                                                                         0x19
5556 #define GRBM_STATUS2__CPF_BUSY__SHIFT                                                                         0x1c
5557 #define GRBM_STATUS2__CPC_BUSY__SHIFT                                                                         0x1d
5558 #define GRBM_STATUS2__CPG_BUSY__SHIFT                                                                         0x1e
5559 #define GRBM_STATUS2__CPAXI_BUSY__SHIFT                                                                       0x1f
5560 #define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK                                                             0x0000000FL
5561 #define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK                                                             0x00000010L
5562 #define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK                                                             0x00000020L
5563 #define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK                                                                0x00000040L
5564 #define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK                                                                0x00000080L
5565 #define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK                                                                0x00000100L
5566 #define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK                                                                0x00000200L
5567 #define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK                                                                0x00000400L
5568 #define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK                                                                0x00000800L
5569 #define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK                                                                0x00001000L
5570 #define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK                                                                0x00002000L
5571 #define GRBM_STATUS2__RLC_RQ_PENDING_MASK                                                                     0x00004000L
5572 #define GRBM_STATUS2__UTCL2_BUSY_MASK                                                                         0x00008000L
5573 #define GRBM_STATUS2__EA_BUSY_MASK                                                                            0x00010000L
5574 #define GRBM_STATUS2__RMI_BUSY_MASK                                                                           0x00020000L
5575 #define GRBM_STATUS2__UTCL2_RQ_PENDING_MASK                                                                   0x00040000L
5576 #define GRBM_STATUS2__CPF_RQ_PENDING_MASK                                                                     0x00080000L
5577 #define GRBM_STATUS2__EA_LINK_BUSY_MASK                                                                       0x00100000L
5578 #define GRBM_STATUS2__SDMA_BUSY_MASK                                                                          0x00200000L
5579 #define GRBM_STATUS2__SDMA0_RQ_PENDING_MASK                                                                   0x00400000L
5580 #define GRBM_STATUS2__SDMA1_RQ_PENDING_MASK                                                                   0x00800000L
5581 #define GRBM_STATUS2__RLC_BUSY_MASK                                                                           0x01000000L
5582 #define GRBM_STATUS2__TCP_BUSY_MASK                                                                           0x02000000L
5583 #define GRBM_STATUS2__CPF_BUSY_MASK                                                                           0x10000000L
5584 #define GRBM_STATUS2__CPC_BUSY_MASK                                                                           0x20000000L
5585 #define GRBM_STATUS2__CPG_BUSY_MASK                                                                           0x40000000L
5586 #define GRBM_STATUS2__CPAXI_BUSY_MASK                                                                         0x80000000L
5587 //GRBM_PWR_CNTL
5588 #define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT                                                                    0x0
5589 #define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT                                                                    0x2
5590 #define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT                                                                    0x4
5591 #define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT                                                                    0x6
5592 #define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT                                                                      0xe
5593 #define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT                                                                      0xf
5594 #define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK                                                                      0x00000003L
5595 #define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK                                                                      0x0000000CL
5596 #define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK                                                                      0x00000030L
5597 #define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK                                                                      0x000000C0L
5598 #define GRBM_PWR_CNTL__GFX_REQ_EN_MASK                                                                        0x00004000L
5599 #define GRBM_PWR_CNTL__ALL_REQ_EN_MASK                                                                        0x00008000L
5600 //GRBM_STATUS
5601 #define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT                                                            0x0
5602 #define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT                                                            0x7
5603 #define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT                                                            0x8
5604 #define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT                                                                0x9
5605 #define GRBM_STATUS__DB_CLEAN__SHIFT                                                                          0xc
5606 #define GRBM_STATUS__CB_CLEAN__SHIFT                                                                          0xd
5607 #define GRBM_STATUS__TA_BUSY__SHIFT                                                                           0xe
5608 #define GRBM_STATUS__GDS_BUSY__SHIFT                                                                          0xf
5609 #define GRBM_STATUS__GE_BUSY_NO_DMA__SHIFT                                                                    0x10
5610 #define GRBM_STATUS__SX_BUSY__SHIFT                                                                           0x14
5611 #define GRBM_STATUS__GE_BUSY__SHIFT                                                                           0x15
5612 #define GRBM_STATUS__SPI_BUSY__SHIFT                                                                          0x16
5613 #define GRBM_STATUS__BCI_BUSY__SHIFT                                                                          0x17
5614 #define GRBM_STATUS__SC_BUSY__SHIFT                                                                           0x18
5615 #define GRBM_STATUS__PA_BUSY__SHIFT                                                                           0x19
5616 #define GRBM_STATUS__DB_BUSY__SHIFT                                                                           0x1a
5617 #define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT                                                                 0x1c
5618 #define GRBM_STATUS__CP_BUSY__SHIFT                                                                           0x1d
5619 #define GRBM_STATUS__CB_BUSY__SHIFT                                                                           0x1e
5620 #define GRBM_STATUS__GUI_ACTIVE__SHIFT                                                                        0x1f
5621 #define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK                                                              0x0000000FL
5622 #define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK                                                              0x00000080L
5623 #define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK                                                              0x00000100L
5624 #define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK                                                                  0x00000200L
5625 #define GRBM_STATUS__DB_CLEAN_MASK                                                                            0x00001000L
5626 #define GRBM_STATUS__CB_CLEAN_MASK                                                                            0x00002000L
5627 #define GRBM_STATUS__TA_BUSY_MASK                                                                             0x00004000L
5628 #define GRBM_STATUS__GDS_BUSY_MASK                                                                            0x00008000L
5629 #define GRBM_STATUS__GE_BUSY_NO_DMA_MASK                                                                      0x00010000L
5630 #define GRBM_STATUS__SX_BUSY_MASK                                                                             0x00100000L
5631 #define GRBM_STATUS__GE_BUSY_MASK                                                                             0x00200000L
5632 #define GRBM_STATUS__SPI_BUSY_MASK                                                                            0x00400000L
5633 #define GRBM_STATUS__BCI_BUSY_MASK                                                                            0x00800000L
5634 #define GRBM_STATUS__SC_BUSY_MASK                                                                             0x01000000L
5635 #define GRBM_STATUS__PA_BUSY_MASK                                                                             0x02000000L
5636 #define GRBM_STATUS__DB_BUSY_MASK                                                                             0x04000000L
5637 #define GRBM_STATUS__CP_COHERENCY_BUSY_MASK                                                                   0x10000000L
5638 #define GRBM_STATUS__CP_BUSY_MASK                                                                             0x20000000L
5639 #define GRBM_STATUS__CB_BUSY_MASK                                                                             0x40000000L
5640 #define GRBM_STATUS__GUI_ACTIVE_MASK                                                                          0x80000000L
5641 //GRBM_STATUS_SE0
5642 #define GRBM_STATUS_SE0__DB_CLEAN__SHIFT                                                                      0x1
5643 #define GRBM_STATUS_SE0__CB_CLEAN__SHIFT                                                                      0x2
5644 #define GRBM_STATUS_SE0__UTCL1_BUSY__SHIFT                                                                    0x3
5645 #define GRBM_STATUS_SE0__TCP_BUSY__SHIFT                                                                      0x4
5646 #define GRBM_STATUS_SE0__GL1CC_BUSY__SHIFT                                                                    0x5
5647 #define GRBM_STATUS_SE0__RMI_BUSY__SHIFT                                                                      0x15
5648 #define GRBM_STATUS_SE0__BCI_BUSY__SHIFT                                                                      0x16
5649 #define GRBM_STATUS_SE0__PA_BUSY__SHIFT                                                                       0x18
5650 #define GRBM_STATUS_SE0__TA_BUSY__SHIFT                                                                       0x19
5651 #define GRBM_STATUS_SE0__SX_BUSY__SHIFT                                                                       0x1a
5652 #define GRBM_STATUS_SE0__SPI_BUSY__SHIFT                                                                      0x1b
5653 #define GRBM_STATUS_SE0__SC_BUSY__SHIFT                                                                       0x1d
5654 #define GRBM_STATUS_SE0__DB_BUSY__SHIFT                                                                       0x1e
5655 #define GRBM_STATUS_SE0__CB_BUSY__SHIFT                                                                       0x1f
5656 #define GRBM_STATUS_SE0__DB_CLEAN_MASK                                                                        0x00000002L
5657 #define GRBM_STATUS_SE0__CB_CLEAN_MASK                                                                        0x00000004L
5658 #define GRBM_STATUS_SE0__UTCL1_BUSY_MASK                                                                      0x00000008L
5659 #define GRBM_STATUS_SE0__TCP_BUSY_MASK                                                                        0x00000010L
5660 #define GRBM_STATUS_SE0__GL1CC_BUSY_MASK                                                                      0x00000020L
5661 #define GRBM_STATUS_SE0__RMI_BUSY_MASK                                                                        0x00200000L
5662 #define GRBM_STATUS_SE0__BCI_BUSY_MASK                                                                        0x00400000L
5663 #define GRBM_STATUS_SE0__PA_BUSY_MASK                                                                         0x01000000L
5664 #define GRBM_STATUS_SE0__TA_BUSY_MASK                                                                         0x02000000L
5665 #define GRBM_STATUS_SE0__SX_BUSY_MASK                                                                         0x04000000L
5666 #define GRBM_STATUS_SE0__SPI_BUSY_MASK                                                                        0x08000000L
5667 #define GRBM_STATUS_SE0__SC_BUSY_MASK                                                                         0x20000000L
5668 #define GRBM_STATUS_SE0__DB_BUSY_MASK                                                                         0x40000000L
5669 #define GRBM_STATUS_SE0__CB_BUSY_MASK                                                                         0x80000000L
5670 //GRBM_STATUS_SE1
5671 #define GRBM_STATUS_SE1__DB_CLEAN__SHIFT                                                                      0x1
5672 #define GRBM_STATUS_SE1__CB_CLEAN__SHIFT                                                                      0x2
5673 #define GRBM_STATUS_SE1__UTCL1_BUSY__SHIFT                                                                    0x3
5674 #define GRBM_STATUS_SE1__TCP_BUSY__SHIFT                                                                      0x4
5675 #define GRBM_STATUS_SE1__GL1CC_BUSY__SHIFT                                                                    0x5
5676 #define GRBM_STATUS_SE1__RMI_BUSY__SHIFT                                                                      0x15
5677 #define GRBM_STATUS_SE1__BCI_BUSY__SHIFT                                                                      0x16
5678 #define GRBM_STATUS_SE1__PA_BUSY__SHIFT                                                                       0x18
5679 #define GRBM_STATUS_SE1__TA_BUSY__SHIFT                                                                       0x19
5680 #define GRBM_STATUS_SE1__SX_BUSY__SHIFT                                                                       0x1a
5681 #define GRBM_STATUS_SE1__SPI_BUSY__SHIFT                                                                      0x1b
5682 #define GRBM_STATUS_SE1__SC_BUSY__SHIFT                                                                       0x1d
5683 #define GRBM_STATUS_SE1__DB_BUSY__SHIFT                                                                       0x1e
5684 #define GRBM_STATUS_SE1__CB_BUSY__SHIFT                                                                       0x1f
5685 #define GRBM_STATUS_SE1__DB_CLEAN_MASK                                                                        0x00000002L
5686 #define GRBM_STATUS_SE1__CB_CLEAN_MASK                                                                        0x00000004L
5687 #define GRBM_STATUS_SE1__UTCL1_BUSY_MASK                                                                      0x00000008L
5688 #define GRBM_STATUS_SE1__TCP_BUSY_MASK                                                                        0x00000010L
5689 #define GRBM_STATUS_SE1__GL1CC_BUSY_MASK                                                                      0x00000020L
5690 #define GRBM_STATUS_SE1__RMI_BUSY_MASK                                                                        0x00200000L
5691 #define GRBM_STATUS_SE1__BCI_BUSY_MASK                                                                        0x00400000L
5692 #define GRBM_STATUS_SE1__PA_BUSY_MASK                                                                         0x01000000L
5693 #define GRBM_STATUS_SE1__TA_BUSY_MASK                                                                         0x02000000L
5694 #define GRBM_STATUS_SE1__SX_BUSY_MASK                                                                         0x04000000L
5695 #define GRBM_STATUS_SE1__SPI_BUSY_MASK                                                                        0x08000000L
5696 #define GRBM_STATUS_SE1__SC_BUSY_MASK                                                                         0x20000000L
5697 #define GRBM_STATUS_SE1__DB_BUSY_MASK                                                                         0x40000000L
5698 #define GRBM_STATUS_SE1__CB_BUSY_MASK                                                                         0x80000000L
5699 //GRBM_STATUS3
5700 #define GRBM_STATUS3__GRBM_RLC_INTR_CREDIT_PENDING__SHIFT                                                     0x5
5701 #define GRBM_STATUS3__GRBM_UTCL2_INTR_CREDIT_PENDING__SHIFT                                                   0x6
5702 #define GRBM_STATUS3__GRBM_CPF_INTR_CREDIT_PENDING__SHIFT                                                     0x7
5703 #define GRBM_STATUS3__MESPIPE0_RQ_PENDING__SHIFT                                                              0x8
5704 #define GRBM_STATUS3__MESPIPE1_RQ_PENDING__SHIFT                                                              0x9
5705 #define GRBM_STATUS3__MESPIPE2_RQ_PENDING__SHIFT                                                              0xa
5706 #define GRBM_STATUS3__MESPIPE3_RQ_PENDING__SHIFT                                                              0xb
5707 #define GRBM_STATUS3__PH_BUSY__SHIFT                                                                          0xd
5708 #define GRBM_STATUS3__CH_BUSY__SHIFT                                                                          0xe
5709 #define GRBM_STATUS3__GL2CC_BUSY__SHIFT                                                                       0xf
5710 #define GRBM_STATUS3__GL1CC_BUSY__SHIFT                                                                       0x10
5711 #define GRBM_STATUS3__GUS_LINK_BUSY__SHIFT                                                                    0x1c
5712 #define GRBM_STATUS3__GUS_BUSY__SHIFT                                                                         0x1d
5713 #define GRBM_STATUS3__UTCL1_BUSY__SHIFT                                                                       0x1e
5714 #define GRBM_STATUS3__PMM_BUSY__SHIFT                                                                         0x1f
5715 #define GRBM_STATUS3__GRBM_RLC_INTR_CREDIT_PENDING_MASK                                                       0x00000020L
5716 #define GRBM_STATUS3__GRBM_UTCL2_INTR_CREDIT_PENDING_MASK                                                     0x00000040L
5717 #define GRBM_STATUS3__GRBM_CPF_INTR_CREDIT_PENDING_MASK                                                       0x00000080L
5718 #define GRBM_STATUS3__MESPIPE0_RQ_PENDING_MASK                                                                0x00000100L
5719 #define GRBM_STATUS3__MESPIPE1_RQ_PENDING_MASK                                                                0x00000200L
5720 #define GRBM_STATUS3__MESPIPE2_RQ_PENDING_MASK                                                                0x00000400L
5721 #define GRBM_STATUS3__MESPIPE3_RQ_PENDING_MASK                                                                0x00000800L
5722 #define GRBM_STATUS3__PH_BUSY_MASK                                                                            0x00002000L
5723 #define GRBM_STATUS3__CH_BUSY_MASK                                                                            0x00004000L
5724 #define GRBM_STATUS3__GL2CC_BUSY_MASK                                                                         0x00008000L
5725 #define GRBM_STATUS3__GL1CC_BUSY_MASK                                                                         0x00010000L
5726 #define GRBM_STATUS3__GUS_LINK_BUSY_MASK                                                                      0x10000000L
5727 #define GRBM_STATUS3__GUS_BUSY_MASK                                                                           0x20000000L
5728 #define GRBM_STATUS3__UTCL1_BUSY_MASK                                                                         0x40000000L
5729 #define GRBM_STATUS3__PMM_BUSY_MASK                                                                           0x80000000L
5730 //GRBM_SOFT_RESET
5731 #define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT                                                                 0x0
5732 #define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT                                                                0x2
5733 #define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT                                                                0x10
5734 #define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT                                                                0x11
5735 #define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT                                                                0x12
5736 #define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT                                                                0x13
5737 #define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT                                                                0x14
5738 #define GRBM_SOFT_RESET__SOFT_RESET_CPAXI__SHIFT                                                              0x15
5739 #define GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT                                                                 0x16
5740 #define GRBM_SOFT_RESET__SOFT_RESET_SDMA0__SHIFT                                                              0x17
5741 #define GRBM_SOFT_RESET__SOFT_RESET_SDMA1__SHIFT                                                              0x18
5742 #define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK                                                                   0x00000001L
5743 #define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK                                                                  0x00000004L
5744 #define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK                                                                  0x00010000L
5745 #define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK                                                                  0x00020000L
5746 #define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK                                                                  0x00040000L
5747 #define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK                                                                  0x00080000L
5748 #define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK                                                                  0x00100000L
5749 #define GRBM_SOFT_RESET__SOFT_RESET_CPAXI_MASK                                                                0x00200000L
5750 #define GRBM_SOFT_RESET__SOFT_RESET_EA_MASK                                                                   0x00400000L
5751 #define GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK                                                                0x00800000L
5752 #define GRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK                                                                0x01000000L
5753 //GRBM_GFX_CLKEN_CNTL
5754 #define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT                                                          0x0
5755 #define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT                                                            0x8
5756 #define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK                                                            0x0000000FL
5757 #define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK                                                              0x00001F00L
5758 //GRBM_WAIT_IDLE_CLOCKS
5759 #define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT                                                        0x0
5760 #define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK                                                          0x000000FFL
5761 //GRBM_STATUS_SE2
5762 #define GRBM_STATUS_SE2__DB_CLEAN__SHIFT                                                                      0x1
5763 #define GRBM_STATUS_SE2__CB_CLEAN__SHIFT                                                                      0x2
5764 #define GRBM_STATUS_SE2__UTCL1_BUSY__SHIFT                                                                    0x3
5765 #define GRBM_STATUS_SE2__TCP_BUSY__SHIFT                                                                      0x4
5766 #define GRBM_STATUS_SE2__GL1CC_BUSY__SHIFT                                                                    0x5
5767 #define GRBM_STATUS_SE2__RMI_BUSY__SHIFT                                                                      0x15
5768 #define GRBM_STATUS_SE2__BCI_BUSY__SHIFT                                                                      0x16
5769 #define GRBM_STATUS_SE2__PA_BUSY__SHIFT                                                                       0x18
5770 #define GRBM_STATUS_SE2__TA_BUSY__SHIFT                                                                       0x19
5771 #define GRBM_STATUS_SE2__SX_BUSY__SHIFT                                                                       0x1a
5772 #define GRBM_STATUS_SE2__SPI_BUSY__SHIFT                                                                      0x1b
5773 #define GRBM_STATUS_SE2__SC_BUSY__SHIFT                                                                       0x1d
5774 #define GRBM_STATUS_SE2__DB_BUSY__SHIFT                                                                       0x1e
5775 #define GRBM_STATUS_SE2__CB_BUSY__SHIFT                                                                       0x1f
5776 #define GRBM_STATUS_SE2__DB_CLEAN_MASK                                                                        0x00000002L
5777 #define GRBM_STATUS_SE2__CB_CLEAN_MASK                                                                        0x00000004L
5778 #define GRBM_STATUS_SE2__UTCL1_BUSY_MASK                                                                      0x00000008L
5779 #define GRBM_STATUS_SE2__TCP_BUSY_MASK                                                                        0x00000010L
5780 #define GRBM_STATUS_SE2__GL1CC_BUSY_MASK                                                                      0x00000020L
5781 #define GRBM_STATUS_SE2__RMI_BUSY_MASK                                                                        0x00200000L
5782 #define GRBM_STATUS_SE2__BCI_BUSY_MASK                                                                        0x00400000L
5783 #define GRBM_STATUS_SE2__PA_BUSY_MASK                                                                         0x01000000L
5784 #define GRBM_STATUS_SE2__TA_BUSY_MASK                                                                         0x02000000L
5785 #define GRBM_STATUS_SE2__SX_BUSY_MASK                                                                         0x04000000L
5786 #define GRBM_STATUS_SE2__SPI_BUSY_MASK                                                                        0x08000000L
5787 #define GRBM_STATUS_SE2__SC_BUSY_MASK                                                                         0x20000000L
5788 #define GRBM_STATUS_SE2__DB_BUSY_MASK                                                                         0x40000000L
5789 #define GRBM_STATUS_SE2__CB_BUSY_MASK                                                                         0x80000000L
5790 //GRBM_STATUS_SE3
5791 #define GRBM_STATUS_SE3__DB_CLEAN__SHIFT                                                                      0x1
5792 #define GRBM_STATUS_SE3__CB_CLEAN__SHIFT                                                                      0x2
5793 #define GRBM_STATUS_SE3__UTCL1_BUSY__SHIFT                                                                    0x3
5794 #define GRBM_STATUS_SE3__TCP_BUSY__SHIFT                                                                      0x4
5795 #define GRBM_STATUS_SE3__GL1CC_BUSY__SHIFT                                                                    0x5
5796 #define GRBM_STATUS_SE3__RMI_BUSY__SHIFT                                                                      0x15
5797 #define GRBM_STATUS_SE3__BCI_BUSY__SHIFT                                                                      0x16
5798 #define GRBM_STATUS_SE3__PA_BUSY__SHIFT                                                                       0x18
5799 #define GRBM_STATUS_SE3__TA_BUSY__SHIFT                                                                       0x19
5800 #define GRBM_STATUS_SE3__SX_BUSY__SHIFT                                                                       0x1a
5801 #define GRBM_STATUS_SE3__SPI_BUSY__SHIFT                                                                      0x1b
5802 #define GRBM_STATUS_SE3__SC_BUSY__SHIFT                                                                       0x1d
5803 #define GRBM_STATUS_SE3__DB_BUSY__SHIFT                                                                       0x1e
5804 #define GRBM_STATUS_SE3__CB_BUSY__SHIFT                                                                       0x1f
5805 #define GRBM_STATUS_SE3__DB_CLEAN_MASK                                                                        0x00000002L
5806 #define GRBM_STATUS_SE3__CB_CLEAN_MASK                                                                        0x00000004L
5807 #define GRBM_STATUS_SE3__UTCL1_BUSY_MASK                                                                      0x00000008L
5808 #define GRBM_STATUS_SE3__TCP_BUSY_MASK                                                                        0x00000010L
5809 #define GRBM_STATUS_SE3__GL1CC_BUSY_MASK                                                                      0x00000020L
5810 #define GRBM_STATUS_SE3__RMI_BUSY_MASK                                                                        0x00200000L
5811 #define GRBM_STATUS_SE3__BCI_BUSY_MASK                                                                        0x00400000L
5812 #define GRBM_STATUS_SE3__PA_BUSY_MASK                                                                         0x01000000L
5813 #define GRBM_STATUS_SE3__TA_BUSY_MASK                                                                         0x02000000L
5814 #define GRBM_STATUS_SE3__SX_BUSY_MASK                                                                         0x04000000L
5815 #define GRBM_STATUS_SE3__SPI_BUSY_MASK                                                                        0x08000000L
5816 #define GRBM_STATUS_SE3__SC_BUSY_MASK                                                                         0x20000000L
5817 #define GRBM_STATUS_SE3__DB_BUSY_MASK                                                                         0x40000000L
5818 #define GRBM_STATUS_SE3__CB_BUSY_MASK                                                                         0x80000000L
5819 //GRBM_PM_CNTL
5820 #define GRBM_PM_CNTL__PM_READY__SHIFT                                                                         0x0
5821 #define GRBM_PM_CNTL__PM_START__SHIFT                                                                         0x10
5822 #define GRBM_PM_CNTL__PM_READY_MASK                                                                           0x00000001L
5823 #define GRBM_PM_CNTL__PM_START_MASK                                                                           0x00010000L
5824 //GRBM_READ_ERROR
5825 #define GRBM_READ_ERROR__READ_ADDRESS__SHIFT                                                                  0x2
5826 #define GRBM_READ_ERROR__READ_PIPEID__SHIFT                                                                   0x14
5827 #define GRBM_READ_ERROR__READ_MEID__SHIFT                                                                     0x16
5828 #define GRBM_READ_ERROR__READ_ERROR__SHIFT                                                                    0x1f
5829 #define GRBM_READ_ERROR__READ_ADDRESS_MASK                                                                    0x0003FFFCL
5830 #define GRBM_READ_ERROR__READ_PIPEID_MASK                                                                     0x00300000L
5831 #define GRBM_READ_ERROR__READ_MEID_MASK                                                                       0x00C00000L
5832 #define GRBM_READ_ERROR__READ_ERROR_MASK                                                                      0x80000000L
5833 //GRBM_READ_ERROR2
5834 #define GRBM_READ_ERROR2__READ_REQUESTER_CPF__SHIFT                                                           0x10
5835 #define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT                                                           0x12
5836 #define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT                                                       0x13
5837 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT                                                   0x14
5838 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT                                                   0x15
5839 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT                                                   0x16
5840 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT                                                   0x17
5841 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT                                                      0x18
5842 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT                                                      0x19
5843 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT                                                      0x1a
5844 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT                                                      0x1b
5845 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT                                                      0x1c
5846 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT                                                      0x1d
5847 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT                                                      0x1e
5848 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT                                                      0x1f
5849 #define GRBM_READ_ERROR2__READ_REQUESTER_CPF_MASK                                                             0x00010000L
5850 #define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK                                                             0x00040000L
5851 #define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK                                                         0x00080000L
5852 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK                                                     0x00100000L
5853 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK                                                     0x00200000L
5854 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK                                                     0x00400000L
5855 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK                                                     0x00800000L
5856 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK                                                        0x01000000L
5857 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK                                                        0x02000000L
5858 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK                                                        0x04000000L
5859 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK                                                        0x08000000L
5860 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK                                                        0x10000000L
5861 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK                                                        0x20000000L
5862 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK                                                        0x40000000L
5863 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK                                                        0x80000000L
5864 //GRBM_INT_CNTL
5865 #define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT                                                                0x0
5866 #define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT                                                             0x13
5867 #define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK                                                                  0x00000001L
5868 #define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK                                                               0x00080000L
5869 //GRBM_TRAP_OP
5870 #define GRBM_TRAP_OP__RW__SHIFT                                                                               0x0
5871 #define GRBM_TRAP_OP__RW_MASK                                                                                 0x00000001L
5872 //GRBM_TRAP_ADDR
5873 #define GRBM_TRAP_ADDR__DATA__SHIFT                                                                           0x0
5874 #define GRBM_TRAP_ADDR__DATA_MASK                                                                             0x0003FFFFL
5875 //GRBM_TRAP_ADDR_MSK
5876 #define GRBM_TRAP_ADDR_MSK__DATA__SHIFT                                                                       0x0
5877 #define GRBM_TRAP_ADDR_MSK__DATA_MASK                                                                         0x0003FFFFL
5878 //GRBM_TRAP_WD
5879 #define GRBM_TRAP_WD__DATA__SHIFT                                                                             0x0
5880 #define GRBM_TRAP_WD__DATA_MASK                                                                               0xFFFFFFFFL
5881 //GRBM_TRAP_WD_MSK
5882 #define GRBM_TRAP_WD_MSK__DATA__SHIFT                                                                         0x0
5883 #define GRBM_TRAP_WD_MSK__DATA_MASK                                                                           0xFFFFFFFFL
5884 //GRBM_DSM_BYPASS
5885 #define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT                                                                   0x0
5886 #define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT                                                                     0x2
5887 #define GRBM_DSM_BYPASS__BYPASS_BITS_MASK                                                                     0x00000003L
5888 #define GRBM_DSM_BYPASS__BYPASS_EN_MASK                                                                       0x00000004L
5889 //GRBM_WRITE_ERROR
5890 #define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT                                                          0x0
5891 #define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT                                                                 0x2
5892 #define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT                                                                   0x5
5893 #define GRBM_WRITE_ERROR__WRITE_VF__SHIFT                                                                     0xc
5894 #define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT                                                                   0xd
5895 #define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT                                                                 0x14
5896 #define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT                                                                   0x16
5897 #define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT                                                                  0x1f
5898 #define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK                                                            0x00000001L
5899 #define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK                                                                   0x0000001CL
5900 #define GRBM_WRITE_ERROR__WRITE_VFID_MASK                                                                     0x000007E0L
5901 #define GRBM_WRITE_ERROR__WRITE_VF_MASK                                                                       0x00001000L
5902 #define GRBM_WRITE_ERROR__WRITE_VMID_MASK                                                                     0x0001E000L
5903 #define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK                                                                   0x00300000L
5904 #define GRBM_WRITE_ERROR__WRITE_MEID_MASK                                                                     0x00C00000L
5905 #define GRBM_WRITE_ERROR__WRITE_ERROR_MASK                                                                    0x80000000L
5906 //GRBM_IOV_ERROR
5907 #define GRBM_IOV_ERROR__IOV_ADDR__SHIFT                                                                       0x2
5908 #define GRBM_IOV_ERROR__IOV_VFID__SHIFT                                                                       0x14
5909 #define GRBM_IOV_ERROR__IOV_VF__SHIFT                                                                         0x1a
5910 #define GRBM_IOV_ERROR__IOV_OP__SHIFT                                                                         0x1b
5911 #define GRBM_IOV_ERROR__IOV_ERROR__SHIFT                                                                      0x1f
5912 #define GRBM_IOV_ERROR__IOV_ADDR_MASK                                                                         0x000FFFFCL
5913 #define GRBM_IOV_ERROR__IOV_VFID_MASK                                                                         0x03F00000L
5914 #define GRBM_IOV_ERROR__IOV_VF_MASK                                                                           0x04000000L
5915 #define GRBM_IOV_ERROR__IOV_OP_MASK                                                                           0x08000000L
5916 #define GRBM_IOV_ERROR__IOV_ERROR_MASK                                                                        0x80000000L
5917 //GRBM_CHIP_REVISION
5918 #define GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT                                                              0x0
5919 #define GRBM_CHIP_REVISION__CHIP_REVISION_MASK                                                                0x000000FFL
5920 //GRBM_GFX_CNTL
5921 #define GRBM_GFX_CNTL__PIPEID__SHIFT                                                                          0x0
5922 #define GRBM_GFX_CNTL__MEID__SHIFT                                                                            0x2
5923 #define GRBM_GFX_CNTL__VMID__SHIFT                                                                            0x4
5924 #define GRBM_GFX_CNTL__QUEUEID__SHIFT                                                                         0x8
5925 #define GRBM_GFX_CNTL__PIPEID_MASK                                                                            0x00000003L
5926 #define GRBM_GFX_CNTL__MEID_MASK                                                                              0x0000000CL
5927 #define GRBM_GFX_CNTL__VMID_MASK                                                                              0x000000F0L
5928 #define GRBM_GFX_CNTL__QUEUEID_MASK                                                                           0x00000700L
5929 //GRBM_IH_CREDIT
5930 #define GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT                                                                   0x0
5931 #define GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT                                                                   0x10
5932 #define GRBM_IH_CREDIT__CREDIT_VALUE_MASK                                                                     0x00000003L
5933 #define GRBM_IH_CREDIT__IH_CLIENT_ID_MASK                                                                     0x00FF0000L
5934 //GRBM_PWR_CNTL2
5935 #define GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT                                                               0x10
5936 #define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT                                                         0x14
5937 #define GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK                                                                 0x00010000L
5938 #define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK                                                           0x00100000L
5939 //GRBM_UTCL2_INVAL_RANGE_START
5940 #define GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT                                                             0x0
5941 #define GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK                                                               0x0003FFFFL
5942 //GRBM_UTCL2_INVAL_RANGE_END
5943 #define GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT                                                               0x0
5944 #define GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK                                                                 0x0003FFFFL
5945 //GRBM_IOV_READ_ERROR
5946 #define GRBM_IOV_READ_ERROR__IOV_ADDR__SHIFT                                                                  0x2
5947 #define GRBM_IOV_READ_ERROR__IOV_VFID__SHIFT                                                                  0x14
5948 #define GRBM_IOV_READ_ERROR__IOV_VF__SHIFT                                                                    0x1a
5949 #define GRBM_IOV_READ_ERROR__IOV_OP__SHIFT                                                                    0x1b
5950 #define GRBM_IOV_READ_ERROR__IOV_ERROR__SHIFT                                                                 0x1f
5951 #define GRBM_IOV_READ_ERROR__IOV_ADDR_MASK                                                                    0x000FFFFCL
5952 #define GRBM_IOV_READ_ERROR__IOV_VFID_MASK                                                                    0x03F00000L
5953 #define GRBM_IOV_READ_ERROR__IOV_VF_MASK                                                                      0x04000000L
5954 #define GRBM_IOV_READ_ERROR__IOV_OP_MASK                                                                      0x08000000L
5955 #define GRBM_IOV_READ_ERROR__IOV_ERROR_MASK                                                                   0x80000000L
5956 //GRBM_FENCE_RANGE0
5957 #define GRBM_FENCE_RANGE0__START__SHIFT                                                                       0x0
5958 #define GRBM_FENCE_RANGE0__END__SHIFT                                                                         0x10
5959 #define GRBM_FENCE_RANGE0__START_MASK                                                                         0x0000FFFFL
5960 #define GRBM_FENCE_RANGE0__END_MASK                                                                           0xFFFF0000L
5961 //GRBM_FENCE_RANGE1
5962 #define GRBM_FENCE_RANGE1__START__SHIFT                                                                       0x0
5963 #define GRBM_FENCE_RANGE1__END__SHIFT                                                                         0x10
5964 #define GRBM_FENCE_RANGE1__START_MASK                                                                         0x0000FFFFL
5965 #define GRBM_FENCE_RANGE1__END_MASK                                                                           0xFFFF0000L
5966 //GRBM_NOWHERE
5967 #define GRBM_NOWHERE__DATA__SHIFT                                                                             0x0
5968 #define GRBM_NOWHERE__DATA_MASK                                                                               0xFFFFFFFFL
5969 //GRBM_SCRATCH_REG0
5970 #define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT                                                                0x0
5971 #define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK                                                                  0xFFFFFFFFL
5972 //GRBM_SCRATCH_REG1
5973 #define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT                                                                0x0
5974 #define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK                                                                  0xFFFFFFFFL
5975 //GRBM_SCRATCH_REG2
5976 #define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT                                                                0x0
5977 #define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK                                                                  0xFFFFFFFFL
5978 //GRBM_SCRATCH_REG3
5979 #define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT                                                                0x0
5980 #define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK                                                                  0xFFFFFFFFL
5981 //GRBM_SCRATCH_REG4
5982 #define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT                                                                0x0
5983 #define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK                                                                  0xFFFFFFFFL
5984 //GRBM_SCRATCH_REG5
5985 #define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT                                                                0x0
5986 #define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK                                                                  0xFFFFFFFFL
5987 //GRBM_SCRATCH_REG6
5988 #define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT                                                                0x0
5989 #define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK                                                                  0xFFFFFFFFL
5990 //GRBM_SCRATCH_REG7
5991 #define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT                                                                0x0
5992 #define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK                                                                  0xFFFFFFFFL
5993 
5994 
5995 // addressBlock: gc_cpdec
5996 //CP_CPC_STATUS
5997 #define CP_CPC_STATUS__MEC1_BUSY__SHIFT                                                                       0x0
5998 #define CP_CPC_STATUS__MEC2_BUSY__SHIFT                                                                       0x1
5999 #define CP_CPC_STATUS__DC0_BUSY__SHIFT                                                                        0x2
6000 #define CP_CPC_STATUS__DC1_BUSY__SHIFT                                                                        0x3
6001 #define CP_CPC_STATUS__RCIU1_BUSY__SHIFT                                                                      0x4
6002 #define CP_CPC_STATUS__RCIU2_BUSY__SHIFT                                                                      0x5
6003 #define CP_CPC_STATUS__ROQ1_BUSY__SHIFT                                                                       0x6
6004 #define CP_CPC_STATUS__ROQ2_BUSY__SHIFT                                                                       0x7
6005 #define CP_CPC_STATUS__TCIU_BUSY__SHIFT                                                                       0xa
6006 #define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT                                                                0xb
6007 #define CP_CPC_STATUS__QU_BUSY__SHIFT                                                                         0xc
6008 #define CP_CPC_STATUS__UTCL2IU_BUSY__SHIFT                                                                    0xd
6009 #define CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT                                                               0xe
6010 #define CP_CPC_STATUS__GCRIU_BUSY__SHIFT                                                                      0xf
6011 #define CP_CPC_STATUS__MES_BUSY__SHIFT                                                                        0x10
6012 #define CP_CPC_STATUS__MES_SCRATCH_RAM_BUSY__SHIFT                                                            0x11
6013 #define CP_CPC_STATUS__RCIU3_BUSY__SHIFT                                                                      0x12
6014 #define CP_CPC_STATUS__MES_INSTRUCTION_CACHE_BUSY__SHIFT                                                      0x13
6015 #define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT                                                                    0x1d
6016 #define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT                                                                    0x1e
6017 #define CP_CPC_STATUS__CPC_BUSY__SHIFT                                                                        0x1f
6018 #define CP_CPC_STATUS__MEC1_BUSY_MASK                                                                         0x00000001L
6019 #define CP_CPC_STATUS__MEC2_BUSY_MASK                                                                         0x00000002L
6020 #define CP_CPC_STATUS__DC0_BUSY_MASK                                                                          0x00000004L
6021 #define CP_CPC_STATUS__DC1_BUSY_MASK                                                                          0x00000008L
6022 #define CP_CPC_STATUS__RCIU1_BUSY_MASK                                                                        0x00000010L
6023 #define CP_CPC_STATUS__RCIU2_BUSY_MASK                                                                        0x00000020L
6024 #define CP_CPC_STATUS__ROQ1_BUSY_MASK                                                                         0x00000040L
6025 #define CP_CPC_STATUS__ROQ2_BUSY_MASK                                                                         0x00000080L
6026 #define CP_CPC_STATUS__TCIU_BUSY_MASK                                                                         0x00000400L
6027 #define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK                                                                  0x00000800L
6028 #define CP_CPC_STATUS__QU_BUSY_MASK                                                                           0x00001000L
6029 #define CP_CPC_STATUS__UTCL2IU_BUSY_MASK                                                                      0x00002000L
6030 #define CP_CPC_STATUS__SAVE_RESTORE_BUSY_MASK                                                                 0x00004000L
6031 #define CP_CPC_STATUS__GCRIU_BUSY_MASK                                                                        0x00008000L
6032 #define CP_CPC_STATUS__MES_BUSY_MASK                                                                          0x00010000L
6033 #define CP_CPC_STATUS__MES_SCRATCH_RAM_BUSY_MASK                                                              0x00020000L
6034 #define CP_CPC_STATUS__RCIU3_BUSY_MASK                                                                        0x00040000L
6035 #define CP_CPC_STATUS__MES_INSTRUCTION_CACHE_BUSY_MASK                                                        0x00080000L
6036 #define CP_CPC_STATUS__CPG_CPC_BUSY_MASK                                                                      0x20000000L
6037 #define CP_CPC_STATUS__CPF_CPC_BUSY_MASK                                                                      0x40000000L
6038 #define CP_CPC_STATUS__CPC_BUSY_MASK                                                                          0x80000000L
6039 //CP_CPC_BUSY_STAT
6040 #define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT                                                               0x0
6041 #define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT                                                          0x1
6042 #define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT                                                              0x2
6043 #define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT                                                            0x3
6044 #define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT                                                          0x4
6045 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT                                                           0x5
6046 #define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT                                                           0x6
6047 #define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT                                                                 0x7
6048 #define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT                                                                0x8
6049 #define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT                                                      0x9
6050 #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT                                                              0xa
6051 #define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT                                                              0xb
6052 #define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT                                                              0xc
6053 #define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT                                                              0xd
6054 #define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT                                                               0x10
6055 #define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT                                                          0x11
6056 #define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT                                                              0x12
6057 #define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT                                                            0x13
6058 #define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT                                                          0x14
6059 #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT                                                           0x15
6060 #define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT                                                           0x16
6061 #define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT                                                                 0x17
6062 #define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT                                                                0x18
6063 #define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT                                                      0x19
6064 #define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT                                                              0x1a
6065 #define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT                                                              0x1b
6066 #define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT                                                              0x1c
6067 #define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT                                                              0x1d
6068 #define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK                                                                 0x00000001L
6069 #define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK                                                            0x00000002L
6070 #define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK                                                                0x00000004L
6071 #define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK                                                              0x00000008L
6072 #define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK                                                            0x00000010L
6073 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK                                                             0x00000020L
6074 #define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK                                                             0x00000040L
6075 #define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK                                                                   0x00000080L
6076 #define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK                                                                  0x00000100L
6077 #define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK                                                        0x00000200L
6078 #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK                                                                0x00000400L
6079 #define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK                                                                0x00000800L
6080 #define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK                                                                0x00001000L
6081 #define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK                                                                0x00002000L
6082 #define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK                                                                 0x00010000L
6083 #define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK                                                            0x00020000L
6084 #define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK                                                                0x00040000L
6085 #define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK                                                              0x00080000L
6086 #define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK                                                            0x00100000L
6087 #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK                                                             0x00200000L
6088 #define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK                                                             0x00400000L
6089 #define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK                                                                   0x00800000L
6090 #define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK                                                                  0x01000000L
6091 #define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK                                                        0x02000000L
6092 #define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK                                                                0x04000000L
6093 #define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK                                                                0x08000000L
6094 #define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK                                                                0x10000000L
6095 #define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK                                                                0x20000000L
6096 //CP_CPC_STALLED_STAT1
6097 #define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT                                                       0x3
6098 #define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT                                                      0x4
6099 #define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT                                                       0x6
6100 #define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT                                                     0x8
6101 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT                                                        0x9
6102 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT                                                   0xa
6103 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT                                                    0xd
6104 #define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT                                                     0x10
6105 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT                                                        0x11
6106 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT                                                   0x12
6107 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT                                                    0x15
6108 #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT                                                  0x16
6109 #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT                                                  0x17
6110 #define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT                                                   0x18
6111 #define CP_CPC_STALLED_STAT1__GCRIU_WAITING_ON_FREE__SHIFT                                                    0x19
6112 #define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK                                                         0x00000008L
6113 #define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK                                                        0x00000010L
6114 #define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK                                                         0x00000040L
6115 #define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK                                                       0x00000100L
6116 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK                                                          0x00000200L
6117 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK                                                     0x00000400L
6118 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK                                                      0x00002000L
6119 #define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK                                                       0x00010000L
6120 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK                                                          0x00020000L
6121 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK                                                     0x00040000L
6122 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK                                                      0x00200000L
6123 #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK                                                    0x00400000L
6124 #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK                                                    0x00800000L
6125 #define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK                                                     0x01000000L
6126 #define CP_CPC_STALLED_STAT1__GCRIU_WAITING_ON_FREE_MASK                                                      0x02000000L
6127 //CP_CPF_STATUS
6128 #define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT                                                              0x0
6129 #define CP_CPF_STATUS__CSF_BUSY__SHIFT                                                                        0x1
6130 #define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT                                                                  0x4
6131 #define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT                                                                   0x5
6132 #define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT                                                              0x6
6133 #define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT                                                              0x7
6134 #define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT                                                                  0x8
6135 #define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT                                                                0x9
6136 #define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT                                                           0xa
6137 #define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT                                                           0xb
6138 #define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT                                                                  0xc
6139 #define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT                                                                  0xd
6140 #define CP_CPF_STATUS__TCIU_BUSY__SHIFT                                                                       0xe
6141 #define CP_CPF_STATUS__HQD_BUSY__SHIFT                                                                        0xf
6142 #define CP_CPF_STATUS__PRT_BUSY__SHIFT                                                                        0x10
6143 #define CP_CPF_STATUS__UTCL2IU_BUSY__SHIFT                                                                    0x11
6144 #define CP_CPF_STATUS__RCIU_BUSY__SHIFT                                                                       0x12
6145 #define CP_CPF_STATUS__RCIU_GFX_BUSY__SHIFT                                                                   0x13
6146 #define CP_CPF_STATUS__RCIU_CMP_BUSY__SHIFT                                                                   0x14
6147 #define CP_CPF_STATUS__ROQ_DATA_BUSY__SHIFT                                                                   0x15
6148 #define CP_CPF_STATUS__ROQ_CE_DATA_BUSY__SHIFT                                                                0x16
6149 #define CP_CPF_STATUS__GCRIU_BUSY__SHIFT                                                                      0x17
6150 #define CP_CPF_STATUS__MES_HQD_BUSY__SHIFT                                                                    0x18
6151 #define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT                                                                    0x1a
6152 #define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT                                                                    0x1b
6153 #define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT                                                              0x1c
6154 #define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT                                                                    0x1e
6155 #define CP_CPF_STATUS__CPF_BUSY__SHIFT                                                                        0x1f
6156 #define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK                                                                0x00000001L
6157 #define CP_CPF_STATUS__CSF_BUSY_MASK                                                                          0x00000002L
6158 #define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK                                                                    0x00000010L
6159 #define CP_CPF_STATUS__ROQ_RING_BUSY_MASK                                                                     0x00000020L
6160 #define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK                                                                0x00000040L
6161 #define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK                                                                0x00000080L
6162 #define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK                                                                    0x00000100L
6163 #define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK                                                                  0x00000200L
6164 #define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK                                                             0x00000400L
6165 #define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK                                                             0x00000800L
6166 #define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK                                                                    0x00001000L
6167 #define CP_CPF_STATUS__INTERRUPT_BUSY_MASK                                                                    0x00002000L
6168 #define CP_CPF_STATUS__TCIU_BUSY_MASK                                                                         0x00004000L
6169 #define CP_CPF_STATUS__HQD_BUSY_MASK                                                                          0x00008000L
6170 #define CP_CPF_STATUS__PRT_BUSY_MASK                                                                          0x00010000L
6171 #define CP_CPF_STATUS__UTCL2IU_BUSY_MASK                                                                      0x00020000L
6172 #define CP_CPF_STATUS__RCIU_BUSY_MASK                                                                         0x00040000L
6173 #define CP_CPF_STATUS__RCIU_GFX_BUSY_MASK                                                                     0x00080000L
6174 #define CP_CPF_STATUS__RCIU_CMP_BUSY_MASK                                                                     0x00100000L
6175 #define CP_CPF_STATUS__ROQ_DATA_BUSY_MASK                                                                     0x00200000L
6176 #define CP_CPF_STATUS__ROQ_CE_DATA_BUSY_MASK                                                                  0x00400000L
6177 #define CP_CPF_STATUS__GCRIU_BUSY_MASK                                                                        0x00800000L
6178 #define CP_CPF_STATUS__MES_HQD_BUSY_MASK                                                                      0x01000000L
6179 #define CP_CPF_STATUS__CPF_GFX_BUSY_MASK                                                                      0x04000000L
6180 #define CP_CPF_STATUS__CPF_CMP_BUSY_MASK                                                                      0x08000000L
6181 #define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK                                                                0x30000000L
6182 #define CP_CPF_STATUS__CPC_CPF_BUSY_MASK                                                                      0x40000000L
6183 #define CP_CPF_STATUS__CPF_BUSY_MASK                                                                          0x80000000L
6184 //CP_CPF_BUSY_STAT
6185 #define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT                                                            0x0
6186 #define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT                                                                0x1
6187 #define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT                                                           0x2
6188 #define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT                                                           0x3
6189 #define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT                                                               0x4
6190 #define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT                                                            0x5
6191 #define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT                                                            0x6
6192 #define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT                                                             0x7
6193 #define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT                                                               0x8
6194 #define CP_CPF_BUSY_STAT__CSF_DATA_BUSY__SHIFT                                                                0x9
6195 #define CP_CPF_BUSY_STAT__CSF_CE_DATA_BUSY__SHIFT                                                             0xa
6196 #define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT                                                      0xb
6197 #define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT                                                            0xc
6198 #define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT                                                            0xd
6199 #define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT                                                         0xe
6200 #define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT                                                      0xf
6201 #define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT                                                    0x10
6202 #define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT                                                             0x11
6203 #define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT                                                          0x12
6204 #define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT                                                          0x13
6205 #define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT                                                          0x14
6206 #define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT                                                         0x15
6207 #define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT                                                       0x16
6208 #define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT                                                         0x17
6209 #define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT                                                           0x18
6210 #define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT                                                             0x19
6211 #define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT                                                              0x1a
6212 #define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT                                                              0x1b
6213 #define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT                                                              0x1c
6214 #define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT                                                           0x1d
6215 #define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT                                                                  0x1e
6216 #define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT                                                                  0x1f
6217 #define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK                                                              0x00000001L
6218 #define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK                                                                  0x00000002L
6219 #define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK                                                             0x00000004L
6220 #define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK                                                             0x00000008L
6221 #define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK                                                                 0x00000010L
6222 #define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK                                                              0x00000020L
6223 #define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK                                                              0x00000040L
6224 #define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK                                                               0x00000080L
6225 #define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK                                                                 0x00000100L
6226 #define CP_CPF_BUSY_STAT__CSF_DATA_BUSY_MASK                                                                  0x00000200L
6227 #define CP_CPF_BUSY_STAT__CSF_CE_DATA_BUSY_MASK                                                               0x00000400L
6228 #define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK                                                        0x00000800L
6229 #define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK                                                              0x00001000L
6230 #define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK                                                              0x00002000L
6231 #define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK                                                           0x00004000L
6232 #define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK                                                        0x00008000L
6233 #define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK                                                      0x00010000L
6234 #define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK                                                               0x00020000L
6235 #define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK                                                            0x00040000L
6236 #define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK                                                            0x00080000L
6237 #define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK                                                            0x00100000L
6238 #define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK                                                           0x00200000L
6239 #define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK                                                         0x00400000L
6240 #define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK                                                           0x00800000L
6241 #define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK                                                             0x01000000L
6242 #define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK                                                               0x02000000L
6243 #define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK                                                                0x04000000L
6244 #define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK                                                                0x08000000L
6245 #define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK                                                                0x10000000L
6246 #define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK                                                             0x20000000L
6247 #define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK                                                                    0x40000000L
6248 #define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK                                                                    0x80000000L
6249 //CP_CPF_STALLED_STAT1
6250 #define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT                                                       0x0
6251 #define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT                                                      0x1
6252 #define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT                                                      0x2
6253 #define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT                                                      0x3
6254 #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT                                                     0x5
6255 #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT                                                     0x6
6256 #define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT                                                  0x7
6257 #define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT                                                  0x8
6258 #define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS__SHIFT                                               0x9
6259 #define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT                                               0xa
6260 #define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE__SHIFT                                                     0xb
6261 #define CP_CPF_STALLED_STAT1__DATA_FETCHING_DATA__SHIFT                                                       0xc
6262 #define CP_CPF_STALLED_STAT1__GCRIU_WAIT_ON_FREE__SHIFT                                                       0xd
6263 #define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK                                                         0x00000001L
6264 #define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK                                                        0x00000002L
6265 #define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK                                                        0x00000004L
6266 #define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK                                                        0x00000008L
6267 #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK                                                       0x00000020L
6268 #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK                                                       0x00000040L
6269 #define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK                                                    0x00000080L
6270 #define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK                                                    0x00000100L
6271 #define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS_MASK                                                 0x00000200L
6272 #define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS_MASK                                                 0x00000400L
6273 #define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE_MASK                                                       0x00000800L
6274 #define CP_CPF_STALLED_STAT1__DATA_FETCHING_DATA_MASK                                                         0x00001000L
6275 #define CP_CPF_STALLED_STAT1__GCRIU_WAIT_ON_FREE_MASK                                                         0x00002000L
6276 //CP_CPC_BUSY_STAT2
6277 #define CP_CPC_BUSY_STAT2__MES_LOAD_BUSY__SHIFT                                                               0x0
6278 #define CP_CPC_BUSY_STAT2__MES_MUTEX_BUSY__SHIFT                                                              0x2
6279 #define CP_CPC_BUSY_STAT2__MES_MESSAGE_BUSY__SHIFT                                                            0x3
6280 #define CP_CPC_BUSY_STAT2__MES_TC_BUSY__SHIFT                                                                 0x7
6281 #define CP_CPC_BUSY_STAT2__MES_DMA_BUSY__SHIFT                                                                0x8
6282 #define CP_CPC_BUSY_STAT2__MES_PIPE0_BUSY__SHIFT                                                              0xa
6283 #define CP_CPC_BUSY_STAT2__MES_PIPE1_BUSY__SHIFT                                                              0xb
6284 #define CP_CPC_BUSY_STAT2__MES_PIPE2_BUSY__SHIFT                                                              0xc
6285 #define CP_CPC_BUSY_STAT2__MES_PIPE3_BUSY__SHIFT                                                              0xd
6286 #define CP_CPC_BUSY_STAT2__MES_LOAD_BUSY_MASK                                                                 0x00000001L
6287 #define CP_CPC_BUSY_STAT2__MES_MUTEX_BUSY_MASK                                                                0x00000004L
6288 #define CP_CPC_BUSY_STAT2__MES_MESSAGE_BUSY_MASK                                                              0x00000008L
6289 #define CP_CPC_BUSY_STAT2__MES_TC_BUSY_MASK                                                                   0x00000080L
6290 #define CP_CPC_BUSY_STAT2__MES_DMA_BUSY_MASK                                                                  0x00000100L
6291 #define CP_CPC_BUSY_STAT2__MES_PIPE0_BUSY_MASK                                                                0x00000400L
6292 #define CP_CPC_BUSY_STAT2__MES_PIPE1_BUSY_MASK                                                                0x00000800L
6293 #define CP_CPC_BUSY_STAT2__MES_PIPE2_BUSY_MASK                                                                0x00001000L
6294 #define CP_CPC_BUSY_STAT2__MES_PIPE3_BUSY_MASK                                                                0x00002000L
6295 //CP_CPC_GRBM_FREE_COUNT
6296 #define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT                                                             0x0
6297 #define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK                                                               0x0000003FL
6298 //CP_MEC_CNTL
6299 #define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT                                                               0x10
6300 #define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT                                                               0x11
6301 #define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT                                                               0x12
6302 #define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT                                                               0x13
6303 #define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT                                                               0x14
6304 #define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT                                                               0x15
6305 #define CP_MEC_CNTL__MEC_ME2_PIPE2_RESET__SHIFT                                                               0x16
6306 #define CP_MEC_CNTL__MEC_ME2_PIPE3_RESET__SHIFT                                                               0x17
6307 #define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT                                                             0x1b
6308 #define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT                                                                      0x1c
6309 #define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT                                                                      0x1d
6310 #define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT                                                                      0x1e
6311 #define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT                                                                      0x1f
6312 #define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK                                                                 0x00010000L
6313 #define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK                                                                 0x00020000L
6314 #define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK                                                                 0x00040000L
6315 #define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK                                                                 0x00080000L
6316 #define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK                                                                 0x00100000L
6317 #define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK                                                                 0x00200000L
6318 #define CP_MEC_CNTL__MEC_ME2_PIPE2_RESET_MASK                                                                 0x00400000L
6319 #define CP_MEC_CNTL__MEC_ME2_PIPE3_RESET_MASK                                                                 0x00800000L
6320 #define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK                                                               0x08000000L
6321 #define CP_MEC_CNTL__MEC_ME2_HALT_MASK                                                                        0x10000000L
6322 #define CP_MEC_CNTL__MEC_ME2_STEP_MASK                                                                        0x20000000L
6323 #define CP_MEC_CNTL__MEC_ME1_HALT_MASK                                                                        0x40000000L
6324 #define CP_MEC_CNTL__MEC_ME1_STEP_MASK                                                                        0x80000000L
6325 //CP_MEC_ME1_HEADER_DUMP
6326 #define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT                                                            0x0
6327 #define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK                                                              0xFFFFFFFFL
6328 //CP_MEC_ME2_HEADER_DUMP
6329 #define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT                                                            0x0
6330 #define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK                                                              0xFFFFFFFFL
6331 //CP_CPC_SCRATCH_INDEX
6332 #define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT                                                            0x0
6333 #define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT                                                 0x1f
6334 #define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK                                                              0x000001FFL
6335 #define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK                                                   0x80000000L
6336 //CP_CPC_SCRATCH_DATA
6337 #define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT                                                              0x0
6338 #define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK                                                                0xFFFFFFFFL
6339 //CP_CPF_GRBM_FREE_COUNT
6340 #define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT__SHIFT                                                             0x0
6341 #define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT_MASK                                                               0x00000007L
6342 //CP_CPF_BUSY_STAT2
6343 #define CP_CPF_BUSY_STAT2__MES_HQD_DISPATCH_BUSY__SHIFT                                                       0xc
6344 #define CP_CPF_BUSY_STAT2__MES_HQD_DMA_OFFLOAD_BUSY__SHIFT                                                    0xe
6345 #define CP_CPF_BUSY_STAT2__MES_HQD_MESSAGE_BUSY__SHIFT                                                        0x11
6346 #define CP_CPF_BUSY_STAT2__MES_HQD_PQ_FETCHER_BUSY__SHIFT                                                     0x12
6347 #define CP_CPF_BUSY_STAT2__MES_HQD_CONSUMED_RPTR_BUSY__SHIFT                                                  0x16
6348 #define CP_CPF_BUSY_STAT2__MES_HQD_FETCHER_ARB_BUSY__SHIFT                                                    0x17
6349 #define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_ALIGN_BUSY__SHIFT                                                      0x18
6350 #define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_PQ_BUSY__SHIFT                                                         0x1b
6351 #define CP_CPF_BUSY_STAT2__MES_HQD_PQ_BUSY__SHIFT                                                             0x1e
6352 #define CP_CPF_BUSY_STAT2__MES_HQD_DISPATCH_BUSY_MASK                                                         0x00001000L
6353 #define CP_CPF_BUSY_STAT2__MES_HQD_DMA_OFFLOAD_BUSY_MASK                                                      0x00004000L
6354 #define CP_CPF_BUSY_STAT2__MES_HQD_MESSAGE_BUSY_MASK                                                          0x00020000L
6355 #define CP_CPF_BUSY_STAT2__MES_HQD_PQ_FETCHER_BUSY_MASK                                                       0x00040000L
6356 #define CP_CPF_BUSY_STAT2__MES_HQD_CONSUMED_RPTR_BUSY_MASK                                                    0x00400000L
6357 #define CP_CPF_BUSY_STAT2__MES_HQD_FETCHER_ARB_BUSY_MASK                                                      0x00800000L
6358 #define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_ALIGN_BUSY_MASK                                                        0x01000000L
6359 #define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_PQ_BUSY_MASK                                                           0x08000000L
6360 #define CP_CPF_BUSY_STAT2__MES_HQD_PQ_BUSY_MASK                                                               0x40000000L
6361 //CP_CPC_HALT_HYST_COUNT
6362 #define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT                                                                  0x0
6363 #define CP_CPC_HALT_HYST_COUNT__COUNT_MASK                                                                    0x0000000FL
6364 //CP_CE_COMPARE_COUNT
6365 #define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT                                                             0x0
6366 #define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK                                                               0xFFFFFFFFL
6367 //CP_CE_DE_COUNT
6368 #define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT                                                              0x0
6369 #define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK                                                                0xFFFFFFFFL
6370 //CP_DE_CE_COUNT
6371 #define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT                                                             0x0
6372 #define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK                                                               0xFFFFFFFFL
6373 //CP_DE_LAST_INVAL_COUNT
6374 #define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT                                                       0x0
6375 #define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK                                                         0xFFFFFFFFL
6376 //CP_DE_DE_COUNT
6377 #define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT                                                              0x0
6378 #define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK                                                                0xFFFFFFFFL
6379 //CP_STALLED_STAT3
6380 #define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT                                                     0x0
6381 #define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT                                        0x1
6382 #define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT                                     0x2
6383 #define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT                                                       0x3
6384 #define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT                                                       0x4
6385 #define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT                                                      0x5
6386 #define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT                                                0x6
6387 #define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT                                                 0x7
6388 #define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT                                                    0xa
6389 #define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT                                                 0xb
6390 #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT                                                     0xc
6391 #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT                                           0xd
6392 #define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT                                                         0xe
6393 #define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT                                                         0xf
6394 #define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT                                                  0x10
6395 #define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT                                                0x11
6396 #define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE__SHIFT                                                      0x12
6397 #define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS__SHIFT                                                      0x13
6398 #define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS__SHIFT                                                       0x14
6399 #define CP_STALLED_STAT3__GCRIU_WAITING_ON_FREE__SHIFT                                                        0x15
6400 #define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK                                                       0x00000001L
6401 #define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK                                          0x00000002L
6402 #define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK                                       0x00000004L
6403 #define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK                                                         0x00000008L
6404 #define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK                                                         0x00000010L
6405 #define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK                                                        0x00000020L
6406 #define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK                                                  0x00000040L
6407 #define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK                                                   0x00000080L
6408 #define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK                                                      0x00000400L
6409 #define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK                                                   0x00000800L
6410 #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK                                                       0x00001000L
6411 #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK                                             0x00002000L
6412 #define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK                                                           0x00004000L
6413 #define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK                                                           0x00008000L
6414 #define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK                                                    0x00010000L
6415 #define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK                                                  0x00020000L
6416 #define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE_MASK                                                        0x00040000L
6417 #define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS_MASK                                                        0x00080000L
6418 #define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS_MASK                                                         0x00100000L
6419 #define CP_STALLED_STAT3__GCRIU_WAITING_ON_FREE_MASK                                                          0x00200000L
6420 //CP_STALLED_STAT1
6421 #define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT                                                   0x0
6422 #define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT                                                   0x2
6423 #define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT                                                 0x4
6424 #define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT                                                 0xa
6425 #define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT                                                 0xb
6426 #define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT                                                  0xc
6427 #define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT                                                0xd
6428 #define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT                                                   0xe
6429 #define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT                                                  0xf
6430 #define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT                                                     0x17
6431 #define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT                                                    0x18
6432 #define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT                                                     0x19
6433 #define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT                                                      0x1a
6434 #define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT                                                     0x1b
6435 #define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT                                                  0x1c
6436 #define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT                                                 0x1d
6437 #define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK                                                     0x00000001L
6438 #define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK                                                     0x00000004L
6439 #define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK                                                   0x00000010L
6440 #define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK                                                   0x00000400L
6441 #define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK                                                   0x00000800L
6442 #define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK                                                    0x00001000L
6443 #define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK                                                  0x00002000L
6444 #define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK                                                     0x00004000L
6445 #define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK                                                    0x00008000L
6446 #define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK                                                       0x00800000L
6447 #define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK                                                      0x01000000L
6448 #define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK                                                       0x02000000L
6449 #define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK                                                        0x04000000L
6450 #define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK                                                       0x08000000L
6451 #define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK                                                    0x10000000L
6452 #define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK                                                   0x20000000L
6453 //CP_STALLED_STAT2
6454 #define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT                                                    0x0
6455 #define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT                                                    0x1
6456 #define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT                                                   0x2
6457 #define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT                                                    0x4
6458 #define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT                                                        0x5
6459 #define CP_STALLED_STAT2__PFP_TO_MEQ_DDID_NOT_RDY_TO_RCV__SHIFT                                               0x6
6460 #define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT                                                   0x8
6461 #define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT                                                        0x9
6462 #define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT                                                      0xa
6463 #define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT                                                     0xb
6464 #define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT                                                       0xc
6465 #define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT                                                   0xd
6466 #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT                                                     0xe
6467 #define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT                                                  0xf
6468 #define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT                                                     0x10
6469 #define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT                                                     0x11
6470 #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT                                                     0x12
6471 #define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT                                                 0x13
6472 #define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT                                               0x14
6473 #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT                                                  0x15
6474 #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT                                                   0x16
6475 #define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT                                                0x17
6476 #define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT                                                   0x18
6477 #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT                                                   0x19
6478 #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT                                                   0x1a
6479 #define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT                                                    0x1b
6480 #define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT                                                      0x1c
6481 #define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT                                              0x1d
6482 #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT                                                   0x1e
6483 #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT                                                    0x1f
6484 #define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK                                                      0x00000001L
6485 #define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK                                                      0x00000002L
6486 #define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK                                                     0x00000004L
6487 #define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK                                                      0x00000010L
6488 #define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK                                                          0x00000020L
6489 #define CP_STALLED_STAT2__PFP_TO_MEQ_DDID_NOT_RDY_TO_RCV_MASK                                                 0x00000040L
6490 #define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK                                                     0x00000100L
6491 #define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK                                                          0x00000200L
6492 #define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK                                                        0x00000400L
6493 #define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK                                                       0x00000800L
6494 #define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK                                                         0x00001000L
6495 #define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK                                                     0x00002000L
6496 #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK                                                       0x00004000L
6497 #define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK                                                    0x00008000L
6498 #define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK                                                       0x00010000L
6499 #define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK                                                       0x00020000L
6500 #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK                                                       0x00040000L
6501 #define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK                                                   0x00080000L
6502 #define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK                                                 0x00100000L
6503 #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK                                                    0x00200000L
6504 #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK                                                     0x00400000L
6505 #define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK                                                  0x00800000L
6506 #define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK                                                     0x01000000L
6507 #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK                                                     0x02000000L
6508 #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK                                                     0x04000000L
6509 #define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK                                                      0x08000000L
6510 #define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK                                                        0x10000000L
6511 #define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK                                                0x20000000L
6512 #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK                                                     0x40000000L
6513 #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK                                                      0x80000000L
6514 //CP_BUSY_STAT
6515 #define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT                                                                0x0
6516 #define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT                                                               0x6
6517 #define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT                                                              0x7
6518 #define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT                                                               0x8
6519 #define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT                                                                    0x9
6520 #define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT                                                                     0xa
6521 #define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT                                                            0xc
6522 #define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT                                                           0xd
6523 #define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT                                                             0xe
6524 #define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT                                                                 0xf
6525 #define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT                                                                   0x11
6526 #define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT                                                                    0x12
6527 #define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT                                                                    0x13
6528 #define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT                                                                  0x14
6529 #define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT                                                                     0x15
6530 #define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT                                                               0x16
6531 #define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK                                                                  0x00000001L
6532 #define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK                                                                 0x00000040L
6533 #define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK                                                                0x00000080L
6534 #define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK                                                                 0x00000100L
6535 #define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK                                                                      0x00000200L
6536 #define CP_BUSY_STAT__RCIU_ME_BUSY_MASK                                                                       0x00000400L
6537 #define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK                                                              0x00001000L
6538 #define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK                                                             0x00002000L
6539 #define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK                                                               0x00004000L
6540 #define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK                                                                   0x00008000L
6541 #define CP_BUSY_STAT__ME_PARSER_BUSY_MASK                                                                     0x00020000L
6542 #define CP_BUSY_STAT__EOP_DONE_BUSY_MASK                                                                      0x00040000L
6543 #define CP_BUSY_STAT__STRM_OUT_BUSY_MASK                                                                      0x00080000L
6544 #define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK                                                                    0x00100000L
6545 #define CP_BUSY_STAT__RCIU_CE_BUSY_MASK                                                                       0x00200000L
6546 #define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK                                                                 0x00400000L
6547 //CP_STAT
6548 #define CP_STAT__ROQ_DB_BUSY__SHIFT                                                                           0x5
6549 #define CP_STAT__ROQ_CE_DB_BUSY__SHIFT                                                                        0x6
6550 #define CP_STAT__ROQ_RING_BUSY__SHIFT                                                                         0x9
6551 #define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT                                                                    0xa
6552 #define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT                                                                    0xb
6553 #define CP_STAT__ROQ_STATE_BUSY__SHIFT                                                                        0xc
6554 #define CP_STAT__DC_BUSY__SHIFT                                                                               0xd
6555 #define CP_STAT__UTCL2IU_BUSY__SHIFT                                                                          0xe
6556 #define CP_STAT__PFP_BUSY__SHIFT                                                                              0xf
6557 #define CP_STAT__MEQ_BUSY__SHIFT                                                                              0x10
6558 #define CP_STAT__ME_BUSY__SHIFT                                                                               0x11
6559 #define CP_STAT__QUERY_BUSY__SHIFT                                                                            0x12
6560 #define CP_STAT__SEMAPHORE_BUSY__SHIFT                                                                        0x13
6561 #define CP_STAT__INTERRUPT_BUSY__SHIFT                                                                        0x14
6562 #define CP_STAT__SURFACE_SYNC_BUSY__SHIFT                                                                     0x15
6563 #define CP_STAT__DMA_BUSY__SHIFT                                                                              0x16
6564 #define CP_STAT__RCIU_BUSY__SHIFT                                                                             0x17
6565 #define CP_STAT__SCRATCH_RAM_BUSY__SHIFT                                                                      0x18
6566 #define CP_STAT__GCRIU_BUSY__SHIFT                                                                            0x19
6567 #define CP_STAT__CE_BUSY__SHIFT                                                                               0x1a
6568 #define CP_STAT__TCIU_BUSY__SHIFT                                                                             0x1b
6569 #define CP_STAT__ROQ_CE_RING_BUSY__SHIFT                                                                      0x1c
6570 #define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT                                                                 0x1d
6571 #define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT                                                                 0x1e
6572 #define CP_STAT__CP_BUSY__SHIFT                                                                               0x1f
6573 #define CP_STAT__ROQ_DB_BUSY_MASK                                                                             0x00000020L
6574 #define CP_STAT__ROQ_CE_DB_BUSY_MASK                                                                          0x00000040L
6575 #define CP_STAT__ROQ_RING_BUSY_MASK                                                                           0x00000200L
6576 #define CP_STAT__ROQ_INDIRECT1_BUSY_MASK                                                                      0x00000400L
6577 #define CP_STAT__ROQ_INDIRECT2_BUSY_MASK                                                                      0x00000800L
6578 #define CP_STAT__ROQ_STATE_BUSY_MASK                                                                          0x00001000L
6579 #define CP_STAT__DC_BUSY_MASK                                                                                 0x00002000L
6580 #define CP_STAT__UTCL2IU_BUSY_MASK                                                                            0x00004000L
6581 #define CP_STAT__PFP_BUSY_MASK                                                                                0x00008000L
6582 #define CP_STAT__MEQ_BUSY_MASK                                                                                0x00010000L
6583 #define CP_STAT__ME_BUSY_MASK                                                                                 0x00020000L
6584 #define CP_STAT__QUERY_BUSY_MASK                                                                              0x00040000L
6585 #define CP_STAT__SEMAPHORE_BUSY_MASK                                                                          0x00080000L
6586 #define CP_STAT__INTERRUPT_BUSY_MASK                                                                          0x00100000L
6587 #define CP_STAT__SURFACE_SYNC_BUSY_MASK                                                                       0x00200000L
6588 #define CP_STAT__DMA_BUSY_MASK                                                                                0x00400000L
6589 #define CP_STAT__RCIU_BUSY_MASK                                                                               0x00800000L
6590 #define CP_STAT__SCRATCH_RAM_BUSY_MASK                                                                        0x01000000L
6591 #define CP_STAT__GCRIU_BUSY_MASK                                                                              0x02000000L
6592 #define CP_STAT__CE_BUSY_MASK                                                                                 0x04000000L
6593 #define CP_STAT__TCIU_BUSY_MASK                                                                               0x08000000L
6594 #define CP_STAT__ROQ_CE_RING_BUSY_MASK                                                                        0x10000000L
6595 #define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK                                                                   0x20000000L
6596 #define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK                                                                   0x40000000L
6597 #define CP_STAT__CP_BUSY_MASK                                                                                 0x80000000L
6598 //CP_ME_HEADER_DUMP
6599 #define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT                                                              0x0
6600 #define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK                                                                0xFFFFFFFFL
6601 //CP_PFP_HEADER_DUMP
6602 #define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT                                                            0x0
6603 #define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK                                                              0xFFFFFFFFL
6604 //CP_GRBM_FREE_COUNT
6605 #define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT                                                                 0x0
6606 #define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT                                                             0x8
6607 #define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT                                                             0x10
6608 #define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK                                                                   0x0000003FL
6609 #define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK                                                               0x00003F00L
6610 #define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK                                                               0x003F0000L
6611 //CP_CE_HEADER_DUMP
6612 #define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT                                                              0x0
6613 #define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK                                                                0xFFFFFFFFL
6614 //CP_PFP_INSTR_PNTR
6615 #define CP_PFP_INSTR_PNTR__INSTR_PNTR__SHIFT                                                                  0x0
6616 #define CP_PFP_INSTR_PNTR__INSTR_PNTR_MASK                                                                    0x0000FFFFL
6617 //CP_ME_INSTR_PNTR
6618 #define CP_ME_INSTR_PNTR__INSTR_PNTR__SHIFT                                                                   0x0
6619 #define CP_ME_INSTR_PNTR__INSTR_PNTR_MASK                                                                     0x0000FFFFL
6620 //CP_CE_INSTR_PNTR
6621 #define CP_CE_INSTR_PNTR__INSTR_PNTR__SHIFT                                                                   0x0
6622 #define CP_CE_INSTR_PNTR__INSTR_PNTR_MASK                                                                     0x0000FFFFL
6623 //CP_MEC1_INSTR_PNTR
6624 #define CP_MEC1_INSTR_PNTR__INSTR_PNTR__SHIFT                                                                 0x0
6625 #define CP_MEC1_INSTR_PNTR__INSTR_PNTR_MASK                                                                   0x0000FFFFL
6626 //CP_MEC2_INSTR_PNTR
6627 #define CP_MEC2_INSTR_PNTR__INSTR_PNTR__SHIFT                                                                 0x0
6628 #define CP_MEC2_INSTR_PNTR__INSTR_PNTR_MASK                                                                   0x0000FFFFL
6629 //CP_CSF_STAT
6630 #define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT                                                              0x8
6631 #define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK                                                                0x0001FF00L
6632 //CP_ME_CNTL
6633 #define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT                                                               0x4
6634 #define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT                                                              0x6
6635 #define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT                                                               0x8
6636 #define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT                                                                     0x10
6637 #define CP_ME_CNTL__CE_PIPE1_RESET__SHIFT                                                                     0x11
6638 #define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT                                                                    0x12
6639 #define CP_ME_CNTL__PFP_PIPE1_RESET__SHIFT                                                                    0x13
6640 #define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT                                                                     0x14
6641 #define CP_ME_CNTL__ME_PIPE1_RESET__SHIFT                                                                     0x15
6642 #define CP_ME_CNTL__CE_HALT__SHIFT                                                                            0x18
6643 #define CP_ME_CNTL__CE_STEP__SHIFT                                                                            0x19
6644 #define CP_ME_CNTL__PFP_HALT__SHIFT                                                                           0x1a
6645 #define CP_ME_CNTL__PFP_STEP__SHIFT                                                                           0x1b
6646 #define CP_ME_CNTL__ME_HALT__SHIFT                                                                            0x1c
6647 #define CP_ME_CNTL__ME_STEP__SHIFT                                                                            0x1d
6648 #define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK                                                                 0x00000010L
6649 #define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK                                                                0x00000040L
6650 #define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK                                                                 0x00000100L
6651 #define CP_ME_CNTL__CE_PIPE0_RESET_MASK                                                                       0x00010000L
6652 #define CP_ME_CNTL__CE_PIPE1_RESET_MASK                                                                       0x00020000L
6653 #define CP_ME_CNTL__PFP_PIPE0_RESET_MASK                                                                      0x00040000L
6654 #define CP_ME_CNTL__PFP_PIPE1_RESET_MASK                                                                      0x00080000L
6655 #define CP_ME_CNTL__ME_PIPE0_RESET_MASK                                                                       0x00100000L
6656 #define CP_ME_CNTL__ME_PIPE1_RESET_MASK                                                                       0x00200000L
6657 #define CP_ME_CNTL__CE_HALT_MASK                                                                              0x01000000L
6658 #define CP_ME_CNTL__CE_STEP_MASK                                                                              0x02000000L
6659 #define CP_ME_CNTL__PFP_HALT_MASK                                                                             0x04000000L
6660 #define CP_ME_CNTL__PFP_STEP_MASK                                                                             0x08000000L
6661 #define CP_ME_CNTL__ME_HALT_MASK                                                                              0x10000000L
6662 #define CP_ME_CNTL__ME_STEP_MASK                                                                              0x20000000L
6663 //CP_CNTX_STAT
6664 #define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT                                                             0x0
6665 #define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT                                                             0x8
6666 #define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT                                                              0x14
6667 #define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT                                                              0x1c
6668 #define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK                                                               0x000000FFL
6669 #define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK                                                               0x00000700L
6670 #define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK                                                                0x0FF00000L
6671 #define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK                                                                0x70000000L
6672 //CP_ME_PREEMPTION
6673 #define CP_ME_PREEMPTION__OBSOLETE__SHIFT                                                                     0x0
6674 #define CP_ME_PREEMPTION__OBSOLETE_MASK                                                                       0x00000001L
6675 //CP_ROQ_THRESHOLDS
6676 #define CP_ROQ_THRESHOLDS__IB1_START__SHIFT                                                                   0x0
6677 #define CP_ROQ_THRESHOLDS__IB2_START__SHIFT                                                                   0x8
6678 #define CP_ROQ_THRESHOLDS__IB1_START_MASK                                                                     0x000000FFL
6679 #define CP_ROQ_THRESHOLDS__IB2_START_MASK                                                                     0x0000FF00L
6680 //CP_MEQ_STQ_THRESHOLD
6681 #define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT                                                                0x0
6682 #define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK                                                                  0x000000FFL
6683 //CP_RB2_RPTR
6684 #define CP_RB2_RPTR__RB_RPTR__SHIFT                                                                           0x0
6685 #define CP_RB2_RPTR__RB_RPTR_MASK                                                                             0x000FFFFFL
6686 //CP_RB1_RPTR
6687 #define CP_RB1_RPTR__RB_RPTR__SHIFT                                                                           0x0
6688 #define CP_RB1_RPTR__RB_RPTR_MASK                                                                             0x000FFFFFL
6689 //CP_RB0_RPTR
6690 #define CP_RB0_RPTR__RB_RPTR__SHIFT                                                                           0x0
6691 #define CP_RB0_RPTR__RB_RPTR_MASK                                                                             0x000FFFFFL
6692 //CP_RB_RPTR
6693 #define CP_RB_RPTR__RB_RPTR__SHIFT                                                                            0x0
6694 #define CP_RB_RPTR__RB_RPTR_MASK                                                                              0x000FFFFFL
6695 //CP_RB_WPTR_DELAY
6696 #define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT                                                              0x0
6697 #define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT                                                              0x1c
6698 #define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK                                                                0x0FFFFFFFL
6699 #define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK                                                                0xF0000000L
6700 //CP_RB_WPTR_POLL_CNTL
6701 #define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT                                                           0x0
6702 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                          0x10
6703 #define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK                                                             0x0000FFFFL
6704 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                            0xFFFF0000L
6705 //CP_ROQ1_THRESHOLDS
6706 #define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT                                                                  0x0
6707 #define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT                                                               0xa
6708 #define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT                                                               0x14
6709 #define CP_ROQ1_THRESHOLDS__RB1_START_MASK                                                                    0x000003FFL
6710 #define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK                                                                 0x000FFC00L
6711 #define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK                                                                 0x3FF00000L
6712 //CP_ROQ2_THRESHOLDS
6713 #define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT                                                               0x0
6714 #define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT                                                               0xa
6715 #define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK                                                                 0x000003FFL
6716 #define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK                                                                 0x000FFC00L
6717 //CP_STQ_THRESHOLDS
6718 #define CP_STQ_THRESHOLDS__STQ0_START__SHIFT                                                                  0x0
6719 #define CP_STQ_THRESHOLDS__STQ1_START__SHIFT                                                                  0x8
6720 #define CP_STQ_THRESHOLDS__STQ2_START__SHIFT                                                                  0x10
6721 #define CP_STQ_THRESHOLDS__STQ0_START_MASK                                                                    0x000000FFL
6722 #define CP_STQ_THRESHOLDS__STQ1_START_MASK                                                                    0x0000FF00L
6723 #define CP_STQ_THRESHOLDS__STQ2_START_MASK                                                                    0x00FF0000L
6724 //CP_QUEUE_THRESHOLDS
6725 #define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT                                                             0x0
6726 #define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT                                                             0x8
6727 #define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK                                                               0x0000003FL
6728 #define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK                                                               0x00003F00L
6729 //CP_MEQ_THRESHOLDS
6730 #define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT                                                                  0x0
6731 #define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT                                                                  0x8
6732 #define CP_MEQ_THRESHOLDS__MEQ1_START_MASK                                                                    0x000000FFL
6733 #define CP_MEQ_THRESHOLDS__MEQ2_START_MASK                                                                    0x0000FF00L
6734 //CP_ROQ_AVAIL
6735 #define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT                                                                     0x0
6736 #define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT                                                                      0x10
6737 #define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK                                                                       0x00000FFFL
6738 #define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK                                                                        0x0FFF0000L
6739 //CP_STQ_AVAIL
6740 #define CP_STQ_AVAIL__STQ_CNT__SHIFT                                                                          0x0
6741 #define CP_STQ_AVAIL__STQ_CNT_MASK                                                                            0x000001FFL
6742 //CP_ROQ2_AVAIL
6743 #define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT                                                                     0x0
6744 #define CP_ROQ2_AVAIL__ROQ_CNT_DB__SHIFT                                                                      0x10
6745 #define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK                                                                       0x00000FFFL
6746 #define CP_ROQ2_AVAIL__ROQ_CNT_DB_MASK                                                                        0x0FFF0000L
6747 //CP_MEQ_AVAIL
6748 #define CP_MEQ_AVAIL__MEQ_CNT__SHIFT                                                                          0x0
6749 #define CP_MEQ_AVAIL__MEQ_CNT_MASK                                                                            0x000003FFL
6750 //CP_CMD_INDEX
6751 #define CP_CMD_INDEX__CMD_INDEX__SHIFT                                                                        0x0
6752 #define CP_CMD_INDEX__CMD_ME_SEL__SHIFT                                                                       0xc
6753 #define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT                                                                    0x10
6754 #define CP_CMD_INDEX__CMD_INDEX_MASK                                                                          0x000007FFL
6755 #define CP_CMD_INDEX__CMD_ME_SEL_MASK                                                                         0x00003000L
6756 #define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK                                                                      0x00070000L
6757 //CP_CMD_DATA
6758 #define CP_CMD_DATA__CMD_DATA__SHIFT                                                                          0x0
6759 #define CP_CMD_DATA__CMD_DATA_MASK                                                                            0xFFFFFFFFL
6760 //CP_ROQ_RB_STAT
6761 #define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT                                                               0x0
6762 #define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT                                                               0x10
6763 #define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK                                                                 0x00000FFFL
6764 #define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK                                                                 0x0FFF0000L
6765 //CP_ROQ_IB1_STAT
6766 #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT                                                            0x0
6767 #define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT                                                            0x10
6768 #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK                                                              0x00000FFFL
6769 #define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK                                                              0x0FFF0000L
6770 //CP_ROQ_IB2_STAT
6771 #define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT                                                            0x0
6772 #define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT                                                            0x10
6773 #define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK                                                              0x00000FFFL
6774 #define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK                                                              0x0FFF0000L
6775 //CP_STQ_STAT
6776 #define CP_STQ_STAT__STQ_RPTR__SHIFT                                                                          0x0
6777 #define CP_STQ_STAT__STQ_RPTR_MASK                                                                            0x000003FFL
6778 //CP_STQ_WR_STAT
6779 #define CP_STQ_WR_STAT__STQ_WPTR__SHIFT                                                                       0x0
6780 #define CP_STQ_WR_STAT__STQ_WPTR_MASK                                                                         0x000003FFL
6781 //CP_MEQ_STAT
6782 #define CP_MEQ_STAT__MEQ_RPTR__SHIFT                                                                          0x0
6783 #define CP_MEQ_STAT__MEQ_WPTR__SHIFT                                                                          0x10
6784 #define CP_MEQ_STAT__MEQ_RPTR_MASK                                                                            0x000003FFL
6785 #define CP_MEQ_STAT__MEQ_WPTR_MASK                                                                            0x03FF0000L
6786 //CP_CEQ1_AVAIL
6787 #define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT                                                                    0x0
6788 #define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT                                                                     0x10
6789 #define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK                                                                      0x00000FFFL
6790 #define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK                                                                       0x0FFF0000L
6791 //CP_CEQ2_AVAIL
6792 #define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT                                                                     0x0
6793 #define CP_CEQ2_AVAIL__CEQ_CNT_DB__SHIFT                                                                      0x10
6794 #define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK                                                                       0x00000FFFL
6795 #define CP_CEQ2_AVAIL__CEQ_CNT_DB_MASK                                                                        0x0FFF0000L
6796 //CP_CE_ROQ_RB_STAT
6797 #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT                                                            0x0
6798 #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT                                                            0x10
6799 #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK                                                              0x00000FFFL
6800 #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK                                                              0x0FFF0000L
6801 //CP_CE_ROQ_IB1_STAT
6802 #define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT                                                         0x0
6803 #define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT                                                         0x10
6804 #define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK                                                           0x00000FFFL
6805 #define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK                                                           0x0FFF0000L
6806 //CP_CE_ROQ_IB2_STAT
6807 #define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT                                                         0x0
6808 #define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT                                                         0x10
6809 #define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK                                                           0x00000FFFL
6810 #define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK                                                           0x0FFF0000L
6811 //CP_CE_ROQ_DB_STAT
6812 #define CP_CE_ROQ_DB_STAT__CEQ_RPTR_DB__SHIFT                                                                 0x0
6813 #define CP_CE_ROQ_DB_STAT__CEQ_WPTR_DB__SHIFT                                                                 0x10
6814 #define CP_CE_ROQ_DB_STAT__CEQ_RPTR_DB_MASK                                                                   0x00000FFFL
6815 #define CP_CE_ROQ_DB_STAT__CEQ_WPTR_DB_MASK                                                                   0x0FFF0000L
6816 //CP_ROQ3_THRESHOLDS
6817 #define CP_ROQ3_THRESHOLDS__R0_DB_START__SHIFT                                                                0x0
6818 #define CP_ROQ3_THRESHOLDS__R1_DB_START__SHIFT                                                                0xa
6819 #define CP_ROQ3_THRESHOLDS__R0_DB_START_MASK                                                                  0x000003FFL
6820 #define CP_ROQ3_THRESHOLDS__R1_DB_START_MASK                                                                  0x000FFC00L
6821 //CP_ROQ_DB_STAT
6822 #define CP_ROQ_DB_STAT__ROQ_RPTR_DB__SHIFT                                                                    0x0
6823 #define CP_ROQ_DB_STAT__ROQ_WPTR_DB__SHIFT                                                                    0x10
6824 #define CP_ROQ_DB_STAT__ROQ_RPTR_DB_MASK                                                                      0x00000FFFL
6825 #define CP_ROQ_DB_STAT__ROQ_WPTR_DB_MASK                                                                      0x0FFF0000L
6826 #define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT                                                     0x16
6827 #define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT                                                       0x17
6828 #define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK                                                       0x00400000L
6829 #define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK                                                         0x00800000L
6830 
6831 
6832 // addressBlock: gc_padec
6833 //VGT_VTX_VECT_EJECT_REG
6834 #define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT                                                             0x0
6835 #define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK                                                               0x000003FFL
6836 //VGT_DMA_DATA_FIFO_DEPTH
6837 #define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT                                                   0x0
6838 #define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK                                                     0x000003FFL
6839 //VGT_DMA_REQ_FIFO_DEPTH
6840 #define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT                                                     0x0
6841 #define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK                                                       0x0000003FL
6842 //VGT_DRAW_INIT_FIFO_DEPTH
6843 #define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT                                                 0x0
6844 #define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK                                                   0x0000003FL
6845 //VGT_LAST_COPY_STATE
6846 #define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT                                                              0x0
6847 #define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT                                                              0x10
6848 #define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK                                                                0x00000007L
6849 #define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK                                                                0x00070000L
6850 //VGT_CACHE_INVALIDATION
6851 #define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT                                                     0x0
6852 #define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT                                                     0x4
6853 #define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT                                                     0x5
6854 #define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT                                                          0x6
6855 #define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT                                                            0x9
6856 #define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT                                                   0xb
6857 #define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT                                                       0xc
6858 #define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT                                                   0xd
6859 #define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT                                                               0x10
6860 #define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG__SHIFT                                                       0x15
6861 #define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1__SHIFT                                                        0x16
6862 #define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2__SHIFT                                                        0x19
6863 #define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE__SHIFT                                                          0x1c
6864 #define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI__SHIFT                                                   0x1d
6865 #define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK                                                       0x00000003L
6866 #define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK                                                       0x00000010L
6867 #define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK                                                       0x00000020L
6868 #define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK                                                            0x000000C0L
6869 #define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK                                                              0x00000200L
6870 #define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK                                                     0x00000800L
6871 #define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK                                                         0x00001000L
6872 #define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK                                                     0x00002000L
6873 #define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK                                                                 0x001F0000L
6874 #define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_MASK                                                         0x00200000L
6875 #define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1_MASK                                                          0x01C00000L
6876 #define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2_MASK                                                          0x0E000000L
6877 #define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE_MASK                                                            0x10000000L
6878 #define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI_MASK                                                     0x20000000L
6879 //VGT_ESGS_RING_SIZE
6880 #define VGT_ESGS_RING_SIZE__MEM_SIZE__SHIFT                                                                   0x0
6881 #define VGT_ESGS_RING_SIZE__MEM_SIZE_MASK                                                                     0xFFFFFFFFL
6882 //VGT_GSVS_RING_SIZE
6883 #define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT                                                                   0x0
6884 #define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK                                                                     0xFFFFFFFFL
6885 //VGT_FIFO_DEPTHS
6886 #define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT                                                          0x0
6887 #define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT                                                                    0x7
6888 #define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT                                                              0x8
6889 #define VGT_FIFO_DEPTHS__RESERVED_1__SHIFT                                                                    0x16
6890 #define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT                                                            0x17
6891 #define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK                                                            0x0000007FL
6892 #define VGT_FIFO_DEPTHS__RESERVED_0_MASK                                                                      0x00000080L
6893 #define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK                                                                0x003FFF00L
6894 #define VGT_FIFO_DEPTHS__RESERVED_1_MASK                                                                      0x00400000L
6895 #define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK                                                              0x1F800000L
6896 //VGT_GS_VERTEX_REUSE
6897 #define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT                                                                0x0
6898 #define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK                                                                  0x0000001FL
6899 //VGT_MC_LAT_CNTL
6900 #define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT                                                             0x0
6901 #define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK                                                               0x0000000FL
6902 //IA_UTCL1_STATUS_2
6903 #define IA_UTCL1_STATUS_2__IA_BUSY__SHIFT                                                                     0x0
6904 #define IA_UTCL1_STATUS_2__IA_DMA_BUSY__SHIFT                                                                 0x1
6905 #define IA_UTCL1_STATUS_2__IA_DMA_REQ_BUSY__SHIFT                                                             0x2
6906 #define IA_UTCL1_STATUS_2__IA_GRP_BUSY__SHIFT                                                                 0x3
6907 #define IA_UTCL1_STATUS_2__IA_ADC_BUSY__SHIFT                                                                 0x4
6908 #define IA_UTCL1_STATUS_2__FAULT_DETECTED__SHIFT                                                              0x5
6909 #define IA_UTCL1_STATUS_2__RETRY_DETECTED__SHIFT                                                              0x6
6910 #define IA_UTCL1_STATUS_2__PRT_DETECTED__SHIFT                                                                0x7
6911 #define IA_UTCL1_STATUS_2__FAULT_UTCL1ID__SHIFT                                                               0x8
6912 #define IA_UTCL1_STATUS_2__RETRY_UTCL1ID__SHIFT                                                               0x10
6913 #define IA_UTCL1_STATUS_2__PRT_UTCL1ID__SHIFT                                                                 0x18
6914 #define IA_UTCL1_STATUS_2__IA_BUSY_MASK                                                                       0x00000001L
6915 #define IA_UTCL1_STATUS_2__IA_DMA_BUSY_MASK                                                                   0x00000002L
6916 #define IA_UTCL1_STATUS_2__IA_DMA_REQ_BUSY_MASK                                                               0x00000004L
6917 #define IA_UTCL1_STATUS_2__IA_GRP_BUSY_MASK                                                                   0x00000008L
6918 #define IA_UTCL1_STATUS_2__IA_ADC_BUSY_MASK                                                                   0x00000010L
6919 #define IA_UTCL1_STATUS_2__FAULT_DETECTED_MASK                                                                0x00000020L
6920 #define IA_UTCL1_STATUS_2__RETRY_DETECTED_MASK                                                                0x00000040L
6921 #define IA_UTCL1_STATUS_2__PRT_DETECTED_MASK                                                                  0x00000080L
6922 #define IA_UTCL1_STATUS_2__FAULT_UTCL1ID_MASK                                                                 0x00003F00L
6923 #define IA_UTCL1_STATUS_2__RETRY_UTCL1ID_MASK                                                                 0x003F0000L
6924 #define IA_UTCL1_STATUS_2__PRT_UTCL1ID_MASK                                                                   0x3F000000L
6925 //VGT_CNTL_STATUS
6926 #define VGT_CNTL_STATUS__VGT_BUSY__SHIFT                                                                      0x0
6927 #define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT                                                             0x1
6928 #define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT                                                                  0x2
6929 #define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT                                                                   0x3
6930 #define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT                                                                   0x4
6931 #define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT                                                                   0x5
6932 #define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT                                                                   0x6
6933 #define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT                                                                   0x7
6934 #define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT                                                                   0x8
6935 #define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT                                                                 0x9
6936 #define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY__SHIFT                                                              0xa
6937 #define VGT_CNTL_STATUS__VGT_BUSY_MASK                                                                        0x00000001L
6938 #define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK                                                               0x00000002L
6939 #define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK                                                                    0x00000004L
6940 #define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK                                                                     0x00000008L
6941 #define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK                                                                     0x00000010L
6942 #define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK                                                                     0x00000020L
6943 #define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK                                                                     0x00000040L
6944 #define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK                                                                     0x00000080L
6945 #define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK                                                                     0x00000100L
6946 #define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK                                                                   0x00000200L
6947 #define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY_MASK                                                                0x00000400L
6948 //WD_CNTL_STATUS
6949 #define WD_CNTL_STATUS__WD_BUSY__SHIFT                                                                        0x0
6950 #define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT                                                                0x1
6951 #define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT                                                                 0x2
6952 #define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT                                                                    0x3
6953 #define WD_CNTL_STATUS__WD_BUSY_MASK                                                                          0x00000001L
6954 #define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK                                                                  0x00000002L
6955 #define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK                                                                   0x00000004L
6956 #define WD_CNTL_STATUS__WD_ADC_BUSY_MASK                                                                      0x00000008L
6957 //CC_GC_PRIM_CONFIG
6958 #define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT                                                                 0x10
6959 #define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT                                                             0x18
6960 #define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK                                                                   0x00030000L
6961 #define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK                                                               0x0F000000L
6962 //GC_USER_PRIM_CONFIG
6963 #define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT                                                               0x10
6964 #define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT                                                           0x18
6965 #define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK                                                                 0x00030000L
6966 #define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK                                                             0x0F000000L
6967 //WD_QOS
6968 #define WD_QOS__DRAW_STALL__SHIFT                                                                             0x0
6969 #define WD_QOS__DRAW_STALL_MASK                                                                               0x00000001L
6970 //WD_UTCL1_CNTL
6971 #define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT                                                            0x0
6972 #define WD_UTCL1_CNTL__VMID_RESET_MODE__SHIFT                                                                 0x17
6973 #define WD_UTCL1_CNTL__DROP_MODE__SHIFT                                                                       0x18
6974 #define WD_UTCL1_CNTL__BYPASS__SHIFT                                                                          0x19
6975 #define WD_UTCL1_CNTL__INVALIDATE__SHIFT                                                                      0x1a
6976 #define WD_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT                                                                 0x1b
6977 #define WD_UTCL1_CNTL__FORCE_SNOOP__SHIFT                                                                     0x1c
6978 #define WD_UTCL1_CNTL__MTYPE_OVERRIDE__SHIFT                                                                  0x1d
6979 #define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK                                                              0x000FFFFFL
6980 #define WD_UTCL1_CNTL__VMID_RESET_MODE_MASK                                                                   0x00800000L
6981 #define WD_UTCL1_CNTL__DROP_MODE_MASK                                                                         0x01000000L
6982 #define WD_UTCL1_CNTL__BYPASS_MASK                                                                            0x02000000L
6983 #define WD_UTCL1_CNTL__INVALIDATE_MASK                                                                        0x04000000L
6984 #define WD_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK                                                                   0x08000000L
6985 #define WD_UTCL1_CNTL__FORCE_SNOOP_MASK                                                                       0x10000000L
6986 #define WD_UTCL1_CNTL__MTYPE_OVERRIDE_MASK                                                                    0x20000000L
6987 //WD_UTCL1_STATUS
6988 #define WD_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                                0x0
6989 #define WD_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                                0x1
6990 #define WD_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                  0x2
6991 #define WD_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT                                                                 0x8
6992 #define WD_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT                                                                 0x10
6993 #define WD_UTCL1_STATUS__PRT_UTCL1ID__SHIFT                                                                   0x18
6994 #define WD_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                  0x00000001L
6995 #define WD_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                  0x00000002L
6996 #define WD_UTCL1_STATUS__PRT_DETECTED_MASK                                                                    0x00000004L
6997 #define WD_UTCL1_STATUS__FAULT_UTCL1ID_MASK                                                                   0x00003F00L
6998 #define WD_UTCL1_STATUS__RETRY_UTCL1ID_MASK                                                                   0x003F0000L
6999 #define WD_UTCL1_STATUS__PRT_UTCL1ID_MASK                                                                     0x3F000000L
7000 //GE_PC_CNTL
7001 #define GE_PC_CNTL__PC_SIZE__SHIFT                                                                            0x0
7002 #define GE_PC_CNTL__EN_GEN_0_1_LATE_ALLOC__SHIFT                                                              0x10
7003 #define GE_PC_CNTL__PC_SIZE_MASK                                                                              0x0000FFFFL
7004 #define GE_PC_CNTL__EN_GEN_0_1_LATE_ALLOC_MASK                                                                0x00010000L
7005 //IA_UTCL1_CNTL
7006 #define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT                                                            0x0
7007 #define IA_UTCL1_CNTL__VMID_RESET_MODE__SHIFT                                                                 0x17
7008 #define IA_UTCL1_CNTL__DROP_MODE__SHIFT                                                                       0x18
7009 #define IA_UTCL1_CNTL__BYPASS__SHIFT                                                                          0x19
7010 #define IA_UTCL1_CNTL__INVALIDATE__SHIFT                                                                      0x1a
7011 #define IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT                                                                 0x1b
7012 #define IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT                                                                     0x1c
7013 #define IA_UTCL1_CNTL__MTYPE_OVERRIDE__SHIFT                                                                  0x1d
7014 #define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK                                                              0x000FFFFFL
7015 #define IA_UTCL1_CNTL__VMID_RESET_MODE_MASK                                                                   0x00800000L
7016 #define IA_UTCL1_CNTL__DROP_MODE_MASK                                                                         0x01000000L
7017 #define IA_UTCL1_CNTL__BYPASS_MASK                                                                            0x02000000L
7018 #define IA_UTCL1_CNTL__INVALIDATE_MASK                                                                        0x04000000L
7019 #define IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK                                                                   0x08000000L
7020 #define IA_UTCL1_CNTL__FORCE_SNOOP_MASK                                                                       0x10000000L
7021 #define IA_UTCL1_CNTL__MTYPE_OVERRIDE_MASK                                                                    0x20000000L
7022 //IA_UTCL1_STATUS
7023 #define IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                                0x0
7024 #define IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                                0x1
7025 #define IA_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                  0x2
7026 #define IA_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT                                                                 0x8
7027 #define IA_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT                                                                 0x10
7028 #define IA_UTCL1_STATUS__PRT_UTCL1ID__SHIFT                                                                   0x18
7029 #define IA_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                  0x00000001L
7030 #define IA_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                  0x00000002L
7031 #define IA_UTCL1_STATUS__PRT_DETECTED_MASK                                                                    0x00000004L
7032 #define IA_UTCL1_STATUS__FAULT_UTCL1ID_MASK                                                                   0x00003F00L
7033 #define IA_UTCL1_STATUS__RETRY_UTCL1ID_MASK                                                                   0x003F0000L
7034 #define IA_UTCL1_STATUS__PRT_UTCL1ID_MASK                                                                     0x3F000000L
7035 //GE_FAST_CLKS
7036 #define GE_FAST_CLKS__HYSTERESIS__SHIFT                                                                       0x0
7037 #define GE_FAST_CLKS__LOCK__SHIFT                                                                             0x1e
7038 #define GE_FAST_CLKS__FORCE_FAST_CLK__SHIFT                                                                   0x1f
7039 #define GE_FAST_CLKS__HYSTERESIS_MASK                                                                         0x3FFFFFFFL
7040 #define GE_FAST_CLKS__LOCK_MASK                                                                               0x40000000L
7041 #define GE_FAST_CLKS__FORCE_FAST_CLK_MASK                                                                     0x80000000L
7042 //VGT_TF_RING_SIZE
7043 #define VGT_TF_RING_SIZE__SIZE__SHIFT                                                                         0x0
7044 #define VGT_TF_RING_SIZE__SIZE_MASK                                                                           0x0000FFFFL
7045 //VGT_SYS_CONFIG
7046 #define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT                                                                   0x0
7047 #define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT                                                               0x1
7048 #define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT                                                       0x7
7049 #define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK                                                                     0x00000001L
7050 #define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK                                                                 0x0000007EL
7051 #define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK                                                         0x00000080L
7052 //GE_PRIV_CONTROL
7053 #define GE_PRIV_CONTROL__DISCARD_LEGACY__SHIFT                                                                0x0
7054 #define GE_PRIV_CONTROL__CLAMP_PRIMGRP_SIZE__SHIFT                                                            0x1
7055 #define GE_PRIV_CONTROL__RESET_ON_PIPELINE_CHANGE__SHIFT                                                      0xa
7056 #define GE_PRIV_CONTROL__DISCARD_LEGACY_MASK                                                                  0x00000001L
7057 #define GE_PRIV_CONTROL__CLAMP_PRIMGRP_SIZE_MASK                                                              0x000003FEL
7058 #define GE_PRIV_CONTROL__RESET_ON_PIPELINE_CHANGE_MASK                                                        0x00000400L
7059 //GE_STATUS
7060 #define GE_STATUS__PERFCOUNTER_STATUS__SHIFT                                                                  0x0
7061 #define GE_STATUS__THREAD_TRACE_STATUS__SHIFT                                                                 0x1
7062 #define GE_STATUS__PERFCOUNTER_STATUS_MASK                                                                    0x00000001L
7063 #define GE_STATUS__THREAD_TRACE_STATUS_MASK                                                                   0x00000002L
7064 //VGT_VS_MAX_WAVE_ID
7065 #define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT                                                                0x0
7066 #define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK                                                                  0x00000FFFL
7067 //VGT_GS_MAX_WAVE_ID
7068 #define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT                                                                0x0
7069 #define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID_MASK                                                                  0x00000FFFL
7070 //CC_GC_SHADER_ARRAY_CONFIG_GEN0
7071 #define CC_GC_SHADER_ARRAY_CONFIG_GEN0__GEN0_INACTIVE_CU__SHIFT                                               0x10
7072 #define CC_GC_SHADER_ARRAY_CONFIG_GEN0__GEN0_INACTIVE_CU_MASK                                                 0x03FF0000L
7073 //VGT_HS_OFFCHIP_PARAM
7074 #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT                                                        0x0
7075 #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT                                                      0x9
7076 #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK                                                          0x000001FFL
7077 #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK                                                        0x00000600L
7078 //GFX_PIPE_CONTROL
7079 #define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT                                                               0x0
7080 #define GFX_PIPE_CONTROL__RESERVED__SHIFT                                                                     0xd
7081 #define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT                                                           0x10
7082 #define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK                                                                 0x00001FFFL
7083 #define GFX_PIPE_CONTROL__RESERVED_MASK                                                                       0x0000E000L
7084 #define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK                                                             0x00010000L
7085 //VGT_TF_MEMORY_BASE
7086 #define VGT_TF_MEMORY_BASE__BASE__SHIFT                                                                       0x0
7087 #define VGT_TF_MEMORY_BASE__BASE_MASK                                                                         0xFFFFFFFFL
7088 //CC_GC_SHADER_ARRAY_CONFIG
7089 #define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT                                                       0x10
7090 #define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK                                                         0xFFFF0000L
7091 //GC_USER_SHADER_ARRAY_CONFIG
7092 #define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT                                                     0x10
7093 #define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK                                                       0xFFFF0000L
7094 //VGT_DMA_PRIMITIVE_TYPE
7095 #define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT                                                              0x0
7096 #define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK                                                                0x0000003FL
7097 //VGT_DMA_CONTROL
7098 #define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT                                                                0x0
7099 #define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT                                                              0x11
7100 #define VGT_DMA_CONTROL__SWITCH_ON_EOI__SHIFT                                                                 0x13
7101 #define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT                                                              0x14
7102 #define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK                                                                  0x0000FFFFL
7103 #define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK                                                                0x00020000L
7104 #define VGT_DMA_CONTROL__SWITCH_ON_EOI_MASK                                                                   0x00080000L
7105 #define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK                                                                0x00100000L
7106 //VGT_DMA_LS_HS_CONFIG
7107 #define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT                                                          0x8
7108 #define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK                                                            0x00003F00L
7109 //VGT_STRMOUT_DELAY
7110 #define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT                                                                  0x0
7111 #define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT                                                                0x8
7112 #define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT                                                                0xb
7113 #define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT                                                                0xe
7114 #define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT                                                                0x11
7115 #define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK                                                                    0x000000FFL
7116 #define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK                                                                  0x00000700L
7117 #define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK                                                                  0x00003800L
7118 #define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK                                                                  0x0001C000L
7119 #define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK                                                                  0x000E0000L
7120 //WD_BUF_RESOURCE_1
7121 #define WD_BUF_RESOURCE_1__POS_BUF_SIZE__SHIFT                                                                0x0
7122 #define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE__SHIFT                                                              0x10
7123 #define WD_BUF_RESOURCE_1__POS_BUF_SIZE_MASK                                                                  0x0000FFFFL
7124 #define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE_MASK                                                                0xFFFF0000L
7125 //WD_BUF_RESOURCE_2
7126 #define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE__SHIFT                                                              0x0
7127 #define WD_BUF_RESOURCE_2__ADDR_MODE__SHIFT                                                                   0xf
7128 #define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE__SHIFT                                                            0x10
7129 #define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE_MASK                                                                0x00001FFFL
7130 #define WD_BUF_RESOURCE_2__ADDR_MODE_MASK                                                                     0x00008000L
7131 #define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE_MASK                                                              0xFFFF0000L
7132 //VGT_TF_MEMORY_BASE_HI
7133 #define VGT_TF_MEMORY_BASE_HI__BASE_HI__SHIFT                                                                 0x0
7134 #define VGT_TF_MEMORY_BASE_HI__BASE_HI_MASK                                                                   0x000000FFL
7135 //PA_CL_CNTL_STATUS
7136 #define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT                                                          0x0
7137 #define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED__SHIFT                                                          0x1
7138 #define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED__SHIFT                                                            0x2
7139 #define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT                                                                     0x1f
7140 #define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED_MASK                                                            0x00000001L
7141 #define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED_MASK                                                            0x00000002L
7142 #define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED_MASK                                                              0x00000004L
7143 #define PA_CL_CNTL_STATUS__CL_BUSY_MASK                                                                       0x80000000L
7144 //PA_CL_ENHANCE
7145 #define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT                                                            0x0
7146 #define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT                                                                    0x1
7147 #define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT                                                          0x3
7148 #define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT                                                             0x4
7149 #define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET__SHIFT                                                           0x6
7150 #define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS__SHIFT                                                           0x7
7151 #define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC__SHIFT                                                                0x8
7152 #define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION__SHIFT                                                0x9
7153 #define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER__SHIFT                                                          0xb
7154 #define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH__SHIFT                                                       0xc
7155 #define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH__SHIFT                                                     0xe
7156 #define PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE__SHIFT                                                     0x11
7157 #define PA_CL_ENHANCE__OUTPUT_SWITCH_TO_LEGACY_EVENT__SHIFT                                                   0x12
7158 #define PA_CL_ENHANCE__NO_SWITCH_TO_LEGACY_AFTER_VMID_RESET__SHIFT                                            0x13
7159 #define PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE__SHIFT                                                    0x14
7160 #define PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE__SHIFT                                                     0x15
7161 #define PA_CL_ENHANCE__DISABLE_PA_PH_INTF_FINE_CLOCK_GATE__SHIFT                                              0x16
7162 #define PA_CL_ENHANCE__EN_32BIT_OBJPRIMID__SHIFT                                                              0x17
7163 #define PA_CL_ENHANCE__ECO_SPARE3__SHIFT                                                                      0x1c
7164 #define PA_CL_ENHANCE__ECO_SPARE2__SHIFT                                                                      0x1d
7165 #define PA_CL_ENHANCE__ECO_SPARE1__SHIFT                                                                      0x1e
7166 #define PA_CL_ENHANCE__ECO_SPARE0__SHIFT                                                                      0x1f
7167 #define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK                                                              0x00000001L
7168 #define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK                                                                      0x00000006L
7169 #define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK                                                            0x00000008L
7170 #define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK                                                               0x00000010L
7171 #define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET_MASK                                                             0x00000040L
7172 #define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS_MASK                                                             0x00000080L
7173 #define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC_MASK                                                                  0x00000100L
7174 #define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION_MASK                                                  0x00000600L
7175 #define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER_MASK                                                            0x00000800L
7176 #define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH_MASK                                                         0x00003000L
7177 #define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH_MASK                                                       0x0001C000L
7178 #define PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE_MASK                                                       0x00020000L
7179 #define PA_CL_ENHANCE__OUTPUT_SWITCH_TO_LEGACY_EVENT_MASK                                                     0x00040000L
7180 #define PA_CL_ENHANCE__NO_SWITCH_TO_LEGACY_AFTER_VMID_RESET_MASK                                              0x00080000L
7181 #define PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE_MASK                                                      0x00100000L
7182 #define PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE_MASK                                                       0x00200000L
7183 #define PA_CL_ENHANCE__DISABLE_PA_PH_INTF_FINE_CLOCK_GATE_MASK                                                0x00400000L
7184 #define PA_CL_ENHANCE__EN_32BIT_OBJPRIMID_MASK                                                                0x00800000L
7185 #define PA_CL_ENHANCE__ECO_SPARE3_MASK                                                                        0x10000000L
7186 #define PA_CL_ENHANCE__ECO_SPARE2_MASK                                                                        0x20000000L
7187 #define PA_CL_ENHANCE__ECO_SPARE1_MASK                                                                        0x40000000L
7188 #define PA_CL_ENHANCE__ECO_SPARE0_MASK                                                                        0x80000000L
7189 //PA_SU_CNTL_STATUS
7190 #define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT                                                                     0x1f
7191 #define PA_SU_CNTL_STATUS__SU_BUSY_MASK                                                                       0x80000000L
7192 //PA_SC_FIFO_DEPTH_CNTL
7193 #define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT                                                                   0x0
7194 #define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK                                                                     0x000003FFL
7195 //PA_SC_P3D_TRAP_SCREEN_HV_LOCK
7196 #define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT                                         0x0
7197 #define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK                                           0x00000001L
7198 //PA_SC_HP3D_TRAP_SCREEN_HV_LOCK
7199 #define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT                                        0x0
7200 #define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK                                          0x00000001L
7201 //PA_SC_TRAP_SCREEN_HV_LOCK
7202 #define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT                                             0x0
7203 #define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK                                               0x00000001L
7204 //PA_SC_FORCE_EOV_MAX_CNTS
7205 #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT                                                0x0
7206 #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT                                                0x10
7207 #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK                                                  0x0000FFFFL
7208 #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK                                                  0xFFFF0000L
7209 //PA_SC_BINNER_EVENT_CNTL_0
7210 #define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0__SHIFT                                                          0x0
7211 #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1__SHIFT                                              0x2
7212 #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2__SHIFT                                              0x4
7213 #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3__SHIFT                                              0x6
7214 #define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS__SHIFT                                                      0x8
7215 #define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT                                                        0xa
7216 #define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH__SHIFT                                                         0xc
7217 #define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH__SHIFT                                                    0xe
7218 #define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC__SHIFT                                                  0x10
7219 #define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9__SHIFT                                                          0x12
7220 #define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET__SHIFT                                                 0x14
7221 #define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE__SHIFT                                                 0x16
7222 #define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END__SHIFT                                                  0x18
7223 #define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT__SHIFT                                                         0x1a
7224 #define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH__SHIFT                                                         0x1c
7225 #define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH__SHIFT                                                    0x1e
7226 #define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0_MASK                                                            0x00000003L
7227 #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1_MASK                                                0x0000000CL
7228 #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2_MASK                                                0x00000030L
7229 #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3_MASK                                                0x000000C0L
7230 #define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS_MASK                                                        0x00000300L
7231 #define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE_MASK                                                          0x00000C00L
7232 #define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_MASK                                                           0x00003000L
7233 #define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH_MASK                                                      0x0000C000L
7234 #define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC_MASK                                                    0x00030000L
7235 #define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9_MASK                                                            0x000C0000L
7236 #define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET_MASK                                                   0x00300000L
7237 #define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE_MASK                                                   0x00C00000L
7238 #define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END_MASK                                                    0x03000000L
7239 #define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT_MASK                                                           0x0C000000L
7240 #define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH_MASK                                                           0x30000000L
7241 #define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH_MASK                                                      0xC0000000L
7242 //PA_SC_BINNER_EVENT_CNTL_1
7243 #define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH__SHIFT                                                    0x0
7244 #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT__SHIFT                                                     0x2
7245 #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM__SHIFT                                                          0x4
7246 #define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT__SHIFT                                                 0x6
7247 #define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT                                        0x8
7248 #define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE__SHIFT                                                          0xa
7249 #define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT__SHIFT                                           0xc
7250 #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START__SHIFT                                                   0xe
7251 #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP__SHIFT                                                    0x10
7252 #define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START__SHIFT                                                  0x12
7253 #define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP__SHIFT                                                   0x14
7254 #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE__SHIFT                                                  0x16
7255 #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT__SHIFT                                                     0x18
7256 #define PA_SC_BINNER_EVENT_CNTL_1__BIN_CONF_OVERRIDE_CHECK__SHIFT                                             0x1a
7257 #define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT__SHIFT                                                 0x1c
7258 #define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH__SHIFT                                               0x1e
7259 #define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH_MASK                                                      0x00000003L
7260 #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT_MASK                                                       0x0000000CL
7261 #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM_MASK                                                            0x00000030L
7262 #define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT_MASK                                                   0x000000C0L
7263 #define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT_MASK                                          0x00000300L
7264 #define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE_MASK                                                            0x00000C00L
7265 #define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT_MASK                                             0x00003000L
7266 #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START_MASK                                                     0x0000C000L
7267 #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP_MASK                                                      0x00030000L
7268 #define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START_MASK                                                    0x000C0000L
7269 #define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP_MASK                                                     0x00300000L
7270 #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE_MASK                                                    0x00C00000L
7271 #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT_MASK                                                       0x03000000L
7272 #define PA_SC_BINNER_EVENT_CNTL_1__BIN_CONF_OVERRIDE_CHECK_MASK                                               0x0C000000L
7273 #define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT_MASK                                                   0x30000000L
7274 #define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH_MASK                                                 0xC0000000L
7275 //PA_SC_BINNER_EVENT_CNTL_2
7276 #define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS__SHIFT                                               0x0
7277 #define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT__SHIFT                                                       0x2
7278 #define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE__SHIFT                                                  0x4
7279 #define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_35__SHIFT                                                         0x6
7280 #define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH__SHIFT                                                           0x8
7281 #define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT                                                       0xa
7282 #define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT__SHIFT                                                        0xc
7283 #define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ__SHIFT                                                      0xe
7284 #define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS__SHIFT                                                   0x10
7285 #define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_41__SHIFT                                                         0x12
7286 #define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV__SHIFT                                              0x14
7287 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS__SHIFT                                            0x16
7288 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META__SHIFT                                               0x18
7289 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS__SHIFT                                            0x1a
7290 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META__SHIFT                                               0x1c
7291 #define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE__SHIFT                                                             0x1e
7292 #define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS_MASK                                                 0x00000003L
7293 #define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT_MASK                                                         0x0000000CL
7294 #define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE_MASK                                                    0x00000030L
7295 #define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_35_MASK                                                           0x000000C0L
7296 #define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH_MASK                                                             0x00000300L
7297 #define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER_MASK                                                         0x00000C00L
7298 #define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT_MASK                                                          0x00003000L
7299 #define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ_MASK                                                        0x0000C000L
7300 #define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS_MASK                                                     0x00030000L
7301 #define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_41_MASK                                                           0x000C0000L
7302 #define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV_MASK                                                0x00300000L
7303 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS_MASK                                              0x00C00000L
7304 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META_MASK                                                 0x03000000L
7305 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS_MASK                                              0x0C000000L
7306 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META_MASK                                                 0x30000000L
7307 #define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE_MASK                                                               0xC0000000L
7308 //PA_SC_BINNER_EVENT_CNTL_3
7309 #define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE__SHIFT                                                             0x0
7310 #define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA__SHIFT                                         0x2
7311 #define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_50__SHIFT                                                         0x4
7312 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START__SHIFT                                                  0x6
7313 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP__SHIFT                                                   0x8
7314 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT                                                 0xa
7315 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_DRAW__SHIFT                                                   0xc
7316 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH__SHIFT                                                 0xe
7317 #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL__SHIFT                                             0x10
7318 #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP__SHIFT                                                0x12
7319 #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET__SHIFT                                               0x14
7320 #define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND__SHIFT                                                     0x16
7321 #define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC__SHIFT                                                  0x18
7322 #define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE__SHIFT                                                 0x1a
7323 #define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE__SHIFT                                              0x1c
7324 #define PA_SC_BINNER_EVENT_CNTL_3__DRAW_DONE__SHIFT                                                           0x1e
7325 #define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE_MASK                                                               0x00000003L
7326 #define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA_MASK                                           0x0000000CL
7327 #define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_50_MASK                                                           0x00000030L
7328 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START_MASK                                                    0x000000C0L
7329 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP_MASK                                                     0x00000300L
7330 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER_MASK                                                   0x00000C00L
7331 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_DRAW_MASK                                                     0x00003000L
7332 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH_MASK                                                   0x0000C000L
7333 #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL_MASK                                               0x00030000L
7334 #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP_MASK                                                  0x000C0000L
7335 #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET_MASK                                                 0x00300000L
7336 #define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND_MASK                                                       0x00C00000L
7337 #define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC_MASK                                                    0x03000000L
7338 #define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE_MASK                                                   0x0C000000L
7339 #define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE_MASK                                                0x30000000L
7340 #define PA_SC_BINNER_EVENT_CNTL_3__DRAW_DONE_MASK                                                             0xC0000000L
7341 //PA_SC_BINNER_TIMEOUT_COUNTER
7342 #define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD__SHIFT                                                        0x0
7343 #define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD_MASK                                                          0xFFFFFFFFL
7344 //PA_SC_BINNER_PERF_CNTL_0
7345 #define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD__SHIFT                                         0x0
7346 #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT                                       0xa
7347 #define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD__SHIFT                                       0x14
7348 #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD__SHIFT                                     0x17
7349 #define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD_MASK                                           0x000003FFL
7350 #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD_MASK                                         0x000FFC00L
7351 #define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD_MASK                                         0x00700000L
7352 #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD_MASK                                       0x03800000L
7353 //PA_SC_BINNER_PERF_CNTL_1
7354 #define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT                              0x0
7355 #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT                            0x5
7356 #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT                         0xa
7357 #define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK                                0x0000001FL
7358 #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK                              0x000003E0L
7359 #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD_MASK                           0x03FFFC00L
7360 //PA_SC_BINNER_PERF_CNTL_2
7361 #define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD__SHIFT                               0x0
7362 #define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD__SHIFT                             0xb
7363 #define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD_MASK                                 0x000007FFL
7364 #define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD_MASK                               0x003FF800L
7365 //PA_SC_BINNER_PERF_CNTL_3
7366 #define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD__SHIFT                              0x0
7367 #define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD_MASK                                0xFFFFFFFFL
7368 //PA_SC_ENHANCE_2
7369 #define PA_SC_ENHANCE_2__ECO_SPARE0__SHIFT                                                                    0x0
7370 #define PA_SC_ENHANCE_2__ECO_SPARE1__SHIFT                                                                    0x1
7371 #define PA_SC_ENHANCE_2__ECO_SPARE2__SHIFT                                                                    0x2
7372 #define PA_SC_ENHANCE_2__ECO_SPARE3__SHIFT                                                                    0x3
7373 #define PA_SC_ENHANCE_2__ENABLE_LPOV_WAVE_BREAK__SHIFT                                                        0x4
7374 #define PA_SC_ENHANCE_2__ENABLE_FPOV_WAVE_BREAK__SHIFT                                                        0x5
7375 #define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_COMPOUND_INDEX_EN__SHIFT                                   0x6
7376 #define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PRIM_PAYLOAD__SHIFT                                     0x7
7377 #define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPE_SWITCH__SHIFT                                        0x8
7378 #define PA_SC_ENHANCE_2__DISABLE_FULL_TILE_WAVE_BREAK__SHIFT                                                  0x9
7379 #define PA_SC_ENHANCE_2__ENABLE_VPZ_INJECTION_BEFORE_NULL_PRIMS__SHIFT                                        0xa
7380 #define PA_SC_ENHANCE_2__PBB_TIMEOUT_THRESHOLD_MODE__SHIFT                                                    0xb
7381 #define PA_SC_ENHANCE_2__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT                                              0xc
7382 #define PA_SC_ENHANCE_2__DISABLE_SC_SPI_INTF_EARLY_WAKEUP__SHIFT                                              0xd
7383 #define PA_SC_ENHANCE_2__DISABLE_SC_BCI_INTF_EARLY_WAKEUP__SHIFT                                              0xe
7384 #define PA_SC_ENHANCE_2__DISABLE_EXPOSED_GT_DETAIL_RATE_TILE_COV_ADJ__SHIFT                                   0xf
7385 #define PA_SC_ENHANCE_2__PBB_WARP_CLK_MAIN_CLK_WAKEUP__SHIFT                                                  0x10
7386 #define PA_SC_ENHANCE_2__PBB_MAIN_CLK_REG_BUSY_WAKEUP__SHIFT                                                  0x11
7387 #define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPELINE_RESET__SHIFT                                     0x12
7388 #define PA_SC_ENHANCE_2__ENABLE_BLOCKING_WRITES_OF_GEN1_REG__SHIFT                                            0x13
7389 #define PA_SC_ENHANCE_2__ENABLE_BLOCKING_WRITES_OF_GEN2_REG__SHIFT                                            0x14
7390 #define PA_SC_ENHANCE_2__DISABLE_SC_DBR_DATAPATH_FGCG__SHIFT                                                  0x15
7391 #define PA_SC_ENHANCE_2__PROCESS_RESET_FORCE_STILE_MASK_TO_ZERO__SHIFT                                        0x17
7392 #define PA_SC_ENHANCE_2__DISABLE_PBB_EOP_INSERTION_FOR_MIXED_BINNING_AND_IMMEDIATE__SHIFT                     0x18
7393 #define PA_SC_ENHANCE_2__DISABLE_DFSM_FLUSH__SHIFT                                                            0x19
7394 #define PA_SC_ENHANCE_2__BREAK_WHEN_ONE_NULL_PRIM_BATCH__SHIFT                                                0x1a
7395 #define PA_SC_ENHANCE_2__NULL_PRIM_BREAK_BATCH_LIMIT__SHIFT                                                   0x1b
7396 #define PA_SC_ENHANCE_2__RSVD__SHIFT                                                                          0x1e
7397 #define PA_SC_ENHANCE_2__ECO_SPARE0_MASK                                                                      0x00000001L
7398 #define PA_SC_ENHANCE_2__ECO_SPARE1_MASK                                                                      0x00000002L
7399 #define PA_SC_ENHANCE_2__ECO_SPARE2_MASK                                                                      0x00000004L
7400 #define PA_SC_ENHANCE_2__ECO_SPARE3_MASK                                                                      0x00000008L
7401 #define PA_SC_ENHANCE_2__ENABLE_LPOV_WAVE_BREAK_MASK                                                          0x00000010L
7402 #define PA_SC_ENHANCE_2__ENABLE_FPOV_WAVE_BREAK_MASK                                                          0x00000020L
7403 #define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_COMPOUND_INDEX_EN_MASK                                     0x00000040L
7404 #define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PRIM_PAYLOAD_MASK                                       0x00000080L
7405 #define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPE_SWITCH_MASK                                          0x00000100L
7406 #define PA_SC_ENHANCE_2__DISABLE_FULL_TILE_WAVE_BREAK_MASK                                                    0x00000200L
7407 #define PA_SC_ENHANCE_2__ENABLE_VPZ_INJECTION_BEFORE_NULL_PRIMS_MASK                                          0x00000400L
7408 #define PA_SC_ENHANCE_2__PBB_TIMEOUT_THRESHOLD_MODE_MASK                                                      0x00000800L
7409 #define PA_SC_ENHANCE_2__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK                                                0x00001000L
7410 #define PA_SC_ENHANCE_2__DISABLE_SC_SPI_INTF_EARLY_WAKEUP_MASK                                                0x00002000L
7411 #define PA_SC_ENHANCE_2__DISABLE_SC_BCI_INTF_EARLY_WAKEUP_MASK                                                0x00004000L
7412 #define PA_SC_ENHANCE_2__DISABLE_EXPOSED_GT_DETAIL_RATE_TILE_COV_ADJ_MASK                                     0x00008000L
7413 #define PA_SC_ENHANCE_2__PBB_WARP_CLK_MAIN_CLK_WAKEUP_MASK                                                    0x00010000L
7414 #define PA_SC_ENHANCE_2__PBB_MAIN_CLK_REG_BUSY_WAKEUP_MASK                                                    0x00020000L
7415 #define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPELINE_RESET_MASK                                       0x00040000L
7416 #define PA_SC_ENHANCE_2__ENABLE_BLOCKING_WRITES_OF_GEN1_REG_MASK                                              0x00080000L
7417 #define PA_SC_ENHANCE_2__ENABLE_BLOCKING_WRITES_OF_GEN2_REG_MASK                                              0x00100000L
7418 #define PA_SC_ENHANCE_2__DISABLE_SC_DBR_DATAPATH_FGCG_MASK                                                    0x00200000L
7419 #define PA_SC_ENHANCE_2__PROCESS_RESET_FORCE_STILE_MASK_TO_ZERO_MASK                                          0x00800000L
7420 #define PA_SC_ENHANCE_2__DISABLE_PBB_EOP_INSERTION_FOR_MIXED_BINNING_AND_IMMEDIATE_MASK                       0x01000000L
7421 #define PA_SC_ENHANCE_2__DISABLE_DFSM_FLUSH_MASK                                                              0x02000000L
7422 #define PA_SC_ENHANCE_2__BREAK_WHEN_ONE_NULL_PRIM_BATCH_MASK                                                  0x04000000L
7423 #define PA_SC_ENHANCE_2__NULL_PRIM_BREAK_BATCH_LIMIT_MASK                                                     0x38000000L
7424 #define PA_SC_ENHANCE_2__RSVD_MASK                                                                            0xC0000000L
7425 //PA_SC_ENHANCE_INTERNAL
7426 #define PA_SC_ENHANCE_INTERNAL__DISABLE_SRBSL_DB_OPTIMIZED_PACKING__SHIFT                                     0x0
7427 #define PA_SC_ENHANCE_INTERNAL__DISABLE_SRBSL_DB_OPTIMIZED_PACKING_MASK                                       0x00000001L
7428 //PA_SC_BINNER_CNTL_OVERRIDE
7429 #define PA_SC_BINNER_CNTL_OVERRIDE__BINNING_MODE__SHIFT                                                       0x0
7430 #define PA_SC_BINNER_CNTL_OVERRIDE__CONTEXT_STATES_PER_BIN__SHIFT                                             0xa
7431 #define PA_SC_BINNER_CNTL_OVERRIDE__PERSISTENT_STATES_PER_BIN__SHIFT                                          0xd
7432 #define PA_SC_BINNER_CNTL_OVERRIDE__FPOVS_PER_BATCH__SHIFT                                                    0x13
7433 #define PA_SC_BINNER_CNTL_OVERRIDE__DIRECT_OVERRIDE_MODE__SHIFT                                               0x1b
7434 #define PA_SC_BINNER_CNTL_OVERRIDE__OVERRIDE__SHIFT                                                           0x1c
7435 #define PA_SC_BINNER_CNTL_OVERRIDE__BINNING_MODE_MASK                                                         0x00000003L
7436 #define PA_SC_BINNER_CNTL_OVERRIDE__CONTEXT_STATES_PER_BIN_MASK                                               0x00001C00L
7437 #define PA_SC_BINNER_CNTL_OVERRIDE__PERSISTENT_STATES_PER_BIN_MASK                                            0x0003E000L
7438 #define PA_SC_BINNER_CNTL_OVERRIDE__FPOVS_PER_BATCH_MASK                                                      0x07F80000L
7439 #define PA_SC_BINNER_CNTL_OVERRIDE__DIRECT_OVERRIDE_MODE_MASK                                                 0x08000000L
7440 #define PA_SC_BINNER_CNTL_OVERRIDE__OVERRIDE_MASK                                                             0xF0000000L
7441 //PA_SC_PBB_OVERRIDE_FLAG
7442 #define PA_SC_PBB_OVERRIDE_FLAG__OVERRIDE__SHIFT                                                              0x0
7443 #define PA_SC_PBB_OVERRIDE_FLAG__PIPE_ID__SHIFT                                                               0x1
7444 #define PA_SC_PBB_OVERRIDE_FLAG__OVERRIDE_MASK                                                                0x00000001L
7445 #define PA_SC_PBB_OVERRIDE_FLAG__PIPE_ID_MASK                                                                 0x00000002L
7446 //PA_PH_INTERFACE_FIFO_SIZE
7447 #define PA_PH_INTERFACE_FIFO_SIZE__PA_PH_IF_FIFO_SIZE__SHIFT                                                  0x0
7448 #define PA_PH_INTERFACE_FIFO_SIZE__PH_SC_IF_FIFO_SIZE__SHIFT                                                  0x10
7449 #define PA_PH_INTERFACE_FIFO_SIZE__PA_PH_IF_FIFO_SIZE_MASK                                                    0x000003FFL
7450 #define PA_PH_INTERFACE_FIFO_SIZE__PH_SC_IF_FIFO_SIZE_MASK                                                    0x003F0000L
7451 //PA_PH_ENHANCE
7452 #define PA_PH_ENHANCE__ECO_SPARE0__SHIFT                                                                      0x0
7453 #define PA_PH_ENHANCE__ECO_SPARE1__SHIFT                                                                      0x1
7454 #define PA_PH_ENHANCE__ECO_SPARE2__SHIFT                                                                      0x2
7455 #define PA_PH_ENHANCE__ECO_SPARE3__SHIFT                                                                      0x3
7456 #define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_FINE_CLOCK_GATE__SHIFT                                              0x4
7457 #define PA_PH_ENHANCE__DISABLE_FOPKT__SHIFT                                                                   0x5
7458 #define PA_PH_ENHANCE__DISABLE_FOPKT_SCAN_POST_RESET__SHIFT                                                   0x6
7459 #define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_CLKEN_CLOCK_GATE__SHIFT                                             0x7
7460 #define PA_PH_ENHANCE__DISABLE_PH_PERF_REG_FGCG__SHIFT                                                        0x9
7461 #define PA_PH_ENHANCE__ENABLE_PH_INTF_CLKEN_STRETCH__SHIFT                                                    0xa
7462 #define PA_PH_ENHANCE__ECO_SPARE0_MASK                                                                        0x00000001L
7463 #define PA_PH_ENHANCE__ECO_SPARE1_MASK                                                                        0x00000002L
7464 #define PA_PH_ENHANCE__ECO_SPARE2_MASK                                                                        0x00000004L
7465 #define PA_PH_ENHANCE__ECO_SPARE3_MASK                                                                        0x00000008L
7466 #define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_FINE_CLOCK_GATE_MASK                                                0x00000010L
7467 #define PA_PH_ENHANCE__DISABLE_FOPKT_MASK                                                                     0x00000020L
7468 #define PA_PH_ENHANCE__DISABLE_FOPKT_SCAN_POST_RESET_MASK                                                     0x00000040L
7469 #define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_CLKEN_CLOCK_GATE_MASK                                               0x00000080L
7470 #define PA_PH_ENHANCE__DISABLE_PH_PERF_REG_FGCG_MASK                                                          0x00000200L
7471 #define PA_PH_ENHANCE__ENABLE_PH_INTF_CLKEN_STRETCH_MASK                                                      0x00001C00L
7472 //PA_SC_BC_WAVE_BREAK
7473 #define PA_SC_BC_WAVE_BREAK__MAX_DEALLOCS_IN_WAVE__SHIFT                                                      0x0
7474 #define PA_SC_BC_WAVE_BREAK__MAX_FPOVS_IN_WAVE__SHIFT                                                         0x10
7475 #define PA_SC_BC_WAVE_BREAK__MAX_DEALLOCS_IN_WAVE_MASK                                                        0x000007FFL
7476 #define PA_SC_BC_WAVE_BREAK__MAX_FPOVS_IN_WAVE_MASK                                                           0x00FF0000L
7477 //PA_SC_FIFO_SIZE
7478 #define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT                                                    0x0
7479 #define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT                                                     0x6
7480 #define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT                                                         0xf
7481 #define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT                                                      0x15
7482 #define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK                                                      0x0000003FL
7483 #define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK                                                       0x00007FC0L
7484 #define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK                                                           0x001F8000L
7485 #define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK                                                        0xFFE00000L
7486 //PA_SC_IF_FIFO_SIZE
7487 #define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT                                                    0x0
7488 #define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT                                                    0x6
7489 #define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT                                                        0xc
7490 #define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT                                                        0x12
7491 #define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK                                                      0x0000003FL
7492 #define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK                                                      0x00000FC0L
7493 #define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK                                                          0x0003F000L
7494 #define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK                                                          0x00FC0000L
7495 //PA_SC_PKR_WAVE_TABLE_CNTL
7496 #define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE__SHIFT                                                                0x0
7497 #define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK                                                                  0x0000003FL
7498 //PA_SIDEBAND_REQUEST_DELAYS
7499 #define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY__SHIFT                                                        0x0
7500 #define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY__SHIFT                                                      0x10
7501 #define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY_MASK                                                          0x0000FFFFL
7502 #define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY_MASK                                                        0xFFFF0000L
7503 //PA_SC_ENHANCE
7504 #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT                                                       0x0
7505 #define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT                                                          0x1
7506 #define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT                                                        0x2
7507 #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT                                                  0x3
7508 #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT                                               0x4
7509 #define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT                                                             0x5
7510 #define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT                                                     0x6
7511 #define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT                                              0x7
7512 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT                                                   0x8
7513 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT                                              0x9
7514 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT                                                   0xa
7515 #define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT                                                          0xb
7516 #define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT                                          0xc
7517 #define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT                                                 0xd
7518 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT                                             0xe
7519 #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT                                                   0xf
7520 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT                                   0x10
7521 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT                                        0x11
7522 #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT                               0x12
7523 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT                               0x13
7524 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT                              0x14
7525 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT                                 0x15
7526 #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT                                   0x16
7527 #define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT                           0x17
7528 #define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT                                          0x18
7529 #define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT                                       0x19
7530 #define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT                                                  0x1a
7531 #define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT                                              0x1b
7532 #define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT                      0x1c
7533 #define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING__SHIFT                              0x1d
7534 #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK                                                         0x00000001L
7535 #define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK                                                            0x00000002L
7536 #define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK                                                          0x00000004L
7537 #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK                                                    0x00000008L
7538 #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK                                                 0x00000010L
7539 #define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK                                                               0x00000020L
7540 #define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK                                                       0x00000040L
7541 #define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK                                                0x00000080L
7542 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK                                                     0x00000100L
7543 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK                                                0x00000200L
7544 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK                                                     0x00000400L
7545 #define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK                                                            0x00000800L
7546 #define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK                                            0x00001000L
7547 #define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK                                                   0x00002000L
7548 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK                                               0x00004000L
7549 #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK                                                     0x00008000L
7550 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK                                     0x00010000L
7551 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK                                          0x00020000L
7552 #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK                                 0x00040000L
7553 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK                                 0x00080000L
7554 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK                                0x00100000L
7555 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK                                   0x00200000L
7556 #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK                                     0x00400000L
7557 #define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK                             0x00800000L
7558 #define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK                                            0x01000000L
7559 #define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK                                         0x02000000L
7560 #define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK                                                    0x04000000L
7561 #define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK                                                0x08000000L
7562 #define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE_MASK                        0x10000000L
7563 #define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING_MASK                                0x20000000L
7564 //PA_SC_ENHANCE_1
7565 #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT                                                0x0
7566 #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT                                                       0x1
7567 #define PA_SC_ENHANCE_1__DISABLE_SC_BINNING__SHIFT                                                            0x3
7568 #define PA_SC_ENHANCE_1__BYPASS_PBB__SHIFT                                                                    0x4
7569 #define PA_SC_ENHANCE_1__ECO_SPARE0__SHIFT                                                                    0x5
7570 #define PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT                                                                    0x6
7571 #define PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT                                                                    0x7
7572 #define PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT                                                                    0x8
7573 #define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB__SHIFT                                                  0x9
7574 #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT                                                       0xa
7575 #define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM__SHIFT                                     0xb
7576 #define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE__SHIFT                                       0xe
7577 #define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION__SHIFT                              0xf
7578 #define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE__SHIFT                                                    0x10
7579 #define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING__SHIFT                                       0x11
7580 #define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION__SHIFT                                                         0x12
7581 #define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS__SHIFT                                                  0x13
7582 #define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION__SHIFT                                                  0x14
7583 #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION__SHIFT                                          0x15
7584 #define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION__SHIFT                                          0x16
7585 #define PA_SC_ENHANCE_1__DISABLE_INTF_CG__SHIFT                                                               0x17
7586 #define PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT                                        0x18
7587 #define PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER__SHIFT                                            0x19
7588 #define PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION__SHIFT                                                   0x1a
7589 #define PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE__SHIFT                                                0x1b
7590 #define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX__SHIFT                                                  0x1c
7591 #define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1__SHIFT                                                0x1d
7592 #define PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI__SHIFT                                                         0x1e
7593 #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK                                                  0x00000001L
7594 #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK                                                         0x00000006L
7595 #define PA_SC_ENHANCE_1__DISABLE_SC_BINNING_MASK                                                              0x00000008L
7596 #define PA_SC_ENHANCE_1__BYPASS_PBB_MASK                                                                      0x00000010L
7597 #define PA_SC_ENHANCE_1__ECO_SPARE0_MASK                                                                      0x00000020L
7598 #define PA_SC_ENHANCE_1__ECO_SPARE1_MASK                                                                      0x00000040L
7599 #define PA_SC_ENHANCE_1__ECO_SPARE2_MASK                                                                      0x00000080L
7600 #define PA_SC_ENHANCE_1__ECO_SPARE3_MASK                                                                      0x00000100L
7601 #define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB_MASK                                                    0x00000200L
7602 #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT_MASK                                                         0x00000400L
7603 #define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM_MASK                                       0x00000800L
7604 #define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE_MASK                                         0x00004000L
7605 #define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION_MASK                                0x00008000L
7606 #define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE_MASK                                                      0x00010000L
7607 #define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING_MASK                                         0x00020000L
7608 #define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION_MASK                                                           0x00040000L
7609 #define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS_MASK                                                    0x00080000L
7610 #define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION_MASK                                                    0x00100000L
7611 #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION_MASK                                            0x00200000L
7612 #define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION_MASK                                            0x00400000L
7613 #define PA_SC_ENHANCE_1__DISABLE_INTF_CG_MASK                                                                 0x00800000L
7614 #define PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK                                          0x01000000L
7615 #define PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER_MASK                                              0x02000000L
7616 #define PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION_MASK                                                     0x04000000L
7617 #define PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE_MASK                                                  0x08000000L
7618 #define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_MASK                                                    0x10000000L
7619 #define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1_MASK                                                  0x20000000L
7620 #define PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI_MASK                                                           0x40000000L
7621 //PA_SC_DSM_CNTL
7622 #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT                                                                0x0
7623 #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT                                                                0x1
7624 #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK                                                                  0x00000001L
7625 #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK                                                                  0x00000002L
7626 //PA_SC_TILE_STEERING_CREST_OVERRIDE
7627 #define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE__SHIFT                                         0x0
7628 #define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT__SHIFT                                                  0x1
7629 #define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT__SHIFT                                                  0x5
7630 #define PA_SC_TILE_STEERING_CREST_OVERRIDE__SA_SELECT__SHIFT                                                  0x8
7631 #define PA_SC_TILE_STEERING_CREST_OVERRIDE__FORCE_TILE_STEERING_OVERRIDE_USE__SHIFT                           0x1f
7632 #define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE_MASK                                           0x00000001L
7633 #define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT_MASK                                                    0x00000006L
7634 #define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT_MASK                                                    0x00000060L
7635 #define PA_SC_TILE_STEERING_CREST_OVERRIDE__SA_SELECT_MASK                                                    0x00000700L
7636 #define PA_SC_TILE_STEERING_CREST_OVERRIDE__FORCE_TILE_STEERING_OVERRIDE_USE_MASK                             0x80000000L
7637 
7638 
7639 // addressBlock: gc_sqdec
7640 //SQ_CONFIG
7641 #define SQ_CONFIG__UNUSED__SHIFT                                                                              0x0
7642 #define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY__SHIFT                                                               0xb
7643 #define SQ_CONFIG__VGPR_SWIZZLE_EN__SHIFT                                                                     0xc
7644 #define SQ_CONFIG__LDS_BUSY_HYSTERESIS_CNT__SHIFT                                                             0xd
7645 #define SQ_CONFIG__SP_BUSY_HYSTERESIS_CNT__SHIFT                                                              0xf
7646 #define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT                                                         0x12
7647 #define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT                                                              0x13
7648 #define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT                                                                    0x15
7649 #define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING__SHIFT                                                  0x1d
7650 #define SQ_CONFIG__TA_BUSY_HYSTERESIS_CNT__SHIFT                                                              0x1e
7651 #define SQ_CONFIG__UNUSED_MASK                                                                                0x0000007FL
7652 #define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY_MASK                                                                 0x00000800L
7653 #define SQ_CONFIG__VGPR_SWIZZLE_EN_MASK                                                                       0x00001000L
7654 #define SQ_CONFIG__LDS_BUSY_HYSTERESIS_CNT_MASK                                                               0x00006000L
7655 #define SQ_CONFIG__SP_BUSY_HYSTERESIS_CNT_MASK                                                                0x00018000L
7656 #define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK                                                           0x00040000L
7657 #define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK                                                                0x00180000L
7658 #define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK                                                                      0x0FE00000L
7659 #define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING_MASK                                                    0x20000000L
7660 #define SQ_CONFIG__TA_BUSY_HYSTERESIS_CNT_MASK                                                                0xC0000000L
7661 //SQC_CONFIG
7662 #define SQC_CONFIG__INST_CACHE_SIZE__SHIFT                                                                    0x0
7663 #define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT                                                                    0x2
7664 #define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT                                                                    0x4
7665 #define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT                                                                     0x6
7666 #define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT                                                                  0x7
7667 #define SQC_CONFIG__FORCE_IN_ORDER__SHIFT                                                                     0x8
7668 #define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT                                                                 0x9
7669 #define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT                                                                  0xa
7670 #define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT                                                               0xb
7671 #define SQC_CONFIG__EVICT_LRU__SHIFT                                                                          0xc
7672 #define SQC_CONFIG__FORCE_2_BANK__SHIFT                                                                       0xe
7673 #define SQC_CONFIG__FORCE_1_BANK__SHIFT                                                                       0xf
7674 #define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT                                                                  0x10
7675 #define SQC_CONFIG__INST_CACHE_SIZE_MASK                                                                      0x00000003L
7676 #define SQC_CONFIG__DATA_CACHE_SIZE_MASK                                                                      0x0000000CL
7677 #define SQC_CONFIG__MISS_FIFO_DEPTH_MASK                                                                      0x00000030L
7678 #define SQC_CONFIG__HIT_FIFO_DEPTH_MASK                                                                       0x00000040L
7679 #define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK                                                                    0x00000080L
7680 #define SQC_CONFIG__FORCE_IN_ORDER_MASK                                                                       0x00000100L
7681 #define SQC_CONFIG__IDENTITY_HASH_BANK_MASK                                                                   0x00000200L
7682 #define SQC_CONFIG__IDENTITY_HASH_SET_MASK                                                                    0x00000400L
7683 #define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK                                                                 0x00000800L
7684 #define SQC_CONFIG__EVICT_LRU_MASK                                                                            0x00003000L
7685 #define SQC_CONFIG__FORCE_2_BANK_MASK                                                                         0x00004000L
7686 #define SQC_CONFIG__FORCE_1_BANK_MASK                                                                         0x00008000L
7687 #define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK                                                                    0x00FF0000L
7688 //LDS_CONFIG
7689 #define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING__SHIFT                                                        0x0
7690 #define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING_MASK                                                          0x00000001L
7691 //SQ_RANDOM_WAVE_PRI
7692 #define SQ_RANDOM_WAVE_PRI__RET__SHIFT                                                                        0x0
7693 #define SQ_RANDOM_WAVE_PRI__RUI__SHIFT                                                                        0x7
7694 #define SQ_RANDOM_WAVE_PRI__RNG__SHIFT                                                                        0xa
7695 #define SQ_RANDOM_WAVE_PRI__RET_MASK                                                                          0x0000007FL
7696 #define SQ_RANDOM_WAVE_PRI__RUI_MASK                                                                          0x00000380L
7697 #define SQ_RANDOM_WAVE_PRI__RNG_MASK                                                                          0x00FFFC00L
7698 //SQG_STATUS
7699 #define SQG_STATUS__REG_BUSY__SHIFT                                                                           0x0
7700 #define SQG_STATUS__REG_BUSY_MASK                                                                             0x00000001L
7701 //SQ_FIFO_SIZES
7702 #define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT                                                             0x0
7703 #define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT                                                                0x8
7704 #define SQ_FIFO_SIZES__EXPORT_BUF_VS_RESERVED__SHIFT                                                          0xc
7705 #define SQ_FIFO_SIZES__EXPORT_BUF_PS_RESERVED__SHIFT                                                          0xe
7706 #define SQ_FIFO_SIZES__EXPORT_BUF_REDUCE__SHIFT                                                               0x10
7707 #define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT                                                             0x12
7708 #define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK                                                               0x0000000FL
7709 #define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK                                                                  0x00000300L
7710 #define SQ_FIFO_SIZES__EXPORT_BUF_VS_RESERVED_MASK                                                            0x00003000L
7711 #define SQ_FIFO_SIZES__EXPORT_BUF_PS_RESERVED_MASK                                                            0x0000C000L
7712 #define SQ_FIFO_SIZES__EXPORT_BUF_REDUCE_MASK                                                                 0x00030000L
7713 #define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK                                                               0x000C0000L
7714 //SQ_DSM_CNTL
7715 #define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT                                                                 0x0
7716 #define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT                                                                 0x1
7717 #define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT                                                                0x2
7718 #define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT                                                                0x3
7719 #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT                                                      0x8
7720 #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT                                                      0x9
7721 #define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT                                                          0xa
7722 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT                                                       0x10
7723 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT                                                       0x11
7724 #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT                                                         0x12
7725 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT                                                       0x13
7726 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT                                                       0x14
7727 #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT                                                         0x15
7728 #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT                                                        0x18
7729 #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT                                                        0x19
7730 #define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT                                                            0x1a
7731 #define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK                                                                   0x00000001L
7732 #define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK                                                                   0x00000002L
7733 #define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK                                                                  0x00000004L
7734 #define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK                                                                  0x00000008L
7735 #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK                                                        0x00000100L
7736 #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK                                                        0x00000200L
7737 #define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK                                                            0x00000400L
7738 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK                                                         0x00010000L
7739 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK                                                         0x00020000L
7740 #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK                                                           0x00040000L
7741 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK                                                         0x00080000L
7742 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK                                                         0x00100000L
7743 #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK                                                           0x00200000L
7744 #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK                                                          0x01000000L
7745 #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK                                                          0x02000000L
7746 #define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK                                                              0x04000000L
7747 //SQ_DSM_CNTL2
7748 #define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT__SHIFT                                                         0x0
7749 #define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY__SHIFT                                                         0x2
7750 #define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT__SHIFT                                                        0x3
7751 #define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY__SHIFT                                                        0x5
7752 #define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT__SHIFT                                                        0x6
7753 #define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY__SHIFT                                                        0x8
7754 #define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT__SHIFT                                                           0x9
7755 #define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY__SHIFT                                                           0xb
7756 #define SQ_DSM_CNTL2__LDS_INJECT_DELAY__SHIFT                                                                 0xe
7757 #define SQ_DSM_CNTL2__SP_INJECT_DELAY__SHIFT                                                                  0x14
7758 #define SQ_DSM_CNTL2__SQ_INJECT_DELAY__SHIFT                                                                  0x1a
7759 #define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT_MASK                                                           0x00000003L
7760 #define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY_MASK                                                           0x00000004L
7761 #define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT_MASK                                                          0x00000018L
7762 #define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY_MASK                                                          0x00000020L
7763 #define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT_MASK                                                          0x000000C0L
7764 #define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY_MASK                                                          0x00000100L
7765 #define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT_MASK                                                             0x00000600L
7766 #define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY_MASK                                                             0x00000800L
7767 #define SQ_DSM_CNTL2__LDS_INJECT_DELAY_MASK                                                                   0x000FC000L
7768 #define SQ_DSM_CNTL2__SP_INJECT_DELAY_MASK                                                                    0x03F00000L
7769 #define SQ_DSM_CNTL2__SQ_INJECT_DELAY_MASK                                                                    0xFC000000L
7770 //SQ_RUNTIME_CONFIG
7771 #define SQ_RUNTIME_CONFIG__UNUSED_REGISTER__SHIFT                                                             0x0
7772 #define SQ_RUNTIME_CONFIG__UNUSED_REGISTER_MASK                                                               0x00000001L
7773 //SH_MEM_BASES
7774 #define SH_MEM_BASES__PRIVATE_BASE__SHIFT                                                                     0x0
7775 #define SH_MEM_BASES__SHARED_BASE__SHIFT                                                                      0x10
7776 #define SH_MEM_BASES__PRIVATE_BASE_MASK                                                                       0x0000FFFFL
7777 #define SH_MEM_BASES__SHARED_BASE_MASK                                                                        0xFFFF0000L
7778 //SP_CONFIG
7779 #define SP_CONFIG__DEST_CACHE_EVICT_COUNTER__SHIFT                                                            0x0
7780 #define SP_CONFIG__ALU_BUSY_MGCG_OVERRIDE__SHIFT                                                              0x2
7781 #define SP_CONFIG__DISABLE_TRANS_COEXEC__SHIFT                                                                0x3
7782 #define SP_CONFIG__TRANS_MGCG_OVERRIDE__SHIFT                                                                 0x4
7783 #define SP_CONFIG__CAC_COUNTER_OVERRIDE__SHIFT                                                                0x5
7784 #define SP_CONFIG__DPMACC_MGCG_OVERRIDE__SHIFT                                                                0x6
7785 #define SP_CONFIG__SMACC_MGCG_OVERRIDE__SHIFT                                                                 0x7
7786 #define SP_CONFIG__UNUSED__SHIFT                                                                              0x8
7787 #define SP_CONFIG__DEST_CACHE_EVICT_COUNTER_MASK                                                              0x00000003L
7788 #define SP_CONFIG__ALU_BUSY_MGCG_OVERRIDE_MASK                                                                0x00000004L
7789 #define SP_CONFIG__DISABLE_TRANS_COEXEC_MASK                                                                  0x00000008L
7790 #define SP_CONFIG__TRANS_MGCG_OVERRIDE_MASK                                                                   0x00000010L
7791 #define SP_CONFIG__CAC_COUNTER_OVERRIDE_MASK                                                                  0x00000020L
7792 #define SP_CONFIG__DPMACC_MGCG_OVERRIDE_MASK                                                                  0x00000040L
7793 #define SP_CONFIG__SMACC_MGCG_OVERRIDE_MASK                                                                   0x00000080L
7794 #define SP_CONFIG__UNUSED_MASK                                                                                0x00000100L
7795 //SQ_ARB_CONFIG
7796 #define SQ_ARB_CONFIG__WG_RR_INTERVAL__SHIFT                                                                  0x0
7797 #define SQ_ARB_CONFIG__FWD_PROG_INTERVAL__SHIFT                                                               0x4
7798 #define SQ_ARB_CONFIG__DISABLE_SECOND_TRY__SHIFT                                                              0x8
7799 #define SQ_ARB_CONFIG__WG_RR_INTERVAL_MASK                                                                    0x00000003L
7800 #define SQ_ARB_CONFIG__FWD_PROG_INTERVAL_MASK                                                                 0x00000030L
7801 #define SQ_ARB_CONFIG__DISABLE_SECOND_TRY_MASK                                                                0x00000100L
7802 //SH_MEM_CONFIG
7803 #define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT                                                                    0x0
7804 #define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT                                                                  0x2
7805 #define SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT                                                                   0x4
7806 #define SH_MEM_CONFIG__RETRY_MODE__SHIFT                                                                      0xc
7807 #define SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT                                                           0xe
7808 #define SH_MEM_CONFIG__NO_PREFETCH_ACROSS_PAGE__SHIFT                                                         0x10
7809 #define SH_MEM_CONFIG__ILLEGAL_INST_CHECK_DISABLE__SHIFT                                                      0x11
7810 #define SH_MEM_CONFIG__ICACHE_USE_GL1__SHIFT                                                                  0x12
7811 #define SH_MEM_CONFIG__ADDRESS_MODE_MASK                                                                      0x00000001L
7812 #define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK                                                                    0x0000000CL
7813 #define SH_MEM_CONFIG__DEFAULT_MTYPE_MASK                                                                     0x00000070L
7814 #define SH_MEM_CONFIG__RETRY_MODE_MASK                                                                        0x00003000L
7815 #define SH_MEM_CONFIG__INITIAL_INST_PREFETCH_MASK                                                             0x0000C000L
7816 #define SH_MEM_CONFIG__NO_PREFETCH_ACROSS_PAGE_MASK                                                           0x00010000L
7817 #define SH_MEM_CONFIG__ILLEGAL_INST_CHECK_DISABLE_MASK                                                        0x00020000L
7818 #define SH_MEM_CONFIG__ICACHE_USE_GL1_MASK                                                                    0x00040000L
7819 //CC_GC_SHADER_RATE_CONFIG
7820 #define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT                                                            0x1
7821 #define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT                                                  0x3
7822 #define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK                                                              0x00000006L
7823 #define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK                                                    0x00000008L
7824 //GC_USER_SHADER_RATE_CONFIG
7825 #define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT                                                          0x1
7826 #define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT                                                0x3
7827 #define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK                                                            0x00000006L
7828 #define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK                                                  0x00000008L
7829 //SQ_INTERRUPT_AUTO_MASK
7830 #define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT                                                                   0x0
7831 #define SQ_INTERRUPT_AUTO_MASK__MASK_MASK                                                                     0x00FFFFFFL
7832 //SQ_INTERRUPT_MSG_CTRL
7833 #define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT                                                                   0x0
7834 #define SQ_INTERRUPT_MSG_CTRL__STALL_MASK                                                                     0x00000001L
7835 //SQG_UTCL0_CNTL1
7836 #define SQG_UTCL0_CNTL1__FORCE_4K_L2_RESP__SHIFT                                                              0x0
7837 #define SQG_UTCL0_CNTL1__GPUVM_64K_DEF__SHIFT                                                                 0x1
7838 #define SQG_UTCL0_CNTL1__GPUVM_PERM_MODE__SHIFT                                                               0x2
7839 #define SQG_UTCL0_CNTL1__RESP_MODE__SHIFT                                                                     0x3
7840 #define SQG_UTCL0_CNTL1__RESP_FAULT_MODE__SHIFT                                                               0x5
7841 #define SQG_UTCL0_CNTL1__CLIENTID__SHIFT                                                                      0x7
7842 #define SQG_UTCL0_CNTL1__RESERVED__SHIFT                                                                      0x10
7843 #define SQG_UTCL0_CNTL1__ENABLE_PUSH_LFIFO__SHIFT                                                             0x11
7844 #define SQG_UTCL0_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT                                                          0x12
7845 #define SQG_UTCL0_CNTL1__REG_INV_VMID__SHIFT                                                                  0x13
7846 #define SQG_UTCL0_CNTL1__REG_INV_ALL_VMID__SHIFT                                                              0x17
7847 #define SQG_UTCL0_CNTL1__REG_INV_TOGGLE__SHIFT                                                                0x18
7848 #define SQG_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT                                                    0x19
7849 #define SQG_UTCL0_CNTL1__FORCE_MISS__SHIFT                                                                    0x1a
7850 #define SQG_UTCL0_CNTL1__FORCE_IN_ORDER__SHIFT                                                                0x1b
7851 #define SQG_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT                                                        0x1c
7852 #define SQG_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT                                                        0x1e
7853 #define SQG_UTCL0_CNTL1__FORCE_4K_L2_RESP_MASK                                                                0x00000001L
7854 #define SQG_UTCL0_CNTL1__GPUVM_64K_DEF_MASK                                                                   0x00000002L
7855 #define SQG_UTCL0_CNTL1__GPUVM_PERM_MODE_MASK                                                                 0x00000004L
7856 #define SQG_UTCL0_CNTL1__RESP_MODE_MASK                                                                       0x00000018L
7857 #define SQG_UTCL0_CNTL1__RESP_FAULT_MODE_MASK                                                                 0x00000060L
7858 #define SQG_UTCL0_CNTL1__CLIENTID_MASK                                                                        0x0000FF80L
7859 #define SQG_UTCL0_CNTL1__RESERVED_MASK                                                                        0x00010000L
7860 #define SQG_UTCL0_CNTL1__ENABLE_PUSH_LFIFO_MASK                                                               0x00020000L
7861 #define SQG_UTCL0_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK                                                            0x00040000L
7862 #define SQG_UTCL0_CNTL1__REG_INV_VMID_MASK                                                                    0x00780000L
7863 #define SQG_UTCL0_CNTL1__REG_INV_ALL_VMID_MASK                                                                0x00800000L
7864 #define SQG_UTCL0_CNTL1__REG_INV_TOGGLE_MASK                                                                  0x01000000L
7865 #define SQG_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK                                                      0x02000000L
7866 #define SQG_UTCL0_CNTL1__FORCE_MISS_MASK                                                                      0x04000000L
7867 #define SQG_UTCL0_CNTL1__FORCE_IN_ORDER_MASK                                                                  0x08000000L
7868 #define SQG_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK                                                          0x30000000L
7869 #define SQG_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK                                                          0xC0000000L
7870 //SQG_UTCL0_CNTL2
7871 #define SQG_UTCL0_CNTL2__SPARE__SHIFT                                                                         0x0
7872 #define SQG_UTCL0_CNTL2__LFIFO_SCAN_DISABLE__SHIFT                                                            0x8
7873 #define SQG_UTCL0_CNTL2__MTYPE_OVRD_DIS__SHIFT                                                                0x9
7874 #define SQG_UTCL0_CNTL2__LINE_VALID__SHIFT                                                                    0xa
7875 #define SQG_UTCL0_CNTL2__DIS_EDC__SHIFT                                                                       0xb
7876 #define SQG_UTCL0_CNTL2__GPUVM_INV_MODE__SHIFT                                                                0xc
7877 #define SQG_UTCL0_CNTL2__SHOOTDOWN_OPT__SHIFT                                                                 0xd
7878 #define SQG_UTCL0_CNTL2__FORCE_SNOOP__SHIFT                                                                   0xe
7879 #define SQG_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT                                                           0xf
7880 #define SQG_UTCL0_CNTL2__ARB_BURST_MODE__SHIFT                                                                0x10
7881 #define SQG_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT                                                       0x12
7882 #define SQG_UTCL0_CNTL2__PERF_EVENT_RD_WR__SHIFT                                                              0x13
7883 #define SQG_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT                                                        0x14
7884 #define SQG_UTCL0_CNTL2__PERF_EVENT_VMID__SHIFT                                                               0x15
7885 #define SQG_UTCL0_CNTL2__DIS_DUAL_L2_REQ__SHIFT                                                               0x19
7886 #define SQG_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT                                                          0x1a
7887 #define SQG_UTCL0_CNTL2__PERM_MODE_OVRD__SHIFT                                                                0x1b
7888 #define SQG_UTCL0_CNTL2__LINE_INVALIDATE_OPT__SHIFT                                                           0x1c
7889 #define SQG_UTCL0_CNTL2__GPUVM_16K_DEF__SHIFT                                                                 0x1d
7890 #define SQG_UTCL0_CNTL2__RESERVED__SHIFT                                                                      0x1e
7891 #define SQG_UTCL0_CNTL2__SPARE_MASK                                                                           0x000000FFL
7892 #define SQG_UTCL0_CNTL2__LFIFO_SCAN_DISABLE_MASK                                                              0x00000100L
7893 #define SQG_UTCL0_CNTL2__MTYPE_OVRD_DIS_MASK                                                                  0x00000200L
7894 #define SQG_UTCL0_CNTL2__LINE_VALID_MASK                                                                      0x00000400L
7895 #define SQG_UTCL0_CNTL2__DIS_EDC_MASK                                                                         0x00000800L
7896 #define SQG_UTCL0_CNTL2__GPUVM_INV_MODE_MASK                                                                  0x00001000L
7897 #define SQG_UTCL0_CNTL2__SHOOTDOWN_OPT_MASK                                                                   0x00002000L
7898 #define SQG_UTCL0_CNTL2__FORCE_SNOOP_MASK                                                                     0x00004000L
7899 #define SQG_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK_MASK                                                             0x00008000L
7900 #define SQG_UTCL0_CNTL2__ARB_BURST_MODE_MASK                                                                  0x00030000L
7901 #define SQG_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK                                                         0x00040000L
7902 #define SQG_UTCL0_CNTL2__PERF_EVENT_RD_WR_MASK                                                                0x00080000L
7903 #define SQG_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID_MASK                                                          0x00100000L
7904 #define SQG_UTCL0_CNTL2__PERF_EVENT_VMID_MASK                                                                 0x01E00000L
7905 #define SQG_UTCL0_CNTL2__DIS_DUAL_L2_REQ_MASK                                                                 0x02000000L
7906 #define SQG_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K_MASK                                                            0x04000000L
7907 #define SQG_UTCL0_CNTL2__PERM_MODE_OVRD_MASK                                                                  0x08000000L
7908 #define SQG_UTCL0_CNTL2__LINE_INVALIDATE_OPT_MASK                                                             0x10000000L
7909 #define SQG_UTCL0_CNTL2__GPUVM_16K_DEF_MASK                                                                   0x20000000L
7910 #define SQG_UTCL0_CNTL2__RESERVED_MASK                                                                        0xC0000000L
7911 //SQG_UTCL0_STATUS
7912 #define SQG_UTCL0_STATUS__FAULT_DETECTED__SHIFT                                                               0x0
7913 #define SQG_UTCL0_STATUS__RETRY_DETECTED__SHIFT                                                               0x1
7914 #define SQG_UTCL0_STATUS__PRT_DETECTED__SHIFT                                                                 0x2
7915 #define SQG_UTCL0_STATUS__RESERVED__SHIFT                                                                     0x3
7916 #define SQG_UTCL0_STATUS__UNUSED__SHIFT                                                                       0x8
7917 #define SQG_UTCL0_STATUS__FAULT_DETECTED_MASK                                                                 0x00000001L
7918 #define SQG_UTCL0_STATUS__RETRY_DETECTED_MASK                                                                 0x00000002L
7919 #define SQG_UTCL0_STATUS__PRT_DETECTED_MASK                                                                   0x00000004L
7920 #define SQG_UTCL0_STATUS__RESERVED_MASK                                                                       0x000000F8L
7921 #define SQG_UTCL0_STATUS__UNUSED_MASK                                                                         0xFFFFFF00L
7922 //SQG_CONFIG
7923 #define SQG_CONFIG__UTCL0_PREFETCH_PAGE__SHIFT                                                                0x0
7924 #define SQG_CONFIG__UTCL0_RETRY_TIMER__SHIFT                                                                  0x4
7925 #define SQG_CONFIG__UTCL0_PREFETCH_PAGE_MASK                                                                  0x0000000FL
7926 #define SQG_CONFIG__UTCL0_RETRY_TIMER_MASK                                                                    0x000007F0L
7927 //SQ_SHADER_TBA_LO
7928 #define SQ_SHADER_TBA_LO__ADDR_LO__SHIFT                                                                      0x0
7929 #define SQ_SHADER_TBA_LO__ADDR_LO_MASK                                                                        0xFFFFFFFFL
7930 //SQ_SHADER_TBA_HI
7931 #define SQ_SHADER_TBA_HI__ADDR_HI__SHIFT                                                                      0x0
7932 #define SQ_SHADER_TBA_HI__TRAP_EN__SHIFT                                                                      0x1f
7933 #define SQ_SHADER_TBA_HI__ADDR_HI_MASK                                                                        0x000000FFL
7934 #define SQ_SHADER_TBA_HI__TRAP_EN_MASK                                                                        0x80000000L
7935 //SQ_SHADER_TMA_LO
7936 #define SQ_SHADER_TMA_LO__ADDR_LO__SHIFT                                                                      0x0
7937 #define SQ_SHADER_TMA_LO__ADDR_LO_MASK                                                                        0xFFFFFFFFL
7938 //SQ_SHADER_TMA_HI
7939 #define SQ_SHADER_TMA_HI__ADDR_HI__SHIFT                                                                      0x0
7940 #define SQ_SHADER_TMA_HI__ADDR_HI_MASK                                                                        0x000000FFL
7941 //SQ_WATCH0_ADDR_H
7942 #define SQ_WATCH0_ADDR_H__ADDR__SHIFT                                                                         0x0
7943 #define SQ_WATCH0_ADDR_H__ADDR_MASK                                                                           0x0000FFFFL
7944 //SQ_WATCH0_ADDR_L
7945 #define SQ_WATCH0_ADDR_L__ADDR__SHIFT                                                                         0x6
7946 #define SQ_WATCH0_ADDR_L__ADDR_MASK                                                                           0xFFFFFFC0L
7947 //SQ_WATCH0_CNTL
7948 #define SQ_WATCH0_CNTL__MASK__SHIFT                                                                           0x0
7949 #define SQ_WATCH0_CNTL__VMID__SHIFT                                                                           0x18
7950 #define SQ_WATCH0_CNTL__MODE__SHIFT                                                                           0x1d
7951 #define SQ_WATCH0_CNTL__VALID__SHIFT                                                                          0x1f
7952 #define SQ_WATCH0_CNTL__MASK_MASK                                                                             0x00FFFFFFL
7953 #define SQ_WATCH0_CNTL__VMID_MASK                                                                             0x0F000000L
7954 #define SQ_WATCH0_CNTL__MODE_MASK                                                                             0x60000000L
7955 #define SQ_WATCH0_CNTL__VALID_MASK                                                                            0x80000000L
7956 //SQ_WATCH1_ADDR_H
7957 #define SQ_WATCH1_ADDR_H__ADDR__SHIFT                                                                         0x0
7958 #define SQ_WATCH1_ADDR_H__ADDR_MASK                                                                           0x0000FFFFL
7959 //SQ_WATCH1_ADDR_L
7960 #define SQ_WATCH1_ADDR_L__ADDR__SHIFT                                                                         0x6
7961 #define SQ_WATCH1_ADDR_L__ADDR_MASK                                                                           0xFFFFFFC0L
7962 //SQ_WATCH1_CNTL
7963 #define SQ_WATCH1_CNTL__MASK__SHIFT                                                                           0x0
7964 #define SQ_WATCH1_CNTL__VMID__SHIFT                                                                           0x18
7965 #define SQ_WATCH1_CNTL__MODE__SHIFT                                                                           0x1d
7966 #define SQ_WATCH1_CNTL__VALID__SHIFT                                                                          0x1f
7967 #define SQ_WATCH1_CNTL__MASK_MASK                                                                             0x00FFFFFFL
7968 #define SQ_WATCH1_CNTL__VMID_MASK                                                                             0x0F000000L
7969 #define SQ_WATCH1_CNTL__MODE_MASK                                                                             0x60000000L
7970 #define SQ_WATCH1_CNTL__VALID_MASK                                                                            0x80000000L
7971 //SQ_WATCH2_ADDR_H
7972 #define SQ_WATCH2_ADDR_H__ADDR__SHIFT                                                                         0x0
7973 #define SQ_WATCH2_ADDR_H__ADDR_MASK                                                                           0x0000FFFFL
7974 //SQ_WATCH2_ADDR_L
7975 #define SQ_WATCH2_ADDR_L__ADDR__SHIFT                                                                         0x6
7976 #define SQ_WATCH2_ADDR_L__ADDR_MASK                                                                           0xFFFFFFC0L
7977 //SQ_WATCH2_CNTL
7978 #define SQ_WATCH2_CNTL__MASK__SHIFT                                                                           0x0
7979 #define SQ_WATCH2_CNTL__VMID__SHIFT                                                                           0x18
7980 #define SQ_WATCH2_CNTL__MODE__SHIFT                                                                           0x1d
7981 #define SQ_WATCH2_CNTL__VALID__SHIFT                                                                          0x1f
7982 #define SQ_WATCH2_CNTL__MASK_MASK                                                                             0x00FFFFFFL
7983 #define SQ_WATCH2_CNTL__VMID_MASK                                                                             0x0F000000L
7984 #define SQ_WATCH2_CNTL__MODE_MASK                                                                             0x60000000L
7985 #define SQ_WATCH2_CNTL__VALID_MASK                                                                            0x80000000L
7986 //SQ_WATCH3_ADDR_H
7987 #define SQ_WATCH3_ADDR_H__ADDR__SHIFT                                                                         0x0
7988 #define SQ_WATCH3_ADDR_H__ADDR_MASK                                                                           0x0000FFFFL
7989 //SQ_WATCH3_ADDR_L
7990 #define SQ_WATCH3_ADDR_L__ADDR__SHIFT                                                                         0x6
7991 #define SQ_WATCH3_ADDR_L__ADDR_MASK                                                                           0xFFFFFFC0L
7992 //SQ_WATCH3_CNTL
7993 #define SQ_WATCH3_CNTL__MASK__SHIFT                                                                           0x0
7994 #define SQ_WATCH3_CNTL__VMID__SHIFT                                                                           0x18
7995 #define SQ_WATCH3_CNTL__MODE__SHIFT                                                                           0x1d
7996 #define SQ_WATCH3_CNTL__VALID__SHIFT                                                                          0x1f
7997 #define SQ_WATCH3_CNTL__MASK_MASK                                                                             0x00FFFFFFL
7998 #define SQ_WATCH3_CNTL__VMID_MASK                                                                             0x0F000000L
7999 #define SQ_WATCH3_CNTL__MODE_MASK                                                                             0x60000000L
8000 #define SQ_WATCH3_CNTL__VALID_MASK                                                                            0x80000000L
8001 //SQ_THREAD_TRACE_BUF0_BASE
8002 #define SQ_THREAD_TRACE_BUF0_BASE__BASE_LO__SHIFT                                                             0x0
8003 #define SQ_THREAD_TRACE_BUF0_BASE__BASE_LO_MASK                                                               0xFFFFFFFFL
8004 //SQ_THREAD_TRACE_BUF0_SIZE
8005 #define SQ_THREAD_TRACE_BUF0_SIZE__BASE_HI__SHIFT                                                             0x0
8006 #define SQ_THREAD_TRACE_BUF0_SIZE__SIZE__SHIFT                                                                0x8
8007 #define SQ_THREAD_TRACE_BUF0_SIZE__BASE_HI_MASK                                                               0x0000000FL
8008 #define SQ_THREAD_TRACE_BUF0_SIZE__SIZE_MASK                                                                  0x3FFFFF00L
8009 //SQ_THREAD_TRACE_BUF1_BASE
8010 #define SQ_THREAD_TRACE_BUF1_BASE__BASE_LO__SHIFT                                                             0x0
8011 #define SQ_THREAD_TRACE_BUF1_BASE__BASE_LO_MASK                                                               0xFFFFFFFFL
8012 //SQ_THREAD_TRACE_BUF1_SIZE
8013 #define SQ_THREAD_TRACE_BUF1_SIZE__BASE_HI__SHIFT                                                             0x0
8014 #define SQ_THREAD_TRACE_BUF1_SIZE__SIZE__SHIFT                                                                0x8
8015 #define SQ_THREAD_TRACE_BUF1_SIZE__BASE_HI_MASK                                                               0x0000000FL
8016 #define SQ_THREAD_TRACE_BUF1_SIZE__SIZE_MASK                                                                  0x3FFFFF00L
8017 //SQ_THREAD_TRACE_WPTR
8018 #define SQ_THREAD_TRACE_WPTR__OFFSET__SHIFT                                                                   0x0
8019 #define SQ_THREAD_TRACE_WPTR__BUFFER_ID__SHIFT                                                                0x1f
8020 #define SQ_THREAD_TRACE_WPTR__OFFSET_MASK                                                                     0x1FFFFFFFL
8021 #define SQ_THREAD_TRACE_WPTR__BUFFER_ID_MASK                                                                  0x80000000L
8022 //SQ_THREAD_TRACE_MASK
8023 #define SQ_THREAD_TRACE_MASK__SIMD_SEL__SHIFT                                                                 0x0
8024 #define SQ_THREAD_TRACE_MASK__WGP_SEL__SHIFT                                                                  0x4
8025 #define SQ_THREAD_TRACE_MASK__SA_SEL__SHIFT                                                                   0x9
8026 #define SQ_THREAD_TRACE_MASK__WTYPE_INCLUDE__SHIFT                                                            0xa
8027 #define SQ_THREAD_TRACE_MASK__SIMD_SEL_MASK                                                                   0x00000003L
8028 #define SQ_THREAD_TRACE_MASK__WGP_SEL_MASK                                                                    0x000000F0L
8029 #define SQ_THREAD_TRACE_MASK__SA_SEL_MASK                                                                     0x00000200L
8030 #define SQ_THREAD_TRACE_MASK__WTYPE_INCLUDE_MASK                                                              0x0001FC00L
8031 //SQ_THREAD_TRACE_TOKEN_MASK
8032 #define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_EXCLUDE__SHIFT                                                      0x0
8033 #define SQ_THREAD_TRACE_TOKEN_MASK__REG_INCLUDE__SHIFT                                                        0x10
8034 #define SQ_THREAD_TRACE_TOKEN_MASK__INST_EXCLUDE__SHIFT                                                       0x18
8035 #define SQ_THREAD_TRACE_TOKEN_MASK__REG_DETAIL_ALL__SHIFT                                                     0x1f
8036 #define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_EXCLUDE_MASK                                                        0x00000FFFL
8037 #define SQ_THREAD_TRACE_TOKEN_MASK__REG_INCLUDE_MASK                                                          0x00FF0000L
8038 #define SQ_THREAD_TRACE_TOKEN_MASK__INST_EXCLUDE_MASK                                                         0x03000000L
8039 #define SQ_THREAD_TRACE_TOKEN_MASK__REG_DETAIL_ALL_MASK                                                       0x80000000L
8040 //SQ_THREAD_TRACE_CTRL
8041 #define SQ_THREAD_TRACE_CTRL__MODE__SHIFT                                                                     0x0
8042 #define SQ_THREAD_TRACE_CTRL__ALL_VMID__SHIFT                                                                 0x2
8043 #define SQ_THREAD_TRACE_CTRL__CH_PERF_EN__SHIFT                                                               0x3
8044 #define SQ_THREAD_TRACE_CTRL__INTERRUPT_EN__SHIFT                                                             0x4
8045 #define SQ_THREAD_TRACE_CTRL__DOUBLE_BUFFER__SHIFT                                                            0x5
8046 #define SQ_THREAD_TRACE_CTRL__HIWATER__SHIFT                                                                  0x6
8047 #define SQ_THREAD_TRACE_CTRL__REG_STALL_EN__SHIFT                                                             0x9
8048 #define SQ_THREAD_TRACE_CTRL__SPI_STALL_EN__SHIFT                                                             0xa
8049 #define SQ_THREAD_TRACE_CTRL__SQ_STALL_EN__SHIFT                                                              0xb
8050 #define SQ_THREAD_TRACE_CTRL__REG_DROP_ON_STALL__SHIFT                                                        0xc
8051 #define SQ_THREAD_TRACE_CTRL__UTIL_TIMER__SHIFT                                                               0xd
8052 #define SQ_THREAD_TRACE_CTRL__WAVESTART_MODE__SHIFT                                                           0xe
8053 #define SQ_THREAD_TRACE_CTRL__RT_FREQ__SHIFT                                                                  0x10
8054 #define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_MARKERS__SHIFT                                                       0x12
8055 #define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_DRAWS__SHIFT                                                         0x13
8056 #define SQ_THREAD_TRACE_CTRL__CAPTURE_ALL__SHIFT                                                              0x1e
8057 #define SQ_THREAD_TRACE_CTRL__DRAW_EVENT_EN__SHIFT                                                            0x1f
8058 #define SQ_THREAD_TRACE_CTRL__MODE_MASK                                                                       0x00000003L
8059 #define SQ_THREAD_TRACE_CTRL__ALL_VMID_MASK                                                                   0x00000004L
8060 #define SQ_THREAD_TRACE_CTRL__CH_PERF_EN_MASK                                                                 0x00000008L
8061 #define SQ_THREAD_TRACE_CTRL__INTERRUPT_EN_MASK                                                               0x00000010L
8062 #define SQ_THREAD_TRACE_CTRL__DOUBLE_BUFFER_MASK                                                              0x00000020L
8063 #define SQ_THREAD_TRACE_CTRL__HIWATER_MASK                                                                    0x000001C0L
8064 #define SQ_THREAD_TRACE_CTRL__REG_STALL_EN_MASK                                                               0x00000200L
8065 #define SQ_THREAD_TRACE_CTRL__SPI_STALL_EN_MASK                                                               0x00000400L
8066 #define SQ_THREAD_TRACE_CTRL__SQ_STALL_EN_MASK                                                                0x00000800L
8067 #define SQ_THREAD_TRACE_CTRL__REG_DROP_ON_STALL_MASK                                                          0x00001000L
8068 #define SQ_THREAD_TRACE_CTRL__UTIL_TIMER_MASK                                                                 0x00002000L
8069 #define SQ_THREAD_TRACE_CTRL__WAVESTART_MODE_MASK                                                             0x0000C000L
8070 #define SQ_THREAD_TRACE_CTRL__RT_FREQ_MASK                                                                    0x00030000L
8071 #define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_MARKERS_MASK                                                         0x00040000L
8072 #define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_DRAWS_MASK                                                           0x00080000L
8073 #define SQ_THREAD_TRACE_CTRL__CAPTURE_ALL_MASK                                                                0x40000000L
8074 #define SQ_THREAD_TRACE_CTRL__DRAW_EVENT_EN_MASK                                                              0x80000000L
8075 //SQ_THREAD_TRACE_STATUS
8076 #define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT                                                         0x0
8077 #define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT                                                            0xc
8078 #define SQ_THREAD_TRACE_STATUS__UTC_ERR__SHIFT                                                                0x18
8079 #define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT                                                                   0x19
8080 #define SQ_THREAD_TRACE_STATUS__EVENT_CNTR_OVERFLOW__SHIFT                                                    0x1a
8081 #define SQ_THREAD_TRACE_STATUS__EVENT_CNTR_STALL__SHIFT                                                       0x1b
8082 #define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK                                                           0x00000FFFL
8083 #define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK                                                              0x00FFF000L
8084 #define SQ_THREAD_TRACE_STATUS__UTC_ERR_MASK                                                                  0x01000000L
8085 #define SQ_THREAD_TRACE_STATUS__BUSY_MASK                                                                     0x02000000L
8086 #define SQ_THREAD_TRACE_STATUS__EVENT_CNTR_OVERFLOW_MASK                                                      0x04000000L
8087 #define SQ_THREAD_TRACE_STATUS__EVENT_CNTR_STALL_MASK                                                         0x08000000L
8088 //SQ_THREAD_TRACE_DROPPED_CNTR
8089 #define SQ_THREAD_TRACE_DROPPED_CNTR__CNTR__SHIFT                                                             0x0
8090 #define SQ_THREAD_TRACE_DROPPED_CNTR__CNTR_MASK                                                               0xFFFFFFFFL
8091 //SQ_THREAD_TRACE_GFX_DRAW_CNTR
8092 #define SQ_THREAD_TRACE_GFX_DRAW_CNTR__CNTR__SHIFT                                                            0x0
8093 #define SQ_THREAD_TRACE_GFX_DRAW_CNTR__CNTR_MASK                                                              0xFFFFFFFFL
8094 //SQ_THREAD_TRACE_GFX_MARKER_CNTR
8095 #define SQ_THREAD_TRACE_GFX_MARKER_CNTR__CNTR__SHIFT                                                          0x0
8096 #define SQ_THREAD_TRACE_GFX_MARKER_CNTR__CNTR_MASK                                                            0xFFFFFFFFL
8097 //SQ_THREAD_TRACE_HP3D_DRAW_CNTR
8098 #define SQ_THREAD_TRACE_HP3D_DRAW_CNTR__CNTR__SHIFT                                                           0x0
8099 #define SQ_THREAD_TRACE_HP3D_DRAW_CNTR__CNTR_MASK                                                             0xFFFFFFFFL
8100 //SQ_THREAD_TRACE_HP3D_MARKER_CNTR
8101 #define SQ_THREAD_TRACE_HP3D_MARKER_CNTR__CNTR__SHIFT                                                         0x0
8102 #define SQ_THREAD_TRACE_HP3D_MARKER_CNTR__CNTR_MASK                                                           0xFFFFFFFFL
8103 //SQ_IND_INDEX
8104 #define SQ_IND_INDEX__WAVE_ID__SHIFT                                                                          0x0
8105 #define SQ_IND_INDEX__WORKITEM_ID__SHIFT                                                                      0x5
8106 #define SQ_IND_INDEX__AUTO_INCR__SHIFT                                                                        0xb
8107 #define SQ_IND_INDEX__INDEX__SHIFT                                                                            0x10
8108 #define SQ_IND_INDEX__WAVE_ID_MASK                                                                            0x0000001FL
8109 #define SQ_IND_INDEX__WORKITEM_ID_MASK                                                                        0x000007E0L
8110 #define SQ_IND_INDEX__AUTO_INCR_MASK                                                                          0x00000800L
8111 #define SQ_IND_INDEX__INDEX_MASK                                                                              0xFFFF0000L
8112 //SQ_IND_DATA
8113 #define SQ_IND_DATA__DATA__SHIFT                                                                              0x0
8114 #define SQ_IND_DATA__DATA_MASK                                                                                0xFFFFFFFFL
8115 //SQ_CMD
8116 #define SQ_CMD__CMD__SHIFT                                                                                    0x0
8117 #define SQ_CMD__MODE__SHIFT                                                                                   0x4
8118 #define SQ_CMD__CHECK_VMID__SHIFT                                                                             0x7
8119 #define SQ_CMD__DATA__SHIFT                                                                                   0x8
8120 #define SQ_CMD__WAVE_ID__SHIFT                                                                                0x10
8121 #define SQ_CMD__QUEUE_ID__SHIFT                                                                               0x18
8122 #define SQ_CMD__VM_ID__SHIFT                                                                                  0x1c
8123 #define SQ_CMD__CMD_MASK                                                                                      0x0000000FL
8124 #define SQ_CMD__MODE_MASK                                                                                     0x00000070L
8125 #define SQ_CMD__CHECK_VMID_MASK                                                                               0x00000080L
8126 #define SQ_CMD__DATA_MASK                                                                                     0x00000F00L
8127 #define SQ_CMD__WAVE_ID_MASK                                                                                  0x001F0000L
8128 #define SQ_CMD__QUEUE_ID_MASK                                                                                 0x07000000L
8129 #define SQ_CMD__VM_ID_MASK                                                                                    0xF0000000L
8130 //SQ_TIME_HI
8131 #define SQ_TIME_HI__TIME__SHIFT                                                                               0x0
8132 #define SQ_TIME_HI__TIME_MASK                                                                                 0xFFFFFFFFL
8133 //SQ_TIME_LO
8134 #define SQ_TIME_LO__TIME__SHIFT                                                                               0x0
8135 #define SQ_TIME_LO__TIME_MASK                                                                                 0xFFFFFFFFL
8136 //SQ_LB_CTR_CTRL
8137 #define SQ_LB_CTR_CTRL__START__SHIFT                                                                          0x0
8138 #define SQ_LB_CTR_CTRL__LOAD__SHIFT                                                                           0x1
8139 #define SQ_LB_CTR_CTRL__CLEAR__SHIFT                                                                          0x2
8140 #define SQ_LB_CTR_CTRL__START_MASK                                                                            0x00000001L
8141 #define SQ_LB_CTR_CTRL__LOAD_MASK                                                                             0x00000002L
8142 #define SQ_LB_CTR_CTRL__CLEAR_MASK                                                                            0x00000004L
8143 //SQ_LB_DATA0
8144 #define SQ_LB_DATA0__DATA__SHIFT                                                                              0x0
8145 #define SQ_LB_DATA0__DATA_MASK                                                                                0xFFFFFFFFL
8146 //SQ_LB_DATA1
8147 #define SQ_LB_DATA1__DATA__SHIFT                                                                              0x0
8148 #define SQ_LB_DATA1__DATA_MASK                                                                                0xFFFFFFFFL
8149 //SQ_LB_DATA2
8150 #define SQ_LB_DATA2__DATA__SHIFT                                                                              0x0
8151 #define SQ_LB_DATA2__DATA_MASK                                                                                0xFFFFFFFFL
8152 //SQ_LB_DATA3
8153 #define SQ_LB_DATA3__DATA__SHIFT                                                                              0x0
8154 #define SQ_LB_DATA3__DATA_MASK                                                                                0xFFFFFFFFL
8155 //SQ_LB_CTR_SEL0
8156 #define SQ_LB_CTR_SEL0__SEL0__SHIFT                                                                           0x0
8157 #define SQ_LB_CTR_SEL0__DIV0__SHIFT                                                                           0xf
8158 #define SQ_LB_CTR_SEL0__SEL1__SHIFT                                                                           0x10
8159 #define SQ_LB_CTR_SEL0__DIV1__SHIFT                                                                           0x1f
8160 #define SQ_LB_CTR_SEL0__SEL0_MASK                                                                             0x000000FFL
8161 #define SQ_LB_CTR_SEL0__DIV0_MASK                                                                             0x00008000L
8162 #define SQ_LB_CTR_SEL0__SEL1_MASK                                                                             0x00FF0000L
8163 #define SQ_LB_CTR_SEL0__DIV1_MASK                                                                             0x80000000L
8164 //SQ_LB_CTR_SEL1
8165 #define SQ_LB_CTR_SEL1__SEL2__SHIFT                                                                           0x0
8166 #define SQ_LB_CTR_SEL1__DIV2__SHIFT                                                                           0xf
8167 #define SQ_LB_CTR_SEL1__SEL3__SHIFT                                                                           0x10
8168 #define SQ_LB_CTR_SEL1__DIV3__SHIFT                                                                           0x1f
8169 #define SQ_LB_CTR_SEL1__SEL2_MASK                                                                             0x000000FFL
8170 #define SQ_LB_CTR_SEL1__DIV2_MASK                                                                             0x00008000L
8171 #define SQ_LB_CTR_SEL1__SEL3_MASK                                                                             0x00FF0000L
8172 #define SQ_LB_CTR_SEL1__DIV3_MASK                                                                             0x80000000L
8173 //SQ_EDC_CNT
8174 #define SQ_EDC_CNT__LDS_D_SEC_COUNT__SHIFT                                                                    0x0
8175 #define SQ_EDC_CNT__LDS_D_DED_COUNT__SHIFT                                                                    0x2
8176 #define SQ_EDC_CNT__LDS_I_SEC_COUNT__SHIFT                                                                    0x4
8177 #define SQ_EDC_CNT__LDS_I_DED_COUNT__SHIFT                                                                    0x6
8178 #define SQ_EDC_CNT__SGPR_SEC_COUNT__SHIFT                                                                     0x8
8179 #define SQ_EDC_CNT__SGPR_DED_COUNT__SHIFT                                                                     0xa
8180 #define SQ_EDC_CNT__VGPR0_SEC_COUNT__SHIFT                                                                    0xc
8181 #define SQ_EDC_CNT__VGPR0_DED_COUNT__SHIFT                                                                    0xe
8182 #define SQ_EDC_CNT__VGPR1_SEC_COUNT__SHIFT                                                                    0x10
8183 #define SQ_EDC_CNT__VGPR1_DED_COUNT__SHIFT                                                                    0x12
8184 #define SQ_EDC_CNT__VGPR2_SEC_COUNT__SHIFT                                                                    0x14
8185 #define SQ_EDC_CNT__VGPR2_DED_COUNT__SHIFT                                                                    0x16
8186 #define SQ_EDC_CNT__VGPR3_SEC_COUNT__SHIFT                                                                    0x18
8187 #define SQ_EDC_CNT__VGPR3_DED_COUNT__SHIFT                                                                    0x1a
8188 #define SQ_EDC_CNT__LDS_D_SEC_COUNT_MASK                                                                      0x00000003L
8189 #define SQ_EDC_CNT__LDS_D_DED_COUNT_MASK                                                                      0x0000000CL
8190 #define SQ_EDC_CNT__LDS_I_SEC_COUNT_MASK                                                                      0x00000030L
8191 #define SQ_EDC_CNT__LDS_I_DED_COUNT_MASK                                                                      0x000000C0L
8192 #define SQ_EDC_CNT__SGPR_SEC_COUNT_MASK                                                                       0x00000300L
8193 #define SQ_EDC_CNT__SGPR_DED_COUNT_MASK                                                                       0x00000C00L
8194 #define SQ_EDC_CNT__VGPR0_SEC_COUNT_MASK                                                                      0x00003000L
8195 #define SQ_EDC_CNT__VGPR0_DED_COUNT_MASK                                                                      0x0000C000L
8196 #define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK                                                                      0x00030000L
8197 #define SQ_EDC_CNT__VGPR1_DED_COUNT_MASK                                                                      0x000C0000L
8198 #define SQ_EDC_CNT__VGPR2_SEC_COUNT_MASK                                                                      0x00300000L
8199 #define SQ_EDC_CNT__VGPR2_DED_COUNT_MASK                                                                      0x00C00000L
8200 #define SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK                                                                      0x03000000L
8201 #define SQ_EDC_CNT__VGPR3_DED_COUNT_MASK                                                                      0x0C000000L
8202 //SQ_EDC_FUE_CNTL
8203 #define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT                                                               0x0
8204 #define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT                                                         0x10
8205 #define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK                                                                 0x0000FFFFL
8206 #define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK                                                           0xFFFF0000L
8207 //SQ_WREXEC_EXEC_HI
8208 #define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT                                                                     0x0
8209 #define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT                                                                  0x1a
8210 #define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT                                                                       0x1c
8211 #define SQ_WREXEC_EXEC_HI__MSB__SHIFT                                                                         0x1f
8212 #define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK                                                                       0x0000FFFFL
8213 #define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK                                                                    0x04000000L
8214 #define SQ_WREXEC_EXEC_HI__MTYPE_MASK                                                                         0x70000000L
8215 #define SQ_WREXEC_EXEC_HI__MSB_MASK                                                                           0x80000000L
8216 //SQ_WREXEC_EXEC_LO
8217 #define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT                                                                     0x0
8218 #define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK                                                                       0xFFFFFFFFL
8219 //SQC_ICACHE_UTCL0_CNTL1
8220 #define SQC_ICACHE_UTCL0_CNTL1__FORCE_4K_L2_RESP__SHIFT                                                       0x0
8221 #define SQC_ICACHE_UTCL0_CNTL1__GPUVM_64K_DEF__SHIFT                                                          0x1
8222 #define SQC_ICACHE_UTCL0_CNTL1__GPUVM_PERM_MODE__SHIFT                                                        0x2
8223 #define SQC_ICACHE_UTCL0_CNTL1__RESP_MODE__SHIFT                                                              0x3
8224 #define SQC_ICACHE_UTCL0_CNTL1__RESP_FAULT_MODE__SHIFT                                                        0x5
8225 #define SQC_ICACHE_UTCL0_CNTL1__CLIENTID__SHIFT                                                               0x7
8226 #define SQC_ICACHE_UTCL0_CNTL1__ENABLE_PUSH_LFIFO__SHIFT                                                      0x11
8227 #define SQC_ICACHE_UTCL0_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT                                                   0x12
8228 #define SQC_ICACHE_UTCL0_CNTL1__REG_INV_VMID__SHIFT                                                           0x13
8229 #define SQC_ICACHE_UTCL0_CNTL1__REG_INV_ALL_VMID__SHIFT                                                       0x17
8230 #define SQC_ICACHE_UTCL0_CNTL1__REG_INV_TOGGLE__SHIFT                                                         0x18
8231 #define SQC_ICACHE_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT                                             0x19
8232 #define SQC_ICACHE_UTCL0_CNTL1__FORCE_MISS__SHIFT                                                             0x1a
8233 #define SQC_ICACHE_UTCL0_CNTL1__FORCE_IN_ORDER__SHIFT                                                         0x1b
8234 #define SQC_ICACHE_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT                                                 0x1c
8235 #define SQC_ICACHE_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT                                                 0x1e
8236 #define SQC_ICACHE_UTCL0_CNTL1__FORCE_4K_L2_RESP_MASK                                                         0x00000001L
8237 #define SQC_ICACHE_UTCL0_CNTL1__GPUVM_64K_DEF_MASK                                                            0x00000002L
8238 #define SQC_ICACHE_UTCL0_CNTL1__GPUVM_PERM_MODE_MASK                                                          0x00000004L
8239 #define SQC_ICACHE_UTCL0_CNTL1__RESP_MODE_MASK                                                                0x00000018L
8240 #define SQC_ICACHE_UTCL0_CNTL1__RESP_FAULT_MODE_MASK                                                          0x00000060L
8241 #define SQC_ICACHE_UTCL0_CNTL1__CLIENTID_MASK                                                                 0x0000FF80L
8242 #define SQC_ICACHE_UTCL0_CNTL1__ENABLE_PUSH_LFIFO_MASK                                                        0x00020000L
8243 #define SQC_ICACHE_UTCL0_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK                                                     0x00040000L
8244 #define SQC_ICACHE_UTCL0_CNTL1__REG_INV_VMID_MASK                                                             0x00780000L
8245 #define SQC_ICACHE_UTCL0_CNTL1__REG_INV_ALL_VMID_MASK                                                         0x00800000L
8246 #define SQC_ICACHE_UTCL0_CNTL1__REG_INV_TOGGLE_MASK                                                           0x01000000L
8247 #define SQC_ICACHE_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK                                               0x02000000L
8248 #define SQC_ICACHE_UTCL0_CNTL1__FORCE_MISS_MASK                                                               0x04000000L
8249 #define SQC_ICACHE_UTCL0_CNTL1__FORCE_IN_ORDER_MASK                                                           0x08000000L
8250 #define SQC_ICACHE_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK                                                   0x30000000L
8251 #define SQC_ICACHE_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK                                                   0xC0000000L
8252 //SQC_ICACHE_UTCL0_CNTL2
8253 #define SQC_ICACHE_UTCL0_CNTL2__SPARE__SHIFT                                                                  0x0
8254 #define SQC_ICACHE_UTCL0_CNTL2__LFIFO_SCAN_DISABLE__SHIFT                                                     0x8
8255 #define SQC_ICACHE_UTCL0_CNTL2__MTYPE_OVRD_DIS__SHIFT                                                         0x9
8256 #define SQC_ICACHE_UTCL0_CNTL2__LINE_VALID__SHIFT                                                             0xa
8257 #define SQC_ICACHE_UTCL0_CNTL2__DIS_EDC__SHIFT                                                                0xb
8258 #define SQC_ICACHE_UTCL0_CNTL2__GPUVM_INV_MODE__SHIFT                                                         0xc
8259 #define SQC_ICACHE_UTCL0_CNTL2__SHOOTDOWN_OPT__SHIFT                                                          0xd
8260 #define SQC_ICACHE_UTCL0_CNTL2__FORCE_SNOOP__SHIFT                                                            0xe
8261 #define SQC_ICACHE_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT                                                    0xf
8262 #define SQC_ICACHE_UTCL0_CNTL2__ARB_BURST_MODE__SHIFT                                                         0x10
8263 #define SQC_ICACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT                                                0x12
8264 #define SQC_ICACHE_UTCL0_CNTL2__PERF_EVENT_RD_WR__SHIFT                                                       0x13
8265 #define SQC_ICACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT                                                 0x14
8266 #define SQC_ICACHE_UTCL0_CNTL2__PERF_EVENT_VMID__SHIFT                                                        0x15
8267 #define SQC_ICACHE_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT                                                   0x1a
8268 #define SQC_ICACHE_UTCL0_CNTL2__PERM_MODE_OVRD__SHIFT                                                         0x1b
8269 #define SQC_ICACHE_UTCL0_CNTL2__LINE_INVALIDATE_OPT__SHIFT                                                    0x1c
8270 #define SQC_ICACHE_UTCL0_CNTL2__GPUVM_16K_DEF__SHIFT                                                          0x1d
8271 #define SQC_ICACHE_UTCL0_CNTL2__SPARE_MASK                                                                    0x000000FFL
8272 #define SQC_ICACHE_UTCL0_CNTL2__LFIFO_SCAN_DISABLE_MASK                                                       0x00000100L
8273 #define SQC_ICACHE_UTCL0_CNTL2__MTYPE_OVRD_DIS_MASK                                                           0x00000200L
8274 #define SQC_ICACHE_UTCL0_CNTL2__LINE_VALID_MASK                                                               0x00000400L
8275 #define SQC_ICACHE_UTCL0_CNTL2__DIS_EDC_MASK                                                                  0x00000800L
8276 #define SQC_ICACHE_UTCL0_CNTL2__GPUVM_INV_MODE_MASK                                                           0x00001000L
8277 #define SQC_ICACHE_UTCL0_CNTL2__SHOOTDOWN_OPT_MASK                                                            0x00002000L
8278 #define SQC_ICACHE_UTCL0_CNTL2__FORCE_SNOOP_MASK                                                              0x00004000L
8279 #define SQC_ICACHE_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK_MASK                                                      0x00008000L
8280 #define SQC_ICACHE_UTCL0_CNTL2__ARB_BURST_MODE_MASK                                                           0x00030000L
8281 #define SQC_ICACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK                                                  0x00040000L
8282 #define SQC_ICACHE_UTCL0_CNTL2__PERF_EVENT_RD_WR_MASK                                                         0x00080000L
8283 #define SQC_ICACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID_MASK                                                   0x00100000L
8284 #define SQC_ICACHE_UTCL0_CNTL2__PERF_EVENT_VMID_MASK                                                          0x01E00000L
8285 #define SQC_ICACHE_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K_MASK                                                     0x04000000L
8286 #define SQC_ICACHE_UTCL0_CNTL2__PERM_MODE_OVRD_MASK                                                           0x08000000L
8287 #define SQC_ICACHE_UTCL0_CNTL2__LINE_INVALIDATE_OPT_MASK                                                      0x10000000L
8288 #define SQC_ICACHE_UTCL0_CNTL2__GPUVM_16K_DEF_MASK                                                            0x20000000L
8289 //SQC_DCACHE_UTCL0_CNTL1
8290 #define SQC_DCACHE_UTCL0_CNTL1__FORCE_4K_L2_RESP__SHIFT                                                       0x0
8291 #define SQC_DCACHE_UTCL0_CNTL1__GPUVM_64K_DEF__SHIFT                                                          0x1
8292 #define SQC_DCACHE_UTCL0_CNTL1__GPUVM_PERM_MODE__SHIFT                                                        0x2
8293 #define SQC_DCACHE_UTCL0_CNTL1__RESP_MODE__SHIFT                                                              0x3
8294 #define SQC_DCACHE_UTCL0_CNTL1__RESP_FAULT_MODE__SHIFT                                                        0x5
8295 #define SQC_DCACHE_UTCL0_CNTL1__CLIENTID__SHIFT                                                               0x7
8296 #define SQC_DCACHE_UTCL0_CNTL1__ENABLE_PUSH_LFIFO__SHIFT                                                      0x11
8297 #define SQC_DCACHE_UTCL0_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT                                                   0x12
8298 #define SQC_DCACHE_UTCL0_CNTL1__REG_INV_VMID__SHIFT                                                           0x13
8299 #define SQC_DCACHE_UTCL0_CNTL1__REG_INV_ALL_VMID__SHIFT                                                       0x17
8300 #define SQC_DCACHE_UTCL0_CNTL1__REG_INV_TOGGLE__SHIFT                                                         0x18
8301 #define SQC_DCACHE_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT                                             0x19
8302 #define SQC_DCACHE_UTCL0_CNTL1__FORCE_MISS__SHIFT                                                             0x1a
8303 #define SQC_DCACHE_UTCL0_CNTL1__FORCE_IN_ORDER__SHIFT                                                         0x1b
8304 #define SQC_DCACHE_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT                                                 0x1c
8305 #define SQC_DCACHE_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT                                                 0x1e
8306 #define SQC_DCACHE_UTCL0_CNTL1__FORCE_4K_L2_RESP_MASK                                                         0x00000001L
8307 #define SQC_DCACHE_UTCL0_CNTL1__GPUVM_64K_DEF_MASK                                                            0x00000002L
8308 #define SQC_DCACHE_UTCL0_CNTL1__GPUVM_PERM_MODE_MASK                                                          0x00000004L
8309 #define SQC_DCACHE_UTCL0_CNTL1__RESP_MODE_MASK                                                                0x00000018L
8310 #define SQC_DCACHE_UTCL0_CNTL1__RESP_FAULT_MODE_MASK                                                          0x00000060L
8311 #define SQC_DCACHE_UTCL0_CNTL1__CLIENTID_MASK                                                                 0x0000FF80L
8312 #define SQC_DCACHE_UTCL0_CNTL1__ENABLE_PUSH_LFIFO_MASK                                                        0x00020000L
8313 #define SQC_DCACHE_UTCL0_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK                                                     0x00040000L
8314 #define SQC_DCACHE_UTCL0_CNTL1__REG_INV_VMID_MASK                                                             0x00780000L
8315 #define SQC_DCACHE_UTCL0_CNTL1__REG_INV_ALL_VMID_MASK                                                         0x00800000L
8316 #define SQC_DCACHE_UTCL0_CNTL1__REG_INV_TOGGLE_MASK                                                           0x01000000L
8317 #define SQC_DCACHE_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK                                               0x02000000L
8318 #define SQC_DCACHE_UTCL0_CNTL1__FORCE_MISS_MASK                                                               0x04000000L
8319 #define SQC_DCACHE_UTCL0_CNTL1__FORCE_IN_ORDER_MASK                                                           0x08000000L
8320 #define SQC_DCACHE_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK                                                   0x30000000L
8321 #define SQC_DCACHE_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK                                                   0xC0000000L
8322 //SQC_DCACHE_UTCL0_CNTL2
8323 #define SQC_DCACHE_UTCL0_CNTL2__SPARE__SHIFT                                                                  0x0
8324 #define SQC_DCACHE_UTCL0_CNTL2__LFIFO_SCAN_DISABLE__SHIFT                                                     0x8
8325 #define SQC_DCACHE_UTCL0_CNTL2__MTYPE_OVRD_DIS__SHIFT                                                         0x9
8326 #define SQC_DCACHE_UTCL0_CNTL2__LINE_VALID__SHIFT                                                             0xa
8327 #define SQC_DCACHE_UTCL0_CNTL2__DIS_EDC__SHIFT                                                                0xb
8328 #define SQC_DCACHE_UTCL0_CNTL2__GPUVM_INV_MODE__SHIFT                                                         0xc
8329 #define SQC_DCACHE_UTCL0_CNTL2__SHOOTDOWN_OPT__SHIFT                                                          0xd
8330 #define SQC_DCACHE_UTCL0_CNTL2__FORCE_SNOOP__SHIFT                                                            0xe
8331 #define SQC_DCACHE_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT                                                    0xf
8332 #define SQC_DCACHE_UTCL0_CNTL2__ARB_BURST_MODE__SHIFT                                                         0x10
8333 #define SQC_DCACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT                                                0x12
8334 #define SQC_DCACHE_UTCL0_CNTL2__PERF_EVENT_RD_WR__SHIFT                                                       0x13
8335 #define SQC_DCACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT                                                 0x14
8336 #define SQC_DCACHE_UTCL0_CNTL2__PERF_EVENT_VMID__SHIFT                                                        0x15
8337 #define SQC_DCACHE_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT                                                   0x1a
8338 #define SQC_DCACHE_UTCL0_CNTL2__PERM_MODE_OVRD__SHIFT                                                         0x1b
8339 #define SQC_DCACHE_UTCL0_CNTL2__LINE_INVALIDATE_OPT__SHIFT                                                    0x1c
8340 #define SQC_DCACHE_UTCL0_CNTL2__GPUVM_16K_DEF__SHIFT                                                          0x1d
8341 #define SQC_DCACHE_UTCL0_CNTL2__SPARE_MASK                                                                    0x000000FFL
8342 #define SQC_DCACHE_UTCL0_CNTL2__LFIFO_SCAN_DISABLE_MASK                                                       0x00000100L
8343 #define SQC_DCACHE_UTCL0_CNTL2__MTYPE_OVRD_DIS_MASK                                                           0x00000200L
8344 #define SQC_DCACHE_UTCL0_CNTL2__LINE_VALID_MASK                                                               0x00000400L
8345 #define SQC_DCACHE_UTCL0_CNTL2__DIS_EDC_MASK                                                                  0x00000800L
8346 #define SQC_DCACHE_UTCL0_CNTL2__GPUVM_INV_MODE_MASK                                                           0x00001000L
8347 #define SQC_DCACHE_UTCL0_CNTL2__SHOOTDOWN_OPT_MASK                                                            0x00002000L
8348 #define SQC_DCACHE_UTCL0_CNTL2__FORCE_SNOOP_MASK                                                              0x00004000L
8349 #define SQC_DCACHE_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK_MASK                                                      0x00008000L
8350 #define SQC_DCACHE_UTCL0_CNTL2__ARB_BURST_MODE_MASK                                                           0x00030000L
8351 #define SQC_DCACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK                                                  0x00040000L
8352 #define SQC_DCACHE_UTCL0_CNTL2__PERF_EVENT_RD_WR_MASK                                                         0x00080000L
8353 #define SQC_DCACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID_MASK                                                   0x00100000L
8354 #define SQC_DCACHE_UTCL0_CNTL2__PERF_EVENT_VMID_MASK                                                          0x01E00000L
8355 #define SQC_DCACHE_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K_MASK                                                     0x04000000L
8356 #define SQC_DCACHE_UTCL0_CNTL2__PERM_MODE_OVRD_MASK                                                           0x08000000L
8357 #define SQC_DCACHE_UTCL0_CNTL2__LINE_INVALIDATE_OPT_MASK                                                      0x10000000L
8358 #define SQC_DCACHE_UTCL0_CNTL2__GPUVM_16K_DEF_MASK                                                            0x20000000L
8359 //SQC_ICACHE_UTCL0_STATUS
8360 #define SQC_ICACHE_UTCL0_STATUS__FAULT_DETECTED__SHIFT                                                        0x0
8361 #define SQC_ICACHE_UTCL0_STATUS__RETRY_DETECTED__SHIFT                                                        0x1
8362 #define SQC_ICACHE_UTCL0_STATUS__PRT_DETECTED__SHIFT                                                          0x2
8363 #define SQC_ICACHE_UTCL0_STATUS__FAULT_DETECTED_MASK                                                          0x00000001L
8364 #define SQC_ICACHE_UTCL0_STATUS__RETRY_DETECTED_MASK                                                          0x00000002L
8365 #define SQC_ICACHE_UTCL0_STATUS__PRT_DETECTED_MASK                                                            0x00000004L
8366 //SQC_DCACHE_UTCL0_STATUS
8367 #define SQC_DCACHE_UTCL0_STATUS__FAULT_DETECTED__SHIFT                                                        0x0
8368 #define SQC_DCACHE_UTCL0_STATUS__RETRY_DETECTED__SHIFT                                                        0x1
8369 #define SQC_DCACHE_UTCL0_STATUS__PRT_DETECTED__SHIFT                                                          0x2
8370 #define SQC_DCACHE_UTCL0_STATUS__FAULT_DETECTED_MASK                                                          0x00000001L
8371 #define SQC_DCACHE_UTCL0_STATUS__RETRY_DETECTED_MASK                                                          0x00000002L
8372 #define SQC_DCACHE_UTCL0_STATUS__PRT_DETECTED_MASK                                                            0x00000004L
8373 //SQC_MISC_CONFIG
8374 #define SQC_MISC_CONFIG__PERFTOKEN_DELAY__SHIFT                                                               0x0
8375 #define SQC_MISC_CONFIG__SQC_SPI_TTRACE_FGCG_OVERRIDE__SHIFT                                                  0x5
8376 #define SQC_MISC_CONFIG__PERFTOKEN_DELAY_MASK                                                                 0x0000001FL
8377 #define SQC_MISC_CONFIG__SQC_SPI_TTRACE_FGCG_OVERRIDE_MASK                                                    0x00000020L
8378 
8379 
8380 // addressBlock: gc_shsdec
8381 //SX_DEBUG_1
8382 #define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT                                                                  0x0
8383 #define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT                                                      0x8
8384 #define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS__SHIFT                                                           0x9
8385 #define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT                                                    0xa
8386 #define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT__SHIFT                                                              0xb
8387 #define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT__SHIFT                                                            0xc
8388 #define SX_DEBUG_1__DISABLE_REP_FGCG__SHIFT                                                                   0xd
8389 #define SX_DEBUG_1__ENABLE_SAME_PC_GDS_CGTS__SHIFT                                                            0xe
8390 #define SX_DEBUG_1__DISABLE_RAM_FGCG__SHIFT                                                                   0xf
8391 #define SX_DEBUG_1__PC_DISABLE_SAME_ADDR_OPT__SHIFT                                                           0x10
8392 #define SX_DEBUG_1__DISABLE_COL_VAL_READ_OPT__SHIFT                                                           0x11
8393 #define SX_DEBUG_1__DEBUG_DATA__SHIFT                                                                         0x12
8394 #define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK                                                                    0x0000007FL
8395 #define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST_MASK                                                        0x00000100L
8396 #define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS_MASK                                                             0x00000200L
8397 #define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK                                                      0x00000400L
8398 #define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT_MASK                                                                0x00000800L
8399 #define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT_MASK                                                              0x00001000L
8400 #define SX_DEBUG_1__DISABLE_REP_FGCG_MASK                                                                     0x00002000L
8401 #define SX_DEBUG_1__ENABLE_SAME_PC_GDS_CGTS_MASK                                                              0x00004000L
8402 #define SX_DEBUG_1__DISABLE_RAM_FGCG_MASK                                                                     0x00008000L
8403 #define SX_DEBUG_1__PC_DISABLE_SAME_ADDR_OPT_MASK                                                             0x00010000L
8404 #define SX_DEBUG_1__DISABLE_COL_VAL_READ_OPT_MASK                                                             0x00020000L
8405 #define SX_DEBUG_1__DEBUG_DATA_MASK                                                                           0xFFFC0000L
8406 //SPI_PS_MAX_WAVE_ID
8407 #define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT                                                                0x0
8408 #define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID__SHIFT                                                      0x10
8409 #define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK                                                                  0x00000FFFL
8410 #define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID_MASK                                                        0x03FF0000L
8411 //SPI_START_PHASE
8412 #define SPI_START_PHASE__PC_X_PHASE_SE0__SHIFT                                                                0x0
8413 #define SPI_START_PHASE__PC_X_PHASE_SE1__SHIFT                                                                0x2
8414 #define SPI_START_PHASE__PC_X_PHASE_SE2__SHIFT                                                                0x4
8415 #define SPI_START_PHASE__PC_X_PHASE_SE3__SHIFT                                                                0x6
8416 #define SPI_START_PHASE__PC_X_PHASE_SE0_MASK                                                                  0x00000003L
8417 #define SPI_START_PHASE__PC_X_PHASE_SE1_MASK                                                                  0x0000000CL
8418 #define SPI_START_PHASE__PC_X_PHASE_SE2_MASK                                                                  0x00000030L
8419 #define SPI_START_PHASE__PC_X_PHASE_SE3_MASK                                                                  0x000000C0L
8420 //SPI_GFX_CNTL
8421 #define SPI_GFX_CNTL__RESET_COUNTS__SHIFT                                                                     0x0
8422 #define SPI_GFX_CNTL__RESET_COUNTS_MASK                                                                       0x00000001L
8423 //SPI_USER_ACCUM_VMID_CNTL
8424 #define SPI_USER_ACCUM_VMID_CNTL__EN_USER_ACCUM__SHIFT                                                        0x0
8425 #define SPI_USER_ACCUM_VMID_CNTL__EN_USER_ACCUM_MASK                                                          0x0000000FL
8426 //SPI_CONFIG_CNTL
8427 #define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT                                                            0x0
8428 #define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT                                                            0x15
8429 #define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT                                                         0x18
8430 #define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT                                                         0x19
8431 #define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT                                                               0x1a
8432 #define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT                                                              0x1b
8433 #define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA__SHIFT                                                             0x1c
8434 #define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA__SHIFT                                                               0x1d
8435 #define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL__SHIFT                                                          0x1e
8436 #define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK                                                              0x001FFFFFL
8437 #define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK                                                              0x00E00000L
8438 #define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK                                                           0x01000000L
8439 #define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK                                                           0x02000000L
8440 #define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK                                                                 0x04000000L
8441 #define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK                                                                0x08000000L
8442 #define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA_MASK                                                               0x10000000L
8443 #define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA_MASK                                                                 0x20000000L
8444 #define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL_MASK                                                            0xC0000000L
8445 //SPI_DSM_CNTL
8446 #define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA__SHIFT                                                    0x0
8447 #define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE__SHIFT                                                   0x2
8448 #define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA_MASK                                                      0x00000003L
8449 #define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE_MASK                                                     0x00000004L
8450 //SPI_DSM_CNTL2
8451 #define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT__SHIFT                                                  0x0
8452 #define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY__SHIFT                                                  0x2
8453 #define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY__SHIFT                                                         0x3
8454 #define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT_MASK                                                    0x00000003L
8455 #define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY_MASK                                                    0x00000004L
8456 #define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY_MASK                                                           0x000001F8L
8457 //SPI_EDC_CNT
8458 #define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT__SHIFT                                                              0x0
8459 #define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT_MASK                                                                0x00000003L
8460 //SPI_WAVE_LIMIT_CNTL
8461 #define SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN__SHIFT                                                              0x0
8462 #define SPI_WAVE_LIMIT_CNTL__VS_WAVE_GRAN__SHIFT                                                              0x2
8463 #define SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN__SHIFT                                                              0x4
8464 #define SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN__SHIFT                                                              0x6
8465 #define SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN_MASK                                                                0x00000003L
8466 #define SPI_WAVE_LIMIT_CNTL__VS_WAVE_GRAN_MASK                                                                0x0000000CL
8467 #define SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN_MASK                                                                0x00000030L
8468 #define SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN_MASK                                                                0x000000C0L
8469 //SPI_CONFIG_CNTL_2
8470 #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT                                    0x0
8471 #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT                                      0x4
8472 #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK                                      0x0000000FL
8473 #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK                                        0x000000F0L
8474 //SPI_CONFIG_CNTL_1
8475 #define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT                                                              0x0
8476 #define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT                                                     0x4
8477 #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT                                                             0x5
8478 #define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT                                                             0x7
8479 #define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT                                                   0x8
8480 #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT                                                            0x9
8481 #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT                                                             0xa
8482 #define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE__SHIFT                                                        0xe
8483 #define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE__SHIFT                                                        0xf
8484 #define SPI_CONFIG_CNTL_1__MAX_VTX_SYNC_CNT__SHIFT                                                            0x10
8485 #define SPI_CONFIG_CNTL_1__EN_USER_ACCUM__SHIFT                                                               0x15
8486 #define SPI_CONFIG_CNTL_1__RESERVED__SHIFT                                                                    0x16
8487 #define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK                                                                0x0000000FL
8488 #define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK                                                       0x00000010L
8489 #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK                                                               0x00000060L
8490 #define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK                                                               0x00000080L
8491 #define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK                                                     0x00000100L
8492 #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK                                                              0x00000200L
8493 #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK                                                               0x00003C00L
8494 #define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE_MASK                                                          0x00004000L
8495 #define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE_MASK                                                          0x00008000L
8496 #define SPI_CONFIG_CNTL_1__MAX_VTX_SYNC_CNT_MASK                                                              0x001F0000L
8497 #define SPI_CONFIG_CNTL_1__EN_USER_ACCUM_MASK                                                                 0x00200000L
8498 #define SPI_CONFIG_CNTL_1__RESERVED_MASK                                                                      0xFFC00000L
8499 //SPI_WF_LIFETIME_CNTL
8500 #define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT                                                            0x0
8501 #define SPI_WF_LIFETIME_CNTL__EN__SHIFT                                                                       0x4
8502 #define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK                                                              0x0000000FL
8503 #define SPI_WF_LIFETIME_CNTL__EN_MASK                                                                         0x00000010L
8504 //SPI_WF_LIFETIME_LIMIT_0
8505 #define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT                                                               0x0
8506 #define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT                                                               0x1f
8507 #define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK                                                                 0x7FFFFFFFL
8508 #define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK                                                                 0x80000000L
8509 //SPI_WF_LIFETIME_LIMIT_1
8510 #define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT                                                               0x0
8511 #define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT                                                               0x1f
8512 #define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK                                                                 0x7FFFFFFFL
8513 #define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK                                                                 0x80000000L
8514 //SPI_WF_LIFETIME_LIMIT_2
8515 #define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT                                                               0x0
8516 #define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT                                                               0x1f
8517 #define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK                                                                 0x7FFFFFFFL
8518 #define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK                                                                 0x80000000L
8519 //SPI_WF_LIFETIME_LIMIT_3
8520 #define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT                                                               0x0
8521 #define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT                                                               0x1f
8522 #define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK                                                                 0x7FFFFFFFL
8523 #define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK                                                                 0x80000000L
8524 //SPI_WF_LIFETIME_LIMIT_4
8525 #define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT                                                               0x0
8526 #define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT                                                               0x1f
8527 #define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK                                                                 0x7FFFFFFFL
8528 #define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK                                                                 0x80000000L
8529 //SPI_WF_LIFETIME_LIMIT_5
8530 #define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT                                                               0x0
8531 #define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT                                                               0x1f
8532 #define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK                                                                 0x7FFFFFFFL
8533 #define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK                                                                 0x80000000L
8534 //SPI_WF_LIFETIME_LIMIT_6
8535 #define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT                                                               0x0
8536 #define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT                                                               0x1f
8537 #define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK                                                                 0x7FFFFFFFL
8538 #define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK                                                                 0x80000000L
8539 //SPI_WF_LIFETIME_LIMIT_7
8540 #define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT                                                               0x0
8541 #define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT                                                               0x1f
8542 #define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK                                                                 0x7FFFFFFFL
8543 #define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK                                                                 0x80000000L
8544 //SPI_WF_LIFETIME_LIMIT_8
8545 #define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT                                                               0x0
8546 #define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT                                                               0x1f
8547 #define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK                                                                 0x7FFFFFFFL
8548 #define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK                                                                 0x80000000L
8549 //SPI_WF_LIFETIME_LIMIT_9
8550 #define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT                                                               0x0
8551 #define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT                                                               0x1f
8552 #define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK                                                                 0x7FFFFFFFL
8553 #define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK                                                                 0x80000000L
8554 //SPI_WF_LIFETIME_STATUS_0
8555 #define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT                                                              0x0
8556 #define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT                                                             0x1f
8557 #define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK                                                                0x7FFFFFFFL
8558 #define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK                                                               0x80000000L
8559 //SPI_WF_LIFETIME_STATUS_1
8560 #define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT                                                              0x0
8561 #define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT                                                             0x1f
8562 #define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK                                                                0x7FFFFFFFL
8563 #define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK                                                               0x80000000L
8564 //SPI_WF_LIFETIME_STATUS_2
8565 #define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT                                                              0x0
8566 #define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT                                                             0x1f
8567 #define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK                                                                0x7FFFFFFFL
8568 #define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK                                                               0x80000000L
8569 //SPI_WF_LIFETIME_STATUS_3
8570 #define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT                                                              0x0
8571 #define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT                                                             0x1f
8572 #define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK                                                                0x7FFFFFFFL
8573 #define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK                                                               0x80000000L
8574 //SPI_WF_LIFETIME_STATUS_4
8575 #define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT                                                              0x0
8576 #define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT                                                             0x1f
8577 #define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK                                                                0x7FFFFFFFL
8578 #define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK                                                               0x80000000L
8579 //SPI_WF_LIFETIME_STATUS_5
8580 #define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT                                                              0x0
8581 #define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT                                                             0x1f
8582 #define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK                                                                0x7FFFFFFFL
8583 #define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK                                                               0x80000000L
8584 //SPI_WF_LIFETIME_STATUS_6
8585 #define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT                                                              0x0
8586 #define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT                                                             0x1f
8587 #define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK                                                                0x7FFFFFFFL
8588 #define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK                                                               0x80000000L
8589 //SPI_WF_LIFETIME_STATUS_7
8590 #define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT                                                              0x0
8591 #define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT                                                             0x1f
8592 #define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK                                                                0x7FFFFFFFL
8593 #define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK                                                               0x80000000L
8594 //SPI_WF_LIFETIME_STATUS_8
8595 #define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT                                                              0x0
8596 #define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT                                                             0x1f
8597 #define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK                                                                0x7FFFFFFFL
8598 #define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK                                                               0x80000000L
8599 //SPI_WF_LIFETIME_STATUS_9
8600 #define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT                                                              0x0
8601 #define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT                                                             0x1f
8602 #define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK                                                                0x7FFFFFFFL
8603 #define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK                                                               0x80000000L
8604 //SPI_WF_LIFETIME_STATUS_10
8605 #define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT                                                             0x0
8606 #define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT                                                            0x1f
8607 #define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK                                                               0x7FFFFFFFL
8608 #define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK                                                              0x80000000L
8609 //SPI_WF_LIFETIME_STATUS_11
8610 #define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT                                                             0x0
8611 #define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT                                                            0x1f
8612 #define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK                                                               0x7FFFFFFFL
8613 #define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK                                                              0x80000000L
8614 //SPI_WF_LIFETIME_STATUS_12
8615 #define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT                                                             0x0
8616 #define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT                                                            0x1f
8617 #define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK                                                               0x7FFFFFFFL
8618 #define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK                                                              0x80000000L
8619 //SPI_WF_LIFETIME_STATUS_13
8620 #define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT                                                             0x0
8621 #define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT                                                            0x1f
8622 #define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK                                                               0x7FFFFFFFL
8623 #define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK                                                              0x80000000L
8624 //SPI_WF_LIFETIME_STATUS_14
8625 #define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT                                                             0x0
8626 #define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT                                                            0x1f
8627 #define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK                                                               0x7FFFFFFFL
8628 #define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK                                                              0x80000000L
8629 //SPI_WF_LIFETIME_STATUS_15
8630 #define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT                                                             0x0
8631 #define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT                                                            0x1f
8632 #define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK                                                               0x7FFFFFFFL
8633 #define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK                                                              0x80000000L
8634 //SPI_WF_LIFETIME_STATUS_16
8635 #define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT                                                             0x0
8636 #define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT                                                            0x1f
8637 #define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK                                                               0x7FFFFFFFL
8638 #define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK                                                              0x80000000L
8639 //SPI_WF_LIFETIME_STATUS_17
8640 #define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT                                                             0x0
8641 #define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT                                                            0x1f
8642 #define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK                                                               0x7FFFFFFFL
8643 #define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK                                                              0x80000000L
8644 //SPI_WF_LIFETIME_STATUS_18
8645 #define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT                                                             0x0
8646 #define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT                                                            0x1f
8647 #define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK                                                               0x7FFFFFFFL
8648 #define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK                                                              0x80000000L
8649 //SPI_WF_LIFETIME_STATUS_19
8650 #define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT                                                             0x0
8651 #define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT                                                            0x1f
8652 #define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK                                                               0x7FFFFFFFL
8653 #define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK                                                              0x80000000L
8654 //SPI_WF_LIFETIME_STATUS_20
8655 #define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT                                                             0x0
8656 #define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT                                                            0x1f
8657 #define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK                                                               0x7FFFFFFFL
8658 #define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK                                                              0x80000000L
8659 //SPI_LB_CTR_CTRL
8660 #define SPI_LB_CTR_CTRL__LOAD__SHIFT                                                                          0x0
8661 #define SPI_LB_CTR_CTRL__WAVES_SELECT__SHIFT                                                                  0x1
8662 #define SPI_LB_CTR_CTRL__CLEAR_ON_READ__SHIFT                                                                 0x3
8663 #define SPI_LB_CTR_CTRL__RESET_COUNTS__SHIFT                                                                  0x4
8664 #define SPI_LB_CTR_CTRL__LOAD_MASK                                                                            0x00000001L
8665 #define SPI_LB_CTR_CTRL__WAVES_SELECT_MASK                                                                    0x00000006L
8666 #define SPI_LB_CTR_CTRL__CLEAR_ON_READ_MASK                                                                   0x00000008L
8667 #define SPI_LB_CTR_CTRL__RESET_COUNTS_MASK                                                                    0x00000010L
8668 //SPI_LB_WGP_MASK
8669 #define SPI_LB_WGP_MASK__WGP_MASK__SHIFT                                                                      0x0
8670 #define SPI_LB_WGP_MASK__WGP_MASK_MASK                                                                        0xFFFFL
8671 //SPI_LB_DATA_REG
8672 #define SPI_LB_DATA_REG__CNT_DATA__SHIFT                                                                      0x0
8673 #define SPI_LB_DATA_REG__CNT_DATA_MASK                                                                        0xFFFFFFFFL
8674 //SPI_PG_ENABLE_STATIC_WGP_MASK
8675 #define SPI_PG_ENABLE_STATIC_WGP_MASK__WGP_MASK__SHIFT                                                        0x0
8676 #define SPI_PG_ENABLE_STATIC_WGP_MASK__WGP_MASK_MASK                                                          0xFFFFL
8677 //SPI_GDS_CREDITS
8678 #define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT                                                               0x0
8679 #define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT                                                                0x8
8680 #define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK                                                                 0x000000FFL
8681 #define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK                                                                  0x0000FF00L
8682 //SPI_SX_EXPORT_BUFFER_SIZES
8683 #define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT                                                  0x0
8684 #define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT                                               0x10
8685 #define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK                                                    0x0000FFFFL
8686 #define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK                                                 0xFFFF0000L
8687 //SPI_SX_SCOREBOARD_BUFFER_SIZES
8688 #define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT                                          0x0
8689 #define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT                                       0x10
8690 #define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK                                            0x0000FFFFL
8691 #define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK                                         0xFFFF0000L
8692 //SPI_CSQ_WF_ACTIVE_STATUS
8693 #define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT                                                               0x0
8694 #define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK                                                                 0xFFFFFFFFL
8695 //SPI_CSQ_WF_ACTIVE_COUNT_0
8696 #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT                                                               0x0
8697 #define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS__SHIFT                                                              0x10
8698 #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK                                                                 0x000007FFL
8699 #define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS_MASK                                                                0x07FF0000L
8700 //SPI_CSQ_WF_ACTIVE_COUNT_1
8701 #define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT                                                               0x0
8702 #define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS__SHIFT                                                              0x10
8703 #define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK                                                                 0x000007FFL
8704 #define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS_MASK                                                                0x07FF0000L
8705 //SPI_CSQ_WF_ACTIVE_COUNT_2
8706 #define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT                                                               0x0
8707 #define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS__SHIFT                                                              0x10
8708 #define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK                                                                 0x000007FFL
8709 #define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS_MASK                                                                0x07FF0000L
8710 //SPI_CSQ_WF_ACTIVE_COUNT_3
8711 #define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT                                                               0x0
8712 #define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS__SHIFT                                                              0x10
8713 #define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK                                                                 0x000007FFL
8714 #define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS_MASK                                                                0x07FF0000L
8715 //SPI_CSQ_WF_ACTIVE_COUNT_4
8716 #define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT                                                               0x0
8717 #define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS__SHIFT                                                              0x10
8718 #define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK                                                                 0x000007FFL
8719 #define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS_MASK                                                                0x07FF0000L
8720 //SPI_CSQ_WF_ACTIVE_COUNT_5
8721 #define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT                                                               0x0
8722 #define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS__SHIFT                                                              0x10
8723 #define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK                                                                 0x000007FFL
8724 #define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS_MASK                                                                0x07FF0000L
8725 //SPI_CSQ_WF_ACTIVE_COUNT_6
8726 #define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT                                                               0x0
8727 #define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS__SHIFT                                                              0x10
8728 #define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK                                                                 0x000007FFL
8729 #define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS_MASK                                                                0x07FF0000L
8730 //SPI_CSQ_WF_ACTIVE_COUNT_7
8731 #define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT                                                               0x0
8732 #define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS__SHIFT                                                              0x10
8733 #define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK                                                                 0x000007FFL
8734 #define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS_MASK                                                                0x07FF0000L
8735 //SPI_LB_DATA_WAVES
8736 #define SPI_LB_DATA_WAVES__COUNT0__SHIFT                                                                      0x0
8737 #define SPI_LB_DATA_WAVES__COUNT1__SHIFT                                                                      0x10
8738 #define SPI_LB_DATA_WAVES__COUNT0_MASK                                                                        0x0000FFFFL
8739 #define SPI_LB_DATA_WAVES__COUNT1_MASK                                                                        0xFFFF0000L
8740 //SPI_LB_DATA_PERWGP_WAVE_HSGS
8741 #define SPI_LB_DATA_PERWGP_WAVE_HSGS__WGP_USED_HS__SHIFT                                                      0x0
8742 #define SPI_LB_DATA_PERWGP_WAVE_HSGS__WGP_USED_GS__SHIFT                                                      0x10
8743 #define SPI_LB_DATA_PERWGP_WAVE_HSGS__WGP_USED_HS_MASK                                                        0x0000FFFFL
8744 #define SPI_LB_DATA_PERWGP_WAVE_HSGS__WGP_USED_GS_MASK                                                        0xFFFF0000L
8745 //SPI_LB_DATA_PERWGP_WAVE_VSPS
8746 #define SPI_LB_DATA_PERWGP_WAVE_VSPS__WGP_USED_VS__SHIFT                                                      0x0
8747 #define SPI_LB_DATA_PERWGP_WAVE_VSPS__WGP_USED_PS__SHIFT                                                      0x10
8748 #define SPI_LB_DATA_PERWGP_WAVE_VSPS__WGP_USED_VS_MASK                                                        0x0000FFFFL
8749 #define SPI_LB_DATA_PERWGP_WAVE_VSPS__WGP_USED_PS_MASK                                                        0xFFFF0000L
8750 //SPI_LB_DATA_PERWGP_WAVE_CS
8751 #define SPI_LB_DATA_PERWGP_WAVE_CS__ACTIVE__SHIFT                                                             0x0
8752 #define SPI_LB_DATA_PERWGP_WAVE_CS__ACTIVE_MASK                                                               0xFFFFL
8753 //SPI_P0_TRAP_SCREEN_PSBA_LO
8754 #define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT                                                           0x0
8755 #define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK                                                             0xFFFFFFFFL
8756 //SPI_P0_TRAP_SCREEN_PSBA_HI
8757 #define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT                                                           0x0
8758 #define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK                                                             0xFFL
8759 //SPI_P0_TRAP_SCREEN_PSMA_LO
8760 #define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT                                                           0x0
8761 #define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK                                                             0xFFFFFFFFL
8762 //SPI_P0_TRAP_SCREEN_PSMA_HI
8763 #define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT                                                           0x0
8764 #define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK                                                             0xFFL
8765 //SPI_P0_TRAP_SCREEN_GPR_MIN
8766 #define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT                                                           0x0
8767 #define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT                                                           0x6
8768 #define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK                                                             0x003FL
8769 #define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK                                                             0x03C0L
8770 //SPI_P1_TRAP_SCREEN_PSBA_LO
8771 #define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT                                                           0x0
8772 #define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK                                                             0xFFFFFFFFL
8773 //SPI_P1_TRAP_SCREEN_PSBA_HI
8774 #define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT                                                           0x0
8775 #define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK                                                             0xFFL
8776 //SPI_P1_TRAP_SCREEN_PSMA_LO
8777 #define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT                                                           0x0
8778 #define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK                                                             0xFFFFFFFFL
8779 //SPI_P1_TRAP_SCREEN_PSMA_HI
8780 #define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT                                                           0x0
8781 #define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK                                                             0xFFL
8782 //SPI_P1_TRAP_SCREEN_GPR_MIN
8783 #define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT                                                           0x0
8784 #define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT                                                           0x6
8785 #define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK                                                             0x003FL
8786 #define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK                                                             0x03C0L
8787 
8788 
8789 // addressBlock: gc_tpdec
8790 //TD_CNTL
8791 #define TD_CNTL__SYNC_PHASE_SH__SHIFT                                                                         0x0
8792 #define TD_CNTL__DISABLE_SAMPLER_NEG_SCALED_NUM_CLAMP__SHIFT                                                  0x3
8793 #define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT                                                                     0x4
8794 #define TD_CNTL__DISABLE_SAMPLER_MAX_NORM_NUM_CLAMP__SHIFT                                                    0x6
8795 #define TD_CNTL__PAD_STALL_EN__SHIFT                                                                          0x8
8796 #define TD_CNTL__EXTEND_LDS_STALL__SHIFT                                                                      0x9
8797 #define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT                                                                0xb
8798 #define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT                                                               0xf
8799 #define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT                                                                    0x10
8800 #define TD_CNTL__LD_FLOAT_MODE__SHIFT                                                                         0x12
8801 #define TD_CNTL__GATHER4_DX9_MODE__SHIFT                                                                      0x13
8802 #define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT                                                                0x14
8803 #define TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT                                                                  0x15
8804 #define TD_CNTL__DISABLE_ROUND_TO_ZERO_FOR_LARGE_FLOAT_TO_SMALL_FLOAT__SHIFT                                  0x16
8805 #define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT__SHIFT                                                            0x17
8806 #define TD_CNTL__ARBITER_OLDEST_PRIORITY__SHIFT                                                               0x19
8807 #define TD_CNTL__DONE_SCOREBOARD_DEPTH__SHIFT                                                                 0x1a
8808 #define TD_CNTL__SYNC_PHASE_SH_MASK                                                                           0x00000003L
8809 #define TD_CNTL__DISABLE_SAMPLER_NEG_SCALED_NUM_CLAMP_MASK                                                    0x00000008L
8810 #define TD_CNTL__SYNC_PHASE_VC_SMX_MASK                                                                       0x00000030L
8811 #define TD_CNTL__DISABLE_SAMPLER_MAX_NORM_NUM_CLAMP_MASK                                                      0x00000040L
8812 #define TD_CNTL__PAD_STALL_EN_MASK                                                                            0x00000100L
8813 #define TD_CNTL__EXTEND_LDS_STALL_MASK                                                                        0x00000600L
8814 #define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK                                                                  0x00001800L
8815 #define TD_CNTL__PRECISION_COMPATIBILITY_MASK                                                                 0x00008000L
8816 #define TD_CNTL__GATHER4_FLOAT_MODE_MASK                                                                      0x00010000L
8817 #define TD_CNTL__LD_FLOAT_MODE_MASK                                                                           0x00040000L
8818 #define TD_CNTL__GATHER4_DX9_MODE_MASK                                                                        0x00080000L
8819 #define TD_CNTL__DISABLE_POWER_THROTTLE_MASK                                                                  0x00100000L
8820 #define TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK                                                                    0x00200000L
8821 #define TD_CNTL__DISABLE_ROUND_TO_ZERO_FOR_LARGE_FLOAT_TO_SMALL_FLOAT_MASK                                    0x00400000L
8822 #define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT_MASK                                                              0x00800000L
8823 #define TD_CNTL__ARBITER_OLDEST_PRIORITY_MASK                                                                 0x02000000L
8824 #define TD_CNTL__DONE_SCOREBOARD_DEPTH_MASK                                                                   0x7C000000L
8825 //TD_STATUS
8826 #define TD_STATUS__BUSY__SHIFT                                                                                0x1f
8827 #define TD_STATUS__BUSY_MASK                                                                                  0x80000000L
8828 //TD_POWER_CNTL
8829 #define TD_POWER_CNTL__FORCE_SAMPLER_CLK_TO_CORE__SHIFT                                                       0x0
8830 #define TD_POWER_CNTL__FORCE_NOFILTER_CLK_TO_CORE__SHIFT                                                      0x1
8831 #define TD_POWER_CNTL__SAMPLER_CLK_VALID_DELAY__SHIFT                                                         0x2
8832 #define TD_POWER_CNTL__NOFILTER_CLK_VALID_DELAY__SHIFT                                                        0x5
8833 #define TD_POWER_CNTL__DISABLE_NOFILTER_FORMATTER_POWER_OPT__SHIFT                                            0x8
8834 #define TD_POWER_CNTL__FORCE_NOFILTER_D16_FORMATTERS_ON__SHIFT                                                0x9
8835 #define TD_POWER_CNTL__FORCE_SAMPLER_CLK_TO_CORE_MASK                                                         0x00000001L
8836 #define TD_POWER_CNTL__FORCE_NOFILTER_CLK_TO_CORE_MASK                                                        0x00000002L
8837 #define TD_POWER_CNTL__SAMPLER_CLK_VALID_DELAY_MASK                                                           0x0000001CL
8838 #define TD_POWER_CNTL__NOFILTER_CLK_VALID_DELAY_MASK                                                          0x000000E0L
8839 #define TD_POWER_CNTL__DISABLE_NOFILTER_FORMATTER_POWER_OPT_MASK                                              0x00000100L
8840 #define TD_POWER_CNTL__FORCE_NOFILTER_D16_FORMATTERS_ON_MASK                                                  0x00000200L
8841 //TD_DSM_CNTL
8842 #define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA__SHIFT                                                  0x0
8843 #define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE__SHIFT                                                 0x2
8844 #define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA__SHIFT                                                  0x3
8845 #define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE__SHIFT                                                 0x5
8846 #define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA__SHIFT                                                     0x6
8847 #define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE__SHIFT                                                    0x8
8848 #define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA_MASK                                                    0x00000003L
8849 #define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE_MASK                                                   0x00000004L
8850 #define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA_MASK                                                    0x00000018L
8851 #define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE_MASK                                                   0x00000020L
8852 #define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA_MASK                                                       0x000000C0L
8853 #define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE_MASK                                                      0x00000100L
8854 //TD_DSM_CNTL2
8855 #define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT__SHIFT                                                0x0
8856 #define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY__SHIFT                                                0x2
8857 #define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT__SHIFT                                                0x3
8858 #define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY__SHIFT                                                0x5
8859 #define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT__SHIFT                                                   0x6
8860 #define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY__SHIFT                                                   0x8
8861 #define TD_DSM_CNTL2__TD_INJECT_DELAY__SHIFT                                                                  0x1a
8862 #define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT_MASK                                                  0x00000003L
8863 #define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY_MASK                                                  0x00000004L
8864 #define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT_MASK                                                  0x00000018L
8865 #define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY_MASK                                                  0x00000020L
8866 #define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT_MASK                                                     0x000000C0L
8867 #define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY_MASK                                                     0x00000100L
8868 #define TD_DSM_CNTL2__TD_INJECT_DELAY_MASK                                                                    0xFC000000L
8869 //TD_SCRATCH
8870 #define TD_SCRATCH__SCRATCH__SHIFT                                                                            0x0
8871 #define TD_SCRATCH__SCRATCH_MASK                                                                              0xFFFFFFFFL
8872 //TA_POWER_CNTL
8873 #define TA_POWER_CNTL__SAMPLER_CLK_VALID_DELAY__SHIFT                                                         0x0
8874 #define TA_POWER_CNTL__SAMPLER_CLK_EN_MODE__SHIFT                                                             0x3
8875 #define TA_POWER_CNTL__NOSAMPLER_CLK_VALID_DELAY__SHIFT                                                       0x10
8876 #define TA_POWER_CNTL__NOSAMPLER_CLK_EN_MODE__SHIFT                                                           0x13
8877 #define TA_POWER_CNTL__SAMPLER_CLK_VALID_DELAY_MASK                                                           0x00000007L
8878 #define TA_POWER_CNTL__SAMPLER_CLK_EN_MODE_MASK                                                               0x00000008L
8879 #define TA_POWER_CNTL__NOSAMPLER_CLK_VALID_DELAY_MASK                                                         0x00070000L
8880 #define TA_POWER_CNTL__NOSAMPLER_CLK_EN_MODE_MASK                                                             0x00080000L
8881 //TA_CNTL
8882 #define TA_CNTL__FX_XNACK_CREDIT__SHIFT                                                                       0x0
8883 #define TA_CNTL__ALIGNER_CREDIT__SHIFT                                                                        0x10
8884 #define TA_CNTL__TD_FIFO_CREDIT__SHIFT                                                                        0x16
8885 #define TA_CNTL__FX_XNACK_CREDIT_MASK                                                                         0x0000007FL
8886 #define TA_CNTL__ALIGNER_CREDIT_MASK                                                                          0x001F0000L
8887 #define TA_CNTL__TD_FIFO_CREDIT_MASK                                                                          0xFFC00000L
8888 //TA_CNTL_AUX
8889 #define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT                                                                  0x0
8890 #define TA_CNTL_AUX__RESERVED__SHIFT                                                                          0x1
8891 #define TA_CNTL_AUX__DERIV_ADJUST_DIS__SHIFT                                                                  0x4
8892 #define TA_CNTL_AUX__TFAULT_EN_OVERRIDE__SHIFT                                                                0x5
8893 #define TA_CNTL_AUX__GATHERH_DST_SEL__SHIFT                                                                   0x6
8894 #define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE__SHIFT                                                        0x7
8895 #define TA_CNTL_AUX__ANISO_MAG_STEP_CLAMP__SHIFT                                                              0x8
8896 #define TA_CNTL_AUX__AUTO_ALIGN_FORMAT__SHIFT                                                                 0x9
8897 #define TA_CNTL_AUX__ANISO_HALF_THRESH__SHIFT                                                                 0xa
8898 #define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS__SHIFT                                                              0xc
8899 #define TA_CNTL_AUX__ANISO_STEP_ORDER__SHIFT                                                                  0xd
8900 #define TA_CNTL_AUX__ANISO_STEP__SHIFT                                                                        0xe
8901 #define TA_CNTL_AUX__MINMAG_UNNORM__SHIFT                                                                     0xf
8902 #define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT                                                                 0x10
8903 #define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT                                                                   0x11
8904 #define TA_CNTL_AUX__ANISO_TAP__SHIFT                                                                         0x12
8905 #define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE__SHIFT                                                      0x14
8906 #define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE__SHIFT                                                 0x15
8907 #define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE__SHIFT                                                          0x16
8908 #define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE__SHIFT                                                 0x17
8909 #define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE__SHIFT                                                  0x18
8910 #define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE__SHIFT                                               0x19
8911 #define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE__SHIFT                                                     0x1a
8912 #define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE__SHIFT                                                         0x1b
8913 #define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP__SHIFT                                                               0x1c
8914 #define TA_CNTL_AUX__TRUNC_SMALL_NEG__SHIFT                                                                   0x1d
8915 #define TA_CNTL_AUX__ARRAY_ROUND_MODE__SHIFT                                                                  0x1e
8916 #define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK                                                                    0x00000001L
8917 #define TA_CNTL_AUX__RESERVED_MASK                                                                            0x0000000EL
8918 #define TA_CNTL_AUX__DERIV_ADJUST_DIS_MASK                                                                    0x00000010L
8919 #define TA_CNTL_AUX__TFAULT_EN_OVERRIDE_MASK                                                                  0x00000020L
8920 #define TA_CNTL_AUX__GATHERH_DST_SEL_MASK                                                                     0x00000040L
8921 #define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE_MASK                                                          0x00000080L
8922 #define TA_CNTL_AUX__ANISO_MAG_STEP_CLAMP_MASK                                                                0x00000100L
8923 #define TA_CNTL_AUX__AUTO_ALIGN_FORMAT_MASK                                                                   0x00000200L
8924 #define TA_CNTL_AUX__ANISO_HALF_THRESH_MASK                                                                   0x00000C00L
8925 #define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS_MASK                                                                0x00001000L
8926 #define TA_CNTL_AUX__ANISO_STEP_ORDER_MASK                                                                    0x00002000L
8927 #define TA_CNTL_AUX__ANISO_STEP_MASK                                                                          0x00004000L
8928 #define TA_CNTL_AUX__MINMAG_UNNORM_MASK                                                                       0x00008000L
8929 #define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK                                                                   0x00010000L
8930 #define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK                                                                     0x00020000L
8931 #define TA_CNTL_AUX__ANISO_TAP_MASK                                                                           0x00040000L
8932 #define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE_MASK                                                        0x00100000L
8933 #define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE_MASK                                                   0x00200000L
8934 #define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE_MASK                                                            0x00400000L
8935 #define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE_MASK                                                   0x00800000L
8936 #define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE_MASK                                                    0x01000000L
8937 #define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE_MASK                                                 0x02000000L
8938 #define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE_MASK                                                       0x04000000L
8939 #define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE_MASK                                                           0x08000000L
8940 #define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP_MASK                                                                 0x10000000L
8941 #define TA_CNTL_AUX__TRUNC_SMALL_NEG_MASK                                                                     0x20000000L
8942 #define TA_CNTL_AUX__ARRAY_ROUND_MODE_MASK                                                                    0xC0000000L
8943 //TA_RESERVED_010C
8944 #define TA_RESERVED_010C__Unused__SHIFT                                                                       0x0
8945 #define TA_RESERVED_010C__Unused_MASK                                                                         0xFFFFFFFFL
8946 //TA_STATUS
8947 #define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT                                                                     0xc
8948 #define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT                                                                     0xd
8949 #define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT                                                                     0xe
8950 #define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT                                                                     0x10
8951 #define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT                                                                     0x11
8952 #define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT                                                                     0x12
8953 #define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT                                                                     0x14
8954 #define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT                                                                     0x15
8955 #define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT                                                                     0x16
8956 #define TA_STATUS__IN_BUSY__SHIFT                                                                             0x18
8957 #define TA_STATUS__FG_BUSY__SHIFT                                                                             0x19
8958 #define TA_STATUS__LA_BUSY__SHIFT                                                                             0x1a
8959 #define TA_STATUS__FL_BUSY__SHIFT                                                                             0x1b
8960 #define TA_STATUS__TA_BUSY__SHIFT                                                                             0x1c
8961 #define TA_STATUS__FA_BUSY__SHIFT                                                                             0x1d
8962 #define TA_STATUS__AL_BUSY__SHIFT                                                                             0x1e
8963 #define TA_STATUS__BUSY__SHIFT                                                                                0x1f
8964 #define TA_STATUS__FG_PFIFO_EMPTYB_MASK                                                                       0x00001000L
8965 #define TA_STATUS__FG_LFIFO_EMPTYB_MASK                                                                       0x00002000L
8966 #define TA_STATUS__FG_SFIFO_EMPTYB_MASK                                                                       0x00004000L
8967 #define TA_STATUS__FL_PFIFO_EMPTYB_MASK                                                                       0x00010000L
8968 #define TA_STATUS__FL_LFIFO_EMPTYB_MASK                                                                       0x00020000L
8969 #define TA_STATUS__FL_SFIFO_EMPTYB_MASK                                                                       0x00040000L
8970 #define TA_STATUS__FA_PFIFO_EMPTYB_MASK                                                                       0x00100000L
8971 #define TA_STATUS__FA_LFIFO_EMPTYB_MASK                                                                       0x00200000L
8972 #define TA_STATUS__FA_SFIFO_EMPTYB_MASK                                                                       0x00400000L
8973 #define TA_STATUS__IN_BUSY_MASK                                                                               0x01000000L
8974 #define TA_STATUS__FG_BUSY_MASK                                                                               0x02000000L
8975 #define TA_STATUS__LA_BUSY_MASK                                                                               0x04000000L
8976 #define TA_STATUS__FL_BUSY_MASK                                                                               0x08000000L
8977 #define TA_STATUS__TA_BUSY_MASK                                                                               0x10000000L
8978 #define TA_STATUS__FA_BUSY_MASK                                                                               0x20000000L
8979 #define TA_STATUS__AL_BUSY_MASK                                                                               0x40000000L
8980 #define TA_STATUS__BUSY_MASK                                                                                  0x80000000L
8981 //TA_SCRATCH
8982 #define TA_SCRATCH__SCRATCH__SHIFT                                                                            0x0
8983 #define TA_SCRATCH__SCRATCH_MASK                                                                              0xFFFFFFFFL
8984 
8985 
8986 // addressBlock: gc_gdsdec
8987 //GDS_CONFIG
8988 #define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT                                                                  0x1
8989 #define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT                                                                  0x3
8990 #define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT                                                                  0x5
8991 #define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT                                                                  0x7
8992 #define GDS_CONFIG__UNUSED__SHIFT                                                                             0x9
8993 #define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK                                                                    0x00000006L
8994 #define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK                                                                    0x00000018L
8995 #define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK                                                                    0x00000060L
8996 #define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK                                                                    0x00000180L
8997 #define GDS_CONFIG__UNUSED_MASK                                                                               0xFFFFFE00L
8998 //GDS_CNTL_STATUS
8999 #define GDS_CNTL_STATUS__GDS_BUSY__SHIFT                                                                      0x0
9000 #define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT                                                                0x1
9001 #define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT                                                                  0x2
9002 #define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT                                                              0x3
9003 #define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT                                                              0x4
9004 #define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT                                                                   0x5
9005 #define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT                                                                   0x6
9006 #define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT                                                                0x7
9007 #define GDS_CNTL_STATUS__DS_BUSY__SHIFT                                                                       0x8
9008 #define GDS_CNTL_STATUS__GWS_BUSY__SHIFT                                                                      0x9
9009 #define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT                                                                 0xa
9010 #define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT                                                                  0xb
9011 #define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT                                                                  0xc
9012 #define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT                                                                  0xd
9013 #define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT                                                                  0xe
9014 #define GDS_CNTL_STATUS__UNUSED__SHIFT                                                                        0xf
9015 #define GDS_CNTL_STATUS__GDS_BUSY_MASK                                                                        0x00000001L
9016 #define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK                                                                  0x00000002L
9017 #define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK                                                                    0x00000004L
9018 #define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK                                                                0x00000008L
9019 #define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK                                                                0x00000010L
9020 #define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK                                                                     0x00000020L
9021 #define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK                                                                     0x00000040L
9022 #define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK                                                                  0x00000080L
9023 #define GDS_CNTL_STATUS__DS_BUSY_MASK                                                                         0x00000100L
9024 #define GDS_CNTL_STATUS__GWS_BUSY_MASK                                                                        0x00000200L
9025 #define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK                                                                   0x00000400L
9026 #define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK                                                                    0x00000800L
9027 #define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK                                                                    0x00001000L
9028 #define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK                                                                    0x00002000L
9029 #define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK                                                                    0x00004000L
9030 #define GDS_CNTL_STATUS__UNUSED_MASK                                                                          0xFFFF8000L
9031 //GDS_ENHANCE
9032 #define GDS_ENHANCE__MISC__SHIFT                                                                              0x0
9033 #define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT                                                                    0x10
9034 #define GDS_ENHANCE__CGPG_RESTORE__SHIFT                                                                      0x11
9035 #define GDS_ENHANCE__UNUSED__SHIFT                                                                            0x12
9036 #define GDS_ENHANCE__MISC_MASK                                                                                0x0000FFFFL
9037 #define GDS_ENHANCE__AUTO_INC_INDEX_MASK                                                                      0x00010000L
9038 #define GDS_ENHANCE__CGPG_RESTORE_MASK                                                                        0x00020000L
9039 #define GDS_ENHANCE__UNUSED_MASK                                                                              0xFFFC0000L
9040 //GDS_PROTECTION_FAULT
9041 #define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT                                                                0x0
9042 #define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT                                                           0x1
9043 #define GDS_PROTECTION_FAULT__GRBM__SHIFT                                                                     0x2
9044 #define GDS_PROTECTION_FAULT__SH_ID__SHIFT                                                                    0x3
9045 #define GDS_PROTECTION_FAULT__CU_ID__SHIFT                                                                    0x6
9046 #define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT                                                                  0xa
9047 #define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT                                                                  0xc
9048 #define GDS_PROTECTION_FAULT__ADDRESS__SHIFT                                                                  0x10
9049 #define GDS_PROTECTION_FAULT__WRITE_DIS_MASK                                                                  0x00000001L
9050 #define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK                                                             0x00000002L
9051 #define GDS_PROTECTION_FAULT__GRBM_MASK                                                                       0x00000004L
9052 #define GDS_PROTECTION_FAULT__SH_ID_MASK                                                                      0x00000038L
9053 #define GDS_PROTECTION_FAULT__CU_ID_MASK                                                                      0x000003C0L
9054 #define GDS_PROTECTION_FAULT__SIMD_ID_MASK                                                                    0x00000C00L
9055 #define GDS_PROTECTION_FAULT__WAVE_ID_MASK                                                                    0x0000F000L
9056 #define GDS_PROTECTION_FAULT__ADDRESS_MASK                                                                    0xFFFF0000L
9057 //GDS_VM_PROTECTION_FAULT
9058 #define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT                                                             0x0
9059 #define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT                                                        0x1
9060 #define GDS_VM_PROTECTION_FAULT__GWS__SHIFT                                                                   0x2
9061 #define GDS_VM_PROTECTION_FAULT__OA__SHIFT                                                                    0x3
9062 #define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT                                                                  0x4
9063 #define GDS_VM_PROTECTION_FAULT__UNUSED1__SHIFT                                                               0x6
9064 #define GDS_VM_PROTECTION_FAULT__VMID__SHIFT                                                                  0x8
9065 #define GDS_VM_PROTECTION_FAULT__UNUSED2__SHIFT                                                               0xc
9066 #define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT                                                               0x10
9067 #define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK                                                               0x00000001L
9068 #define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK                                                          0x00000002L
9069 #define GDS_VM_PROTECTION_FAULT__GWS_MASK                                                                     0x00000004L
9070 #define GDS_VM_PROTECTION_FAULT__OA_MASK                                                                      0x00000008L
9071 #define GDS_VM_PROTECTION_FAULT__GRBM_MASK                                                                    0x00000010L
9072 #define GDS_VM_PROTECTION_FAULT__UNUSED1_MASK                                                                 0x000000C0L
9073 #define GDS_VM_PROTECTION_FAULT__VMID_MASK                                                                    0x00000F00L
9074 #define GDS_VM_PROTECTION_FAULT__UNUSED2_MASK                                                                 0x0000F000L
9075 #define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK                                                                 0xFFFF0000L
9076 //GDS_EDC_CNT
9077 #define GDS_EDC_CNT__GDS_MEM_DED__SHIFT                                                                       0x0
9078 #define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED__SHIFT                                                               0x2
9079 #define GDS_EDC_CNT__GDS_MEM_SEC__SHIFT                                                                       0x4
9080 #define GDS_EDC_CNT__UNUSED__SHIFT                                                                            0x6
9081 #define GDS_EDC_CNT__GDS_MEM_DED_MASK                                                                         0x00000003L
9082 #define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED_MASK                                                                 0x0000000CL
9083 #define GDS_EDC_CNT__GDS_MEM_SEC_MASK                                                                         0x00000030L
9084 #define GDS_EDC_CNT__UNUSED_MASK                                                                              0xFFFFFFC0L
9085 //GDS_EDC_GRBM_CNT
9086 #define GDS_EDC_GRBM_CNT__DED__SHIFT                                                                          0x0
9087 #define GDS_EDC_GRBM_CNT__SEC__SHIFT                                                                          0x2
9088 #define GDS_EDC_GRBM_CNT__UNUSED__SHIFT                                                                       0x4
9089 #define GDS_EDC_GRBM_CNT__DED_MASK                                                                            0x00000003L
9090 #define GDS_EDC_GRBM_CNT__SEC_MASK                                                                            0x0000000CL
9091 #define GDS_EDC_GRBM_CNT__UNUSED_MASK                                                                         0xFFFFFFF0L
9092 //GDS_EDC_OA_DED
9093 #define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT                                                            0x0
9094 #define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT                                                            0x1
9095 #define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT                                                                     0x2
9096 #define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED__SHIFT                                                             0x3
9097 #define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT                                                                  0x4
9098 #define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT                                                                  0x5
9099 #define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT                                                                  0x6
9100 #define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT                                                                  0x7
9101 #define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT                                                                  0x8
9102 #define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT                                                                  0x9
9103 #define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT                                                                  0xa
9104 #define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT                                                                  0xb
9105 #define GDS_EDC_OA_DED__UNUSED1__SHIFT                                                                        0xc
9106 #define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK                                                              0x00000001L
9107 #define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK                                                              0x00000002L
9108 #define GDS_EDC_OA_DED__ME0_CS_DED_MASK                                                                       0x00000004L
9109 #define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED_MASK                                                               0x00000008L
9110 #define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK                                                                    0x00000010L
9111 #define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK                                                                    0x00000020L
9112 #define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK                                                                    0x00000040L
9113 #define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK                                                                    0x00000080L
9114 #define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK                                                                    0x00000100L
9115 #define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK                                                                    0x00000200L
9116 #define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK                                                                    0x00000400L
9117 #define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK                                                                    0x00000800L
9118 #define GDS_EDC_OA_DED__UNUSED1_MASK                                                                          0xFFFFF000L
9119 //GDS_DSM_CNTL
9120 #define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0__SHIFT                                                 0x0
9121 #define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1__SHIFT                                                 0x1
9122 #define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE__SHIFT                                                      0x2
9123 #define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0__SHIFT                                         0x3
9124 #define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1__SHIFT                                         0x4
9125 #define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE__SHIFT                                              0x5
9126 #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0__SHIFT                                         0x6
9127 #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1__SHIFT                                         0x7
9128 #define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE__SHIFT                                              0x8
9129 #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0__SHIFT                                        0x9
9130 #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1__SHIFT                                        0xa
9131 #define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE__SHIFT                                             0xb
9132 #define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0__SHIFT                                            0xc
9133 #define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1__SHIFT                                            0xd
9134 #define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE__SHIFT                                                 0xe
9135 #define GDS_DSM_CNTL__UNUSED__SHIFT                                                                           0xf
9136 #define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0_MASK                                                   0x00000001L
9137 #define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1_MASK                                                   0x00000002L
9138 #define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE_MASK                                                        0x00000004L
9139 #define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0_MASK                                           0x00000008L
9140 #define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1_MASK                                           0x00000010L
9141 #define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE_MASK                                                0x00000020L
9142 #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0_MASK                                           0x00000040L
9143 #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1_MASK                                           0x00000080L
9144 #define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE_MASK                                                0x00000100L
9145 #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0_MASK                                          0x00000200L
9146 #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1_MASK                                          0x00000400L
9147 #define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE_MASK                                               0x00000800L
9148 #define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0_MASK                                              0x00001000L
9149 #define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1_MASK                                              0x00002000L
9150 #define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE_MASK                                                   0x00004000L
9151 #define GDS_DSM_CNTL__UNUSED_MASK                                                                             0xFFFF8000L
9152 //GDS_EDC_OA_PHY_CNT
9153 #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC__SHIFT                                                        0x0
9154 #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED__SHIFT                                                        0x2
9155 #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC__SHIFT                                                        0x4
9156 #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED__SHIFT                                                        0x6
9157 #define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED__SHIFT                                                       0x8
9158 #define GDS_EDC_OA_PHY_CNT__UNUSED1__SHIFT                                                                    0xa
9159 #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC_MASK                                                          0x00000003L
9160 #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED_MASK                                                          0x0000000CL
9161 #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC_MASK                                                          0x00000030L
9162 #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED_MASK                                                          0x000000C0L
9163 #define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED_MASK                                                         0x00000300L
9164 #define GDS_EDC_OA_PHY_CNT__UNUSED1_MASK                                                                      0xFFFFFC00L
9165 //GDS_EDC_OA_PIPE_CNT
9166 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC__SHIFT                                                    0x0
9167 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED__SHIFT                                                    0x2
9168 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC__SHIFT                                                    0x4
9169 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED__SHIFT                                                    0x6
9170 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC__SHIFT                                                    0x8
9171 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED__SHIFT                                                    0xa
9172 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC__SHIFT                                                    0xc
9173 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED__SHIFT                                                    0xe
9174 #define GDS_EDC_OA_PIPE_CNT__UNUSED__SHIFT                                                                    0x10
9175 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC_MASK                                                      0x00000003L
9176 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED_MASK                                                      0x0000000CL
9177 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC_MASK                                                      0x00000030L
9178 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED_MASK                                                      0x000000C0L
9179 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC_MASK                                                      0x00000300L
9180 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED_MASK                                                      0x00000C00L
9181 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC_MASK                                                      0x00003000L
9182 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED_MASK                                                      0x0000C000L
9183 #define GDS_EDC_OA_PIPE_CNT__UNUSED_MASK                                                                      0xFFFF0000L
9184 //GDS_DSM_CNTL2
9185 #define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT__SHIFT                                                     0x0
9186 #define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY__SHIFT                                                     0x2
9187 #define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT__SHIFT                                             0x3
9188 #define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY__SHIFT                                             0x5
9189 #define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT__SHIFT                                             0x6
9190 #define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY__SHIFT                                             0x8
9191 #define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT                                            0x9
9192 #define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY__SHIFT                                            0xb
9193 #define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT__SHIFT                                                0xc
9194 #define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY__SHIFT                                                0xe
9195 #define GDS_DSM_CNTL2__UNUSED__SHIFT                                                                          0xf
9196 #define GDS_DSM_CNTL2__GDS_INJECT_DELAY__SHIFT                                                                0x1a
9197 #define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT_MASK                                                       0x00000003L
9198 #define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY_MASK                                                       0x00000004L
9199 #define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT_MASK                                               0x00000018L
9200 #define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY_MASK                                               0x00000020L
9201 #define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT_MASK                                               0x000000C0L
9202 #define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY_MASK                                               0x00000100L
9203 #define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT_MASK                                              0x00000600L
9204 #define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY_MASK                                              0x00000800L
9205 #define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT_MASK                                                  0x00003000L
9206 #define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY_MASK                                                  0x00004000L
9207 #define GDS_DSM_CNTL2__UNUSED_MASK                                                                            0x03FF8000L
9208 #define GDS_DSM_CNTL2__GDS_INJECT_DELAY_MASK                                                                  0xFC000000L
9209 //GDS_WD_GDS_CSB
9210 #define GDS_WD_GDS_CSB__COUNTER__SHIFT                                                                        0x0
9211 #define GDS_WD_GDS_CSB__UNUSED__SHIFT                                                                         0xd
9212 #define GDS_WD_GDS_CSB__COUNTER_MASK                                                                          0x00001FFFL
9213 #define GDS_WD_GDS_CSB__UNUSED_MASK                                                                           0xFFFFE000L
9214 
9215 
9216 // addressBlock: gc_rbdec
9217 //DB_DEBUG
9218 #define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT                                                       0x0
9219 #define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT                                                         0x1
9220 #define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT                                                                    0x2
9221 #define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT                                                              0x3
9222 #define DB_DEBUG__FORCE_Z_MODE__SHIFT                                                                         0x4
9223 #define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT                                                               0x6
9224 #define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT                                                             0x7
9225 #define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT                                                               0x8
9226 #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT                                                              0xa
9227 #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT                                                              0xc
9228 #define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT                                                                 0xe
9229 #define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT                                                           0xf
9230 #define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT                                                              0x10
9231 #define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT                                                                  0x11
9232 #define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT                                                               0x12
9233 #define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT                                                             0x13
9234 #define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT                                                                    0x15
9235 #define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT                                                0x16
9236 #define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT                                                    0x17
9237 #define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT                                                           0x18
9238 #define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT                                                                   0x1c
9239 #define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT                                                           0x1d
9240 #define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT                                                           0x1e
9241 #define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT                                                           0x1f
9242 #define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK                                                         0x00000001L
9243 #define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK                                                           0x00000002L
9244 #define DB_DEBUG__FETCH_FULL_Z_TILE_MASK                                                                      0x00000004L
9245 #define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK                                                                0x00000008L
9246 #define DB_DEBUG__FORCE_Z_MODE_MASK                                                                           0x00000030L
9247 #define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK                                                                 0x00000040L
9248 #define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK                                                               0x00000080L
9249 #define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK                                                                 0x00000300L
9250 #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK                                                                0x00000C00L
9251 #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK                                                                0x00003000L
9252 #define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK                                                                   0x00004000L
9253 #define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK                                                             0x00008000L
9254 #define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK                                                                0x00010000L
9255 #define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK                                                                    0x00020000L
9256 #define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK                                                                 0x00040000L
9257 #define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK                                                               0x00180000L
9258 #define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK                                                                      0x00200000L
9259 #define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK                                                  0x00400000L
9260 #define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK                                                      0x00800000L
9261 #define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK                                                             0x0F000000L
9262 #define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK                                                                     0x10000000L
9263 #define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK                                                             0x20000000L
9264 #define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK                                                             0x40000000L
9265 #define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK                                                             0x80000000L
9266 //DB_DEBUG2
9267 #define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT                                                            0x0
9268 #define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT                                                          0x1
9269 #define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT                                                            0x2
9270 #define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT                                                                 0x3
9271 #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT                                                        0x4
9272 #define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL__SHIFT                                                            0x5
9273 #define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ__SHIFT                                                        0x6
9274 #define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL__SHIFT                                                        0x7
9275 #define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE__SHIFT                                                     0x8
9276 #define DB_DEBUG2__CLK_OFF_DELAY__SHIFT                                                                       0x9
9277 #define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT                                                    0xe
9278 #define DB_DEBUG2__FULL_TILE_CACHE_EVICT_ON_HALF_FULL__SHIFT                                                  0xf
9279 #define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES__SHIFT                                                          0x10
9280 #define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT                                                         0x11
9281 #define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT                                                         0x12
9282 #define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT                                                        0x13
9283 #define DB_DEBUG2__FULL_TILE_WAVE_BREAK_MODE__SHIFT                                                           0x14
9284 #define DB_DEBUG2__DUAL_PIPE_REZ_STALL_MANUAL_CONTROL__SHIFT                                                  0x16
9285 #define DB_DEBUG2__DUAL_PIPE_REZ_STALL_SELECT_NEW__SHIFT                                                      0x17
9286 #define DB_DEBUG2__FORCE_ITERATE_256__SHIFT                                                                   0x18
9287 #define DB_DEBUG2__DISABLE_VR_OBJ_PRIM_ID__SHIFT                                                              0x1a
9288 #define DB_DEBUG2__DISABLE_VR_PS_INVOKE__SHIFT                                                                0x1b
9289 #define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT                                                             0x1c
9290 #define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT                                                        0x1d
9291 #define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT                                                    0x1e
9292 #define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT                                                0x1f
9293 #define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK                                                              0x00000001L
9294 #define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK                                                            0x00000002L
9295 #define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK                                                              0x00000004L
9296 #define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK                                                                   0x00000008L
9297 #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK                                                          0x00000010L
9298 #define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_MASK                                                              0x00000020L
9299 #define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ_MASK                                                          0x00000040L
9300 #define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL_MASK                                                          0x00000080L
9301 #define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE_MASK                                                       0x00000100L
9302 #define DB_DEBUG2__CLK_OFF_DELAY_MASK                                                                         0x00003E00L
9303 #define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK                                                      0x00004000L
9304 #define DB_DEBUG2__FULL_TILE_CACHE_EVICT_ON_HALF_FULL_MASK                                                    0x00008000L
9305 #define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES_MASK                                                            0x00010000L
9306 #define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK                                                           0x00020000L
9307 #define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK                                                           0x00040000L
9308 #define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK                                                          0x00080000L
9309 #define DB_DEBUG2__FULL_TILE_WAVE_BREAK_MODE_MASK                                                             0x00300000L
9310 #define DB_DEBUG2__DUAL_PIPE_REZ_STALL_MANUAL_CONTROL_MASK                                                    0x00400000L
9311 #define DB_DEBUG2__DUAL_PIPE_REZ_STALL_SELECT_NEW_MASK                                                        0x00800000L
9312 #define DB_DEBUG2__FORCE_ITERATE_256_MASK                                                                     0x03000000L
9313 #define DB_DEBUG2__DISABLE_VR_OBJ_PRIM_ID_MASK                                                                0x04000000L
9314 #define DB_DEBUG2__DISABLE_VR_PS_INVOKE_MASK                                                                  0x08000000L
9315 #define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK                                                               0x10000000L
9316 #define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK                                                          0x20000000L
9317 #define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK                                                      0x40000000L
9318 #define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK                                                  0x80000000L
9319 //DB_DEBUG3
9320 #define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION__SHIFT                                                     0x0
9321 #define DB_DEBUG3__DISABLE_RELOAD_CONTEXT_DRAW_DATA__SHIFT                                                    0x1
9322 #define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT                                                                    0x2
9323 #define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT                                                     0x3
9324 #define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT                                                          0x4
9325 #define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT                                                             0x5
9326 #define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT                                                              0x6
9327 #define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT                                                              0x7
9328 #define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT                                                      0x8
9329 #define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT                                                 0x9
9330 #define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT                                            0xa
9331 #define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT                                                        0xb
9332 #define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT                                                        0xc
9333 #define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT                                                                0xd
9334 #define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT                                                         0xe
9335 #define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT                                                       0xf
9336 #define DB_DEBUG3__DISABLE_SLOCS_PER_CTXT_MATCH__SHIFT                                                        0x10
9337 #define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT                                                         0x11
9338 #define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT                                                        0x12
9339 #define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT                                                     0x13
9340 #define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT                                                         0x14
9341 #define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT                                                0x15
9342 #define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT                                                        0x16
9343 #define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT                                                  0x17
9344 #define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT                                                           0x18
9345 #define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT                                                                 0x19
9346 #define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT                                                             0x1a
9347 #define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT                                                       0x1b
9348 #define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT                                                         0x1c
9349 #define DB_DEBUG3__DELETE_CONTEXT_SUSPEND__SHIFT                                                              0x1d
9350 #define DB_DEBUG3__DISABLE_TS_WRITE_L0__SHIFT                                                                 0x1e
9351 #define DB_DEBUG3__DISABLE_MULTIDTAG_FL_PANIC_REQUIREMENT__SHIFT                                              0x1f
9352 #define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION_MASK                                                       0x00000001L
9353 #define DB_DEBUG3__DISABLE_RELOAD_CONTEXT_DRAW_DATA_MASK                                                      0x00000002L
9354 #define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK                                                                      0x00000004L
9355 #define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK                                                       0x00000008L
9356 #define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK                                                            0x00000010L
9357 #define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK                                                               0x00000020L
9358 #define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK                                                                0x00000040L
9359 #define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK                                                                0x00000080L
9360 #define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK                                                        0x00000100L
9361 #define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK                                                   0x00000200L
9362 #define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK                                              0x00000400L
9363 #define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK                                                          0x00000800L
9364 #define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK                                                          0x00001000L
9365 #define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK                                                                  0x00002000L
9366 #define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK                                                           0x00004000L
9367 #define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK                                                         0x00008000L
9368 #define DB_DEBUG3__DISABLE_SLOCS_PER_CTXT_MATCH_MASK                                                          0x00010000L
9369 #define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK                                                           0x00020000L
9370 #define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK                                                          0x00040000L
9371 #define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK                                                       0x00080000L
9372 #define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK                                                           0x00100000L
9373 #define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK                                                  0x00200000L
9374 #define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK                                                          0x00400000L
9375 #define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK                                                    0x00800000L
9376 #define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK                                                             0x01000000L
9377 #define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK                                                                   0x02000000L
9378 #define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK                                                               0x04000000L
9379 #define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK                                                         0x08000000L
9380 #define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK                                                           0x10000000L
9381 #define DB_DEBUG3__DELETE_CONTEXT_SUSPEND_MASK                                                                0x20000000L
9382 #define DB_DEBUG3__DISABLE_TS_WRITE_L0_MASK                                                                   0x40000000L
9383 #define DB_DEBUG3__DISABLE_MULTIDTAG_FL_PANIC_REQUIREMENT_MASK                                                0x80000000L
9384 //DB_DEBUG4
9385 #define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT                                                         0x0
9386 #define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT                                                   0x1
9387 #define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT                                                    0x2
9388 #define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT                                             0x3
9389 #define DB_DEBUG4__DISABLE_SEPARATE_OP_PIPE_CLK__SHIFT                                                        0x4
9390 #define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK__SHIFT                                                           0x5
9391 #define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN__SHIFT                                                                0x6
9392 #define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE__SHIFT                                                    0x7
9393 #define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS__SHIFT                                                  0x8
9394 #define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR__SHIFT                                                        0x9
9395 #define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR__SHIFT                                                        0xa
9396 #define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR__SHIFT                                                        0xb
9397 #define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT                                                       0xc
9398 #define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP__SHIFT                                                   0xd
9399 #define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION__SHIFT                                              0xe
9400 #define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE__SHIFT                                                0xf
9401 #define DB_DEBUG4__DISABLE_HIZ_TS_COLLISION_DETECT__SHIFT                                                     0x10
9402 #define DB_DEBUG4__DISABLE_LAST_OF_BURST_ON_ACCUM_ALL_EOT__SHIFT                                              0x11
9403 #define DB_DEBUG4__DISABLE_LAST_OF_BURST_ON_FLUSH_CHUNK0_ALL_DONE__SHIFT                                      0x12
9404 #define DB_DEBUG4__ENABLE_CZ_OVERFLOW_TESTMODE__SHIFT                                                         0x13
9405 #define DB_DEBUG4__DISABLE_LATEZ_NO_EXPORT_POWER_SAVING__SHIFT                                                0x14
9406 #define DB_DEBUG4__DISABLE_MCC_BURST_FIFO__SHIFT                                                              0x15
9407 #define DB_DEBUG4__DISABLE_MCC_BURST_FIFO_CONFLICT__SHIFT                                                     0x16
9408 #define DB_DEBUG4__DISABLE_WR_MEM_BURST_FLF_CONSECUTIVE_CHECK__SHIFT                                          0x17
9409 #define DB_DEBUG4__WR_MEM_BURST_CTL__SHIFT                                                                    0x18
9410 #define DB_DEBUG4__DISABLE_WR_MEM_BURST_POOLING__SHIFT                                                        0x1b
9411 #define DB_DEBUG4__DISABLE_RD_MEM_BURST__SHIFT                                                                0x1c
9412 #define DB_DEBUG4__LATE_ACK_SCOREBOARD_NEW__SHIFT                                                             0x1d
9413 #define DB_DEBUG4__LATE_ACK_SCOREBOARD_MULTIPLE_SLOT__SHIFT                                                   0x1e
9414 #define DB_DEBUG4__LATE_ACK_PSD_EOP_GFX9_METHOD__SHIFT                                                        0x1f
9415 #define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK                                                           0x00000001L
9416 #define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK                                                     0x00000002L
9417 #define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK                                                      0x00000004L
9418 #define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK                                               0x00000008L
9419 #define DB_DEBUG4__DISABLE_SEPARATE_OP_PIPE_CLK_MASK                                                          0x00000010L
9420 #define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK_MASK                                                             0x00000020L
9421 #define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN_MASK                                                                  0x00000040L
9422 #define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE_MASK                                                      0x00000080L
9423 #define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS_MASK                                                    0x00000100L
9424 #define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR_MASK                                                          0x00000200L
9425 #define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR_MASK                                                          0x00000400L
9426 #define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR_MASK                                                          0x00000800L
9427 #define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK                                                         0x00001000L
9428 #define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP_MASK                                                     0x00002000L
9429 #define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION_MASK                                                0x00004000L
9430 #define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE_MASK                                                  0x00008000L
9431 #define DB_DEBUG4__DISABLE_HIZ_TS_COLLISION_DETECT_MASK                                                       0x00010000L
9432 #define DB_DEBUG4__DISABLE_LAST_OF_BURST_ON_ACCUM_ALL_EOT_MASK                                                0x00020000L
9433 #define DB_DEBUG4__DISABLE_LAST_OF_BURST_ON_FLUSH_CHUNK0_ALL_DONE_MASK                                        0x00040000L
9434 #define DB_DEBUG4__ENABLE_CZ_OVERFLOW_TESTMODE_MASK                                                           0x00080000L
9435 #define DB_DEBUG4__DISABLE_LATEZ_NO_EXPORT_POWER_SAVING_MASK                                                  0x00100000L
9436 #define DB_DEBUG4__DISABLE_MCC_BURST_FIFO_MASK                                                                0x00200000L
9437 #define DB_DEBUG4__DISABLE_MCC_BURST_FIFO_CONFLICT_MASK                                                       0x00400000L
9438 #define DB_DEBUG4__DISABLE_WR_MEM_BURST_FLF_CONSECUTIVE_CHECK_MASK                                            0x00800000L
9439 #define DB_DEBUG4__WR_MEM_BURST_CTL_MASK                                                                      0x07000000L
9440 #define DB_DEBUG4__DISABLE_WR_MEM_BURST_POOLING_MASK                                                          0x08000000L
9441 #define DB_DEBUG4__DISABLE_RD_MEM_BURST_MASK                                                                  0x10000000L
9442 #define DB_DEBUG4__LATE_ACK_SCOREBOARD_NEW_MASK                                                               0x20000000L
9443 #define DB_DEBUG4__LATE_ACK_SCOREBOARD_MULTIPLE_SLOT_MASK                                                     0x40000000L
9444 #define DB_DEBUG4__LATE_ACK_PSD_EOP_GFX9_METHOD_MASK                                                          0x80000000L
9445 //DB_ETILE_STUTTER_CONTROL
9446 #define DB_ETILE_STUTTER_CONTROL__THRESHOLD__SHIFT                                                            0x0
9447 #define DB_ETILE_STUTTER_CONTROL__TIMEOUT__SHIFT                                                              0x10
9448 #define DB_ETILE_STUTTER_CONTROL__THRESHOLD_MASK                                                              0x000000FFL
9449 #define DB_ETILE_STUTTER_CONTROL__TIMEOUT_MASK                                                                0x00FF0000L
9450 //DB_LTILE_STUTTER_CONTROL
9451 #define DB_LTILE_STUTTER_CONTROL__THRESHOLD__SHIFT                                                            0x0
9452 #define DB_LTILE_STUTTER_CONTROL__TIMEOUT__SHIFT                                                              0x10
9453 #define DB_LTILE_STUTTER_CONTROL__THRESHOLD_MASK                                                              0x000000FFL
9454 #define DB_LTILE_STUTTER_CONTROL__TIMEOUT_MASK                                                                0x00FF0000L
9455 //DB_EQUAD_STUTTER_CONTROL
9456 #define DB_EQUAD_STUTTER_CONTROL__THRESHOLD__SHIFT                                                            0x0
9457 #define DB_EQUAD_STUTTER_CONTROL__TIMEOUT__SHIFT                                                              0x10
9458 #define DB_EQUAD_STUTTER_CONTROL__THRESHOLD_MASK                                                              0x000000FFL
9459 #define DB_EQUAD_STUTTER_CONTROL__TIMEOUT_MASK                                                                0x00FF0000L
9460 //DB_LQUAD_STUTTER_CONTROL
9461 #define DB_LQUAD_STUTTER_CONTROL__THRESHOLD__SHIFT                                                            0x0
9462 #define DB_LQUAD_STUTTER_CONTROL__TIMEOUT__SHIFT                                                              0x10
9463 #define DB_LQUAD_STUTTER_CONTROL__THRESHOLD_MASK                                                              0x000000FFL
9464 #define DB_LQUAD_STUTTER_CONTROL__TIMEOUT_MASK                                                                0x00FF0000L
9465 //DB_CREDIT_LIMIT
9466 #define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT                                                            0x0
9467 #define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT                                                            0x5
9468 #define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT                                                           0xa
9469 #define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT                                                            0x18
9470 #define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK                                                              0x0000001FL
9471 #define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK                                                              0x000003E0L
9472 #define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK                                                             0x00001C00L
9473 #define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK                                                              0x7F000000L
9474 //DB_WATERMARKS
9475 #define DB_WATERMARKS__DEPTH_FREE__SHIFT                                                                      0x0
9476 #define DB_WATERMARKS__DEPTH_FLUSH__SHIFT                                                                     0x8
9477 #define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT                                                              0x10
9478 #define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT                                                            0x18
9479 #define DB_WATERMARKS__DEPTH_FREE_MASK                                                                        0x000000FFL
9480 #define DB_WATERMARKS__DEPTH_FLUSH_MASK                                                                       0x0000FF00L
9481 #define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK                                                                0x00FF0000L
9482 #define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK                                                              0xFF000000L
9483 //DB_SUBTILE_CONTROL
9484 #define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT                                                                    0x0
9485 #define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT                                                                    0x2
9486 #define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT                                                                    0x4
9487 #define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT                                                                    0x6
9488 #define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT                                                                    0x8
9489 #define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT                                                                    0xa
9490 #define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT                                                                    0xc
9491 #define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT                                                                    0xe
9492 #define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT                                                                   0x10
9493 #define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT                                                                   0x12
9494 #define DB_SUBTILE_CONTROL__MSAA1_X_MASK                                                                      0x00000003L
9495 #define DB_SUBTILE_CONTROL__MSAA1_Y_MASK                                                                      0x0000000CL
9496 #define DB_SUBTILE_CONTROL__MSAA2_X_MASK                                                                      0x00000030L
9497 #define DB_SUBTILE_CONTROL__MSAA2_Y_MASK                                                                      0x000000C0L
9498 #define DB_SUBTILE_CONTROL__MSAA4_X_MASK                                                                      0x00000300L
9499 #define DB_SUBTILE_CONTROL__MSAA4_Y_MASK                                                                      0x00000C00L
9500 #define DB_SUBTILE_CONTROL__MSAA8_X_MASK                                                                      0x00003000L
9501 #define DB_SUBTILE_CONTROL__MSAA8_Y_MASK                                                                      0x0000C000L
9502 #define DB_SUBTILE_CONTROL__MSAA16_X_MASK                                                                     0x00030000L
9503 #define DB_SUBTILE_CONTROL__MSAA16_Y_MASK                                                                     0x000C0000L
9504 //DB_FREE_CACHELINES
9505 #define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT                                                           0x0
9506 #define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT                                                           0x8
9507 #define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT                                                               0x10
9508 #define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT                                                           0x18
9509 #define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK                                                             0x000000FFL
9510 #define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK                                                             0x0000FF00L
9511 #define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK                                                                 0x00FF0000L
9512 #define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK                                                             0xFF000000L
9513 //DB_FIFO_DEPTH1
9514 #define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT                                                            0x0
9515 #define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT                                                            0x8
9516 #define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT                                                                      0x10
9517 #define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT                                                                       0x18
9518 #define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK                                                              0x000000FFL
9519 #define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK                                                              0x0000FF00L
9520 #define DB_FIFO_DEPTH1__MCC_DEPTH_MASK                                                                        0x00FF0000L
9521 #define DB_FIFO_DEPTH1__QC_DEPTH_MASK                                                                         0xFF000000L
9522 //DB_FIFO_DEPTH2
9523 #define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT                                                               0x0
9524 #define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT                                                            0x8
9525 #define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT                                                               0x10
9526 #define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT                                                            0x19
9527 #define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK                                                                 0x000000FFL
9528 #define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK                                                              0x0000FF00L
9529 #define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK                                                                 0x01FF0000L
9530 #define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK                                                              0xFE000000L
9531 //DB_LAST_OF_BURST_CONFIG
9532 #define DB_LAST_OF_BURST_CONFIG__MAXBURST__SHIFT                                                              0x0
9533 #define DB_LAST_OF_BURST_CONFIG__TIMEOUT__SHIFT                                                               0x8
9534 #define DB_LAST_OF_BURST_CONFIG__DBCB_LOB_SWITCH_TIMEOUT__SHIFT                                               0xb
9535 #define DB_LAST_OF_BURST_CONFIG__ENABLE_FG_DEFAULT_TIMEOUT__SHIFT                                             0x12
9536 #define DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_COUNT_RESET_ON_LOB__SHIFT                                  0x13
9537 #define DB_LAST_OF_BURST_CONFIG__DISABLE_FLQ_LOB_EVERY_256B__SHIFT                                            0x14
9538 #define DB_LAST_OF_BURST_CONFIG__DISABLE_ZCACHE_FL_OP_EVEN_ARB__SHIFT                                         0x15
9539 #define DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_FORCE_FLUSH_BEFORE_FIFO__SHIFT                             0x16
9540 #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_DKG_LOB_GEN__SHIFT                                            0x17
9541 #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_LPF_LOB_GEN__SHIFT                                            0x18
9542 #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_CB_LOB_GEN__SHIFT                                             0x19
9543 #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FL_BURST__SHIFT                                               0x1a
9544 #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FG_LOB_FWDR__SHIFT                                            0x1b
9545 #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_RD_BA_ACCUM__SHIFT                                            0x1c
9546 #define DB_LAST_OF_BURST_CONFIG__BYPASS_SORT_RD_BA__SHIFT                                                     0x1d
9547 #define DB_LAST_OF_BURST_CONFIG__DISABLE_RD_BURST__SHIFT                                                      0x1e
9548 #define DB_LAST_OF_BURST_CONFIG__LEGACY_LOB_INSERT_EN__SHIFT                                                  0x1f
9549 #define DB_LAST_OF_BURST_CONFIG__MAXBURST_MASK                                                                0x000000FFL
9550 #define DB_LAST_OF_BURST_CONFIG__TIMEOUT_MASK                                                                 0x00000700L
9551 #define DB_LAST_OF_BURST_CONFIG__DBCB_LOB_SWITCH_TIMEOUT_MASK                                                 0x0003F800L
9552 #define DB_LAST_OF_BURST_CONFIG__ENABLE_FG_DEFAULT_TIMEOUT_MASK                                               0x00040000L
9553 #define DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_COUNT_RESET_ON_LOB_MASK                                    0x00080000L
9554 #define DB_LAST_OF_BURST_CONFIG__DISABLE_FLQ_LOB_EVERY_256B_MASK                                              0x00100000L
9555 #define DB_LAST_OF_BURST_CONFIG__DISABLE_ZCACHE_FL_OP_EVEN_ARB_MASK                                           0x00200000L
9556 #define DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_FORCE_FLUSH_BEFORE_FIFO_MASK                               0x00400000L
9557 #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_DKG_LOB_GEN_MASK                                              0x00800000L
9558 #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_LPF_LOB_GEN_MASK                                              0x01000000L
9559 #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_CB_LOB_GEN_MASK                                               0x02000000L
9560 #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FL_BURST_MASK                                                 0x04000000L
9561 #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FG_LOB_FWDR_MASK                                              0x08000000L
9562 #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_RD_BA_ACCUM_MASK                                              0x10000000L
9563 #define DB_LAST_OF_BURST_CONFIG__BYPASS_SORT_RD_BA_MASK                                                       0x20000000L
9564 #define DB_LAST_OF_BURST_CONFIG__DISABLE_RD_BURST_MASK                                                        0x40000000L
9565 #define DB_LAST_OF_BURST_CONFIG__LEGACY_LOB_INSERT_EN_MASK                                                    0x80000000L
9566 //DB_RING_CONTROL
9567 #define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT                                                               0x0
9568 #define DB_RING_CONTROL__COUNTER_CONTROL_MASK                                                                 0x00000003L
9569 //DB_MEM_ARB_WATERMARKS
9570 #define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK__SHIFT                                                       0x0
9571 #define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK__SHIFT                                                       0x8
9572 #define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK__SHIFT                                                       0x10
9573 #define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK__SHIFT                                                       0x18
9574 #define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK_MASK                                                         0x00000007L
9575 #define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK_MASK                                                         0x00000700L
9576 #define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK_MASK                                                         0x00070000L
9577 #define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK_MASK                                                         0x07000000L
9578 //DB_FIFO_DEPTH3
9579 #define DB_FIFO_DEPTH3__LTILE_PROBE_FIFO_DEPTH__SHIFT                                                         0x0
9580 #define DB_FIFO_DEPTH3__QUAD_READ_REQS__SHIFT                                                                 0x18
9581 #define DB_FIFO_DEPTH3__LTILE_PROBE_FIFO_DEPTH_MASK                                                           0x000000FFL
9582 #define DB_FIFO_DEPTH3__QUAD_READ_REQS_MASK                                                                   0xFF000000L
9583 //DB_RMI_BC_GL2_CACHE_CONTROL
9584 #define DB_RMI_BC_GL2_CACHE_CONTROL__Z_WR_POLICY__SHIFT                                                       0x0
9585 #define DB_RMI_BC_GL2_CACHE_CONTROL__S_WR_POLICY__SHIFT                                                       0x2
9586 #define DB_RMI_BC_GL2_CACHE_CONTROL__HTILE_WR_POLICY__SHIFT                                                   0x4
9587 #define DB_RMI_BC_GL2_CACHE_CONTROL__ZPCPSD_WR_POLICY__SHIFT                                                  0x6
9588 #define DB_RMI_BC_GL2_CACHE_CONTROL__Z_RD_POLICY__SHIFT                                                       0x10
9589 #define DB_RMI_BC_GL2_CACHE_CONTROL__S_RD_POLICY__SHIFT                                                       0x12
9590 #define DB_RMI_BC_GL2_CACHE_CONTROL__HTILE_RD_POLICY__SHIFT                                                   0x14
9591 #define DB_RMI_BC_GL2_CACHE_CONTROL__VOL__SHIFT                                                               0x1f
9592 #define DB_RMI_BC_GL2_CACHE_CONTROL__Z_WR_POLICY_MASK                                                         0x00000003L
9593 #define DB_RMI_BC_GL2_CACHE_CONTROL__S_WR_POLICY_MASK                                                         0x0000000CL
9594 #define DB_RMI_BC_GL2_CACHE_CONTROL__HTILE_WR_POLICY_MASK                                                     0x00000030L
9595 #define DB_RMI_BC_GL2_CACHE_CONTROL__ZPCPSD_WR_POLICY_MASK                                                    0x000000C0L
9596 #define DB_RMI_BC_GL2_CACHE_CONTROL__Z_RD_POLICY_MASK                                                         0x00030000L
9597 #define DB_RMI_BC_GL2_CACHE_CONTROL__S_RD_POLICY_MASK                                                         0x000C0000L
9598 #define DB_RMI_BC_GL2_CACHE_CONTROL__HTILE_RD_POLICY_MASK                                                     0x00300000L
9599 #define DB_RMI_BC_GL2_CACHE_CONTROL__VOL_MASK                                                                 0x80000000L
9600 //DB_EXCEPTION_CONTROL
9601 #define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE__SHIFT                                                    0x0
9602 #define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE__SHIFT                                                     0x1
9603 #define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE__SHIFT                                                       0x2
9604 #define DB_EXCEPTION_CONTROL__AUTO_FLUSH_HTILE__SHIFT                                                         0x3
9605 #define DB_EXCEPTION_CONTROL__AUTO_FLUSH_QUAD__SHIFT                                                          0x4
9606 #define DB_EXCEPTION_CONTROL__EXTRA_BITS_GROUP_A__SHIFT                                                       0x5
9607 #define DB_EXCEPTION_CONTROL__FORCE_SUMMARIZE__SHIFT                                                          0x8
9608 #define DB_EXCEPTION_CONTROL__EXTRA_BITS_GROUP_B__SHIFT                                                       0xc
9609 #define DB_EXCEPTION_CONTROL__DTAG_WATERMARK__SHIFT                                                           0x18
9610 #define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE_MASK                                                      0x00000001L
9611 #define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE_MASK                                                       0x00000002L
9612 #define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE_MASK                                                         0x00000004L
9613 #define DB_EXCEPTION_CONTROL__AUTO_FLUSH_HTILE_MASK                                                           0x00000008L
9614 #define DB_EXCEPTION_CONTROL__AUTO_FLUSH_QUAD_MASK                                                            0x00000010L
9615 #define DB_EXCEPTION_CONTROL__EXTRA_BITS_GROUP_A_MASK                                                         0x000000E0L
9616 #define DB_EXCEPTION_CONTROL__FORCE_SUMMARIZE_MASK                                                            0x00000F00L
9617 #define DB_EXCEPTION_CONTROL__EXTRA_BITS_GROUP_B_MASK                                                         0x00FFF000L
9618 #define DB_EXCEPTION_CONTROL__DTAG_WATERMARK_MASK                                                             0x7F000000L
9619 //DB_DFSM_CONFIG
9620 #define DB_DFSM_CONFIG__BYPASS_DFSM__SHIFT                                                                    0x0
9621 #define DB_DFSM_CONFIG__DISABLE_PUNCHOUT__SHIFT                                                               0x1
9622 #define DB_DFSM_CONFIG__DISABLE_POPS__SHIFT                                                                   0x2
9623 #define DB_DFSM_CONFIG__FORCE_FLUSH__SHIFT                                                                    0x3
9624 #define DB_DFSM_CONFIG__SQUAD_WATERMARK__SHIFT                                                                0x4
9625 #define DB_DFSM_CONFIG__CAM_WATERMARK__SHIFT                                                                  0x10
9626 #define DB_DFSM_CONFIG__OUTPUT_WATCHDOG__SHIFT                                                                0x18
9627 #define DB_DFSM_CONFIG__BYPASS_DFSM_MASK                                                                      0x00000001L
9628 #define DB_DFSM_CONFIG__DISABLE_PUNCHOUT_MASK                                                                 0x00000002L
9629 #define DB_DFSM_CONFIG__DISABLE_POPS_MASK                                                                     0x00000004L
9630 #define DB_DFSM_CONFIG__FORCE_FLUSH_MASK                                                                      0x00000008L
9631 #define DB_DFSM_CONFIG__SQUAD_WATERMARK_MASK                                                                  0x00003FF0L
9632 #define DB_DFSM_CONFIG__CAM_WATERMARK_MASK                                                                    0x00FF0000L
9633 #define DB_DFSM_CONFIG__OUTPUT_WATCHDOG_MASK                                                                  0xFF000000L
9634 //DB_DFSM_TILES_IN_FLIGHT
9635 #define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK__SHIFT                                                        0x0
9636 #define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK_MASK                                                          0x0000FFFFL
9637 //DB_DFSM_PRIMS_IN_FLIGHT
9638 #define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK__SHIFT                                                        0x0
9639 #define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK_MASK                                                          0x0000FFFFL
9640 //DB_DFSM_WATCHDOG
9641 #define DB_DFSM_WATCHDOG__TIMER_TARGET__SHIFT                                                                 0x0
9642 #define DB_DFSM_WATCHDOG__TIMER_TARGET_MASK                                                                   0xFFFFFFFFL
9643 //DB_DFSM_FLUSH_ENABLE
9644 #define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS__SHIFT                                                           0x0
9645 #define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU__SHIFT                                                       0x18
9646 #define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS__SHIFT                                                               0x1c
9647 #define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS_MASK                                                             0x000007FFL
9648 #define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU_MASK                                                         0x0F000000L
9649 #define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS_MASK                                                                 0xF0000000L
9650 //DB_DFSM_FLUSH_AUX_EVENT
9651 #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A__SHIFT                                                               0x0
9652 #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B__SHIFT                                                               0x8
9653 #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C__SHIFT                                                               0x10
9654 #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D__SHIFT                                                               0x18
9655 #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A_MASK                                                                 0x000000FFL
9656 #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B_MASK                                                                 0x0000FF00L
9657 #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C_MASK                                                                 0x00FF0000L
9658 #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D_MASK                                                                 0xFF000000L
9659 //DB_FGCG_SRAMS_CLK_CTRL
9660 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE0__SHIFT                                                              0x0
9661 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE1__SHIFT                                                              0x1
9662 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE2__SHIFT                                                              0x2
9663 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE3__SHIFT                                                              0x3
9664 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE4__SHIFT                                                              0x4
9665 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE5__SHIFT                                                              0x5
9666 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE6__SHIFT                                                              0x6
9667 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE7__SHIFT                                                              0x7
9668 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE8__SHIFT                                                              0x8
9669 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE9__SHIFT                                                              0x9
9670 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE10__SHIFT                                                             0xa
9671 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE11__SHIFT                                                             0xb
9672 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE12__SHIFT                                                             0xc
9673 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE13__SHIFT                                                             0xd
9674 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE14__SHIFT                                                             0xe
9675 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE15__SHIFT                                                             0xf
9676 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE16__SHIFT                                                             0x10
9677 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE17__SHIFT                                                             0x11
9678 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE18__SHIFT                                                             0x12
9679 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE19__SHIFT                                                             0x13
9680 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE20__SHIFT                                                             0x14
9681 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE21__SHIFT                                                             0x15
9682 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE22__SHIFT                                                             0x16
9683 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE23__SHIFT                                                             0x17
9684 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE24__SHIFT                                                             0x18
9685 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE25__SHIFT                                                             0x19
9686 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE26__SHIFT                                                             0x1a
9687 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE0_MASK                                                                0x00000001L
9688 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE1_MASK                                                                0x00000002L
9689 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE2_MASK                                                                0x00000004L
9690 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE3_MASK                                                                0x00000008L
9691 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE4_MASK                                                                0x00000010L
9692 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE5_MASK                                                                0x00000020L
9693 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE6_MASK                                                                0x00000040L
9694 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE7_MASK                                                                0x00000080L
9695 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE8_MASK                                                                0x00000100L
9696 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE9_MASK                                                                0x00000200L
9697 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE10_MASK                                                               0x00000400L
9698 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE11_MASK                                                               0x00000800L
9699 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE12_MASK                                                               0x00001000L
9700 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE13_MASK                                                               0x00002000L
9701 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE14_MASK                                                               0x00004000L
9702 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE15_MASK                                                               0x00008000L
9703 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE16_MASK                                                               0x00010000L
9704 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE17_MASK                                                               0x00020000L
9705 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE18_MASK                                                               0x00040000L
9706 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE19_MASK                                                               0x00080000L
9707 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE20_MASK                                                               0x00100000L
9708 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE21_MASK                                                               0x00200000L
9709 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE22_MASK                                                               0x00400000L
9710 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE23_MASK                                                               0x00800000L
9711 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE24_MASK                                                               0x01000000L
9712 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE25_MASK                                                               0x02000000L
9713 #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE26_MASK                                                               0x04000000L
9714 //DB_FGCG_INTERFACES_CLK_CTRL
9715 #define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_QUAD_OVERRIDE__SHIFT                                               0x0
9716 #define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_TILE_OVERRIDE__SHIFT                                               0x1
9717 #define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_LQUAD_OVERRIDE__SHIFT                                              0x2
9718 #define DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_RDREQ_OVERRIDE__SHIFT                                             0x3
9719 #define DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_WRREQ_OVERRIDE__SHIFT                                             0x4
9720 #define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_TILE_OVERRIDE__SHIFT                                               0x5
9721 #define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_RMIRET_OVERRIDE__SHIFT                                             0x6
9722 #define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_QUAD_OVERRIDE_MASK                                                 0x00000001L
9723 #define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_TILE_OVERRIDE_MASK                                                 0x00000002L
9724 #define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_LQUAD_OVERRIDE_MASK                                                0x00000004L
9725 #define DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_RDREQ_OVERRIDE_MASK                                               0x00000008L
9726 #define DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_WRREQ_OVERRIDE_MASK                                               0x00000010L
9727 #define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_TILE_OVERRIDE_MASK                                                 0x00000020L
9728 #define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_RMIRET_OVERRIDE_MASK                                               0x00000040L
9729 //CC_RB_REDUNDANCY
9730 #define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT                                                                   0x8
9731 #define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT                                                               0xc
9732 #define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT                                                                   0x10
9733 #define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT                                                               0x14
9734 #define CC_RB_REDUNDANCY__FAILED_RB0_MASK                                                                     0x00000F00L
9735 #define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK                                                                 0x00001000L
9736 #define CC_RB_REDUNDANCY__FAILED_RB1_MASK                                                                     0x000F0000L
9737 #define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK                                                                 0x00100000L
9738 //CC_RB_BACKEND_DISABLE
9739 #define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT                                                         0x10
9740 #define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK                                                           0x00FF0000L
9741 //GB_ADDR_CONFIG
9742 #define GB_ADDR_CONFIG__NUM_PIPES__SHIFT                                                                      0x0
9743 #define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                           0x3
9744 #define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                           0x6
9745 #define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT                                                             0x13
9746 #define GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT                                                                  0x1a
9747 #define GB_ADDR_CONFIG__NUM_PIPES_MASK                                                                        0x00000007L
9748 #define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                             0x00000038L
9749 #define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                             0x000000C0L
9750 #define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK                                                               0x00180000L
9751 #define GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK                                                                    0x0C000000L
9752 //GB_BACKEND_MAP
9753 #define GB_BACKEND_MAP__BACKEND_MAP__SHIFT                                                                    0x0
9754 #define GB_BACKEND_MAP__BACKEND_MAP_MASK                                                                      0xFFFFFFFFL
9755 //GB_GPU_ID
9756 #define GB_GPU_ID__GPU_ID__SHIFT                                                                              0x0
9757 #define GB_GPU_ID__GPU_ID_MASK                                                                                0x0000000FL
9758 //CC_RB_DAISY_CHAIN
9759 #define CC_RB_DAISY_CHAIN__RB_0__SHIFT                                                                        0x0
9760 #define CC_RB_DAISY_CHAIN__RB_1__SHIFT                                                                        0x4
9761 #define CC_RB_DAISY_CHAIN__RB_2__SHIFT                                                                        0x8
9762 #define CC_RB_DAISY_CHAIN__RB_3__SHIFT                                                                        0xc
9763 #define CC_RB_DAISY_CHAIN__RB_4__SHIFT                                                                        0x10
9764 #define CC_RB_DAISY_CHAIN__RB_5__SHIFT                                                                        0x14
9765 #define CC_RB_DAISY_CHAIN__RB_6__SHIFT                                                                        0x18
9766 #define CC_RB_DAISY_CHAIN__RB_7__SHIFT                                                                        0x1c
9767 #define CC_RB_DAISY_CHAIN__RB_0_MASK                                                                          0x0000000FL
9768 #define CC_RB_DAISY_CHAIN__RB_1_MASK                                                                          0x000000F0L
9769 #define CC_RB_DAISY_CHAIN__RB_2_MASK                                                                          0x00000F00L
9770 #define CC_RB_DAISY_CHAIN__RB_3_MASK                                                                          0x0000F000L
9771 #define CC_RB_DAISY_CHAIN__RB_4_MASK                                                                          0x000F0000L
9772 #define CC_RB_DAISY_CHAIN__RB_5_MASK                                                                          0x00F00000L
9773 #define CC_RB_DAISY_CHAIN__RB_6_MASK                                                                          0x0F000000L
9774 #define CC_RB_DAISY_CHAIN__RB_7_MASK                                                                          0xF0000000L
9775 //GB_ADDR_CONFIG_READ
9776 #define GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT                                                                 0x0
9777 #define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT                                                      0x3
9778 #define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT                                                      0x6
9779 #define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT                                                        0x13
9780 #define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT                                                             0x1a
9781 #define GB_ADDR_CONFIG_READ__NUM_PIPES_MASK                                                                   0x00000007L
9782 #define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK                                                        0x00000038L
9783 #define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK                                                        0x000000C0L
9784 #define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK                                                          0x00180000L
9785 #define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK                                                               0x0C000000L
9786 //GB_TILE_MODE0
9787 #define GB_TILE_MODE0__ARRAY_MODE__SHIFT                                                                      0x2
9788 #define GB_TILE_MODE0__PIPE_CONFIG__SHIFT                                                                     0x6
9789 #define GB_TILE_MODE0__TILE_SPLIT__SHIFT                                                                      0xb
9790 #define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
9791 #define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT                                                                    0x19
9792 #define GB_TILE_MODE0__ARRAY_MODE_MASK                                                                        0x0000003CL
9793 #define GB_TILE_MODE0__PIPE_CONFIG_MASK                                                                       0x000007C0L
9794 #define GB_TILE_MODE0__TILE_SPLIT_MASK                                                                        0x00003800L
9795 #define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
9796 #define GB_TILE_MODE0__SAMPLE_SPLIT_MASK                                                                      0x06000000L
9797 //GB_TILE_MODE1
9798 #define GB_TILE_MODE1__ARRAY_MODE__SHIFT                                                                      0x2
9799 #define GB_TILE_MODE1__PIPE_CONFIG__SHIFT                                                                     0x6
9800 #define GB_TILE_MODE1__TILE_SPLIT__SHIFT                                                                      0xb
9801 #define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
9802 #define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT                                                                    0x19
9803 #define GB_TILE_MODE1__ARRAY_MODE_MASK                                                                        0x0000003CL
9804 #define GB_TILE_MODE1__PIPE_CONFIG_MASK                                                                       0x000007C0L
9805 #define GB_TILE_MODE1__TILE_SPLIT_MASK                                                                        0x00003800L
9806 #define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
9807 #define GB_TILE_MODE1__SAMPLE_SPLIT_MASK                                                                      0x06000000L
9808 //GB_TILE_MODE2
9809 #define GB_TILE_MODE2__ARRAY_MODE__SHIFT                                                                      0x2
9810 #define GB_TILE_MODE2__PIPE_CONFIG__SHIFT                                                                     0x6
9811 #define GB_TILE_MODE2__TILE_SPLIT__SHIFT                                                                      0xb
9812 #define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
9813 #define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT                                                                    0x19
9814 #define GB_TILE_MODE2__ARRAY_MODE_MASK                                                                        0x0000003CL
9815 #define GB_TILE_MODE2__PIPE_CONFIG_MASK                                                                       0x000007C0L
9816 #define GB_TILE_MODE2__TILE_SPLIT_MASK                                                                        0x00003800L
9817 #define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
9818 #define GB_TILE_MODE2__SAMPLE_SPLIT_MASK                                                                      0x06000000L
9819 //GB_TILE_MODE3
9820 #define GB_TILE_MODE3__ARRAY_MODE__SHIFT                                                                      0x2
9821 #define GB_TILE_MODE3__PIPE_CONFIG__SHIFT                                                                     0x6
9822 #define GB_TILE_MODE3__TILE_SPLIT__SHIFT                                                                      0xb
9823 #define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
9824 #define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT                                                                    0x19
9825 #define GB_TILE_MODE3__ARRAY_MODE_MASK                                                                        0x0000003CL
9826 #define GB_TILE_MODE3__PIPE_CONFIG_MASK                                                                       0x000007C0L
9827 #define GB_TILE_MODE3__TILE_SPLIT_MASK                                                                        0x00003800L
9828 #define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
9829 #define GB_TILE_MODE3__SAMPLE_SPLIT_MASK                                                                      0x06000000L
9830 //GB_TILE_MODE4
9831 #define GB_TILE_MODE4__ARRAY_MODE__SHIFT                                                                      0x2
9832 #define GB_TILE_MODE4__PIPE_CONFIG__SHIFT                                                                     0x6
9833 #define GB_TILE_MODE4__TILE_SPLIT__SHIFT                                                                      0xb
9834 #define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
9835 #define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT                                                                    0x19
9836 #define GB_TILE_MODE4__ARRAY_MODE_MASK                                                                        0x0000003CL
9837 #define GB_TILE_MODE4__PIPE_CONFIG_MASK                                                                       0x000007C0L
9838 #define GB_TILE_MODE4__TILE_SPLIT_MASK                                                                        0x00003800L
9839 #define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
9840 #define GB_TILE_MODE4__SAMPLE_SPLIT_MASK                                                                      0x06000000L
9841 //GB_TILE_MODE5
9842 #define GB_TILE_MODE5__ARRAY_MODE__SHIFT                                                                      0x2
9843 #define GB_TILE_MODE5__PIPE_CONFIG__SHIFT                                                                     0x6
9844 #define GB_TILE_MODE5__TILE_SPLIT__SHIFT                                                                      0xb
9845 #define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
9846 #define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT                                                                    0x19
9847 #define GB_TILE_MODE5__ARRAY_MODE_MASK                                                                        0x0000003CL
9848 #define GB_TILE_MODE5__PIPE_CONFIG_MASK                                                                       0x000007C0L
9849 #define GB_TILE_MODE5__TILE_SPLIT_MASK                                                                        0x00003800L
9850 #define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
9851 #define GB_TILE_MODE5__SAMPLE_SPLIT_MASK                                                                      0x06000000L
9852 //GB_TILE_MODE6
9853 #define GB_TILE_MODE6__ARRAY_MODE__SHIFT                                                                      0x2
9854 #define GB_TILE_MODE6__PIPE_CONFIG__SHIFT                                                                     0x6
9855 #define GB_TILE_MODE6__TILE_SPLIT__SHIFT                                                                      0xb
9856 #define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
9857 #define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT                                                                    0x19
9858 #define GB_TILE_MODE6__ARRAY_MODE_MASK                                                                        0x0000003CL
9859 #define GB_TILE_MODE6__PIPE_CONFIG_MASK                                                                       0x000007C0L
9860 #define GB_TILE_MODE6__TILE_SPLIT_MASK                                                                        0x00003800L
9861 #define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
9862 #define GB_TILE_MODE6__SAMPLE_SPLIT_MASK                                                                      0x06000000L
9863 //GB_TILE_MODE7
9864 #define GB_TILE_MODE7__ARRAY_MODE__SHIFT                                                                      0x2
9865 #define GB_TILE_MODE7__PIPE_CONFIG__SHIFT                                                                     0x6
9866 #define GB_TILE_MODE7__TILE_SPLIT__SHIFT                                                                      0xb
9867 #define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
9868 #define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT                                                                    0x19
9869 #define GB_TILE_MODE7__ARRAY_MODE_MASK                                                                        0x0000003CL
9870 #define GB_TILE_MODE7__PIPE_CONFIG_MASK                                                                       0x000007C0L
9871 #define GB_TILE_MODE7__TILE_SPLIT_MASK                                                                        0x00003800L
9872 #define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
9873 #define GB_TILE_MODE7__SAMPLE_SPLIT_MASK                                                                      0x06000000L
9874 //GB_TILE_MODE8
9875 #define GB_TILE_MODE8__ARRAY_MODE__SHIFT                                                                      0x2
9876 #define GB_TILE_MODE8__PIPE_CONFIG__SHIFT                                                                     0x6
9877 #define GB_TILE_MODE8__TILE_SPLIT__SHIFT                                                                      0xb
9878 #define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
9879 #define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT                                                                    0x19
9880 #define GB_TILE_MODE8__ARRAY_MODE_MASK                                                                        0x0000003CL
9881 #define GB_TILE_MODE8__PIPE_CONFIG_MASK                                                                       0x000007C0L
9882 #define GB_TILE_MODE8__TILE_SPLIT_MASK                                                                        0x00003800L
9883 #define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
9884 #define GB_TILE_MODE8__SAMPLE_SPLIT_MASK                                                                      0x06000000L
9885 //GB_TILE_MODE9
9886 #define GB_TILE_MODE9__ARRAY_MODE__SHIFT                                                                      0x2
9887 #define GB_TILE_MODE9__PIPE_CONFIG__SHIFT                                                                     0x6
9888 #define GB_TILE_MODE9__TILE_SPLIT__SHIFT                                                                      0xb
9889 #define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
9890 #define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT                                                                    0x19
9891 #define GB_TILE_MODE9__ARRAY_MODE_MASK                                                                        0x0000003CL
9892 #define GB_TILE_MODE9__PIPE_CONFIG_MASK                                                                       0x000007C0L
9893 #define GB_TILE_MODE9__TILE_SPLIT_MASK                                                                        0x00003800L
9894 #define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
9895 #define GB_TILE_MODE9__SAMPLE_SPLIT_MASK                                                                      0x06000000L
9896 //GB_TILE_MODE10
9897 #define GB_TILE_MODE10__ARRAY_MODE__SHIFT                                                                     0x2
9898 #define GB_TILE_MODE10__PIPE_CONFIG__SHIFT                                                                    0x6
9899 #define GB_TILE_MODE10__TILE_SPLIT__SHIFT                                                                     0xb
9900 #define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
9901 #define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT                                                                   0x19
9902 #define GB_TILE_MODE10__ARRAY_MODE_MASK                                                                       0x0000003CL
9903 #define GB_TILE_MODE10__PIPE_CONFIG_MASK                                                                      0x000007C0L
9904 #define GB_TILE_MODE10__TILE_SPLIT_MASK                                                                       0x00003800L
9905 #define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
9906 #define GB_TILE_MODE10__SAMPLE_SPLIT_MASK                                                                     0x06000000L
9907 //GB_TILE_MODE11
9908 #define GB_TILE_MODE11__ARRAY_MODE__SHIFT                                                                     0x2
9909 #define GB_TILE_MODE11__PIPE_CONFIG__SHIFT                                                                    0x6
9910 #define GB_TILE_MODE11__TILE_SPLIT__SHIFT                                                                     0xb
9911 #define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
9912 #define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT                                                                   0x19
9913 #define GB_TILE_MODE11__ARRAY_MODE_MASK                                                                       0x0000003CL
9914 #define GB_TILE_MODE11__PIPE_CONFIG_MASK                                                                      0x000007C0L
9915 #define GB_TILE_MODE11__TILE_SPLIT_MASK                                                                       0x00003800L
9916 #define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
9917 #define GB_TILE_MODE11__SAMPLE_SPLIT_MASK                                                                     0x06000000L
9918 //GB_TILE_MODE12
9919 #define GB_TILE_MODE12__ARRAY_MODE__SHIFT                                                                     0x2
9920 #define GB_TILE_MODE12__PIPE_CONFIG__SHIFT                                                                    0x6
9921 #define GB_TILE_MODE12__TILE_SPLIT__SHIFT                                                                     0xb
9922 #define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
9923 #define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT                                                                   0x19
9924 #define GB_TILE_MODE12__ARRAY_MODE_MASK                                                                       0x0000003CL
9925 #define GB_TILE_MODE12__PIPE_CONFIG_MASK                                                                      0x000007C0L
9926 #define GB_TILE_MODE12__TILE_SPLIT_MASK                                                                       0x00003800L
9927 #define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
9928 #define GB_TILE_MODE12__SAMPLE_SPLIT_MASK                                                                     0x06000000L
9929 //GB_TILE_MODE13
9930 #define GB_TILE_MODE13__ARRAY_MODE__SHIFT                                                                     0x2
9931 #define GB_TILE_MODE13__PIPE_CONFIG__SHIFT                                                                    0x6
9932 #define GB_TILE_MODE13__TILE_SPLIT__SHIFT                                                                     0xb
9933 #define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
9934 #define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT                                                                   0x19
9935 #define GB_TILE_MODE13__ARRAY_MODE_MASK                                                                       0x0000003CL
9936 #define GB_TILE_MODE13__PIPE_CONFIG_MASK                                                                      0x000007C0L
9937 #define GB_TILE_MODE13__TILE_SPLIT_MASK                                                                       0x00003800L
9938 #define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
9939 #define GB_TILE_MODE13__SAMPLE_SPLIT_MASK                                                                     0x06000000L
9940 //GB_TILE_MODE14
9941 #define GB_TILE_MODE14__ARRAY_MODE__SHIFT                                                                     0x2
9942 #define GB_TILE_MODE14__PIPE_CONFIG__SHIFT                                                                    0x6
9943 #define GB_TILE_MODE14__TILE_SPLIT__SHIFT                                                                     0xb
9944 #define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
9945 #define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT                                                                   0x19
9946 #define GB_TILE_MODE14__ARRAY_MODE_MASK                                                                       0x0000003CL
9947 #define GB_TILE_MODE14__PIPE_CONFIG_MASK                                                                      0x000007C0L
9948 #define GB_TILE_MODE14__TILE_SPLIT_MASK                                                                       0x00003800L
9949 #define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
9950 #define GB_TILE_MODE14__SAMPLE_SPLIT_MASK                                                                     0x06000000L
9951 //GB_TILE_MODE15
9952 #define GB_TILE_MODE15__ARRAY_MODE__SHIFT                                                                     0x2
9953 #define GB_TILE_MODE15__PIPE_CONFIG__SHIFT                                                                    0x6
9954 #define GB_TILE_MODE15__TILE_SPLIT__SHIFT                                                                     0xb
9955 #define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
9956 #define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT                                                                   0x19
9957 #define GB_TILE_MODE15__ARRAY_MODE_MASK                                                                       0x0000003CL
9958 #define GB_TILE_MODE15__PIPE_CONFIG_MASK                                                                      0x000007C0L
9959 #define GB_TILE_MODE15__TILE_SPLIT_MASK                                                                       0x00003800L
9960 #define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
9961 #define GB_TILE_MODE15__SAMPLE_SPLIT_MASK                                                                     0x06000000L
9962 //GB_TILE_MODE16
9963 #define GB_TILE_MODE16__ARRAY_MODE__SHIFT                                                                     0x2
9964 #define GB_TILE_MODE16__PIPE_CONFIG__SHIFT                                                                    0x6
9965 #define GB_TILE_MODE16__TILE_SPLIT__SHIFT                                                                     0xb
9966 #define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
9967 #define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT                                                                   0x19
9968 #define GB_TILE_MODE16__ARRAY_MODE_MASK                                                                       0x0000003CL
9969 #define GB_TILE_MODE16__PIPE_CONFIG_MASK                                                                      0x000007C0L
9970 #define GB_TILE_MODE16__TILE_SPLIT_MASK                                                                       0x00003800L
9971 #define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
9972 #define GB_TILE_MODE16__SAMPLE_SPLIT_MASK                                                                     0x06000000L
9973 //GB_TILE_MODE17
9974 #define GB_TILE_MODE17__ARRAY_MODE__SHIFT                                                                     0x2
9975 #define GB_TILE_MODE17__PIPE_CONFIG__SHIFT                                                                    0x6
9976 #define GB_TILE_MODE17__TILE_SPLIT__SHIFT                                                                     0xb
9977 #define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
9978 #define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT                                                                   0x19
9979 #define GB_TILE_MODE17__ARRAY_MODE_MASK                                                                       0x0000003CL
9980 #define GB_TILE_MODE17__PIPE_CONFIG_MASK                                                                      0x000007C0L
9981 #define GB_TILE_MODE17__TILE_SPLIT_MASK                                                                       0x00003800L
9982 #define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
9983 #define GB_TILE_MODE17__SAMPLE_SPLIT_MASK                                                                     0x06000000L
9984 //GB_TILE_MODE18
9985 #define GB_TILE_MODE18__ARRAY_MODE__SHIFT                                                                     0x2
9986 #define GB_TILE_MODE18__PIPE_CONFIG__SHIFT                                                                    0x6
9987 #define GB_TILE_MODE18__TILE_SPLIT__SHIFT                                                                     0xb
9988 #define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
9989 #define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT                                                                   0x19
9990 #define GB_TILE_MODE18__ARRAY_MODE_MASK                                                                       0x0000003CL
9991 #define GB_TILE_MODE18__PIPE_CONFIG_MASK                                                                      0x000007C0L
9992 #define GB_TILE_MODE18__TILE_SPLIT_MASK                                                                       0x00003800L
9993 #define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
9994 #define GB_TILE_MODE18__SAMPLE_SPLIT_MASK                                                                     0x06000000L
9995 //GB_TILE_MODE19
9996 #define GB_TILE_MODE19__ARRAY_MODE__SHIFT                                                                     0x2
9997 #define GB_TILE_MODE19__PIPE_CONFIG__SHIFT                                                                    0x6
9998 #define GB_TILE_MODE19__TILE_SPLIT__SHIFT                                                                     0xb
9999 #define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
10000 #define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT                                                                   0x19
10001 #define GB_TILE_MODE19__ARRAY_MODE_MASK                                                                       0x0000003CL
10002 #define GB_TILE_MODE19__PIPE_CONFIG_MASK                                                                      0x000007C0L
10003 #define GB_TILE_MODE19__TILE_SPLIT_MASK                                                                       0x00003800L
10004 #define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
10005 #define GB_TILE_MODE19__SAMPLE_SPLIT_MASK                                                                     0x06000000L
10006 //GB_TILE_MODE20
10007 #define GB_TILE_MODE20__ARRAY_MODE__SHIFT                                                                     0x2
10008 #define GB_TILE_MODE20__PIPE_CONFIG__SHIFT                                                                    0x6
10009 #define GB_TILE_MODE20__TILE_SPLIT__SHIFT                                                                     0xb
10010 #define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
10011 #define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT                                                                   0x19
10012 #define GB_TILE_MODE20__ARRAY_MODE_MASK                                                                       0x0000003CL
10013 #define GB_TILE_MODE20__PIPE_CONFIG_MASK                                                                      0x000007C0L
10014 #define GB_TILE_MODE20__TILE_SPLIT_MASK                                                                       0x00003800L
10015 #define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
10016 #define GB_TILE_MODE20__SAMPLE_SPLIT_MASK                                                                     0x06000000L
10017 //GB_TILE_MODE21
10018 #define GB_TILE_MODE21__ARRAY_MODE__SHIFT                                                                     0x2
10019 #define GB_TILE_MODE21__PIPE_CONFIG__SHIFT                                                                    0x6
10020 #define GB_TILE_MODE21__TILE_SPLIT__SHIFT                                                                     0xb
10021 #define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
10022 #define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT                                                                   0x19
10023 #define GB_TILE_MODE21__ARRAY_MODE_MASK                                                                       0x0000003CL
10024 #define GB_TILE_MODE21__PIPE_CONFIG_MASK                                                                      0x000007C0L
10025 #define GB_TILE_MODE21__TILE_SPLIT_MASK                                                                       0x00003800L
10026 #define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
10027 #define GB_TILE_MODE21__SAMPLE_SPLIT_MASK                                                                     0x06000000L
10028 //GB_TILE_MODE22
10029 #define GB_TILE_MODE22__ARRAY_MODE__SHIFT                                                                     0x2
10030 #define GB_TILE_MODE22__PIPE_CONFIG__SHIFT                                                                    0x6
10031 #define GB_TILE_MODE22__TILE_SPLIT__SHIFT                                                                     0xb
10032 #define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
10033 #define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT                                                                   0x19
10034 #define GB_TILE_MODE22__ARRAY_MODE_MASK                                                                       0x0000003CL
10035 #define GB_TILE_MODE22__PIPE_CONFIG_MASK                                                                      0x000007C0L
10036 #define GB_TILE_MODE22__TILE_SPLIT_MASK                                                                       0x00003800L
10037 #define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
10038 #define GB_TILE_MODE22__SAMPLE_SPLIT_MASK                                                                     0x06000000L
10039 //GB_TILE_MODE23
10040 #define GB_TILE_MODE23__ARRAY_MODE__SHIFT                                                                     0x2
10041 #define GB_TILE_MODE23__PIPE_CONFIG__SHIFT                                                                    0x6
10042 #define GB_TILE_MODE23__TILE_SPLIT__SHIFT                                                                     0xb
10043 #define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
10044 #define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT                                                                   0x19
10045 #define GB_TILE_MODE23__ARRAY_MODE_MASK                                                                       0x0000003CL
10046 #define GB_TILE_MODE23__PIPE_CONFIG_MASK                                                                      0x000007C0L
10047 #define GB_TILE_MODE23__TILE_SPLIT_MASK                                                                       0x00003800L
10048 #define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
10049 #define GB_TILE_MODE23__SAMPLE_SPLIT_MASK                                                                     0x06000000L
10050 //GB_TILE_MODE24
10051 #define GB_TILE_MODE24__ARRAY_MODE__SHIFT                                                                     0x2
10052 #define GB_TILE_MODE24__PIPE_CONFIG__SHIFT                                                                    0x6
10053 #define GB_TILE_MODE24__TILE_SPLIT__SHIFT                                                                     0xb
10054 #define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
10055 #define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT                                                                   0x19
10056 #define GB_TILE_MODE24__ARRAY_MODE_MASK                                                                       0x0000003CL
10057 #define GB_TILE_MODE24__PIPE_CONFIG_MASK                                                                      0x000007C0L
10058 #define GB_TILE_MODE24__TILE_SPLIT_MASK                                                                       0x00003800L
10059 #define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
10060 #define GB_TILE_MODE24__SAMPLE_SPLIT_MASK                                                                     0x06000000L
10061 //GB_TILE_MODE25
10062 #define GB_TILE_MODE25__ARRAY_MODE__SHIFT                                                                     0x2
10063 #define GB_TILE_MODE25__PIPE_CONFIG__SHIFT                                                                    0x6
10064 #define GB_TILE_MODE25__TILE_SPLIT__SHIFT                                                                     0xb
10065 #define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
10066 #define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT                                                                   0x19
10067 #define GB_TILE_MODE25__ARRAY_MODE_MASK                                                                       0x0000003CL
10068 #define GB_TILE_MODE25__PIPE_CONFIG_MASK                                                                      0x000007C0L
10069 #define GB_TILE_MODE25__TILE_SPLIT_MASK                                                                       0x00003800L
10070 #define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
10071 #define GB_TILE_MODE25__SAMPLE_SPLIT_MASK                                                                     0x06000000L
10072 //GB_TILE_MODE26
10073 #define GB_TILE_MODE26__ARRAY_MODE__SHIFT                                                                     0x2
10074 #define GB_TILE_MODE26__PIPE_CONFIG__SHIFT                                                                    0x6
10075 #define GB_TILE_MODE26__TILE_SPLIT__SHIFT                                                                     0xb
10076 #define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
10077 #define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT                                                                   0x19
10078 #define GB_TILE_MODE26__ARRAY_MODE_MASK                                                                       0x0000003CL
10079 #define GB_TILE_MODE26__PIPE_CONFIG_MASK                                                                      0x000007C0L
10080 #define GB_TILE_MODE26__TILE_SPLIT_MASK                                                                       0x00003800L
10081 #define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
10082 #define GB_TILE_MODE26__SAMPLE_SPLIT_MASK                                                                     0x06000000L
10083 //GB_TILE_MODE27
10084 #define GB_TILE_MODE27__ARRAY_MODE__SHIFT                                                                     0x2
10085 #define GB_TILE_MODE27__PIPE_CONFIG__SHIFT                                                                    0x6
10086 #define GB_TILE_MODE27__TILE_SPLIT__SHIFT                                                                     0xb
10087 #define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
10088 #define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT                                                                   0x19
10089 #define GB_TILE_MODE27__ARRAY_MODE_MASK                                                                       0x0000003CL
10090 #define GB_TILE_MODE27__PIPE_CONFIG_MASK                                                                      0x000007C0L
10091 #define GB_TILE_MODE27__TILE_SPLIT_MASK                                                                       0x00003800L
10092 #define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
10093 #define GB_TILE_MODE27__SAMPLE_SPLIT_MASK                                                                     0x06000000L
10094 //GB_TILE_MODE28
10095 #define GB_TILE_MODE28__ARRAY_MODE__SHIFT                                                                     0x2
10096 #define GB_TILE_MODE28__PIPE_CONFIG__SHIFT                                                                    0x6
10097 #define GB_TILE_MODE28__TILE_SPLIT__SHIFT                                                                     0xb
10098 #define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
10099 #define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT                                                                   0x19
10100 #define GB_TILE_MODE28__ARRAY_MODE_MASK                                                                       0x0000003CL
10101 #define GB_TILE_MODE28__PIPE_CONFIG_MASK                                                                      0x000007C0L
10102 #define GB_TILE_MODE28__TILE_SPLIT_MASK                                                                       0x00003800L
10103 #define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
10104 #define GB_TILE_MODE28__SAMPLE_SPLIT_MASK                                                                     0x06000000L
10105 //GB_TILE_MODE29
10106 #define GB_TILE_MODE29__ARRAY_MODE__SHIFT                                                                     0x2
10107 #define GB_TILE_MODE29__PIPE_CONFIG__SHIFT                                                                    0x6
10108 #define GB_TILE_MODE29__TILE_SPLIT__SHIFT                                                                     0xb
10109 #define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
10110 #define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT                                                                   0x19
10111 #define GB_TILE_MODE29__ARRAY_MODE_MASK                                                                       0x0000003CL
10112 #define GB_TILE_MODE29__PIPE_CONFIG_MASK                                                                      0x000007C0L
10113 #define GB_TILE_MODE29__TILE_SPLIT_MASK                                                                       0x00003800L
10114 #define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
10115 #define GB_TILE_MODE29__SAMPLE_SPLIT_MASK                                                                     0x06000000L
10116 //GB_TILE_MODE30
10117 #define GB_TILE_MODE30__ARRAY_MODE__SHIFT                                                                     0x2
10118 #define GB_TILE_MODE30__PIPE_CONFIG__SHIFT                                                                    0x6
10119 #define GB_TILE_MODE30__TILE_SPLIT__SHIFT                                                                     0xb
10120 #define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
10121 #define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT                                                                   0x19
10122 #define GB_TILE_MODE30__ARRAY_MODE_MASK                                                                       0x0000003CL
10123 #define GB_TILE_MODE30__PIPE_CONFIG_MASK                                                                      0x000007C0L
10124 #define GB_TILE_MODE30__TILE_SPLIT_MASK                                                                       0x00003800L
10125 #define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
10126 #define GB_TILE_MODE30__SAMPLE_SPLIT_MASK                                                                     0x06000000L
10127 //GB_TILE_MODE31
10128 #define GB_TILE_MODE31__ARRAY_MODE__SHIFT                                                                     0x2
10129 #define GB_TILE_MODE31__PIPE_CONFIG__SHIFT                                                                    0x6
10130 #define GB_TILE_MODE31__TILE_SPLIT__SHIFT                                                                     0xb
10131 #define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
10132 #define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT                                                                   0x19
10133 #define GB_TILE_MODE31__ARRAY_MODE_MASK                                                                       0x0000003CL
10134 #define GB_TILE_MODE31__PIPE_CONFIG_MASK                                                                      0x000007C0L
10135 #define GB_TILE_MODE31__TILE_SPLIT_MASK                                                                       0x00003800L
10136 #define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
10137 #define GB_TILE_MODE31__SAMPLE_SPLIT_MASK                                                                     0x06000000L
10138 //GB_MACROTILE_MODE0
10139 #define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT                                                                 0x0
10140 #define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT                                                                0x2
10141 #define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT                                                          0x4
10142 #define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT                                                                  0x6
10143 #define GB_MACROTILE_MODE0__BANK_WIDTH_MASK                                                                   0x00000003L
10144 #define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK                                                                  0x0000000CL
10145 #define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
10146 #define GB_MACROTILE_MODE0__NUM_BANKS_MASK                                                                    0x000000C0L
10147 //GB_MACROTILE_MODE1
10148 #define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT                                                                 0x0
10149 #define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT                                                                0x2
10150 #define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT                                                          0x4
10151 #define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT                                                                  0x6
10152 #define GB_MACROTILE_MODE1__BANK_WIDTH_MASK                                                                   0x00000003L
10153 #define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK                                                                  0x0000000CL
10154 #define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
10155 #define GB_MACROTILE_MODE1__NUM_BANKS_MASK                                                                    0x000000C0L
10156 //GB_MACROTILE_MODE2
10157 #define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT                                                                 0x0
10158 #define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT                                                                0x2
10159 #define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT                                                          0x4
10160 #define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT                                                                  0x6
10161 #define GB_MACROTILE_MODE2__BANK_WIDTH_MASK                                                                   0x00000003L
10162 #define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK                                                                  0x0000000CL
10163 #define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
10164 #define GB_MACROTILE_MODE2__NUM_BANKS_MASK                                                                    0x000000C0L
10165 //GB_MACROTILE_MODE3
10166 #define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT                                                                 0x0
10167 #define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT                                                                0x2
10168 #define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT                                                          0x4
10169 #define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT                                                                  0x6
10170 #define GB_MACROTILE_MODE3__BANK_WIDTH_MASK                                                                   0x00000003L
10171 #define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK                                                                  0x0000000CL
10172 #define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
10173 #define GB_MACROTILE_MODE3__NUM_BANKS_MASK                                                                    0x000000C0L
10174 //GB_MACROTILE_MODE4
10175 #define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT                                                                 0x0
10176 #define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT                                                                0x2
10177 #define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT                                                          0x4
10178 #define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT                                                                  0x6
10179 #define GB_MACROTILE_MODE4__BANK_WIDTH_MASK                                                                   0x00000003L
10180 #define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK                                                                  0x0000000CL
10181 #define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
10182 #define GB_MACROTILE_MODE4__NUM_BANKS_MASK                                                                    0x000000C0L
10183 //GB_MACROTILE_MODE5
10184 #define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT                                                                 0x0
10185 #define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT                                                                0x2
10186 #define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT                                                          0x4
10187 #define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT                                                                  0x6
10188 #define GB_MACROTILE_MODE5__BANK_WIDTH_MASK                                                                   0x00000003L
10189 #define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK                                                                  0x0000000CL
10190 #define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
10191 #define GB_MACROTILE_MODE5__NUM_BANKS_MASK                                                                    0x000000C0L
10192 //GB_MACROTILE_MODE6
10193 #define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT                                                                 0x0
10194 #define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT                                                                0x2
10195 #define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT                                                          0x4
10196 #define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT                                                                  0x6
10197 #define GB_MACROTILE_MODE6__BANK_WIDTH_MASK                                                                   0x00000003L
10198 #define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK                                                                  0x0000000CL
10199 #define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
10200 #define GB_MACROTILE_MODE6__NUM_BANKS_MASK                                                                    0x000000C0L
10201 //GB_MACROTILE_MODE7
10202 #define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT                                                                 0x0
10203 #define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT                                                                0x2
10204 #define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT                                                          0x4
10205 #define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT                                                                  0x6
10206 #define GB_MACROTILE_MODE7__BANK_WIDTH_MASK                                                                   0x00000003L
10207 #define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK                                                                  0x0000000CL
10208 #define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
10209 #define GB_MACROTILE_MODE7__NUM_BANKS_MASK                                                                    0x000000C0L
10210 //GB_MACROTILE_MODE8
10211 #define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT                                                                 0x0
10212 #define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT                                                                0x2
10213 #define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT                                                          0x4
10214 #define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT                                                                  0x6
10215 #define GB_MACROTILE_MODE8__BANK_WIDTH_MASK                                                                   0x00000003L
10216 #define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK                                                                  0x0000000CL
10217 #define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
10218 #define GB_MACROTILE_MODE8__NUM_BANKS_MASK                                                                    0x000000C0L
10219 //GB_MACROTILE_MODE9
10220 #define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT                                                                 0x0
10221 #define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT                                                                0x2
10222 #define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT                                                          0x4
10223 #define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT                                                                  0x6
10224 #define GB_MACROTILE_MODE9__BANK_WIDTH_MASK                                                                   0x00000003L
10225 #define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK                                                                  0x0000000CL
10226 #define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
10227 #define GB_MACROTILE_MODE9__NUM_BANKS_MASK                                                                    0x000000C0L
10228 //GB_MACROTILE_MODE10
10229 #define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT                                                                0x0
10230 #define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT                                                               0x2
10231 #define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT                                                         0x4
10232 #define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT                                                                 0x6
10233 #define GB_MACROTILE_MODE10__BANK_WIDTH_MASK                                                                  0x00000003L
10234 #define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK                                                                 0x0000000CL
10235 #define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK                                                           0x00000030L
10236 #define GB_MACROTILE_MODE10__NUM_BANKS_MASK                                                                   0x000000C0L
10237 //GB_MACROTILE_MODE11
10238 #define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT                                                                0x0
10239 #define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT                                                               0x2
10240 #define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT                                                         0x4
10241 #define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT                                                                 0x6
10242 #define GB_MACROTILE_MODE11__BANK_WIDTH_MASK                                                                  0x00000003L
10243 #define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK                                                                 0x0000000CL
10244 #define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK                                                           0x00000030L
10245 #define GB_MACROTILE_MODE11__NUM_BANKS_MASK                                                                   0x000000C0L
10246 //GB_MACROTILE_MODE12
10247 #define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT                                                                0x0
10248 #define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT                                                               0x2
10249 #define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT                                                         0x4
10250 #define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT                                                                 0x6
10251 #define GB_MACROTILE_MODE12__BANK_WIDTH_MASK                                                                  0x00000003L
10252 #define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK                                                                 0x0000000CL
10253 #define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK                                                           0x00000030L
10254 #define GB_MACROTILE_MODE12__NUM_BANKS_MASK                                                                   0x000000C0L
10255 //GB_MACROTILE_MODE13
10256 #define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT                                                                0x0
10257 #define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT                                                               0x2
10258 #define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT                                                         0x4
10259 #define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT                                                                 0x6
10260 #define GB_MACROTILE_MODE13__BANK_WIDTH_MASK                                                                  0x00000003L
10261 #define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK                                                                 0x0000000CL
10262 #define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK                                                           0x00000030L
10263 #define GB_MACROTILE_MODE13__NUM_BANKS_MASK                                                                   0x000000C0L
10264 //GB_MACROTILE_MODE14
10265 #define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT                                                                0x0
10266 #define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT                                                               0x2
10267 #define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT                                                         0x4
10268 #define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT                                                                 0x6
10269 #define GB_MACROTILE_MODE14__BANK_WIDTH_MASK                                                                  0x00000003L
10270 #define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK                                                                 0x0000000CL
10271 #define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK                                                           0x00000030L
10272 #define GB_MACROTILE_MODE14__NUM_BANKS_MASK                                                                   0x000000C0L
10273 //GB_MACROTILE_MODE15
10274 #define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT                                                                0x0
10275 #define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT                                                               0x2
10276 #define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT                                                         0x4
10277 #define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT                                                                 0x6
10278 #define GB_MACROTILE_MODE15__BANK_WIDTH_MASK                                                                  0x00000003L
10279 #define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK                                                                 0x0000000CL
10280 #define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK                                                           0x00000030L
10281 #define GB_MACROTILE_MODE15__NUM_BANKS_MASK                                                                   0x000000C0L
10282 //CB_HW_CONTROL_4
10283 #define CB_HW_CONTROL_4__COLOR_CACHE_FETCH_NUM_CLS_LOG2__SHIFT                                                0x0
10284 #define CB_HW_CONTROL_4__FMASK_CACHE_FETCH_NUM_CLS_LOG2__SHIFT                                                0x3
10285 #define CB_HW_CONTROL_4__DISABLE_USE_OF_QUAD_SCOREBOARD__SHIFT                                                0x5
10286 #define CB_HW_CONTROL_4__DISABLE_CMASK_CLOCK_GATING__SHIFT                                                    0x6
10287 #define CB_HW_CONTROL_4__DISABLE_FMASK_CLOCK_GATING__SHIFT                                                    0x7
10288 #define CB_HW_CONTROL_4__DISABLE_COLOR_CLOCK_GATING__SHIFT                                                    0x8
10289 #define CB_HW_CONTROL_4__DISABLE_QSB_AA_MODE__SHIFT                                                           0x9
10290 #define CB_HW_CONTROL_4__DISABLE_QSB_WAIT_FOR_SCORE__SHIFT                                                    0xa
10291 #define CB_HW_CONTROL_4__DISABLE_QSB_FRAG_GT0__SHIFT                                                          0xb
10292 #define CB_HW_CONTROL_4__REVERSE_KEYXFR_RD_PRIORITY__SHIFT                                                    0xc
10293 #define CB_HW_CONTROL_4__DISABLE_KEYXFR_HIT_RETURNS__SHIFT                                                    0xd
10294 #define CB_HW_CONTROL_4__DISABLE_BC_COLOR_CACHE_PREFETCH__SHIFT                                               0xe
10295 #define CB_HW_CONTROL_4__DISABLE_MA_WAIT_FOR_LAST__SHIFT                                                      0xf
10296 #define CB_HW_CONTROL_4__DISABLE_QSB_SPECULATIVE__SHIFT                                                       0x10
10297 #define CB_HW_CONTROL_4__QSB_WAIT_FOR_SCORE__SHIFT                                                            0x11
10298 #define CB_HW_CONTROL_4__DISABLE_TILE_FGCG__SHIFT                                                             0x16
10299 #define CB_HW_CONTROL_4__DISABLE_LQUAD_FGCG__SHIFT                                                            0x17
10300 #define CB_HW_CONTROL_4__FC_QSB_FIFO_DEPTH__SHIFT                                                             0x18
10301 #define CB_HW_CONTROL_4__COLOR_CACHE_FETCH_NUM_CLS_LOG2_MASK                                                  0x00000007L
10302 #define CB_HW_CONTROL_4__FMASK_CACHE_FETCH_NUM_CLS_LOG2_MASK                                                  0x00000018L
10303 #define CB_HW_CONTROL_4__DISABLE_USE_OF_QUAD_SCOREBOARD_MASK                                                  0x00000020L
10304 #define CB_HW_CONTROL_4__DISABLE_CMASK_CLOCK_GATING_MASK                                                      0x00000040L
10305 #define CB_HW_CONTROL_4__DISABLE_FMASK_CLOCK_GATING_MASK                                                      0x00000080L
10306 #define CB_HW_CONTROL_4__DISABLE_COLOR_CLOCK_GATING_MASK                                                      0x00000100L
10307 #define CB_HW_CONTROL_4__DISABLE_QSB_AA_MODE_MASK                                                             0x00000200L
10308 #define CB_HW_CONTROL_4__DISABLE_QSB_WAIT_FOR_SCORE_MASK                                                      0x00000400L
10309 #define CB_HW_CONTROL_4__DISABLE_QSB_FRAG_GT0_MASK                                                            0x00000800L
10310 #define CB_HW_CONTROL_4__REVERSE_KEYXFR_RD_PRIORITY_MASK                                                      0x00001000L
10311 #define CB_HW_CONTROL_4__DISABLE_KEYXFR_HIT_RETURNS_MASK                                                      0x00002000L
10312 #define CB_HW_CONTROL_4__DISABLE_BC_COLOR_CACHE_PREFETCH_MASK                                                 0x00004000L
10313 #define CB_HW_CONTROL_4__DISABLE_MA_WAIT_FOR_LAST_MASK                                                        0x00008000L
10314 #define CB_HW_CONTROL_4__DISABLE_QSB_SPECULATIVE_MASK                                                         0x00010000L
10315 #define CB_HW_CONTROL_4__QSB_WAIT_FOR_SCORE_MASK                                                              0x003E0000L
10316 #define CB_HW_CONTROL_4__DISABLE_TILE_FGCG_MASK                                                               0x00400000L
10317 #define CB_HW_CONTROL_4__DISABLE_LQUAD_FGCG_MASK                                                              0x00800000L
10318 #define CB_HW_CONTROL_4__FC_QSB_FIFO_DEPTH_MASK                                                               0xFF000000L
10319 //CB_HW_CONTROL_3
10320 #define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT                                        0x0
10321 #define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT                                              0x1
10322 #define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT                                                  0x2
10323 #define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT                                                 0x3
10324 #define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT                                            0x4
10325 #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT                                            0x5
10326 #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT                                                 0x7
10327 #define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT                             0x8
10328 #define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT                                                 0x9
10329 #define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT                                                     0xa
10330 #define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION__SHIFT                                             0xb
10331 #define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967__SHIFT                                              0xc
10332 #define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657__SHIFT                                              0xd
10333 #define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542__SHIFT                                                0xe
10334 #define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH__SHIFT                                                           0xf
10335 #define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH__SHIFT                                                          0x10
10336 #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC__SHIFT                                                       0x11
10337 #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC__SHIFT                                                       0x12
10338 #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC__SHIFT                                                       0x13
10339 #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM__SHIFT                                                       0x14
10340 #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC__SHIFT                                                    0x15
10341 #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC__SHIFT                                                    0x16
10342 #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC__SHIFT                                                    0x17
10343 #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM__SHIFT                                                    0x18
10344 #define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT__SHIFT                                                  0x19
10345 #define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING__SHIFT                                                  0x1a
10346 #define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX__SHIFT                                            0x1b
10347 #define CB_HW_CONTROL_3__DISABLE_FMASK_NOFETCH_OPT__SHIFT                                                     0x1e
10348 #define CB_HW_CONTROL_3__DISABLE_FMASK_NOFETCH_OPT_BC__SHIFT                                                  0x1f
10349 #define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK                                          0x00000001L
10350 #define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK                                                0x00000002L
10351 #define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK                                                    0x00000004L
10352 #define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK                                                   0x00000008L
10353 #define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK                                              0x00000010L
10354 #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK                                              0x00000020L
10355 #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK                                                   0x00000080L
10356 #define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK                               0x00000100L
10357 #define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK                                                   0x00000200L
10358 #define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK                                                       0x00000400L
10359 #define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION_MASK                                               0x00000800L
10360 #define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967_MASK                                                0x00001000L
10361 #define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657_MASK                                                0x00002000L
10362 #define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542_MASK                                                  0x00004000L
10363 #define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH_MASK                                                             0x00008000L
10364 #define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH_MASK                                                            0x00010000L
10365 #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC_MASK                                                         0x00020000L
10366 #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC_MASK                                                         0x00040000L
10367 #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC_MASK                                                         0x00080000L
10368 #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM_MASK                                                         0x00100000L
10369 #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC_MASK                                                      0x00200000L
10370 #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC_MASK                                                      0x00400000L
10371 #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC_MASK                                                      0x00800000L
10372 #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM_MASK                                                      0x01000000L
10373 #define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT_MASK                                                    0x02000000L
10374 #define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING_MASK                                                    0x04000000L
10375 #define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX_MASK                                              0x08000000L
10376 #define CB_HW_CONTROL_3__DISABLE_FMASK_NOFETCH_OPT_MASK                                                       0x40000000L
10377 #define CB_HW_CONTROL_3__DISABLE_FMASK_NOFETCH_OPT_BC_MASK                                                    0x80000000L
10378 //CB_HW_CONTROL
10379 #define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT                                                      0x0
10380 #define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT                                                0x12
10381 #define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT                                                                 0x13
10382 #define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT                                                             0x14
10383 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT                                                0x15
10384 #define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT                                                         0x16
10385 #define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT                                             0x17
10386 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT                                                   0x18
10387 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT                                                        0x19
10388 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT                                                 0x1a
10389 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT                                0x1b
10390 #define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT                                   0x1c
10391 #define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT                                0x1d
10392 #define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT                                              0x1e
10393 #define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT                                    0x1f
10394 #define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK                                                        0x00000001L
10395 #define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK                                                  0x00040000L
10396 #define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK                                                                   0x00080000L
10397 #define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK                                                               0x00100000L
10398 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK                                                  0x00200000L
10399 #define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK                                                           0x00400000L
10400 #define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK                                               0x00800000L
10401 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK                                                     0x01000000L
10402 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK                                                          0x02000000L
10403 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK                                                   0x04000000L
10404 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK                                  0x08000000L
10405 #define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK                                     0x10000000L
10406 #define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK                                  0x20000000L
10407 #define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK                                                0x40000000L
10408 #define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK                                      0x80000000L
10409 //CB_HW_CONTROL_1
10410 #define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT                                                             0x0
10411 #define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT                                                             0x5
10412 #define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT                                                             0xb
10413 #define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT                                                            0x11
10414 #define CB_HW_CONTROL_1__RMI_CREDITS__SHIFT                                                                   0x1a
10415 #define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK                                                               0x0000001FL
10416 #define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK                                                               0x000007E0L
10417 #define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK                                                               0x0001F800L
10418 #define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK                                                              0x03FE0000L
10419 #define CB_HW_CONTROL_1__RMI_CREDITS_MASK                                                                     0xFC000000L
10420 //CB_HW_CONTROL_2
10421 #define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT                                                        0x0
10422 #define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT                                                      0x8
10423 #define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT                                                      0xf
10424 #define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT                                                   0x18
10425 #define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT                                                                  0x1e
10426 #define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK                                                          0x000000FFL
10427 #define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK                                                        0x00007F00L
10428 #define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK                                                        0x007F8000L
10429 #define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK                                                     0x3F000000L
10430 #define CB_HW_CONTROL_2__CHICKEN_BITS_MASK                                                                    0xC0000000L
10431 //CB_DCC_CONFIG
10432 #define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT                                                        0x0
10433 #define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT                                                      0x5
10434 #define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT                                               0x6
10435 #define CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE__SHIFT                                                         0x7
10436 #define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT                                                       0x8
10437 #define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT                                                     0x10
10438 #define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT                                                              0x1a
10439 #define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK                                                          0x0000001FL
10440 #define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK                                                        0x00000020L
10441 #define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK                                                 0x00000040L
10442 #define CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE_MASK                                                           0x00000080L
10443 #define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK                                                         0x0000FF00L
10444 #define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK                                                       0x01FF0000L
10445 #define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK                                                                0xFC000000L
10446 //CB_HW_MEM_ARBITER_RD
10447 #define CB_HW_MEM_ARBITER_RD__MODE__SHIFT                                                                     0x0
10448 #define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE__SHIFT                                                        0x2
10449 #define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE__SHIFT                                                          0x6
10450 #define CB_HW_MEM_ARBITER_RD__WEIGHT_CC__SHIFT                                                                0xa
10451 #define CB_HW_MEM_ARBITER_RD__WEIGHT_FC__SHIFT                                                                0xc
10452 #define CB_HW_MEM_ARBITER_RD__WEIGHT_CM__SHIFT                                                                0xe
10453 #define CB_HW_MEM_ARBITER_RD__WEIGHT_DC__SHIFT                                                                0x10
10454 #define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS__SHIFT                                                        0x12
10455 #define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS__SHIFT                                                      0x14
10456 #define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS__SHIFT                                                   0x16
10457 #define CB_HW_MEM_ARBITER_RD__SCALE_AGE__SHIFT                                                                0x17
10458 #define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT__SHIFT                                                             0x1a
10459 #define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS__SHIFT                                                 0x1d
10460 #define CB_HW_MEM_ARBITER_RD__MODE_MASK                                                                       0x00000003L
10461 #define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE_MASK                                                          0x0000003CL
10462 #define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE_MASK                                                            0x000003C0L
10463 #define CB_HW_MEM_ARBITER_RD__WEIGHT_CC_MASK                                                                  0x00000C00L
10464 #define CB_HW_MEM_ARBITER_RD__WEIGHT_FC_MASK                                                                  0x00003000L
10465 #define CB_HW_MEM_ARBITER_RD__WEIGHT_CM_MASK                                                                  0x0000C000L
10466 #define CB_HW_MEM_ARBITER_RD__WEIGHT_DC_MASK                                                                  0x00030000L
10467 #define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS_MASK                                                          0x000C0000L
10468 #define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS_MASK                                                        0x00300000L
10469 #define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS_MASK                                                     0x00400000L
10470 #define CB_HW_MEM_ARBITER_RD__SCALE_AGE_MASK                                                                  0x03800000L
10471 #define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT_MASK                                                               0x1C000000L
10472 #define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS_MASK                                                   0x20000000L
10473 //CB_HW_MEM_ARBITER_WR
10474 #define CB_HW_MEM_ARBITER_WR__MODE__SHIFT                                                                     0x0
10475 #define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE__SHIFT                                                        0x2
10476 #define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE__SHIFT                                                          0x6
10477 #define CB_HW_MEM_ARBITER_WR__WEIGHT_CC__SHIFT                                                                0xa
10478 #define CB_HW_MEM_ARBITER_WR__WEIGHT_FC__SHIFT                                                                0xc
10479 #define CB_HW_MEM_ARBITER_WR__WEIGHT_CM__SHIFT                                                                0xe
10480 #define CB_HW_MEM_ARBITER_WR__WEIGHT_DC__SHIFT                                                                0x10
10481 #define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS__SHIFT                                                        0x12
10482 #define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS__SHIFT                                                      0x14
10483 #define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK__SHIFT                                                  0x16
10484 #define CB_HW_MEM_ARBITER_WR__SCALE_AGE__SHIFT                                                                0x17
10485 #define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT__SHIFT                                                             0x1a
10486 #define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS__SHIFT                                                 0x1d
10487 #define CB_HW_MEM_ARBITER_WR__MODE_MASK                                                                       0x00000003L
10488 #define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE_MASK                                                          0x0000003CL
10489 #define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE_MASK                                                            0x000003C0L
10490 #define CB_HW_MEM_ARBITER_WR__WEIGHT_CC_MASK                                                                  0x00000C00L
10491 #define CB_HW_MEM_ARBITER_WR__WEIGHT_FC_MASK                                                                  0x00003000L
10492 #define CB_HW_MEM_ARBITER_WR__WEIGHT_CM_MASK                                                                  0x0000C000L
10493 #define CB_HW_MEM_ARBITER_WR__WEIGHT_DC_MASK                                                                  0x00030000L
10494 #define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS_MASK                                                          0x000C0000L
10495 #define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS_MASK                                                        0x00300000L
10496 #define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK_MASK                                                    0x00400000L
10497 #define CB_HW_MEM_ARBITER_WR__SCALE_AGE_MASK                                                                  0x03800000L
10498 #define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT_MASK                                                               0x1C000000L
10499 #define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS_MASK                                                   0x20000000L
10500 //CB_RMI_BC_GL2_CACHE_CONTROL
10501 #define CB_RMI_BC_GL2_CACHE_CONTROL__CMASK_WR_POLICY__SHIFT                                                   0x0
10502 #define CB_RMI_BC_GL2_CACHE_CONTROL__FMASK_WR_POLICY__SHIFT                                                   0x2
10503 #define CB_RMI_BC_GL2_CACHE_CONTROL__DCC_WR_POLICY__SHIFT                                                     0x4
10504 #define CB_RMI_BC_GL2_CACHE_CONTROL__COLOR_WR_POLICY__SHIFT                                                   0x6
10505 #define CB_RMI_BC_GL2_CACHE_CONTROL__CMASK_RD_POLICY__SHIFT                                                   0x10
10506 #define CB_RMI_BC_GL2_CACHE_CONTROL__FMASK_RD_POLICY__SHIFT                                                   0x12
10507 #define CB_RMI_BC_GL2_CACHE_CONTROL__DCC_RD_POLICY__SHIFT                                                     0x14
10508 #define CB_RMI_BC_GL2_CACHE_CONTROL__COLOR_RD_POLICY__SHIFT                                                   0x16
10509 #define CB_RMI_BC_GL2_CACHE_CONTROL__VOLAT__SHIFT                                                             0x1f
10510 #define CB_RMI_BC_GL2_CACHE_CONTROL__CMASK_WR_POLICY_MASK                                                     0x00000003L
10511 #define CB_RMI_BC_GL2_CACHE_CONTROL__FMASK_WR_POLICY_MASK                                                     0x0000000CL
10512 #define CB_RMI_BC_GL2_CACHE_CONTROL__DCC_WR_POLICY_MASK                                                       0x00000030L
10513 #define CB_RMI_BC_GL2_CACHE_CONTROL__COLOR_WR_POLICY_MASK                                                     0x000000C0L
10514 #define CB_RMI_BC_GL2_CACHE_CONTROL__CMASK_RD_POLICY_MASK                                                     0x00030000L
10515 #define CB_RMI_BC_GL2_CACHE_CONTROL__FMASK_RD_POLICY_MASK                                                     0x000C0000L
10516 #define CB_RMI_BC_GL2_CACHE_CONTROL__DCC_RD_POLICY_MASK                                                       0x00300000L
10517 #define CB_RMI_BC_GL2_CACHE_CONTROL__COLOR_RD_POLICY_MASK                                                     0x00C00000L
10518 #define CB_RMI_BC_GL2_CACHE_CONTROL__VOLAT_MASK                                                               0x80000000L
10519 //CB_STUTTER_CONTROL_CMASK_RDLAT
10520 #define CB_STUTTER_CONTROL_CMASK_RDLAT__THRESHOLD__SHIFT                                                      0x0
10521 #define CB_STUTTER_CONTROL_CMASK_RDLAT__TIMEOUT__SHIFT                                                        0x8
10522 #define CB_STUTTER_CONTROL_CMASK_RDLAT__THRESHOLD_MASK                                                        0x000000FFL
10523 #define CB_STUTTER_CONTROL_CMASK_RDLAT__TIMEOUT_MASK                                                          0x0000FF00L
10524 //CB_STUTTER_CONTROL_FMASK_RDLAT
10525 #define CB_STUTTER_CONTROL_FMASK_RDLAT__THRESHOLD__SHIFT                                                      0x0
10526 #define CB_STUTTER_CONTROL_FMASK_RDLAT__TIMEOUT__SHIFT                                                        0x8
10527 #define CB_STUTTER_CONTROL_FMASK_RDLAT__THRESHOLD_MASK                                                        0x000000FFL
10528 #define CB_STUTTER_CONTROL_FMASK_RDLAT__TIMEOUT_MASK                                                          0x0000FF00L
10529 //CB_STUTTER_CONTROL_COLOR_RDLAT
10530 #define CB_STUTTER_CONTROL_COLOR_RDLAT__THRESHOLD__SHIFT                                                      0x0
10531 #define CB_STUTTER_CONTROL_COLOR_RDLAT__TIMEOUT__SHIFT                                                        0x8
10532 #define CB_STUTTER_CONTROL_COLOR_RDLAT__THRESHOLD_MASK                                                        0x000000FFL
10533 #define CB_STUTTER_CONTROL_COLOR_RDLAT__TIMEOUT_MASK                                                          0x0000FF00L
10534 //CB_CACHE_EVICT_POINTS
10535 #define CB_CACHE_EVICT_POINTS__CM_CACHE_EVICT_POINT__SHIFT                                                    0x0
10536 #define CB_CACHE_EVICT_POINTS__FC_CACHE_EVICT_POINT__SHIFT                                                    0x8
10537 #define CB_CACHE_EVICT_POINTS__DCC_CACHE_EVICT_POINT__SHIFT                                                   0x10
10538 #define CB_CACHE_EVICT_POINTS__CC_CACHE_EVICT_POINT__SHIFT                                                    0x18
10539 #define CB_CACHE_EVICT_POINTS__CM_CACHE_EVICT_POINT_MASK                                                      0x000000FFL
10540 #define CB_CACHE_EVICT_POINTS__FC_CACHE_EVICT_POINT_MASK                                                      0x0000FF00L
10541 #define CB_CACHE_EVICT_POINTS__DCC_CACHE_EVICT_POINT_MASK                                                     0x00FF0000L
10542 #define CB_CACHE_EVICT_POINTS__CC_CACHE_EVICT_POINT_MASK                                                      0xFF000000L
10543 //GC_USER_RB_REDUNDANCY
10544 #define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT                                                              0x8
10545 #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT                                                          0xc
10546 #define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT                                                              0x10
10547 #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT                                                          0x14
10548 #define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK                                                                0x00000F00L
10549 #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK                                                            0x00001000L
10550 #define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK                                                                0x000F0000L
10551 #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK                                                            0x00100000L
10552 //GC_USER_RB_BACKEND_DISABLE
10553 #define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT                                                    0x10
10554 #define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK                                                      0x00FF0000L
10555 
10556 
10557 // addressBlock: gc_gceadec2
10558 //GCEA_SDP_VCD_RESERVE1
10559 #define GCEA_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT                                                             0x0
10560 #define GCEA_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT                                                             0x6
10561 #define GCEA_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT                                                             0xc
10562 #define GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                         0x1f
10563 #define GCEA_SDP_VCD_RESERVE1__VC5_CREDITS_MASK                                                               0x0000003FL
10564 #define GCEA_SDP_VCD_RESERVE1__VC6_CREDITS_MASK                                                               0x00000FC0L
10565 #define GCEA_SDP_VCD_RESERVE1__VC7_CREDITS_MASK                                                               0x0003F000L
10566 #define GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK                                                           0x80000000L
10567 //GCEA_SDP_REQ_CNTL
10568 #define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT                                                   0x0
10569 #define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT                                                  0x1
10570 #define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT                                                 0x2
10571 #define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT                                                     0x3
10572 #define GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT                                                           0x4
10573 #define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK                                                     0x00000001L
10574 #define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK                                                    0x00000002L
10575 #define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK                                                   0x00000004L
10576 #define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK                                                       0x00000008L
10577 #define GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK                                                             0x00000010L
10578 //GCEA_MISC
10579 #define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT                                                         0x0
10580 #define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT                                                         0x1
10581 #define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT                                                          0x2
10582 #define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT                                                          0x3
10583 #define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT                                                           0x4
10584 #define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT                                                           0x5
10585 #define GCEA_MISC__EARLYWRRET_ENABLE_VC0__SHIFT                                                               0x6
10586 #define GCEA_MISC__EARLYWRRET_ENABLE_VC1__SHIFT                                                               0x7
10587 #define GCEA_MISC__EARLYWRRET_ENABLE_VC2__SHIFT                                                               0x8
10588 #define GCEA_MISC__EARLYWRRET_ENABLE_VC3__SHIFT                                                               0x9
10589 #define GCEA_MISC__EARLYWRRET_ENABLE_VC4__SHIFT                                                               0xa
10590 #define GCEA_MISC__EARLYWRRET_ENABLE_VC5__SHIFT                                                               0xb
10591 #define GCEA_MISC__EARLYWRRET_ENABLE_VC6__SHIFT                                                               0xc
10592 #define GCEA_MISC__EARLYWRRET_ENABLE_VC7__SHIFT                                                               0xd
10593 #define GCEA_MISC__EARLY_SDP_ORIGDATA__SHIFT                                                                  0xe
10594 #define GCEA_MISC__LINKMGR_DYNAMIC_MODE__SHIFT                                                                0xf
10595 #define GCEA_MISC__LINKMGR_HALT_THRESHOLD__SHIFT                                                              0x11
10596 #define GCEA_MISC__LINKMGR_RECONNECT_DELAY__SHIFT                                                             0x13
10597 #define GCEA_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT                                                              0x15
10598 #define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT                                                      0x1a
10599 #define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT                                                       0x1b
10600 #define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT                                                          0x1c
10601 #define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT                                                           0x1d
10602 #define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT                                                        0x1e
10603 #define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT                                                         0x1f
10604 #define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK                                                           0x00000001L
10605 #define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK                                                           0x00000002L
10606 #define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK                                                            0x00000004L
10607 #define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK                                                            0x00000008L
10608 #define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK                                                             0x00000010L
10609 #define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK                                                             0x00000020L
10610 #define GCEA_MISC__EARLYWRRET_ENABLE_VC0_MASK                                                                 0x00000040L
10611 #define GCEA_MISC__EARLYWRRET_ENABLE_VC1_MASK                                                                 0x00000080L
10612 #define GCEA_MISC__EARLYWRRET_ENABLE_VC2_MASK                                                                 0x00000100L
10613 #define GCEA_MISC__EARLYWRRET_ENABLE_VC3_MASK                                                                 0x00000200L
10614 #define GCEA_MISC__EARLYWRRET_ENABLE_VC4_MASK                                                                 0x00000400L
10615 #define GCEA_MISC__EARLYWRRET_ENABLE_VC5_MASK                                                                 0x00000800L
10616 #define GCEA_MISC__EARLYWRRET_ENABLE_VC6_MASK                                                                 0x00001000L
10617 #define GCEA_MISC__EARLYWRRET_ENABLE_VC7_MASK                                                                 0x00002000L
10618 #define GCEA_MISC__EARLY_SDP_ORIGDATA_MASK                                                                    0x00004000L
10619 #define GCEA_MISC__LINKMGR_DYNAMIC_MODE_MASK                                                                  0x00018000L
10620 #define GCEA_MISC__LINKMGR_HALT_THRESHOLD_MASK                                                                0x00060000L
10621 #define GCEA_MISC__LINKMGR_RECONNECT_DELAY_MASK                                                               0x00180000L
10622 #define GCEA_MISC__LINKMGR_IDLE_THRESHOLD_MASK                                                                0x03E00000L
10623 #define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK                                                        0x04000000L
10624 #define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK                                                         0x08000000L
10625 #define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK                                                            0x10000000L
10626 #define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK                                                             0x20000000L
10627 #define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK                                                          0x40000000L
10628 #define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK                                                           0x80000000L
10629 //GCEA_LATENCY_SAMPLING
10630 #define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT                                                           0x0
10631 #define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT                                                           0x1
10632 #define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT                                                            0x2
10633 #define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT                                                            0x3
10634 #define GCEA_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT                                                             0x4
10635 #define GCEA_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT                                                             0x5
10636 #define GCEA_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT                                                           0x6
10637 #define GCEA_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT                                                           0x7
10638 #define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT                                                          0x8
10639 #define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT                                                          0x9
10640 #define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT                                                     0xa
10641 #define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT                                                     0xb
10642 #define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT                                                   0xc
10643 #define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT                                                   0xd
10644 #define GCEA_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT                                                             0xe
10645 #define GCEA_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT                                                             0x16
10646 #define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK                                                             0x00000001L
10647 #define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK                                                             0x00000002L
10648 #define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI_MASK                                                              0x00000004L
10649 #define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI_MASK                                                              0x00000008L
10650 #define GCEA_LATENCY_SAMPLING__SAMPLER0_IO_MASK                                                               0x00000010L
10651 #define GCEA_LATENCY_SAMPLING__SAMPLER1_IO_MASK                                                               0x00000020L
10652 #define GCEA_LATENCY_SAMPLING__SAMPLER0_READ_MASK                                                             0x00000040L
10653 #define GCEA_LATENCY_SAMPLING__SAMPLER1_READ_MASK                                                             0x00000080L
10654 #define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK                                                            0x00000100L
10655 #define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK                                                            0x00000200L
10656 #define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK                                                       0x00000400L
10657 #define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK                                                       0x00000800L
10658 #define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK                                                     0x00001000L
10659 #define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK                                                     0x00002000L
10660 #define GCEA_LATENCY_SAMPLING__SAMPLER0_VC_MASK                                                               0x003FC000L
10661 #define GCEA_LATENCY_SAMPLING__SAMPLER1_VC_MASK                                                               0x3FC00000L
10662 //GCEA_PERFCOUNTER_LO
10663 #define GCEA_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                                0x0
10664 #define GCEA_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                  0xFFFFFFFFL
10665 //GCEA_PERFCOUNTER_HI
10666 #define GCEA_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                                0x0
10667 #define GCEA_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                             0x10
10668 #define GCEA_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                  0x0000FFFFL
10669 #define GCEA_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                               0xFFFF0000L
10670 //GCEA_PERFCOUNTER0_CFG
10671 #define GCEA_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                                0x0
10672 #define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                            0x8
10673 #define GCEA_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                               0x18
10674 #define GCEA_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                  0x1c
10675 #define GCEA_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                   0x1d
10676 #define GCEA_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                  0x000000FFL
10677 #define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                              0x0000FF00L
10678 #define GCEA_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                 0x0F000000L
10679 #define GCEA_PERFCOUNTER0_CFG__ENABLE_MASK                                                                    0x10000000L
10680 #define GCEA_PERFCOUNTER0_CFG__CLEAR_MASK                                                                     0x20000000L
10681 //GCEA_PERFCOUNTER1_CFG
10682 #define GCEA_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                                0x0
10683 #define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                            0x8
10684 #define GCEA_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                               0x18
10685 #define GCEA_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                  0x1c
10686 #define GCEA_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                   0x1d
10687 #define GCEA_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                  0x000000FFL
10688 #define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                              0x0000FF00L
10689 #define GCEA_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                 0x0F000000L
10690 #define GCEA_PERFCOUNTER1_CFG__ENABLE_MASK                                                                    0x10000000L
10691 #define GCEA_PERFCOUNTER1_CFG__CLEAR_MASK                                                                     0x20000000L
10692 //GCEA_PERFCOUNTER_RSLT_CNTL
10693 #define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                                0x0
10694 #define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                      0x8
10695 #define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                       0x10
10696 #define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                         0x18
10697 #define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                          0x19
10698 #define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                               0x1a
10699 #define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                  0x0000000FL
10700 #define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                        0x0000FF00L
10701 #define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                         0x00FF0000L
10702 #define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                           0x01000000L
10703 #define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                            0x02000000L
10704 #define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                 0x04000000L
10705 //GCEA_EDC_CNT
10706 #define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT                                                          0x0
10707 #define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT                                                          0x2
10708 #define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT                                                          0x4
10709 #define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT                                                          0x6
10710 #define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT                                                         0x8
10711 #define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT                                                         0xa
10712 #define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT                                                            0xc
10713 #define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT                                                            0xe
10714 #define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT                                                            0x10
10715 #define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT                                                            0x12
10716 #define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT                                                         0x14
10717 #define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT                                                         0x16
10718 #define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT                                                            0x18
10719 #define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT                                                            0x1a
10720 #define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT                                                           0x1c
10721 #define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK                                                            0x00000003L
10722 #define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK                                                            0x0000000CL
10723 #define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK                                                            0x00000030L
10724 #define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK                                                            0x000000C0L
10725 #define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK                                                           0x00000300L
10726 #define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK                                                           0x00000C00L
10727 #define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK                                                              0x00003000L
10728 #define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK                                                              0x0000C000L
10729 #define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK                                                              0x00030000L
10730 #define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK                                                              0x000C0000L
10731 #define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK                                                           0x00300000L
10732 #define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK                                                           0x00C00000L
10733 #define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK                                                              0x03000000L
10734 #define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK                                                              0x0C000000L
10735 #define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK                                                             0x30000000L
10736 //GCEA_EDC_CNT2
10737 #define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT                                                          0x0
10738 #define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT                                                          0x2
10739 #define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT                                                          0x4
10740 #define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT                                                          0x6
10741 #define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT                                                         0x8
10742 #define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT                                                         0xa
10743 #define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT                                                         0xc
10744 #define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT                                                         0xe
10745 #define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK                                                            0x00000003L
10746 #define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK                                                            0x0000000CL
10747 #define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK                                                            0x00000030L
10748 #define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK                                                            0x000000C0L
10749 #define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK                                                           0x00000300L
10750 #define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK                                                           0x00000C00L
10751 #define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK                                                           0x00003000L
10752 #define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK                                                           0x0000C000L
10753 //GCEA_DSM_CNTL
10754 #define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x0
10755 #define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x2
10756 #define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x3
10757 #define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x5
10758 #define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x6
10759 #define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x8
10760 #define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                  0x9
10761 #define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                 0xb
10762 #define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                  0xc
10763 #define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                 0xe
10764 #define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0xf
10765 #define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0x11
10766 #define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0x12
10767 #define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0x14
10768 #define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x15
10769 #define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x17
10770 #define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00000003L
10771 #define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000004L
10772 #define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00000018L
10773 #define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000020L
10774 #define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x000000C0L
10775 #define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000100L
10776 #define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                    0x00000600L
10777 #define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                   0x00000800L
10778 #define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                    0x00003000L
10779 #define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                   0x00004000L
10780 #define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00018000L
10781 #define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00020000L
10782 #define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                   0x000C0000L
10783 #define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00100000L
10784 #define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00600000L
10785 #define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00800000L
10786 //GCEA_DSM_CNTLA
10787 #define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x0
10788 #define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x2
10789 #define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x3
10790 #define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x5
10791 #define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0x6
10792 #define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0x8
10793 #define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0x9
10794 #define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xb
10795 #define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                                0xc
10796 #define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0xe
10797 #define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                               0xf
10798 #define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x11
10799 #define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x12
10800 #define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x14
10801 #define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x00000003L
10802 #define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00000004L
10803 #define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x00000018L
10804 #define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00000020L
10805 #define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                   0x000000C0L
10806 #define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00000100L
10807 #define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00000600L
10808 #define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00000800L
10809 #define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00003000L
10810 #define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00004000L
10811 #define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00018000L
10812 #define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00020000L
10813 #define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                 0x000C0000L
10814 #define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00100000L
10815 //GCEA_DSM_CNTLB
10816 //GCEA_DSM_CNTL2
10817 #define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x0
10818 #define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x2
10819 #define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x3
10820 #define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x5
10821 #define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x6
10822 #define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0x8
10823 #define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                                0x9
10824 #define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                                0xb
10825 #define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                                0xc
10826 #define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                                0xe
10827 #define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                               0xf
10828 #define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                               0x11
10829 #define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                               0x12
10830 #define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                               0x14
10831 #define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x15
10832 #define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                              0x17
10833 #define GCEA_DSM_CNTL2__INJECT_DELAY__SHIFT                                                                   0x1a
10834 #define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00000003L
10835 #define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000004L
10836 #define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00000018L
10837 #define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000020L
10838 #define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x000000C0L
10839 #define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00000100L
10840 #define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                  0x00000600L
10841 #define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                  0x00000800L
10842 #define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                  0x00003000L
10843 #define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                  0x00004000L
10844 #define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00018000L
10845 #define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                 0x00020000L
10846 #define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                 0x000C0000L
10847 #define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                 0x00100000L
10848 #define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                                0x00600000L
10849 #define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                                0x00800000L
10850 #define GCEA_DSM_CNTL2__INJECT_DELAY_MASK                                                                     0xFC000000L
10851 //GCEA_DSM_CNTL2A
10852 #define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x0
10853 #define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x2
10854 #define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x3
10855 #define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x5
10856 #define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                               0x6
10857 #define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                               0x8
10858 #define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                               0x9
10859 #define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                               0xb
10860 #define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                              0xc
10861 #define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                              0xe
10862 #define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                             0xf
10863 #define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                             0x11
10864 #define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x12
10865 #define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                             0x14
10866 #define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x00000003L
10867 #define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00000004L
10868 #define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x00000018L
10869 #define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00000020L
10870 #define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                 0x000000C0L
10871 #define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                 0x00000100L
10872 #define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00000600L
10873 #define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                 0x00000800L
10874 #define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                                0x00003000L
10875 #define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                                0x00004000L
10876 #define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                               0x00018000L
10877 #define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                               0x00020000L
10878 #define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                               0x000C0000L
10879 #define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                               0x00100000L
10880 //GCEA_DSM_CNTL2B
10881 //GCEA_GL2C_XBR_CREDITS
10882 #define GCEA_GL2C_XBR_CREDITS__DRAM_RD_LIMIT__SHIFT                                                           0x0
10883 #define GCEA_GL2C_XBR_CREDITS__DRAM_RD_RESERVE__SHIFT                                                         0x6
10884 #define GCEA_GL2C_XBR_CREDITS__IO_RD_LIMIT__SHIFT                                                             0x8
10885 #define GCEA_GL2C_XBR_CREDITS__IO_RD_RESERVE__SHIFT                                                           0xe
10886 #define GCEA_GL2C_XBR_CREDITS__DRAM_WR_LIMIT__SHIFT                                                           0x10
10887 #define GCEA_GL2C_XBR_CREDITS__DRAM_WR_RESERVE__SHIFT                                                         0x16
10888 #define GCEA_GL2C_XBR_CREDITS__IO_WR_LIMIT__SHIFT                                                             0x18
10889 #define GCEA_GL2C_XBR_CREDITS__IO_WR_RESERVE__SHIFT                                                           0x1e
10890 #define GCEA_GL2C_XBR_CREDITS__DRAM_RD_LIMIT_MASK                                                             0x0000003FL
10891 #define GCEA_GL2C_XBR_CREDITS__DRAM_RD_RESERVE_MASK                                                           0x000000C0L
10892 #define GCEA_GL2C_XBR_CREDITS__IO_RD_LIMIT_MASK                                                               0x00003F00L
10893 #define GCEA_GL2C_XBR_CREDITS__IO_RD_RESERVE_MASK                                                             0x0000C000L
10894 #define GCEA_GL2C_XBR_CREDITS__DRAM_WR_LIMIT_MASK                                                             0x003F0000L
10895 #define GCEA_GL2C_XBR_CREDITS__DRAM_WR_RESERVE_MASK                                                           0x00C00000L
10896 #define GCEA_GL2C_XBR_CREDITS__IO_WR_LIMIT_MASK                                                               0x3F000000L
10897 #define GCEA_GL2C_XBR_CREDITS__IO_WR_RESERVE_MASK                                                             0xC0000000L
10898 //GCEA_GL2C_XBR_MAXBURST
10899 #define GCEA_GL2C_XBR_MAXBURST__DRAM_RD__SHIFT                                                                0x0
10900 #define GCEA_GL2C_XBR_MAXBURST__IO_RD__SHIFT                                                                  0x4
10901 #define GCEA_GL2C_XBR_MAXBURST__DRAM_WR__SHIFT                                                                0x8
10902 #define GCEA_GL2C_XBR_MAXBURST__IO_WR__SHIFT                                                                  0xc
10903 #define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_FLUSH_TIMER__SHIFT                                               0x10
10904 #define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_SAME64B_ONLY__SHIFT                                              0x13
10905 #define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_FLUSH_TIMER__SHIFT                                               0x14
10906 #define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_SAME64B_ONLY__SHIFT                                              0x17
10907 #define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_MASK                                                                  0x0000000FL
10908 #define GCEA_GL2C_XBR_MAXBURST__IO_RD_MASK                                                                    0x000000F0L
10909 #define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_MASK                                                                  0x00000F00L
10910 #define GCEA_GL2C_XBR_MAXBURST__IO_WR_MASK                                                                    0x0000F000L
10911 #define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_FLUSH_TIMER_MASK                                                 0x00070000L
10912 #define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_SAME64B_ONLY_MASK                                                0x00080000L
10913 #define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_FLUSH_TIMER_MASK                                                 0x00700000L
10914 #define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_SAME64B_ONLY_MASK                                                0x00800000L
10915 //GCEA_PROBE_CNTL
10916 #define GCEA_PROBE_CNTL__REQ2RSP_DELAY__SHIFT                                                                 0x0
10917 #define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE__SHIFT                                                            0x5
10918 #define GCEA_PROBE_CNTL__REQ2RSP_DELAY_MASK                                                                   0x0000001FL
10919 #define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE_MASK                                                              0x00000020L
10920 //GCEA_PROBE_MAP
10921 #define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTGL2C__SHIFT                                                           0x0
10922 #define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTGL2C__SHIFT                                                           0x1
10923 #define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTGL2C__SHIFT                                                           0x2
10924 #define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTGL2C__SHIFT                                                           0x3
10925 #define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTGL2C__SHIFT                                                           0x4
10926 #define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTGL2C__SHIFT                                                           0x5
10927 #define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTGL2C__SHIFT                                                           0x6
10928 #define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTGL2C__SHIFT                                                           0x7
10929 #define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTGL2C__SHIFT                                                           0x8
10930 #define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTGL2C__SHIFT                                                           0x9
10931 #define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTGL2C__SHIFT                                                          0xa
10932 #define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTGL2C__SHIFT                                                          0xb
10933 #define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTGL2C__SHIFT                                                          0xc
10934 #define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTGL2C__SHIFT                                                          0xd
10935 #define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTGL2C__SHIFT                                                          0xe
10936 #define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTGL2C__SHIFT                                                          0xf
10937 #define GCEA_PROBE_MAP__INTLV_SIZE__SHIFT                                                                     0x10
10938 #define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTGL2C_MASK                                                             0x00000001L
10939 #define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTGL2C_MASK                                                             0x00000002L
10940 #define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTGL2C_MASK                                                             0x00000004L
10941 #define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTGL2C_MASK                                                             0x00000008L
10942 #define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTGL2C_MASK                                                             0x00000010L
10943 #define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTGL2C_MASK                                                             0x00000020L
10944 #define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTGL2C_MASK                                                             0x00000040L
10945 #define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTGL2C_MASK                                                             0x00000080L
10946 #define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTGL2C_MASK                                                             0x00000100L
10947 #define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTGL2C_MASK                                                             0x00000200L
10948 #define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTGL2C_MASK                                                            0x00000400L
10949 #define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTGL2C_MASK                                                            0x00000800L
10950 #define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTGL2C_MASK                                                            0x00001000L
10951 #define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTGL2C_MASK                                                            0x00002000L
10952 #define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTGL2C_MASK                                                            0x00004000L
10953 #define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTGL2C_MASK                                                            0x00008000L
10954 #define GCEA_PROBE_MAP__INTLV_SIZE_MASK                                                                       0x00030000L
10955 //GCEA_ERR_STATUS
10956 #define GCEA_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT                                                              0x0
10957 #define GCEA_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT                                                              0x4
10958 #define GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT                                                          0x8
10959 #define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT                                                    0xa
10960 #define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT                                                            0xb
10961 #define GCEA_ERR_STATUS__BUSY_ON_ERROR__SHIFT                                                                 0xc
10962 #define GCEA_ERR_STATUS__FUE_FLAG__SHIFT                                                                      0xd
10963 #define GCEA_ERR_STATUS__SDP_RDRSP_STATUS_MASK                                                                0x0000000FL
10964 #define GCEA_ERR_STATUS__SDP_WRRSP_STATUS_MASK                                                                0x000000F0L
10965 #define GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK                                                            0x00000300L
10966 #define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK                                                      0x00000400L
10967 #define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS_MASK                                                              0x00000800L
10968 #define GCEA_ERR_STATUS__BUSY_ON_ERROR_MASK                                                                   0x00001000L
10969 #define GCEA_ERR_STATUS__FUE_FLAG_MASK                                                                        0x00002000L
10970 //GCEA_MISC2
10971 #define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT                                                           0x0
10972 #define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT                                                            0x1
10973 #define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT                                                        0x2
10974 #define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT                                                         0x7
10975 #define GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT                                                            0xc
10976 #define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK                                                             0x00000001L
10977 #define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK                                                              0x00000002L
10978 #define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK                                                          0x0000007CL
10979 #define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK                                                           0x00000F80L
10980 #define GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK                                                              0x00001000L
10981 
10982 
10983 // addressBlock: gc_spipdec2
10984 //SPI_PQEV_CTRL
10985 #define SPI_PQEV_CTRL__SCAN_PERIOD__SHIFT                                                                     0x0
10986 #define SPI_PQEV_CTRL__QUEUE_DURATION__SHIFT                                                                  0xa
10987 #define SPI_PQEV_CTRL__COMPUTE_PIPE_EN__SHIFT                                                                 0x10
10988 #define SPI_PQEV_CTRL__SCAN_PERIOD_MASK                                                                       0x000003FFL
10989 #define SPI_PQEV_CTRL__QUEUE_DURATION_MASK                                                                    0x0000FC00L
10990 #define SPI_PQEV_CTRL__COMPUTE_PIPE_EN_MASK                                                                   0x00FF0000L
10991 //SPI_SYS_COMPUTE
10992 #define SPI_SYS_COMPUTE__PIPE__SHIFT                                                                          0x0
10993 #define SPI_SYS_COMPUTE__PIPE_MASK                                                                            0x000000FFL
10994 //SPI_SYS_WIF_CNTL
10995 #define SPI_SYS_WIF_CNTL__THRESHOLD__SHIFT                                                                    0x0
10996 #define SPI_SYS_WIF_CNTL__THRESHOLD_MASK                                                                      0x000000FFL
10997 
10998 
10999 // addressBlock: gc_gceadec3
11000 //GCEA_DRAM_BANK_ARB
11001 #define GCEA_DRAM_BANK_ARB__AGEBASED_BANKARB__SHIFT                                                           0x0
11002 #define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_CYCLIM__SHIFT                                                      0x1
11003 #define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_REQLIM__SHIFT                                                      0x8
11004 #define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_STALLMODE__SHIFT                                                   0xe
11005 #define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_RD_DECRATE__SHIFT                                                  0xf
11006 #define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_WR_DECRATE__SHIFT                                                  0x11
11007 #define GCEA_DRAM_BANK_ARB__AGEBASED_BANKARB_MASK                                                             0x00000001L
11008 #define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_CYCLIM_MASK                                                        0x000000FEL
11009 #define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_REQLIM_MASK                                                        0x00003F00L
11010 #define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_STALLMODE_MASK                                                     0x00004000L
11011 #define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_RD_DECRATE_MASK                                                    0x00018000L
11012 #define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_WR_DECRATE_MASK                                                    0x00060000L
11013 //GCEA_DRAM_BANK_ARB_RFSH
11014 #define GCEA_DRAM_BANK_ARB_RFSH__REFRESH_INTERVAL__SHIFT                                                      0x0
11015 #define GCEA_DRAM_BANK_ARB_RFSH__REFRESH_CYCLE__SHIFT                                                         0xc
11016 #define GCEA_DRAM_BANK_ARB_RFSH__REFRESH_P2B_ENABLE__SHIFT                                                    0x15
11017 #define GCEA_DRAM_BANK_ARB_RFSH__REFRESH_P2B_PAIRMSB__SHIFT                                                   0x16
11018 #define GCEA_DRAM_BANK_ARB_RFSH__REFRESH_INTERVAL_MASK                                                        0x00000FFFL
11019 #define GCEA_DRAM_BANK_ARB_RFSH__REFRESH_CYCLE_MASK                                                           0x001FF000L
11020 #define GCEA_DRAM_BANK_ARB_RFSH__REFRESH_P2B_ENABLE_MASK                                                      0x00200000L
11021 #define GCEA_DRAM_BANK_ARB_RFSH__REFRESH_P2B_PAIRMSB_MASK                                                     0x00400000L
11022 //GCEA_SDP_BACKDOOR_CMDCREDITS0
11023 #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC0_CREDITS_RECEIVED__SHIFT                                            0x0
11024 #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC1_CREDITS_RECEIVED__SHIFT                                            0x7
11025 #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC2_CREDITS_RECEIVED__SHIFT                                            0xe
11026 #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC3_CREDITS_RECEIVED__SHIFT                                            0x15
11027 #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC4_CREDITS_RECEIVED__SHIFT                                            0x1c
11028 #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC0_CREDITS_RECEIVED_MASK                                              0x0000007FL
11029 #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC1_CREDITS_RECEIVED_MASK                                              0x00003F80L
11030 #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC2_CREDITS_RECEIVED_MASK                                              0x001FC000L
11031 #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC3_CREDITS_RECEIVED_MASK                                              0x0FE00000L
11032 #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC4_CREDITS_RECEIVED_MASK                                              0xF0000000L
11033 //GCEA_SDP_BACKDOOR_CMDCREDITS1
11034 #define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC4_CREDITS_RECEIVED__SHIFT                                            0x0
11035 #define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC5_CREDITS_RECEIVED__SHIFT                                            0x3
11036 #define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC6_CREDITS_RECEIVED__SHIFT                                            0xa
11037 #define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC7_CREDITS_RECEIVED__SHIFT                                            0x11
11038 #define GCEA_SDP_BACKDOOR_CMDCREDITS1__POOL_CREDITS_RECEIVED__SHIFT                                           0x18
11039 #define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC4_CREDITS_RECEIVED_MASK                                              0x00000007L
11040 #define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC5_CREDITS_RECEIVED_MASK                                              0x000003F8L
11041 #define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC6_CREDITS_RECEIVED_MASK                                              0x0001FC00L
11042 #define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC7_CREDITS_RECEIVED_MASK                                              0x00FE0000L
11043 #define GCEA_SDP_BACKDOOR_CMDCREDITS1__POOL_CREDITS_RECEIVED_MASK                                             0x7F000000L
11044 //GCEA_SDP_BACKDOOR_DATACREDITS0
11045 #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC0_CREDITS_RECEIVED__SHIFT                                           0x0
11046 #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC1_CREDITS_RECEIVED__SHIFT                                           0x7
11047 #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC2_CREDITS_RECEIVED__SHIFT                                           0xe
11048 #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC3_CREDITS_RECEIVED__SHIFT                                           0x15
11049 #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC4_CREDITS_RECEIVED__SHIFT                                           0x1c
11050 #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC0_CREDITS_RECEIVED_MASK                                             0x0000007FL
11051 #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC1_CREDITS_RECEIVED_MASK                                             0x00003F80L
11052 #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC2_CREDITS_RECEIVED_MASK                                             0x001FC000L
11053 #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC3_CREDITS_RECEIVED_MASK                                             0x0FE00000L
11054 #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC4_CREDITS_RECEIVED_MASK                                             0xF0000000L
11055 //GCEA_SDP_BACKDOOR_DATACREDITS1
11056 #define GCEA_SDP_BACKDOOR_DATACREDITS1__VC4_CREDITS_RECEIVED__SHIFT                                           0x0
11057 #define GCEA_SDP_BACKDOOR_DATACREDITS1__VC5_CREDITS_RECEIVED__SHIFT                                           0x3
11058 #define GCEA_SDP_BACKDOOR_DATACREDITS1__VC6_CREDITS_RECEIVED__SHIFT                                           0xa
11059 #define GCEA_SDP_BACKDOOR_DATACREDITS1__VC7_CREDITS_RECEIVED__SHIFT                                           0x11
11060 #define GCEA_SDP_BACKDOOR_DATACREDITS1__POOL_CREDITS_RECEIVED__SHIFT                                          0x18
11061 #define GCEA_SDP_BACKDOOR_DATACREDITS1__VC4_CREDITS_RECEIVED_MASK                                             0x00000007L
11062 #define GCEA_SDP_BACKDOOR_DATACREDITS1__VC5_CREDITS_RECEIVED_MASK                                             0x000003F8L
11063 #define GCEA_SDP_BACKDOOR_DATACREDITS1__VC6_CREDITS_RECEIVED_MASK                                             0x0001FC00L
11064 #define GCEA_SDP_BACKDOOR_DATACREDITS1__VC7_CREDITS_RECEIVED_MASK                                             0x00FE0000L
11065 #define GCEA_SDP_BACKDOOR_DATACREDITS1__POOL_CREDITS_RECEIVED_MASK                                            0x7F000000L
11066 //GCEA_SDP_BACKDOOR_MISCCREDITS
11067 #define GCEA_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED__SHIFT                                          0x0
11068 #define GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED__SHIFT                                          0x8
11069 #define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED__SHIFT                                        0x10
11070 #define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED__SHIFT                                        0x17
11071 #define GCEA_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED_MASK                                            0x000000FFL
11072 #define GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED_MASK                                            0x0000FF00L
11073 #define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED_MASK                                          0x007F0000L
11074 #define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED_MASK                                          0x3F800000L
11075 //GCEA_ADDRDECDRAM_ADDR_HASH_PACH
11076 #define GCEA_ADDRDECDRAM_ADDR_HASH_PACH__XOR_ENABLE__SHIFT                                                    0x0
11077 #define GCEA_ADDRDECDRAM_ADDR_HASH_PACH__NA_XOR__SHIFT                                                        0x1
11078 #define GCEA_ADDRDECDRAM_ADDR_HASH_PACH__XOR_ENABLE_MASK                                                      0x00000001L
11079 #define GCEA_ADDRDECDRAM_ADDR_HASH_PACH__NA_XOR_MASK                                                          0xFFFFFFFEL
11080 //GCEA_RRET_MEM_RESERVE
11081 #define GCEA_RRET_MEM_RESERVE__VC0__SHIFT                                                                     0x0
11082 #define GCEA_RRET_MEM_RESERVE__VC1__SHIFT                                                                     0x4
11083 #define GCEA_RRET_MEM_RESERVE__VC2__SHIFT                                                                     0x8
11084 #define GCEA_RRET_MEM_RESERVE__VC3__SHIFT                                                                     0xc
11085 #define GCEA_RRET_MEM_RESERVE__VC4__SHIFT                                                                     0x10
11086 #define GCEA_RRET_MEM_RESERVE__VC5__SHIFT                                                                     0x14
11087 #define GCEA_RRET_MEM_RESERVE__VC6__SHIFT                                                                     0x18
11088 #define GCEA_RRET_MEM_RESERVE__VC7__SHIFT                                                                     0x1c
11089 #define GCEA_RRET_MEM_RESERVE__VC0_MASK                                                                       0x0000000FL
11090 #define GCEA_RRET_MEM_RESERVE__VC1_MASK                                                                       0x000000F0L
11091 #define GCEA_RRET_MEM_RESERVE__VC2_MASK                                                                       0x00000F00L
11092 #define GCEA_RRET_MEM_RESERVE__VC3_MASK                                                                       0x0000F000L
11093 #define GCEA_RRET_MEM_RESERVE__VC4_MASK                                                                       0x000F0000L
11094 #define GCEA_RRET_MEM_RESERVE__VC5_MASK                                                                       0x00F00000L
11095 #define GCEA_RRET_MEM_RESERVE__VC6_MASK                                                                       0x0F000000L
11096 #define GCEA_RRET_MEM_RESERVE__VC7_MASK                                                                       0xF0000000L
11097 //GCEA_ADDRDEC_SELECT
11098 #define GCEA_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT                                                0x0
11099 #define GCEA_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT                                                  0x5
11100 #define GCEA_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT                                                 0xa
11101 #define GCEA_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT                                                   0xf
11102 #define GCEA_ADDRDEC_SELECT__DRAM_GECC_ENABLE__SHIFT                                                          0x14
11103 #define GCEA_ADDRDEC_SELECT__GMI_GECC_ENABLE__SHIFT                                                           0x15
11104 #define GCEA_ADDRDEC_SELECT__DRAM_SKIP_MSB__SHIFT                                                             0x16
11105 #define GCEA_ADDRDEC_SELECT__GMI_SKIP_MSB__SHIFT                                                              0x17
11106 #define GCEA_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK                                                  0x0000001FL
11107 #define GCEA_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK                                                    0x000003E0L
11108 #define GCEA_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK                                                   0x00007C00L
11109 #define GCEA_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK                                                     0x000F8000L
11110 #define GCEA_ADDRDEC_SELECT__DRAM_GECC_ENABLE_MASK                                                            0x00100000L
11111 #define GCEA_ADDRDEC_SELECT__GMI_GECC_ENABLE_MASK                                                             0x00200000L
11112 #define GCEA_ADDRDEC_SELECT__DRAM_SKIP_MSB_MASK                                                               0x00400000L
11113 #define GCEA_ADDRDEC_SELECT__GMI_SKIP_MSB_MASK                                                                0x00800000L
11114 //GCEA_SDP_ENABLE
11115 #define GCEA_SDP_ENABLE__ENABLE__SHIFT                                                                        0x0
11116 #define GCEA_SDP_ENABLE__ENABLE_MASK                                                                          0x00000001L
11117 
11118 
11119 // addressBlock: gc_rmi_rmidec
11120 //RMI_GENERAL_CNTL
11121 #define RMI_GENERAL_CNTL__BURST_DISABLE__SHIFT                                                                0x0
11122 #define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE__SHIFT                                                           0x1
11123 #define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG__SHIFT                                                              0x11
11124 #define RMI_GENERAL_CNTL__RB0_HARVEST_EN__SHIFT                                                               0x13
11125 #define RMI_GENERAL_CNTL__RB1_HARVEST_EN__SHIFT                                                               0x14
11126 #define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE__SHIFT                                                     0x15
11127 #define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE__SHIFT                                                       0x19
11128 #define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK__SHIFT                                              0x1a
11129 #define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK__SHIFT                                             0x1b
11130 #define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK__SHIFT                                              0x1c
11131 #define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK__SHIFT                                             0x1d
11132 #define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK__SHIFT                                       0x1e
11133 #define RMI_GENERAL_CNTL__BURST_DISABLE_MASK                                                                  0x00000001L
11134 #define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE_MASK                                                             0x0001FFFEL
11135 #define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_MASK                                                                0x00060000L
11136 #define RMI_GENERAL_CNTL__RB0_HARVEST_EN_MASK                                                                 0x00080000L
11137 #define RMI_GENERAL_CNTL__RB1_HARVEST_EN_MASK                                                                 0x00100000L
11138 #define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE_MASK                                                       0x01E00000L
11139 #define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE_MASK                                                         0x02000000L
11140 #define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK_MASK                                                0x04000000L
11141 #define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK_MASK                                               0x08000000L
11142 #define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK_MASK                                                0x10000000L
11143 #define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK_MASK                                               0x20000000L
11144 #define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK_MASK                                         0x40000000L
11145 //RMI_GENERAL_CNTL1
11146 #define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE__SHIFT                                                0x0
11147 #define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE__SHIFT                                                     0x4
11148 #define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE__SHIFT                                                     0x6
11149 #define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK__SHIFT                                            0x8
11150 #define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE__SHIFT                                                       0x9
11151 #define RMI_GENERAL_CNTL1__POLICY_OVERRIDE__SHIFT                                                             0xb
11152 #define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN__SHIFT                                           0xc
11153 #define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN__SHIFT                                           0xd
11154 #define RMI_GENERAL_CNTL1__ARBITER_ADDRESS_CHANGE_ENABLE__SHIFT                                               0xe
11155 #define RMI_GENERAL_CNTL1__LAST_OF_BURST_INSERTION_DISABLE__SHIFT                                             0xf
11156 #define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE_MASK                                                  0x0000000FL
11157 #define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE_MASK                                                       0x00000030L
11158 #define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE_MASK                                                       0x000000C0L
11159 #define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK_MASK                                              0x00000100L
11160 #define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE_MASK                                                         0x00000600L
11161 #define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_MASK                                                               0x00000800L
11162 #define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN_MASK                                             0x00001000L
11163 #define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN_MASK                                             0x00002000L
11164 #define RMI_GENERAL_CNTL1__ARBITER_ADDRESS_CHANGE_ENABLE_MASK                                                 0x00004000L
11165 #define RMI_GENERAL_CNTL1__LAST_OF_BURST_INSERTION_DISABLE_MASK                                               0x00008000L
11166 //RMI_GENERAL_STATUS
11167 #define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED__SHIFT                                                0x0
11168 #define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR__SHIFT                                                 0x1
11169 #define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR__SHIFT                                                0x2
11170 #define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR__SHIFT                                                 0x3
11171 #define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR__SHIFT                                                0x4
11172 #define RMI_GENERAL_STATUS__RMI_XBAR_BUSY__SHIFT                                                              0x5
11173 #define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY__SHIFT                                                             0x6
11174 #define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY__SHIFT                                                        0x7
11175 #define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY__SHIFT                                                        0x8
11176 #define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY__SHIFT                                                           0x9
11177 #define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT                                                       0xa
11178 #define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY__SHIFT                                                 0xb
11179 #define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY__SHIFT                                                 0xc
11180 #define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY__SHIFT                                                        0xd
11181 #define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY__SHIFT                                                           0xe
11182 #define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY__SHIFT                                                       0xf
11183 #define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY__SHIFT                                                 0x10
11184 #define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY__SHIFT                                                 0x11
11185 #define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY__SHIFT                                                            0x12
11186 #define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY__SHIFT                                                            0x13
11187 #define RMI_GENERAL_STATUS__RMI_XNACK_BUSY__SHIFT                                                             0x14
11188 #define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED__SHIFT                                                        0x15
11189 #define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY__SHIFT                                                           0x1d
11190 #define RMI_GENERAL_STATUS__XNACK_FIFO_FULL__SHIFT                                                            0x1e
11191 #define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR__SHIFT                                          0x1f
11192 #define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED_MASK                                                  0x00000001L
11193 #define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR_MASK                                                   0x00000002L
11194 #define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR_MASK                                                  0x00000004L
11195 #define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR_MASK                                                   0x00000008L
11196 #define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR_MASK                                                  0x00000010L
11197 #define RMI_GENERAL_STATUS__RMI_XBAR_BUSY_MASK                                                                0x00000020L
11198 #define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY_MASK                                                               0x00000040L
11199 #define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY_MASK                                                          0x00000080L
11200 #define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY_MASK                                                          0x00000100L
11201 #define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY_MASK                                                             0x00000200L
11202 #define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY_MASK                                                         0x00000400L
11203 #define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY_MASK                                                   0x00000800L
11204 #define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY_MASK                                                   0x00001000L
11205 #define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY_MASK                                                          0x00002000L
11206 #define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY_MASK                                                             0x00004000L
11207 #define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY_MASK                                                         0x00008000L
11208 #define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY_MASK                                                   0x00010000L
11209 #define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY_MASK                                                   0x00020000L
11210 #define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY_MASK                                                              0x00040000L
11211 #define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY_MASK                                                              0x00080000L
11212 #define RMI_GENERAL_STATUS__RMI_XNACK_BUSY_MASK                                                               0x00100000L
11213 #define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED_MASK                                                          0x1FE00000L
11214 #define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY_MASK                                                             0x20000000L
11215 #define RMI_GENERAL_STATUS__XNACK_FIFO_FULL_MASK                                                              0x40000000L
11216 #define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK                                            0x80000000L
11217 //RMI_SUBBLOCK_STATUS0
11218 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0__SHIFT                                     0x0
11219 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0__SHIFT                                         0x7
11220 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0__SHIFT                                        0x8
11221 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1__SHIFT                                     0x9
11222 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1__SHIFT                                         0x10
11223 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1__SHIFT                                        0x11
11224 #define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT__SHIFT                                                       0x12
11225 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0_MASK                                       0x0000007FL
11226 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0_MASK                                           0x00000080L
11227 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0_MASK                                          0x00000100L
11228 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1_MASK                                       0x0000FE00L
11229 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1_MASK                                           0x00010000L
11230 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1_MASK                                          0x00020000L
11231 #define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT_MASK                                                         0x0FFC0000L
11232 //RMI_SUBBLOCK_STATUS1
11233 #define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE__SHIFT                                                   0x0
11234 #define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT                                                   0xa
11235 #define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT__SHIFT                                                       0x14
11236 #define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE_MASK                                                     0x000003FFL
11237 #define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE_MASK                                                     0x000FFC00L
11238 #define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT_MASK                                                         0x3FF00000L
11239 //RMI_SUBBLOCK_STATUS2
11240 #define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED__SHIFT                                                      0x0
11241 #define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED__SHIFT                                                      0x9
11242 #define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED_MASK                                                        0x000001FFL
11243 #define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED_MASK                                                        0x0003FE00L
11244 //RMI_SUBBLOCK_STATUS3
11245 #define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL__SHIFT                                             0x0
11246 #define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT                                             0xa
11247 #define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL_MASK                                               0x000003FFL
11248 #define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL_MASK                                               0x000FFC00L
11249 //RMI_XBAR_CONFIG
11250 #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE__SHIFT                                                      0x0
11251 #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE__SHIFT                                             0x2
11252 #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE__SHIFT                                                0x6
11253 #define RMI_XBAR_CONFIG__ARBITER_DIS__SHIFT                                                                   0x7
11254 #define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ__SHIFT                                                                0x8
11255 #define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE__SHIFT                                                       0xc
11256 #define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0__SHIFT                                                                0xd
11257 #define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1__SHIFT                                                                0xe
11258 #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE_MASK                                                        0x00000003L
11259 #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE_MASK                                               0x0000003CL
11260 #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE_MASK                                                  0x00000040L
11261 #define RMI_XBAR_CONFIG__ARBITER_DIS_MASK                                                                     0x00000080L
11262 #define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_MASK                                                                  0x00000F00L
11263 #define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE_MASK                                                         0x00001000L
11264 #define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0_MASK                                                                  0x00002000L
11265 #define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1_MASK                                                                  0x00004000L
11266 //RMI_PROBE_POP_LOGIC_CNTL
11267 #define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH__SHIFT                                             0x0
11268 #define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS__SHIFT                                                    0x7
11269 #define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2__SHIFT                                      0x8
11270 #define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT                                             0xa
11271 #define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS__SHIFT                                                    0x11
11272 #define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH_MASK                                               0x0000007FL
11273 #define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS_MASK                                                      0x00000080L
11274 #define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2_MASK                                        0x00000300L
11275 #define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH_MASK                                               0x0001FC00L
11276 #define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS_MASK                                                      0x00020000L
11277 //RMI_UTC_XNACK_N_MISC_CNTL
11278 #define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC__SHIFT                                              0x0
11279 #define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE__SHIFT                                         0x8
11280 #define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE__SHIFT                                                     0xc
11281 #define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE__SHIFT                                       0xd
11282 #define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC_MASK                                                0x000000FFL
11283 #define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE_MASK                                           0x00000F00L
11284 #define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE_MASK                                                       0x00001000L
11285 #define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE_MASK                                         0x00002000L
11286 //RMI_DEMUX_CNTL
11287 #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL__SHIFT                                                               0x0
11288 #define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT                                                 0x1
11289 #define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_OVERRIDE_EN__SHIFT                                                    0x2
11290 #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE__SHIFT                                                0x4
11291 #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE__SHIFT                                             0x6
11292 #define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE__SHIFT                                                                0xe
11293 #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL__SHIFT                                                               0x10
11294 #define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT                                                 0x11
11295 #define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_OVERRIDE_EN__SHIFT                                                    0x12
11296 #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE__SHIFT                                                0x14
11297 #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE__SHIFT                                             0x16
11298 #define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE__SHIFT                                                                0x1e
11299 #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_MASK                                                                 0x00000001L
11300 #define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN_MASK                                                   0x00000002L
11301 #define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_OVERRIDE_EN_MASK                                                      0x00000004L
11302 #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE_MASK                                                  0x00000030L
11303 #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE_MASK                                               0x00003FC0L
11304 #define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_MASK                                                                  0x0000C000L
11305 #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_MASK                                                                 0x00010000L
11306 #define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN_MASK                                                   0x00020000L
11307 #define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_OVERRIDE_EN_MASK                                                      0x00040000L
11308 #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE_MASK                                                  0x00300000L
11309 #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE_MASK                                               0x3FC00000L
11310 #define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_MASK                                                                  0xC0000000L
11311 //RMI_UTCL1_CNTL1
11312 #define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT                                                              0x0
11313 #define RMI_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT                                                                 0x1
11314 #define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT                                                               0x2
11315 #define RMI_UTCL1_CNTL1__RESP_MODE__SHIFT                                                                     0x3
11316 #define RMI_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT                                                               0x5
11317 #define RMI_UTCL1_CNTL1__CLIENTID__SHIFT                                                                      0x7
11318 #define RMI_UTCL1_CNTL1__USERVM_DIS__SHIFT                                                                    0x10
11319 #define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT                                                             0x11
11320 #define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT                                                          0x12
11321 #define RMI_UTCL1_CNTL1__REG_INV_VMID__SHIFT                                                                  0x13
11322 #define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT                                                              0x17
11323 #define RMI_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT                                                                0x18
11324 #define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT                                                    0x19
11325 #define RMI_UTCL1_CNTL1__FORCE_MISS__SHIFT                                                                    0x1a
11326 #define RMI_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT                                                                0x1b
11327 #define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT                                                        0x1c
11328 #define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT                                                        0x1e
11329 #define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK                                                                0x00000001L
11330 #define RMI_UTCL1_CNTL1__GPUVM_64K_DEF_MASK                                                                   0x00000002L
11331 #define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK                                                                 0x00000004L
11332 #define RMI_UTCL1_CNTL1__RESP_MODE_MASK                                                                       0x00000018L
11333 #define RMI_UTCL1_CNTL1__RESP_FAULT_MODE_MASK                                                                 0x00000060L
11334 #define RMI_UTCL1_CNTL1__CLIENTID_MASK                                                                        0x0000FF80L
11335 #define RMI_UTCL1_CNTL1__USERVM_DIS_MASK                                                                      0x00010000L
11336 #define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK                                                               0x00020000L
11337 #define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK                                                            0x00040000L
11338 #define RMI_UTCL1_CNTL1__REG_INV_VMID_MASK                                                                    0x00780000L
11339 #define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK                                                                0x00800000L
11340 #define RMI_UTCL1_CNTL1__REG_INV_TOGGLE_MASK                                                                  0x01000000L
11341 #define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK                                                      0x02000000L
11342 #define RMI_UTCL1_CNTL1__FORCE_MISS_MASK                                                                      0x04000000L
11343 #define RMI_UTCL1_CNTL1__FORCE_IN_ORDER_MASK                                                                  0x08000000L
11344 #define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK                                                          0x30000000L
11345 #define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK                                                          0xC0000000L
11346 //RMI_UTCL1_CNTL2
11347 #define RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT                                                                     0x0
11348 #define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT                                                                0x9
11349 #define RMI_UTCL1_CNTL2__LINE_VALID__SHIFT                                                                    0xa
11350 #define RMI_UTCL1_CNTL2__DIS_EDC__SHIFT                                                                       0xb
11351 #define RMI_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT                                                                0xc
11352 #define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT                                                                 0xd
11353 #define RMI_UTCL1_CNTL2__FORCE_SNOOP__SHIFT                                                                   0xe
11354 #define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT                                                           0xf
11355 #define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE__SHIFT                                                          0x10
11356 #define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR__SHIFT                                                 0x12
11357 #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR__SHIFT                                                        0x13
11358 #define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID__SHIFT                                                  0x14
11359 #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID__SHIFT                                                         0x15
11360 #define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ__SHIFT                                                         0x19
11361 #define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K__SHIFT                                                    0x1a
11362 #define RMI_UTCL1_CNTL2__PERM_MODE_OVRD__SHIFT                                                                0x1b
11363 #define RMI_UTCL1_CNTL2__LINE_INVALIDATE_OPT__SHIFT                                                           0x1c
11364 #define RMI_UTCL1_CNTL2__GPUVM_16K_DEFAULT__SHIFT                                                             0x1d
11365 #define RMI_UTCL1_CNTL2__UTC_SPARE_MASK                                                                       0x000000FFL
11366 #define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK                                                                  0x00000200L
11367 #define RMI_UTCL1_CNTL2__LINE_VALID_MASK                                                                      0x00000400L
11368 #define RMI_UTCL1_CNTL2__DIS_EDC_MASK                                                                         0x00000800L
11369 #define RMI_UTCL1_CNTL2__GPUVM_INV_MODE_MASK                                                                  0x00001000L
11370 #define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK                                                                   0x00002000L
11371 #define RMI_UTCL1_CNTL2__FORCE_SNOOP_MASK                                                                     0x00004000L
11372 #define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK                                                             0x00008000L
11373 #define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE_MASK                                                            0x00030000L
11374 #define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR_MASK                                                   0x00040000L
11375 #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK                                                          0x00080000L
11376 #define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID_MASK                                                    0x00100000L
11377 #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID_MASK                                                           0x01E00000L
11378 #define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ_MASK                                                           0x02000000L
11379 #define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K_MASK                                                      0x04000000L
11380 #define RMI_UTCL1_CNTL2__PERM_MODE_OVRD_MASK                                                                  0x08000000L
11381 #define RMI_UTCL1_CNTL2__LINE_INVALIDATE_OPT_MASK                                                             0x10000000L
11382 #define RMI_UTCL1_CNTL2__GPUVM_16K_DEFAULT_MASK                                                               0x20000000L
11383 //RMI_TCIW_FORMATTER0_CNTL
11384 #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE__SHIFT                                             0x0
11385 #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW__SHIFT                                          0x1
11386 #define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ__SHIFT                                       0x9
11387 #define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA__SHIFT                                         0x13
11388 #define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE__SHIFT                                  0x1b
11389 #define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE__SHIFT                                                  0x1c
11390 #define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS__SHIFT                                                  0x1d
11391 #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST__SHIFT                                     0x1e
11392 #define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA__SHIFT                                                  0x1f
11393 #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE_MASK                                               0x00000001L
11394 #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW_MASK                                            0x000001FEL
11395 #define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ_MASK                                         0x0007FE00L
11396 #define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_MASK                                           0x07F80000L
11397 #define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE_MASK                                    0x08000000L
11398 #define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE_MASK                                                    0x10000000L
11399 #define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS_MASK                                                    0x20000000L
11400 #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST_MASK                                       0x40000000L
11401 #define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA_MASK                                                    0x80000000L
11402 //RMI_TCIW_FORMATTER1_CNTL
11403 #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE__SHIFT                                             0x0
11404 #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW__SHIFT                                          0x1
11405 #define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ__SHIFT                                       0x9
11406 #define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA__SHIFT                                         0x13
11407 #define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE__SHIFT                                  0x1b
11408 #define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE__SHIFT                                                  0x1c
11409 #define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS__SHIFT                                                  0x1d
11410 #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST__SHIFT                                     0x1e
11411 #define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA__SHIFT                                                  0x1f
11412 #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE_MASK                                               0x00000001L
11413 #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW_MASK                                            0x000001FEL
11414 #define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ_MASK                                         0x0007FE00L
11415 #define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_MASK                                           0x07F80000L
11416 #define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE_MASK                                    0x08000000L
11417 #define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE_MASK                                                    0x10000000L
11418 #define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS_MASK                                                    0x20000000L
11419 #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST_MASK                                       0x40000000L
11420 #define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA_MASK                                                    0x80000000L
11421 //RMI_SCOREBOARD_CNTL
11422 #define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH__SHIFT                                                        0x0
11423 #define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0__SHIFT                                              0x1
11424 #define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH__SHIFT                                                        0x2
11425 #define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1__SHIFT                                              0x3
11426 #define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1__SHIFT                                                      0x4
11427 #define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN__SHIFT                                         0x5
11428 #define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE__SHIFT                                      0x6
11429 #define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0__SHIFT                                                      0x7
11430 #define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN__SHIFT                                                  0x8
11431 #define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE__SHIFT                                   0x9
11432 #define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH_MASK                                                          0x00000001L
11433 #define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0_MASK                                                0x00000002L
11434 #define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH_MASK                                                          0x00000004L
11435 #define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1_MASK                                                0x00000008L
11436 #define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1_MASK                                                        0x00000010L
11437 #define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN_MASK                                           0x00000020L
11438 #define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE_MASK                                        0x00000040L
11439 #define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0_MASK                                                        0x00000080L
11440 #define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN_MASK                                                    0x00000100L
11441 #define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE_MASK                                     0x001FFE00L
11442 //RMI_SCOREBOARD_STATUS0
11443 #define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID__SHIFT                                                     0x0
11444 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG__SHIFT                                                    0x1
11445 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID__SHIFT                                                   0x2
11446 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE__SHIFT                                                   0x12
11447 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE__SHIFT                                                       0x13
11448 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE__SHIFT                                                 0x14
11449 #define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE__SHIFT                                                    0x15
11450 #define RMI_SCOREBOARD_STATUS0__COUNTER_SELECT__SHIFT                                                         0x16
11451 #define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID_MASK                                                       0x00000001L
11452 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG_MASK                                                      0x00000002L
11453 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID_MASK                                                     0x0003FFFCL
11454 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE_MASK                                                     0x00040000L
11455 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE_MASK                                                         0x00080000L
11456 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE_MASK                                                   0x00100000L
11457 #define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE_MASK                                                      0x00200000L
11458 #define RMI_SCOREBOARD_STATUS0__COUNTER_SELECT_MASK                                                           0x07C00000L
11459 //RMI_SCOREBOARD_STATUS1
11460 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0__SHIFT                                                        0x0
11461 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0__SHIFT                                              0xc
11462 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0__SHIFT                                               0xd
11463 #define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED__SHIFT                                      0xe
11464 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1__SHIFT                                                        0xf
11465 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1__SHIFT                                              0x1b
11466 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1__SHIFT                                               0x1c
11467 #define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1__SHIFT                                                  0x1d
11468 #define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0__SHIFT                                                  0x1e
11469 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0_MASK                                                          0x00000FFFL
11470 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0_MASK                                                0x00001000L
11471 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0_MASK                                                 0x00002000L
11472 #define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED_MASK                                        0x00004000L
11473 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1_MASK                                                          0x07FF8000L
11474 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1_MASK                                                0x08000000L
11475 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1_MASK                                                 0x10000000L
11476 #define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1_MASK                                                    0x20000000L
11477 #define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0_MASK                                                    0x40000000L
11478 //RMI_SCOREBOARD_STATUS2
11479 #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0__SHIFT                                                       0x0
11480 #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0__SHIFT                                             0xc
11481 #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1__SHIFT                                                       0xd
11482 #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1__SHIFT                                             0x19
11483 #define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1__SHIFT                                                     0x1a
11484 #define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0__SHIFT                                                     0x1b
11485 #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0__SHIFT                                           0x1c
11486 #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1__SHIFT                                           0x1d
11487 #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0__SHIFT                                              0x1e
11488 #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1__SHIFT                                              0x1f
11489 #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0_MASK                                                         0x00000FFFL
11490 #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0_MASK                                               0x00001000L
11491 #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1_MASK                                                         0x01FFE000L
11492 #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1_MASK                                               0x02000000L
11493 #define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1_MASK                                                       0x04000000L
11494 #define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0_MASK                                                       0x08000000L
11495 #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0_MASK                                             0x10000000L
11496 #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1_MASK                                             0x20000000L
11497 #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0_MASK                                                0x40000000L
11498 #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1_MASK                                                0x80000000L
11499 //RMI_XBAR_ARBITER_CONFIG
11500 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE__SHIFT                                                        0x0
11501 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR__SHIFT                                     0x2
11502 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL__SHIFT                                                       0x3
11503 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT                                         0x4
11504 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_OVERRIDE_EN__SHIFT                                            0x5
11505 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE__SHIFT                                        0x6
11506 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE__SHIFT                                     0x8
11507 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE__SHIFT                                                        0x10
11508 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR__SHIFT                                     0x12
11509 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL__SHIFT                                                       0x13
11510 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT                                         0x14
11511 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_OVERRIDE_EN__SHIFT                                            0x15
11512 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE__SHIFT                                        0x16
11513 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE__SHIFT                                     0x18
11514 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_MASK                                                          0x00000003L
11515 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR_MASK                                       0x00000004L
11516 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_MASK                                                         0x00000008L
11517 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN_MASK                                           0x00000010L
11518 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_OVERRIDE_EN_MASK                                              0x00000020L
11519 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE_MASK                                          0x000000C0L
11520 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE_MASK                                       0x0000FF00L
11521 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_MASK                                                          0x00030000L
11522 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR_MASK                                       0x00040000L
11523 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_MASK                                                         0x00080000L
11524 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN_MASK                                           0x00100000L
11525 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_OVERRIDE_EN_MASK                                              0x00200000L
11526 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE_MASK                                          0x00C00000L
11527 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE_MASK                                       0xFF000000L
11528 //RMI_XBAR_ARBITER_CONFIG_1
11529 #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD__SHIFT                                  0x0
11530 #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR__SHIFT                                  0x8
11531 #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD__SHIFT                                  0x10
11532 #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR__SHIFT                                  0x18
11533 #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD_MASK                                    0x000000FFL
11534 #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR_MASK                                    0x0000FF00L
11535 #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD_MASK                                    0x00FF0000L
11536 #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR_MASK                                    0xFF000000L
11537 //RMI_CLOCK_CNTRL
11538 #define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK__SHIFT                                                         0x0
11539 #define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK__SHIFT                                                         0x5
11540 #define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT                                                       0xa
11541 #define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK__SHIFT                                                       0xf
11542 #define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK__SHIFT                                                         0x14
11543 #define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK__SHIFT                                                       0x19
11544 #define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK_MASK                                                           0x0000001FL
11545 #define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK_MASK                                                           0x000003E0L
11546 #define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK_MASK                                                         0x00007C00L
11547 #define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK_MASK                                                         0x000F8000L
11548 #define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK_MASK                                                           0x01F00000L
11549 #define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK_MASK                                                         0x3E000000L
11550 //RMI_UTCL1_STATUS
11551 #define RMI_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                               0x0
11552 #define RMI_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                               0x1
11553 #define RMI_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                 0x2
11554 #define RMI_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                 0x00000001L
11555 #define RMI_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                 0x00000002L
11556 #define RMI_UTCL1_STATUS__PRT_DETECTED_MASK                                                                   0x00000004L
11557 //RMI_RB_GLX_CID_MAP
11558 #define RMI_RB_GLX_CID_MAP__CB_COLOR_MAP__SHIFT                                                               0x0
11559 #define RMI_RB_GLX_CID_MAP__CB_FMASK_MAP__SHIFT                                                               0x4
11560 #define RMI_RB_GLX_CID_MAP__CB_CMASK_MAP__SHIFT                                                               0x8
11561 #define RMI_RB_GLX_CID_MAP__CB_DCC_MAP__SHIFT                                                                 0xc
11562 #define RMI_RB_GLX_CID_MAP__DB_Z_MAP__SHIFT                                                                   0x10
11563 #define RMI_RB_GLX_CID_MAP__DB_S_MAP__SHIFT                                                                   0x14
11564 #define RMI_RB_GLX_CID_MAP__DB_TILE_MAP__SHIFT                                                                0x18
11565 #define RMI_RB_GLX_CID_MAP__DB_ZPCPSD_MAP__SHIFT                                                              0x1c
11566 #define RMI_RB_GLX_CID_MAP__CB_COLOR_MAP_MASK                                                                 0x0000000FL
11567 #define RMI_RB_GLX_CID_MAP__CB_FMASK_MAP_MASK                                                                 0x000000F0L
11568 #define RMI_RB_GLX_CID_MAP__CB_CMASK_MAP_MASK                                                                 0x00000F00L
11569 #define RMI_RB_GLX_CID_MAP__CB_DCC_MAP_MASK                                                                   0x0000F000L
11570 #define RMI_RB_GLX_CID_MAP__DB_Z_MAP_MASK                                                                     0x000F0000L
11571 #define RMI_RB_GLX_CID_MAP__DB_S_MAP_MASK                                                                     0x00F00000L
11572 #define RMI_RB_GLX_CID_MAP__DB_TILE_MAP_MASK                                                                  0x0F000000L
11573 #define RMI_RB_GLX_CID_MAP__DB_ZPCPSD_MAP_MASK                                                                0xF0000000L
11574 //RMI_SPARE
11575 #define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING__SHIFT                                     0x0
11576 #define RMI_SPARE__RMI_2_GL1_128B_READ_DISABLE__SHIFT                                                         0x1
11577 #define RMI_SPARE__RMI_2_GL1_REPEATER_FGCG_DISABLE__SHIFT                                                     0x2
11578 #define RMI_SPARE__RMI_2_RB_REPEATER_FGCG_DISABLE__SHIFT                                                      0x3
11579 #define RMI_SPARE__EARLY_WRITE_ACK_ENABLE_C_RW_NOA_RESOLVE_DIS__SHIFT                                         0x4
11580 #define RMI_SPARE__RMI_REORDER_BYPASS_CHANNEL_DIS__SHIFT                                                      0x5
11581 #define RMI_SPARE__SPARE_BIT_6__SHIFT                                                                         0x6
11582 #define RMI_SPARE__SPARE_BIT_7__SHIFT                                                                         0x7
11583 #define RMI_SPARE__NOFILL_RMI_CID_CC__SHIFT                                                                   0x8
11584 #define RMI_SPARE__NOFILL_RMI_CID_FC__SHIFT                                                                   0x9
11585 #define RMI_SPARE__NOFILL_RMI_CID_CM__SHIFT                                                                   0xa
11586 #define RMI_SPARE__NOFILL_RMI_CID_DC__SHIFT                                                                   0xb
11587 #define RMI_SPARE__NOFILL_RMI_CID_Z__SHIFT                                                                    0xc
11588 #define RMI_SPARE__NOFILL_RMI_CID_S__SHIFT                                                                    0xd
11589 #define RMI_SPARE__NOFILL_RMI_CID_TILE__SHIFT                                                                 0xe
11590 #define RMI_SPARE__SPARE_BIT_15_0__SHIFT                                                                      0xf
11591 #define RMI_SPARE__ARBITER_ADDRESS_MASK__SHIFT                                                                0x10
11592 #define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING_MASK                                       0x00000001L
11593 #define RMI_SPARE__RMI_2_GL1_128B_READ_DISABLE_MASK                                                           0x00000002L
11594 #define RMI_SPARE__RMI_2_GL1_REPEATER_FGCG_DISABLE_MASK                                                       0x00000004L
11595 #define RMI_SPARE__RMI_2_RB_REPEATER_FGCG_DISABLE_MASK                                                        0x00000008L
11596 #define RMI_SPARE__EARLY_WRITE_ACK_ENABLE_C_RW_NOA_RESOLVE_DIS_MASK                                           0x00000010L
11597 #define RMI_SPARE__RMI_REORDER_BYPASS_CHANNEL_DIS_MASK                                                        0x00000020L
11598 #define RMI_SPARE__SPARE_BIT_6_MASK                                                                           0x00000040L
11599 #define RMI_SPARE__SPARE_BIT_7_MASK                                                                           0x00000080L
11600 #define RMI_SPARE__NOFILL_RMI_CID_CC_MASK                                                                     0x00000100L
11601 #define RMI_SPARE__NOFILL_RMI_CID_FC_MASK                                                                     0x00000200L
11602 #define RMI_SPARE__NOFILL_RMI_CID_CM_MASK                                                                     0x00000400L
11603 #define RMI_SPARE__NOFILL_RMI_CID_DC_MASK                                                                     0x00000800L
11604 #define RMI_SPARE__NOFILL_RMI_CID_Z_MASK                                                                      0x00001000L
11605 #define RMI_SPARE__NOFILL_RMI_CID_S_MASK                                                                      0x00002000L
11606 #define RMI_SPARE__NOFILL_RMI_CID_TILE_MASK                                                                   0x00004000L
11607 #define RMI_SPARE__SPARE_BIT_15_0_MASK                                                                        0x00008000L
11608 #define RMI_SPARE__ARBITER_ADDRESS_MASK_MASK                                                                  0xFFFF0000L
11609 //RMI_SPARE_1
11610 #define RMI_SPARE_1__SPARE_BIT_8__SHIFT                                                                       0x0
11611 #define RMI_SPARE_1__SPARE_BIT_9__SHIFT                                                                       0x1
11612 #define RMI_SPARE_1__SPARE_BIT_10__SHIFT                                                                      0x2
11613 #define RMI_SPARE_1__SPARE_BIT_11__SHIFT                                                                      0x3
11614 #define RMI_SPARE_1__SPARE_BIT_12__SHIFT                                                                      0x4
11615 #define RMI_SPARE_1__SPARE_BIT_13__SHIFT                                                                      0x5
11616 #define RMI_SPARE_1__SPARE_BIT_14__SHIFT                                                                      0x6
11617 #define RMI_SPARE_1__SPARE_BIT_15__SHIFT                                                                      0x7
11618 #define RMI_SPARE_1__RMI_REORDER_DIS_BY_CID__SHIFT                                                            0x8
11619 #define RMI_SPARE_1__SPARE_BIT_16_1__SHIFT                                                                    0x10
11620 #define RMI_SPARE_1__SPARE_BIT_8_MASK                                                                         0x00000001L
11621 #define RMI_SPARE_1__SPARE_BIT_9_MASK                                                                         0x00000002L
11622 #define RMI_SPARE_1__SPARE_BIT_10_MASK                                                                        0x00000004L
11623 #define RMI_SPARE_1__SPARE_BIT_11_MASK                                                                        0x00000008L
11624 #define RMI_SPARE_1__SPARE_BIT_12_MASK                                                                        0x00000010L
11625 #define RMI_SPARE_1__SPARE_BIT_13_MASK                                                                        0x00000020L
11626 #define RMI_SPARE_1__SPARE_BIT_14_MASK                                                                        0x00000040L
11627 #define RMI_SPARE_1__SPARE_BIT_15_MASK                                                                        0x00000080L
11628 #define RMI_SPARE_1__RMI_REORDER_DIS_BY_CID_MASK                                                              0x0000FF00L
11629 #define RMI_SPARE_1__SPARE_BIT_16_1_MASK                                                                      0xFFFF0000L
11630 //RMI_SPARE_2
11631 #define RMI_SPARE_2__SPARE_BIT_16__SHIFT                                                                      0x0
11632 #define RMI_SPARE_2__SPARE_BIT_17__SHIFT                                                                      0x1
11633 #define RMI_SPARE_2__SPARE_BIT_18__SHIFT                                                                      0x2
11634 #define RMI_SPARE_2__SPARE_BIT_19__SHIFT                                                                      0x3
11635 #define RMI_SPARE_2__SPARE_BIT_20__SHIFT                                                                      0x4
11636 #define RMI_SPARE_2__SPARE_BIT_21__SHIFT                                                                      0x5
11637 #define RMI_SPARE_2__SPARE_BIT_22__SHIFT                                                                      0x6
11638 #define RMI_SPARE_2__SPARE_BIT_23__SHIFT                                                                      0x7
11639 #define RMI_SPARE_2__SPARE_BIT_4_0__SHIFT                                                                     0x8
11640 #define RMI_SPARE_2__SPARE_BIT_4_1__SHIFT                                                                     0xc
11641 #define RMI_SPARE_2__SPARE_BIT_8_2__SHIFT                                                                     0x10
11642 #define RMI_SPARE_2__SPARE_BIT_8_3__SHIFT                                                                     0x18
11643 #define RMI_SPARE_2__SPARE_BIT_16_MASK                                                                        0x00000001L
11644 #define RMI_SPARE_2__SPARE_BIT_17_MASK                                                                        0x00000002L
11645 #define RMI_SPARE_2__SPARE_BIT_18_MASK                                                                        0x00000004L
11646 #define RMI_SPARE_2__SPARE_BIT_19_MASK                                                                        0x00000008L
11647 #define RMI_SPARE_2__SPARE_BIT_20_MASK                                                                        0x00000010L
11648 #define RMI_SPARE_2__SPARE_BIT_21_MASK                                                                        0x00000020L
11649 #define RMI_SPARE_2__SPARE_BIT_22_MASK                                                                        0x00000040L
11650 #define RMI_SPARE_2__SPARE_BIT_23_MASK                                                                        0x00000080L
11651 #define RMI_SPARE_2__SPARE_BIT_4_0_MASK                                                                       0x00000F00L
11652 #define RMI_SPARE_2__SPARE_BIT_4_1_MASK                                                                       0x0000F000L
11653 #define RMI_SPARE_2__SPARE_BIT_8_2_MASK                                                                       0x00FF0000L
11654 #define RMI_SPARE_2__SPARE_BIT_8_3_MASK                                                                       0xFF000000L
11655 //CC_RMI_REDUNDANCY
11656 #define CC_RMI_REDUNDANCY__REPAIR_EN_IN_0__SHIFT                                                              0x1
11657 #define CC_RMI_REDUNDANCY__REPAIR_EN_IN_1__SHIFT                                                              0x2
11658 #define CC_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE__SHIFT                                                         0x3
11659 #define CC_RMI_REDUNDANCY__REPAIR_ID_SWAP__SHIFT                                                              0x4
11660 #define CC_RMI_REDUNDANCY__REPAIR_EN_IN_0_MASK                                                                0x00000002L
11661 #define CC_RMI_REDUNDANCY__REPAIR_EN_IN_1_MASK                                                                0x00000004L
11662 #define CC_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE_MASK                                                           0x00000008L
11663 #define CC_RMI_REDUNDANCY__REPAIR_ID_SWAP_MASK                                                                0x00000010L
11664 //GC_USER_RMI_REDUNDANCY
11665 #define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_0__SHIFT                                                         0x1
11666 #define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_1__SHIFT                                                         0x2
11667 #define GC_USER_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE__SHIFT                                                    0x3
11668 #define GC_USER_RMI_REDUNDANCY__REPAIR_ID_SWAP__SHIFT                                                         0x4
11669 #define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_0_MASK                                                           0x00000002L
11670 #define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_1_MASK                                                           0x00000004L
11671 #define GC_USER_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE_MASK                                                      0x00000008L
11672 #define GC_USER_RMI_REDUNDANCY__REPAIR_ID_SWAP_MASK                                                           0x00000010L
11673 
11674 
11675 // addressBlock: gc_pmmdec
11676 //PMM_GENERAL_CNTL
11677 #define PMM_GENERAL_CNTL__PMM_MODE__SHIFT                                                                     0x0
11678 #define PMM_GENERAL_CNTL__PMM_DISABLE__SHIFT                                                                  0x1
11679 #define PMM_GENERAL_CNTL__PMM_ALOG_IH_IDLE__SHIFT                                                             0x2
11680 #define PMM_GENERAL_CNTL__PMM_MODE_MASK                                                                       0x00000001L
11681 #define PMM_GENERAL_CNTL__PMM_DISABLE_MASK                                                                    0x00000002L
11682 #define PMM_GENERAL_CNTL__PMM_ALOG_IH_IDLE_MASK                                                               0x00000004L
11683 //GCR_PIO_CNTL
11684 #define GCR_PIO_CNTL__GCR_DATA_INDEX__SHIFT                                                                   0x0
11685 #define GCR_PIO_CNTL__GCR_REG_DONE__SHIFT                                                                     0x2
11686 #define GCR_PIO_CNTL__GCR_REG_RESET__SHIFT                                                                    0x3
11687 #define GCR_PIO_CNTL__GCR_PIO_RSP_TAG__SHIFT                                                                  0x10
11688 #define GCR_PIO_CNTL__GCR_PIO_RSP_DONE__SHIFT                                                                 0x1e
11689 #define GCR_PIO_CNTL__GCR_READY__SHIFT                                                                        0x1f
11690 #define GCR_PIO_CNTL__GCR_DATA_INDEX_MASK                                                                     0x00000003L
11691 #define GCR_PIO_CNTL__GCR_REG_DONE_MASK                                                                       0x00000004L
11692 #define GCR_PIO_CNTL__GCR_REG_RESET_MASK                                                                      0x00000008L
11693 #define GCR_PIO_CNTL__GCR_PIO_RSP_TAG_MASK                                                                    0x00FF0000L
11694 #define GCR_PIO_CNTL__GCR_PIO_RSP_DONE_MASK                                                                   0x40000000L
11695 #define GCR_PIO_CNTL__GCR_READY_MASK                                                                          0x80000000L
11696 //GCR_PIO_DATA
11697 #define GCR_PIO_DATA__GCR_DATA__SHIFT                                                                         0x0
11698 #define GCR_PIO_DATA__GCR_DATA_MASK                                                                           0xFFFFFFFFL
11699 //GCR_GENERAL_CNTL
11700 #define GCR_GENERAL_CNTL__FORCE_4K_L2_RESP__SHIFT                                                             0x0
11701 #define GCR_GENERAL_CNTL__REDUCE_HALF_MAIN_WQ__SHIFT                                                          0x1
11702 #define GCR_GENERAL_CNTL__REDUCE_HALF_PHY_WQ__SHIFT                                                           0x2
11703 #define GCR_GENERAL_CNTL__FORCE_INV_ALL__SHIFT                                                                0x3
11704 #define GCR_GENERAL_CNTL__HI_PRIORITY_CNTL__SHIFT                                                             0x4
11705 #define GCR_GENERAL_CNTL__HI_PRIORITY_DISABLE__SHIFT                                                          0x6
11706 #define GCR_GENERAL_CNTL__BIG_PAGE_FILTER_DISABLE__SHIFT                                                      0x7
11707 #define GCR_GENERAL_CNTL__PERF_CNTR_ENABLE__SHIFT                                                             0x8
11708 #define GCR_GENERAL_CNTL__FORCE_SINGLE_WQ__SHIFT                                                              0x9
11709 #define GCR_GENERAL_CNTL__UTCL2_REQ_PERM__SHIFT                                                               0xa
11710 #define GCR_GENERAL_CNTL__TARGET_MGCG_CLKEN_DIS__SHIFT                                                        0xd
11711 #define GCR_GENERAL_CNTL__MIXED_RANGE_MODE_DIS__SHIFT                                                         0xe
11712 #define GCR_GENERAL_CNTL__ENABLE_16K_UTCL2_REQ__SHIFT                                                         0xf
11713 #define GCR_GENERAL_CNTL__CLIENT_ID__SHIFT                                                                    0x14
11714 #define GCR_GENERAL_CNTL__FORCE_4K_L2_RESP_MASK                                                               0x00000001L
11715 #define GCR_GENERAL_CNTL__REDUCE_HALF_MAIN_WQ_MASK                                                            0x00000002L
11716 #define GCR_GENERAL_CNTL__REDUCE_HALF_PHY_WQ_MASK                                                             0x00000004L
11717 #define GCR_GENERAL_CNTL__FORCE_INV_ALL_MASK                                                                  0x00000008L
11718 #define GCR_GENERAL_CNTL__HI_PRIORITY_CNTL_MASK                                                               0x00000030L
11719 #define GCR_GENERAL_CNTL__HI_PRIORITY_DISABLE_MASK                                                            0x00000040L
11720 #define GCR_GENERAL_CNTL__BIG_PAGE_FILTER_DISABLE_MASK                                                        0x00000080L
11721 #define GCR_GENERAL_CNTL__PERF_CNTR_ENABLE_MASK                                                               0x00000100L
11722 #define GCR_GENERAL_CNTL__FORCE_SINGLE_WQ_MASK                                                                0x00000200L
11723 #define GCR_GENERAL_CNTL__UTCL2_REQ_PERM_MASK                                                                 0x00001C00L
11724 #define GCR_GENERAL_CNTL__TARGET_MGCG_CLKEN_DIS_MASK                                                          0x00002000L
11725 #define GCR_GENERAL_CNTL__MIXED_RANGE_MODE_DIS_MASK                                                           0x00004000L
11726 #define GCR_GENERAL_CNTL__ENABLE_16K_UTCL2_REQ_MASK                                                           0x00008000L
11727 #define GCR_GENERAL_CNTL__CLIENT_ID_MASK                                                                      0x1FF00000L
11728 //GCR_TARGET_DISABLE
11729 #define GCR_TARGET_DISABLE__DISABLE_SA0_PHY__SHIFT                                                            0x0
11730 #define GCR_TARGET_DISABLE__DISABLE_SA0_VIRT__SHIFT                                                           0x1
11731 #define GCR_TARGET_DISABLE__DISABLE_SA1_PHY__SHIFT                                                            0x2
11732 #define GCR_TARGET_DISABLE__DISABLE_SA1_VIRT__SHIFT                                                           0x3
11733 #define GCR_TARGET_DISABLE__DISABLE_SA2_PHY__SHIFT                                                            0x4
11734 #define GCR_TARGET_DISABLE__DISABLE_SA2_VIRT__SHIFT                                                           0x5
11735 #define GCR_TARGET_DISABLE__DISABLE_SA3_PHY__SHIFT                                                            0x6
11736 #define GCR_TARGET_DISABLE__DISABLE_SA3_VIRT__SHIFT                                                           0x7
11737 #define GCR_TARGET_DISABLE__DISABLE_GL2A0_PHY__SHIFT                                                          0x8
11738 #define GCR_TARGET_DISABLE__DISABLE_GL2A1_PHY__SHIFT                                                          0x9
11739 #define GCR_TARGET_DISABLE__DISABLE_GL2A2_PHY__SHIFT                                                          0xa
11740 #define GCR_TARGET_DISABLE__DISABLE_GL2A3_PHY__SHIFT                                                          0xb
11741 #define GCR_TARGET_DISABLE__DISABLE_SA0_PHY_MASK                                                              0x00000001L
11742 #define GCR_TARGET_DISABLE__DISABLE_SA0_VIRT_MASK                                                             0x00000002L
11743 #define GCR_TARGET_DISABLE__DISABLE_SA1_PHY_MASK                                                              0x00000004L
11744 #define GCR_TARGET_DISABLE__DISABLE_SA1_VIRT_MASK                                                             0x00000008L
11745 #define GCR_TARGET_DISABLE__DISABLE_SA2_PHY_MASK                                                              0x00000010L
11746 #define GCR_TARGET_DISABLE__DISABLE_SA2_VIRT_MASK                                                             0x00000020L
11747 #define GCR_TARGET_DISABLE__DISABLE_SA3_PHY_MASK                                                              0x00000040L
11748 #define GCR_TARGET_DISABLE__DISABLE_SA3_VIRT_MASK                                                             0x00000080L
11749 #define GCR_TARGET_DISABLE__DISABLE_GL2A0_PHY_MASK                                                            0x00000100L
11750 #define GCR_TARGET_DISABLE__DISABLE_GL2A1_PHY_MASK                                                            0x00000200L
11751 #define GCR_TARGET_DISABLE__DISABLE_GL2A2_PHY_MASK                                                            0x00000400L
11752 #define GCR_TARGET_DISABLE__DISABLE_GL2A3_PHY_MASK                                                            0x00000800L
11753 //GCR_CMD_STATUS
11754 #define GCR_CMD_STATUS__GCR_CONTROL__SHIFT                                                                    0x0
11755 #define GCR_CMD_STATUS__GCR_SRC__SHIFT                                                                        0x14
11756 #define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN__SHIFT                                                              0x17
11757 #define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_VMID__SHIFT                                                         0x18
11758 #define GCR_CMD_STATUS__UTCL2_NACK_STATUS__SHIFT                                                              0x1c
11759 #define GCR_CMD_STATUS__GCR_SEQ_OP_ERROR__SHIFT                                                               0x1e
11760 #define GCR_CMD_STATUS__UTCL2_NACK_ERROR__SHIFT                                                               0x1f
11761 #define GCR_CMD_STATUS__GCR_CONTROL_MASK                                                                      0x0007FFFFL
11762 #define GCR_CMD_STATUS__GCR_SRC_MASK                                                                          0x00700000L
11763 #define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_MASK                                                                0x00800000L
11764 #define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_VMID_MASK                                                           0x0F000000L
11765 #define GCR_CMD_STATUS__UTCL2_NACK_STATUS_MASK                                                                0x30000000L
11766 #define GCR_CMD_STATUS__GCR_SEQ_OP_ERROR_MASK                                                                 0x40000000L
11767 #define GCR_CMD_STATUS__UTCL2_NACK_ERROR_MASK                                                                 0x80000000L
11768 //GCR_SPARE
11769 #define GCR_SPARE__SPARE_BIT_1__SHIFT                                                                         0x1
11770 #define GCR_SPARE__SPARE_BIT_2__SHIFT                                                                         0x2
11771 #define GCR_SPARE__SPARE_BIT_3__SHIFT                                                                         0x3
11772 #define GCR_SPARE__SPARE_BIT_4__SHIFT                                                                         0x4
11773 #define GCR_SPARE__SPARE_BIT_5__SHIFT                                                                         0x5
11774 #define GCR_SPARE__SPARE_BIT_6__SHIFT                                                                         0x6
11775 #define GCR_SPARE__SPARE_BIT_7__SHIFT                                                                         0x7
11776 #define GCR_SPARE__SPARE_BIT_8_0__SHIFT                                                                       0x8
11777 #define GCR_SPARE__SPARE_BIT_31_16__SHIFT                                                                     0x10
11778 #define GCR_SPARE__SPARE_BIT_1_MASK                                                                           0x00000002L
11779 #define GCR_SPARE__SPARE_BIT_2_MASK                                                                           0x00000004L
11780 #define GCR_SPARE__SPARE_BIT_3_MASK                                                                           0x00000008L
11781 #define GCR_SPARE__SPARE_BIT_4_MASK                                                                           0x00000010L
11782 #define GCR_SPARE__SPARE_BIT_5_MASK                                                                           0x00000020L
11783 #define GCR_SPARE__SPARE_BIT_6_MASK                                                                           0x00000040L
11784 #define GCR_SPARE__SPARE_BIT_7_MASK                                                                           0x00000080L
11785 #define GCR_SPARE__SPARE_BIT_8_0_MASK                                                                         0x0000FF00L
11786 #define GCR_SPARE__SPARE_BIT_31_16_MASK                                                                       0xFFFF0000L
11787 
11788 
11789 // addressBlock: gc_utcl1dec
11790 //UTCL1_CTRL
11791 #define UTCL1_CTRL__UTCL1_SMALL_PAGE_SIZE__SHIFT                                                              0x0
11792 #define UTCL1_CTRL__UTCL1_LARGE_PAGE_SIZE__SHIFT                                                              0x1
11793 #define UTCL1_CTRL__UTCL1_CACHE_CORE_BYPASS__SHIFT                                                            0x2
11794 #define UTCL1_CTRL__UTCL1_TCP_BYPASS__SHIFT                                                                   0x3
11795 #define UTCL1_CTRL__UTCL1_SQCI_BYPASS__SHIFT                                                                  0x4
11796 #define UTCL1_CTRL__UTCL1_SQCD_BYPASS__SHIFT                                                                  0x5
11797 #define UTCL1_CTRL__UTCL1_RMI_BYPASS__SHIFT                                                                   0x6
11798 #define UTCL1_CTRL__UTCL1_SQG_BYPASS__SHIFT                                                                   0x7
11799 #define UTCL1_CTRL__UTCL1_RMI_DEDICATED_CACHE_CORE__SHIFT                                                     0x8
11800 #define UTCL1_CTRL__UTCL1_FORCE_RANGE_INV_TO_VMID__SHIFT                                                      0x9
11801 #define UTCL1_CTRL__UTCL1_FORCE_INV_ALL__SHIFT                                                                0xa
11802 #define UTCL1_CTRL__UTCL1_FORCE_INV_ALL_DONE__SHIFT                                                           0xb
11803 #define UTCL1_CTRL__UTCL1_UTCL2_FGCG_REPEATERS_OVERRIDE__SHIFT                                                0xc
11804 #define UTCL1_CTRL__UTCL1_INV_FILTER_2M__SHIFT                                                                0xd
11805 #define UTCL1_CTRL__UTCL1_RANGE_INV_FORCE_CHK_ALL__SHIFT                                                      0xe
11806 #define UTCL1_CTRL__RESERVED__SHIFT                                                                           0xf
11807 #define UTCL1_CTRL__UTCL1_MH_INV_FRAG_SIZE_OVERRIDE__SHIFT                                                    0x12
11808 #define UTCL1_CTRL__UTCL1_CACHE_WRITE_PERM__SHIFT                                                             0x13
11809 #define UTCL1_CTRL__UTCL1_MH_CAM_DUPLICATE_4K_FILTER__SHIFT                                                   0x14
11810 #define UTCL1_CTRL__UTCL1_MH_DISABLE_DUPLICATES__SHIFT                                                        0x15
11811 #define UTCL1_CTRL__UTCL1_MH_DISABLE_REQUEST_SQUASHING__SHIFT                                                 0x16
11812 #define UTCL1_CTRL__UTCL1_MH_DISABLE_RECENT_BUFFER__SHIFT                                                     0x17
11813 #define UTCL1_CTRL__UTCL1_MISS_CC_PRIORITY__SHIFT                                                             0x18
11814 #define UTCL1_CTRL__UTCL1_REDUCE_CC_SIZE__SHIFT                                                               0x1a
11815 #define UTCL1_CTRL__UTCL1_REDUCE_MH_CFIFO_SIZE__SHIFT                                                         0x1c
11816 #define UTCL1_CTRL__UTCL1_REDUCE_MH_CAM_SIZE__SHIFT                                                           0x1e
11817 #define UTCL1_CTRL__UTCL1_SMALL_PAGE_SIZE_MASK                                                                0x00000001L
11818 #define UTCL1_CTRL__UTCL1_LARGE_PAGE_SIZE_MASK                                                                0x00000002L
11819 #define UTCL1_CTRL__UTCL1_CACHE_CORE_BYPASS_MASK                                                              0x00000004L
11820 #define UTCL1_CTRL__UTCL1_TCP_BYPASS_MASK                                                                     0x00000008L
11821 #define UTCL1_CTRL__UTCL1_SQCI_BYPASS_MASK                                                                    0x00000010L
11822 #define UTCL1_CTRL__UTCL1_SQCD_BYPASS_MASK                                                                    0x00000020L
11823 #define UTCL1_CTRL__UTCL1_RMI_BYPASS_MASK                                                                     0x00000040L
11824 #define UTCL1_CTRL__UTCL1_SQG_BYPASS_MASK                                                                     0x00000080L
11825 #define UTCL1_CTRL__UTCL1_RMI_DEDICATED_CACHE_CORE_MASK                                                       0x00000100L
11826 #define UTCL1_CTRL__UTCL1_FORCE_RANGE_INV_TO_VMID_MASK                                                        0x00000200L
11827 #define UTCL1_CTRL__UTCL1_FORCE_INV_ALL_MASK                                                                  0x00000400L
11828 #define UTCL1_CTRL__UTCL1_FORCE_INV_ALL_DONE_MASK                                                             0x00000800L
11829 #define UTCL1_CTRL__UTCL1_UTCL2_FGCG_REPEATERS_OVERRIDE_MASK                                                  0x00001000L
11830 #define UTCL1_CTRL__UTCL1_INV_FILTER_2M_MASK                                                                  0x00002000L
11831 #define UTCL1_CTRL__UTCL1_RANGE_INV_FORCE_CHK_ALL_MASK                                                        0x00004000L
11832 #define UTCL1_CTRL__RESERVED_MASK                                                                             0x00038000L
11833 #define UTCL1_CTRL__UTCL1_MH_INV_FRAG_SIZE_OVERRIDE_MASK                                                      0x00040000L
11834 #define UTCL1_CTRL__UTCL1_CACHE_WRITE_PERM_MASK                                                               0x00080000L
11835 #define UTCL1_CTRL__UTCL1_MH_CAM_DUPLICATE_4K_FILTER_MASK                                                     0x00100000L
11836 #define UTCL1_CTRL__UTCL1_MH_DISABLE_DUPLICATES_MASK                                                          0x00200000L
11837 #define UTCL1_CTRL__UTCL1_MH_DISABLE_REQUEST_SQUASHING_MASK                                                   0x00400000L
11838 #define UTCL1_CTRL__UTCL1_MH_DISABLE_RECENT_BUFFER_MASK                                                       0x00800000L
11839 #define UTCL1_CTRL__UTCL1_MISS_CC_PRIORITY_MASK                                                               0x03000000L
11840 #define UTCL1_CTRL__UTCL1_REDUCE_CC_SIZE_MASK                                                                 0x0C000000L
11841 #define UTCL1_CTRL__UTCL1_REDUCE_MH_CFIFO_SIZE_MASK                                                           0x30000000L
11842 #define UTCL1_CTRL__UTCL1_REDUCE_MH_CAM_SIZE_MASK                                                             0xC0000000L
11843 //UTCL1_ALOG
11844 #define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_THRESHOLD__SHIFT                                                 0x0
11845 #define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER2_BYPASS__SHIFT                                                    0x3
11846 #define UTCL1_ALOG__UTCL1_ALOG_ACTIVE__SHIFT                                                                  0x4
11847 #define UTCL1_ALOG__UTCL1_ALOG_MODE__SHIFT                                                                    0x5
11848 #define UTCL1_ALOG__UTCL1_ALOG_MODE2_LOCK_WINDOW__SHIFT                                                       0x6
11849 #define UTCL1_ALOG__UTCL1_ALOG_ONLY_MISS__SHIFT                                                               0x9
11850 #define UTCL1_ALOG__UTCL1_ALOG_MODE2_INTR_THRESHOLD__SHIFT                                                    0xa
11851 #define UTCL1_ALOG__UTCL1_ALOG_SPACE_EN__SHIFT                                                                0xc
11852 #define UTCL1_ALOG__UTCL1_ALOG_CLEAN__SHIFT                                                                   0xf
11853 #define UTCL1_ALOG__UTCL1_ALOG_IDLE__SHIFT                                                                    0x10
11854 #define UTCL1_ALOG__UTCL1_ALOG_TRACK_SEGMENT_SIZE__SHIFT                                                      0x11
11855 #define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_BYPASS__SHIFT                                                    0x17
11856 #define UTCL1_ALOG__UTCL1_ALOG_MODE1_INTR_ON_ALLOC__SHIFT                                                     0x18
11857 #define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_THRESHOLD_MASK                                                   0x00000007L
11858 #define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER2_BYPASS_MASK                                                      0x00000008L
11859 #define UTCL1_ALOG__UTCL1_ALOG_ACTIVE_MASK                                                                    0x00000010L
11860 #define UTCL1_ALOG__UTCL1_ALOG_MODE_MASK                                                                      0x00000020L
11861 #define UTCL1_ALOG__UTCL1_ALOG_MODE2_LOCK_WINDOW_MASK                                                         0x000001C0L
11862 #define UTCL1_ALOG__UTCL1_ALOG_ONLY_MISS_MASK                                                                 0x00000200L
11863 #define UTCL1_ALOG__UTCL1_ALOG_MODE2_INTR_THRESHOLD_MASK                                                      0x00000C00L
11864 #define UTCL1_ALOG__UTCL1_ALOG_SPACE_EN_MASK                                                                  0x00007000L
11865 #define UTCL1_ALOG__UTCL1_ALOG_CLEAN_MASK                                                                     0x00008000L
11866 #define UTCL1_ALOG__UTCL1_ALOG_IDLE_MASK                                                                      0x00010000L
11867 #define UTCL1_ALOG__UTCL1_ALOG_TRACK_SEGMENT_SIZE_MASK                                                        0x007E0000L
11868 #define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_BYPASS_MASK                                                      0x00800000L
11869 #define UTCL1_ALOG__UTCL1_ALOG_MODE1_INTR_ON_ALLOC_MASK                                                       0x01000000L
11870 //UTCL1_UTCL0_INVREQ_DISABLE
11871 #define UTCL1_UTCL0_INVREQ_DISABLE__UTCL1_UTCL0_INVREQ_DISABLE__SHIFT                                         0x0
11872 #define UTCL1_UTCL0_INVREQ_DISABLE__UTCL1_UTCL0_INVREQ_DISABLE_MASK                                           0x01FFFFFFL
11873 //GCRD_SA_TARGETS_DISABLE
11874 #define GCRD_SA_TARGETS_DISABLE__GCRD_TARGETS_DISABLE__SHIFT                                                  0x0
11875 #define GCRD_SA_TARGETS_DISABLE__GCRD_TARGETS_DISABLE_MASK                                                    0x0007FFFFL
11876 
11877 
11878 // addressBlock: gc_gcatcl2dec
11879 //GC_ATC_L2_CNTL
11880 #define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT                                            0x0
11881 #define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT                                           0x3
11882 #define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT                                0x6
11883 #define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT                               0x7
11884 #define GC_ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT                                                          0x8
11885 #define GC_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT                                       0xb
11886 #define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK                                              0x00000003L
11887 #define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK                                             0x00000018L
11888 #define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK                                  0x00000040L
11889 #define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK                                 0x00000080L
11890 #define GC_ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK                                                            0x00000700L
11891 #define GC_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK                                         0x00000800L
11892 //GC_ATC_L2_CNTL2
11893 #define GC_ATC_L2_CNTL2__BANK_SELECT__SHIFT                                                                   0x0
11894 #define GC_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT                                                          0x6
11895 #define GC_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                           0x8
11896 #define GC_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT                                                  0x9
11897 #define GC_ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT                                                            0xc
11898 #define GC_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT                                      0xf
11899 #define GC_ATC_L2_CNTL2__BANK_SELECT_MASK                                                                     0x0000003FL
11900 #define GC_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK                                                            0x000000C0L
11901 #define GC_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK                                             0x00000100L
11902 #define GC_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK                                                    0x00000E00L
11903 #define GC_ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK                                                              0x00007000L
11904 #define GC_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK                                        0x001F8000L
11905 //GC_ATC_L2_CACHE_DATA0
11906 #define GC_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT                                                     0x0
11907 #define GC_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT                                                       0x1
11908 #define GC_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT                                                       0x2
11909 #define GC_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT                                               0x18
11910 #define GC_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK                                                       0x00000001L
11911 #define GC_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK                                                         0x00000002L
11912 #define GC_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK                                                         0x00FFFFFCL
11913 #define GC_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK                                                 0x0F000000L
11914 //GC_ATC_L2_CACHE_DATA1
11915 #define GC_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT                                                0x0
11916 #define GC_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK                                                  0xFFFFFFFFL
11917 //GC_ATC_L2_CACHE_DATA2
11918 #define GC_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT                                                   0x0
11919 #define GC_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK                                                     0xFFFFFFFFL
11920 //GC_ATC_L2_CNTL3
11921 #define GC_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT                                               0x0
11922 #define GC_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT                                                     0x3
11923 #define GC_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT                                                     0x9
11924 #define GC_ATC_L2_CNTL3__REPEATER_FGCG_OFF__SHIFT                                                             0xc
11925 #define GC_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK                                                 0x00000007L
11926 #define GC_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK                                                       0x000001F8L
11927 #define GC_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK                                                       0x00000E00L
11928 #define GC_ATC_L2_CNTL3__REPEATER_FGCG_OFF_MASK                                                               0x00001000L
11929 //GC_ATC_L2_STATUS
11930 #define GC_ATC_L2_STATUS__BUSY__SHIFT                                                                         0x0
11931 #define GC_ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT                                                            0x1
11932 #define GC_ATC_L2_STATUS__BUSY_MASK                                                                           0x00000001L
11933 #define GC_ATC_L2_STATUS__PARITY_ERROR_INFO_MASK                                                              0x3FFFFFFEL
11934 //GC_ATC_L2_STATUS2
11935 #define GC_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT                                           0x0
11936 #define GC_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT                                               0x8
11937 #define GC_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK                                             0x000000FFL
11938 #define GC_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK                                                 0x0000FF00L
11939 //GC_ATC_L2_MISC_CG
11940 #define GC_ATC_L2_MISC_CG__OFFDLY__SHIFT                                                                      0x6
11941 #define GC_ATC_L2_MISC_CG__ENABLE__SHIFT                                                                      0x12
11942 #define GC_ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT                                                               0x13
11943 #define GC_ATC_L2_MISC_CG__OFFDLY_MASK                                                                        0x00000FC0L
11944 #define GC_ATC_L2_MISC_CG__ENABLE_MASK                                                                        0x00040000L
11945 #define GC_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK                                                                 0x00080000L
11946 //GC_ATC_L2_MEM_POWER_LS
11947 #define GC_ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT                                                               0x0
11948 #define GC_ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT                                                                0x6
11949 #define GC_ATC_L2_MEM_POWER_LS__LS_SETUP_MASK                                                                 0x0000003FL
11950 #define GC_ATC_L2_MEM_POWER_LS__LS_HOLD_MASK                                                                  0x00000FC0L
11951 //GC_ATC_L2_CGTT_CLK_CTRL
11952 #define GC_ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                              0x0
11953 #define GC_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                        0x4
11954 #define GC_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                         0xf
11955 #define GC_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                   0x10
11956 #define GC_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT                                                         0x18
11957 #define GC_ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                0x0000000FL
11958 #define GC_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                          0x00000FF0L
11959 #define GC_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK                                                           0x00008000L
11960 #define GC_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                     0x00FF0000L
11961 #define GC_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK                                                           0xFF000000L
11962 //GC_ATC_L2_SDPPORT_CTRL
11963 #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN__SHIFT                                                      0x0
11964 #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV__SHIFT                                                   0x1
11965 #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN__SHIFT                                                  0x2
11966 #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV__SHIFT                                               0x3
11967 #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN__SHIFT                                                      0x4
11968 #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV__SHIFT                                                   0x5
11969 #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN__SHIFT                                                        0x6
11970 #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV__SHIFT                                                     0x7
11971 #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN__SHIFT                                                   0x8
11972 #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV__SHIFT                                                0x9
11973 #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN_MASK                                                        0x00000001L
11974 #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV_MASK                                                     0x00000002L
11975 #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN_MASK                                                    0x00000004L
11976 #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV_MASK                                                 0x00000008L
11977 #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN_MASK                                                        0x00000010L
11978 #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV_MASK                                                     0x00000020L
11979 #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN_MASK                                                          0x00000040L
11980 #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV_MASK                                                       0x00000080L
11981 #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN_MASK                                                     0x00000100L
11982 #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV_MASK                                                  0x00000200L
11983 
11984 
11985 // addressBlock: gc_gcvml2pfdec
11986 //GCVM_L2_CNTL
11987 #define GCVM_L2_CNTL__ENABLE_L2_CACHE__SHIFT                                                                  0x0
11988 #define GCVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT                                                    0x1
11989 #define GCVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT                                                    0x2
11990 #define GCVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT                                                    0x4
11991 #define GCVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT                                                0x8
11992 #define GCVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                          0x9
11993 #define GCVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                         0xa
11994 #define GCVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT                                         0xb
11995 #define GCVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT                                                         0xc
11996 #define GCVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT                                                          0xf
11997 #define GCVM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT                                                         0x12
11998 #define GCVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT                                                    0x13
11999 #define GCVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT                                                      0x15
12000 #define GCVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT                                                           0x1a
12001 #define GCVM_L2_CNTL__ENABLE_L2_CACHE_MASK                                                                    0x00000001L
12002 #define GCVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK                                                      0x00000002L
12003 #define GCVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK                                                      0x0000000CL
12004 #define GCVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK                                                      0x00000030L
12005 #define GCVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK                                                  0x00000100L
12006 #define GCVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK                                            0x00000200L
12007 #define GCVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK                                           0x00000400L
12008 #define GCVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK                                           0x00000800L
12009 #define GCVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK                                                           0x00007000L
12010 #define GCVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK                                                            0x00038000L
12011 #define GCVM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK                                                           0x00040000L
12012 #define GCVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK                                                      0x00180000L
12013 #define GCVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK                                                        0x03E00000L
12014 #define GCVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK                                                             0x0C000000L
12015 //GCVM_L2_CNTL2
12016 #define GCVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT                                                          0x0
12017 #define GCVM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT                                                             0x1
12018 #define GCVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT                                                   0x15
12019 #define GCVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT                                                 0x16
12020 #define GCVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT                                                          0x17
12021 #define GCVM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT                                                           0x1a
12022 #define GCVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT                                                        0x1c
12023 #define GCVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK                                                            0x00000001L
12024 #define GCVM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK                                                               0x00000002L
12025 #define GCVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK                                                     0x00200000L
12026 #define GCVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK                                                   0x00400000L
12027 #define GCVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK                                                            0x03800000L
12028 #define GCVM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK                                                             0x0C000000L
12029 #define GCVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK                                                          0x70000000L
12030 //GCVM_L2_CNTL3
12031 #define GCVM_L2_CNTL3__BANK_SELECT__SHIFT                                                                     0x0
12032 #define GCVM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT                                                            0x6
12033 #define GCVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT                                        0x8
12034 #define GCVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                                                     0xf
12035 #define GCVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT                                                     0x14
12036 #define GCVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT                                                      0x15
12037 #define GCVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT                                                    0x18
12038 #define GCVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT                                                          0x1c
12039 #define GCVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT                                                        0x1d
12040 #define GCVM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT                                                            0x1e
12041 #define GCVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT                                                       0x1f
12042 #define GCVM_L2_CNTL3__BANK_SELECT_MASK                                                                       0x0000003FL
12043 #define GCVM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK                                                              0x000000C0L
12044 #define GCVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK                                          0x00001F00L
12045 #define GCVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                                                       0x000F8000L
12046 #define GCVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK                                                       0x00100000L
12047 #define GCVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK                                                        0x00E00000L
12048 #define GCVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK                                                      0x0F000000L
12049 #define GCVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK                                                            0x10000000L
12050 #define GCVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK                                                          0x20000000L
12051 #define GCVM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK                                                              0x40000000L
12052 #define GCVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK                                                         0x80000000L
12053 //GCVM_L2_STATUS
12054 #define GCVM_L2_STATUS__L2_BUSY__SHIFT                                                                        0x0
12055 #define GCVM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT                                                            0x1
12056 #define GCVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT                                               0x11
12057 #define GCVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT                                             0x12
12058 #define GCVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT                                                 0x13
12059 #define GCVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT                                                 0x14
12060 #define GCVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT                                                 0x15
12061 #define GCVM_L2_STATUS__L2_BUSY_MASK                                                                          0x00000001L
12062 #define GCVM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK                                                              0x0001FFFEL
12063 #define GCVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK                                                 0x00020000L
12064 #define GCVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK                                               0x00040000L
12065 #define GCVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK                                                   0x00080000L
12066 #define GCVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK                                                   0x00100000L
12067 #define GCVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK                                                   0x00200000L
12068 //GCVM_DUMMY_PAGE_FAULT_CNTL
12069 #define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT                                            0x0
12070 #define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT                                         0x1
12071 #define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT                                            0x2
12072 #define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK                                              0x00000001L
12073 #define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK                                           0x00000002L
12074 #define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK                                              0x000000FCL
12075 //GCVM_DUMMY_PAGE_FAULT_ADDR_LO32
12076 #define GCVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT                                          0x0
12077 #define GCVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK                                            0xFFFFFFFFL
12078 //GCVM_DUMMY_PAGE_FAULT_ADDR_HI32
12079 #define GCVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT                                           0x0
12080 #define GCVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK                                             0x0000000FL
12081 //GCVM_INVALIDATE_CNTL
12082 #define GCVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING__SHIFT                                                      0x0
12083 #define GCVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING__SHIFT                                                      0x8
12084 #define GCVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING_MASK                                                        0x000000FFL
12085 #define GCVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING_MASK                                                        0x0000FF00L
12086 //GCVM_L2_PROTECTION_FAULT_CNTL
12087 #define GCVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                              0x0
12088 #define GCVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT           0x1
12089 #define GCVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0x2
12090 #define GCVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                            0x3
12091 #define GCVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                            0x4
12092 #define GCVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                            0x5
12093 #define GCVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT               0x6
12094 #define GCVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                            0x7
12095 #define GCVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                      0x8
12096 #define GCVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0x9
12097 #define GCVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                            0xa
12098 #define GCVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xb
12099 #define GCVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                         0xc
12100 #define GCVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                              0xd
12101 #define GCVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                        0x1d
12102 #define GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT                                         0x1e
12103 #define GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT                                            0x1f
12104 #define GCVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                0x00000001L
12105 #define GCVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK             0x00000002L
12106 #define GCVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00000004L
12107 #define GCVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                              0x00000008L
12108 #define GCVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                              0x00000010L
12109 #define GCVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                              0x00000020L
12110 #define GCVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                 0x00000040L
12111 #define GCVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                              0x00000080L
12112 #define GCVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                        0x00000100L
12113 #define GCVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00000200L
12114 #define GCVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                              0x00000400L
12115 #define GCVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00000800L
12116 #define GCVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                           0x00001000L
12117 #define GCVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                                0x1FFFE000L
12118 #define GCVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                          0x20000000L
12119 #define GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK                                           0x40000000L
12120 #define GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK                                              0x80000000L
12121 //GCVM_L2_PROTECTION_FAULT_CNTL2
12122 #define GCVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT                                  0x0
12123 #define GCVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT                            0x10
12124 #define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT                                      0x11
12125 #define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT                           0x12
12126 #define GCVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT                                   0x13
12127 #define GCVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK                                    0x0000FFFFL
12128 #define GCVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK                              0x00010000L
12129 #define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK                                        0x00020000L
12130 #define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK                             0x00040000L
12131 #define GCVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK                                     0x00080000L
12132 //GCVM_L2_PROTECTION_FAULT_MM_CNTL3
12133 #define GCVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                0x0
12134 #define GCVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                  0xFFFFFFFFL
12135 //GCVM_L2_PROTECTION_FAULT_MM_CNTL4
12136 #define GCVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT               0x0
12137 #define GCVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                 0xFFFFFFFFL
12138 //GCVM_L2_PROTECTION_FAULT_STATUS
12139 #define GCVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT                                                   0x0
12140 #define GCVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT                                                  0x1
12141 #define GCVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT                                             0x4
12142 #define GCVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT                                                 0x8
12143 #define GCVM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT                                                           0x9
12144 #define GCVM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT                                                            0x12
12145 #define GCVM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT                                                        0x13
12146 #define GCVM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT                                                          0x14
12147 #define GCVM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT                                                            0x18
12148 #define GCVM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT                                                          0x19
12149 #define GCVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK                                                     0x00000001L
12150 #define GCVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK                                                    0x0000000EL
12151 #define GCVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK                                               0x000000F0L
12152 #define GCVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK                                                   0x00000100L
12153 #define GCVM_L2_PROTECTION_FAULT_STATUS__CID_MASK                                                             0x0003FE00L
12154 #define GCVM_L2_PROTECTION_FAULT_STATUS__RW_MASK                                                              0x00040000L
12155 #define GCVM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK                                                          0x00080000L
12156 #define GCVM_L2_PROTECTION_FAULT_STATUS__VMID_MASK                                                            0x00F00000L
12157 #define GCVM_L2_PROTECTION_FAULT_STATUS__VF_MASK                                                              0x01000000L
12158 #define GCVM_L2_PROTECTION_FAULT_STATUS__VFID_MASK                                                            0x3E000000L
12159 //GCVM_L2_PROTECTION_FAULT_ADDR_LO32
12160 #define GCVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT                                     0x0
12161 #define GCVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK                                       0xFFFFFFFFL
12162 //GCVM_L2_PROTECTION_FAULT_ADDR_HI32
12163 #define GCVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT                                      0x0
12164 #define GCVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK                                        0x0000000FL
12165 //GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32
12166 #define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT                            0x0
12167 #define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK                              0xFFFFFFFFL
12168 //GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32
12169 #define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT                             0x0
12170 #define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK                               0x0000000FL
12171 //GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32
12172 #define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                     0x0
12173 #define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                       0xFFFFFFFFL
12174 //GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32
12175 #define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                      0x0
12176 #define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                        0x0000000FL
12177 //GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32
12178 #define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                    0x0
12179 #define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                      0xFFFFFFFFL
12180 //GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32
12181 #define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                     0x0
12182 #define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                       0x0000000FL
12183 //GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32
12184 #define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT                       0x0
12185 #define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK                         0xFFFFFFFFL
12186 //GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32
12187 #define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT                        0x0
12188 #define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK                          0x0000000FL
12189 //GCVM_L2_CNTL4
12190 #define GCVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT                                                     0x0
12191 #define GCVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT                                                    0x6
12192 #define GCVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT                                                    0x7
12193 #define GCVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                         0x8
12194 #define GCVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                        0x12
12195 #define GCVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT                                                             0x1c
12196 #define GCVM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT                                                                  0x1d
12197 #define GCVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK                                                       0x0000003FL
12198 #define GCVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK                                                      0x00000040L
12199 #define GCVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK                                                      0x00000080L
12200 #define GCVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                           0x0003FF00L
12201 #define GCVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                          0x0FFC0000L
12202 #define GCVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK                                                               0x10000000L
12203 #define GCVM_L2_CNTL4__GC_CH_FGCG_OFF_MASK                                                                    0x20000000L
12204 //GCVM_L2_MM_GROUP_RT_CLASSES
12205 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT                                                  0x0
12206 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT                                                  0x1
12207 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT                                                  0x2
12208 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT                                                  0x3
12209 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT                                                  0x4
12210 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT                                                  0x5
12211 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT                                                  0x6
12212 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT                                                  0x7
12213 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT                                                  0x8
12214 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT                                                  0x9
12215 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT                                                 0xa
12216 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT                                                 0xb
12217 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT                                                 0xc
12218 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT                                                 0xd
12219 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT                                                 0xe
12220 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT                                                 0xf
12221 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT                                                 0x10
12222 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT                                                 0x11
12223 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT                                                 0x12
12224 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT                                                 0x13
12225 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT                                                 0x14
12226 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT                                                 0x15
12227 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT                                                 0x16
12228 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT                                                 0x17
12229 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT                                                 0x18
12230 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT                                                 0x19
12231 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT                                                 0x1a
12232 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT                                                 0x1b
12233 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT                                                 0x1c
12234 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT                                                 0x1d
12235 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT                                                 0x1e
12236 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT                                                 0x1f
12237 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK                                                    0x00000001L
12238 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK                                                    0x00000002L
12239 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK                                                    0x00000004L
12240 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK                                                    0x00000008L
12241 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK                                                    0x00000010L
12242 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK                                                    0x00000020L
12243 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK                                                    0x00000040L
12244 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK                                                    0x00000080L
12245 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK                                                    0x00000100L
12246 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK                                                    0x00000200L
12247 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK                                                   0x00000400L
12248 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK                                                   0x00000800L
12249 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK                                                   0x00001000L
12250 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK                                                   0x00002000L
12251 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK                                                   0x00004000L
12252 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK                                                   0x00008000L
12253 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK                                                   0x00010000L
12254 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK                                                   0x00020000L
12255 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK                                                   0x00040000L
12256 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK                                                   0x00080000L
12257 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK                                                   0x00100000L
12258 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK                                                   0x00200000L
12259 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK                                                   0x00400000L
12260 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK                                                   0x00800000L
12261 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK                                                   0x01000000L
12262 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK                                                   0x02000000L
12263 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK                                                   0x04000000L
12264 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK                                                   0x08000000L
12265 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK                                                   0x10000000L
12266 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK                                                   0x20000000L
12267 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK                                                   0x40000000L
12268 #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK                                                   0x80000000L
12269 //GCVM_L2_BANK_SELECT_RESERVED_CID
12270 #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT                                      0x0
12271 #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT                                     0xa
12272 #define GCVM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT                                                       0x14
12273 #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT                             0x18
12274 #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT                          0x19
12275 #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT                                 0x1a
12276 #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK                                        0x000001FFL
12277 #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK                                       0x0007FC00L
12278 #define GCVM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK                                                         0x00100000L
12279 #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK                               0x01000000L
12280 #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK                            0x02000000L
12281 #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE_MASK                                   0x7C000000L
12282 //GCVM_L2_BANK_SELECT_RESERVED_CID2
12283 #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT                                     0x0
12284 #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT                                    0xa
12285 #define GCVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT                                                      0x14
12286 #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT                            0x18
12287 #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT                         0x19
12288 #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT                                0x1a
12289 #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK                                       0x000001FFL
12290 #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK                                      0x0007FC00L
12291 #define GCVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK                                                        0x00100000L
12292 #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK                              0x01000000L
12293 #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK                           0x02000000L
12294 #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE_MASK                                  0x7C000000L
12295 //GCVM_L2_CACHE_PARITY_CNTL
12296 #define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT                               0x0
12297 #define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT                             0x1
12298 #define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT                                  0x2
12299 #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT                               0x3
12300 #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT                             0x4
12301 #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT                                  0x5
12302 #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT                                                    0x6
12303 #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT                                                  0x9
12304 #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT                                                   0xc
12305 #define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK                                 0x00000001L
12306 #define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK                               0x00000002L
12307 #define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK                                    0x00000004L
12308 #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK                                 0x00000008L
12309 #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK                               0x00000010L
12310 #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK                                    0x00000020L
12311 #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK                                                      0x000001C0L
12312 #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK                                                    0x00000E00L
12313 #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK                                                     0x0000F000L
12314 //GCVM_L2_CGTT_CLK_CTRL
12315 #define GCVM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                0x0
12316 #define GCVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                          0x4
12317 #define GCVM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                           0xf
12318 #define GCVM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                     0x10
12319 #define GCVM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT                                                           0x18
12320 #define GCVM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                  0x0000000FL
12321 #define GCVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                            0x00000FF0L
12322 #define GCVM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK                                                             0x00008000L
12323 #define GCVM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                       0x00FF0000L
12324 #define GCVM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK                                                             0xFF000000L
12325 //GCVM_L2_CNTL5
12326 #define GCVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT                                                   0x0
12327 #define GCVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID__SHIFT                                                       0x5
12328 #define GCVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                                                     0x0000001FL
12329 #define GCVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID_MASK                                                         0x00003FE0L
12330 //GCVM_L2_GCR_CNTL
12331 #define GCVM_L2_GCR_CNTL__GCR_ENABLE__SHIFT                                                                   0x0
12332 #define GCVM_L2_GCR_CNTL__GCR_CLIENT_ID__SHIFT                                                                0x1
12333 #define GCVM_L2_GCR_CNTL__GCR_ENABLE_MASK                                                                     0x00000001L
12334 #define GCVM_L2_GCR_CNTL__GCR_CLIENT_ID_MASK                                                                  0x000003FEL
12335 //GCVML2_WALKER_MACRO_THROTTLE_TIME
12336 #define GCVML2_WALKER_MACRO_THROTTLE_TIME__TIME__SHIFT                                                        0x0
12337 #define GCVML2_WALKER_MACRO_THROTTLE_TIME__TIME_MASK                                                          0x00FFFFFFL
12338 //GCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT
12339 #define GCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT__LIMIT__SHIFT                                                0x1
12340 #define GCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT__LIMIT_MASK                                                  0x0000FFFEL
12341 //GCVML2_WALKER_MICRO_THROTTLE_TIME
12342 #define GCVML2_WALKER_MICRO_THROTTLE_TIME__TIME__SHIFT                                                        0x0
12343 #define GCVML2_WALKER_MICRO_THROTTLE_TIME__TIME_MASK                                                          0x00FFFFFFL
12344 //GCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT
12345 #define GCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT__LIMIT__SHIFT                                                0x1
12346 #define GCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT__LIMIT_MASK                                                  0x0000FFFEL
12347 
12348 
12349 // addressBlock: gc_gcvml2vcdec
12350 //GCVM_CONTEXT0_CNTL
12351 #define GCVM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
12352 #define GCVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
12353 #define GCVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
12354 #define GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
12355 #define GCVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
12356 #define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
12357 #define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
12358 #define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
12359 #define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
12360 #define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
12361 #define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
12362 #define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
12363 #define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
12364 #define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
12365 #define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
12366 #define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
12367 #define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
12368 #define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
12369 #define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
12370 #define GCVM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
12371 #define GCVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
12372 #define GCVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
12373 #define GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
12374 #define GCVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
12375 #define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
12376 #define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
12377 #define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
12378 #define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
12379 #define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
12380 #define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
12381 #define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
12382 #define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
12383 #define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
12384 #define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
12385 #define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
12386 #define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
12387 #define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
12388 #define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
12389 //GCVM_CONTEXT1_CNTL
12390 #define GCVM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
12391 #define GCVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
12392 #define GCVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
12393 #define GCVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
12394 #define GCVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
12395 #define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
12396 #define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
12397 #define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
12398 #define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
12399 #define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
12400 #define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
12401 #define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
12402 #define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
12403 #define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
12404 #define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
12405 #define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
12406 #define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
12407 #define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
12408 #define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
12409 #define GCVM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
12410 #define GCVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
12411 #define GCVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
12412 #define GCVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
12413 #define GCVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
12414 #define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
12415 #define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
12416 #define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
12417 #define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
12418 #define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
12419 #define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
12420 #define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
12421 #define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
12422 #define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
12423 #define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
12424 #define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
12425 #define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
12426 #define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
12427 #define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
12428 //GCVM_CONTEXT2_CNTL
12429 #define GCVM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
12430 #define GCVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
12431 #define GCVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
12432 #define GCVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
12433 #define GCVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
12434 #define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
12435 #define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
12436 #define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
12437 #define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
12438 #define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
12439 #define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
12440 #define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
12441 #define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
12442 #define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
12443 #define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
12444 #define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
12445 #define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
12446 #define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
12447 #define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
12448 #define GCVM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
12449 #define GCVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
12450 #define GCVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
12451 #define GCVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
12452 #define GCVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
12453 #define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
12454 #define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
12455 #define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
12456 #define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
12457 #define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
12458 #define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
12459 #define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
12460 #define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
12461 #define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
12462 #define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
12463 #define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
12464 #define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
12465 #define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
12466 #define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
12467 //GCVM_CONTEXT3_CNTL
12468 #define GCVM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
12469 #define GCVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
12470 #define GCVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
12471 #define GCVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
12472 #define GCVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
12473 #define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
12474 #define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
12475 #define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
12476 #define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
12477 #define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
12478 #define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
12479 #define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
12480 #define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
12481 #define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
12482 #define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
12483 #define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
12484 #define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
12485 #define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
12486 #define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
12487 #define GCVM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
12488 #define GCVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
12489 #define GCVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
12490 #define GCVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
12491 #define GCVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
12492 #define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
12493 #define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
12494 #define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
12495 #define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
12496 #define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
12497 #define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
12498 #define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
12499 #define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
12500 #define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
12501 #define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
12502 #define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
12503 #define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
12504 #define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
12505 #define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
12506 //GCVM_CONTEXT4_CNTL
12507 #define GCVM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
12508 #define GCVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
12509 #define GCVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
12510 #define GCVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
12511 #define GCVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
12512 #define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
12513 #define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
12514 #define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
12515 #define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
12516 #define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
12517 #define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
12518 #define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
12519 #define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
12520 #define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
12521 #define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
12522 #define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
12523 #define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
12524 #define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
12525 #define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
12526 #define GCVM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
12527 #define GCVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
12528 #define GCVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
12529 #define GCVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
12530 #define GCVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
12531 #define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
12532 #define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
12533 #define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
12534 #define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
12535 #define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
12536 #define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
12537 #define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
12538 #define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
12539 #define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
12540 #define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
12541 #define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
12542 #define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
12543 #define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
12544 #define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
12545 //GCVM_CONTEXT5_CNTL
12546 #define GCVM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
12547 #define GCVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
12548 #define GCVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
12549 #define GCVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
12550 #define GCVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
12551 #define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
12552 #define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
12553 #define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
12554 #define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
12555 #define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
12556 #define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
12557 #define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
12558 #define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
12559 #define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
12560 #define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
12561 #define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
12562 #define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
12563 #define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
12564 #define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
12565 #define GCVM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
12566 #define GCVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
12567 #define GCVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
12568 #define GCVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
12569 #define GCVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
12570 #define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
12571 #define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
12572 #define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
12573 #define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
12574 #define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
12575 #define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
12576 #define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
12577 #define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
12578 #define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
12579 #define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
12580 #define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
12581 #define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
12582 #define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
12583 #define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
12584 //GCVM_CONTEXT6_CNTL
12585 #define GCVM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
12586 #define GCVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
12587 #define GCVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
12588 #define GCVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
12589 #define GCVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
12590 #define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
12591 #define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
12592 #define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
12593 #define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
12594 #define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
12595 #define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
12596 #define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
12597 #define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
12598 #define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
12599 #define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
12600 #define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
12601 #define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
12602 #define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
12603 #define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
12604 #define GCVM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
12605 #define GCVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
12606 #define GCVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
12607 #define GCVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
12608 #define GCVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
12609 #define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
12610 #define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
12611 #define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
12612 #define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
12613 #define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
12614 #define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
12615 #define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
12616 #define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
12617 #define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
12618 #define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
12619 #define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
12620 #define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
12621 #define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
12622 #define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
12623 //GCVM_CONTEXT7_CNTL
12624 #define GCVM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
12625 #define GCVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
12626 #define GCVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
12627 #define GCVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
12628 #define GCVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
12629 #define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
12630 #define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
12631 #define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
12632 #define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
12633 #define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
12634 #define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
12635 #define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
12636 #define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
12637 #define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
12638 #define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
12639 #define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
12640 #define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
12641 #define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
12642 #define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
12643 #define GCVM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
12644 #define GCVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
12645 #define GCVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
12646 #define GCVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
12647 #define GCVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
12648 #define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
12649 #define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
12650 #define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
12651 #define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
12652 #define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
12653 #define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
12654 #define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
12655 #define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
12656 #define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
12657 #define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
12658 #define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
12659 #define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
12660 #define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
12661 #define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
12662 //GCVM_CONTEXT8_CNTL
12663 #define GCVM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
12664 #define GCVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
12665 #define GCVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
12666 #define GCVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
12667 #define GCVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
12668 #define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
12669 #define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
12670 #define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
12671 #define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
12672 #define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
12673 #define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
12674 #define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
12675 #define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
12676 #define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
12677 #define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
12678 #define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
12679 #define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
12680 #define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
12681 #define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
12682 #define GCVM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
12683 #define GCVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
12684 #define GCVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
12685 #define GCVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
12686 #define GCVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
12687 #define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
12688 #define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
12689 #define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
12690 #define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
12691 #define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
12692 #define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
12693 #define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
12694 #define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
12695 #define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
12696 #define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
12697 #define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
12698 #define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
12699 #define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
12700 #define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
12701 //GCVM_CONTEXT9_CNTL
12702 #define GCVM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
12703 #define GCVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
12704 #define GCVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
12705 #define GCVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
12706 #define GCVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
12707 #define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
12708 #define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
12709 #define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
12710 #define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
12711 #define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
12712 #define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
12713 #define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
12714 #define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
12715 #define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
12716 #define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
12717 #define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
12718 #define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
12719 #define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
12720 #define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
12721 #define GCVM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
12722 #define GCVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
12723 #define GCVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
12724 #define GCVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
12725 #define GCVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
12726 #define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
12727 #define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
12728 #define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
12729 #define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
12730 #define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
12731 #define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
12732 #define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
12733 #define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
12734 #define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
12735 #define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
12736 #define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
12737 #define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
12738 #define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
12739 #define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
12740 //GCVM_CONTEXT10_CNTL
12741 #define GCVM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT                                                            0x0
12742 #define GCVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                          0x1
12743 #define GCVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                     0x3
12744 #define GCVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                    0x7
12745 #define GCVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT                                                         0x8
12746 #define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x9
12747 #define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0xa
12748 #define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xb
12749 #define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xc
12750 #define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xd
12751 #define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xe
12752 #define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0xf
12753 #define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x10
12754 #define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x11
12755 #define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x12
12756 #define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x13
12757 #define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x14
12758 #define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0x15
12759 #define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0x16
12760 #define GCVM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK                                                              0x00000001L
12761 #define GCVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK                                                            0x00000006L
12762 #define GCVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                       0x00000078L
12763 #define GCVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                      0x00000080L
12764 #define GCVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK                                                           0x00000100L
12765 #define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00000200L
12766 #define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00000400L
12767 #define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000800L
12768 #define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00001000L
12769 #define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00002000L
12770 #define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00004000L
12771 #define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00008000L
12772 #define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00010000L
12773 #define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00020000L
12774 #define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00040000L
12775 #define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00080000L
12776 #define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00100000L
12777 #define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00200000L
12778 #define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00400000L
12779 //GCVM_CONTEXT11_CNTL
12780 #define GCVM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT                                                            0x0
12781 #define GCVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                          0x1
12782 #define GCVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                     0x3
12783 #define GCVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                    0x7
12784 #define GCVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT                                                         0x8
12785 #define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x9
12786 #define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0xa
12787 #define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xb
12788 #define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xc
12789 #define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xd
12790 #define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xe
12791 #define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0xf
12792 #define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x10
12793 #define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x11
12794 #define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x12
12795 #define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x13
12796 #define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x14
12797 #define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0x15
12798 #define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0x16
12799 #define GCVM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK                                                              0x00000001L
12800 #define GCVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK                                                            0x00000006L
12801 #define GCVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                       0x00000078L
12802 #define GCVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                      0x00000080L
12803 #define GCVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK                                                           0x00000100L
12804 #define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00000200L
12805 #define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00000400L
12806 #define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000800L
12807 #define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00001000L
12808 #define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00002000L
12809 #define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00004000L
12810 #define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00008000L
12811 #define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00010000L
12812 #define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00020000L
12813 #define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00040000L
12814 #define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00080000L
12815 #define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00100000L
12816 #define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00200000L
12817 #define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00400000L
12818 //GCVM_CONTEXT12_CNTL
12819 #define GCVM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT                                                            0x0
12820 #define GCVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                          0x1
12821 #define GCVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                     0x3
12822 #define GCVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                    0x7
12823 #define GCVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT                                                         0x8
12824 #define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x9
12825 #define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0xa
12826 #define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xb
12827 #define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xc
12828 #define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xd
12829 #define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xe
12830 #define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0xf
12831 #define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x10
12832 #define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x11
12833 #define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x12
12834 #define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x13
12835 #define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x14
12836 #define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0x15
12837 #define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0x16
12838 #define GCVM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK                                                              0x00000001L
12839 #define GCVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK                                                            0x00000006L
12840 #define GCVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                       0x00000078L
12841 #define GCVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                      0x00000080L
12842 #define GCVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK                                                           0x00000100L
12843 #define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00000200L
12844 #define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00000400L
12845 #define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000800L
12846 #define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00001000L
12847 #define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00002000L
12848 #define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00004000L
12849 #define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00008000L
12850 #define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00010000L
12851 #define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00020000L
12852 #define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00040000L
12853 #define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00080000L
12854 #define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00100000L
12855 #define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00200000L
12856 #define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00400000L
12857 //GCVM_CONTEXT13_CNTL
12858 #define GCVM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT                                                            0x0
12859 #define GCVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                          0x1
12860 #define GCVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                     0x3
12861 #define GCVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                    0x7
12862 #define GCVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT                                                         0x8
12863 #define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x9
12864 #define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0xa
12865 #define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xb
12866 #define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xc
12867 #define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xd
12868 #define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xe
12869 #define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0xf
12870 #define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x10
12871 #define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x11
12872 #define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x12
12873 #define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x13
12874 #define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x14
12875 #define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0x15
12876 #define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0x16
12877 #define GCVM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK                                                              0x00000001L
12878 #define GCVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK                                                            0x00000006L
12879 #define GCVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                       0x00000078L
12880 #define GCVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                      0x00000080L
12881 #define GCVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK                                                           0x00000100L
12882 #define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00000200L
12883 #define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00000400L
12884 #define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000800L
12885 #define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00001000L
12886 #define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00002000L
12887 #define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00004000L
12888 #define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00008000L
12889 #define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00010000L
12890 #define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00020000L
12891 #define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00040000L
12892 #define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00080000L
12893 #define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00100000L
12894 #define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00200000L
12895 #define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00400000L
12896 //GCVM_CONTEXT14_CNTL
12897 #define GCVM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT                                                            0x0
12898 #define GCVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                          0x1
12899 #define GCVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                     0x3
12900 #define GCVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                    0x7
12901 #define GCVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT                                                         0x8
12902 #define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x9
12903 #define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0xa
12904 #define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xb
12905 #define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xc
12906 #define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xd
12907 #define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xe
12908 #define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0xf
12909 #define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x10
12910 #define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x11
12911 #define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x12
12912 #define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x13
12913 #define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x14
12914 #define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0x15
12915 #define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0x16
12916 #define GCVM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK                                                              0x00000001L
12917 #define GCVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK                                                            0x00000006L
12918 #define GCVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                       0x00000078L
12919 #define GCVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                      0x00000080L
12920 #define GCVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK                                                           0x00000100L
12921 #define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00000200L
12922 #define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00000400L
12923 #define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000800L
12924 #define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00001000L
12925 #define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00002000L
12926 #define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00004000L
12927 #define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00008000L
12928 #define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00010000L
12929 #define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00020000L
12930 #define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00040000L
12931 #define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00080000L
12932 #define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00100000L
12933 #define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00200000L
12934 #define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00400000L
12935 //GCVM_CONTEXT15_CNTL
12936 #define GCVM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT                                                            0x0
12937 #define GCVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                          0x1
12938 #define GCVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                     0x3
12939 #define GCVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                    0x7
12940 #define GCVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT                                                         0x8
12941 #define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x9
12942 #define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0xa
12943 #define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xb
12944 #define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xc
12945 #define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xd
12946 #define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xe
12947 #define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0xf
12948 #define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x10
12949 #define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x11
12950 #define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x12
12951 #define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x13
12952 #define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x14
12953 #define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0x15
12954 #define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0x16
12955 #define GCVM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK                                                              0x00000001L
12956 #define GCVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK                                                            0x00000006L
12957 #define GCVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                       0x00000078L
12958 #define GCVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                      0x00000080L
12959 #define GCVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK                                                           0x00000100L
12960 #define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00000200L
12961 #define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00000400L
12962 #define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000800L
12963 #define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00001000L
12964 #define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00002000L
12965 #define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00004000L
12966 #define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00008000L
12967 #define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00010000L
12968 #define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00020000L
12969 #define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00040000L
12970 #define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00080000L
12971 #define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00100000L
12972 #define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00200000L
12973 #define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00400000L
12974 //GCVM_CONTEXTS_DISABLE
12975 #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT                                                       0x0
12976 #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT                                                       0x1
12977 #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT                                                       0x2
12978 #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT                                                       0x3
12979 #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT                                                       0x4
12980 #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT                                                       0x5
12981 #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT                                                       0x6
12982 #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT                                                       0x7
12983 #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT                                                       0x8
12984 #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT                                                       0x9
12985 #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT                                                      0xa
12986 #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT                                                      0xb
12987 #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT                                                      0xc
12988 #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT                                                      0xd
12989 #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT                                                      0xe
12990 #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT                                                      0xf
12991 #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK                                                         0x00000001L
12992 #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK                                                         0x00000002L
12993 #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK                                                         0x00000004L
12994 #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK                                                         0x00000008L
12995 #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK                                                         0x00000010L
12996 #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK                                                         0x00000020L
12997 #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK                                                         0x00000040L
12998 #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK                                                         0x00000080L
12999 #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK                                                         0x00000100L
13000 #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK                                                         0x00000200L
13001 #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK                                                        0x00000400L
13002 #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK                                                        0x00000800L
13003 #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK                                                        0x00001000L
13004 #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK                                                        0x00002000L
13005 #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK                                                        0x00004000L
13006 #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK                                                        0x00008000L
13007 //GCVM_INVALIDATE_ENG0_SEM
13008 #define GCVM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT                                                            0x0
13009 #define GCVM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK                                                              0x00000001L
13010 //GCVM_INVALIDATE_ENG1_SEM
13011 #define GCVM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT                                                            0x0
13012 #define GCVM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK                                                              0x00000001L
13013 //GCVM_INVALIDATE_ENG2_SEM
13014 #define GCVM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT                                                            0x0
13015 #define GCVM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK                                                              0x00000001L
13016 //GCVM_INVALIDATE_ENG3_SEM
13017 #define GCVM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT                                                            0x0
13018 #define GCVM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK                                                              0x00000001L
13019 //GCVM_INVALIDATE_ENG4_SEM
13020 #define GCVM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT                                                            0x0
13021 #define GCVM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK                                                              0x00000001L
13022 //GCVM_INVALIDATE_ENG5_SEM
13023 #define GCVM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT                                                            0x0
13024 #define GCVM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK                                                              0x00000001L
13025 //GCVM_INVALIDATE_ENG6_SEM
13026 #define GCVM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT                                                            0x0
13027 #define GCVM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK                                                              0x00000001L
13028 //GCVM_INVALIDATE_ENG7_SEM
13029 #define GCVM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT                                                            0x0
13030 #define GCVM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK                                                              0x00000001L
13031 //GCVM_INVALIDATE_ENG8_SEM
13032 #define GCVM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT                                                            0x0
13033 #define GCVM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK                                                              0x00000001L
13034 //GCVM_INVALIDATE_ENG9_SEM
13035 #define GCVM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT                                                            0x0
13036 #define GCVM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK                                                              0x00000001L
13037 //GCVM_INVALIDATE_ENG10_SEM
13038 #define GCVM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT                                                           0x0
13039 #define GCVM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK                                                             0x00000001L
13040 //GCVM_INVALIDATE_ENG11_SEM
13041 #define GCVM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT                                                           0x0
13042 #define GCVM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK                                                             0x00000001L
13043 //GCVM_INVALIDATE_ENG12_SEM
13044 #define GCVM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT                                                           0x0
13045 #define GCVM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK                                                             0x00000001L
13046 //GCVM_INVALIDATE_ENG13_SEM
13047 #define GCVM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT                                                           0x0
13048 #define GCVM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK                                                             0x00000001L
13049 //GCVM_INVALIDATE_ENG14_SEM
13050 #define GCVM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT                                                           0x0
13051 #define GCVM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK                                                             0x00000001L
13052 //GCVM_INVALIDATE_ENG15_SEM
13053 #define GCVM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT                                                           0x0
13054 #define GCVM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK                                                             0x00000001L
13055 //GCVM_INVALIDATE_ENG16_SEM
13056 #define GCVM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT                                                           0x0
13057 #define GCVM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK                                                             0x00000001L
13058 //GCVM_INVALIDATE_ENG17_SEM
13059 #define GCVM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT                                                           0x0
13060 #define GCVM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK                                                             0x00000001L
13061 //GCVM_INVALIDATE_ENG0_REQ
13062 #define GCVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
13063 #define GCVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT                                                           0x10
13064 #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
13065 #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
13066 #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
13067 #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
13068 #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
13069 #define GCVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
13070 #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
13071 #define GCVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
13072 #define GCVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
13073 #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
13074 #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
13075 #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
13076 #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
13077 #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
13078 #define GCVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
13079 #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
13080 //GCVM_INVALIDATE_ENG1_REQ
13081 #define GCVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
13082 #define GCVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT                                                           0x10
13083 #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
13084 #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
13085 #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
13086 #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
13087 #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
13088 #define GCVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
13089 #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
13090 #define GCVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
13091 #define GCVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
13092 #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
13093 #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
13094 #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
13095 #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
13096 #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
13097 #define GCVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
13098 #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
13099 //GCVM_INVALIDATE_ENG2_REQ
13100 #define GCVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
13101 #define GCVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT                                                           0x10
13102 #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
13103 #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
13104 #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
13105 #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
13106 #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
13107 #define GCVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
13108 #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
13109 #define GCVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
13110 #define GCVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
13111 #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
13112 #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
13113 #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
13114 #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
13115 #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
13116 #define GCVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
13117 #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
13118 //GCVM_INVALIDATE_ENG3_REQ
13119 #define GCVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
13120 #define GCVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT                                                           0x10
13121 #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
13122 #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
13123 #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
13124 #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
13125 #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
13126 #define GCVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
13127 #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
13128 #define GCVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
13129 #define GCVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
13130 #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
13131 #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
13132 #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
13133 #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
13134 #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
13135 #define GCVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
13136 #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
13137 //GCVM_INVALIDATE_ENG4_REQ
13138 #define GCVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
13139 #define GCVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT                                                           0x10
13140 #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
13141 #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
13142 #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
13143 #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
13144 #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
13145 #define GCVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
13146 #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
13147 #define GCVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
13148 #define GCVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
13149 #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
13150 #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
13151 #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
13152 #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
13153 #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
13154 #define GCVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
13155 #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
13156 //GCVM_INVALIDATE_ENG5_REQ
13157 #define GCVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
13158 #define GCVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT                                                           0x10
13159 #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
13160 #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
13161 #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
13162 #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
13163 #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
13164 #define GCVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
13165 #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
13166 #define GCVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
13167 #define GCVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
13168 #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
13169 #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
13170 #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
13171 #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
13172 #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
13173 #define GCVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
13174 #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
13175 //GCVM_INVALIDATE_ENG6_REQ
13176 #define GCVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
13177 #define GCVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT                                                           0x10
13178 #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
13179 #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
13180 #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
13181 #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
13182 #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
13183 #define GCVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
13184 #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
13185 #define GCVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
13186 #define GCVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
13187 #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
13188 #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
13189 #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
13190 #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
13191 #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
13192 #define GCVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
13193 #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
13194 //GCVM_INVALIDATE_ENG7_REQ
13195 #define GCVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
13196 #define GCVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT                                                           0x10
13197 #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
13198 #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
13199 #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
13200 #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
13201 #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
13202 #define GCVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
13203 #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
13204 #define GCVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
13205 #define GCVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
13206 #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
13207 #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
13208 #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
13209 #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
13210 #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
13211 #define GCVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
13212 #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
13213 //GCVM_INVALIDATE_ENG8_REQ
13214 #define GCVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
13215 #define GCVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT                                                           0x10
13216 #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
13217 #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
13218 #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
13219 #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
13220 #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
13221 #define GCVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
13222 #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
13223 #define GCVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
13224 #define GCVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
13225 #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
13226 #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
13227 #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
13228 #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
13229 #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
13230 #define GCVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
13231 #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
13232 //GCVM_INVALIDATE_ENG9_REQ
13233 #define GCVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
13234 #define GCVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT                                                           0x10
13235 #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
13236 #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
13237 #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
13238 #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
13239 #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
13240 #define GCVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
13241 #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
13242 #define GCVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
13243 #define GCVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
13244 #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
13245 #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
13246 #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
13247 #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
13248 #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
13249 #define GCVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
13250 #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
13251 //GCVM_INVALIDATE_ENG10_REQ
13252 #define GCVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
13253 #define GCVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT                                                          0x10
13254 #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
13255 #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
13256 #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
13257 #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
13258 #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
13259 #define GCVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
13260 #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
13261 #define GCVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
13262 #define GCVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
13263 #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
13264 #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
13265 #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
13266 #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
13267 #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
13268 #define GCVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
13269 #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
13270 //GCVM_INVALIDATE_ENG11_REQ
13271 #define GCVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
13272 #define GCVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT                                                          0x10
13273 #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
13274 #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
13275 #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
13276 #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
13277 #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
13278 #define GCVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
13279 #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
13280 #define GCVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
13281 #define GCVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
13282 #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
13283 #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
13284 #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
13285 #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
13286 #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
13287 #define GCVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
13288 #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
13289 //GCVM_INVALIDATE_ENG12_REQ
13290 #define GCVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
13291 #define GCVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT                                                          0x10
13292 #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
13293 #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
13294 #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
13295 #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
13296 #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
13297 #define GCVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
13298 #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
13299 #define GCVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
13300 #define GCVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
13301 #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
13302 #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
13303 #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
13304 #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
13305 #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
13306 #define GCVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
13307 #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
13308 //GCVM_INVALIDATE_ENG13_REQ
13309 #define GCVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
13310 #define GCVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT                                                          0x10
13311 #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
13312 #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
13313 #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
13314 #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
13315 #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
13316 #define GCVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
13317 #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
13318 #define GCVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
13319 #define GCVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
13320 #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
13321 #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
13322 #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
13323 #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
13324 #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
13325 #define GCVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
13326 #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
13327 //GCVM_INVALIDATE_ENG14_REQ
13328 #define GCVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
13329 #define GCVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT                                                          0x10
13330 #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
13331 #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
13332 #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
13333 #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
13334 #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
13335 #define GCVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
13336 #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
13337 #define GCVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
13338 #define GCVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
13339 #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
13340 #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
13341 #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
13342 #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
13343 #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
13344 #define GCVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
13345 #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
13346 //GCVM_INVALIDATE_ENG15_REQ
13347 #define GCVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
13348 #define GCVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT                                                          0x10
13349 #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
13350 #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
13351 #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
13352 #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
13353 #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
13354 #define GCVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
13355 #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
13356 #define GCVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
13357 #define GCVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
13358 #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
13359 #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
13360 #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
13361 #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
13362 #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
13363 #define GCVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
13364 #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
13365 //GCVM_INVALIDATE_ENG16_REQ
13366 #define GCVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
13367 #define GCVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT                                                          0x10
13368 #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
13369 #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
13370 #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
13371 #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
13372 #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
13373 #define GCVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
13374 #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
13375 #define GCVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
13376 #define GCVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
13377 #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
13378 #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
13379 #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
13380 #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
13381 #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
13382 #define GCVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
13383 #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
13384 //GCVM_INVALIDATE_ENG17_REQ
13385 #define GCVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
13386 #define GCVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT                                                          0x10
13387 #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
13388 #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
13389 #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
13390 #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
13391 #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
13392 #define GCVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
13393 #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
13394 #define GCVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
13395 #define GCVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
13396 #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
13397 #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
13398 #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
13399 #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
13400 #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
13401 #define GCVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
13402 #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
13403 //GCVM_INVALIDATE_ENG0_ACK
13404 #define GCVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
13405 #define GCVM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT                                                            0x10
13406 #define GCVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
13407 #define GCVM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK                                                              0x00010000L
13408 //GCVM_INVALIDATE_ENG1_ACK
13409 #define GCVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
13410 #define GCVM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT                                                            0x10
13411 #define GCVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
13412 #define GCVM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK                                                              0x00010000L
13413 //GCVM_INVALIDATE_ENG2_ACK
13414 #define GCVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
13415 #define GCVM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT                                                            0x10
13416 #define GCVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
13417 #define GCVM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK                                                              0x00010000L
13418 //GCVM_INVALIDATE_ENG3_ACK
13419 #define GCVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
13420 #define GCVM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT                                                            0x10
13421 #define GCVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
13422 #define GCVM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK                                                              0x00010000L
13423 //GCVM_INVALIDATE_ENG4_ACK
13424 #define GCVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
13425 #define GCVM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT                                                            0x10
13426 #define GCVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
13427 #define GCVM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK                                                              0x00010000L
13428 //GCVM_INVALIDATE_ENG5_ACK
13429 #define GCVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
13430 #define GCVM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT                                                            0x10
13431 #define GCVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
13432 #define GCVM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK                                                              0x00010000L
13433 //GCVM_INVALIDATE_ENG6_ACK
13434 #define GCVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
13435 #define GCVM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT                                                            0x10
13436 #define GCVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
13437 #define GCVM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK                                                              0x00010000L
13438 //GCVM_INVALIDATE_ENG7_ACK
13439 #define GCVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
13440 #define GCVM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT                                                            0x10
13441 #define GCVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
13442 #define GCVM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK                                                              0x00010000L
13443 //GCVM_INVALIDATE_ENG8_ACK
13444 #define GCVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
13445 #define GCVM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT                                                            0x10
13446 #define GCVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
13447 #define GCVM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK                                                              0x00010000L
13448 //GCVM_INVALIDATE_ENG9_ACK
13449 #define GCVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
13450 #define GCVM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT                                                            0x10
13451 #define GCVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
13452 #define GCVM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK                                                              0x00010000L
13453 //GCVM_INVALIDATE_ENG10_ACK
13454 #define GCVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
13455 #define GCVM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT                                                           0x10
13456 #define GCVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
13457 #define GCVM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK                                                             0x00010000L
13458 //GCVM_INVALIDATE_ENG11_ACK
13459 #define GCVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
13460 #define GCVM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT                                                           0x10
13461 #define GCVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
13462 #define GCVM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK                                                             0x00010000L
13463 //GCVM_INVALIDATE_ENG12_ACK
13464 #define GCVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
13465 #define GCVM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT                                                           0x10
13466 #define GCVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
13467 #define GCVM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK                                                             0x00010000L
13468 //GCVM_INVALIDATE_ENG13_ACK
13469 #define GCVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
13470 #define GCVM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT                                                           0x10
13471 #define GCVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
13472 #define GCVM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK                                                             0x00010000L
13473 //GCVM_INVALIDATE_ENG14_ACK
13474 #define GCVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
13475 #define GCVM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT                                                           0x10
13476 #define GCVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
13477 #define GCVM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK                                                             0x00010000L
13478 //GCVM_INVALIDATE_ENG15_ACK
13479 #define GCVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
13480 #define GCVM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT                                                           0x10
13481 #define GCVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
13482 #define GCVM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK                                                             0x00010000L
13483 //GCVM_INVALIDATE_ENG16_ACK
13484 #define GCVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
13485 #define GCVM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT                                                           0x10
13486 #define GCVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
13487 #define GCVM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK                                                             0x00010000L
13488 //GCVM_INVALIDATE_ENG17_ACK
13489 #define GCVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
13490 #define GCVM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT                                                           0x10
13491 #define GCVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
13492 #define GCVM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK                                                             0x00010000L
13493 //GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32
13494 #define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
13495 #define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
13496 #define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
13497 #define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
13498 //GCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32
13499 #define GCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
13500 #define GCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
13501 //GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32
13502 #define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
13503 #define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
13504 #define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
13505 #define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
13506 //GCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32
13507 #define GCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
13508 #define GCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
13509 //GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32
13510 #define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
13511 #define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
13512 #define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
13513 #define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
13514 //GCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32
13515 #define GCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
13516 #define GCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
13517 //GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32
13518 #define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
13519 #define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
13520 #define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
13521 #define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
13522 //GCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32
13523 #define GCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
13524 #define GCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
13525 //GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32
13526 #define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
13527 #define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
13528 #define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
13529 #define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
13530 //GCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32
13531 #define GCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
13532 #define GCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
13533 //GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32
13534 #define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
13535 #define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
13536 #define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
13537 #define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
13538 //GCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32
13539 #define GCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
13540 #define GCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
13541 //GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32
13542 #define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
13543 #define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
13544 #define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
13545 #define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
13546 //GCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32
13547 #define GCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
13548 #define GCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
13549 //GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32
13550 #define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
13551 #define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
13552 #define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
13553 #define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
13554 //GCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32
13555 #define GCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
13556 #define GCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
13557 //GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32
13558 #define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
13559 #define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
13560 #define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
13561 #define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
13562 //GCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32
13563 #define GCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
13564 #define GCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
13565 //GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32
13566 #define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
13567 #define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
13568 #define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
13569 #define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
13570 //GCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32
13571 #define GCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
13572 #define GCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
13573 //GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32
13574 #define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
13575 #define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
13576 #define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
13577 #define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
13578 //GCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32
13579 #define GCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
13580 #define GCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
13581 //GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32
13582 #define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
13583 #define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
13584 #define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
13585 #define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
13586 //GCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32
13587 #define GCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
13588 #define GCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
13589 //GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32
13590 #define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
13591 #define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
13592 #define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
13593 #define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
13594 //GCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32
13595 #define GCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
13596 #define GCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
13597 //GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32
13598 #define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
13599 #define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
13600 #define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
13601 #define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
13602 //GCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32
13603 #define GCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
13604 #define GCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
13605 //GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32
13606 #define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
13607 #define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
13608 #define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
13609 #define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
13610 //GCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32
13611 #define GCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
13612 #define GCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
13613 //GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32
13614 #define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
13615 #define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
13616 #define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
13617 #define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
13618 //GCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32
13619 #define GCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
13620 #define GCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
13621 //GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32
13622 #define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
13623 #define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
13624 #define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
13625 #define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
13626 //GCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32
13627 #define GCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
13628 #define GCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
13629 //GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32
13630 #define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
13631 #define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
13632 #define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
13633 #define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
13634 //GCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32
13635 #define GCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
13636 #define GCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
13637 //GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
13638 #define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
13639 #define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
13640 //GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
13641 #define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
13642 #define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
13643 //GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
13644 #define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
13645 #define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
13646 //GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32
13647 #define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
13648 #define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
13649 //GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32
13650 #define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
13651 #define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
13652 //GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32
13653 #define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
13654 #define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
13655 //GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
13656 #define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
13657 #define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
13658 //GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32
13659 #define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
13660 #define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
13661 //GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32
13662 #define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
13663 #define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
13664 //GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32
13665 #define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
13666 #define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
13667 //GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32
13668 #define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
13669 #define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
13670 //GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32
13671 #define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
13672 #define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
13673 //GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32
13674 #define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
13675 #define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
13676 //GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32
13677 #define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
13678 #define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
13679 //GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32
13680 #define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
13681 #define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
13682 //GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32
13683 #define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
13684 #define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
13685 //GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32
13686 #define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
13687 #define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
13688 //GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32
13689 #define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
13690 #define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
13691 //GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32
13692 #define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
13693 #define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
13694 //GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32
13695 #define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
13696 #define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
13697 //GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32
13698 #define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                            0x0
13699 #define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                              0xFFFFFFFFL
13700 //GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32
13701 #define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                            0x0
13702 #define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                              0xFFFFFFFFL
13703 //GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32
13704 #define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                            0x0
13705 #define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                              0xFFFFFFFFL
13706 //GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32
13707 #define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                            0x0
13708 #define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                              0xFFFFFFFFL
13709 //GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32
13710 #define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                            0x0
13711 #define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                              0xFFFFFFFFL
13712 //GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32
13713 #define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                            0x0
13714 #define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                              0xFFFFFFFFL
13715 //GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32
13716 #define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                            0x0
13717 #define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                              0xFFFFFFFFL
13718 //GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32
13719 #define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                            0x0
13720 #define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                              0xFFFFFFFFL
13721 //GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32
13722 #define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                            0x0
13723 #define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                              0xFFFFFFFFL
13724 //GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32
13725 #define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                            0x0
13726 #define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                              0xFFFFFFFFL
13727 //GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32
13728 #define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                            0x0
13729 #define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                              0xFFFFFFFFL
13730 //GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32
13731 #define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                            0x0
13732 #define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                              0xFFFFFFFFL
13733 //GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
13734 #define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
13735 #define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
13736 //GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
13737 #define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
13738 #define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
13739 //GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32
13740 #define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
13741 #define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
13742 //GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32
13743 #define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
13744 #define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
13745 //GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32
13746 #define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
13747 #define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
13748 //GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32
13749 #define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
13750 #define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
13751 //GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32
13752 #define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
13753 #define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
13754 //GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32
13755 #define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
13756 #define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
13757 //GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32
13758 #define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
13759 #define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
13760 //GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32
13761 #define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
13762 #define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
13763 //GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32
13764 #define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
13765 #define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
13766 //GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32
13767 #define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
13768 #define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
13769 //GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32
13770 #define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
13771 #define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
13772 //GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32
13773 #define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
13774 #define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
13775 //GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32
13776 #define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
13777 #define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
13778 //GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32
13779 #define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
13780 #define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
13781 //GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32
13782 #define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
13783 #define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
13784 //GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32
13785 #define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
13786 #define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
13787 //GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32
13788 #define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
13789 #define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
13790 //GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32
13791 #define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
13792 #define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
13793 //GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32
13794 #define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                            0x0
13795 #define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                              0xFFFFFFFFL
13796 //GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32
13797 #define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                             0x0
13798 #define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                               0x0000000FL
13799 //GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32
13800 #define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                            0x0
13801 #define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                              0xFFFFFFFFL
13802 //GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32
13803 #define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                             0x0
13804 #define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                               0x0000000FL
13805 //GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32
13806 #define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                            0x0
13807 #define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                              0xFFFFFFFFL
13808 //GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32
13809 #define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                             0x0
13810 #define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                               0x0000000FL
13811 //GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32
13812 #define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                            0x0
13813 #define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                              0xFFFFFFFFL
13814 //GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32
13815 #define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                             0x0
13816 #define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                               0x0000000FL
13817 //GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32
13818 #define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                            0x0
13819 #define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                              0xFFFFFFFFL
13820 //GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32
13821 #define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                             0x0
13822 #define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                               0x0000000FL
13823 //GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32
13824 #define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                            0x0
13825 #define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                              0xFFFFFFFFL
13826 //GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32
13827 #define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                             0x0
13828 #define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                               0x0000000FL
13829 //GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
13830 #define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
13831 #define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
13832 //GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
13833 #define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
13834 #define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
13835 //GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32
13836 #define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
13837 #define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
13838 //GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32
13839 #define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
13840 #define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
13841 //GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32
13842 #define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
13843 #define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
13844 //GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32
13845 #define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
13846 #define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
13847 //GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32
13848 #define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
13849 #define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
13850 //GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32
13851 #define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
13852 #define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
13853 //GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32
13854 #define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
13855 #define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
13856 //GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32
13857 #define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
13858 #define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
13859 //GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32
13860 #define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
13861 #define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
13862 //GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32
13863 #define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
13864 #define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
13865 //GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32
13866 #define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
13867 #define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
13868 //GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32
13869 #define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
13870 #define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
13871 //GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32
13872 #define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
13873 #define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
13874 //GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32
13875 #define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
13876 #define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
13877 //GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32
13878 #define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
13879 #define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
13880 //GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32
13881 #define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
13882 #define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
13883 //GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32
13884 #define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
13885 #define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
13886 //GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32
13887 #define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
13888 #define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
13889 //GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32
13890 #define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
13891 #define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
13892 //GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32
13893 #define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
13894 #define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
13895 //GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32
13896 #define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
13897 #define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
13898 //GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32
13899 #define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
13900 #define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
13901 //GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32
13902 #define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
13903 #define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
13904 //GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32
13905 #define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
13906 #define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
13907 //GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32
13908 #define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
13909 #define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
13910 //GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32
13911 #define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
13912 #define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
13913 //GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32
13914 #define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
13915 #define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
13916 //GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32
13917 #define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
13918 #define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
13919 //GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32
13920 #define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
13921 #define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
13922 //GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32
13923 #define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
13924 #define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
13925 
13926 
13927 // addressBlock: gc_gcvmsharedpfdec
13928 //GCMC_VM_NB_MMIOBASE
13929 #define GCMC_VM_NB_MMIOBASE__MMIOBASE__SHIFT                                                                  0x0
13930 #define GCMC_VM_NB_MMIOBASE__MMIOBASE_MASK                                                                    0xFFFFFFFFL
13931 //GCMC_VM_NB_MMIOLIMIT
13932 #define GCMC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT                                                                0x0
13933 #define GCMC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK                                                                  0xFFFFFFFFL
13934 //GCMC_VM_NB_PCI_CTRL
13935 #define GCMC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT                                                                0x17
13936 #define GCMC_VM_NB_PCI_CTRL__MMIOENABLE_MASK                                                                  0x00800000L
13937 //GCMC_VM_NB_PCI_ARB
13938 #define GCMC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT                                                                   0x3
13939 #define GCMC_VM_NB_PCI_ARB__VGA_HOLE_MASK                                                                     0x00000008L
13940 //GCMC_VM_NB_TOP_OF_DRAM_SLOT1
13941 #define GCMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT                                                      0x17
13942 #define GCMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK                                                        0xFF800000L
13943 //GCMC_VM_NB_LOWER_TOP_OF_DRAM2
13944 #define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT                                                          0x0
13945 #define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT                                                      0x17
13946 #define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK                                                            0x00000001L
13947 #define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK                                                        0xFF800000L
13948 //GCMC_VM_NB_UPPER_TOP_OF_DRAM2
13949 #define GCMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT                                                      0x0
13950 #define GCMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK                                                        0x00000FFFL
13951 //GCMC_VM_FB_OFFSET
13952 #define GCMC_VM_FB_OFFSET__FB_OFFSET__SHIFT                                                                   0x0
13953 #define GCMC_VM_FB_OFFSET__FB_OFFSET_MASK                                                                     0x00FFFFFFL
13954 //GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
13955 #define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT                             0x0
13956 #define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK                               0xFFFFFFFFL
13957 //GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB
13958 #define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT                             0x0
13959 #define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK                               0x0000000FL
13960 //GCMC_VM_STEERING
13961 #define GCMC_VM_STEERING__DEFAULT_STEERING__SHIFT                                                             0x0
13962 #define GCMC_VM_STEERING__DEFAULT_STEERING_MASK                                                               0x00000003L
13963 //GCMC_SHARED_VIRT_RESET_REQ
13964 #define GCMC_SHARED_VIRT_RESET_REQ__VF__SHIFT                                                                 0x0
13965 #define GCMC_SHARED_VIRT_RESET_REQ__PF__SHIFT                                                                 0x1f
13966 #define GCMC_SHARED_VIRT_RESET_REQ__VF_MASK                                                                   0x7FFFFFFFL
13967 #define GCMC_SHARED_VIRT_RESET_REQ__PF_MASK                                                                   0x80000000L
13968 //GCMC_MEM_POWER_LS
13969 #define GCMC_MEM_POWER_LS__LS_SETUP__SHIFT                                                                    0x0
13970 #define GCMC_MEM_POWER_LS__LS_HOLD__SHIFT                                                                     0x6
13971 #define GCMC_MEM_POWER_LS__LS_SETUP_MASK                                                                      0x0000003FL
13972 #define GCMC_MEM_POWER_LS__LS_HOLD_MASK                                                                       0x00000FC0L
13973 //GCMC_VM_CACHEABLE_DRAM_ADDRESS_START
13974 #define GCMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT                                                  0x0
13975 #define GCMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK                                                    0x000FFFFFL
13976 //GCMC_VM_CACHEABLE_DRAM_ADDRESS_END
13977 #define GCMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT                                                    0x0
13978 #define GCMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK                                                      0x000FFFFFL
13979 //GCMC_VM_APT_CNTL
13980 #define GCMC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT                                                               0x0
13981 #define GCMC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT                                                             0x1
13982 #define GCMC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK                                                                 0x00000001L
13983 #define GCMC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK                                                               0x00000002L
13984 //GCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL
13985 #define GCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT                                                      0x0
13986 #define GCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK                                                        0x00000001L
13987 //GCMC_VM_LOCAL_HBM_ADDRESS_START
13988 #define GCMC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT                                                       0x0
13989 #define GCMC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK                                                         0x000FFFFFL
13990 //GCMC_VM_LOCAL_HBM_ADDRESS_END
13991 #define GCMC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT                                                         0x0
13992 #define GCMC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK                                                           0x000FFFFFL
13993 //GCMC_SHARED_VIRT_RESET_REQ2
13994 #define GCMC_SHARED_VIRT_RESET_REQ2__VF__SHIFT                                                                0x0
13995 #define GCMC_SHARED_VIRT_RESET_REQ2__VF_MASK                                                                  0x00000001L
13996 
13997 
13998 // addressBlock: gc_gcvmsharedvcdec
13999 //GCMC_VM_FB_LOCATION_BASE
14000 #define GCMC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT                                                              0x0
14001 #define GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK                                                                0x00FFFFFFL
14002 //GCMC_VM_FB_LOCATION_TOP
14003 #define GCMC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT                                                                0x0
14004 #define GCMC_VM_FB_LOCATION_TOP__FB_TOP_MASK                                                                  0x00FFFFFFL
14005 //GCMC_VM_AGP_TOP
14006 #define GCMC_VM_AGP_TOP__AGP_TOP__SHIFT                                                                       0x0
14007 #define GCMC_VM_AGP_TOP__AGP_TOP_MASK                                                                         0x00FFFFFFL
14008 //GCMC_VM_AGP_BOT
14009 #define GCMC_VM_AGP_BOT__AGP_BOT__SHIFT                                                                       0x0
14010 #define GCMC_VM_AGP_BOT__AGP_BOT_MASK                                                                         0x00FFFFFFL
14011 //GCMC_VM_AGP_BASE
14012 #define GCMC_VM_AGP_BASE__AGP_BASE__SHIFT                                                                     0x0
14013 #define GCMC_VM_AGP_BASE__AGP_BASE_MASK                                                                       0x00FFFFFFL
14014 //GCMC_VM_SYSTEM_APERTURE_LOW_ADDR
14015 #define GCMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT                                                 0x0
14016 #define GCMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK                                                   0x3FFFFFFFL
14017 //GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR
14018 #define GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT                                                0x0
14019 #define GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK                                                  0x3FFFFFFFL
14020 //GCMC_VM_MX_L1_TLB_CNTL
14021 #define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                          0x0
14022 #define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                                     0x3
14023 #define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                        0x5
14024 #define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                           0x6
14025 #define GCMC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT                                                               0x7
14026 #define GCMC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT                                                                  0xb
14027 #define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                            0x00000001L
14028 #define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                                       0x00000018L
14029 #define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                          0x00000020L
14030 #define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                             0x00000040L
14031 #define GCMC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK                                                                 0x00000780L
14032 #define GCMC_VM_MX_L1_TLB_CNTL__MTYPE_MASK                                                                    0x00003800L
14033 
14034 
14035 // addressBlock: gc_gceadec
14036 //GCEA_DRAM_RD_CLI2GRP_MAP0
14037 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
14038 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
14039 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
14040 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
14041 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
14042 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
14043 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
14044 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
14045 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
14046 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
14047 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
14048 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
14049 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
14050 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
14051 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
14052 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
14053 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
14054 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
14055 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
14056 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
14057 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
14058 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
14059 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
14060 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
14061 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
14062 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
14063 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
14064 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
14065 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
14066 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
14067 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
14068 #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
14069 //GCEA_DRAM_RD_CLI2GRP_MAP1
14070 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
14071 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
14072 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
14073 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
14074 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
14075 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
14076 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
14077 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
14078 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
14079 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
14080 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
14081 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
14082 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
14083 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
14084 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
14085 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
14086 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
14087 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
14088 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
14089 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
14090 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
14091 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
14092 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
14093 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
14094 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
14095 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
14096 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
14097 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
14098 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
14099 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
14100 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
14101 #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
14102 //GCEA_DRAM_WR_CLI2GRP_MAP0
14103 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
14104 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
14105 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
14106 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
14107 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
14108 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
14109 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
14110 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
14111 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
14112 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
14113 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
14114 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
14115 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
14116 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
14117 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
14118 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
14119 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
14120 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
14121 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
14122 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
14123 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
14124 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
14125 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
14126 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
14127 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
14128 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
14129 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
14130 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
14131 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
14132 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
14133 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
14134 #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
14135 //GCEA_DRAM_WR_CLI2GRP_MAP1
14136 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
14137 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
14138 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
14139 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
14140 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
14141 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
14142 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
14143 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
14144 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
14145 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
14146 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
14147 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
14148 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
14149 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
14150 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
14151 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
14152 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
14153 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
14154 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
14155 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
14156 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
14157 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
14158 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
14159 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
14160 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
14161 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
14162 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
14163 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
14164 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
14165 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
14166 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
14167 #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
14168 //GCEA_DRAM_RD_GRP2VC_MAP
14169 #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
14170 #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
14171 #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
14172 #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
14173 #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
14174 #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
14175 #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
14176 #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
14177 //GCEA_DRAM_WR_GRP2VC_MAP
14178 #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
14179 #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
14180 #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
14181 #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
14182 #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
14183 #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
14184 #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
14185 #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
14186 //GCEA_DRAM_RD_LAZY
14187 #define GCEA_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
14188 #define GCEA_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
14189 #define GCEA_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
14190 #define GCEA_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
14191 #define GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
14192 #define GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
14193 #define GCEA_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
14194 #define GCEA_DRAM_RD_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
14195 #define GCEA_DRAM_RD_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
14196 #define GCEA_DRAM_RD_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
14197 #define GCEA_DRAM_RD_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
14198 #define GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
14199 #define GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
14200 #define GCEA_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
14201 //GCEA_DRAM_WR_LAZY
14202 #define GCEA_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
14203 #define GCEA_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
14204 #define GCEA_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
14205 #define GCEA_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
14206 #define GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
14207 #define GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
14208 #define GCEA_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
14209 #define GCEA_DRAM_WR_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
14210 #define GCEA_DRAM_WR_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
14211 #define GCEA_DRAM_WR_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
14212 #define GCEA_DRAM_WR_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
14213 #define GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
14214 #define GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
14215 #define GCEA_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
14216 //GCEA_DRAM_RD_CAM_CNTL
14217 #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
14218 #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
14219 #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
14220 #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
14221 #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
14222 #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
14223 #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
14224 #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
14225 #define GCEA_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
14226 #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
14227 #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
14228 #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
14229 #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
14230 #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
14231 #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
14232 #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
14233 #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
14234 #define GCEA_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
14235 //GCEA_DRAM_WR_CAM_CNTL
14236 #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
14237 #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
14238 #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
14239 #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
14240 #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
14241 #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
14242 #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
14243 #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
14244 #define GCEA_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
14245 #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
14246 #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
14247 #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
14248 #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
14249 #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
14250 #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
14251 #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
14252 #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
14253 #define GCEA_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
14254 //GCEA_DRAM_PAGE_BURST
14255 #define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
14256 #define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
14257 #define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
14258 #define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
14259 #define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
14260 #define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
14261 #define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
14262 #define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
14263 //GCEA_DRAM_RD_PRI_AGE
14264 #define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
14265 #define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
14266 #define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
14267 #define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
14268 #define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
14269 #define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
14270 #define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
14271 #define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
14272 #define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
14273 #define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
14274 #define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
14275 #define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
14276 #define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
14277 #define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
14278 #define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
14279 #define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
14280 //GCEA_DRAM_WR_PRI_AGE
14281 #define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
14282 #define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
14283 #define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
14284 #define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
14285 #define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
14286 #define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
14287 #define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
14288 #define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
14289 #define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
14290 #define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
14291 #define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
14292 #define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
14293 #define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
14294 #define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
14295 #define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
14296 #define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
14297 //GCEA_DRAM_RD_PRI_QUEUING
14298 #define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
14299 #define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
14300 #define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
14301 #define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
14302 #define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
14303 #define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
14304 #define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
14305 #define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
14306 //GCEA_DRAM_WR_PRI_QUEUING
14307 #define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
14308 #define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
14309 #define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
14310 #define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
14311 #define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
14312 #define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
14313 #define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
14314 #define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
14315 //GCEA_DRAM_RD_PRI_FIXED
14316 #define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
14317 #define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
14318 #define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
14319 #define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
14320 #define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
14321 #define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
14322 #define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
14323 #define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
14324 //GCEA_DRAM_WR_PRI_FIXED
14325 #define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
14326 #define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
14327 #define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
14328 #define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
14329 #define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
14330 #define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
14331 #define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
14332 #define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
14333 //GCEA_DRAM_RD_PRI_URGENCY
14334 #define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
14335 #define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
14336 #define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
14337 #define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
14338 #define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
14339 #define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
14340 #define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
14341 #define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
14342 #define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
14343 #define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
14344 #define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
14345 #define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
14346 #define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
14347 #define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
14348 #define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
14349 #define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
14350 //GCEA_DRAM_WR_PRI_URGENCY
14351 #define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
14352 #define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
14353 #define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
14354 #define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
14355 #define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
14356 #define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
14357 #define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
14358 #define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
14359 #define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
14360 #define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
14361 #define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
14362 #define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
14363 #define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
14364 #define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
14365 #define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
14366 #define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
14367 //GCEA_DRAM_RD_PRI_QUANT_PRI1
14368 #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
14369 #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
14370 #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
14371 #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
14372 #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
14373 #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
14374 #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
14375 #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
14376 //GCEA_DRAM_RD_PRI_QUANT_PRI2
14377 #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
14378 #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
14379 #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
14380 #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
14381 #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
14382 #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
14383 #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
14384 #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
14385 //GCEA_DRAM_RD_PRI_QUANT_PRI3
14386 #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
14387 #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
14388 #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
14389 #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
14390 #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
14391 #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
14392 #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
14393 #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
14394 //GCEA_DRAM_WR_PRI_QUANT_PRI1
14395 #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
14396 #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
14397 #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
14398 #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
14399 #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
14400 #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
14401 #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
14402 #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
14403 //GCEA_DRAM_WR_PRI_QUANT_PRI2
14404 #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
14405 #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
14406 #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
14407 #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
14408 #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
14409 #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
14410 #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
14411 #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
14412 //GCEA_DRAM_WR_PRI_QUANT_PRI3
14413 #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
14414 #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
14415 #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
14416 #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
14417 #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
14418 #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
14419 #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
14420 #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
14421 //GCEA_ADDRNORM_BASE_ADDR0
14422 #define GCEA_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT                                                         0x0
14423 #define GCEA_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT                                                    0x1
14424 #define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT                                                       0x2
14425 #define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT                                                       0x6
14426 #define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT                                                    0x8
14427 #define GCEA_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT                                                       0x9
14428 #define GCEA_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT                                                            0xc
14429 #define GCEA_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK                                                           0x00000001L
14430 #define GCEA_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK                                                      0x00000002L
14431 #define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK                                                         0x0000003CL
14432 #define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK                                                         0x000000C0L
14433 #define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK                                                      0x00000100L
14434 #define GCEA_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK                                                         0x00000E00L
14435 #define GCEA_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK                                                              0xFFFFF000L
14436 //GCEA_ADDRNORM_LIMIT_ADDR0
14437 #define GCEA_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT                                                       0x0
14438 #define GCEA_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT                                                          0xc
14439 #define GCEA_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK                                                         0x0000001FL
14440 #define GCEA_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK                                                            0xFFFFF000L
14441 //GCEA_ADDRNORM_BASE_ADDR1
14442 #define GCEA_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT                                                         0x0
14443 #define GCEA_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT                                                    0x1
14444 #define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT                                                       0x2
14445 #define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT                                                       0x6
14446 #define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT                                                    0x8
14447 #define GCEA_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT                                                       0x9
14448 #define GCEA_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT                                                            0xc
14449 #define GCEA_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK                                                           0x00000001L
14450 #define GCEA_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK                                                      0x00000002L
14451 #define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK                                                         0x0000003CL
14452 #define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK                                                         0x000000C0L
14453 #define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK                                                      0x00000100L
14454 #define GCEA_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK                                                         0x00000E00L
14455 #define GCEA_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK                                                              0xFFFFF000L
14456 //GCEA_ADDRNORM_LIMIT_ADDR1
14457 #define GCEA_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT                                                       0x0
14458 #define GCEA_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT                                                          0xc
14459 #define GCEA_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK                                                         0x0000001FL
14460 #define GCEA_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK                                                            0xFFFFF000L
14461 //GCEA_ADDRNORM_OFFSET_ADDR1
14462 #define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT                                                  0x0
14463 #define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT                                                     0x14
14464 #define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK                                                    0x00000001L
14465 #define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK                                                       0xFFF00000L
14466 //GCEA_ADDRNORMDRAM_HOLE_CNTL
14467 #define GCEA_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                   0x0
14468 #define GCEA_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                  0x7
14469 #define GCEA_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                     0x00000001L
14470 #define GCEA_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                    0x0000FF80L
14471 //GCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG
14472 #define GCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT                                         0x0
14473 #define GCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT                                         0x6
14474 #define GCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK                                           0x0000003FL
14475 #define GCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK                                           0x00000FC0L
14476 //GCEA_ADDRDEC_BANK_CFG
14477 #define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT                                                          0x0
14478 #define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT                                                           0x5
14479 #define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT                                                      0xa
14480 #define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT                                                       0xd
14481 #define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT                                               0x10
14482 #define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT                                                0x11
14483 #define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK                                                            0x0000001FL
14484 #define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK                                                             0x000003E0L
14485 #define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK                                                        0x00001C00L
14486 #define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK                                                         0x0000E000L
14487 #define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK                                                 0x00010000L
14488 #define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK                                                  0x00020000L
14489 //GCEA_ADDRDEC_MISC_CFG
14490 #define GCEA_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT                                                                 0x0
14491 #define GCEA_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT                                                                 0x1
14492 #define GCEA_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT                                                                 0x2
14493 #define GCEA_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT                                                                 0x3
14494 #define GCEA_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT                                                                 0x4
14495 #define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT                                                           0x8
14496 #define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT                                                            0x9
14497 #define GCEA_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT                                                            0xc
14498 #define GCEA_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT                                                             0x11
14499 #define GCEA_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT                                                            0x16
14500 #define GCEA_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT                                                             0x18
14501 #define GCEA_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT                                                            0x1a
14502 #define GCEA_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT                                                             0x1d
14503 #define GCEA_ADDRDEC_MISC_CFG__VCM_EN0_MASK                                                                   0x00000001L
14504 #define GCEA_ADDRDEC_MISC_CFG__VCM_EN1_MASK                                                                   0x00000002L
14505 #define GCEA_ADDRDEC_MISC_CFG__VCM_EN2_MASK                                                                   0x00000004L
14506 #define GCEA_ADDRDEC_MISC_CFG__VCM_EN3_MASK                                                                   0x00000008L
14507 #define GCEA_ADDRDEC_MISC_CFG__VCM_EN4_MASK                                                                   0x00000010L
14508 #define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK                                                             0x00000100L
14509 #define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK                                                              0x00000200L
14510 #define GCEA_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK                                                              0x0001F000L
14511 #define GCEA_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK                                                               0x003E0000L
14512 #define GCEA_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK                                                              0x00C00000L
14513 #define GCEA_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK                                                               0x03000000L
14514 #define GCEA_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK                                                              0x1C000000L
14515 #define GCEA_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK                                                               0xE0000000L
14516 //GCEA_ADDRDECDRAM_ADDR_HASH_BANK0
14517 #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT                                                   0x0
14518 #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT                                                      0x1
14519 #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT                                                      0xe
14520 #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK                                                     0x00000001L
14521 #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK                                                        0x00003FFEL
14522 #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK                                                        0xFFFFC000L
14523 //GCEA_ADDRDECDRAM_ADDR_HASH_BANK1
14524 #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT                                                   0x0
14525 #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT                                                      0x1
14526 #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT                                                      0xe
14527 #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK                                                     0x00000001L
14528 #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK                                                        0x00003FFEL
14529 #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK                                                        0xFFFFC000L
14530 //GCEA_ADDRDECDRAM_ADDR_HASH_BANK2
14531 #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT                                                   0x0
14532 #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT                                                      0x1
14533 #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT                                                      0xe
14534 #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK                                                     0x00000001L
14535 #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK                                                        0x00003FFEL
14536 #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK                                                        0xFFFFC000L
14537 //GCEA_ADDRDECDRAM_ADDR_HASH_BANK3
14538 #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT                                                   0x0
14539 #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT                                                      0x1
14540 #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT                                                      0xe
14541 #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK                                                     0x00000001L
14542 #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK                                                        0x00003FFEL
14543 #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK                                                        0xFFFFC000L
14544 //GCEA_ADDRDECDRAM_ADDR_HASH_BANK4
14545 #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT                                                   0x0
14546 #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT                                                      0x1
14547 #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT                                                      0xe
14548 #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK                                                     0x00000001L
14549 #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK                                                        0x00003FFEL
14550 #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK                                                        0xFFFFC000L
14551 //GCEA_ADDRDECDRAM_ADDR_HASH_PC
14552 #define GCEA_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT                                                      0x0
14553 #define GCEA_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT                                                         0x1
14554 #define GCEA_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT                                                         0xe
14555 #define GCEA_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK                                                        0x00000001L
14556 #define GCEA_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK                                                           0x00003FFEL
14557 #define GCEA_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK                                                           0xFFFFC000L
14558 //GCEA_ADDRDECDRAM_ADDR_HASH_PC2
14559 #define GCEA_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT                                                       0x0
14560 #define GCEA_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK                                                         0x0000001FL
14561 //GCEA_ADDRDECDRAM_ADDR_HASH_CS0
14562 #define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT                                                     0x0
14563 #define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT                                                         0x1
14564 #define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK                                                       0x00000001L
14565 #define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK                                                           0xFFFFFFFEL
14566 //GCEA_ADDRDECDRAM_ADDR_HASH_CS1
14567 #define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT                                                     0x0
14568 #define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT                                                         0x1
14569 #define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK                                                       0x00000001L
14570 #define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK                                                           0xFFFFFFFEL
14571 //GCEA_ADDRDECDRAM_HARVEST_ENABLE
14572 #define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                   0x0
14573 #define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                  0x1
14574 #define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                   0x2
14575 #define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                  0x3
14576 #define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                     0x00000001L
14577 #define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                    0x00000002L
14578 #define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                     0x00000004L
14579 #define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                    0x00000008L
14580 //GCEA_ADDRDECDRAM_HARVNA_ADDR_START0
14581 #define GCEA_ADDRDECDRAM_HARVNA_ADDR_START0__START__SHIFT                                                     0x0
14582 #define GCEA_ADDRDECDRAM_HARVNA_ADDR_START0__BANK_XOR__SHIFT                                                  0x1c
14583 #define GCEA_ADDRDECDRAM_HARVNA_ADDR_START0__START_MASK                                                       0x000FFFFFL
14584 #define GCEA_ADDRDECDRAM_HARVNA_ADDR_START0__BANK_XOR_MASK                                                    0xF0000000L
14585 //GCEA_ADDRDECDRAM_HARVNA_ADDR_END0
14586 #define GCEA_ADDRDECDRAM_HARVNA_ADDR_END0__END__SHIFT                                                         0x0
14587 #define GCEA_ADDRDECDRAM_HARVNA_ADDR_END0__END_MASK                                                           0x000FFFFFL
14588 //GCEA_ADDRDECDRAM_HARVNA_ADDR_START1
14589 #define GCEA_ADDRDECDRAM_HARVNA_ADDR_START1__START__SHIFT                                                     0x0
14590 #define GCEA_ADDRDECDRAM_HARVNA_ADDR_START1__BANK_XOR__SHIFT                                                  0x1c
14591 #define GCEA_ADDRDECDRAM_HARVNA_ADDR_START1__START_MASK                                                       0x000FFFFFL
14592 #define GCEA_ADDRDECDRAM_HARVNA_ADDR_START1__BANK_XOR_MASK                                                    0xF0000000L
14593 //GCEA_ADDRDECDRAM_HARVNA_ADDR_END1
14594 #define GCEA_ADDRDECDRAM_HARVNA_ADDR_END1__END__SHIFT                                                         0x0
14595 #define GCEA_ADDRDECDRAM_HARVNA_ADDR_END1__END_MASK                                                           0x000FFFFFL
14596 //GCEA_ADDRDEC0_BASE_ADDR_CS0
14597 #define GCEA_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT                                                             0x0
14598 #define GCEA_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                         0x1
14599 #define GCEA_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK                                                               0x00000001L
14600 #define GCEA_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK                                                           0xFFFFFFFEL
14601 //GCEA_ADDRDEC0_BASE_ADDR_CS1
14602 #define GCEA_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT                                                             0x0
14603 #define GCEA_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                         0x1
14604 #define GCEA_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK                                                               0x00000001L
14605 #define GCEA_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK                                                           0xFFFFFFFEL
14606 //GCEA_ADDRDEC0_BASE_ADDR_CS2
14607 #define GCEA_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT                                                             0x0
14608 #define GCEA_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                         0x1
14609 #define GCEA_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK                                                               0x00000001L
14610 #define GCEA_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK                                                           0xFFFFFFFEL
14611 //GCEA_ADDRDEC0_BASE_ADDR_CS3
14612 #define GCEA_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT                                                             0x0
14613 #define GCEA_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                         0x1
14614 #define GCEA_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK                                                               0x00000001L
14615 #define GCEA_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK                                                           0xFFFFFFFEL
14616 //GCEA_ADDRDEC0_BASE_ADDR_SECCS0
14617 #define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                          0x0
14618 #define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                      0x1
14619 #define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK                                                            0x00000001L
14620 #define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                        0xFFFFFFFEL
14621 //GCEA_ADDRDEC0_BASE_ADDR_SECCS1
14622 #define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                          0x0
14623 #define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                      0x1
14624 #define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK                                                            0x00000001L
14625 #define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                        0xFFFFFFFEL
14626 //GCEA_ADDRDEC0_BASE_ADDR_SECCS2
14627 #define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                          0x0
14628 #define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                      0x1
14629 #define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK                                                            0x00000001L
14630 #define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                        0xFFFFFFFEL
14631 //GCEA_ADDRDEC0_BASE_ADDR_SECCS3
14632 #define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                          0x0
14633 #define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                      0x1
14634 #define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK                                                            0x00000001L
14635 #define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                        0xFFFFFFFEL
14636 //GCEA_ADDRDEC0_ADDR_MASK_CS01
14637 #define GCEA_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                        0x1
14638 #define GCEA_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK                                                          0xFFFFFFFEL
14639 //GCEA_ADDRDEC0_ADDR_MASK_CS23
14640 #define GCEA_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                        0x1
14641 #define GCEA_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK                                                          0xFFFFFFFEL
14642 //GCEA_ADDRDEC0_ADDR_MASK_SECCS01
14643 #define GCEA_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                     0x1
14644 #define GCEA_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                       0xFFFFFFFEL
14645 //GCEA_ADDRDEC0_ADDR_MASK_SECCS23
14646 #define GCEA_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                     0x1
14647 #define GCEA_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                       0xFFFFFFFEL
14648 //GCEA_ADDRDEC0_ADDR_CFG_CS01
14649 #define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                   0x2
14650 #define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT                                                            0x4
14651 #define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                        0x8
14652 #define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                        0xc
14653 #define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT                                                           0x10
14654 #define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                         0x14
14655 #define GCEA_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                         0x1f
14656 #define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                     0x0000000CL
14657 #define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK                                                              0x00000030L
14658 #define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                          0x00000F00L
14659 #define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                          0x0000F000L
14660 #define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK                                                             0x000F0000L
14661 #define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK                                                           0x00300000L
14662 #define GCEA_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK                                                           0x80000000L
14663 //GCEA_ADDRDEC0_ADDR_CFG_CS23
14664 #define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                   0x2
14665 #define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT                                                            0x4
14666 #define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                        0x8
14667 #define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                        0xc
14668 #define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT                                                           0x10
14669 #define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                         0x14
14670 #define GCEA_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                         0x1f
14671 #define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                     0x0000000CL
14672 #define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK                                                              0x00000030L
14673 #define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                          0x00000F00L
14674 #define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                          0x0000F000L
14675 #define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK                                                             0x000F0000L
14676 #define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK                                                           0x00300000L
14677 #define GCEA_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK                                                           0x80000000L
14678 //GCEA_ADDRDEC0_ADDR_SEL_CS01
14679 #define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT                                                             0x0
14680 #define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT                                                             0x4
14681 #define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT                                                             0x8
14682 #define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT                                                             0xc
14683 #define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT                                                             0x10
14684 #define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT                                                            0x18
14685 #define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT                                                            0x1c
14686 #define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK                                                               0x0000000FL
14687 #define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK                                                               0x000000F0L
14688 #define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK                                                               0x00000F00L
14689 #define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK                                                               0x0000F000L
14690 #define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK                                                               0x001F0000L
14691 #define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK                                                              0x0F000000L
14692 #define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK                                                              0xF0000000L
14693 //GCEA_ADDRDEC0_ADDR_SEL_CS23
14694 #define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT                                                             0x0
14695 #define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT                                                             0x4
14696 #define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT                                                             0x8
14697 #define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT                                                             0xc
14698 #define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT                                                             0x10
14699 #define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT                                                            0x18
14700 #define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT                                                            0x1c
14701 #define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK                                                               0x0000000FL
14702 #define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK                                                               0x000000F0L
14703 #define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK                                                               0x00000F00L
14704 #define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK                                                               0x0000F000L
14705 #define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK                                                               0x001F0000L
14706 #define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK                                                              0x0F000000L
14707 #define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK                                                              0xF0000000L
14708 //GCEA_ADDRDEC0_COL_SEL_LO_CS01
14709 #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT                                                            0x0
14710 #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT                                                            0x4
14711 #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT                                                            0x8
14712 #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT                                                            0xc
14713 #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT                                                            0x10
14714 #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT                                                            0x14
14715 #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT                                                            0x18
14716 #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT                                                            0x1c
14717 #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK                                                              0x0000000FL
14718 #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK                                                              0x000000F0L
14719 #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK                                                              0x00000F00L
14720 #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK                                                              0x0000F000L
14721 #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK                                                              0x000F0000L
14722 #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK                                                              0x00F00000L
14723 #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK                                                              0x0F000000L
14724 #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK                                                              0xF0000000L
14725 //GCEA_ADDRDEC0_COL_SEL_LO_CS23
14726 #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT                                                            0x0
14727 #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT                                                            0x4
14728 #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT                                                            0x8
14729 #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT                                                            0xc
14730 #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT                                                            0x10
14731 #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT                                                            0x14
14732 #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT                                                            0x18
14733 #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT                                                            0x1c
14734 #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK                                                              0x0000000FL
14735 #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK                                                              0x000000F0L
14736 #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK                                                              0x00000F00L
14737 #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK                                                              0x0000F000L
14738 #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK                                                              0x000F0000L
14739 #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK                                                              0x00F00000L
14740 #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK                                                              0x0F000000L
14741 #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK                                                              0xF0000000L
14742 //GCEA_ADDRDEC0_COL_SEL_HI_CS01
14743 #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT                                                            0x0
14744 #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT                                                            0x4
14745 #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT                                                           0x8
14746 #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT                                                           0xc
14747 #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT                                                           0x10
14748 #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT                                                           0x14
14749 #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT                                                           0x18
14750 #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT                                                           0x1c
14751 #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK                                                              0x0000000FL
14752 #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK                                                              0x000000F0L
14753 #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK                                                             0x00000F00L
14754 #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK                                                             0x0000F000L
14755 #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK                                                             0x000F0000L
14756 #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK                                                             0x00F00000L
14757 #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK                                                             0x0F000000L
14758 #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK                                                             0xF0000000L
14759 //GCEA_ADDRDEC0_COL_SEL_HI_CS23
14760 #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT                                                            0x0
14761 #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT                                                            0x4
14762 #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT                                                           0x8
14763 #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT                                                           0xc
14764 #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT                                                           0x10
14765 #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT                                                           0x14
14766 #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT                                                           0x18
14767 #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT                                                           0x1c
14768 #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK                                                              0x0000000FL
14769 #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK                                                              0x000000F0L
14770 #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK                                                             0x00000F00L
14771 #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK                                                             0x0000F000L
14772 #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK                                                             0x000F0000L
14773 #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK                                                             0x00F00000L
14774 #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK                                                             0x0F000000L
14775 #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK                                                             0xF0000000L
14776 //GCEA_ADDRDEC0_RM_SEL_CS01
14777 #define GCEA_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT                                                                 0x0
14778 #define GCEA_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT                                                                 0x4
14779 #define GCEA_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT                                                                 0x8
14780 #define GCEA_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT                                                            0xc
14781 #define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                                0x10
14782 #define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                 0x12
14783 #define GCEA_ADDRDEC0_RM_SEL_CS01__RM0_MASK                                                                   0x0000000FL
14784 #define GCEA_ADDRDEC0_RM_SEL_CS01__RM1_MASK                                                                   0x000000F0L
14785 #define GCEA_ADDRDEC0_RM_SEL_CS01__RM2_MASK                                                                   0x00000F00L
14786 #define GCEA_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK                                                              0x0000F000L
14787 #define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                  0x00030000L
14788 #define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                   0x000C0000L
14789 //GCEA_ADDRDEC0_RM_SEL_CS23
14790 #define GCEA_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT                                                                 0x0
14791 #define GCEA_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT                                                                 0x4
14792 #define GCEA_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT                                                                 0x8
14793 #define GCEA_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT                                                            0xc
14794 #define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                                0x10
14795 #define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                 0x12
14796 #define GCEA_ADDRDEC0_RM_SEL_CS23__RM0_MASK                                                                   0x0000000FL
14797 #define GCEA_ADDRDEC0_RM_SEL_CS23__RM1_MASK                                                                   0x000000F0L
14798 #define GCEA_ADDRDEC0_RM_SEL_CS23__RM2_MASK                                                                   0x00000F00L
14799 #define GCEA_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK                                                              0x0000F000L
14800 #define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                  0x00030000L
14801 #define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                   0x000C0000L
14802 //GCEA_ADDRDEC0_RM_SEL_SECCS01
14803 #define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT                                                              0x0
14804 #define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT                                                              0x4
14805 #define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT                                                              0x8
14806 #define GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                         0xc
14807 #define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                             0x10
14808 #define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                              0x12
14809 #define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK                                                                0x0000000FL
14810 #define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK                                                                0x000000F0L
14811 #define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK                                                                0x00000F00L
14812 #define GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK                                                           0x0000F000L
14813 #define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                               0x00030000L
14814 #define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                                0x000C0000L
14815 //GCEA_ADDRDEC0_RM_SEL_SECCS23
14816 #define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT                                                              0x0
14817 #define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT                                                              0x4
14818 #define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT                                                              0x8
14819 #define GCEA_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                         0xc
14820 #define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                             0x10
14821 #define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                              0x12
14822 #define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK                                                                0x0000000FL
14823 #define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK                                                                0x000000F0L
14824 #define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK                                                                0x00000F00L
14825 #define GCEA_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK                                                           0x0000F000L
14826 #define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                               0x00030000L
14827 #define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                                0x000C0000L
14828 //GCEA_ADDRDEC1_BASE_ADDR_CS0
14829 #define GCEA_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT                                                             0x0
14830 #define GCEA_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                         0x1
14831 #define GCEA_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK                                                               0x00000001L
14832 #define GCEA_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK                                                           0xFFFFFFFEL
14833 //GCEA_ADDRDEC1_BASE_ADDR_CS1
14834 #define GCEA_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT                                                             0x0
14835 #define GCEA_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                         0x1
14836 #define GCEA_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK                                                               0x00000001L
14837 #define GCEA_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK                                                           0xFFFFFFFEL
14838 //GCEA_ADDRDEC1_BASE_ADDR_CS2
14839 #define GCEA_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT                                                             0x0
14840 #define GCEA_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                         0x1
14841 #define GCEA_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK                                                               0x00000001L
14842 #define GCEA_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK                                                           0xFFFFFFFEL
14843 //GCEA_ADDRDEC1_BASE_ADDR_CS3
14844 #define GCEA_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT                                                             0x0
14845 #define GCEA_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                         0x1
14846 #define GCEA_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK                                                               0x00000001L
14847 #define GCEA_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK                                                           0xFFFFFFFEL
14848 //GCEA_ADDRDEC1_BASE_ADDR_SECCS0
14849 #define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                          0x0
14850 #define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                      0x1
14851 #define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK                                                            0x00000001L
14852 #define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                        0xFFFFFFFEL
14853 //GCEA_ADDRDEC1_BASE_ADDR_SECCS1
14854 #define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                          0x0
14855 #define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                      0x1
14856 #define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK                                                            0x00000001L
14857 #define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                        0xFFFFFFFEL
14858 //GCEA_ADDRDEC1_BASE_ADDR_SECCS2
14859 #define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                          0x0
14860 #define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                      0x1
14861 #define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK                                                            0x00000001L
14862 #define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                        0xFFFFFFFEL
14863 //GCEA_ADDRDEC1_BASE_ADDR_SECCS3
14864 #define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                          0x0
14865 #define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                      0x1
14866 #define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK                                                            0x00000001L
14867 #define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                        0xFFFFFFFEL
14868 //GCEA_ADDRDEC1_ADDR_MASK_CS01
14869 #define GCEA_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                        0x1
14870 #define GCEA_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK                                                          0xFFFFFFFEL
14871 //GCEA_ADDRDEC1_ADDR_MASK_CS23
14872 #define GCEA_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                        0x1
14873 #define GCEA_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK                                                          0xFFFFFFFEL
14874 //GCEA_ADDRDEC1_ADDR_MASK_SECCS01
14875 #define GCEA_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                     0x1
14876 #define GCEA_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                       0xFFFFFFFEL
14877 //GCEA_ADDRDEC1_ADDR_MASK_SECCS23
14878 #define GCEA_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                     0x1
14879 #define GCEA_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                       0xFFFFFFFEL
14880 //GCEA_ADDRDEC1_ADDR_CFG_CS01
14881 #define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                   0x2
14882 #define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT                                                            0x4
14883 #define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                        0x8
14884 #define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                        0xc
14885 #define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT                                                           0x10
14886 #define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                         0x14
14887 #define GCEA_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                         0x1f
14888 #define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                     0x0000000CL
14889 #define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK                                                              0x00000030L
14890 #define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                          0x00000F00L
14891 #define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                          0x0000F000L
14892 #define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK                                                             0x000F0000L
14893 #define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK                                                           0x00300000L
14894 #define GCEA_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK                                                           0x80000000L
14895 //GCEA_ADDRDEC1_ADDR_CFG_CS23
14896 #define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                   0x2
14897 #define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT                                                            0x4
14898 #define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                        0x8
14899 #define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                        0xc
14900 #define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT                                                           0x10
14901 #define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                         0x14
14902 #define GCEA_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                         0x1f
14903 #define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                     0x0000000CL
14904 #define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK                                                              0x00000030L
14905 #define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                          0x00000F00L
14906 #define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                          0x0000F000L
14907 #define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK                                                             0x000F0000L
14908 #define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK                                                           0x00300000L
14909 #define GCEA_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK                                                           0x80000000L
14910 //GCEA_ADDRDEC1_ADDR_SEL_CS01
14911 #define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT                                                             0x0
14912 #define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT                                                             0x4
14913 #define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT                                                             0x8
14914 #define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT                                                             0xc
14915 #define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT                                                             0x10
14916 #define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT                                                            0x18
14917 #define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT                                                            0x1c
14918 #define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK                                                               0x0000000FL
14919 #define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK                                                               0x000000F0L
14920 #define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK                                                               0x00000F00L
14921 #define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK                                                               0x0000F000L
14922 #define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK                                                               0x001F0000L
14923 #define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK                                                              0x0F000000L
14924 #define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK                                                              0xF0000000L
14925 //GCEA_ADDRDEC1_ADDR_SEL_CS23
14926 #define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT                                                             0x0
14927 #define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT                                                             0x4
14928 #define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT                                                             0x8
14929 #define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT                                                             0xc
14930 #define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT                                                             0x10
14931 #define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT                                                            0x18
14932 #define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT                                                            0x1c
14933 #define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK                                                               0x0000000FL
14934 #define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK                                                               0x000000F0L
14935 #define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK                                                               0x00000F00L
14936 #define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK                                                               0x0000F000L
14937 #define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK                                                               0x001F0000L
14938 #define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK                                                              0x0F000000L
14939 #define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK                                                              0xF0000000L
14940 //GCEA_ADDRDEC1_COL_SEL_LO_CS01
14941 #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT                                                            0x0
14942 #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT                                                            0x4
14943 #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT                                                            0x8
14944 #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT                                                            0xc
14945 #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT                                                            0x10
14946 #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT                                                            0x14
14947 #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT                                                            0x18
14948 #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT                                                            0x1c
14949 #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK                                                              0x0000000FL
14950 #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK                                                              0x000000F0L
14951 #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK                                                              0x00000F00L
14952 #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK                                                              0x0000F000L
14953 #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK                                                              0x000F0000L
14954 #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK                                                              0x00F00000L
14955 #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK                                                              0x0F000000L
14956 #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK                                                              0xF0000000L
14957 //GCEA_ADDRDEC1_COL_SEL_LO_CS23
14958 #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT                                                            0x0
14959 #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT                                                            0x4
14960 #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT                                                            0x8
14961 #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT                                                            0xc
14962 #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT                                                            0x10
14963 #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT                                                            0x14
14964 #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT                                                            0x18
14965 #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT                                                            0x1c
14966 #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK                                                              0x0000000FL
14967 #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK                                                              0x000000F0L
14968 #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK                                                              0x00000F00L
14969 #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK                                                              0x0000F000L
14970 #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK                                                              0x000F0000L
14971 #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK                                                              0x00F00000L
14972 #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK                                                              0x0F000000L
14973 #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK                                                              0xF0000000L
14974 //GCEA_ADDRDEC1_COL_SEL_HI_CS01
14975 #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT                                                            0x0
14976 #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT                                                            0x4
14977 #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT                                                           0x8
14978 #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT                                                           0xc
14979 #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT                                                           0x10
14980 #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT                                                           0x14
14981 #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT                                                           0x18
14982 #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT                                                           0x1c
14983 #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK                                                              0x0000000FL
14984 #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK                                                              0x000000F0L
14985 #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK                                                             0x00000F00L
14986 #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK                                                             0x0000F000L
14987 #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK                                                             0x000F0000L
14988 #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK                                                             0x00F00000L
14989 #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK                                                             0x0F000000L
14990 #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK                                                             0xF0000000L
14991 //GCEA_ADDRDEC1_COL_SEL_HI_CS23
14992 #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT                                                            0x0
14993 #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT                                                            0x4
14994 #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT                                                           0x8
14995 #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT                                                           0xc
14996 #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT                                                           0x10
14997 #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT                                                           0x14
14998 #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT                                                           0x18
14999 #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT                                                           0x1c
15000 #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK                                                              0x0000000FL
15001 #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK                                                              0x000000F0L
15002 #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK                                                             0x00000F00L
15003 #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK                                                             0x0000F000L
15004 #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK                                                             0x000F0000L
15005 #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK                                                             0x00F00000L
15006 #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK                                                             0x0F000000L
15007 #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK                                                             0xF0000000L
15008 //GCEA_ADDRDEC1_RM_SEL_CS01
15009 #define GCEA_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT                                                                 0x0
15010 #define GCEA_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT                                                                 0x4
15011 #define GCEA_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT                                                                 0x8
15012 #define GCEA_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT                                                            0xc
15013 #define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                                0x10
15014 #define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                 0x12
15015 #define GCEA_ADDRDEC1_RM_SEL_CS01__RM0_MASK                                                                   0x0000000FL
15016 #define GCEA_ADDRDEC1_RM_SEL_CS01__RM1_MASK                                                                   0x000000F0L
15017 #define GCEA_ADDRDEC1_RM_SEL_CS01__RM2_MASK                                                                   0x00000F00L
15018 #define GCEA_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK                                                              0x0000F000L
15019 #define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                  0x00030000L
15020 #define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                   0x000C0000L
15021 //GCEA_ADDRDEC1_RM_SEL_CS23
15022 #define GCEA_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT                                                                 0x0
15023 #define GCEA_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT                                                                 0x4
15024 #define GCEA_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT                                                                 0x8
15025 #define GCEA_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT                                                            0xc
15026 #define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                                0x10
15027 #define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                 0x12
15028 #define GCEA_ADDRDEC1_RM_SEL_CS23__RM0_MASK                                                                   0x0000000FL
15029 #define GCEA_ADDRDEC1_RM_SEL_CS23__RM1_MASK                                                                   0x000000F0L
15030 #define GCEA_ADDRDEC1_RM_SEL_CS23__RM2_MASK                                                                   0x00000F00L
15031 #define GCEA_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK                                                              0x0000F000L
15032 #define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                  0x00030000L
15033 #define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                   0x000C0000L
15034 //GCEA_ADDRDEC1_RM_SEL_SECCS01
15035 #define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT                                                              0x0
15036 #define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT                                                              0x4
15037 #define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT                                                              0x8
15038 #define GCEA_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                         0xc
15039 #define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                             0x10
15040 #define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                              0x12
15041 #define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK                                                                0x0000000FL
15042 #define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK                                                                0x000000F0L
15043 #define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK                                                                0x00000F00L
15044 #define GCEA_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK                                                           0x0000F000L
15045 #define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                               0x00030000L
15046 #define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                                0x000C0000L
15047 //GCEA_ADDRDEC1_RM_SEL_SECCS23
15048 #define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT                                                              0x0
15049 #define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT                                                              0x4
15050 #define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT                                                              0x8
15051 #define GCEA_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                         0xc
15052 #define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                             0x10
15053 #define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                              0x12
15054 #define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK                                                                0x0000000FL
15055 #define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK                                                                0x000000F0L
15056 #define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK                                                                0x00000F00L
15057 #define GCEA_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK                                                           0x0000F000L
15058 #define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                               0x00030000L
15059 #define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                                0x000C0000L
15060 //GCEA_IO_RD_CLI2GRP_MAP0
15061 #define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                            0x0
15062 #define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                            0x2
15063 #define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                            0x4
15064 #define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                            0x6
15065 #define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                            0x8
15066 #define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                            0xa
15067 #define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                            0xc
15068 #define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                            0xe
15069 #define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                            0x10
15070 #define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                            0x12
15071 #define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                           0x14
15072 #define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                           0x16
15073 #define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                           0x18
15074 #define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                           0x1a
15075 #define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                           0x1c
15076 #define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                           0x1e
15077 #define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                              0x00000003L
15078 #define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                              0x0000000CL
15079 #define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                              0x00000030L
15080 #define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                              0x000000C0L
15081 #define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                              0x00000300L
15082 #define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                              0x00000C00L
15083 #define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                              0x00003000L
15084 #define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                              0x0000C000L
15085 #define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                              0x00030000L
15086 #define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                              0x000C0000L
15087 #define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                             0x00300000L
15088 #define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                             0x00C00000L
15089 #define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                             0x03000000L
15090 #define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                             0x0C000000L
15091 #define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                             0x30000000L
15092 #define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                             0xC0000000L
15093 //GCEA_IO_RD_CLI2GRP_MAP1
15094 #define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                           0x0
15095 #define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                           0x2
15096 #define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                           0x4
15097 #define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                           0x6
15098 #define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                           0x8
15099 #define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                           0xa
15100 #define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                           0xc
15101 #define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                           0xe
15102 #define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                           0x10
15103 #define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                           0x12
15104 #define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                           0x14
15105 #define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                           0x16
15106 #define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                           0x18
15107 #define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                           0x1a
15108 #define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                           0x1c
15109 #define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                           0x1e
15110 #define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                             0x00000003L
15111 #define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                             0x0000000CL
15112 #define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                             0x00000030L
15113 #define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                             0x000000C0L
15114 #define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                             0x00000300L
15115 #define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                             0x00000C00L
15116 #define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                             0x00003000L
15117 #define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                             0x0000C000L
15118 #define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                             0x00030000L
15119 #define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                             0x000C0000L
15120 #define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                             0x00300000L
15121 #define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                             0x00C00000L
15122 #define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                             0x03000000L
15123 #define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                             0x0C000000L
15124 #define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                             0x30000000L
15125 #define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                             0xC0000000L
15126 //GCEA_IO_WR_CLI2GRP_MAP0
15127 #define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                            0x0
15128 #define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                            0x2
15129 #define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                            0x4
15130 #define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                            0x6
15131 #define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                            0x8
15132 #define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                            0xa
15133 #define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                            0xc
15134 #define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                            0xe
15135 #define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                            0x10
15136 #define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                            0x12
15137 #define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                           0x14
15138 #define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                           0x16
15139 #define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                           0x18
15140 #define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                           0x1a
15141 #define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                           0x1c
15142 #define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                           0x1e
15143 #define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                              0x00000003L
15144 #define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                              0x0000000CL
15145 #define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                              0x00000030L
15146 #define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                              0x000000C0L
15147 #define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                              0x00000300L
15148 #define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                              0x00000C00L
15149 #define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                              0x00003000L
15150 #define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                              0x0000C000L
15151 #define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                              0x00030000L
15152 #define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                              0x000C0000L
15153 #define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                             0x00300000L
15154 #define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                             0x00C00000L
15155 #define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                             0x03000000L
15156 #define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                             0x0C000000L
15157 #define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                             0x30000000L
15158 #define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                             0xC0000000L
15159 //GCEA_IO_WR_CLI2GRP_MAP1
15160 #define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                           0x0
15161 #define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                           0x2
15162 #define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                           0x4
15163 #define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                           0x6
15164 #define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                           0x8
15165 #define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                           0xa
15166 #define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                           0xc
15167 #define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                           0xe
15168 #define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                           0x10
15169 #define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                           0x12
15170 #define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                           0x14
15171 #define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                           0x16
15172 #define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                           0x18
15173 #define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                           0x1a
15174 #define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                           0x1c
15175 #define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                           0x1e
15176 #define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                             0x00000003L
15177 #define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                             0x0000000CL
15178 #define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                             0x00000030L
15179 #define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                             0x000000C0L
15180 #define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                             0x00000300L
15181 #define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                             0x00000C00L
15182 #define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                             0x00003000L
15183 #define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                             0x0000C000L
15184 #define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                             0x00030000L
15185 #define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                             0x000C0000L
15186 #define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                             0x00300000L
15187 #define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                             0x00C00000L
15188 #define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                             0x03000000L
15189 #define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                             0x0C000000L
15190 #define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                             0x30000000L
15191 #define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                             0xC0000000L
15192 //GCEA_IO_RD_COMBINE_FLUSH
15193 #define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                         0x0
15194 #define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                         0x4
15195 #define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                         0x8
15196 #define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                         0xc
15197 #define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                           0x0000000FL
15198 #define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                           0x000000F0L
15199 #define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                           0x00000F00L
15200 #define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                           0x0000F000L
15201 //GCEA_IO_WR_COMBINE_FLUSH
15202 #define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                         0x0
15203 #define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                         0x4
15204 #define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                         0x8
15205 #define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                         0xc
15206 #define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                           0x0000000FL
15207 #define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                           0x000000F0L
15208 #define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                           0x00000F00L
15209 #define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                           0x0000F000L
15210 //GCEA_IO_GROUP_BURST
15211 #define GCEA_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT                                                               0x0
15212 #define GCEA_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT                                                               0x8
15213 #define GCEA_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT                                                               0x10
15214 #define GCEA_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT                                                               0x18
15215 #define GCEA_IO_GROUP_BURST__RD_LIMIT_LO_MASK                                                                 0x000000FFL
15216 #define GCEA_IO_GROUP_BURST__RD_LIMIT_HI_MASK                                                                 0x0000FF00L
15217 #define GCEA_IO_GROUP_BURST__WR_LIMIT_LO_MASK                                                                 0x00FF0000L
15218 #define GCEA_IO_GROUP_BURST__WR_LIMIT_HI_MASK                                                                 0xFF000000L
15219 //GCEA_IO_RD_PRI_AGE
15220 #define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                          0x0
15221 #define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                          0x3
15222 #define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                          0x6
15223 #define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                          0x9
15224 #define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                     0xc
15225 #define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                     0xf
15226 #define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                     0x12
15227 #define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                     0x15
15228 #define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                            0x00000007L
15229 #define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                            0x00000038L
15230 #define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                            0x000001C0L
15231 #define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                            0x00000E00L
15232 #define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                       0x00007000L
15233 #define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                       0x00038000L
15234 #define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                       0x001C0000L
15235 #define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                       0x00E00000L
15236 //GCEA_IO_WR_PRI_AGE
15237 #define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                          0x0
15238 #define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                          0x3
15239 #define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                          0x6
15240 #define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                          0x9
15241 #define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                     0xc
15242 #define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                     0xf
15243 #define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                     0x12
15244 #define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                     0x15
15245 #define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                            0x00000007L
15246 #define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                            0x00000038L
15247 #define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                            0x000001C0L
15248 #define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                            0x00000E00L
15249 #define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                       0x00007000L
15250 #define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                       0x00038000L
15251 #define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                       0x001C0000L
15252 #define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                       0x00E00000L
15253 //GCEA_IO_RD_PRI_QUEUING
15254 #define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                             0x0
15255 #define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                             0x3
15256 #define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                             0x6
15257 #define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                             0x9
15258 #define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                               0x00000007L
15259 #define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                               0x00000038L
15260 #define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                               0x000001C0L
15261 #define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                               0x00000E00L
15262 //GCEA_IO_WR_PRI_QUEUING
15263 #define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                             0x0
15264 #define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                             0x3
15265 #define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                             0x6
15266 #define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                             0x9
15267 #define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                               0x00000007L
15268 #define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                               0x00000038L
15269 #define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                               0x000001C0L
15270 #define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                               0x00000E00L
15271 //GCEA_IO_RD_PRI_FIXED
15272 #define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                 0x0
15273 #define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                 0x3
15274 #define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                 0x6
15275 #define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                 0x9
15276 #define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                   0x00000007L
15277 #define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                   0x00000038L
15278 #define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                   0x000001C0L
15279 #define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                   0x00000E00L
15280 //GCEA_IO_WR_PRI_FIXED
15281 #define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                 0x0
15282 #define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                 0x3
15283 #define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                 0x6
15284 #define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                 0x9
15285 #define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                   0x00000007L
15286 #define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                   0x00000038L
15287 #define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                   0x000001C0L
15288 #define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                   0x00000E00L
15289 //GCEA_IO_RD_PRI_URGENCY
15290 #define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                             0x0
15291 #define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                             0x3
15292 #define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                             0x6
15293 #define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                             0x9
15294 #define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                    0xc
15295 #define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                    0xd
15296 #define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                    0xe
15297 #define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                    0xf
15298 #define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                               0x00000007L
15299 #define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                               0x00000038L
15300 #define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                               0x000001C0L
15301 #define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                               0x00000E00L
15302 #define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                      0x00001000L
15303 #define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                      0x00002000L
15304 #define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                      0x00004000L
15305 #define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                      0x00008000L
15306 //GCEA_IO_WR_PRI_URGENCY
15307 #define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                             0x0
15308 #define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                             0x3
15309 #define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                             0x6
15310 #define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                             0x9
15311 #define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                    0xc
15312 #define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                    0xd
15313 #define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                    0xe
15314 #define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                    0xf
15315 #define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                               0x00000007L
15316 #define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                               0x00000038L
15317 #define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                               0x000001C0L
15318 #define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                               0x00000E00L
15319 #define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                      0x00001000L
15320 #define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                      0x00002000L
15321 #define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                      0x00004000L
15322 #define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                      0x00008000L
15323 //GCEA_IO_RD_PRI_URGENCY_MASKING
15324 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                      0x0
15325 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                      0x1
15326 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                      0x2
15327 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                      0x3
15328 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                      0x4
15329 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                      0x5
15330 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                      0x6
15331 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                      0x7
15332 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                      0x8
15333 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                      0x9
15334 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                     0xa
15335 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                     0xb
15336 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                     0xc
15337 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                     0xd
15338 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                     0xe
15339 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                     0xf
15340 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                     0x10
15341 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                     0x11
15342 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                     0x12
15343 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                     0x13
15344 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                     0x14
15345 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                     0x15
15346 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                     0x16
15347 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                     0x17
15348 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                     0x18
15349 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                     0x19
15350 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                     0x1a
15351 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                     0x1b
15352 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                     0x1c
15353 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                     0x1d
15354 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                     0x1e
15355 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                     0x1f
15356 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                        0x00000001L
15357 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                        0x00000002L
15358 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                        0x00000004L
15359 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                        0x00000008L
15360 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                        0x00000010L
15361 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                        0x00000020L
15362 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                        0x00000040L
15363 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                        0x00000080L
15364 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                        0x00000100L
15365 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                        0x00000200L
15366 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                       0x00000400L
15367 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                       0x00000800L
15368 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                       0x00001000L
15369 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                       0x00002000L
15370 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                       0x00004000L
15371 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                       0x00008000L
15372 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                       0x00010000L
15373 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                       0x00020000L
15374 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                       0x00040000L
15375 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                       0x00080000L
15376 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                       0x00100000L
15377 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                       0x00200000L
15378 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                       0x00400000L
15379 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                       0x00800000L
15380 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                       0x01000000L
15381 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                       0x02000000L
15382 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                       0x04000000L
15383 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                       0x08000000L
15384 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                       0x10000000L
15385 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                       0x20000000L
15386 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                       0x40000000L
15387 #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                       0x80000000L
15388 //GCEA_IO_WR_PRI_URGENCY_MASKING
15389 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                      0x0
15390 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                      0x1
15391 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                      0x2
15392 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                      0x3
15393 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                      0x4
15394 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                      0x5
15395 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                      0x6
15396 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                      0x7
15397 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                      0x8
15398 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                      0x9
15399 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                     0xa
15400 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                     0xb
15401 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                     0xc
15402 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                     0xd
15403 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                     0xe
15404 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                     0xf
15405 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                     0x10
15406 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                     0x11
15407 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                     0x12
15408 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                     0x13
15409 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                     0x14
15410 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                     0x15
15411 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                     0x16
15412 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                     0x17
15413 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                     0x18
15414 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                     0x19
15415 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                     0x1a
15416 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                     0x1b
15417 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                     0x1c
15418 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                     0x1d
15419 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                     0x1e
15420 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                     0x1f
15421 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                        0x00000001L
15422 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                        0x00000002L
15423 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                        0x00000004L
15424 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                        0x00000008L
15425 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                        0x00000010L
15426 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                        0x00000020L
15427 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                        0x00000040L
15428 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                        0x00000080L
15429 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                        0x00000100L
15430 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                        0x00000200L
15431 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                       0x00000400L
15432 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                       0x00000800L
15433 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                       0x00001000L
15434 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                       0x00002000L
15435 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                       0x00004000L
15436 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                       0x00008000L
15437 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                       0x00010000L
15438 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                       0x00020000L
15439 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                       0x00040000L
15440 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                       0x00080000L
15441 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                       0x00100000L
15442 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                       0x00200000L
15443 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                       0x00400000L
15444 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                       0x00800000L
15445 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                       0x01000000L
15446 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                       0x02000000L
15447 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                       0x04000000L
15448 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                       0x08000000L
15449 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                       0x10000000L
15450 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                       0x20000000L
15451 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                       0x40000000L
15452 #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                       0x80000000L
15453 //GCEA_IO_RD_PRI_QUANT_PRI1
15454 #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                    0x0
15455 #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                    0x8
15456 #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                    0x10
15457 #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                    0x18
15458 #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                      0x000000FFL
15459 #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                      0x0000FF00L
15460 #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                      0x00FF0000L
15461 #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                      0xFF000000L
15462 //GCEA_IO_RD_PRI_QUANT_PRI2
15463 #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                    0x0
15464 #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                    0x8
15465 #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                    0x10
15466 #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                    0x18
15467 #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                      0x000000FFL
15468 #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                      0x0000FF00L
15469 #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                      0x00FF0000L
15470 #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                      0xFF000000L
15471 //GCEA_IO_RD_PRI_QUANT_PRI3
15472 #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                    0x0
15473 #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                    0x8
15474 #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                    0x10
15475 #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                    0x18
15476 #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                      0x000000FFL
15477 #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                      0x0000FF00L
15478 #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                      0x00FF0000L
15479 #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                      0xFF000000L
15480 //GCEA_IO_WR_PRI_QUANT_PRI1
15481 #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                    0x0
15482 #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                    0x8
15483 #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                    0x10
15484 #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                    0x18
15485 #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                      0x000000FFL
15486 #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                      0x0000FF00L
15487 #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                      0x00FF0000L
15488 #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                      0xFF000000L
15489 //GCEA_IO_WR_PRI_QUANT_PRI2
15490 #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                    0x0
15491 #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                    0x8
15492 #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                    0x10
15493 #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                    0x18
15494 #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                      0x000000FFL
15495 #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                      0x0000FF00L
15496 #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                      0x00FF0000L
15497 #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                      0xFF000000L
15498 //GCEA_IO_WR_PRI_QUANT_PRI3
15499 #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                    0x0
15500 #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                    0x8
15501 #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                    0x10
15502 #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                    0x18
15503 #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                      0x000000FFL
15504 #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                      0x0000FF00L
15505 #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                      0x00FF0000L
15506 #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                      0xFF000000L
15507 //GCEA_SDP_ARB_DRAM
15508 #define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT                                                       0x0
15509 #define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT                                                       0x8
15510 #define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT                                                          0x10
15511 #define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT                                                          0x11
15512 #define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT                                                          0x12
15513 #define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT                                                          0x13
15514 #define GCEA_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT                                                               0x14
15515 #define GCEA_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                      0x15
15516 #define GCEA_SDP_ARB_DRAM__ALLOW_CHAIN_BREAKING__SHIFT                                                        0x16
15517 #define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK                                                         0x0000007FL
15518 #define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK                                                         0x00007F00L
15519 #define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK                                                            0x00010000L
15520 #define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK                                                            0x00020000L
15521 #define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK                                                            0x00040000L
15522 #define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK                                                            0x00080000L
15523 #define GCEA_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK                                                                 0x00100000L
15524 #define GCEA_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK                                                        0x00200000L
15525 #define GCEA_SDP_ARB_DRAM__ALLOW_CHAIN_BREAKING_MASK                                                          0x00400000L
15526 //GCEA_SDP_ARB_FINAL
15527 #define GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT                                                           0x0
15528 #define GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT                                                            0x5
15529 #define GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT                                                             0xa
15530 #define GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT                                                     0xf
15531 #define GCEA_SDP_ARB_FINAL__RDONLY_VC0__SHIFT                                                                 0x11
15532 #define GCEA_SDP_ARB_FINAL__RDONLY_VC1__SHIFT                                                                 0x12
15533 #define GCEA_SDP_ARB_FINAL__RDONLY_VC2__SHIFT                                                                 0x13
15534 #define GCEA_SDP_ARB_FINAL__RDONLY_VC3__SHIFT                                                                 0x14
15535 #define GCEA_SDP_ARB_FINAL__RDONLY_VC4__SHIFT                                                                 0x15
15536 #define GCEA_SDP_ARB_FINAL__RDONLY_VC5__SHIFT                                                                 0x16
15537 #define GCEA_SDP_ARB_FINAL__RDONLY_VC6__SHIFT                                                                 0x17
15538 #define GCEA_SDP_ARB_FINAL__RDONLY_VC7__SHIFT                                                                 0x18
15539 #define GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT                                                          0x19
15540 #define GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT                                                           0x1a
15541 #define GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK                                                             0x0000001FL
15542 #define GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK                                                              0x000003E0L
15543 #define GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK                                                               0x00007C00L
15544 #define GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK                                                       0x00018000L
15545 #define GCEA_SDP_ARB_FINAL__RDONLY_VC0_MASK                                                                   0x00020000L
15546 #define GCEA_SDP_ARB_FINAL__RDONLY_VC1_MASK                                                                   0x00040000L
15547 #define GCEA_SDP_ARB_FINAL__RDONLY_VC2_MASK                                                                   0x00080000L
15548 #define GCEA_SDP_ARB_FINAL__RDONLY_VC3_MASK                                                                   0x00100000L
15549 #define GCEA_SDP_ARB_FINAL__RDONLY_VC4_MASK                                                                   0x00200000L
15550 #define GCEA_SDP_ARB_FINAL__RDONLY_VC5_MASK                                                                   0x00400000L
15551 #define GCEA_SDP_ARB_FINAL__RDONLY_VC6_MASK                                                                   0x00800000L
15552 #define GCEA_SDP_ARB_FINAL__RDONLY_VC7_MASK                                                                   0x01000000L
15553 #define GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK                                                            0x02000000L
15554 #define GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK                                                             0x04000000L
15555 //GCEA_SDP_DRAM_PRIORITY
15556 #define GCEA_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                     0x0
15557 #define GCEA_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                     0x4
15558 #define GCEA_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                     0x8
15559 #define GCEA_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                     0xc
15560 #define GCEA_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                     0x10
15561 #define GCEA_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                     0x14
15562 #define GCEA_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                     0x18
15563 #define GCEA_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                     0x1c
15564 #define GCEA_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                       0x0000000FL
15565 #define GCEA_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                       0x000000F0L
15566 #define GCEA_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                       0x00000F00L
15567 #define GCEA_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                       0x0000F000L
15568 #define GCEA_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                       0x000F0000L
15569 #define GCEA_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                       0x00F00000L
15570 #define GCEA_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                       0x0F000000L
15571 #define GCEA_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                       0xF0000000L
15572 //GCEA_SDP_IO_PRIORITY
15573 #define GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                       0x0
15574 #define GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                       0x4
15575 #define GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                       0x8
15576 #define GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                       0xc
15577 #define GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                       0x10
15578 #define GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                       0x14
15579 #define GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                       0x18
15580 #define GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                       0x1c
15581 #define GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                         0x0000000FL
15582 #define GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                         0x000000F0L
15583 #define GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                         0x00000F00L
15584 #define GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                         0x0000F000L
15585 #define GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                         0x000F0000L
15586 #define GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                         0x00F00000L
15587 #define GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                         0x0F000000L
15588 #define GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                         0xF0000000L
15589 //GCEA_SDP_CREDITS
15590 #define GCEA_SDP_CREDITS__TAG_LIMIT__SHIFT                                                                    0x0
15591 #define GCEA_SDP_CREDITS__WR_RESP_CREDITS__SHIFT                                                              0x8
15592 #define GCEA_SDP_CREDITS__RD_RESP_CREDITS__SHIFT                                                              0x10
15593 #define GCEA_SDP_CREDITS__PRB_REQ_CREDITS__SHIFT                                                              0x18
15594 #define GCEA_SDP_CREDITS__TAG_LIMIT_MASK                                                                      0x000000FFL
15595 #define GCEA_SDP_CREDITS__WR_RESP_CREDITS_MASK                                                                0x00007F00L
15596 #define GCEA_SDP_CREDITS__RD_RESP_CREDITS_MASK                                                                0x007F0000L
15597 #define GCEA_SDP_CREDITS__PRB_REQ_CREDITS_MASK                                                                0x3F000000L
15598 //GCEA_SDP_TAG_RESERVE0
15599 #define GCEA_SDP_TAG_RESERVE0__VC0__SHIFT                                                                     0x0
15600 #define GCEA_SDP_TAG_RESERVE0__VC1__SHIFT                                                                     0x8
15601 #define GCEA_SDP_TAG_RESERVE0__VC2__SHIFT                                                                     0x10
15602 #define GCEA_SDP_TAG_RESERVE0__VC3__SHIFT                                                                     0x18
15603 #define GCEA_SDP_TAG_RESERVE0__VC0_MASK                                                                       0x000000FFL
15604 #define GCEA_SDP_TAG_RESERVE0__VC1_MASK                                                                       0x0000FF00L
15605 #define GCEA_SDP_TAG_RESERVE0__VC2_MASK                                                                       0x00FF0000L
15606 #define GCEA_SDP_TAG_RESERVE0__VC3_MASK                                                                       0xFF000000L
15607 //GCEA_SDP_TAG_RESERVE1
15608 #define GCEA_SDP_TAG_RESERVE1__VC4__SHIFT                                                                     0x0
15609 #define GCEA_SDP_TAG_RESERVE1__VC5__SHIFT                                                                     0x8
15610 #define GCEA_SDP_TAG_RESERVE1__VC6__SHIFT                                                                     0x10
15611 #define GCEA_SDP_TAG_RESERVE1__VC7__SHIFT                                                                     0x18
15612 #define GCEA_SDP_TAG_RESERVE1__VC4_MASK                                                                       0x000000FFL
15613 #define GCEA_SDP_TAG_RESERVE1__VC5_MASK                                                                       0x0000FF00L
15614 #define GCEA_SDP_TAG_RESERVE1__VC6_MASK                                                                       0x00FF0000L
15615 #define GCEA_SDP_TAG_RESERVE1__VC7_MASK                                                                       0xFF000000L
15616 //GCEA_SDP_VCC_RESERVE0
15617 #define GCEA_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT                                                             0x0
15618 #define GCEA_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT                                                             0x6
15619 #define GCEA_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT                                                             0xc
15620 #define GCEA_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT                                                             0x12
15621 #define GCEA_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT                                                             0x18
15622 #define GCEA_SDP_VCC_RESERVE0__VC0_CREDITS_MASK                                                               0x0000003FL
15623 #define GCEA_SDP_VCC_RESERVE0__VC1_CREDITS_MASK                                                               0x00000FC0L
15624 #define GCEA_SDP_VCC_RESERVE0__VC2_CREDITS_MASK                                                               0x0003F000L
15625 #define GCEA_SDP_VCC_RESERVE0__VC3_CREDITS_MASK                                                               0x00FC0000L
15626 #define GCEA_SDP_VCC_RESERVE0__VC4_CREDITS_MASK                                                               0x3F000000L
15627 //GCEA_SDP_VCC_RESERVE1
15628 #define GCEA_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT                                                             0x0
15629 #define GCEA_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT                                                             0x6
15630 #define GCEA_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT                                                             0xc
15631 #define GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                         0x1f
15632 #define GCEA_SDP_VCC_RESERVE1__VC5_CREDITS_MASK                                                               0x0000003FL
15633 #define GCEA_SDP_VCC_RESERVE1__VC6_CREDITS_MASK                                                               0x00000FC0L
15634 #define GCEA_SDP_VCC_RESERVE1__VC7_CREDITS_MASK                                                               0x0003F000L
15635 #define GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK                                                           0x80000000L
15636 //GCEA_SDP_VCD_RESERVE0
15637 #define GCEA_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT                                                             0x0
15638 #define GCEA_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT                                                             0x6
15639 #define GCEA_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT                                                             0xc
15640 #define GCEA_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT                                                             0x12
15641 #define GCEA_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT                                                             0x18
15642 #define GCEA_SDP_VCD_RESERVE0__VC0_CREDITS_MASK                                                               0x0000003FL
15643 #define GCEA_SDP_VCD_RESERVE0__VC1_CREDITS_MASK                                                               0x00000FC0L
15644 #define GCEA_SDP_VCD_RESERVE0__VC2_CREDITS_MASK                                                               0x0003F000L
15645 #define GCEA_SDP_VCD_RESERVE0__VC3_CREDITS_MASK                                                               0x00FC0000L
15646 #define GCEA_SDP_VCD_RESERVE0__VC4_CREDITS_MASK                                                               0x3F000000L
15647 
15648 
15649 // addressBlock: gc_tcdec
15650 //TCP_INVALIDATE
15651 #define TCP_INVALIDATE__START__SHIFT                                                                          0x0
15652 #define TCP_INVALIDATE__START_MASK                                                                            0x00000001L
15653 //TCP_STATUS
15654 #define TCP_STATUS__TCP_BUSY__SHIFT                                                                           0x0
15655 #define TCP_STATUS__INPUT_BUSY__SHIFT                                                                         0x1
15656 #define TCP_STATUS__ADRS_BUSY__SHIFT                                                                          0x2
15657 #define TCP_STATUS__TAGRAMS_BUSY__SHIFT                                                                       0x3
15658 #define TCP_STATUS__CNTRL_BUSY__SHIFT                                                                         0x4
15659 #define TCP_STATUS__LFIFO_BUSY__SHIFT                                                                         0x5
15660 #define TCP_STATUS__READ_BUSY__SHIFT                                                                          0x6
15661 #define TCP_STATUS__FORMAT_BUSY__SHIFT                                                                        0x7
15662 #define TCP_STATUS__VM_BUSY__SHIFT                                                                            0x8
15663 #define TCP_STATUS__OFIFO_BUSY__SHIFT                                                                         0x9
15664 #define TCP_STATUS__MEMIF_BUSY__SHIFT                                                                         0xa
15665 #define TCP_STATUS__TCP_BUSY_MASK                                                                             0x00000001L
15666 #define TCP_STATUS__INPUT_BUSY_MASK                                                                           0x00000002L
15667 #define TCP_STATUS__ADRS_BUSY_MASK                                                                            0x00000004L
15668 #define TCP_STATUS__TAGRAMS_BUSY_MASK                                                                         0x00000008L
15669 #define TCP_STATUS__CNTRL_BUSY_MASK                                                                           0x00000010L
15670 #define TCP_STATUS__LFIFO_BUSY_MASK                                                                           0x00000020L
15671 #define TCP_STATUS__READ_BUSY_MASK                                                                            0x00000040L
15672 #define TCP_STATUS__FORMAT_BUSY_MASK                                                                          0x00000080L
15673 #define TCP_STATUS__VM_BUSY_MASK                                                                              0x00000100L
15674 #define TCP_STATUS__OFIFO_BUSY_MASK                                                                           0x00000200L
15675 #define TCP_STATUS__MEMIF_BUSY_MASK                                                                           0x00000400L
15676 //TCP_CNTL
15677 #define TCP_CNTL__FORCE_HIT__SHIFT                                                                            0x0
15678 #define TCP_CNTL__FORCE_MISS__SHIFT                                                                           0x1
15679 #define TCP_CNTL__L0_SIZE__SHIFT                                                                              0x2
15680 #define TCP_CNTL__BIG_PAGE_ADDR_COMBINE_DISABLE__SHIFT                                                        0x4
15681 #define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT                                                               0x5
15682 #define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT                                                                  0xf
15683 #define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT                                                                 0x16
15684 #define TCP_CNTL__DISABLE_Z_MAP__SHIFT                                                                        0x1c
15685 #define TCP_CNTL__LFIFO_SIZE__SHIFT                                                                           0x1d
15686 #define TCP_CNTL__ASTC_VE_MSB_TOLERANT__SHIFT                                                                 0x1f
15687 #define TCP_CNTL__FORCE_HIT_MASK                                                                              0x00000001L
15688 #define TCP_CNTL__FORCE_MISS_MASK                                                                             0x00000002L
15689 #define TCP_CNTL__L0_SIZE_MASK                                                                                0x0000000CL
15690 #define TCP_CNTL__BIG_PAGE_ADDR_COMBINE_DISABLE_MASK                                                          0x00000010L
15691 #define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK                                                                 0x00000020L
15692 #define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK                                                                    0x001F8000L
15693 #define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK                                                                   0x0FC00000L
15694 #define TCP_CNTL__DISABLE_Z_MAP_MASK                                                                          0x10000000L
15695 #define TCP_CNTL__LFIFO_SIZE_MASK                                                                             0x60000000L
15696 #define TCP_CNTL__ASTC_VE_MSB_TOLERANT_MASK                                                                   0x80000000L
15697 //TCP_CREDIT
15698 #define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT                                                                    0x10
15699 #define TCP_CREDIT__TD_CREDIT__SHIFT                                                                          0x1d
15700 #define TCP_CREDIT__REQ_FIFO_CREDIT_MASK                                                                      0x007F0000L
15701 #define TCP_CREDIT__TD_CREDIT_MASK                                                                            0xE0000000L
15702 //TCP_BUFFER_ADDR_HASH_CNTL
15703 #define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT                                                        0x0
15704 #define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT                                                           0x8
15705 #define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT                                                   0x10
15706 #define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT                                                      0x18
15707 #define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK                                                          0x00000007L
15708 #define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK                                                             0x00000700L
15709 #define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK                                                     0x00070000L
15710 #define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK                                                        0x07000000L
15711 //TCP_EDC_CNT
15712 #define TCP_EDC_CNT__SEC_COUNT__SHIFT                                                                         0x0
15713 #define TCP_EDC_CNT__LFIFO_SED_COUNT__SHIFT                                                                   0x8
15714 #define TCP_EDC_CNT__DED_COUNT__SHIFT                                                                         0x10
15715 #define TCP_EDC_CNT__SEC_COUNT_MASK                                                                           0x000000FFL
15716 #define TCP_EDC_CNT__LFIFO_SED_COUNT_MASK                                                                     0x0000FF00L
15717 #define TCP_EDC_CNT__DED_COUNT_MASK                                                                           0x00FF0000L
15718 //TCI_STATUS
15719 #define TCI_STATUS__TCI_BUSY__SHIFT                                                                           0x0
15720 #define TCI_STATUS__TCI_BUSY_MASK                                                                             0x00000001L
15721 //TCI_CNTL_1
15722 #define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT                                                                 0x0
15723 #define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT                                                                     0x10
15724 #define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT                                                                    0x18
15725 #define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK                                                                   0x0000FFFFL
15726 #define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK                                                                       0x00FF0000L
15727 #define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK                                                                      0xFF000000L
15728 //TCI_CNTL_2
15729 #define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT                                                                0x0
15730 #define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT                                                                     0x1
15731 #define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK                                                                  0x00000001L
15732 #define TCI_CNTL_2__TCA_MAX_CREDIT_MASK                                                                       0x000001FEL
15733 
15734 
15735 // addressBlock: gc_shdec
15736 //SPI_SHADER_PGM_RSRC4_PS
15737 #define SPI_SHADER_PGM_RSRC4_PS__CU_EN__SHIFT                                                                 0x0
15738 #define SPI_SHADER_PGM_RSRC4_PS__CU_EN_MASK                                                                   0x0000FFFFL
15739 //SPI_SHADER_PGM_CHKSUM_PS
15740 #define SPI_SHADER_PGM_CHKSUM_PS__CHECKSUM__SHIFT                                                             0x0
15741 #define SPI_SHADER_PGM_CHKSUM_PS__CHECKSUM_MASK                                                               0xFFFFFFFFL
15742 //SPI_SHADER_PGM_RSRC3_PS
15743 #define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT                                                                 0x0
15744 #define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT                                                            0x10
15745 #define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT                                                    0x16
15746 #define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK                                                                   0x0000FFFFL
15747 #define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK                                                              0x003F0000L
15748 #define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK                                                      0x03C00000L
15749 //SPI_SHADER_PGM_LO_PS
15750 #define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT                                                                 0x0
15751 #define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK                                                                   0xFFFFFFFFL
15752 //SPI_SHADER_PGM_HI_PS
15753 #define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT                                                                 0x0
15754 #define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK                                                                   0xFFL
15755 //SPI_SHADER_PGM_RSRC1_PS
15756 #define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT                                                                 0x0
15757 #define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT                                                                 0x6
15758 #define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT                                                              0xa
15759 #define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT                                                            0xc
15760 #define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT                                                                  0x14
15761 #define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT                                                            0x15
15762 #define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT                                                             0x17
15763 #define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT                                                      0x18
15764 #define SPI_SHADER_PGM_RSRC1_PS__MEM_ORDERED__SHIFT                                                           0x19
15765 #define SPI_SHADER_PGM_RSRC1_PS__FWD_PROGRESS__SHIFT                                                          0x1a
15766 #define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL__SHIFT                                                             0x1d
15767 #define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK                                                                   0x0000003FL
15768 #define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK                                                                   0x000003C0L
15769 #define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK                                                                0x00000C00L
15770 #define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK                                                              0x000FF000L
15771 #define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK                                                                    0x00100000L
15772 #define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK                                                              0x00200000L
15773 #define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK                                                               0x00800000L
15774 #define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK                                                        0x01000000L
15775 #define SPI_SHADER_PGM_RSRC1_PS__MEM_ORDERED_MASK                                                             0x02000000L
15776 #define SPI_SHADER_PGM_RSRC1_PS__FWD_PROGRESS_MASK                                                            0x04000000L
15777 #define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL_MASK                                                               0x20000000L
15778 //SPI_SHADER_PGM_RSRC2_PS
15779 #define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT                                                            0x0
15780 #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT                                                             0x1
15781 #define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT                                                          0x6
15782 #define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT                                                           0x7
15783 #define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT                                                        0x8
15784 #define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT                                                               0x10
15785 #define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID__SHIFT                                                 0x19
15786 #define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION__SHIFT                                              0x1a
15787 #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB__SHIFT                                                         0x1b
15788 #define SPI_SHADER_PGM_RSRC2_PS__SHARED_VGPR_CNT__SHIFT                                                       0x1c
15789 #define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK                                                              0x00000001L
15790 #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK                                                               0x0000003EL
15791 #define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK                                                            0x00000040L
15792 #define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK                                                             0x00000080L
15793 #define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK                                                          0x0000FF00L
15794 #define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK                                                                 0x01FF0000L
15795 #define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID_MASK                                                   0x02000000L
15796 #define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION_MASK                                                0x04000000L
15797 #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB_MASK                                                           0x08000000L
15798 #define SPI_SHADER_PGM_RSRC2_PS__SHARED_VGPR_CNT_MASK                                                         0xF0000000L
15799 //SPI_SHADER_USER_DATA_PS_0
15800 #define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT                                                                0x0
15801 #define SPI_SHADER_USER_DATA_PS_0__DATA_MASK                                                                  0xFFFFFFFFL
15802 //SPI_SHADER_USER_DATA_PS_1
15803 #define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT                                                                0x0
15804 #define SPI_SHADER_USER_DATA_PS_1__DATA_MASK                                                                  0xFFFFFFFFL
15805 //SPI_SHADER_USER_DATA_PS_2
15806 #define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT                                                                0x0
15807 #define SPI_SHADER_USER_DATA_PS_2__DATA_MASK                                                                  0xFFFFFFFFL
15808 //SPI_SHADER_USER_DATA_PS_3
15809 #define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT                                                                0x0
15810 #define SPI_SHADER_USER_DATA_PS_3__DATA_MASK                                                                  0xFFFFFFFFL
15811 //SPI_SHADER_USER_DATA_PS_4
15812 #define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT                                                                0x0
15813 #define SPI_SHADER_USER_DATA_PS_4__DATA_MASK                                                                  0xFFFFFFFFL
15814 //SPI_SHADER_USER_DATA_PS_5
15815 #define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT                                                                0x0
15816 #define SPI_SHADER_USER_DATA_PS_5__DATA_MASK                                                                  0xFFFFFFFFL
15817 //SPI_SHADER_USER_DATA_PS_6
15818 #define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT                                                                0x0
15819 #define SPI_SHADER_USER_DATA_PS_6__DATA_MASK                                                                  0xFFFFFFFFL
15820 //SPI_SHADER_USER_DATA_PS_7
15821 #define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT                                                                0x0
15822 #define SPI_SHADER_USER_DATA_PS_7__DATA_MASK                                                                  0xFFFFFFFFL
15823 //SPI_SHADER_USER_DATA_PS_8
15824 #define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT                                                                0x0
15825 #define SPI_SHADER_USER_DATA_PS_8__DATA_MASK                                                                  0xFFFFFFFFL
15826 //SPI_SHADER_USER_DATA_PS_9
15827 #define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT                                                                0x0
15828 #define SPI_SHADER_USER_DATA_PS_9__DATA_MASK                                                                  0xFFFFFFFFL
15829 //SPI_SHADER_USER_DATA_PS_10
15830 #define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT                                                               0x0
15831 #define SPI_SHADER_USER_DATA_PS_10__DATA_MASK                                                                 0xFFFFFFFFL
15832 //SPI_SHADER_USER_DATA_PS_11
15833 #define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT                                                               0x0
15834 #define SPI_SHADER_USER_DATA_PS_11__DATA_MASK                                                                 0xFFFFFFFFL
15835 //SPI_SHADER_USER_DATA_PS_12
15836 #define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT                                                               0x0
15837 #define SPI_SHADER_USER_DATA_PS_12__DATA_MASK                                                                 0xFFFFFFFFL
15838 //SPI_SHADER_USER_DATA_PS_13
15839 #define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT                                                               0x0
15840 #define SPI_SHADER_USER_DATA_PS_13__DATA_MASK                                                                 0xFFFFFFFFL
15841 //SPI_SHADER_USER_DATA_PS_14
15842 #define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT                                                               0x0
15843 #define SPI_SHADER_USER_DATA_PS_14__DATA_MASK                                                                 0xFFFFFFFFL
15844 //SPI_SHADER_USER_DATA_PS_15
15845 #define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT                                                               0x0
15846 #define SPI_SHADER_USER_DATA_PS_15__DATA_MASK                                                                 0xFFFFFFFFL
15847 //SPI_SHADER_USER_DATA_PS_16
15848 #define SPI_SHADER_USER_DATA_PS_16__DATA__SHIFT                                                               0x0
15849 #define SPI_SHADER_USER_DATA_PS_16__DATA_MASK                                                                 0xFFFFFFFFL
15850 //SPI_SHADER_USER_DATA_PS_17
15851 #define SPI_SHADER_USER_DATA_PS_17__DATA__SHIFT                                                               0x0
15852 #define SPI_SHADER_USER_DATA_PS_17__DATA_MASK                                                                 0xFFFFFFFFL
15853 //SPI_SHADER_USER_DATA_PS_18
15854 #define SPI_SHADER_USER_DATA_PS_18__DATA__SHIFT                                                               0x0
15855 #define SPI_SHADER_USER_DATA_PS_18__DATA_MASK                                                                 0xFFFFFFFFL
15856 //SPI_SHADER_USER_DATA_PS_19
15857 #define SPI_SHADER_USER_DATA_PS_19__DATA__SHIFT                                                               0x0
15858 #define SPI_SHADER_USER_DATA_PS_19__DATA_MASK                                                                 0xFFFFFFFFL
15859 //SPI_SHADER_USER_DATA_PS_20
15860 #define SPI_SHADER_USER_DATA_PS_20__DATA__SHIFT                                                               0x0
15861 #define SPI_SHADER_USER_DATA_PS_20__DATA_MASK                                                                 0xFFFFFFFFL
15862 //SPI_SHADER_USER_DATA_PS_21
15863 #define SPI_SHADER_USER_DATA_PS_21__DATA__SHIFT                                                               0x0
15864 #define SPI_SHADER_USER_DATA_PS_21__DATA_MASK                                                                 0xFFFFFFFFL
15865 //SPI_SHADER_USER_DATA_PS_22
15866 #define SPI_SHADER_USER_DATA_PS_22__DATA__SHIFT                                                               0x0
15867 #define SPI_SHADER_USER_DATA_PS_22__DATA_MASK                                                                 0xFFFFFFFFL
15868 //SPI_SHADER_USER_DATA_PS_23
15869 #define SPI_SHADER_USER_DATA_PS_23__DATA__SHIFT                                                               0x0
15870 #define SPI_SHADER_USER_DATA_PS_23__DATA_MASK                                                                 0xFFFFFFFFL
15871 //SPI_SHADER_USER_DATA_PS_24
15872 #define SPI_SHADER_USER_DATA_PS_24__DATA__SHIFT                                                               0x0
15873 #define SPI_SHADER_USER_DATA_PS_24__DATA_MASK                                                                 0xFFFFFFFFL
15874 //SPI_SHADER_USER_DATA_PS_25
15875 #define SPI_SHADER_USER_DATA_PS_25__DATA__SHIFT                                                               0x0
15876 #define SPI_SHADER_USER_DATA_PS_25__DATA_MASK                                                                 0xFFFFFFFFL
15877 //SPI_SHADER_USER_DATA_PS_26
15878 #define SPI_SHADER_USER_DATA_PS_26__DATA__SHIFT                                                               0x0
15879 #define SPI_SHADER_USER_DATA_PS_26__DATA_MASK                                                                 0xFFFFFFFFL
15880 //SPI_SHADER_USER_DATA_PS_27
15881 #define SPI_SHADER_USER_DATA_PS_27__DATA__SHIFT                                                               0x0
15882 #define SPI_SHADER_USER_DATA_PS_27__DATA_MASK                                                                 0xFFFFFFFFL
15883 //SPI_SHADER_USER_DATA_PS_28
15884 #define SPI_SHADER_USER_DATA_PS_28__DATA__SHIFT                                                               0x0
15885 #define SPI_SHADER_USER_DATA_PS_28__DATA_MASK                                                                 0xFFFFFFFFL
15886 //SPI_SHADER_USER_DATA_PS_29
15887 #define SPI_SHADER_USER_DATA_PS_29__DATA__SHIFT                                                               0x0
15888 #define SPI_SHADER_USER_DATA_PS_29__DATA_MASK                                                                 0xFFFFFFFFL
15889 //SPI_SHADER_USER_DATA_PS_30
15890 #define SPI_SHADER_USER_DATA_PS_30__DATA__SHIFT                                                               0x0
15891 #define SPI_SHADER_USER_DATA_PS_30__DATA_MASK                                                                 0xFFFFFFFFL
15892 //SPI_SHADER_USER_DATA_PS_31
15893 #define SPI_SHADER_USER_DATA_PS_31__DATA__SHIFT                                                               0x0
15894 #define SPI_SHADER_USER_DATA_PS_31__DATA_MASK                                                                 0xFFFFFFFFL
15895 //SPI_SHADER_REQ_CTRL_PS
15896 #define SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_EN__SHIFT                                                       0x0
15897 #define SPI_SHADER_REQ_CTRL_PS__NUMBER_OF_REQUESTS_PER_CU__SHIFT                                              0x1
15898 #define SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT                                       0x5
15899 #define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_HYSTERESIS__SHIFT                                                   0x9
15900 #define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_LOW_THRESHOLD__SHIFT                                                0xa
15901 #define SPI_SHADER_REQ_CTRL_PS__PRODUCER_REQUEST_LOCKOUT__SHIFT                                               0xf
15902 #define SPI_SHADER_REQ_CTRL_PS__GLOBAL_SCANNING_EN__SHIFT                                                     0x10
15903 #define SPI_SHADER_REQ_CTRL_PS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT                                   0x11
15904 #define SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_EN_MASK                                                         0x00000001L
15905 #define SPI_SHADER_REQ_CTRL_PS__NUMBER_OF_REQUESTS_PER_CU_MASK                                                0x0000001EL
15906 #define SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK                                         0x000001E0L
15907 #define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_HYSTERESIS_MASK                                                     0x00000200L
15908 #define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_LOW_THRESHOLD_MASK                                                  0x00007C00L
15909 #define SPI_SHADER_REQ_CTRL_PS__PRODUCER_REQUEST_LOCKOUT_MASK                                                 0x00008000L
15910 #define SPI_SHADER_REQ_CTRL_PS__GLOBAL_SCANNING_EN_MASK                                                       0x00010000L
15911 #define SPI_SHADER_REQ_CTRL_PS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK                                     0x000E0000L
15912 //SPI_SHADER_PREF_PRI_CNTR_CTRL_PS
15913 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_PS__TOTAL_WAVE_COUNT_HIER_SELECT__SHIFT                                 0x0
15914 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_PS__PER_TYPE_WAVE_COUNT_HIER_SELECT__SHIFT                              0x3
15915 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_PS__GROUP_UPDATE_EN__SHIFT                                              0x6
15916 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_PS__TOTAL_WAVE_COUNT_COEFFICIENT__SHIFT                                 0x8
15917 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_PS__PER_TYPE_WAVE_COUNT_COEFFICIENT__SHIFT                              0x10
15918 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_PS__TOTAL_WAVE_COUNT_HIER_SELECT_MASK                                   0x00000007L
15919 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_PS__PER_TYPE_WAVE_COUNT_HIER_SELECT_MASK                                0x00000038L
15920 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_PS__GROUP_UPDATE_EN_MASK                                                0x00000040L
15921 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_PS__TOTAL_WAVE_COUNT_COEFFICIENT_MASK                                   0x0000FF00L
15922 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_PS__PER_TYPE_WAVE_COUNT_COEFFICIENT_MASK                                0x00FF0000L
15923 //SPI_SHADER_PREF_PRI_ACCUM_PS_0
15924 #define SPI_SHADER_PREF_PRI_ACCUM_PS_0__CONTRIBUTION__SHIFT                                                   0x0
15925 #define SPI_SHADER_PREF_PRI_ACCUM_PS_0__COEFFICIENT_HIER_SELECT__SHIFT                                        0x7
15926 #define SPI_SHADER_PREF_PRI_ACCUM_PS_0__CONTRIBUTION_HIER_SELECT__SHIFT                                       0xa
15927 #define SPI_SHADER_PREF_PRI_ACCUM_PS_0__GROUP_UPDATE_EN__SHIFT                                                0xd
15928 #define SPI_SHADER_PREF_PRI_ACCUM_PS_0__RESERVED__SHIFT                                                       0xe
15929 #define SPI_SHADER_PREF_PRI_ACCUM_PS_0__COEFFICIENT__SHIFT                                                    0xf
15930 #define SPI_SHADER_PREF_PRI_ACCUM_PS_0__CONTRIBUTION_MASK                                                     0x0000007FL
15931 #define SPI_SHADER_PREF_PRI_ACCUM_PS_0__COEFFICIENT_HIER_SELECT_MASK                                          0x00000380L
15932 #define SPI_SHADER_PREF_PRI_ACCUM_PS_0__CONTRIBUTION_HIER_SELECT_MASK                                         0x00001C00L
15933 #define SPI_SHADER_PREF_PRI_ACCUM_PS_0__GROUP_UPDATE_EN_MASK                                                  0x00002000L
15934 #define SPI_SHADER_PREF_PRI_ACCUM_PS_0__RESERVED_MASK                                                         0x00004000L
15935 #define SPI_SHADER_PREF_PRI_ACCUM_PS_0__COEFFICIENT_MASK                                                      0x007F8000L
15936 //SPI_SHADER_USER_ACCUM_PS_0
15937 #define SPI_SHADER_USER_ACCUM_PS_0__CONTRIBUTION__SHIFT                                                       0x0
15938 #define SPI_SHADER_USER_ACCUM_PS_0__CONTRIBUTION_MASK                                                         0x0000007FL
15939 //SPI_SHADER_PREF_PRI_ACCUM_PS_1
15940 #define SPI_SHADER_PREF_PRI_ACCUM_PS_1__CONTRIBUTION__SHIFT                                                   0x0
15941 #define SPI_SHADER_PREF_PRI_ACCUM_PS_1__COEFFICIENT_HIER_SELECT__SHIFT                                        0x7
15942 #define SPI_SHADER_PREF_PRI_ACCUM_PS_1__CONTRIBUTION_HIER_SELECT__SHIFT                                       0xa
15943 #define SPI_SHADER_PREF_PRI_ACCUM_PS_1__GROUP_UPDATE_EN__SHIFT                                                0xd
15944 #define SPI_SHADER_PREF_PRI_ACCUM_PS_1__RESERVED__SHIFT                                                       0xe
15945 #define SPI_SHADER_PREF_PRI_ACCUM_PS_1__COEFFICIENT__SHIFT                                                    0xf
15946 #define SPI_SHADER_PREF_PRI_ACCUM_PS_1__CONTRIBUTION_MASK                                                     0x0000007FL
15947 #define SPI_SHADER_PREF_PRI_ACCUM_PS_1__COEFFICIENT_HIER_SELECT_MASK                                          0x00000380L
15948 #define SPI_SHADER_PREF_PRI_ACCUM_PS_1__CONTRIBUTION_HIER_SELECT_MASK                                         0x00001C00L
15949 #define SPI_SHADER_PREF_PRI_ACCUM_PS_1__GROUP_UPDATE_EN_MASK                                                  0x00002000L
15950 #define SPI_SHADER_PREF_PRI_ACCUM_PS_1__RESERVED_MASK                                                         0x00004000L
15951 #define SPI_SHADER_PREF_PRI_ACCUM_PS_1__COEFFICIENT_MASK                                                      0x007F8000L
15952 //SPI_SHADER_USER_ACCUM_PS_1
15953 #define SPI_SHADER_USER_ACCUM_PS_1__CONTRIBUTION__SHIFT                                                       0x0
15954 #define SPI_SHADER_USER_ACCUM_PS_1__CONTRIBUTION_MASK                                                         0x0000007FL
15955 //SPI_SHADER_PREF_PRI_ACCUM_PS_2
15956 #define SPI_SHADER_PREF_PRI_ACCUM_PS_2__CONTRIBUTION__SHIFT                                                   0x0
15957 #define SPI_SHADER_PREF_PRI_ACCUM_PS_2__COEFFICIENT_HIER_SELECT__SHIFT                                        0x7
15958 #define SPI_SHADER_PREF_PRI_ACCUM_PS_2__CONTRIBUTION_HIER_SELECT__SHIFT                                       0xa
15959 #define SPI_SHADER_PREF_PRI_ACCUM_PS_2__GROUP_UPDATE_EN__SHIFT                                                0xd
15960 #define SPI_SHADER_PREF_PRI_ACCUM_PS_2__RESERVED__SHIFT                                                       0xe
15961 #define SPI_SHADER_PREF_PRI_ACCUM_PS_2__COEFFICIENT__SHIFT                                                    0xf
15962 #define SPI_SHADER_PREF_PRI_ACCUM_PS_2__CONTRIBUTION_MASK                                                     0x0000007FL
15963 #define SPI_SHADER_PREF_PRI_ACCUM_PS_2__COEFFICIENT_HIER_SELECT_MASK                                          0x00000380L
15964 #define SPI_SHADER_PREF_PRI_ACCUM_PS_2__CONTRIBUTION_HIER_SELECT_MASK                                         0x00001C00L
15965 #define SPI_SHADER_PREF_PRI_ACCUM_PS_2__GROUP_UPDATE_EN_MASK                                                  0x00002000L
15966 #define SPI_SHADER_PREF_PRI_ACCUM_PS_2__RESERVED_MASK                                                         0x00004000L
15967 #define SPI_SHADER_PREF_PRI_ACCUM_PS_2__COEFFICIENT_MASK                                                      0x007F8000L
15968 //SPI_SHADER_USER_ACCUM_PS_2
15969 #define SPI_SHADER_USER_ACCUM_PS_2__CONTRIBUTION__SHIFT                                                       0x0
15970 #define SPI_SHADER_USER_ACCUM_PS_2__CONTRIBUTION_MASK                                                         0x0000007FL
15971 //SPI_SHADER_PREF_PRI_ACCUM_PS_3
15972 #define SPI_SHADER_PREF_PRI_ACCUM_PS_3__CONTRIBUTION__SHIFT                                                   0x0
15973 #define SPI_SHADER_PREF_PRI_ACCUM_PS_3__COEFFICIENT_HIER_SELECT__SHIFT                                        0x7
15974 #define SPI_SHADER_PREF_PRI_ACCUM_PS_3__CONTRIBUTION_HIER_SELECT__SHIFT                                       0xa
15975 #define SPI_SHADER_PREF_PRI_ACCUM_PS_3__GROUP_UPDATE_EN__SHIFT                                                0xd
15976 #define SPI_SHADER_PREF_PRI_ACCUM_PS_3__RESERVED__SHIFT                                                       0xe
15977 #define SPI_SHADER_PREF_PRI_ACCUM_PS_3__COEFFICIENT__SHIFT                                                    0xf
15978 #define SPI_SHADER_PREF_PRI_ACCUM_PS_3__CONTRIBUTION_MASK                                                     0x0000007FL
15979 #define SPI_SHADER_PREF_PRI_ACCUM_PS_3__COEFFICIENT_HIER_SELECT_MASK                                          0x00000380L
15980 #define SPI_SHADER_PREF_PRI_ACCUM_PS_3__CONTRIBUTION_HIER_SELECT_MASK                                         0x00001C00L
15981 #define SPI_SHADER_PREF_PRI_ACCUM_PS_3__GROUP_UPDATE_EN_MASK                                                  0x00002000L
15982 #define SPI_SHADER_PREF_PRI_ACCUM_PS_3__RESERVED_MASK                                                         0x00004000L
15983 #define SPI_SHADER_PREF_PRI_ACCUM_PS_3__COEFFICIENT_MASK                                                      0x007F8000L
15984 //SPI_SHADER_USER_ACCUM_PS_3
15985 #define SPI_SHADER_USER_ACCUM_PS_3__CONTRIBUTION__SHIFT                                                       0x0
15986 #define SPI_SHADER_USER_ACCUM_PS_3__CONTRIBUTION_MASK                                                         0x0000007FL
15987 //SPI_SHADER_PGM_RSRC4_VS
15988 #define SPI_SHADER_PGM_RSRC4_VS__CU_EN__SHIFT                                                                 0x0
15989 #define SPI_SHADER_PGM_RSRC4_VS__CU_EN_MASK                                                                   0x0000FFFFL
15990 //SPI_SHADER_PGM_CHKSUM_VS
15991 #define SPI_SHADER_PGM_CHKSUM_VS__CHECKSUM__SHIFT                                                             0x0
15992 #define SPI_SHADER_PGM_CHKSUM_VS__CHECKSUM_MASK                                                               0xFFFFFFFFL
15993 //SPI_SHADER_PGM_RSRC3_VS
15994 #define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT                                                                 0x0
15995 #define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT                                                            0x10
15996 #define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT                                                    0x16
15997 #define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK                                                                   0x0000FFFFL
15998 #define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK                                                              0x003F0000L
15999 #define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK                                                      0x03C00000L
16000 //SPI_SHADER_LATE_ALLOC_VS
16001 #define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT                                                                0x0
16002 #define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK                                                                  0x0000003FL
16003 //SPI_SHADER_PGM_LO_VS
16004 #define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT                                                                 0x0
16005 #define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK                                                                   0xFFFFFFFFL
16006 //SPI_SHADER_PGM_HI_VS
16007 #define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT                                                                 0x0
16008 #define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK                                                                   0xFFL
16009 //SPI_SHADER_PGM_RSRC1_VS
16010 #define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT                                                                 0x0
16011 #define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT                                                                 0x6
16012 #define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT                                                              0xa
16013 #define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT                                                            0xc
16014 #define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT                                                                  0x14
16015 #define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT                                                            0x15
16016 #define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT                                                             0x17
16017 #define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT                                                         0x18
16018 #define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT                                                       0x1a
16019 #define SPI_SHADER_PGM_RSRC1_VS__MEM_ORDERED__SHIFT                                                           0x1b
16020 #define SPI_SHADER_PGM_RSRC1_VS__FWD_PROGRESS__SHIFT                                                          0x1c
16021 #define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL__SHIFT                                                             0x1f
16022 #define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK                                                                   0x0000003FL
16023 #define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK                                                                   0x000003C0L
16024 #define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK                                                                0x00000C00L
16025 #define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK                                                              0x000FF000L
16026 #define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK                                                                    0x00100000L
16027 #define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK                                                              0x00200000L
16028 #define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK                                                               0x00800000L
16029 #define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK                                                           0x03000000L
16030 #define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK                                                         0x04000000L
16031 #define SPI_SHADER_PGM_RSRC1_VS__MEM_ORDERED_MASK                                                             0x08000000L
16032 #define SPI_SHADER_PGM_RSRC1_VS__FWD_PROGRESS_MASK                                                            0x10000000L
16033 #define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL_MASK                                                               0x80000000L
16034 //SPI_SHADER_PGM_RSRC2_VS
16035 #define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT                                                            0x0
16036 #define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT                                                             0x1
16037 #define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT                                                          0x6
16038 #define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT                                                             0x7
16039 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT                                                           0x8
16040 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT                                                           0x9
16041 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT                                                           0xa
16042 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT                                                           0xb
16043 #define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT                                                                 0xc
16044 #define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT                                                               0xd
16045 #define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN__SHIFT                                                            0x16
16046 #define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN__SHIFT                                                      0x18
16047 #define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB__SHIFT                                                         0x1b
16048 #define SPI_SHADER_PGM_RSRC2_VS__SHARED_VGPR_CNT__SHIFT                                                       0x1c
16049 #define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK                                                              0x00000001L
16050 #define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK                                                               0x0000003EL
16051 #define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK                                                            0x00000040L
16052 #define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK                                                               0x00000080L
16053 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK                                                             0x00000100L
16054 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK                                                             0x00000200L
16055 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK                                                             0x00000400L
16056 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK                                                             0x00000800L
16057 #define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK                                                                   0x00001000L
16058 #define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK                                                                 0x003FE000L
16059 #define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN_MASK                                                              0x00400000L
16060 #define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN_MASK                                                        0x01000000L
16061 #define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB_MASK                                                           0x08000000L
16062 #define SPI_SHADER_PGM_RSRC2_VS__SHARED_VGPR_CNT_MASK                                                         0xF0000000L
16063 //SPI_SHADER_USER_DATA_VS_0
16064 #define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT                                                                0x0
16065 #define SPI_SHADER_USER_DATA_VS_0__DATA_MASK                                                                  0xFFFFFFFFL
16066 //SPI_SHADER_USER_DATA_VS_1
16067 #define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT                                                                0x0
16068 #define SPI_SHADER_USER_DATA_VS_1__DATA_MASK                                                                  0xFFFFFFFFL
16069 //SPI_SHADER_USER_DATA_VS_2
16070 #define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT                                                                0x0
16071 #define SPI_SHADER_USER_DATA_VS_2__DATA_MASK                                                                  0xFFFFFFFFL
16072 //SPI_SHADER_USER_DATA_VS_3
16073 #define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT                                                                0x0
16074 #define SPI_SHADER_USER_DATA_VS_3__DATA_MASK                                                                  0xFFFFFFFFL
16075 //SPI_SHADER_USER_DATA_VS_4
16076 #define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT                                                                0x0
16077 #define SPI_SHADER_USER_DATA_VS_4__DATA_MASK                                                                  0xFFFFFFFFL
16078 //SPI_SHADER_USER_DATA_VS_5
16079 #define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT                                                                0x0
16080 #define SPI_SHADER_USER_DATA_VS_5__DATA_MASK                                                                  0xFFFFFFFFL
16081 //SPI_SHADER_USER_DATA_VS_6
16082 #define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT                                                                0x0
16083 #define SPI_SHADER_USER_DATA_VS_6__DATA_MASK                                                                  0xFFFFFFFFL
16084 //SPI_SHADER_USER_DATA_VS_7
16085 #define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT                                                                0x0
16086 #define SPI_SHADER_USER_DATA_VS_7__DATA_MASK                                                                  0xFFFFFFFFL
16087 //SPI_SHADER_USER_DATA_VS_8
16088 #define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT                                                                0x0
16089 #define SPI_SHADER_USER_DATA_VS_8__DATA_MASK                                                                  0xFFFFFFFFL
16090 //SPI_SHADER_USER_DATA_VS_9
16091 #define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT                                                                0x0
16092 #define SPI_SHADER_USER_DATA_VS_9__DATA_MASK                                                                  0xFFFFFFFFL
16093 //SPI_SHADER_USER_DATA_VS_10
16094 #define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT                                                               0x0
16095 #define SPI_SHADER_USER_DATA_VS_10__DATA_MASK                                                                 0xFFFFFFFFL
16096 //SPI_SHADER_USER_DATA_VS_11
16097 #define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT                                                               0x0
16098 #define SPI_SHADER_USER_DATA_VS_11__DATA_MASK                                                                 0xFFFFFFFFL
16099 //SPI_SHADER_USER_DATA_VS_12
16100 #define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT                                                               0x0
16101 #define SPI_SHADER_USER_DATA_VS_12__DATA_MASK                                                                 0xFFFFFFFFL
16102 //SPI_SHADER_USER_DATA_VS_13
16103 #define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT                                                               0x0
16104 #define SPI_SHADER_USER_DATA_VS_13__DATA_MASK                                                                 0xFFFFFFFFL
16105 //SPI_SHADER_USER_DATA_VS_14
16106 #define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT                                                               0x0
16107 #define SPI_SHADER_USER_DATA_VS_14__DATA_MASK                                                                 0xFFFFFFFFL
16108 //SPI_SHADER_USER_DATA_VS_15
16109 #define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT                                                               0x0
16110 #define SPI_SHADER_USER_DATA_VS_15__DATA_MASK                                                                 0xFFFFFFFFL
16111 //SPI_SHADER_USER_DATA_VS_16
16112 #define SPI_SHADER_USER_DATA_VS_16__DATA__SHIFT                                                               0x0
16113 #define SPI_SHADER_USER_DATA_VS_16__DATA_MASK                                                                 0xFFFFFFFFL
16114 //SPI_SHADER_USER_DATA_VS_17
16115 #define SPI_SHADER_USER_DATA_VS_17__DATA__SHIFT                                                               0x0
16116 #define SPI_SHADER_USER_DATA_VS_17__DATA_MASK                                                                 0xFFFFFFFFL
16117 //SPI_SHADER_USER_DATA_VS_18
16118 #define SPI_SHADER_USER_DATA_VS_18__DATA__SHIFT                                                               0x0
16119 #define SPI_SHADER_USER_DATA_VS_18__DATA_MASK                                                                 0xFFFFFFFFL
16120 //SPI_SHADER_USER_DATA_VS_19
16121 #define SPI_SHADER_USER_DATA_VS_19__DATA__SHIFT                                                               0x0
16122 #define SPI_SHADER_USER_DATA_VS_19__DATA_MASK                                                                 0xFFFFFFFFL
16123 //SPI_SHADER_USER_DATA_VS_20
16124 #define SPI_SHADER_USER_DATA_VS_20__DATA__SHIFT                                                               0x0
16125 #define SPI_SHADER_USER_DATA_VS_20__DATA_MASK                                                                 0xFFFFFFFFL
16126 //SPI_SHADER_USER_DATA_VS_21
16127 #define SPI_SHADER_USER_DATA_VS_21__DATA__SHIFT                                                               0x0
16128 #define SPI_SHADER_USER_DATA_VS_21__DATA_MASK                                                                 0xFFFFFFFFL
16129 //SPI_SHADER_USER_DATA_VS_22
16130 #define SPI_SHADER_USER_DATA_VS_22__DATA__SHIFT                                                               0x0
16131 #define SPI_SHADER_USER_DATA_VS_22__DATA_MASK                                                                 0xFFFFFFFFL
16132 //SPI_SHADER_USER_DATA_VS_23
16133 #define SPI_SHADER_USER_DATA_VS_23__DATA__SHIFT                                                               0x0
16134 #define SPI_SHADER_USER_DATA_VS_23__DATA_MASK                                                                 0xFFFFFFFFL
16135 //SPI_SHADER_USER_DATA_VS_24
16136 #define SPI_SHADER_USER_DATA_VS_24__DATA__SHIFT                                                               0x0
16137 #define SPI_SHADER_USER_DATA_VS_24__DATA_MASK                                                                 0xFFFFFFFFL
16138 //SPI_SHADER_USER_DATA_VS_25
16139 #define SPI_SHADER_USER_DATA_VS_25__DATA__SHIFT                                                               0x0
16140 #define SPI_SHADER_USER_DATA_VS_25__DATA_MASK                                                                 0xFFFFFFFFL
16141 //SPI_SHADER_USER_DATA_VS_26
16142 #define SPI_SHADER_USER_DATA_VS_26__DATA__SHIFT                                                               0x0
16143 #define SPI_SHADER_USER_DATA_VS_26__DATA_MASK                                                                 0xFFFFFFFFL
16144 //SPI_SHADER_USER_DATA_VS_27
16145 #define SPI_SHADER_USER_DATA_VS_27__DATA__SHIFT                                                               0x0
16146 #define SPI_SHADER_USER_DATA_VS_27__DATA_MASK                                                                 0xFFFFFFFFL
16147 //SPI_SHADER_USER_DATA_VS_28
16148 #define SPI_SHADER_USER_DATA_VS_28__DATA__SHIFT                                                               0x0
16149 #define SPI_SHADER_USER_DATA_VS_28__DATA_MASK                                                                 0xFFFFFFFFL
16150 //SPI_SHADER_USER_DATA_VS_29
16151 #define SPI_SHADER_USER_DATA_VS_29__DATA__SHIFT                                                               0x0
16152 #define SPI_SHADER_USER_DATA_VS_29__DATA_MASK                                                                 0xFFFFFFFFL
16153 //SPI_SHADER_USER_DATA_VS_30
16154 #define SPI_SHADER_USER_DATA_VS_30__DATA__SHIFT                                                               0x0
16155 #define SPI_SHADER_USER_DATA_VS_30__DATA_MASK                                                                 0xFFFFFFFFL
16156 //SPI_SHADER_USER_DATA_VS_31
16157 #define SPI_SHADER_USER_DATA_VS_31__DATA__SHIFT                                                               0x0
16158 #define SPI_SHADER_USER_DATA_VS_31__DATA_MASK                                                                 0xFFFFFFFFL
16159 //SPI_SHADER_REQ_CTRL_VS
16160 #define SPI_SHADER_REQ_CTRL_VS__SOFT_GROUPING_EN__SHIFT                                                       0x0
16161 #define SPI_SHADER_REQ_CTRL_VS__NUMBER_OF_REQUESTS_PER_CU__SHIFT                                              0x1
16162 #define SPI_SHADER_REQ_CTRL_VS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT                                       0x5
16163 #define SPI_SHADER_REQ_CTRL_VS__HARD_LOCK_HYSTERESIS__SHIFT                                                   0x9
16164 #define SPI_SHADER_REQ_CTRL_VS__HARD_LOCK_LOW_THRESHOLD__SHIFT                                                0xa
16165 #define SPI_SHADER_REQ_CTRL_VS__PRODUCER_REQUEST_LOCKOUT__SHIFT                                               0xf
16166 #define SPI_SHADER_REQ_CTRL_VS__GLOBAL_SCANNING_EN__SHIFT                                                     0x10
16167 #define SPI_SHADER_REQ_CTRL_VS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT                                   0x11
16168 #define SPI_SHADER_REQ_CTRL_VS__SOFT_GROUPING_EN_MASK                                                         0x00000001L
16169 #define SPI_SHADER_REQ_CTRL_VS__NUMBER_OF_REQUESTS_PER_CU_MASK                                                0x0000001EL
16170 #define SPI_SHADER_REQ_CTRL_VS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK                                         0x000001E0L
16171 #define SPI_SHADER_REQ_CTRL_VS__HARD_LOCK_HYSTERESIS_MASK                                                     0x00000200L
16172 #define SPI_SHADER_REQ_CTRL_VS__HARD_LOCK_LOW_THRESHOLD_MASK                                                  0x00007C00L
16173 #define SPI_SHADER_REQ_CTRL_VS__PRODUCER_REQUEST_LOCKOUT_MASK                                                 0x00008000L
16174 #define SPI_SHADER_REQ_CTRL_VS__GLOBAL_SCANNING_EN_MASK                                                       0x00010000L
16175 #define SPI_SHADER_REQ_CTRL_VS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK                                     0x000E0000L
16176 //SPI_SHADER_PREF_PRI_CNTR_CTRL_VS
16177 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_VS__TOTAL_WAVE_COUNT_HIER_SELECT__SHIFT                                 0x0
16178 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_VS__PER_TYPE_WAVE_COUNT_HIER_SELECT__SHIFT                              0x3
16179 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_VS__GROUP_UPDATE_EN__SHIFT                                              0x6
16180 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_VS__TOTAL_WAVE_COUNT_COEFFICIENT__SHIFT                                 0x8
16181 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_VS__PER_TYPE_WAVE_COUNT_COEFFICIENT__SHIFT                              0x10
16182 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_VS__TOTAL_WAVE_COUNT_HIER_SELECT_MASK                                   0x00000007L
16183 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_VS__PER_TYPE_WAVE_COUNT_HIER_SELECT_MASK                                0x00000038L
16184 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_VS__GROUP_UPDATE_EN_MASK                                                0x00000040L
16185 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_VS__TOTAL_WAVE_COUNT_COEFFICIENT_MASK                                   0x0000FF00L
16186 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_VS__PER_TYPE_WAVE_COUNT_COEFFICIENT_MASK                                0x00FF0000L
16187 //SPI_SHADER_PREF_PRI_ACCUM_VS_0
16188 #define SPI_SHADER_PREF_PRI_ACCUM_VS_0__CONTRIBUTION__SHIFT                                                   0x0
16189 #define SPI_SHADER_PREF_PRI_ACCUM_VS_0__COEFFICIENT_HIER_SELECT__SHIFT                                        0x7
16190 #define SPI_SHADER_PREF_PRI_ACCUM_VS_0__CONTRIBUTION_HIER_SELECT__SHIFT                                       0xa
16191 #define SPI_SHADER_PREF_PRI_ACCUM_VS_0__GROUP_UPDATE_EN__SHIFT                                                0xd
16192 #define SPI_SHADER_PREF_PRI_ACCUM_VS_0__RESERVED__SHIFT                                                       0xe
16193 #define SPI_SHADER_PREF_PRI_ACCUM_VS_0__COEFFICIENT__SHIFT                                                    0xf
16194 #define SPI_SHADER_PREF_PRI_ACCUM_VS_0__CONTRIBUTION_MASK                                                     0x0000007FL
16195 #define SPI_SHADER_PREF_PRI_ACCUM_VS_0__COEFFICIENT_HIER_SELECT_MASK                                          0x00000380L
16196 #define SPI_SHADER_PREF_PRI_ACCUM_VS_0__CONTRIBUTION_HIER_SELECT_MASK                                         0x00001C00L
16197 #define SPI_SHADER_PREF_PRI_ACCUM_VS_0__GROUP_UPDATE_EN_MASK                                                  0x00002000L
16198 #define SPI_SHADER_PREF_PRI_ACCUM_VS_0__RESERVED_MASK                                                         0x00004000L
16199 #define SPI_SHADER_PREF_PRI_ACCUM_VS_0__COEFFICIENT_MASK                                                      0x007F8000L
16200 //SPI_SHADER_USER_ACCUM_VS_0
16201 #define SPI_SHADER_USER_ACCUM_VS_0__CONTRIBUTION__SHIFT                                                       0x0
16202 #define SPI_SHADER_USER_ACCUM_VS_0__CONTRIBUTION_MASK                                                         0x0000007FL
16203 //SPI_SHADER_PREF_PRI_ACCUM_VS_1
16204 #define SPI_SHADER_PREF_PRI_ACCUM_VS_1__CONTRIBUTION__SHIFT                                                   0x0
16205 #define SPI_SHADER_PREF_PRI_ACCUM_VS_1__COEFFICIENT_HIER_SELECT__SHIFT                                        0x7
16206 #define SPI_SHADER_PREF_PRI_ACCUM_VS_1__CONTRIBUTION_HIER_SELECT__SHIFT                                       0xa
16207 #define SPI_SHADER_PREF_PRI_ACCUM_VS_1__GROUP_UPDATE_EN__SHIFT                                                0xd
16208 #define SPI_SHADER_PREF_PRI_ACCUM_VS_1__RESERVED__SHIFT                                                       0xe
16209 #define SPI_SHADER_PREF_PRI_ACCUM_VS_1__COEFFICIENT__SHIFT                                                    0xf
16210 #define SPI_SHADER_PREF_PRI_ACCUM_VS_1__CONTRIBUTION_MASK                                                     0x0000007FL
16211 #define SPI_SHADER_PREF_PRI_ACCUM_VS_1__COEFFICIENT_HIER_SELECT_MASK                                          0x00000380L
16212 #define SPI_SHADER_PREF_PRI_ACCUM_VS_1__CONTRIBUTION_HIER_SELECT_MASK                                         0x00001C00L
16213 #define SPI_SHADER_PREF_PRI_ACCUM_VS_1__GROUP_UPDATE_EN_MASK                                                  0x00002000L
16214 #define SPI_SHADER_PREF_PRI_ACCUM_VS_1__RESERVED_MASK                                                         0x00004000L
16215 #define SPI_SHADER_PREF_PRI_ACCUM_VS_1__COEFFICIENT_MASK                                                      0x007F8000L
16216 //SPI_SHADER_USER_ACCUM_VS_1
16217 #define SPI_SHADER_USER_ACCUM_VS_1__CONTRIBUTION__SHIFT                                                       0x0
16218 #define SPI_SHADER_USER_ACCUM_VS_1__CONTRIBUTION_MASK                                                         0x0000007FL
16219 //SPI_SHADER_PREF_PRI_ACCUM_VS_2
16220 #define SPI_SHADER_PREF_PRI_ACCUM_VS_2__CONTRIBUTION__SHIFT                                                   0x0
16221 #define SPI_SHADER_PREF_PRI_ACCUM_VS_2__COEFFICIENT_HIER_SELECT__SHIFT                                        0x7
16222 #define SPI_SHADER_PREF_PRI_ACCUM_VS_2__CONTRIBUTION_HIER_SELECT__SHIFT                                       0xa
16223 #define SPI_SHADER_PREF_PRI_ACCUM_VS_2__GROUP_UPDATE_EN__SHIFT                                                0xd
16224 #define SPI_SHADER_PREF_PRI_ACCUM_VS_2__RESERVED__SHIFT                                                       0xe
16225 #define SPI_SHADER_PREF_PRI_ACCUM_VS_2__COEFFICIENT__SHIFT                                                    0xf
16226 #define SPI_SHADER_PREF_PRI_ACCUM_VS_2__CONTRIBUTION_MASK                                                     0x0000007FL
16227 #define SPI_SHADER_PREF_PRI_ACCUM_VS_2__COEFFICIENT_HIER_SELECT_MASK                                          0x00000380L
16228 #define SPI_SHADER_PREF_PRI_ACCUM_VS_2__CONTRIBUTION_HIER_SELECT_MASK                                         0x00001C00L
16229 #define SPI_SHADER_PREF_PRI_ACCUM_VS_2__GROUP_UPDATE_EN_MASK                                                  0x00002000L
16230 #define SPI_SHADER_PREF_PRI_ACCUM_VS_2__RESERVED_MASK                                                         0x00004000L
16231 #define SPI_SHADER_PREF_PRI_ACCUM_VS_2__COEFFICIENT_MASK                                                      0x007F8000L
16232 //SPI_SHADER_USER_ACCUM_VS_2
16233 #define SPI_SHADER_USER_ACCUM_VS_2__CONTRIBUTION__SHIFT                                                       0x0
16234 #define SPI_SHADER_USER_ACCUM_VS_2__CONTRIBUTION_MASK                                                         0x0000007FL
16235 //SPI_SHADER_PREF_PRI_ACCUM_VS_3
16236 #define SPI_SHADER_PREF_PRI_ACCUM_VS_3__CONTRIBUTION__SHIFT                                                   0x0
16237 #define SPI_SHADER_PREF_PRI_ACCUM_VS_3__COEFFICIENT_HIER_SELECT__SHIFT                                        0x7
16238 #define SPI_SHADER_PREF_PRI_ACCUM_VS_3__CONTRIBUTION_HIER_SELECT__SHIFT                                       0xa
16239 #define SPI_SHADER_PREF_PRI_ACCUM_VS_3__GROUP_UPDATE_EN__SHIFT                                                0xd
16240 #define SPI_SHADER_PREF_PRI_ACCUM_VS_3__RESERVED__SHIFT                                                       0xe
16241 #define SPI_SHADER_PREF_PRI_ACCUM_VS_3__COEFFICIENT__SHIFT                                                    0xf
16242 #define SPI_SHADER_PREF_PRI_ACCUM_VS_3__CONTRIBUTION_MASK                                                     0x0000007FL
16243 #define SPI_SHADER_PREF_PRI_ACCUM_VS_3__COEFFICIENT_HIER_SELECT_MASK                                          0x00000380L
16244 #define SPI_SHADER_PREF_PRI_ACCUM_VS_3__CONTRIBUTION_HIER_SELECT_MASK                                         0x00001C00L
16245 #define SPI_SHADER_PREF_PRI_ACCUM_VS_3__GROUP_UPDATE_EN_MASK                                                  0x00002000L
16246 #define SPI_SHADER_PREF_PRI_ACCUM_VS_3__RESERVED_MASK                                                         0x00004000L
16247 #define SPI_SHADER_PREF_PRI_ACCUM_VS_3__COEFFICIENT_MASK                                                      0x007F8000L
16248 //SPI_SHADER_USER_ACCUM_VS_3
16249 #define SPI_SHADER_USER_ACCUM_VS_3__CONTRIBUTION__SHIFT                                                       0x0
16250 #define SPI_SHADER_USER_ACCUM_VS_3__CONTRIBUTION_MASK                                                         0x0000007FL
16251 //SPI_SHADER_PGM_RSRC2_GS_VS
16252 #define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN__SHIFT                                                         0x0
16253 #define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR__SHIFT                                                          0x1
16254 #define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT__SHIFT                                                       0x6
16255 #define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN__SHIFT                                                            0x7
16256 #define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT__SHIFT                                                      0x10
16257 #define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN__SHIFT                                                          0x12
16258 #define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE__SHIFT                                                           0x13
16259 #define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0__SHIFT                                                        0x1b
16260 #define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB__SHIFT                                                      0x1c
16261 #define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN_MASK                                                           0x00000001L
16262 #define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MASK                                                            0x0000003EL
16263 #define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT_MASK                                                         0x00000040L
16264 #define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN_MASK                                                              0x0000FF80L
16265 #define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT_MASK                                                        0x00030000L
16266 #define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN_MASK                                                            0x00040000L
16267 #define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE_MASK                                                             0x07F80000L
16268 #define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0_MASK                                                          0x08000000L
16269 #define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB_MASK                                                        0x10000000L
16270 //SPI_SHADER_PGM_RSRC2_ES_VS
16271 #define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN__SHIFT                                                         0x0
16272 #define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR__SHIFT                                                          0x1
16273 #define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT__SHIFT                                                       0x6
16274 #define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN__SHIFT                                                          0x7
16275 #define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN__SHIFT                                                            0x8
16276 #define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE__SHIFT                                                           0x14
16277 #define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN_MASK                                                           0x00000001L
16278 #define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR_MASK                                                            0x0000003EL
16279 #define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT_MASK                                                         0x00000040L
16280 #define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN_MASK                                                            0x00000080L
16281 #define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN_MASK                                                              0x0001FF00L
16282 #define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE_MASK                                                             0x1FF00000L
16283 //SPI_SHADER_PGM_RSRC2_LS_VS
16284 #define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN__SHIFT                                                         0x0
16285 #define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR__SHIFT                                                          0x1
16286 #define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT__SHIFT                                                       0x6
16287 #define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE__SHIFT                                                           0x7
16288 #define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN__SHIFT                                                            0x10
16289 #define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN_MASK                                                           0x00000001L
16290 #define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR_MASK                                                            0x0000003EL
16291 #define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT_MASK                                                         0x00000040L
16292 #define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE_MASK                                                             0x0000FF80L
16293 #define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN_MASK                                                              0x01FF0000L
16294 //SPI_SHADER_PGM_CHKSUM_GS
16295 #define SPI_SHADER_PGM_CHKSUM_GS__CHECKSUM__SHIFT                                                             0x0
16296 #define SPI_SHADER_PGM_CHKSUM_GS__CHECKSUM_MASK                                                               0xFFFFFFFFL
16297 //SPI_SHADER_PGM_RSRC4_GS
16298 #define SPI_SHADER_PGM_RSRC4_GS__CU_EN__SHIFT                                                                 0x0
16299 #define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS__SHIFT                                              0x10
16300 #define SPI_SHADER_PGM_RSRC4_GS__CU_EN_MASK                                                                   0x0000FFFFL
16301 #define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS_MASK                                                0x007F0000L
16302 //SPI_SHADER_USER_DATA_ADDR_LO_GS
16303 #define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE__SHIFT                                                      0x0
16304 #define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE_MASK                                                        0xFFFFFFFFL
16305 //SPI_SHADER_USER_DATA_ADDR_HI_GS
16306 #define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE__SHIFT                                                      0x0
16307 #define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE_MASK                                                        0xFFFFFFFFL
16308 //SPI_SHADER_PGM_LO_ES_GS
16309 #define SPI_SHADER_PGM_LO_ES_GS__MEM_BASE__SHIFT                                                              0x0
16310 #define SPI_SHADER_PGM_LO_ES_GS__MEM_BASE_MASK                                                                0xFFFFFFFFL
16311 //SPI_SHADER_PGM_HI_ES_GS
16312 #define SPI_SHADER_PGM_HI_ES_GS__MEM_BASE__SHIFT                                                              0x0
16313 #define SPI_SHADER_PGM_HI_ES_GS__MEM_BASE_MASK                                                                0xFFL
16314 //SPI_SHADER_PGM_RSRC3_GS
16315 #define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT                                                                 0x0
16316 #define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT                                                            0x10
16317 #define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT                                                    0x16
16318 #define SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH__SHIFT                                                      0x1a
16319 #define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK                                                                   0x0000FFFFL
16320 #define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK                                                              0x003F0000L
16321 #define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK                                                      0x03C00000L
16322 #define SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH_MASK                                                        0xFC000000L
16323 //SPI_SHADER_PGM_LO_GS
16324 #define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT                                                                 0x0
16325 #define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK                                                                   0xFFFFFFFFL
16326 //SPI_SHADER_PGM_HI_GS
16327 #define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT                                                                 0x0
16328 #define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK                                                                   0xFFL
16329 //SPI_SHADER_PGM_RSRC1_GS
16330 #define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT                                                                 0x0
16331 #define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT                                                                 0x6
16332 #define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT                                                              0xa
16333 #define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT                                                            0xc
16334 #define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT                                                                  0x14
16335 #define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT                                                            0x15
16336 #define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT                                                             0x17
16337 #define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT                                                       0x18
16338 #define SPI_SHADER_PGM_RSRC1_GS__MEM_ORDERED__SHIFT                                                           0x19
16339 #define SPI_SHADER_PGM_RSRC1_GS__FWD_PROGRESS__SHIFT                                                          0x1a
16340 #define SPI_SHADER_PGM_RSRC1_GS__WGP_MODE__SHIFT                                                              0x1b
16341 #define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT__SHIFT                                                      0x1d
16342 #define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL__SHIFT                                                             0x1f
16343 #define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK                                                                   0x0000003FL
16344 #define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK                                                                   0x000003C0L
16345 #define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK                                                                0x00000C00L
16346 #define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK                                                              0x000FF000L
16347 #define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK                                                                    0x00100000L
16348 #define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK                                                              0x00200000L
16349 #define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK                                                               0x00800000L
16350 #define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK                                                         0x01000000L
16351 #define SPI_SHADER_PGM_RSRC1_GS__MEM_ORDERED_MASK                                                             0x02000000L
16352 #define SPI_SHADER_PGM_RSRC1_GS__FWD_PROGRESS_MASK                                                            0x04000000L
16353 #define SPI_SHADER_PGM_RSRC1_GS__WGP_MODE_MASK                                                                0x08000000L
16354 #define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT_MASK                                                        0x60000000L
16355 #define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL_MASK                                                               0x80000000L
16356 //SPI_SHADER_PGM_RSRC2_GS
16357 #define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT                                                            0x0
16358 #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT                                                             0x1
16359 #define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT                                                          0x6
16360 #define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT                                                               0x7
16361 #define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT__SHIFT                                                      0x10
16362 #define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN__SHIFT                                                             0x12
16363 #define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE__SHIFT                                                              0x13
16364 #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB__SHIFT                                                         0x1b
16365 #define SPI_SHADER_PGM_RSRC2_GS__SHARED_VGPR_CNT__SHIFT                                                       0x1c
16366 #define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK                                                              0x00000001L
16367 #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK                                                               0x0000003EL
16368 #define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK                                                            0x00000040L
16369 #define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK                                                                 0x0000FF80L
16370 #define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT_MASK                                                        0x00030000L
16371 #define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN_MASK                                                               0x00040000L
16372 #define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE_MASK                                                                0x07F80000L
16373 #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB_MASK                                                           0x08000000L
16374 #define SPI_SHADER_PGM_RSRC2_GS__SHARED_VGPR_CNT_MASK                                                         0xF0000000L
16375 //SPI_SHADER_USER_DATA_GS_0
16376 #define SPI_SHADER_USER_DATA_GS_0__DATA__SHIFT                                                                0x0
16377 #define SPI_SHADER_USER_DATA_GS_0__DATA_MASK                                                                  0xFFFFFFFFL
16378 //SPI_SHADER_USER_DATA_GS_1
16379 #define SPI_SHADER_USER_DATA_GS_1__DATA__SHIFT                                                                0x0
16380 #define SPI_SHADER_USER_DATA_GS_1__DATA_MASK                                                                  0xFFFFFFFFL
16381 //SPI_SHADER_USER_DATA_GS_2
16382 #define SPI_SHADER_USER_DATA_GS_2__DATA__SHIFT                                                                0x0
16383 #define SPI_SHADER_USER_DATA_GS_2__DATA_MASK                                                                  0xFFFFFFFFL
16384 //SPI_SHADER_USER_DATA_GS_3
16385 #define SPI_SHADER_USER_DATA_GS_3__DATA__SHIFT                                                                0x0
16386 #define SPI_SHADER_USER_DATA_GS_3__DATA_MASK                                                                  0xFFFFFFFFL
16387 //SPI_SHADER_USER_DATA_GS_4
16388 #define SPI_SHADER_USER_DATA_GS_4__DATA__SHIFT                                                                0x0
16389 #define SPI_SHADER_USER_DATA_GS_4__DATA_MASK                                                                  0xFFFFFFFFL
16390 //SPI_SHADER_USER_DATA_GS_5
16391 #define SPI_SHADER_USER_DATA_GS_5__DATA__SHIFT                                                                0x0
16392 #define SPI_SHADER_USER_DATA_GS_5__DATA_MASK                                                                  0xFFFFFFFFL
16393 //SPI_SHADER_USER_DATA_GS_6
16394 #define SPI_SHADER_USER_DATA_GS_6__DATA__SHIFT                                                                0x0
16395 #define SPI_SHADER_USER_DATA_GS_6__DATA_MASK                                                                  0xFFFFFFFFL
16396 //SPI_SHADER_USER_DATA_GS_7
16397 #define SPI_SHADER_USER_DATA_GS_7__DATA__SHIFT                                                                0x0
16398 #define SPI_SHADER_USER_DATA_GS_7__DATA_MASK                                                                  0xFFFFFFFFL
16399 //SPI_SHADER_USER_DATA_GS_8
16400 #define SPI_SHADER_USER_DATA_GS_8__DATA__SHIFT                                                                0x0
16401 #define SPI_SHADER_USER_DATA_GS_8__DATA_MASK                                                                  0xFFFFFFFFL
16402 //SPI_SHADER_USER_DATA_GS_9
16403 #define SPI_SHADER_USER_DATA_GS_9__DATA__SHIFT                                                                0x0
16404 #define SPI_SHADER_USER_DATA_GS_9__DATA_MASK                                                                  0xFFFFFFFFL
16405 //SPI_SHADER_USER_DATA_GS_10
16406 #define SPI_SHADER_USER_DATA_GS_10__DATA__SHIFT                                                               0x0
16407 #define SPI_SHADER_USER_DATA_GS_10__DATA_MASK                                                                 0xFFFFFFFFL
16408 //SPI_SHADER_USER_DATA_GS_11
16409 #define SPI_SHADER_USER_DATA_GS_11__DATA__SHIFT                                                               0x0
16410 #define SPI_SHADER_USER_DATA_GS_11__DATA_MASK                                                                 0xFFFFFFFFL
16411 //SPI_SHADER_USER_DATA_GS_12
16412 #define SPI_SHADER_USER_DATA_GS_12__DATA__SHIFT                                                               0x0
16413 #define SPI_SHADER_USER_DATA_GS_12__DATA_MASK                                                                 0xFFFFFFFFL
16414 //SPI_SHADER_USER_DATA_GS_13
16415 #define SPI_SHADER_USER_DATA_GS_13__DATA__SHIFT                                                               0x0
16416 #define SPI_SHADER_USER_DATA_GS_13__DATA_MASK                                                                 0xFFFFFFFFL
16417 //SPI_SHADER_USER_DATA_GS_14
16418 #define SPI_SHADER_USER_DATA_GS_14__DATA__SHIFT                                                               0x0
16419 #define SPI_SHADER_USER_DATA_GS_14__DATA_MASK                                                                 0xFFFFFFFFL
16420 //SPI_SHADER_USER_DATA_GS_15
16421 #define SPI_SHADER_USER_DATA_GS_15__DATA__SHIFT                                                               0x0
16422 #define SPI_SHADER_USER_DATA_GS_15__DATA_MASK                                                                 0xFFFFFFFFL
16423 //SPI_SHADER_USER_DATA_GS_16
16424 #define SPI_SHADER_USER_DATA_GS_16__DATA__SHIFT                                                               0x0
16425 #define SPI_SHADER_USER_DATA_GS_16__DATA_MASK                                                                 0xFFFFFFFFL
16426 //SPI_SHADER_USER_DATA_GS_17
16427 #define SPI_SHADER_USER_DATA_GS_17__DATA__SHIFT                                                               0x0
16428 #define SPI_SHADER_USER_DATA_GS_17__DATA_MASK                                                                 0xFFFFFFFFL
16429 //SPI_SHADER_USER_DATA_GS_18
16430 #define SPI_SHADER_USER_DATA_GS_18__DATA__SHIFT                                                               0x0
16431 #define SPI_SHADER_USER_DATA_GS_18__DATA_MASK                                                                 0xFFFFFFFFL
16432 //SPI_SHADER_USER_DATA_GS_19
16433 #define SPI_SHADER_USER_DATA_GS_19__DATA__SHIFT                                                               0x0
16434 #define SPI_SHADER_USER_DATA_GS_19__DATA_MASK                                                                 0xFFFFFFFFL
16435 //SPI_SHADER_USER_DATA_GS_20
16436 #define SPI_SHADER_USER_DATA_GS_20__DATA__SHIFT                                                               0x0
16437 #define SPI_SHADER_USER_DATA_GS_20__DATA_MASK                                                                 0xFFFFFFFFL
16438 //SPI_SHADER_USER_DATA_GS_21
16439 #define SPI_SHADER_USER_DATA_GS_21__DATA__SHIFT                                                               0x0
16440 #define SPI_SHADER_USER_DATA_GS_21__DATA_MASK                                                                 0xFFFFFFFFL
16441 //SPI_SHADER_USER_DATA_GS_22
16442 #define SPI_SHADER_USER_DATA_GS_22__DATA__SHIFT                                                               0x0
16443 #define SPI_SHADER_USER_DATA_GS_22__DATA_MASK                                                                 0xFFFFFFFFL
16444 //SPI_SHADER_USER_DATA_GS_23
16445 #define SPI_SHADER_USER_DATA_GS_23__DATA__SHIFT                                                               0x0
16446 #define SPI_SHADER_USER_DATA_GS_23__DATA_MASK                                                                 0xFFFFFFFFL
16447 //SPI_SHADER_USER_DATA_GS_24
16448 #define SPI_SHADER_USER_DATA_GS_24__DATA__SHIFT                                                               0x0
16449 #define SPI_SHADER_USER_DATA_GS_24__DATA_MASK                                                                 0xFFFFFFFFL
16450 //SPI_SHADER_USER_DATA_GS_25
16451 #define SPI_SHADER_USER_DATA_GS_25__DATA__SHIFT                                                               0x0
16452 #define SPI_SHADER_USER_DATA_GS_25__DATA_MASK                                                                 0xFFFFFFFFL
16453 //SPI_SHADER_USER_DATA_GS_26
16454 #define SPI_SHADER_USER_DATA_GS_26__DATA__SHIFT                                                               0x0
16455 #define SPI_SHADER_USER_DATA_GS_26__DATA_MASK                                                                 0xFFFFFFFFL
16456 //SPI_SHADER_USER_DATA_GS_27
16457 #define SPI_SHADER_USER_DATA_GS_27__DATA__SHIFT                                                               0x0
16458 #define SPI_SHADER_USER_DATA_GS_27__DATA_MASK                                                                 0xFFFFFFFFL
16459 //SPI_SHADER_USER_DATA_GS_28
16460 #define SPI_SHADER_USER_DATA_GS_28__DATA__SHIFT                                                               0x0
16461 #define SPI_SHADER_USER_DATA_GS_28__DATA_MASK                                                                 0xFFFFFFFFL
16462 //SPI_SHADER_USER_DATA_GS_29
16463 #define SPI_SHADER_USER_DATA_GS_29__DATA__SHIFT                                                               0x0
16464 #define SPI_SHADER_USER_DATA_GS_29__DATA_MASK                                                                 0xFFFFFFFFL
16465 //SPI_SHADER_USER_DATA_GS_30
16466 #define SPI_SHADER_USER_DATA_GS_30__DATA__SHIFT                                                               0x0
16467 #define SPI_SHADER_USER_DATA_GS_30__DATA_MASK                                                                 0xFFFFFFFFL
16468 //SPI_SHADER_USER_DATA_GS_31
16469 #define SPI_SHADER_USER_DATA_GS_31__DATA__SHIFT                                                               0x0
16470 #define SPI_SHADER_USER_DATA_GS_31__DATA_MASK                                                                 0xFFFFFFFFL
16471 //SPI_SHADER_REQ_CTRL_ESGS
16472 #define SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_EN__SHIFT                                                     0x0
16473 #define SPI_SHADER_REQ_CTRL_ESGS__NUMBER_OF_REQUESTS_PER_CU__SHIFT                                            0x1
16474 #define SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT                                     0x5
16475 #define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_HYSTERESIS__SHIFT                                                 0x9
16476 #define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_LOW_THRESHOLD__SHIFT                                              0xa
16477 #define SPI_SHADER_REQ_CTRL_ESGS__PRODUCER_REQUEST_LOCKOUT__SHIFT                                             0xf
16478 #define SPI_SHADER_REQ_CTRL_ESGS__GLOBAL_SCANNING_EN__SHIFT                                                   0x10
16479 #define SPI_SHADER_REQ_CTRL_ESGS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT                                 0x11
16480 #define SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_EN_MASK                                                       0x00000001L
16481 #define SPI_SHADER_REQ_CTRL_ESGS__NUMBER_OF_REQUESTS_PER_CU_MASK                                              0x0000001EL
16482 #define SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK                                       0x000001E0L
16483 #define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_HYSTERESIS_MASK                                                   0x00000200L
16484 #define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_LOW_THRESHOLD_MASK                                                0x00007C00L
16485 #define SPI_SHADER_REQ_CTRL_ESGS__PRODUCER_REQUEST_LOCKOUT_MASK                                               0x00008000L
16486 #define SPI_SHADER_REQ_CTRL_ESGS__GLOBAL_SCANNING_EN_MASK                                                     0x00010000L
16487 #define SPI_SHADER_REQ_CTRL_ESGS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK                                   0x000E0000L
16488 //SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS
16489 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS__TOTAL_WAVE_COUNT_HIER_SELECT__SHIFT                               0x0
16490 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS__PER_TYPE_WAVE_COUNT_HIER_SELECT__SHIFT                            0x3
16491 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS__GROUP_UPDATE_EN__SHIFT                                            0x6
16492 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS__TOTAL_WAVE_COUNT_COEFFICIENT__SHIFT                               0x8
16493 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS__PER_TYPE_WAVE_COUNT_COEFFICIENT__SHIFT                            0x10
16494 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS__TOTAL_WAVE_COUNT_HIER_SELECT_MASK                                 0x00000007L
16495 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS__PER_TYPE_WAVE_COUNT_HIER_SELECT_MASK                              0x00000038L
16496 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS__GROUP_UPDATE_EN_MASK                                              0x00000040L
16497 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS__TOTAL_WAVE_COUNT_COEFFICIENT_MASK                                 0x0000FF00L
16498 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS__PER_TYPE_WAVE_COUNT_COEFFICIENT_MASK                              0x00FF0000L
16499 //SPI_SHADER_PREF_PRI_ACCUM_ESGS_0
16500 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_0__CONTRIBUTION__SHIFT                                                 0x0
16501 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_0__COEFFICIENT_HIER_SELECT__SHIFT                                      0x7
16502 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_0__CONTRIBUTION_HIER_SELECT__SHIFT                                     0xa
16503 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_0__GROUP_UPDATE_EN__SHIFT                                              0xd
16504 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_0__RESERVED__SHIFT                                                     0xe
16505 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_0__COEFFICIENT__SHIFT                                                  0xf
16506 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_0__CONTRIBUTION_MASK                                                   0x0000007FL
16507 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_0__COEFFICIENT_HIER_SELECT_MASK                                        0x00000380L
16508 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_0__CONTRIBUTION_HIER_SELECT_MASK                                       0x00001C00L
16509 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_0__GROUP_UPDATE_EN_MASK                                                0x00002000L
16510 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_0__RESERVED_MASK                                                       0x00004000L
16511 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_0__COEFFICIENT_MASK                                                    0x007F8000L
16512 //SPI_SHADER_USER_ACCUM_ESGS_0
16513 #define SPI_SHADER_USER_ACCUM_ESGS_0__CONTRIBUTION__SHIFT                                                     0x0
16514 #define SPI_SHADER_USER_ACCUM_ESGS_0__CONTRIBUTION_MASK                                                       0x0000007FL
16515 //SPI_SHADER_PREF_PRI_ACCUM_ESGS_1
16516 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_1__CONTRIBUTION__SHIFT                                                 0x0
16517 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_1__COEFFICIENT_HIER_SELECT__SHIFT                                      0x7
16518 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_1__CONTRIBUTION_HIER_SELECT__SHIFT                                     0xa
16519 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_1__GROUP_UPDATE_EN__SHIFT                                              0xd
16520 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_1__RESERVED__SHIFT                                                     0xe
16521 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_1__COEFFICIENT__SHIFT                                                  0xf
16522 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_1__CONTRIBUTION_MASK                                                   0x0000007FL
16523 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_1__COEFFICIENT_HIER_SELECT_MASK                                        0x00000380L
16524 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_1__CONTRIBUTION_HIER_SELECT_MASK                                       0x00001C00L
16525 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_1__GROUP_UPDATE_EN_MASK                                                0x00002000L
16526 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_1__RESERVED_MASK                                                       0x00004000L
16527 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_1__COEFFICIENT_MASK                                                    0x007F8000L
16528 //SPI_SHADER_USER_ACCUM_ESGS_1
16529 #define SPI_SHADER_USER_ACCUM_ESGS_1__CONTRIBUTION__SHIFT                                                     0x0
16530 #define SPI_SHADER_USER_ACCUM_ESGS_1__CONTRIBUTION_MASK                                                       0x0000007FL
16531 //SPI_SHADER_PREF_PRI_ACCUM_ESGS_2
16532 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_2__CONTRIBUTION__SHIFT                                                 0x0
16533 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_2__COEFFICIENT_HIER_SELECT__SHIFT                                      0x7
16534 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_2__CONTRIBUTION_HIER_SELECT__SHIFT                                     0xa
16535 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_2__GROUP_UPDATE_EN__SHIFT                                              0xd
16536 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_2__RESERVED__SHIFT                                                     0xe
16537 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_2__COEFFICIENT__SHIFT                                                  0xf
16538 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_2__CONTRIBUTION_MASK                                                   0x0000007FL
16539 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_2__COEFFICIENT_HIER_SELECT_MASK                                        0x00000380L
16540 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_2__CONTRIBUTION_HIER_SELECT_MASK                                       0x00001C00L
16541 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_2__GROUP_UPDATE_EN_MASK                                                0x00002000L
16542 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_2__RESERVED_MASK                                                       0x00004000L
16543 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_2__COEFFICIENT_MASK                                                    0x007F8000L
16544 //SPI_SHADER_USER_ACCUM_ESGS_2
16545 #define SPI_SHADER_USER_ACCUM_ESGS_2__CONTRIBUTION__SHIFT                                                     0x0
16546 #define SPI_SHADER_USER_ACCUM_ESGS_2__CONTRIBUTION_MASK                                                       0x0000007FL
16547 //SPI_SHADER_PREF_PRI_ACCUM_ESGS_3
16548 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_3__CONTRIBUTION__SHIFT                                                 0x0
16549 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_3__COEFFICIENT_HIER_SELECT__SHIFT                                      0x7
16550 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_3__CONTRIBUTION_HIER_SELECT__SHIFT                                     0xa
16551 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_3__GROUP_UPDATE_EN__SHIFT                                              0xd
16552 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_3__RESERVED__SHIFT                                                     0xe
16553 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_3__COEFFICIENT__SHIFT                                                  0xf
16554 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_3__CONTRIBUTION_MASK                                                   0x0000007FL
16555 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_3__COEFFICIENT_HIER_SELECT_MASK                                        0x00000380L
16556 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_3__CONTRIBUTION_HIER_SELECT_MASK                                       0x00001C00L
16557 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_3__GROUP_UPDATE_EN_MASK                                                0x00002000L
16558 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_3__RESERVED_MASK                                                       0x00004000L
16559 #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_3__COEFFICIENT_MASK                                                    0x007F8000L
16560 //SPI_SHADER_USER_ACCUM_ESGS_3
16561 #define SPI_SHADER_USER_ACCUM_ESGS_3__CONTRIBUTION__SHIFT                                                     0x0
16562 #define SPI_SHADER_USER_ACCUM_ESGS_3__CONTRIBUTION_MASK                                                       0x0000007FL
16563 //SPI_SHADER_PGM_RSRC2_ES_GS
16564 #define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN__SHIFT                                                         0x0
16565 #define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR__SHIFT                                                          0x1
16566 #define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT__SHIFT                                                       0x6
16567 #define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN__SHIFT                                                          0x7
16568 #define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN__SHIFT                                                            0x8
16569 #define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE__SHIFT                                                           0x14
16570 #define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN_MASK                                                           0x00000001L
16571 #define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR_MASK                                                            0x0000003EL
16572 #define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT_MASK                                                         0x00000040L
16573 #define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN_MASK                                                            0x00000080L
16574 #define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN_MASK                                                              0x0001FF00L
16575 #define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE_MASK                                                             0x1FF00000L
16576 //SPI_SHADER_PGM_RSRC3_ES
16577 #define SPI_SHADER_PGM_RSRC3_ES__CU_EN__SHIFT                                                                 0x0
16578 #define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT__SHIFT                                                            0x10
16579 #define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD__SHIFT                                                    0x16
16580 #define SPI_SHADER_PGM_RSRC3_ES__GROUP_FIFO_DEPTH__SHIFT                                                      0x1a
16581 #define SPI_SHADER_PGM_RSRC3_ES__CU_EN_MASK                                                                   0x0000FFFFL
16582 #define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT_MASK                                                              0x003F0000L
16583 #define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD_MASK                                                      0x03C00000L
16584 #define SPI_SHADER_PGM_RSRC3_ES__GROUP_FIFO_DEPTH_MASK                                                        0xFC000000L
16585 //SPI_SHADER_PGM_LO_ES
16586 #define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT                                                                 0x0
16587 #define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK                                                                   0xFFFFFFFFL
16588 //SPI_SHADER_PGM_HI_ES
16589 #define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT                                                                 0x0
16590 #define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK                                                                   0xFFL
16591 //SPI_SHADER_PGM_RSRC1_ES
16592 #define SPI_SHADER_PGM_RSRC1_ES__VGPRS__SHIFT                                                                 0x0
16593 #define SPI_SHADER_PGM_RSRC1_ES__SGPRS__SHIFT                                                                 0x6
16594 #define SPI_SHADER_PGM_RSRC1_ES__PRIORITY__SHIFT                                                              0xa
16595 #define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE__SHIFT                                                            0xc
16596 #define SPI_SHADER_PGM_RSRC1_ES__PRIV__SHIFT                                                                  0x14
16597 #define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP__SHIFT                                                            0x15
16598 #define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE__SHIFT                                                             0x17
16599 #define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT__SHIFT                                                         0x18
16600 #define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE__SHIFT                                                       0x1a
16601 #define SPI_SHADER_PGM_RSRC1_ES__FP16_OVFL__SHIFT                                                             0x1f
16602 #define SPI_SHADER_PGM_RSRC1_ES__VGPRS_MASK                                                                   0x0000003FL
16603 #define SPI_SHADER_PGM_RSRC1_ES__SGPRS_MASK                                                                   0x000003C0L
16604 #define SPI_SHADER_PGM_RSRC1_ES__PRIORITY_MASK                                                                0x00000C00L
16605 #define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE_MASK                                                              0x000FF000L
16606 #define SPI_SHADER_PGM_RSRC1_ES__PRIV_MASK                                                                    0x00100000L
16607 #define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP_MASK                                                              0x00200000L
16608 #define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE_MASK                                                               0x00800000L
16609 #define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT_MASK                                                           0x03000000L
16610 #define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE_MASK                                                         0x04000000L
16611 #define SPI_SHADER_PGM_RSRC1_ES__FP16_OVFL_MASK                                                               0x80000000L
16612 //SPI_SHADER_PGM_RSRC2_ES
16613 #define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN__SHIFT                                                            0x0
16614 #define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR__SHIFT                                                             0x1
16615 #define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT__SHIFT                                                          0x6
16616 #define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN__SHIFT                                                             0x7
16617 #define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN__SHIFT                                                               0x8
16618 #define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE__SHIFT                                                              0x14
16619 #define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN_MASK                                                              0x00000001L
16620 #define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR_MASK                                                               0x0000003EL
16621 #define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT_MASK                                                            0x00000040L
16622 #define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN_MASK                                                               0x00000080L
16623 #define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN_MASK                                                                 0x0001FF00L
16624 #define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE_MASK                                                                0x1FF00000L
16625 //SPI_SHADER_USER_DATA_ES_0
16626 #define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT                                                                0x0
16627 #define SPI_SHADER_USER_DATA_ES_0__DATA_MASK                                                                  0xFFFFFFFFL
16628 //SPI_SHADER_USER_DATA_ES_1
16629 #define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT                                                                0x0
16630 #define SPI_SHADER_USER_DATA_ES_1__DATA_MASK                                                                  0xFFFFFFFFL
16631 //SPI_SHADER_USER_DATA_ES_2
16632 #define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT                                                                0x0
16633 #define SPI_SHADER_USER_DATA_ES_2__DATA_MASK                                                                  0xFFFFFFFFL
16634 //SPI_SHADER_USER_DATA_ES_3
16635 #define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT                                                                0x0
16636 #define SPI_SHADER_USER_DATA_ES_3__DATA_MASK                                                                  0xFFFFFFFFL
16637 //SPI_SHADER_USER_DATA_ES_4
16638 #define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT                                                                0x0
16639 #define SPI_SHADER_USER_DATA_ES_4__DATA_MASK                                                                  0xFFFFFFFFL
16640 //SPI_SHADER_USER_DATA_ES_5
16641 #define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT                                                                0x0
16642 #define SPI_SHADER_USER_DATA_ES_5__DATA_MASK                                                                  0xFFFFFFFFL
16643 //SPI_SHADER_USER_DATA_ES_6
16644 #define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT                                                                0x0
16645 #define SPI_SHADER_USER_DATA_ES_6__DATA_MASK                                                                  0xFFFFFFFFL
16646 //SPI_SHADER_USER_DATA_ES_7
16647 #define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT                                                                0x0
16648 #define SPI_SHADER_USER_DATA_ES_7__DATA_MASK                                                                  0xFFFFFFFFL
16649 //SPI_SHADER_USER_DATA_ES_8
16650 #define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT                                                                0x0
16651 #define SPI_SHADER_USER_DATA_ES_8__DATA_MASK                                                                  0xFFFFFFFFL
16652 //SPI_SHADER_USER_DATA_ES_9
16653 #define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT                                                                0x0
16654 #define SPI_SHADER_USER_DATA_ES_9__DATA_MASK                                                                  0xFFFFFFFFL
16655 //SPI_SHADER_USER_DATA_ES_10
16656 #define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT                                                               0x0
16657 #define SPI_SHADER_USER_DATA_ES_10__DATA_MASK                                                                 0xFFFFFFFFL
16658 //SPI_SHADER_USER_DATA_ES_11
16659 #define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT                                                               0x0
16660 #define SPI_SHADER_USER_DATA_ES_11__DATA_MASK                                                                 0xFFFFFFFFL
16661 //SPI_SHADER_USER_DATA_ES_12
16662 #define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT                                                               0x0
16663 #define SPI_SHADER_USER_DATA_ES_12__DATA_MASK                                                                 0xFFFFFFFFL
16664 //SPI_SHADER_USER_DATA_ES_13
16665 #define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT                                                               0x0
16666 #define SPI_SHADER_USER_DATA_ES_13__DATA_MASK                                                                 0xFFFFFFFFL
16667 //SPI_SHADER_USER_DATA_ES_14
16668 #define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT                                                               0x0
16669 #define SPI_SHADER_USER_DATA_ES_14__DATA_MASK                                                                 0xFFFFFFFFL
16670 //SPI_SHADER_USER_DATA_ES_15
16671 #define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT                                                               0x0
16672 #define SPI_SHADER_USER_DATA_ES_15__DATA_MASK                                                                 0xFFFFFFFFL
16673 //SPI_SHADER_PGM_RSRC2_LS_ES
16674 #define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN__SHIFT                                                         0x0
16675 #define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR__SHIFT                                                          0x1
16676 #define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT__SHIFT                                                       0x6
16677 #define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE__SHIFT                                                           0x7
16678 #define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN__SHIFT                                                            0x10
16679 #define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN_MASK                                                           0x00000001L
16680 #define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR_MASK                                                            0x0000003EL
16681 #define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT_MASK                                                         0x00000040L
16682 #define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE_MASK                                                             0x0000FF80L
16683 #define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN_MASK                                                              0x01FF0000L
16684 //SPI_SHADER_PGM_CHKSUM_HS
16685 #define SPI_SHADER_PGM_CHKSUM_HS__CHECKSUM__SHIFT                                                             0x0
16686 #define SPI_SHADER_PGM_CHKSUM_HS__CHECKSUM_MASK                                                               0xFFFFFFFFL
16687 //SPI_SHADER_PGM_RSRC4_HS
16688 #define SPI_SHADER_PGM_RSRC4_HS__CU_EN__SHIFT                                                                 0x0
16689 #define SPI_SHADER_PGM_RSRC4_HS__CU_EN_MASK                                                                   0x0000FFFFL
16690 //SPI_SHADER_USER_DATA_ADDR_LO_HS
16691 #define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE__SHIFT                                                      0x0
16692 #define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE_MASK                                                        0xFFFFFFFFL
16693 //SPI_SHADER_USER_DATA_ADDR_HI_HS
16694 #define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE__SHIFT                                                      0x0
16695 #define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE_MASK                                                        0xFFFFFFFFL
16696 //SPI_SHADER_PGM_LO_LS_HS
16697 #define SPI_SHADER_PGM_LO_LS_HS__MEM_BASE__SHIFT                                                              0x0
16698 #define SPI_SHADER_PGM_LO_LS_HS__MEM_BASE_MASK                                                                0xFFFFFFFFL
16699 //SPI_SHADER_PGM_HI_LS_HS
16700 #define SPI_SHADER_PGM_HI_LS_HS__MEM_BASE__SHIFT                                                              0x0
16701 #define SPI_SHADER_PGM_HI_LS_HS__MEM_BASE_MASK                                                                0xFFL
16702 //SPI_SHADER_PGM_RSRC3_HS
16703 #define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT                                                            0x0
16704 #define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT                                                    0x6
16705 #define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH__SHIFT                                                      0xa
16706 #define SPI_SHADER_PGM_RSRC3_HS__CU_EN__SHIFT                                                                 0x10
16707 #define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK                                                              0x0000003FL
16708 #define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK                                                      0x000003C0L
16709 #define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH_MASK                                                        0x0000FC00L
16710 #define SPI_SHADER_PGM_RSRC3_HS__CU_EN_MASK                                                                   0xFFFF0000L
16711 //SPI_SHADER_PGM_LO_HS
16712 #define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT                                                                 0x0
16713 #define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK                                                                   0xFFFFFFFFL
16714 //SPI_SHADER_PGM_HI_HS
16715 #define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT                                                                 0x0
16716 #define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK                                                                   0xFFL
16717 //SPI_SHADER_PGM_RSRC1_HS
16718 #define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT                                                                 0x0
16719 #define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT                                                                 0x6
16720 #define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT                                                              0xa
16721 #define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT                                                            0xc
16722 #define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT                                                                  0x14
16723 #define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT                                                            0x15
16724 #define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT                                                             0x17
16725 #define SPI_SHADER_PGM_RSRC1_HS__MEM_ORDERED__SHIFT                                                           0x18
16726 #define SPI_SHADER_PGM_RSRC1_HS__FWD_PROGRESS__SHIFT                                                          0x19
16727 #define SPI_SHADER_PGM_RSRC1_HS__WGP_MODE__SHIFT                                                              0x1a
16728 #define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT__SHIFT                                                      0x1c
16729 #define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL__SHIFT                                                             0x1e
16730 #define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK                                                                   0x0000003FL
16731 #define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK                                                                   0x000003C0L
16732 #define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK                                                                0x00000C00L
16733 #define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK                                                              0x000FF000L
16734 #define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK                                                                    0x00100000L
16735 #define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK                                                              0x00200000L
16736 #define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK                                                               0x00800000L
16737 #define SPI_SHADER_PGM_RSRC1_HS__MEM_ORDERED_MASK                                                             0x01000000L
16738 #define SPI_SHADER_PGM_RSRC1_HS__FWD_PROGRESS_MASK                                                            0x02000000L
16739 #define SPI_SHADER_PGM_RSRC1_HS__WGP_MODE_MASK                                                                0x04000000L
16740 #define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT_MASK                                                        0x30000000L
16741 #define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL_MASK                                                               0x40000000L
16742 //SPI_SHADER_PGM_RSRC2_HS
16743 #define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT                                                            0x0
16744 #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT                                                             0x1
16745 #define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT                                                          0x6
16746 #define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN__SHIFT                                                             0x7
16747 #define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN__SHIFT                                                            0x8
16748 #define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT                                                               0x9
16749 #define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE__SHIFT                                                              0x12
16750 #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB__SHIFT                                                         0x1b
16751 #define SPI_SHADER_PGM_RSRC2_HS__SHARED_VGPR_CNT__SHIFT                                                       0x1c
16752 #define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK                                                              0x00000001L
16753 #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK                                                               0x0000003EL
16754 #define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK                                                            0x00000040L
16755 #define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN_MASK                                                               0x00000080L
16756 #define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN_MASK                                                              0x00000100L
16757 #define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK                                                                 0x0003FE00L
16758 #define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE_MASK                                                                0x07FC0000L
16759 #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB_MASK                                                           0x08000000L
16760 #define SPI_SHADER_PGM_RSRC2_HS__SHARED_VGPR_CNT_MASK                                                         0xF0000000L
16761 //SPI_SHADER_USER_DATA_HS_0
16762 #define SPI_SHADER_USER_DATA_HS_0__DATA__SHIFT                                                                0x0
16763 #define SPI_SHADER_USER_DATA_HS_0__DATA_MASK                                                                  0xFFFFFFFFL
16764 //SPI_SHADER_USER_DATA_HS_1
16765 #define SPI_SHADER_USER_DATA_HS_1__DATA__SHIFT                                                                0x0
16766 #define SPI_SHADER_USER_DATA_HS_1__DATA_MASK                                                                  0xFFFFFFFFL
16767 //SPI_SHADER_USER_DATA_HS_2
16768 #define SPI_SHADER_USER_DATA_HS_2__DATA__SHIFT                                                                0x0
16769 #define SPI_SHADER_USER_DATA_HS_2__DATA_MASK                                                                  0xFFFFFFFFL
16770 //SPI_SHADER_USER_DATA_HS_3
16771 #define SPI_SHADER_USER_DATA_HS_3__DATA__SHIFT                                                                0x0
16772 #define SPI_SHADER_USER_DATA_HS_3__DATA_MASK                                                                  0xFFFFFFFFL
16773 //SPI_SHADER_USER_DATA_HS_4
16774 #define SPI_SHADER_USER_DATA_HS_4__DATA__SHIFT                                                                0x0
16775 #define SPI_SHADER_USER_DATA_HS_4__DATA_MASK                                                                  0xFFFFFFFFL
16776 //SPI_SHADER_USER_DATA_HS_5
16777 #define SPI_SHADER_USER_DATA_HS_5__DATA__SHIFT                                                                0x0
16778 #define SPI_SHADER_USER_DATA_HS_5__DATA_MASK                                                                  0xFFFFFFFFL
16779 //SPI_SHADER_USER_DATA_HS_6
16780 #define SPI_SHADER_USER_DATA_HS_6__DATA__SHIFT                                                                0x0
16781 #define SPI_SHADER_USER_DATA_HS_6__DATA_MASK                                                                  0xFFFFFFFFL
16782 //SPI_SHADER_USER_DATA_HS_7
16783 #define SPI_SHADER_USER_DATA_HS_7__DATA__SHIFT                                                                0x0
16784 #define SPI_SHADER_USER_DATA_HS_7__DATA_MASK                                                                  0xFFFFFFFFL
16785 //SPI_SHADER_USER_DATA_HS_8
16786 #define SPI_SHADER_USER_DATA_HS_8__DATA__SHIFT                                                                0x0
16787 #define SPI_SHADER_USER_DATA_HS_8__DATA_MASK                                                                  0xFFFFFFFFL
16788 //SPI_SHADER_USER_DATA_HS_9
16789 #define SPI_SHADER_USER_DATA_HS_9__DATA__SHIFT                                                                0x0
16790 #define SPI_SHADER_USER_DATA_HS_9__DATA_MASK                                                                  0xFFFFFFFFL
16791 //SPI_SHADER_USER_DATA_HS_10
16792 #define SPI_SHADER_USER_DATA_HS_10__DATA__SHIFT                                                               0x0
16793 #define SPI_SHADER_USER_DATA_HS_10__DATA_MASK                                                                 0xFFFFFFFFL
16794 //SPI_SHADER_USER_DATA_HS_11
16795 #define SPI_SHADER_USER_DATA_HS_11__DATA__SHIFT                                                               0x0
16796 #define SPI_SHADER_USER_DATA_HS_11__DATA_MASK                                                                 0xFFFFFFFFL
16797 //SPI_SHADER_USER_DATA_HS_12
16798 #define SPI_SHADER_USER_DATA_HS_12__DATA__SHIFT                                                               0x0
16799 #define SPI_SHADER_USER_DATA_HS_12__DATA_MASK                                                                 0xFFFFFFFFL
16800 //SPI_SHADER_USER_DATA_HS_13
16801 #define SPI_SHADER_USER_DATA_HS_13__DATA__SHIFT                                                               0x0
16802 #define SPI_SHADER_USER_DATA_HS_13__DATA_MASK                                                                 0xFFFFFFFFL
16803 //SPI_SHADER_USER_DATA_HS_14
16804 #define SPI_SHADER_USER_DATA_HS_14__DATA__SHIFT                                                               0x0
16805 #define SPI_SHADER_USER_DATA_HS_14__DATA_MASK                                                                 0xFFFFFFFFL
16806 //SPI_SHADER_USER_DATA_HS_15
16807 #define SPI_SHADER_USER_DATA_HS_15__DATA__SHIFT                                                               0x0
16808 #define SPI_SHADER_USER_DATA_HS_15__DATA_MASK                                                                 0xFFFFFFFFL
16809 //SPI_SHADER_USER_DATA_HS_16
16810 #define SPI_SHADER_USER_DATA_HS_16__DATA__SHIFT                                                               0x0
16811 #define SPI_SHADER_USER_DATA_HS_16__DATA_MASK                                                                 0xFFFFFFFFL
16812 //SPI_SHADER_USER_DATA_HS_17
16813 #define SPI_SHADER_USER_DATA_HS_17__DATA__SHIFT                                                               0x0
16814 #define SPI_SHADER_USER_DATA_HS_17__DATA_MASK                                                                 0xFFFFFFFFL
16815 //SPI_SHADER_USER_DATA_HS_18
16816 #define SPI_SHADER_USER_DATA_HS_18__DATA__SHIFT                                                               0x0
16817 #define SPI_SHADER_USER_DATA_HS_18__DATA_MASK                                                                 0xFFFFFFFFL
16818 //SPI_SHADER_USER_DATA_HS_19
16819 #define SPI_SHADER_USER_DATA_HS_19__DATA__SHIFT                                                               0x0
16820 #define SPI_SHADER_USER_DATA_HS_19__DATA_MASK                                                                 0xFFFFFFFFL
16821 //SPI_SHADER_USER_DATA_HS_20
16822 #define SPI_SHADER_USER_DATA_HS_20__DATA__SHIFT                                                               0x0
16823 #define SPI_SHADER_USER_DATA_HS_20__DATA_MASK                                                                 0xFFFFFFFFL
16824 //SPI_SHADER_USER_DATA_HS_21
16825 #define SPI_SHADER_USER_DATA_HS_21__DATA__SHIFT                                                               0x0
16826 #define SPI_SHADER_USER_DATA_HS_21__DATA_MASK                                                                 0xFFFFFFFFL
16827 //SPI_SHADER_USER_DATA_HS_22
16828 #define SPI_SHADER_USER_DATA_HS_22__DATA__SHIFT                                                               0x0
16829 #define SPI_SHADER_USER_DATA_HS_22__DATA_MASK                                                                 0xFFFFFFFFL
16830 //SPI_SHADER_USER_DATA_HS_23
16831 #define SPI_SHADER_USER_DATA_HS_23__DATA__SHIFT                                                               0x0
16832 #define SPI_SHADER_USER_DATA_HS_23__DATA_MASK                                                                 0xFFFFFFFFL
16833 //SPI_SHADER_USER_DATA_HS_24
16834 #define SPI_SHADER_USER_DATA_HS_24__DATA__SHIFT                                                               0x0
16835 #define SPI_SHADER_USER_DATA_HS_24__DATA_MASK                                                                 0xFFFFFFFFL
16836 //SPI_SHADER_USER_DATA_HS_25
16837 #define SPI_SHADER_USER_DATA_HS_25__DATA__SHIFT                                                               0x0
16838 #define SPI_SHADER_USER_DATA_HS_25__DATA_MASK                                                                 0xFFFFFFFFL
16839 //SPI_SHADER_USER_DATA_HS_26
16840 #define SPI_SHADER_USER_DATA_HS_26__DATA__SHIFT                                                               0x0
16841 #define SPI_SHADER_USER_DATA_HS_26__DATA_MASK                                                                 0xFFFFFFFFL
16842 //SPI_SHADER_USER_DATA_HS_27
16843 #define SPI_SHADER_USER_DATA_HS_27__DATA__SHIFT                                                               0x0
16844 #define SPI_SHADER_USER_DATA_HS_27__DATA_MASK                                                                 0xFFFFFFFFL
16845 //SPI_SHADER_USER_DATA_HS_28
16846 #define SPI_SHADER_USER_DATA_HS_28__DATA__SHIFT                                                               0x0
16847 #define SPI_SHADER_USER_DATA_HS_28__DATA_MASK                                                                 0xFFFFFFFFL
16848 //SPI_SHADER_USER_DATA_HS_29
16849 #define SPI_SHADER_USER_DATA_HS_29__DATA__SHIFT                                                               0x0
16850 #define SPI_SHADER_USER_DATA_HS_29__DATA_MASK                                                                 0xFFFFFFFFL
16851 //SPI_SHADER_USER_DATA_HS_30
16852 #define SPI_SHADER_USER_DATA_HS_30__DATA__SHIFT                                                               0x0
16853 #define SPI_SHADER_USER_DATA_HS_30__DATA_MASK                                                                 0xFFFFFFFFL
16854 //SPI_SHADER_USER_DATA_HS_31
16855 #define SPI_SHADER_USER_DATA_HS_31__DATA__SHIFT                                                               0x0
16856 #define SPI_SHADER_USER_DATA_HS_31__DATA_MASK                                                                 0xFFFFFFFFL
16857 //SPI_SHADER_REQ_CTRL_LSHS
16858 #define SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_EN__SHIFT                                                     0x0
16859 #define SPI_SHADER_REQ_CTRL_LSHS__NUMBER_OF_REQUESTS_PER_CU__SHIFT                                            0x1
16860 #define SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT                                     0x5
16861 #define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_HYSTERESIS__SHIFT                                                 0x9
16862 #define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_LOW_THRESHOLD__SHIFT                                              0xa
16863 #define SPI_SHADER_REQ_CTRL_LSHS__PRODUCER_REQUEST_LOCKOUT__SHIFT                                             0xf
16864 #define SPI_SHADER_REQ_CTRL_LSHS__GLOBAL_SCANNING_EN__SHIFT                                                   0x10
16865 #define SPI_SHADER_REQ_CTRL_LSHS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT                                 0x11
16866 #define SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_EN_MASK                                                       0x00000001L
16867 #define SPI_SHADER_REQ_CTRL_LSHS__NUMBER_OF_REQUESTS_PER_CU_MASK                                              0x0000001EL
16868 #define SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK                                       0x000001E0L
16869 #define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_HYSTERESIS_MASK                                                   0x00000200L
16870 #define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_LOW_THRESHOLD_MASK                                                0x00007C00L
16871 #define SPI_SHADER_REQ_CTRL_LSHS__PRODUCER_REQUEST_LOCKOUT_MASK                                               0x00008000L
16872 #define SPI_SHADER_REQ_CTRL_LSHS__GLOBAL_SCANNING_EN_MASK                                                     0x00010000L
16873 #define SPI_SHADER_REQ_CTRL_LSHS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK                                   0x000E0000L
16874 //SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS
16875 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS__TOTAL_WAVE_COUNT_HIER_SELECT__SHIFT                               0x0
16876 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS__PER_TYPE_WAVE_COUNT_HIER_SELECT__SHIFT                            0x3
16877 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS__GROUP_UPDATE_EN__SHIFT                                            0x6
16878 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS__TOTAL_WAVE_COUNT_COEFFICIENT__SHIFT                               0x8
16879 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS__PER_TYPE_WAVE_COUNT_COEFFICIENT__SHIFT                            0x10
16880 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS__TOTAL_WAVE_COUNT_HIER_SELECT_MASK                                 0x00000007L
16881 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS__PER_TYPE_WAVE_COUNT_HIER_SELECT_MASK                              0x00000038L
16882 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS__GROUP_UPDATE_EN_MASK                                              0x00000040L
16883 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS__TOTAL_WAVE_COUNT_COEFFICIENT_MASK                                 0x0000FF00L
16884 #define SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS__PER_TYPE_WAVE_COUNT_COEFFICIENT_MASK                              0x00FF0000L
16885 //SPI_SHADER_PREF_PRI_ACCUM_LSHS_0
16886 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_0__CONTRIBUTION__SHIFT                                                 0x0
16887 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_0__COEFFICIENT_HIER_SELECT__SHIFT                                      0x7
16888 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_0__CONTRIBUTION_HIER_SELECT__SHIFT                                     0xa
16889 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_0__GROUP_UPDATE_EN__SHIFT                                              0xd
16890 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_0__RESERVED__SHIFT                                                     0xe
16891 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_0__COEFFICIENT__SHIFT                                                  0xf
16892 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_0__CONTRIBUTION_MASK                                                   0x0000007FL
16893 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_0__COEFFICIENT_HIER_SELECT_MASK                                        0x00000380L
16894 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_0__CONTRIBUTION_HIER_SELECT_MASK                                       0x00001C00L
16895 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_0__GROUP_UPDATE_EN_MASK                                                0x00002000L
16896 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_0__RESERVED_MASK                                                       0x00004000L
16897 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_0__COEFFICIENT_MASK                                                    0x007F8000L
16898 //SPI_SHADER_USER_ACCUM_LSHS_0
16899 #define SPI_SHADER_USER_ACCUM_LSHS_0__CONTRIBUTION__SHIFT                                                     0x0
16900 #define SPI_SHADER_USER_ACCUM_LSHS_0__CONTRIBUTION_MASK                                                       0x0000007FL
16901 //SPI_SHADER_PREF_PRI_ACCUM_LSHS_1
16902 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_1__CONTRIBUTION__SHIFT                                                 0x0
16903 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_1__COEFFICIENT_HIER_SELECT__SHIFT                                      0x7
16904 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_1__CONTRIBUTION_HIER_SELECT__SHIFT                                     0xa
16905 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_1__GROUP_UPDATE_EN__SHIFT                                              0xd
16906 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_1__RESERVED__SHIFT                                                     0xe
16907 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_1__COEFFICIENT__SHIFT                                                  0xf
16908 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_1__CONTRIBUTION_MASK                                                   0x0000007FL
16909 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_1__COEFFICIENT_HIER_SELECT_MASK                                        0x00000380L
16910 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_1__CONTRIBUTION_HIER_SELECT_MASK                                       0x00001C00L
16911 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_1__GROUP_UPDATE_EN_MASK                                                0x00002000L
16912 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_1__RESERVED_MASK                                                       0x00004000L
16913 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_1__COEFFICIENT_MASK                                                    0x007F8000L
16914 //SPI_SHADER_USER_ACCUM_LSHS_1
16915 #define SPI_SHADER_USER_ACCUM_LSHS_1__CONTRIBUTION__SHIFT                                                     0x0
16916 #define SPI_SHADER_USER_ACCUM_LSHS_1__CONTRIBUTION_MASK                                                       0x0000007FL
16917 //SPI_SHADER_PREF_PRI_ACCUM_LSHS_2
16918 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_2__CONTRIBUTION__SHIFT                                                 0x0
16919 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_2__COEFFICIENT_HIER_SELECT__SHIFT                                      0x7
16920 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_2__CONTRIBUTION_HIER_SELECT__SHIFT                                     0xa
16921 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_2__GROUP_UPDATE_EN__SHIFT                                              0xd
16922 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_2__RESERVED__SHIFT                                                     0xe
16923 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_2__COEFFICIENT__SHIFT                                                  0xf
16924 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_2__CONTRIBUTION_MASK                                                   0x0000007FL
16925 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_2__COEFFICIENT_HIER_SELECT_MASK                                        0x00000380L
16926 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_2__CONTRIBUTION_HIER_SELECT_MASK                                       0x00001C00L
16927 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_2__GROUP_UPDATE_EN_MASK                                                0x00002000L
16928 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_2__RESERVED_MASK                                                       0x00004000L
16929 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_2__COEFFICIENT_MASK                                                    0x007F8000L
16930 //SPI_SHADER_USER_ACCUM_LSHS_2
16931 #define SPI_SHADER_USER_ACCUM_LSHS_2__CONTRIBUTION__SHIFT                                                     0x0
16932 #define SPI_SHADER_USER_ACCUM_LSHS_2__CONTRIBUTION_MASK                                                       0x0000007FL
16933 //SPI_SHADER_PREF_PRI_ACCUM_LSHS_3
16934 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_3__CONTRIBUTION__SHIFT                                                 0x0
16935 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_3__COEFFICIENT_HIER_SELECT__SHIFT                                      0x7
16936 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_3__CONTRIBUTION_HIER_SELECT__SHIFT                                     0xa
16937 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_3__GROUP_UPDATE_EN__SHIFT                                              0xd
16938 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_3__RESERVED__SHIFT                                                     0xe
16939 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_3__COEFFICIENT__SHIFT                                                  0xf
16940 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_3__CONTRIBUTION_MASK                                                   0x0000007FL
16941 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_3__COEFFICIENT_HIER_SELECT_MASK                                        0x00000380L
16942 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_3__CONTRIBUTION_HIER_SELECT_MASK                                       0x00001C00L
16943 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_3__GROUP_UPDATE_EN_MASK                                                0x00002000L
16944 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_3__RESERVED_MASK                                                       0x00004000L
16945 #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_3__COEFFICIENT_MASK                                                    0x007F8000L
16946 //SPI_SHADER_USER_ACCUM_LSHS_3
16947 #define SPI_SHADER_USER_ACCUM_LSHS_3__CONTRIBUTION__SHIFT                                                     0x0
16948 #define SPI_SHADER_USER_ACCUM_LSHS_3__CONTRIBUTION_MASK                                                       0x0000007FL
16949 //SPI_SHADER_PGM_RSRC2_LS_HS
16950 #define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN__SHIFT                                                         0x0
16951 #define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR__SHIFT                                                          0x1
16952 #define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT__SHIFT                                                       0x6
16953 #define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE__SHIFT                                                           0x7
16954 #define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN__SHIFT                                                            0x10
16955 #define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN_MASK                                                           0x00000001L
16956 #define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR_MASK                                                            0x0000003EL
16957 #define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT_MASK                                                         0x00000040L
16958 #define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE_MASK                                                             0x0000FF80L
16959 #define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN_MASK                                                              0x01FF0000L
16960 //SPI_SHADER_PGM_RSRC3_LS
16961 #define SPI_SHADER_PGM_RSRC3_LS__CU_EN__SHIFT                                                                 0x0
16962 #define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT__SHIFT                                                            0x10
16963 #define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD__SHIFT                                                    0x16
16964 #define SPI_SHADER_PGM_RSRC3_LS__GROUP_FIFO_DEPTH__SHIFT                                                      0x1a
16965 #define SPI_SHADER_PGM_RSRC3_LS__CU_EN_MASK                                                                   0x0000FFFFL
16966 #define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT_MASK                                                              0x003F0000L
16967 #define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD_MASK                                                      0x03C00000L
16968 #define SPI_SHADER_PGM_RSRC3_LS__GROUP_FIFO_DEPTH_MASK                                                        0xFC000000L
16969 //SPI_SHADER_PGM_LO_LS
16970 #define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT                                                                 0x0
16971 #define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK                                                                   0xFFFFFFFFL
16972 //SPI_SHADER_PGM_HI_LS
16973 #define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT                                                                 0x0
16974 #define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK                                                                   0xFFL
16975 //SPI_SHADER_PGM_RSRC1_LS
16976 #define SPI_SHADER_PGM_RSRC1_LS__VGPRS__SHIFT                                                                 0x0
16977 #define SPI_SHADER_PGM_RSRC1_LS__SGPRS__SHIFT                                                                 0x6
16978 #define SPI_SHADER_PGM_RSRC1_LS__PRIORITY__SHIFT                                                              0xa
16979 #define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE__SHIFT                                                            0xc
16980 #define SPI_SHADER_PGM_RSRC1_LS__PRIV__SHIFT                                                                  0x14
16981 #define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP__SHIFT                                                            0x15
16982 #define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE__SHIFT                                                             0x17
16983 #define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT__SHIFT                                                         0x18
16984 #define SPI_SHADER_PGM_RSRC1_LS__FP16_OVFL__SHIFT                                                             0x1e
16985 #define SPI_SHADER_PGM_RSRC1_LS__VGPRS_MASK                                                                   0x0000003FL
16986 #define SPI_SHADER_PGM_RSRC1_LS__SGPRS_MASK                                                                   0x000003C0L
16987 #define SPI_SHADER_PGM_RSRC1_LS__PRIORITY_MASK                                                                0x00000C00L
16988 #define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE_MASK                                                              0x000FF000L
16989 #define SPI_SHADER_PGM_RSRC1_LS__PRIV_MASK                                                                    0x00100000L
16990 #define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP_MASK                                                              0x00200000L
16991 #define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE_MASK                                                               0x00800000L
16992 #define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT_MASK                                                           0x03000000L
16993 #define SPI_SHADER_PGM_RSRC1_LS__FP16_OVFL_MASK                                                               0x40000000L
16994 //SPI_SHADER_PGM_RSRC2_LS
16995 #define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN__SHIFT                                                            0x0
16996 #define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR__SHIFT                                                             0x1
16997 #define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT__SHIFT                                                          0x6
16998 #define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE__SHIFT                                                              0x7
16999 #define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN__SHIFT                                                               0x10
17000 #define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN_MASK                                                              0x00000001L
17001 #define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR_MASK                                                               0x0000003EL
17002 #define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT_MASK                                                            0x00000040L
17003 #define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE_MASK                                                                0x0000FF80L
17004 #define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN_MASK                                                                 0x01FF0000L
17005 //SPI_SHADER_USER_DATA_LS_0
17006 #define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT                                                                0x0
17007 #define SPI_SHADER_USER_DATA_LS_0__DATA_MASK                                                                  0xFFFFFFFFL
17008 //SPI_SHADER_USER_DATA_LS_1
17009 #define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT                                                                0x0
17010 #define SPI_SHADER_USER_DATA_LS_1__DATA_MASK                                                                  0xFFFFFFFFL
17011 //SPI_SHADER_USER_DATA_LS_2
17012 #define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT                                                                0x0
17013 #define SPI_SHADER_USER_DATA_LS_2__DATA_MASK                                                                  0xFFFFFFFFL
17014 //SPI_SHADER_USER_DATA_LS_3
17015 #define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT                                                                0x0
17016 #define SPI_SHADER_USER_DATA_LS_3__DATA_MASK                                                                  0xFFFFFFFFL
17017 //SPI_SHADER_USER_DATA_LS_4
17018 #define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT                                                                0x0
17019 #define SPI_SHADER_USER_DATA_LS_4__DATA_MASK                                                                  0xFFFFFFFFL
17020 //SPI_SHADER_USER_DATA_LS_5
17021 #define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT                                                                0x0
17022 #define SPI_SHADER_USER_DATA_LS_5__DATA_MASK                                                                  0xFFFFFFFFL
17023 //SPI_SHADER_USER_DATA_LS_6
17024 #define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT                                                                0x0
17025 #define SPI_SHADER_USER_DATA_LS_6__DATA_MASK                                                                  0xFFFFFFFFL
17026 //SPI_SHADER_USER_DATA_LS_7
17027 #define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT                                                                0x0
17028 #define SPI_SHADER_USER_DATA_LS_7__DATA_MASK                                                                  0xFFFFFFFFL
17029 //SPI_SHADER_USER_DATA_LS_8
17030 #define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT                                                                0x0
17031 #define SPI_SHADER_USER_DATA_LS_8__DATA_MASK                                                                  0xFFFFFFFFL
17032 //SPI_SHADER_USER_DATA_LS_9
17033 #define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT                                                                0x0
17034 #define SPI_SHADER_USER_DATA_LS_9__DATA_MASK                                                                  0xFFFFFFFFL
17035 //SPI_SHADER_USER_DATA_LS_10
17036 #define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT                                                               0x0
17037 #define SPI_SHADER_USER_DATA_LS_10__DATA_MASK                                                                 0xFFFFFFFFL
17038 //SPI_SHADER_USER_DATA_LS_11
17039 #define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT                                                               0x0
17040 #define SPI_SHADER_USER_DATA_LS_11__DATA_MASK                                                                 0xFFFFFFFFL
17041 //SPI_SHADER_USER_DATA_LS_12
17042 #define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT                                                               0x0
17043 #define SPI_SHADER_USER_DATA_LS_12__DATA_MASK                                                                 0xFFFFFFFFL
17044 //SPI_SHADER_USER_DATA_LS_13
17045 #define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT                                                               0x0
17046 #define SPI_SHADER_USER_DATA_LS_13__DATA_MASK                                                                 0xFFFFFFFFL
17047 //SPI_SHADER_USER_DATA_LS_14
17048 #define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT                                                               0x0
17049 #define SPI_SHADER_USER_DATA_LS_14__DATA_MASK                                                                 0xFFFFFFFFL
17050 //SPI_SHADER_USER_DATA_LS_15
17051 #define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT                                                               0x0
17052 #define SPI_SHADER_USER_DATA_LS_15__DATA_MASK                                                                 0xFFFFFFFFL
17053 //COMPUTE_DISPATCH_INITIATOR
17054 #define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT                                                  0x0
17055 #define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT                                                      0x1
17056 #define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT                                                 0x2
17057 #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT                                                0x3
17058 #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT                                                0x4
17059 #define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT                                              0x5
17060 #define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT                                                         0x6
17061 #define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT                                                  0xa
17062 #define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT                                                  0xb
17063 #define COMPUTE_DISPATCH_INITIATOR__RESERVED__SHIFT                                                           0xc
17064 #define COMPUTE_DISPATCH_INITIATOR__TUNNEL_ENABLE__SHIFT                                                      0xd
17065 #define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT                                                            0xe
17066 #define COMPUTE_DISPATCH_INITIATOR__CS_W32_EN__SHIFT                                                          0xf
17067 #define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK                                                    0x00000001L
17068 #define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK                                                        0x00000002L
17069 #define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK                                                   0x00000004L
17070 #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK                                                  0x00000008L
17071 #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK                                                  0x00000010L
17072 #define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK                                                0x00000020L
17073 #define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK                                                           0x00000040L
17074 #define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK                                                    0x00000400L
17075 #define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK                                                    0x00000800L
17076 #define COMPUTE_DISPATCH_INITIATOR__RESERVED_MASK                                                             0x00001000L
17077 #define COMPUTE_DISPATCH_INITIATOR__TUNNEL_ENABLE_MASK                                                        0x00002000L
17078 #define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK                                                              0x00004000L
17079 #define COMPUTE_DISPATCH_INITIATOR__CS_W32_EN_MASK                                                            0x00008000L
17080 //COMPUTE_DIM_X
17081 #define COMPUTE_DIM_X__SIZE__SHIFT                                                                            0x0
17082 #define COMPUTE_DIM_X__SIZE_MASK                                                                              0xFFFFFFFFL
17083 //COMPUTE_DIM_Y
17084 #define COMPUTE_DIM_Y__SIZE__SHIFT                                                                            0x0
17085 #define COMPUTE_DIM_Y__SIZE_MASK                                                                              0xFFFFFFFFL
17086 //COMPUTE_DIM_Z
17087 #define COMPUTE_DIM_Z__SIZE__SHIFT                                                                            0x0
17088 #define COMPUTE_DIM_Z__SIZE_MASK                                                                              0xFFFFFFFFL
17089 //COMPUTE_START_X
17090 #define COMPUTE_START_X__START__SHIFT                                                                         0x0
17091 #define COMPUTE_START_X__START_MASK                                                                           0xFFFFFFFFL
17092 //COMPUTE_START_Y
17093 #define COMPUTE_START_Y__START__SHIFT                                                                         0x0
17094 #define COMPUTE_START_Y__START_MASK                                                                           0xFFFFFFFFL
17095 //COMPUTE_START_Z
17096 #define COMPUTE_START_Z__START__SHIFT                                                                         0x0
17097 #define COMPUTE_START_Z__START_MASK                                                                           0xFFFFFFFFL
17098 //COMPUTE_NUM_THREAD_X
17099 #define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT                                                          0x0
17100 #define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT                                                       0x10
17101 #define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK                                                            0x0000FFFFL
17102 #define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK                                                         0xFFFF0000L
17103 //COMPUTE_NUM_THREAD_Y
17104 #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT                                                          0x0
17105 #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT                                                       0x10
17106 #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK                                                            0x0000FFFFL
17107 #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK                                                         0xFFFF0000L
17108 //COMPUTE_NUM_THREAD_Z
17109 #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT                                                          0x0
17110 #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT                                                       0x10
17111 #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK                                                            0x0000FFFFL
17112 #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK                                                         0xFFFF0000L
17113 //COMPUTE_PIPELINESTAT_ENABLE
17114 #define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT                                               0x0
17115 #define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK                                                 0x00000001L
17116 //COMPUTE_PERFCOUNT_ENABLE
17117 #define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT                                                     0x0
17118 #define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK                                                       0x00000001L
17119 //COMPUTE_PGM_LO
17120 #define COMPUTE_PGM_LO__DATA__SHIFT                                                                           0x0
17121 #define COMPUTE_PGM_LO__DATA_MASK                                                                             0xFFFFFFFFL
17122 //COMPUTE_PGM_HI
17123 #define COMPUTE_PGM_HI__DATA__SHIFT                                                                           0x0
17124 #define COMPUTE_PGM_HI__DATA_MASK                                                                             0x000000FFL
17125 //COMPUTE_DISPATCH_PKT_ADDR_LO
17126 #define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA__SHIFT                                                             0x0
17127 #define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA_MASK                                                               0xFFFFFFFFL
17128 //COMPUTE_DISPATCH_PKT_ADDR_HI
17129 #define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA__SHIFT                                                             0x0
17130 #define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA_MASK                                                               0x000000FFL
17131 //COMPUTE_DISPATCH_SCRATCH_BASE_LO
17132 #define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA__SHIFT                                                         0x0
17133 #define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA_MASK                                                           0xFFFFFFFFL
17134 //COMPUTE_DISPATCH_SCRATCH_BASE_HI
17135 #define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA__SHIFT                                                         0x0
17136 #define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA_MASK                                                           0x000000FFL
17137 //COMPUTE_PGM_RSRC1
17138 #define COMPUTE_PGM_RSRC1__VGPRS__SHIFT                                                                       0x0
17139 #define COMPUTE_PGM_RSRC1__SGPRS__SHIFT                                                                       0x6
17140 #define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT                                                                    0xa
17141 #define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT                                                                  0xc
17142 #define COMPUTE_PGM_RSRC1__PRIV__SHIFT                                                                        0x14
17143 #define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT                                                                  0x15
17144 #define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT                                                                   0x17
17145 #define COMPUTE_PGM_RSRC1__BULKY__SHIFT                                                                       0x18
17146 #define COMPUTE_PGM_RSRC1__FP16_OVFL__SHIFT                                                                   0x1a
17147 #define COMPUTE_PGM_RSRC1__WGP_MODE__SHIFT                                                                    0x1d
17148 #define COMPUTE_PGM_RSRC1__MEM_ORDERED__SHIFT                                                                 0x1e
17149 #define COMPUTE_PGM_RSRC1__FWD_PROGRESS__SHIFT                                                                0x1f
17150 #define COMPUTE_PGM_RSRC1__VGPRS_MASK                                                                         0x0000003FL
17151 #define COMPUTE_PGM_RSRC1__SGPRS_MASK                                                                         0x000003C0L
17152 #define COMPUTE_PGM_RSRC1__PRIORITY_MASK                                                                      0x00000C00L
17153 #define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK                                                                    0x000FF000L
17154 #define COMPUTE_PGM_RSRC1__PRIV_MASK                                                                          0x00100000L
17155 #define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK                                                                    0x00200000L
17156 #define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK                                                                     0x00800000L
17157 #define COMPUTE_PGM_RSRC1__BULKY_MASK                                                                         0x01000000L
17158 #define COMPUTE_PGM_RSRC1__FP16_OVFL_MASK                                                                     0x04000000L
17159 #define COMPUTE_PGM_RSRC1__WGP_MODE_MASK                                                                      0x20000000L
17160 #define COMPUTE_PGM_RSRC1__MEM_ORDERED_MASK                                                                   0x40000000L
17161 #define COMPUTE_PGM_RSRC1__FWD_PROGRESS_MASK                                                                  0x80000000L
17162 //COMPUTE_PGM_RSRC2
17163 #define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT                                                                  0x0
17164 #define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT                                                                   0x1
17165 #define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT                                                                0x6
17166 #define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT                                                                   0x7
17167 #define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT                                                                   0x8
17168 #define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT                                                                   0x9
17169 #define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT                                                                  0xa
17170 #define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT                                                              0xb
17171 #define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT                                                                 0xd
17172 #define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT                                                                    0xf
17173 #define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT                                                                     0x18
17174 #define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK                                                                    0x00000001L
17175 #define COMPUTE_PGM_RSRC2__USER_SGPR_MASK                                                                     0x0000003EL
17176 #define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK                                                                  0x00000040L
17177 #define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK                                                                     0x00000080L
17178 #define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK                                                                     0x00000100L
17179 #define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK                                                                     0x00000200L
17180 #define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK                                                                    0x00000400L
17181 #define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK                                                                0x00001800L
17182 #define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK                                                                   0x00006000L
17183 #define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK                                                                      0x00FF8000L
17184 #define COMPUTE_PGM_RSRC2__EXCP_EN_MASK                                                                       0x7F000000L
17185 //COMPUTE_VMID
17186 #define COMPUTE_VMID__DATA__SHIFT                                                                             0x0
17187 #define COMPUTE_VMID__DATA_MASK                                                                               0x0000000FL
17188 //COMPUTE_RESOURCE_LIMITS
17189 #define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT                                                          0x0
17190 #define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT                                                             0xc
17191 #define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT                                                        0x10
17192 #define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT                                                        0x16
17193 #define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT                                                       0x17
17194 #define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT                                                        0x18
17195 #define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK                                                            0x000003FFL
17196 #define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK                                                               0x0000F000L
17197 #define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK                                                          0x003F0000L
17198 #define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK                                                          0x00400000L
17199 #define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK                                                         0x00800000L
17200 #define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK                                                          0x07000000L
17201 //COMPUTE_DESTINATION_EN_SE0
17202 #define COMPUTE_DESTINATION_EN_SE0__CU_EN__SHIFT                                                              0x0
17203 #define COMPUTE_DESTINATION_EN_SE0__CU_EN_MASK                                                                0xFFFFFFFFL
17204 //COMPUTE_STATIC_THREAD_MGMT_SE0
17205 #define COMPUTE_STATIC_THREAD_MGMT_SE0__SA0_CU_EN__SHIFT                                                      0x0
17206 #define COMPUTE_STATIC_THREAD_MGMT_SE0__SA1_CU_EN__SHIFT                                                      0x10
17207 #define COMPUTE_STATIC_THREAD_MGMT_SE0__SA0_CU_EN_MASK                                                        0x0000FFFFL
17208 #define COMPUTE_STATIC_THREAD_MGMT_SE0__SA1_CU_EN_MASK                                                        0xFFFF0000L
17209 //COMPUTE_DESTINATION_EN_SE1
17210 #define COMPUTE_DESTINATION_EN_SE1__CU_EN__SHIFT                                                              0x0
17211 #define COMPUTE_DESTINATION_EN_SE1__CU_EN_MASK                                                                0xFFFFFFFFL
17212 //COMPUTE_STATIC_THREAD_MGMT_SE1
17213 #define COMPUTE_STATIC_THREAD_MGMT_SE1__SA0_CU_EN__SHIFT                                                      0x0
17214 #define COMPUTE_STATIC_THREAD_MGMT_SE1__SA1_CU_EN__SHIFT                                                      0x10
17215 #define COMPUTE_STATIC_THREAD_MGMT_SE1__SA0_CU_EN_MASK                                                        0x0000FFFFL
17216 #define COMPUTE_STATIC_THREAD_MGMT_SE1__SA1_CU_EN_MASK                                                        0xFFFF0000L
17217 //COMPUTE_TMPRING_SIZE
17218 #define COMPUTE_TMPRING_SIZE__WAVES__SHIFT                                                                    0x0
17219 #define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT                                                                 0xc
17220 #define COMPUTE_TMPRING_SIZE__WAVES_MASK                                                                      0x00000FFFL
17221 #define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK                                                                   0x01FFF000L
17222 //COMPUTE_DESTINATION_EN_SE2
17223 #define COMPUTE_DESTINATION_EN_SE2__CU_EN__SHIFT                                                              0x0
17224 #define COMPUTE_DESTINATION_EN_SE2__CU_EN_MASK                                                                0xFFFFFFFFL
17225 //COMPUTE_STATIC_THREAD_MGMT_SE2
17226 #define COMPUTE_STATIC_THREAD_MGMT_SE2__SA0_CU_EN__SHIFT                                                      0x0
17227 #define COMPUTE_STATIC_THREAD_MGMT_SE2__SA1_CU_EN__SHIFT                                                      0x10
17228 #define COMPUTE_STATIC_THREAD_MGMT_SE2__SA0_CU_EN_MASK                                                        0x0000FFFFL
17229 #define COMPUTE_STATIC_THREAD_MGMT_SE2__SA1_CU_EN_MASK                                                        0xFFFF0000L
17230 //COMPUTE_DESTINATION_EN_SE3
17231 #define COMPUTE_DESTINATION_EN_SE3__CU_EN__SHIFT                                                              0x0
17232 #define COMPUTE_DESTINATION_EN_SE3__CU_EN_MASK                                                                0xFFFFFFFFL
17233 //COMPUTE_STATIC_THREAD_MGMT_SE3
17234 #define COMPUTE_STATIC_THREAD_MGMT_SE3__SA0_CU_EN__SHIFT                                                      0x0
17235 #define COMPUTE_STATIC_THREAD_MGMT_SE3__SA1_CU_EN__SHIFT                                                      0x10
17236 #define COMPUTE_STATIC_THREAD_MGMT_SE3__SA0_CU_EN_MASK                                                        0x0000FFFFL
17237 #define COMPUTE_STATIC_THREAD_MGMT_SE3__SA1_CU_EN_MASK                                                        0xFFFF0000L
17238 //COMPUTE_RESTART_X
17239 #define COMPUTE_RESTART_X__RESTART__SHIFT                                                                     0x0
17240 #define COMPUTE_RESTART_X__RESTART_MASK                                                                       0xFFFFFFFFL
17241 //COMPUTE_RESTART_Y
17242 #define COMPUTE_RESTART_Y__RESTART__SHIFT                                                                     0x0
17243 #define COMPUTE_RESTART_Y__RESTART_MASK                                                                       0xFFFFFFFFL
17244 //COMPUTE_RESTART_Z
17245 #define COMPUTE_RESTART_Z__RESTART__SHIFT                                                                     0x0
17246 #define COMPUTE_RESTART_Z__RESTART_MASK                                                                       0xFFFFFFFFL
17247 //COMPUTE_THREAD_TRACE_ENABLE
17248 #define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT                                               0x0
17249 #define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK                                                 0x00000001L
17250 //COMPUTE_MISC_RESERVED
17251 #define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT                                                               0x0
17252 #define COMPUTE_MISC_RESERVED__RESERVED2__SHIFT                                                               0x2
17253 #define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT                                                               0x3
17254 #define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT                                                               0x4
17255 #define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT                                                            0x5
17256 #define COMPUTE_MISC_RESERVED__SEND_SEID_MASK                                                                 0x00000003L
17257 #define COMPUTE_MISC_RESERVED__RESERVED2_MASK                                                                 0x00000004L
17258 #define COMPUTE_MISC_RESERVED__RESERVED3_MASK                                                                 0x00000008L
17259 #define COMPUTE_MISC_RESERVED__RESERVED4_MASK                                                                 0x00000010L
17260 #define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK                                                              0x0001FFE0L
17261 //COMPUTE_DISPATCH_ID
17262 #define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT                                                               0x0
17263 #define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK                                                                 0xFFFFFFFFL
17264 //COMPUTE_THREADGROUP_ID
17265 #define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT                                                         0x0
17266 #define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK                                                           0xFFFFFFFFL
17267 //COMPUTE_REQ_CTRL
17268 #define COMPUTE_REQ_CTRL__SOFT_GROUPING_EN__SHIFT                                                             0x0
17269 #define COMPUTE_REQ_CTRL__NUMBER_OF_REQUESTS_PER_CU__SHIFT                                                    0x1
17270 #define COMPUTE_REQ_CTRL__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT                                             0x5
17271 #define COMPUTE_REQ_CTRL__HARD_LOCK_HYSTERESIS__SHIFT                                                         0x9
17272 #define COMPUTE_REQ_CTRL__HARD_LOCK_LOW_THRESHOLD__SHIFT                                                      0xa
17273 #define COMPUTE_REQ_CTRL__PRODUCER_REQUEST_LOCKOUT__SHIFT                                                     0xf
17274 #define COMPUTE_REQ_CTRL__GLOBAL_SCANNING_EN__SHIFT                                                           0x10
17275 #define COMPUTE_REQ_CTRL__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT                                         0x11
17276 #define COMPUTE_REQ_CTRL__DEDICATED_PREALLOCATION_BUFFER_LIMIT__SHIFT                                         0x14
17277 #define COMPUTE_REQ_CTRL__SOFT_GROUPING_EN_MASK                                                               0x00000001L
17278 #define COMPUTE_REQ_CTRL__NUMBER_OF_REQUESTS_PER_CU_MASK                                                      0x0000001EL
17279 #define COMPUTE_REQ_CTRL__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK                                               0x000001E0L
17280 #define COMPUTE_REQ_CTRL__HARD_LOCK_HYSTERESIS_MASK                                                           0x00000200L
17281 #define COMPUTE_REQ_CTRL__HARD_LOCK_LOW_THRESHOLD_MASK                                                        0x00007C00L
17282 #define COMPUTE_REQ_CTRL__PRODUCER_REQUEST_LOCKOUT_MASK                                                       0x00008000L
17283 #define COMPUTE_REQ_CTRL__GLOBAL_SCANNING_EN_MASK                                                             0x00010000L
17284 #define COMPUTE_REQ_CTRL__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK                                           0x000E0000L
17285 #define COMPUTE_REQ_CTRL__DEDICATED_PREALLOCATION_BUFFER_LIMIT_MASK                                           0x07F00000L
17286 //COMPUTE_PREF_PRI_ACCUM_0
17287 #define COMPUTE_PREF_PRI_ACCUM_0__CONTRIBUTION__SHIFT                                                         0x0
17288 #define COMPUTE_PREF_PRI_ACCUM_0__COEFFICIENT_HIER_SELECT__SHIFT                                              0x7
17289 #define COMPUTE_PREF_PRI_ACCUM_0__CONTRIBUTION_HIER_SELECT__SHIFT                                             0xa
17290 #define COMPUTE_PREF_PRI_ACCUM_0__GROUP_UPDATE_EN__SHIFT                                                      0xd
17291 #define COMPUTE_PREF_PRI_ACCUM_0__RESERVED__SHIFT                                                             0xe
17292 #define COMPUTE_PREF_PRI_ACCUM_0__COEFFICIENT__SHIFT                                                          0xf
17293 #define COMPUTE_PREF_PRI_ACCUM_0__CONTRIBUTION_MASK                                                           0x0000007FL
17294 #define COMPUTE_PREF_PRI_ACCUM_0__COEFFICIENT_HIER_SELECT_MASK                                                0x00000380L
17295 #define COMPUTE_PREF_PRI_ACCUM_0__CONTRIBUTION_HIER_SELECT_MASK                                               0x00001C00L
17296 #define COMPUTE_PREF_PRI_ACCUM_0__GROUP_UPDATE_EN_MASK                                                        0x00002000L
17297 #define COMPUTE_PREF_PRI_ACCUM_0__RESERVED_MASK                                                               0x00004000L
17298 #define COMPUTE_PREF_PRI_ACCUM_0__COEFFICIENT_MASK                                                            0x007F8000L
17299 //COMPUTE_USER_ACCUM_0
17300 #define COMPUTE_USER_ACCUM_0__CONTRIBUTION__SHIFT                                                             0x0
17301 #define COMPUTE_USER_ACCUM_0__CONTRIBUTION_MASK                                                               0x0000007FL
17302 //COMPUTE_PREF_PRI_ACCUM_1
17303 #define COMPUTE_PREF_PRI_ACCUM_1__CONTRIBUTION__SHIFT                                                         0x0
17304 #define COMPUTE_PREF_PRI_ACCUM_1__COEFFICIENT_HIER_SELECT__SHIFT                                              0x7
17305 #define COMPUTE_PREF_PRI_ACCUM_1__CONTRIBUTION_HIER_SELECT__SHIFT                                             0xa
17306 #define COMPUTE_PREF_PRI_ACCUM_1__GROUP_UPDATE_EN__SHIFT                                                      0xd
17307 #define COMPUTE_PREF_PRI_ACCUM_1__RESERVED__SHIFT                                                             0xe
17308 #define COMPUTE_PREF_PRI_ACCUM_1__COEFFICIENT__SHIFT                                                          0xf
17309 #define COMPUTE_PREF_PRI_ACCUM_1__CONTRIBUTION_MASK                                                           0x0000007FL
17310 #define COMPUTE_PREF_PRI_ACCUM_1__COEFFICIENT_HIER_SELECT_MASK                                                0x00000380L
17311 #define COMPUTE_PREF_PRI_ACCUM_1__CONTRIBUTION_HIER_SELECT_MASK                                               0x00001C00L
17312 #define COMPUTE_PREF_PRI_ACCUM_1__GROUP_UPDATE_EN_MASK                                                        0x00002000L
17313 #define COMPUTE_PREF_PRI_ACCUM_1__RESERVED_MASK                                                               0x00004000L
17314 #define COMPUTE_PREF_PRI_ACCUM_1__COEFFICIENT_MASK                                                            0x007F8000L
17315 //COMPUTE_USER_ACCUM_1
17316 #define COMPUTE_USER_ACCUM_1__CONTRIBUTION__SHIFT                                                             0x0
17317 #define COMPUTE_USER_ACCUM_1__CONTRIBUTION_MASK                                                               0x0000007FL
17318 //COMPUTE_PREF_PRI_ACCUM_2
17319 #define COMPUTE_PREF_PRI_ACCUM_2__CONTRIBUTION__SHIFT                                                         0x0
17320 #define COMPUTE_PREF_PRI_ACCUM_2__COEFFICIENT_HIER_SELECT__SHIFT                                              0x7
17321 #define COMPUTE_PREF_PRI_ACCUM_2__CONTRIBUTION_HIER_SELECT__SHIFT                                             0xa
17322 #define COMPUTE_PREF_PRI_ACCUM_2__GROUP_UPDATE_EN__SHIFT                                                      0xd
17323 #define COMPUTE_PREF_PRI_ACCUM_2__RESERVED__SHIFT                                                             0xe
17324 #define COMPUTE_PREF_PRI_ACCUM_2__COEFFICIENT__SHIFT                                                          0xf
17325 #define COMPUTE_PREF_PRI_ACCUM_2__CONTRIBUTION_MASK                                                           0x0000007FL
17326 #define COMPUTE_PREF_PRI_ACCUM_2__COEFFICIENT_HIER_SELECT_MASK                                                0x00000380L
17327 #define COMPUTE_PREF_PRI_ACCUM_2__CONTRIBUTION_HIER_SELECT_MASK                                               0x00001C00L
17328 #define COMPUTE_PREF_PRI_ACCUM_2__GROUP_UPDATE_EN_MASK                                                        0x00002000L
17329 #define COMPUTE_PREF_PRI_ACCUM_2__RESERVED_MASK                                                               0x00004000L
17330 #define COMPUTE_PREF_PRI_ACCUM_2__COEFFICIENT_MASK                                                            0x007F8000L
17331 //COMPUTE_USER_ACCUM_2
17332 #define COMPUTE_USER_ACCUM_2__CONTRIBUTION__SHIFT                                                             0x0
17333 #define COMPUTE_USER_ACCUM_2__CONTRIBUTION_MASK                                                               0x0000007FL
17334 //COMPUTE_PREF_PRI_ACCUM_3
17335 #define COMPUTE_PREF_PRI_ACCUM_3__CONTRIBUTION__SHIFT                                                         0x0
17336 #define COMPUTE_PREF_PRI_ACCUM_3__COEFFICIENT_HIER_SELECT__SHIFT                                              0x7
17337 #define COMPUTE_PREF_PRI_ACCUM_3__CONTRIBUTION_HIER_SELECT__SHIFT                                             0xa
17338 #define COMPUTE_PREF_PRI_ACCUM_3__GROUP_UPDATE_EN__SHIFT                                                      0xd
17339 #define COMPUTE_PREF_PRI_ACCUM_3__RESERVED__SHIFT                                                             0xe
17340 #define COMPUTE_PREF_PRI_ACCUM_3__COEFFICIENT__SHIFT                                                          0xf
17341 #define COMPUTE_PREF_PRI_ACCUM_3__CONTRIBUTION_MASK                                                           0x0000007FL
17342 #define COMPUTE_PREF_PRI_ACCUM_3__COEFFICIENT_HIER_SELECT_MASK                                                0x00000380L
17343 #define COMPUTE_PREF_PRI_ACCUM_3__CONTRIBUTION_HIER_SELECT_MASK                                               0x00001C00L
17344 #define COMPUTE_PREF_PRI_ACCUM_3__GROUP_UPDATE_EN_MASK                                                        0x00002000L
17345 #define COMPUTE_PREF_PRI_ACCUM_3__RESERVED_MASK                                                               0x00004000L
17346 #define COMPUTE_PREF_PRI_ACCUM_3__COEFFICIENT_MASK                                                            0x007F8000L
17347 //COMPUTE_USER_ACCUM_3
17348 #define COMPUTE_USER_ACCUM_3__CONTRIBUTION__SHIFT                                                             0x0
17349 #define COMPUTE_USER_ACCUM_3__CONTRIBUTION_MASK                                                               0x0000007FL
17350 //COMPUTE_PGM_RSRC3
17351 #define COMPUTE_PGM_RSRC3__SHARED_VGPR_CNT__SHIFT                                                             0x0
17352 #define COMPUTE_PGM_RSRC3__SHARED_VGPR_CNT_MASK                                                               0x0000000FL
17353 //COMPUTE_DDID_INDEX
17354 #define COMPUTE_DDID_INDEX__INDEX__SHIFT                                                                      0x0
17355 #define COMPUTE_DDID_INDEX__INDEX_MASK                                                                        0x000007FFL
17356 //COMPUTE_SHADER_CHKSUM
17357 #define COMPUTE_SHADER_CHKSUM__CHECKSUM__SHIFT                                                                0x0
17358 #define COMPUTE_SHADER_CHKSUM__CHECKSUM_MASK                                                                  0xFFFFFFFFL
17359 //COMPUTE_RELAUNCH
17360 #define COMPUTE_RELAUNCH__PAYLOAD__SHIFT                                                                      0x0
17361 #define COMPUTE_RELAUNCH__IS_EVENT__SHIFT                                                                     0x1e
17362 #define COMPUTE_RELAUNCH__IS_STATE__SHIFT                                                                     0x1f
17363 #define COMPUTE_RELAUNCH__PAYLOAD_MASK                                                                        0x3FFFFFFFL
17364 #define COMPUTE_RELAUNCH__IS_EVENT_MASK                                                                       0x40000000L
17365 #define COMPUTE_RELAUNCH__IS_STATE_MASK                                                                       0x80000000L
17366 //COMPUTE_WAVE_RESTORE_ADDR_LO
17367 #define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT                                                             0x0
17368 #define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK                                                               0xFFFFFFFFL
17369 //COMPUTE_WAVE_RESTORE_ADDR_HI
17370 #define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT                                                             0x0
17371 #define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK                                                               0xFFFFL
17372 //COMPUTE_RELAUNCH2
17373 #define COMPUTE_RELAUNCH2__PAYLOAD__SHIFT                                                                     0x0
17374 #define COMPUTE_RELAUNCH2__IS_EVENT__SHIFT                                                                    0x1e
17375 #define COMPUTE_RELAUNCH2__IS_STATE__SHIFT                                                                    0x1f
17376 #define COMPUTE_RELAUNCH2__PAYLOAD_MASK                                                                       0x3FFFFFFFL
17377 #define COMPUTE_RELAUNCH2__IS_EVENT_MASK                                                                      0x40000000L
17378 #define COMPUTE_RELAUNCH2__IS_STATE_MASK                                                                      0x80000000L
17379 //COMPUTE_USER_DATA_0
17380 #define COMPUTE_USER_DATA_0__DATA__SHIFT                                                                      0x0
17381 #define COMPUTE_USER_DATA_0__DATA_MASK                                                                        0xFFFFFFFFL
17382 //COMPUTE_USER_DATA_1
17383 #define COMPUTE_USER_DATA_1__DATA__SHIFT                                                                      0x0
17384 #define COMPUTE_USER_DATA_1__DATA_MASK                                                                        0xFFFFFFFFL
17385 //COMPUTE_USER_DATA_2
17386 #define COMPUTE_USER_DATA_2__DATA__SHIFT                                                                      0x0
17387 #define COMPUTE_USER_DATA_2__DATA_MASK                                                                        0xFFFFFFFFL
17388 //COMPUTE_USER_DATA_3
17389 #define COMPUTE_USER_DATA_3__DATA__SHIFT                                                                      0x0
17390 #define COMPUTE_USER_DATA_3__DATA_MASK                                                                        0xFFFFFFFFL
17391 //COMPUTE_USER_DATA_4
17392 #define COMPUTE_USER_DATA_4__DATA__SHIFT                                                                      0x0
17393 #define COMPUTE_USER_DATA_4__DATA_MASK                                                                        0xFFFFFFFFL
17394 //COMPUTE_USER_DATA_5
17395 #define COMPUTE_USER_DATA_5__DATA__SHIFT                                                                      0x0
17396 #define COMPUTE_USER_DATA_5__DATA_MASK                                                                        0xFFFFFFFFL
17397 //COMPUTE_USER_DATA_6
17398 #define COMPUTE_USER_DATA_6__DATA__SHIFT                                                                      0x0
17399 #define COMPUTE_USER_DATA_6__DATA_MASK                                                                        0xFFFFFFFFL
17400 //COMPUTE_USER_DATA_7
17401 #define COMPUTE_USER_DATA_7__DATA__SHIFT                                                                      0x0
17402 #define COMPUTE_USER_DATA_7__DATA_MASK                                                                        0xFFFFFFFFL
17403 //COMPUTE_USER_DATA_8
17404 #define COMPUTE_USER_DATA_8__DATA__SHIFT                                                                      0x0
17405 #define COMPUTE_USER_DATA_8__DATA_MASK                                                                        0xFFFFFFFFL
17406 //COMPUTE_USER_DATA_9
17407 #define COMPUTE_USER_DATA_9__DATA__SHIFT                                                                      0x0
17408 #define COMPUTE_USER_DATA_9__DATA_MASK                                                                        0xFFFFFFFFL
17409 //COMPUTE_USER_DATA_10
17410 #define COMPUTE_USER_DATA_10__DATA__SHIFT                                                                     0x0
17411 #define COMPUTE_USER_DATA_10__DATA_MASK                                                                       0xFFFFFFFFL
17412 //COMPUTE_USER_DATA_11
17413 #define COMPUTE_USER_DATA_11__DATA__SHIFT                                                                     0x0
17414 #define COMPUTE_USER_DATA_11__DATA_MASK                                                                       0xFFFFFFFFL
17415 //COMPUTE_USER_DATA_12
17416 #define COMPUTE_USER_DATA_12__DATA__SHIFT                                                                     0x0
17417 #define COMPUTE_USER_DATA_12__DATA_MASK                                                                       0xFFFFFFFFL
17418 //COMPUTE_USER_DATA_13
17419 #define COMPUTE_USER_DATA_13__DATA__SHIFT                                                                     0x0
17420 #define COMPUTE_USER_DATA_13__DATA_MASK                                                                       0xFFFFFFFFL
17421 //COMPUTE_USER_DATA_14
17422 #define COMPUTE_USER_DATA_14__DATA__SHIFT                                                                     0x0
17423 #define COMPUTE_USER_DATA_14__DATA_MASK                                                                       0xFFFFFFFFL
17424 //COMPUTE_USER_DATA_15
17425 #define COMPUTE_USER_DATA_15__DATA__SHIFT                                                                     0x0
17426 #define COMPUTE_USER_DATA_15__DATA_MASK                                                                       0xFFFFFFFFL
17427 //COMPUTE_DISPATCH_TUNNEL
17428 #define COMPUTE_DISPATCH_TUNNEL__OFF_DELAY__SHIFT                                                             0x0
17429 #define COMPUTE_DISPATCH_TUNNEL__IMMEDIATE__SHIFT                                                             0xa
17430 #define COMPUTE_DISPATCH_TUNNEL__OFF_DELAY_MASK                                                               0x000003FFL
17431 #define COMPUTE_DISPATCH_TUNNEL__IMMEDIATE_MASK                                                               0x00000400L
17432 //COMPUTE_DISPATCH_END
17433 #define COMPUTE_DISPATCH_END__DATA__SHIFT                                                                     0x0
17434 #define COMPUTE_DISPATCH_END__DATA_MASK                                                                       0xFFFFFFFFL
17435 //COMPUTE_NOWHERE
17436 #define COMPUTE_NOWHERE__DATA__SHIFT                                                                          0x0
17437 #define COMPUTE_NOWHERE__DATA_MASK                                                                            0xFFFFFFFFL
17438 
17439 
17440 // addressBlock: gc_cppdec
17441 //CP_EOPQ_WAIT_TIME
17442 #define CP_EOPQ_WAIT_TIME__WAIT_TIME__SHIFT                                                                   0x0
17443 #define CP_EOPQ_WAIT_TIME__SCALE_COUNT__SHIFT                                                                 0xa
17444 #define CP_EOPQ_WAIT_TIME__WAIT_TIME_MASK                                                                     0x000003FFL
17445 #define CP_EOPQ_WAIT_TIME__SCALE_COUNT_MASK                                                                   0x0003FC00L
17446 //CP_CPC_MGCG_SYNC_CNTL
17447 #define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT                                                         0x0
17448 #define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT                                                           0x8
17449 #define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK                                                           0x000000FFL
17450 #define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK                                                             0x0000FF00L
17451 //CPC_INT_INFO
17452 #define CPC_INT_INFO__ADDR_HI__SHIFT                                                                          0x0
17453 #define CPC_INT_INFO__TYPE__SHIFT                                                                             0x10
17454 #define CPC_INT_INFO__VMID__SHIFT                                                                             0x14
17455 #define CPC_INT_INFO__QUEUE_ID__SHIFT                                                                         0x1c
17456 #define CPC_INT_INFO__ADDR_HI_MASK                                                                            0x0000FFFFL
17457 #define CPC_INT_INFO__TYPE_MASK                                                                               0x00010000L
17458 #define CPC_INT_INFO__VMID_MASK                                                                               0x00F00000L
17459 #define CPC_INT_INFO__QUEUE_ID_MASK                                                                           0x70000000L
17460 //CP_VIRT_STATUS
17461 #define CP_VIRT_STATUS__VIRT_STATUS__SHIFT                                                                    0x0
17462 #define CP_VIRT_STATUS__VIRT_STATUS_MASK                                                                      0xFFFFFFFFL
17463 //CPC_INT_ADDR
17464 #define CPC_INT_ADDR__ADDR__SHIFT                                                                             0x0
17465 #define CPC_INT_ADDR__ADDR_MASK                                                                               0xFFFFFFFFL
17466 //CPC_INT_PASID
17467 #define CPC_INT_PASID__PASID__SHIFT                                                                           0x0
17468 #define CPC_INT_PASID__BYPASS_PASID__SHIFT                                                                    0x10
17469 #define CPC_INT_PASID__PASID_MASK                                                                             0x0000FFFFL
17470 #define CPC_INT_PASID__BYPASS_PASID_MASK                                                                      0x00010000L
17471 //CP_GFX_ERROR
17472 #define CP_GFX_ERROR__EDC_ERROR_ID__SHIFT                                                                     0x0
17473 #define CP_GFX_ERROR__SUA_ERROR__SHIFT                                                                        0x4
17474 #define CP_GFX_ERROR__CE_DATA_FETCHER_UTCL1_ERROR__SHIFT                                                      0x5
17475 #define CP_GFX_ERROR__DATA_FETCHER_UTCL1_ERROR__SHIFT                                                         0x6
17476 #define CP_GFX_ERROR__SEM_UTCL1_ERROR__SHIFT                                                                  0x7
17477 #define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR__SHIFT                                                              0x8
17478 #define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR__SHIFT                                                               0x9
17479 #define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR__SHIFT                                                              0xa
17480 #define CP_GFX_ERROR__QU_READ_UTCL1_ERROR__SHIFT                                                              0xb
17481 #define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR__SHIFT                                                           0xc
17482 #define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR__SHIFT                                                           0xd
17483 #define CP_GFX_ERROR__SHADOW_UTCL1_ERROR__SHIFT                                                               0xe
17484 #define CP_GFX_ERROR__APPEND_UTCL1_ERROR__SHIFT                                                               0xf
17485 #define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR__SHIFT                                                               0x10
17486 #define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR__SHIFT                                                           0x11
17487 #define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT                                                              0x12
17488 #define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR__SHIFT                                                              0x13
17489 #define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR__SHIFT                                                               0x14
17490 #define CP_GFX_ERROR__ME_TC_UTCL1_ERROR__SHIFT                                                                0x15
17491 #define CP_GFX_ERROR__CE_TC_UTCL1_ERROR__SHIFT                                                                0x16
17492 #define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR__SHIFT                                                              0x17
17493 #define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR__SHIFT                                                            0x18
17494 #define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR__SHIFT                                                           0x19
17495 #define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR__SHIFT                                                           0x1a
17496 #define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR__SHIFT                                                           0x1b
17497 #define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR__SHIFT                                                           0x1c
17498 #define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR__SHIFT                                                           0x1d
17499 #define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR__SHIFT                                                           0x1e
17500 #define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR__SHIFT                                                              0x1f
17501 #define CP_GFX_ERROR__EDC_ERROR_ID_MASK                                                                       0x0000000FL
17502 #define CP_GFX_ERROR__SUA_ERROR_MASK                                                                          0x00000010L
17503 #define CP_GFX_ERROR__CE_DATA_FETCHER_UTCL1_ERROR_MASK                                                        0x00000020L
17504 #define CP_GFX_ERROR__DATA_FETCHER_UTCL1_ERROR_MASK                                                           0x00000040L
17505 #define CP_GFX_ERROR__SEM_UTCL1_ERROR_MASK                                                                    0x00000080L
17506 #define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR_MASK                                                                0x00000100L
17507 #define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR_MASK                                                                 0x00000200L
17508 #define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR_MASK                                                                0x00000400L
17509 #define CP_GFX_ERROR__QU_READ_UTCL1_ERROR_MASK                                                                0x00000800L
17510 #define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR_MASK                                                             0x00001000L
17511 #define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR_MASK                                                             0x00002000L
17512 #define CP_GFX_ERROR__SHADOW_UTCL1_ERROR_MASK                                                                 0x00004000L
17513 #define CP_GFX_ERROR__APPEND_UTCL1_ERROR_MASK                                                                 0x00008000L
17514 #define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR_MASK                                                                 0x00010000L
17515 #define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR_MASK                                                             0x00020000L
17516 #define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR_MASK                                                                0x00040000L
17517 #define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR_MASK                                                                0x00080000L
17518 #define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR_MASK                                                                 0x00100000L
17519 #define CP_GFX_ERROR__ME_TC_UTCL1_ERROR_MASK                                                                  0x00200000L
17520 #define CP_GFX_ERROR__CE_TC_UTCL1_ERROR_MASK                                                                  0x00400000L
17521 #define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR_MASK                                                                0x00800000L
17522 #define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR_MASK                                                              0x01000000L
17523 #define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR_MASK                                                             0x02000000L
17524 #define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR_MASK                                                             0x04000000L
17525 #define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR_MASK                                                             0x08000000L
17526 #define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR_MASK                                                             0x10000000L
17527 #define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR_MASK                                                             0x20000000L
17528 #define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR_MASK                                                             0x40000000L
17529 #define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR_MASK                                                                0x80000000L
17530 //CPG_UTCL1_CNTL
17531 #define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT                                                           0x0
17532 #define CPG_UTCL1_CNTL__VMID_RESET_MODE__SHIFT                                                                0x17
17533 #define CPG_UTCL1_CNTL__DROP_MODE__SHIFT                                                                      0x18
17534 #define CPG_UTCL1_CNTL__BYPASS__SHIFT                                                                         0x19
17535 #define CPG_UTCL1_CNTL__INVALIDATE__SHIFT                                                                     0x1a
17536 #define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT                                                                0x1b
17537 #define CPG_UTCL1_CNTL__FORCE_SNOOP__SHIFT                                                                    0x1c
17538 #define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT                                                              0x1e
17539 #define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK                                                             0x000FFFFFL
17540 #define CPG_UTCL1_CNTL__VMID_RESET_MODE_MASK                                                                  0x00800000L
17541 #define CPG_UTCL1_CNTL__DROP_MODE_MASK                                                                        0x01000000L
17542 #define CPG_UTCL1_CNTL__BYPASS_MASK                                                                           0x02000000L
17543 #define CPG_UTCL1_CNTL__INVALIDATE_MASK                                                                       0x04000000L
17544 #define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK                                                                  0x08000000L
17545 #define CPG_UTCL1_CNTL__FORCE_SNOOP_MASK                                                                      0x10000000L
17546 #define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK                                                                0x40000000L
17547 //CPC_UTCL1_CNTL
17548 #define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT                                                           0x0
17549 #define CPC_UTCL1_CNTL__DROP_MODE__SHIFT                                                                      0x18
17550 #define CPC_UTCL1_CNTL__BYPASS__SHIFT                                                                         0x19
17551 #define CPC_UTCL1_CNTL__INVALIDATE__SHIFT                                                                     0x1a
17552 #define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT                                                                0x1b
17553 #define CPC_UTCL1_CNTL__FORCE_SNOOP__SHIFT                                                                    0x1c
17554 #define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT                                                              0x1e
17555 #define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK                                                             0x000FFFFFL
17556 #define CPC_UTCL1_CNTL__DROP_MODE_MASK                                                                        0x01000000L
17557 #define CPC_UTCL1_CNTL__BYPASS_MASK                                                                           0x02000000L
17558 #define CPC_UTCL1_CNTL__INVALIDATE_MASK                                                                       0x04000000L
17559 #define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK                                                                  0x08000000L
17560 #define CPC_UTCL1_CNTL__FORCE_SNOOP_MASK                                                                      0x10000000L
17561 #define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK                                                                0x40000000L
17562 //CPF_UTCL1_CNTL
17563 #define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT                                                           0x0
17564 #define CPF_UTCL1_CNTL__VMID_RESET_MODE__SHIFT                                                                0x17
17565 #define CPF_UTCL1_CNTL__DROP_MODE__SHIFT                                                                      0x18
17566 #define CPF_UTCL1_CNTL__BYPASS__SHIFT                                                                         0x19
17567 #define CPF_UTCL1_CNTL__INVALIDATE__SHIFT                                                                     0x1a
17568 #define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT                                                                0x1b
17569 #define CPF_UTCL1_CNTL__FORCE_SNOOP__SHIFT                                                                    0x1c
17570 #define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT                                                              0x1e
17571 #define CPF_UTCL1_CNTL__FORCE_NO_EXE__SHIFT                                                                   0x1f
17572 #define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK                                                             0x000FFFFFL
17573 #define CPF_UTCL1_CNTL__VMID_RESET_MODE_MASK                                                                  0x00800000L
17574 #define CPF_UTCL1_CNTL__DROP_MODE_MASK                                                                        0x01000000L
17575 #define CPF_UTCL1_CNTL__BYPASS_MASK                                                                           0x02000000L
17576 #define CPF_UTCL1_CNTL__INVALIDATE_MASK                                                                       0x04000000L
17577 #define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK                                                                  0x08000000L
17578 #define CPF_UTCL1_CNTL__FORCE_SNOOP_MASK                                                                      0x10000000L
17579 #define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK                                                                0x40000000L
17580 #define CPF_UTCL1_CNTL__FORCE_NO_EXE_MASK                                                                     0x80000000L
17581 //CP_AQL_SMM_STATUS
17582 #define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM__SHIFT                                                               0x0
17583 #define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM_MASK                                                                 0xFFFFFFFFL
17584 //CP_RB0_BASE
17585 #define CP_RB0_BASE__RB_BASE__SHIFT                                                                           0x0
17586 #define CP_RB0_BASE__RB_BASE_MASK                                                                             0xFFFFFFFFL
17587 //CP_RB_BASE
17588 #define CP_RB_BASE__RB_BASE__SHIFT                                                                            0x0
17589 #define CP_RB_BASE__RB_BASE_MASK                                                                              0xFFFFFFFFL
17590 //CP_RB0_CNTL
17591 #define CP_RB0_CNTL__RB_BUFSZ__SHIFT                                                                          0x0
17592 #define CP_RB0_CNTL__RB_BLKSZ__SHIFT                                                                          0x8
17593 #define CP_RB0_CNTL__BUF_SWAP__SHIFT                                                                          0x10
17594 #define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT                                                                       0x14
17595 #define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT                                                                    0x16
17596 #define CP_RB0_CNTL__CACHE_POLICY__SHIFT                                                                      0x18
17597 #define CP_RB0_CNTL__RB_VOLATILE__SHIFT                                                                       0x1a
17598 #define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT                                                                      0x1b
17599 #define CP_RB0_CNTL__RB_EXE__SHIFT                                                                            0x1c
17600 #define CP_RB0_CNTL__CE_HQD_NEQ_RB_HQD__SHIFT                                                                 0x1e
17601 #define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT                                                                    0x1f
17602 #define CP_RB0_CNTL__RB_BUFSZ_MASK                                                                            0x0000003FL
17603 #define CP_RB0_CNTL__RB_BLKSZ_MASK                                                                            0x00003F00L
17604 #define CP_RB0_CNTL__BUF_SWAP_MASK                                                                            0x00030000L
17605 #define CP_RB0_CNTL__MIN_AVAILSZ_MASK                                                                         0x00300000L
17606 #define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK                                                                      0x00C00000L
17607 #define CP_RB0_CNTL__CACHE_POLICY_MASK                                                                        0x03000000L
17608 #define CP_RB0_CNTL__RB_VOLATILE_MASK                                                                         0x04000000L
17609 #define CP_RB0_CNTL__RB_NO_UPDATE_MASK                                                                        0x08000000L
17610 #define CP_RB0_CNTL__RB_EXE_MASK                                                                              0x10000000L
17611 #define CP_RB0_CNTL__CE_HQD_NEQ_RB_HQD_MASK                                                                   0x40000000L
17612 #define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK                                                                      0x80000000L
17613 //CP_RB_CNTL
17614 #define CP_RB_CNTL__RB_BUFSZ__SHIFT                                                                           0x0
17615 #define CP_RB_CNTL__RB_BLKSZ__SHIFT                                                                           0x8
17616 #define CP_RB_CNTL__BUF_SWAP__SHIFT                                                                           0x10
17617 #define CP_RB_CNTL__MIN_AVAILSZ__SHIFT                                                                        0x14
17618 #define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT                                                                     0x16
17619 #define CP_RB_CNTL__CACHE_POLICY__SHIFT                                                                       0x18
17620 #define CP_RB_CNTL__RB_VOLATILE__SHIFT                                                                        0x1a
17621 #define CP_RB_CNTL__RB_NO_UPDATE__SHIFT                                                                       0x1b
17622 #define CP_RB_CNTL__RB_EXE__SHIFT                                                                             0x1c
17623 #define CP_RB_CNTL__KMD_QUEUE__SHIFT                                                                          0x1d
17624 #define CP_RB_CNTL__CE_HQD_NEQ_RB_HQD__SHIFT                                                                  0x1e
17625 #define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT                                                                     0x1f
17626 #define CP_RB_CNTL__RB_BUFSZ_MASK                                                                             0x0000003FL
17627 #define CP_RB_CNTL__RB_BLKSZ_MASK                                                                             0x00003F00L
17628 #define CP_RB_CNTL__BUF_SWAP_MASK                                                                             0x00030000L
17629 #define CP_RB_CNTL__MIN_AVAILSZ_MASK                                                                          0x00300000L
17630 #define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK                                                                       0x00C00000L
17631 #define CP_RB_CNTL__CACHE_POLICY_MASK                                                                         0x03000000L
17632 #define CP_RB_CNTL__RB_VOLATILE_MASK                                                                          0x04000000L
17633 #define CP_RB_CNTL__RB_NO_UPDATE_MASK                                                                         0x08000000L
17634 #define CP_RB_CNTL__RB_EXE_MASK                                                                               0x10000000L
17635 #define CP_RB_CNTL__KMD_QUEUE_MASK                                                                            0x20000000L
17636 #define CP_RB_CNTL__CE_HQD_NEQ_RB_HQD_MASK                                                                    0x40000000L
17637 #define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK                                                                       0x80000000L
17638 //CP_RB_RPTR_WR
17639 #define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT                                                                      0x0
17640 #define CP_RB_RPTR_WR__RB_RPTR_WR_MASK                                                                        0x000FFFFFL
17641 //CP_RB0_RPTR_ADDR
17642 #define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT                                                                 0x2
17643 #define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK                                                                   0xFFFFFFFCL
17644 //CP_RB_RPTR_ADDR
17645 #define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT                                                                  0x2
17646 #define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK                                                                    0xFFFFFFFCL
17647 //CP_RB0_RPTR_ADDR_HI
17648 #define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT                                                           0x0
17649 #define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK                                                             0x0000FFFFL
17650 //CP_RB_RPTR_ADDR_HI
17651 #define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT                                                            0x0
17652 #define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK                                                              0x0000FFFFL
17653 //CP_RB0_BUFSZ_MASK
17654 #define CP_RB0_BUFSZ_MASK__DATA__SHIFT                                                                        0x0
17655 #define CP_RB0_BUFSZ_MASK__DATA_MASK                                                                          0x000FFFFFL
17656 //CP_RB_BUFSZ_MASK
17657 #define CP_RB_BUFSZ_MASK__DATA__SHIFT                                                                         0x0
17658 #define CP_RB_BUFSZ_MASK__DATA_MASK                                                                           0x000FFFFFL
17659 //CP_INT_CNTL
17660 #define CP_INT_CNTL__RESUME_INT_ENABLE__SHIFT                                                                 0x8
17661 #define CP_INT_CNTL__SUSPEND_INT_ENABLE__SHIFT                                                                0x9
17662 #define CP_INT_CNTL__DMA_WATCH_INT_ENABLE__SHIFT                                                              0xa
17663 #define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT                                                      0xb
17664 #define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                           0xe
17665 #define CP_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                                    0x10
17666 #define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                                       0x11
17667 #define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT                                                               0x12
17668 #define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT                                                              0x13
17669 #define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT                                                             0x14
17670 #define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT                                                               0x15
17671 #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT                                                             0x16
17672 #define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                               0x17
17673 #define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                           0x18
17674 #define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                             0x1a
17675 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                                     0x1b
17676 #define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                               0x1d
17677 #define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                               0x1e
17678 #define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                               0x1f
17679 #define CP_INT_CNTL__RESUME_INT_ENABLE_MASK                                                                   0x00000100L
17680 #define CP_INT_CNTL__SUSPEND_INT_ENABLE_MASK                                                                  0x00000200L
17681 #define CP_INT_CNTL__DMA_WATCH_INT_ENABLE_MASK                                                                0x00000400L
17682 #define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK                                                        0x00000800L
17683 #define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                             0x00004000L
17684 #define CP_INT_CNTL__GPF_INT_ENABLE_MASK                                                                      0x00010000L
17685 #define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                                         0x00020000L
17686 #define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK                                                                 0x00040000L
17687 #define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK                                                                0x00080000L
17688 #define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK                                                               0x00100000L
17689 #define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK                                                                 0x00200000L
17690 #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK                                                               0x00400000L
17691 #define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                                 0x00800000L
17692 #define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                             0x01000000L
17693 #define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                               0x04000000L
17694 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                                       0x08000000L
17695 #define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                                 0x20000000L
17696 #define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                                 0x40000000L
17697 #define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                                 0x80000000L
17698 //CP_INT_STATUS
17699 #define CP_INT_STATUS__RESUME_INT_STAT__SHIFT                                                                 0x8
17700 #define CP_INT_STATUS__SUSPEND_INT_STAT__SHIFT                                                                0x9
17701 #define CP_INT_STATUS__DMA_WATCH_INT_STAT__SHIFT                                                              0xa
17702 #define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT                                                      0xb
17703 #define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT                                                           0xe
17704 #define CP_INT_STATUS__GPF_INT_STAT__SHIFT                                                                    0x10
17705 #define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT                                                       0x11
17706 #define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT                                                               0x12
17707 #define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT                                                              0x13
17708 #define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT                                                             0x14
17709 #define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT                                                               0x15
17710 #define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT                                                             0x16
17711 #define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT                                                               0x17
17712 #define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT                                                           0x18
17713 #define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT                                                             0x1a
17714 #define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT                                                     0x1b
17715 #define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT                                                               0x1d
17716 #define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT                                                               0x1e
17717 #define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT                                                               0x1f
17718 #define CP_INT_STATUS__RESUME_INT_STAT_MASK                                                                   0x00000100L
17719 #define CP_INT_STATUS__SUSPEND_INT_STAT_MASK                                                                  0x00000200L
17720 #define CP_INT_STATUS__DMA_WATCH_INT_STAT_MASK                                                                0x00000400L
17721 #define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK                                                        0x00000800L
17722 #define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK                                                             0x00004000L
17723 #define CP_INT_STATUS__GPF_INT_STAT_MASK                                                                      0x00010000L
17724 #define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK                                                         0x00020000L
17725 #define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK                                                                 0x00040000L
17726 #define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK                                                                0x00080000L
17727 #define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK                                                               0x00100000L
17728 #define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK                                                                 0x00200000L
17729 #define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK                                                               0x00400000L
17730 #define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK                                                                 0x00800000L
17731 #define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK                                                             0x01000000L
17732 #define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK                                                               0x04000000L
17733 #define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK                                                       0x08000000L
17734 #define CP_INT_STATUS__GENERIC2_INT_STAT_MASK                                                                 0x20000000L
17735 #define CP_INT_STATUS__GENERIC1_INT_STAT_MASK                                                                 0x40000000L
17736 #define CP_INT_STATUS__GENERIC0_INT_STAT_MASK                                                                 0x80000000L
17737 //CP_DEVICE_ID
17738 #define CP_DEVICE_ID__DEVICE_ID__SHIFT                                                                        0x0
17739 #define CP_DEVICE_ID__DEVICE_ID_MASK                                                                          0x000000FFL
17740 //CP_ME0_PIPE_PRIORITY_CNTS
17741 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT                                                       0x0
17742 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT                                                      0x8
17743 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT                                                      0x10
17744 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT                                                       0x18
17745 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK                                                         0x000000FFL
17746 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK                                                        0x0000FF00L
17747 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK                                                        0x00FF0000L
17748 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK                                                         0xFF000000L
17749 //CP_RING_PRIORITY_CNTS
17750 #define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT                                                           0x0
17751 #define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT                                                          0x8
17752 #define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT                                                          0x10
17753 #define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT                                                           0x18
17754 #define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK                                                             0x000000FFL
17755 #define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK                                                            0x0000FF00L
17756 #define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK                                                            0x00FF0000L
17757 #define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK                                                             0xFF000000L
17758 //CP_ME0_PIPE0_PRIORITY
17759 #define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT                                                                0x0
17760 #define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
17761 //CP_RING0_PRIORITY
17762 #define CP_RING0_PRIORITY__PRIORITY__SHIFT                                                                    0x0
17763 #define CP_RING0_PRIORITY__PRIORITY_MASK                                                                      0x00000003L
17764 //CP_ME0_PIPE1_PRIORITY
17765 #define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT                                                                0x0
17766 #define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
17767 //CP_RING1_PRIORITY
17768 #define CP_RING1_PRIORITY__PRIORITY__SHIFT                                                                    0x0
17769 #define CP_RING1_PRIORITY__PRIORITY_MASK                                                                      0x00000003L
17770 //CP_ME0_PIPE2_PRIORITY
17771 #define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT                                                                0x0
17772 #define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
17773 //CP_RING2_PRIORITY
17774 #define CP_RING2_PRIORITY__PRIORITY__SHIFT                                                                    0x0
17775 #define CP_RING2_PRIORITY__PRIORITY_MASK                                                                      0x00000003L
17776 //CP_FATAL_ERROR
17777 #define CP_FATAL_ERROR__CPF_FATAL_ERROR__SHIFT                                                                0x0
17778 #define CP_FATAL_ERROR__CPG_FATAL_ERROR__SHIFT                                                                0x1
17779 #define CP_FATAL_ERROR__GFX_HALT_PROC__SHIFT                                                                  0x2
17780 #define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR__SHIFT                                                            0x3
17781 #define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN__SHIFT                                                         0x4
17782 #define CP_FATAL_ERROR__CPF_FATAL_ERROR_MASK                                                                  0x00000001L
17783 #define CP_FATAL_ERROR__CPG_FATAL_ERROR_MASK                                                                  0x00000002L
17784 #define CP_FATAL_ERROR__GFX_HALT_PROC_MASK                                                                    0x00000004L
17785 #define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR_MASK                                                              0x00000008L
17786 #define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN_MASK                                                           0x00000010L
17787 //CP_RB_VMID
17788 #define CP_RB_VMID__RB0_VMID__SHIFT                                                                           0x0
17789 #define CP_RB_VMID__RB1_VMID__SHIFT                                                                           0x8
17790 #define CP_RB_VMID__RB2_VMID__SHIFT                                                                           0x10
17791 #define CP_RB_VMID__RB0_VMID_MASK                                                                             0x0000000FL
17792 #define CP_RB_VMID__RB1_VMID_MASK                                                                             0x00000F00L
17793 #define CP_RB_VMID__RB2_VMID_MASK                                                                             0x000F0000L
17794 //CP_ME0_PIPE0_VMID
17795 #define CP_ME0_PIPE0_VMID__VMID__SHIFT                                                                        0x0
17796 #define CP_ME0_PIPE0_VMID__VMID_MASK                                                                          0x0000000FL
17797 //CP_ME0_PIPE1_VMID
17798 #define CP_ME0_PIPE1_VMID__VMID__SHIFT                                                                        0x0
17799 #define CP_ME0_PIPE1_VMID__VMID_MASK                                                                          0x0000000FL
17800 //CP_RB0_WPTR
17801 #define CP_RB0_WPTR__RB_WPTR__SHIFT                                                                           0x0
17802 #define CP_RB0_WPTR__RB_WPTR_MASK                                                                             0xFFFFFFFFL
17803 //CP_RB_WPTR
17804 #define CP_RB_WPTR__RB_WPTR__SHIFT                                                                            0x0
17805 #define CP_RB_WPTR__RB_WPTR_MASK                                                                              0xFFFFFFFFL
17806 //CP_RB0_WPTR_HI
17807 #define CP_RB0_WPTR_HI__RB_WPTR__SHIFT                                                                        0x0
17808 #define CP_RB0_WPTR_HI__RB_WPTR_MASK                                                                          0xFFFFFFFFL
17809 //CP_RB_WPTR_HI
17810 #define CP_RB_WPTR_HI__RB_WPTR__SHIFT                                                                         0x0
17811 #define CP_RB_WPTR_HI__RB_WPTR_MASK                                                                           0xFFFFFFFFL
17812 //CP_RB1_WPTR
17813 #define CP_RB1_WPTR__RB_WPTR__SHIFT                                                                           0x0
17814 #define CP_RB1_WPTR__RB_WPTR_MASK                                                                             0xFFFFFFFFL
17815 //CP_RB1_WPTR_HI
17816 #define CP_RB1_WPTR_HI__RB_WPTR__SHIFT                                                                        0x0
17817 #define CP_RB1_WPTR_HI__RB_WPTR_MASK                                                                          0xFFFFFFFFL
17818 //CP_RB2_WPTR
17819 #define CP_RB2_WPTR__RB_WPTR__SHIFT                                                                           0x0
17820 #define CP_RB2_WPTR__RB_WPTR_MASK                                                                             0x000FFFFFL
17821 //CP_PROCESS_QUANTUM
17822 #define CP_PROCESS_QUANTUM__QUANTUM_DURATION__SHIFT                                                           0x0
17823 #define CP_PROCESS_QUANTUM__TIMER_EXPIRED__SHIFT                                                              0x1c
17824 #define CP_PROCESS_QUANTUM__QUANTUM_SCALE__SHIFT                                                              0x1d
17825 #define CP_PROCESS_QUANTUM__QUANTUM_EN__SHIFT                                                                 0x1f
17826 #define CP_PROCESS_QUANTUM__QUANTUM_DURATION_MASK                                                             0x0FFFFFFFL
17827 #define CP_PROCESS_QUANTUM__TIMER_EXPIRED_MASK                                                                0x10000000L
17828 #define CP_PROCESS_QUANTUM__QUANTUM_SCALE_MASK                                                                0x60000000L
17829 #define CP_PROCESS_QUANTUM__QUANTUM_EN_MASK                                                                   0x80000000L
17830 //CP_RB_DOORBELL_RANGE_LOWER
17831 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT                                               0x2
17832 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK                                                 0x0FFFFFFCL
17833 //CP_RB_DOORBELL_RANGE_UPPER
17834 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT                                               0x2
17835 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK                                                 0x0FFFFFFCL
17836 //CP_MEC_DOORBELL_RANGE_LOWER
17837 #define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT                                              0x2
17838 #define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK                                                0x0FFFFFFCL
17839 //CP_MEC_DOORBELL_RANGE_UPPER
17840 #define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT                                              0x2
17841 #define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK                                                0x0FFFFFFCL
17842 //CPG_UTCL1_ERROR
17843 #define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT                                                           0x0
17844 #define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK                                                             0x00000001L
17845 //CPC_UTCL1_ERROR
17846 #define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT                                                           0x0
17847 #define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK                                                             0x00000001L
17848 //CP_RB1_BASE
17849 #define CP_RB1_BASE__RB_BASE__SHIFT                                                                           0x0
17850 #define CP_RB1_BASE__RB_BASE_MASK                                                                             0xFFFFFFFFL
17851 //CP_RB1_CNTL
17852 #define CP_RB1_CNTL__RB_BUFSZ__SHIFT                                                                          0x0
17853 #define CP_RB1_CNTL__RB_BLKSZ__SHIFT                                                                          0x8
17854 #define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT                                                                       0x14
17855 #define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT                                                                    0x16
17856 #define CP_RB1_CNTL__CACHE_POLICY__SHIFT                                                                      0x18
17857 #define CP_RB1_CNTL__RB_VOLATILE__SHIFT                                                                       0x1a
17858 #define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT                                                                      0x1b
17859 #define CP_RB1_CNTL__RB_EXE__SHIFT                                                                            0x1c
17860 #define CP_RB1_CNTL__KMD_QUEUE__SHIFT                                                                         0x1d
17861 #define CP_RB1_CNTL__CE_HQD_NEQ_RB_HQD__SHIFT                                                                 0x1e
17862 #define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT                                                                    0x1f
17863 #define CP_RB1_CNTL__RB_BUFSZ_MASK                                                                            0x0000003FL
17864 #define CP_RB1_CNTL__RB_BLKSZ_MASK                                                                            0x00003F00L
17865 #define CP_RB1_CNTL__MIN_AVAILSZ_MASK                                                                         0x00300000L
17866 #define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK                                                                      0x00C00000L
17867 #define CP_RB1_CNTL__CACHE_POLICY_MASK                                                                        0x03000000L
17868 #define CP_RB1_CNTL__RB_VOLATILE_MASK                                                                         0x04000000L
17869 #define CP_RB1_CNTL__RB_NO_UPDATE_MASK                                                                        0x08000000L
17870 #define CP_RB1_CNTL__RB_EXE_MASK                                                                              0x10000000L
17871 #define CP_RB1_CNTL__KMD_QUEUE_MASK                                                                           0x20000000L
17872 #define CP_RB1_CNTL__CE_HQD_NEQ_RB_HQD_MASK                                                                   0x40000000L
17873 #define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK                                                                      0x80000000L
17874 //CP_RB1_RPTR_ADDR
17875 #define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT                                                                 0x2
17876 #define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK                                                                   0xFFFFFFFCL
17877 //CP_RB1_RPTR_ADDR_HI
17878 #define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT                                                           0x0
17879 #define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK                                                             0x0000FFFFL
17880 //CP_RB1_BUFSZ_MASK
17881 #define CP_RB1_BUFSZ_MASK__DATA__SHIFT                                                                        0x0
17882 #define CP_RB1_BUFSZ_MASK__DATA_MASK                                                                          0x000FFFFFL
17883 //CP_RB2_BASE
17884 #define CP_RB2_BASE__RB_BASE__SHIFT                                                                           0x0
17885 #define CP_RB2_BASE__RB_BASE_MASK                                                                             0xFFFFFFFFL
17886 //CP_RB2_CNTL
17887 #define CP_RB2_CNTL__RB_BUFSZ__SHIFT                                                                          0x0
17888 #define CP_RB2_CNTL__RB_BLKSZ__SHIFT                                                                          0x8
17889 #define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT                                                                       0x14
17890 #define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT                                                                    0x16
17891 #define CP_RB2_CNTL__CACHE_POLICY__SHIFT                                                                      0x18
17892 #define CP_RB2_CNTL__RB_VOLATILE__SHIFT                                                                       0x1a
17893 #define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT                                                                      0x1b
17894 #define CP_RB2_CNTL__RB_EXE__SHIFT                                                                            0x1c
17895 #define CP_RB2_CNTL__KMD_QUEUE__SHIFT                                                                         0x1d
17896 #define CP_RB2_CNTL__CE_HQD_NEQ_RB_HQD__SHIFT                                                                 0x1e
17897 #define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT                                                                    0x1f
17898 #define CP_RB2_CNTL__RB_BUFSZ_MASK                                                                            0x0000003FL
17899 #define CP_RB2_CNTL__RB_BLKSZ_MASK                                                                            0x00003F00L
17900 #define CP_RB2_CNTL__MIN_AVAILSZ_MASK                                                                         0x00300000L
17901 #define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK                                                                      0x00C00000L
17902 #define CP_RB2_CNTL__CACHE_POLICY_MASK                                                                        0x03000000L
17903 #define CP_RB2_CNTL__RB_VOLATILE_MASK                                                                         0x04000000L
17904 #define CP_RB2_CNTL__RB_NO_UPDATE_MASK                                                                        0x08000000L
17905 #define CP_RB2_CNTL__RB_EXE_MASK                                                                              0x10000000L
17906 #define CP_RB2_CNTL__KMD_QUEUE_MASK                                                                           0x20000000L
17907 #define CP_RB2_CNTL__CE_HQD_NEQ_RB_HQD_MASK                                                                   0x40000000L
17908 #define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK                                                                      0x80000000L
17909 //CP_RB2_RPTR_ADDR
17910 #define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT                                                                 0x2
17911 #define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK                                                                   0xFFFFFFFCL
17912 //CP_RB2_RPTR_ADDR_HI
17913 #define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT                                                           0x0
17914 #define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK                                                             0x0000FFFFL
17915 //CP_INT_CNTL_RING0
17916 #define CP_INT_CNTL_RING0__RESUME_INT_ENABLE__SHIFT                                                           0x8
17917 #define CP_INT_CNTL_RING0__SUSPEND_INT_ENABLE__SHIFT                                                          0x9
17918 #define CP_INT_CNTL_RING0__DMA_WATCH_INT_ENABLE__SHIFT                                                        0xa
17919 #define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT                                                0xb
17920 #define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                     0xe
17921 #define CP_INT_CNTL_RING0__GPF_INT_ENABLE__SHIFT                                                              0x10
17922 #define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                                 0x11
17923 #define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT                                                         0x12
17924 #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT                                                        0x13
17925 #define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT                                                       0x14
17926 #define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT                                                         0x15
17927 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT                                                       0x16
17928 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT                                                         0x17
17929 #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT                                                     0x18
17930 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT                                                       0x1a
17931 #define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                               0x1b
17932 #define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT                                                         0x1d
17933 #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT                                                         0x1e
17934 #define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT                                                         0x1f
17935 #define CP_INT_CNTL_RING0__RESUME_INT_ENABLE_MASK                                                             0x00000100L
17936 #define CP_INT_CNTL_RING0__SUSPEND_INT_ENABLE_MASK                                                            0x00000200L
17937 #define CP_INT_CNTL_RING0__DMA_WATCH_INT_ENABLE_MASK                                                          0x00000400L
17938 #define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK                                                  0x00000800L
17939 #define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK                                                       0x00004000L
17940 #define CP_INT_CNTL_RING0__GPF_INT_ENABLE_MASK                                                                0x00010000L
17941 #define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                                   0x00020000L
17942 #define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK                                                           0x00040000L
17943 #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK                                                          0x00080000L
17944 #define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK                                                         0x00100000L
17945 #define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK                                                           0x00200000L
17946 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK                                                         0x00400000L
17947 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK                                                           0x00800000L
17948 #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK                                                       0x01000000L
17949 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK                                                         0x04000000L
17950 #define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                                 0x08000000L
17951 #define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK                                                           0x20000000L
17952 #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK                                                           0x40000000L
17953 #define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK                                                           0x80000000L
17954 //CP_INT_CNTL_RING1
17955 #define CP_INT_CNTL_RING1__DMA_WATCH_INT_ENABLE__SHIFT                                                        0xa
17956 #define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT                                                0xb
17957 #define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                     0xe
17958 #define CP_INT_CNTL_RING1__GPF_INT_ENABLE__SHIFT                                                              0x10
17959 #define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                                 0x11
17960 #define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT                                                         0x12
17961 #define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT                                                        0x13
17962 #define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT                                                       0x14
17963 #define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT                                                         0x15
17964 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT                                                       0x16
17965 #define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT                                                         0x17
17966 #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT                                                     0x18
17967 #define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT                                                       0x1a
17968 #define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                               0x1b
17969 #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT                                                         0x1d
17970 #define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT                                                         0x1e
17971 #define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT                                                         0x1f
17972 #define CP_INT_CNTL_RING1__DMA_WATCH_INT_ENABLE_MASK                                                          0x00000400L
17973 #define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK                                                  0x00000800L
17974 #define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK                                                       0x00004000L
17975 #define CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK                                                                0x00010000L
17976 #define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                                   0x00020000L
17977 #define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK                                                           0x00040000L
17978 #define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK                                                          0x00080000L
17979 #define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK                                                         0x00100000L
17980 #define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK                                                           0x00200000L
17981 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK                                                         0x00400000L
17982 #define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK                                                           0x00800000L
17983 #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK                                                       0x01000000L
17984 #define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK                                                         0x04000000L
17985 #define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                                 0x08000000L
17986 #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK                                                           0x20000000L
17987 #define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK                                                           0x40000000L
17988 #define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK                                                           0x80000000L
17989 //CP_INT_CNTL_RING2
17990 #define CP_INT_CNTL_RING2__DMA_WATCH_INT_ENABLE__SHIFT                                                        0xa
17991 #define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT                                                0xb
17992 #define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                     0xe
17993 #define CP_INT_CNTL_RING2__GPF_INT_ENABLE__SHIFT                                                              0x10
17994 #define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                                 0x11
17995 #define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT                                                         0x12
17996 #define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT                                                        0x13
17997 #define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT                                                       0x14
17998 #define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT                                                         0x15
17999 #define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT                                                       0x16
18000 #define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT                                                         0x17
18001 #define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT                                                     0x18
18002 #define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT                                                       0x1a
18003 #define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                               0x1b
18004 #define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT                                                         0x1d
18005 #define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT                                                         0x1e
18006 #define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT                                                         0x1f
18007 #define CP_INT_CNTL_RING2__DMA_WATCH_INT_ENABLE_MASK                                                          0x00000400L
18008 #define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK                                                  0x00000800L
18009 #define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK                                                       0x00004000L
18010 #define CP_INT_CNTL_RING2__GPF_INT_ENABLE_MASK                                                                0x00010000L
18011 #define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                                   0x00020000L
18012 #define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK                                                           0x00040000L
18013 #define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK                                                          0x00080000L
18014 #define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK                                                         0x00100000L
18015 #define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK                                                           0x00200000L
18016 #define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK                                                         0x00400000L
18017 #define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK                                                           0x00800000L
18018 #define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK                                                       0x01000000L
18019 #define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK                                                         0x04000000L
18020 #define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                                 0x08000000L
18021 #define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK                                                           0x20000000L
18022 #define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK                                                           0x40000000L
18023 #define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK                                                           0x80000000L
18024 //CP_INT_STATUS_RING0
18025 #define CP_INT_STATUS_RING0__RESUME_INT_STAT__SHIFT                                                           0x8
18026 #define CP_INT_STATUS_RING0__SUSPEND_INT_STAT__SHIFT                                                          0x9
18027 #define CP_INT_STATUS_RING0__DMA_WATCH_INT_STAT__SHIFT                                                        0xa
18028 #define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT                                                0xb
18029 #define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT                                                     0xe
18030 #define CP_INT_STATUS_RING0__GPF_INT_STAT__SHIFT                                                              0x10
18031 #define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT                                                 0x11
18032 #define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT                                                         0x12
18033 #define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT                                                       0x13
18034 #define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT                                                       0x14
18035 #define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT                                                         0x15
18036 #define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT                                                       0x16
18037 #define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT                                                         0x17
18038 #define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT                                                     0x18
18039 #define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT                                                       0x1a
18040 #define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT                                               0x1b
18041 #define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT                                                         0x1d
18042 #define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT                                                         0x1e
18043 #define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT                                                         0x1f
18044 #define CP_INT_STATUS_RING0__RESUME_INT_STAT_MASK                                                             0x00000100L
18045 #define CP_INT_STATUS_RING0__SUSPEND_INT_STAT_MASK                                                            0x00000200L
18046 #define CP_INT_STATUS_RING0__DMA_WATCH_INT_STAT_MASK                                                          0x00000400L
18047 #define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK                                                  0x00000800L
18048 #define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK                                                       0x00004000L
18049 #define CP_INT_STATUS_RING0__GPF_INT_STAT_MASK                                                                0x00010000L
18050 #define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK                                                   0x00020000L
18051 #define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK                                                           0x00040000L
18052 #define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK                                                         0x00080000L
18053 #define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK                                                         0x00100000L
18054 #define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK                                                           0x00200000L
18055 #define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK                                                         0x00400000L
18056 #define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK                                                           0x00800000L
18057 #define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK                                                       0x01000000L
18058 #define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK                                                         0x04000000L
18059 #define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK                                                 0x08000000L
18060 #define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK                                                           0x20000000L
18061 #define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK                                                           0x40000000L
18062 #define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK                                                           0x80000000L
18063 //CP_INT_STATUS_RING1
18064 #define CP_INT_STATUS_RING1__DMA_WATCH_INT_STAT__SHIFT                                                        0xa
18065 #define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT                                                0xb
18066 #define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT                                                     0xe
18067 #define CP_INT_STATUS_RING1__GPF_INT_STAT__SHIFT                                                              0x10
18068 #define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT                                                 0x11
18069 #define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT                                                         0x12
18070 #define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT                                                        0x13
18071 #define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT                                                       0x14
18072 #define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT                                                         0x15
18073 #define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT                                                       0x16
18074 #define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT                                                         0x17
18075 #define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT                                                     0x18
18076 #define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT                                                       0x1a
18077 #define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT                                               0x1b
18078 #define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT                                                         0x1d
18079 #define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT                                                         0x1e
18080 #define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT                                                         0x1f
18081 #define CP_INT_STATUS_RING1__DMA_WATCH_INT_STAT_MASK                                                          0x00000400L
18082 #define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK                                                  0x00000800L
18083 #define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK                                                       0x00004000L
18084 #define CP_INT_STATUS_RING1__GPF_INT_STAT_MASK                                                                0x00010000L
18085 #define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK                                                   0x00020000L
18086 #define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK                                                           0x00040000L
18087 #define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK                                                          0x00080000L
18088 #define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK                                                         0x00100000L
18089 #define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK                                                           0x00200000L
18090 #define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK                                                         0x00400000L
18091 #define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK                                                           0x00800000L
18092 #define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK                                                       0x01000000L
18093 #define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK                                                         0x04000000L
18094 #define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK                                                 0x08000000L
18095 #define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK                                                           0x20000000L
18096 #define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK                                                           0x40000000L
18097 #define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK                                                           0x80000000L
18098 //CP_INT_STATUS_RING2
18099 #define CP_INT_STATUS_RING2__DMA_WATCH_INT_STAT__SHIFT                                                        0xa
18100 #define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT                                                0xb
18101 #define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT                                                     0xe
18102 #define CP_INT_STATUS_RING2__GPF_INT_STAT__SHIFT                                                              0x10
18103 #define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT                                                 0x11
18104 #define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT                                                         0x12
18105 #define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT                                                        0x13
18106 #define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT                                                       0x14
18107 #define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT                                                         0x15
18108 #define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT                                                       0x16
18109 #define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT                                                         0x17
18110 #define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT                                                     0x18
18111 #define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT                                                       0x1a
18112 #define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT                                               0x1b
18113 #define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT                                                         0x1d
18114 #define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT                                                         0x1e
18115 #define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT                                                         0x1f
18116 #define CP_INT_STATUS_RING2__DMA_WATCH_INT_STAT_MASK                                                          0x00000400L
18117 #define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK                                                  0x00000800L
18118 #define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK                                                       0x00004000L
18119 #define CP_INT_STATUS_RING2__GPF_INT_STAT_MASK                                                                0x00010000L
18120 #define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK                                                   0x00020000L
18121 #define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK                                                           0x00040000L
18122 #define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK                                                          0x00080000L
18123 #define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK                                                         0x00100000L
18124 #define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK                                                           0x00200000L
18125 #define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK                                                         0x00400000L
18126 #define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK                                                           0x00800000L
18127 #define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK                                                       0x01000000L
18128 #define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK                                                         0x04000000L
18129 #define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK                                                 0x08000000L
18130 #define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK                                                           0x20000000L
18131 #define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK                                                           0x40000000L
18132 #define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK                                                           0x80000000L
18133 #define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT                                                             0x1
18134 #define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK                                                               0x00000002L
18135 #define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT                                                            0x1
18136 #define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK                                                              0x00000002L
18137 #define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT                                                            0x1
18138 #define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK                                                              0x00000002L
18139 //CP_PWR_CNTL
18140 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT                                                            0x0
18141 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT                                                            0x1
18142 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT                                                            0x8
18143 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT                                                            0x9
18144 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT                                                            0xa
18145 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT                                                            0xb
18146 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT                                                            0x10
18147 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT                                                            0x11
18148 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT                                                            0x12
18149 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT                                                            0x13
18150 #define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE0__SHIFT                                                            0x14
18151 #define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE1__SHIFT                                                            0x15
18152 #define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE2__SHIFT                                                            0x16
18153 #define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE3__SHIFT                                                            0x17
18154 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK                                                              0x00000001L
18155 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK                                                              0x00000002L
18156 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK                                                              0x00000100L
18157 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK                                                              0x00000200L
18158 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK                                                              0x00000400L
18159 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK                                                              0x00000800L
18160 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK                                                              0x00010000L
18161 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK                                                              0x00020000L
18162 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK                                                              0x00040000L
18163 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK                                                              0x00080000L
18164 #define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE0_MASK                                                              0x00100000L
18165 #define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE1_MASK                                                              0x00200000L
18166 #define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE2_MASK                                                              0x00400000L
18167 #define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE3_MASK                                                              0x00800000L
18168 //CP_MEM_SLP_CNTL
18169 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT                                                                  0x0
18170 #define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT                                                                  0x1
18171 #define CP_MEM_SLP_CNTL__RESERVED__SHIFT                                                                      0x2
18172 #define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT                                                        0x7
18173 #define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT                                                            0x8
18174 #define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT                                                           0x10
18175 #define CP_MEM_SLP_CNTL__RESERVED1__SHIFT                                                                     0x18
18176 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK                                                                    0x00000001L
18177 #define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK                                                                    0x00000002L
18178 #define CP_MEM_SLP_CNTL__RESERVED_MASK                                                                        0x0000007CL
18179 #define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK                                                          0x00000080L
18180 #define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK                                                              0x0000FF00L
18181 #define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK                                                             0x00FF0000L
18182 #define CP_MEM_SLP_CNTL__RESERVED1_MASK                                                                       0xFF000000L
18183 //CP_ECC_FIRSTOCCURRENCE
18184 #define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT                                                              0x0
18185 #define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT                                                                 0x4
18186 #define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT                                                                     0x8
18187 #define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT                                                                   0xa
18188 #define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT                                                                  0xc
18189 #define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT                                                                   0x10
18190 #define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK                                                                0x00000003L
18191 #define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK                                                                   0x000000F0L
18192 #define CP_ECC_FIRSTOCCURRENCE__ME_MASK                                                                       0x00000300L
18193 #define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK                                                                     0x00000C00L
18194 #define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK                                                                    0x00007000L
18195 #define CP_ECC_FIRSTOCCURRENCE__VMID_MASK                                                                     0x000F0000L
18196 //CP_ECC_FIRSTOCCURRENCE_RING0
18197 #define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT                                                         0x0
18198 #define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK                                                           0xFFFFFFFFL
18199 //CP_ECC_FIRSTOCCURRENCE_RING1
18200 #define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT                                                         0x0
18201 #define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK                                                           0xFFFFFFFFL
18202 //CP_ECC_FIRSTOCCURRENCE_RING2
18203 #define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT                                                         0x0
18204 #define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK                                                           0xFFFFFFFFL
18205 //GB_EDC_MODE
18206 #define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT                                                                  0xf
18207 #define GB_EDC_MODE__COUNT_FED_OUT__SHIFT                                                                     0x10
18208 #define GB_EDC_MODE__GATE_FUE__SHIFT                                                                          0x11
18209 #define GB_EDC_MODE__DED_MODE__SHIFT                                                                          0x14
18210 #define GB_EDC_MODE__PROP_FED__SHIFT                                                                          0x1d
18211 #define GB_EDC_MODE__BYPASS__SHIFT                                                                            0x1f
18212 #define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK                                                                    0x00008000L
18213 #define GB_EDC_MODE__COUNT_FED_OUT_MASK                                                                       0x00010000L
18214 #define GB_EDC_MODE__GATE_FUE_MASK                                                                            0x00020000L
18215 #define GB_EDC_MODE__DED_MODE_MASK                                                                            0x00300000L
18216 #define GB_EDC_MODE__PROP_FED_MASK                                                                            0x20000000L
18217 #define GB_EDC_MODE__BYPASS_MASK                                                                              0x80000000L
18218 //CP_FETCHER_SOURCE
18219 #define CP_FETCHER_SOURCE__ME_SRC__SHIFT                                                                      0x0
18220 #define CP_FETCHER_SOURCE__ME_SRC_MASK                                                                        0x00000001L
18221 //CP_PQ_WPTR_POLL_CNTL
18222 #define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT                                                                   0x0
18223 #define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT__SHIFT                                                0x1d
18224 #define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT                                                              0x1e
18225 #define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT                                                                       0x1f
18226 #define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK                                                                     0x000000FFL
18227 #define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT_MASK                                                  0x20000000L
18228 #define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK                                                                0x40000000L
18229 #define CP_PQ_WPTR_POLL_CNTL__EN_MASK                                                                         0x80000000L
18230 //CP_PQ_WPTR_POLL_CNTL1
18231 #define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT                                                              0x0
18232 #define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK                                                                0xFFFFFFFFL
18233 //CP_ME1_PIPE0_INT_CNTL
18234 #define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
18235 #define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
18236 #define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
18237 #define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
18238 #define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
18239 #define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
18240 #define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
18241 #define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
18242 #define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
18243 #define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
18244 #define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
18245 #define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
18246 #define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
18247 #define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
18248 #define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
18249 #define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
18250 #define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
18251 #define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
18252 #define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
18253 #define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
18254 #define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
18255 #define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
18256 #define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
18257 #define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
18258 #define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
18259 #define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
18260 //CP_ME1_PIPE1_INT_CNTL
18261 #define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
18262 #define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
18263 #define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
18264 #define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
18265 #define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
18266 #define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
18267 #define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
18268 #define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
18269 #define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
18270 #define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
18271 #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
18272 #define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
18273 #define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
18274 #define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
18275 #define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
18276 #define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
18277 #define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
18278 #define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
18279 #define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
18280 #define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
18281 #define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
18282 #define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
18283 #define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
18284 #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
18285 #define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
18286 #define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
18287 //CP_ME1_PIPE2_INT_CNTL
18288 #define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
18289 #define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
18290 #define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
18291 #define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
18292 #define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
18293 #define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
18294 #define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
18295 #define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
18296 #define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
18297 #define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
18298 #define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
18299 #define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
18300 #define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
18301 #define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
18302 #define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
18303 #define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
18304 #define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
18305 #define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
18306 #define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
18307 #define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
18308 #define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
18309 #define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
18310 #define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
18311 #define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
18312 #define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
18313 #define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
18314 //CP_ME1_PIPE3_INT_CNTL
18315 #define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
18316 #define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
18317 #define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
18318 #define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
18319 #define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
18320 #define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
18321 #define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
18322 #define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
18323 #define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
18324 #define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
18325 #define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
18326 #define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
18327 #define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
18328 #define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
18329 #define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
18330 #define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
18331 #define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
18332 #define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
18333 #define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
18334 #define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
18335 #define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
18336 #define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
18337 #define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
18338 #define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
18339 #define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
18340 #define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
18341 //CP_ME2_PIPE0_INT_CNTL
18342 #define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
18343 #define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
18344 #define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
18345 #define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
18346 #define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
18347 #define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
18348 #define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
18349 #define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
18350 #define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
18351 #define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
18352 #define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
18353 #define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
18354 #define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
18355 #define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
18356 #define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
18357 #define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
18358 #define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
18359 #define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
18360 #define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
18361 #define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
18362 #define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
18363 #define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
18364 #define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
18365 #define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
18366 #define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
18367 #define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
18368 //CP_ME2_PIPE1_INT_CNTL
18369 #define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
18370 #define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
18371 #define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
18372 #define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
18373 #define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
18374 #define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
18375 #define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
18376 #define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
18377 #define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
18378 #define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
18379 #define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
18380 #define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
18381 #define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
18382 #define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
18383 #define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
18384 #define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
18385 #define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
18386 #define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
18387 #define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
18388 #define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
18389 #define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
18390 #define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
18391 #define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
18392 #define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
18393 #define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
18394 #define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
18395 //CP_ME2_PIPE2_INT_CNTL
18396 #define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
18397 #define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
18398 #define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
18399 #define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
18400 #define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
18401 #define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
18402 #define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
18403 #define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
18404 #define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
18405 #define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
18406 #define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
18407 #define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
18408 #define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
18409 #define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
18410 #define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
18411 #define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
18412 #define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
18413 #define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
18414 #define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
18415 #define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
18416 #define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
18417 #define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
18418 #define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
18419 #define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
18420 #define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
18421 #define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
18422 //CP_ME2_PIPE3_INT_CNTL
18423 #define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
18424 #define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
18425 #define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
18426 #define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
18427 #define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
18428 #define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
18429 #define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
18430 #define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
18431 #define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
18432 #define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
18433 #define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
18434 #define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
18435 #define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
18436 #define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
18437 #define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
18438 #define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
18439 #define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
18440 #define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
18441 #define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
18442 #define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
18443 #define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
18444 #define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
18445 #define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
18446 #define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
18447 #define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
18448 #define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
18449 //CP_ME1_PIPE0_INT_STATUS
18450 #define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
18451 #define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
18452 #define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
18453 #define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
18454 #define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
18455 #define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
18456 #define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
18457 #define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
18458 #define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
18459 #define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
18460 #define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
18461 #define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
18462 #define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
18463 #define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
18464 #define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
18465 #define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
18466 #define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
18467 #define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
18468 #define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
18469 #define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
18470 #define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
18471 #define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
18472 #define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
18473 #define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
18474 #define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
18475 #define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
18476 //CP_ME1_PIPE1_INT_STATUS
18477 #define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
18478 #define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
18479 #define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
18480 #define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
18481 #define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
18482 #define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
18483 #define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
18484 #define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
18485 #define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
18486 #define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
18487 #define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
18488 #define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
18489 #define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
18490 #define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
18491 #define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
18492 #define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
18493 #define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
18494 #define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
18495 #define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
18496 #define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
18497 #define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
18498 #define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
18499 #define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
18500 #define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
18501 #define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
18502 #define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
18503 //CP_ME1_PIPE2_INT_STATUS
18504 #define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
18505 #define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
18506 #define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
18507 #define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
18508 #define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
18509 #define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
18510 #define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
18511 #define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
18512 #define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
18513 #define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
18514 #define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
18515 #define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
18516 #define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
18517 #define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
18518 #define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
18519 #define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
18520 #define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
18521 #define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
18522 #define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
18523 #define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
18524 #define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
18525 #define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
18526 #define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
18527 #define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
18528 #define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
18529 #define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
18530 //CP_ME1_PIPE3_INT_STATUS
18531 #define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
18532 #define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
18533 #define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
18534 #define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
18535 #define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
18536 #define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
18537 #define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
18538 #define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
18539 #define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
18540 #define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
18541 #define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
18542 #define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
18543 #define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
18544 #define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
18545 #define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
18546 #define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
18547 #define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
18548 #define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
18549 #define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
18550 #define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
18551 #define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
18552 #define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
18553 #define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
18554 #define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
18555 #define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
18556 #define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
18557 //CP_ME2_PIPE0_INT_STATUS
18558 #define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
18559 #define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
18560 #define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
18561 #define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
18562 #define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
18563 #define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
18564 #define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
18565 #define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
18566 #define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
18567 #define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
18568 #define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
18569 #define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
18570 #define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
18571 #define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
18572 #define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
18573 #define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
18574 #define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
18575 #define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
18576 #define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
18577 #define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
18578 #define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
18579 #define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
18580 #define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
18581 #define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
18582 #define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
18583 #define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
18584 //CP_ME2_PIPE1_INT_STATUS
18585 #define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
18586 #define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
18587 #define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
18588 #define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
18589 #define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
18590 #define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
18591 #define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
18592 #define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
18593 #define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
18594 #define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
18595 #define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
18596 #define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
18597 #define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
18598 #define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
18599 #define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
18600 #define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
18601 #define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
18602 #define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
18603 #define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
18604 #define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
18605 #define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
18606 #define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
18607 #define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
18608 #define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
18609 #define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
18610 #define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
18611 //CP_ME2_PIPE2_INT_STATUS
18612 #define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
18613 #define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
18614 #define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
18615 #define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
18616 #define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
18617 #define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
18618 #define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
18619 #define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
18620 #define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
18621 #define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
18622 #define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
18623 #define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
18624 #define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
18625 #define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
18626 #define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
18627 #define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
18628 #define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
18629 #define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
18630 #define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
18631 #define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
18632 #define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
18633 #define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
18634 #define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
18635 #define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
18636 #define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
18637 #define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
18638 //CP_ME2_PIPE3_INT_STATUS
18639 #define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
18640 #define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
18641 #define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
18642 #define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
18643 #define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
18644 #define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
18645 #define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
18646 #define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
18647 #define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
18648 #define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
18649 #define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
18650 #define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
18651 #define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
18652 #define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
18653 #define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
18654 #define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
18655 #define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
18656 #define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
18657 #define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
18658 #define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
18659 #define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
18660 #define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
18661 #define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
18662 #define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
18663 #define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
18664 #define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
18665 #define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT                                                   0x17
18666 #define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK                                                     0x00800000L
18667 #define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT                                                   0x17
18668 #define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK                                                     0x00800000L
18669 //CP_GFX_QUEUE_INDEX
18670 #define CP_GFX_QUEUE_INDEX__QUEUE_ACCESS__SHIFT                                                               0x0
18671 #define CP_GFX_QUEUE_INDEX__PIPE_ID__SHIFT                                                                    0x4
18672 #define CP_GFX_QUEUE_INDEX__QUEUE_ID__SHIFT                                                                   0x8
18673 #define CP_GFX_QUEUE_INDEX__QUEUE_ACCESS_MASK                                                                 0x00000001L
18674 #define CP_GFX_QUEUE_INDEX__PIPE_ID_MASK                                                                      0x00000030L
18675 #define CP_GFX_QUEUE_INDEX__QUEUE_ID_MASK                                                                     0x00000700L
18676 //CC_GC_EDC_CONFIG
18677 #define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT                                                                      0x1
18678 #define CC_GC_EDC_CONFIG__DIS_EDC_MASK                                                                        0x00000002L
18679 //CP_ME1_PIPE_PRIORITY_CNTS
18680 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT                                                       0x0
18681 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT                                                      0x8
18682 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT                                                      0x10
18683 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT                                                       0x18
18684 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK                                                         0x000000FFL
18685 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK                                                        0x0000FF00L
18686 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK                                                        0x00FF0000L
18687 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK                                                         0xFF000000L
18688 //CP_ME1_PIPE0_PRIORITY
18689 #define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT                                                                0x0
18690 #define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
18691 //CP_ME1_PIPE1_PRIORITY
18692 #define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT                                                                0x0
18693 #define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
18694 //CP_ME1_PIPE2_PRIORITY
18695 #define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT                                                                0x0
18696 #define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
18697 //CP_ME1_PIPE3_PRIORITY
18698 #define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT                                                                0x0
18699 #define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
18700 //CP_ME2_PIPE_PRIORITY_CNTS
18701 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT                                                       0x0
18702 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT                                                      0x8
18703 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT                                                      0x10
18704 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT                                                       0x18
18705 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK                                                         0x000000FFL
18706 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK                                                        0x0000FF00L
18707 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK                                                        0x00FF0000L
18708 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK                                                         0xFF000000L
18709 //CP_ME2_PIPE0_PRIORITY
18710 #define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT                                                                0x0
18711 #define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
18712 //CP_ME2_PIPE1_PRIORITY
18713 #define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT                                                                0x0
18714 #define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
18715 //CP_ME2_PIPE2_PRIORITY
18716 #define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT                                                                0x0
18717 #define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
18718 //CP_ME2_PIPE3_PRIORITY
18719 #define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT                                                                0x0
18720 #define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
18721 //CP_CE_PRGRM_CNTR_START
18722 #define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT                                                               0x0
18723 #define CP_CE_PRGRM_CNTR_START__IP_START_MASK                                                                 0x000FFFFFL
18724 //CP_PFP_PRGRM_CNTR_START
18725 #define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT                                                              0x0
18726 #define CP_PFP_PRGRM_CNTR_START__IP_START_MASK                                                                0x000FFFFFL
18727 //CP_ME_PRGRM_CNTR_START
18728 #define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT                                                               0x0
18729 #define CP_ME_PRGRM_CNTR_START__IP_START_MASK                                                                 0x000FFFFFL
18730 //CP_MEC1_PRGRM_CNTR_START
18731 #define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT                                                             0x0
18732 #define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK                                                               0x000FFFFFL
18733 //CP_MEC2_PRGRM_CNTR_START
18734 #define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT                                                             0x0
18735 #define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK                                                               0x000FFFFFL
18736 //CP_CE_INTR_ROUTINE_START
18737 #define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT                                                             0x0
18738 #define CP_CE_INTR_ROUTINE_START__IR_START_MASK                                                               0x000FFFFFL
18739 //CP_PFP_INTR_ROUTINE_START
18740 #define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT                                                            0x0
18741 #define CP_PFP_INTR_ROUTINE_START__IR_START_MASK                                                              0x000FFFFFL
18742 //CP_ME_INTR_ROUTINE_START
18743 #define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT                                                             0x0
18744 #define CP_ME_INTR_ROUTINE_START__IR_START_MASK                                                               0x000FFFFFL
18745 //CP_MEC1_INTR_ROUTINE_START
18746 #define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT                                                           0x0
18747 #define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK                                                             0x000FFFFFL
18748 //CP_MEC2_INTR_ROUTINE_START
18749 #define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT                                                           0x0
18750 #define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK                                                             0x000FFFFFL
18751 //CP_CONTEXT_CNTL
18752 #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_GE_CNTX__SHIFT                                                          0x0
18753 #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT                                                        0x4
18754 #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_GE_CNTX__SHIFT                                                          0x10
18755 #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT                                                        0x14
18756 #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_GE_CNTX_MASK                                                            0x00000007L
18757 #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK                                                          0x00000070L
18758 #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_GE_CNTX_MASK                                                            0x00070000L
18759 #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK                                                          0x00700000L
18760 //CP_MAX_CONTEXT
18761 #define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT                                                                    0x0
18762 #define CP_MAX_CONTEXT__MAX_CONTEXT_MASK                                                                      0x00000007L
18763 //CP_IQ_WAIT_TIME1
18764 #define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT                                                                   0x0
18765 #define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT                                                               0x8
18766 #define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT                                                                  0x10
18767 #define CP_IQ_WAIT_TIME1__GWS__SHIFT                                                                          0x18
18768 #define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK                                                                     0x000000FFL
18769 #define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK                                                                 0x0000FF00L
18770 #define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK                                                                    0x00FF0000L
18771 #define CP_IQ_WAIT_TIME1__GWS_MASK                                                                            0xFF000000L
18772 //CP_IQ_WAIT_TIME2
18773 #define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT                                                                    0x0
18774 #define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT                                                                     0x8
18775 #define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT                                                                    0x10
18776 #define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT                                                                    0x18
18777 #define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK                                                                      0x000000FFL
18778 #define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK                                                                       0x0000FF00L
18779 #define CP_IQ_WAIT_TIME2__SEM_REARM_MASK                                                                      0x00FF0000L
18780 #define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK                                                                      0xFF000000L
18781 //CP_RB0_BASE_HI
18782 #define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT                                                                     0x0
18783 #define CP_RB0_BASE_HI__RB_BASE_HI_MASK                                                                       0x000000FFL
18784 //CP_RB1_BASE_HI
18785 #define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT                                                                     0x0
18786 #define CP_RB1_BASE_HI__RB_BASE_HI_MASK                                                                       0x000000FFL
18787 //CP_VMID_RESET
18788 #define CP_VMID_RESET__RESET_REQUEST__SHIFT                                                                   0x0
18789 #define CP_VMID_RESET__PIPE0_QUEUES__SHIFT                                                                    0x10
18790 #define CP_VMID_RESET__PIPE1_QUEUES__SHIFT                                                                    0x18
18791 #define CP_VMID_RESET__RESET_REQUEST_MASK                                                                     0x0000FFFFL
18792 #define CP_VMID_RESET__PIPE0_QUEUES_MASK                                                                      0x00FF0000L
18793 #define CP_VMID_RESET__PIPE1_QUEUES_MASK                                                                      0xFF000000L
18794 //CPC_INT_CNTL
18795 #define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                                      0xc
18796 #define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                                       0xd
18797 #define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                          0xe
18798 #define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                         0xf
18799 #define CPC_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                                   0x10
18800 #define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                                      0x11
18801 #define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                              0x17
18802 #define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                          0x18
18803 #define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                            0x1a
18804 #define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                                    0x1b
18805 #define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                              0x1d
18806 #define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                              0x1e
18807 #define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                              0x1f
18808 #define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                                        0x00001000L
18809 #define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                         0x00002000L
18810 #define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                            0x00004000L
18811 #define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                           0x00008000L
18812 #define CPC_INT_CNTL__GPF_INT_ENABLE_MASK                                                                     0x00010000L
18813 #define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                                        0x00020000L
18814 #define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                                0x00800000L
18815 #define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                            0x01000000L
18816 #define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                              0x04000000L
18817 #define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                                      0x08000000L
18818 #define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                                0x20000000L
18819 #define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                                0x40000000L
18820 #define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                                0x80000000L
18821 //CPC_INT_STATUS
18822 #define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                                    0xc
18823 #define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                                     0xd
18824 #define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                                        0xe
18825 #define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                                       0xf
18826 #define CPC_INT_STATUS__GPF_INT_STATUS__SHIFT                                                                 0x10
18827 #define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                                    0x11
18828 #define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                            0x17
18829 #define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                                        0x18
18830 #define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                          0x1a
18831 #define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                                  0x1b
18832 #define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                            0x1d
18833 #define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                            0x1e
18834 #define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                            0x1f
18835 #define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                                      0x00001000L
18836 #define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                                       0x00002000L
18837 #define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                          0x00004000L
18838 #define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                         0x00008000L
18839 #define CPC_INT_STATUS__GPF_INT_STATUS_MASK                                                                   0x00010000L
18840 #define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                                      0x00020000L
18841 #define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                              0x00800000L
18842 #define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                          0x01000000L
18843 #define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                            0x04000000L
18844 #define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                                    0x08000000L
18845 #define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                              0x20000000L
18846 #define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                              0x40000000L
18847 #define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                              0x80000000L
18848 //CP_VMID_PREEMPT
18849 #define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT                                                               0x0
18850 #define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT                                                                  0x10
18851 #define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK                                                                 0x0000FFFFL
18852 #define CP_VMID_PREEMPT__VIRT_COMMAND_MASK                                                                    0x000F0000L
18853 //CPC_INT_CNTX_ID
18854 #define CPC_INT_CNTX_ID__CNTX_ID__SHIFT                                                                       0x0
18855 #define CPC_INT_CNTX_ID__CNTX_ID_MASK                                                                         0xFFFFFFFFL
18856 //CP_PQ_STATUS
18857 #define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT                                                                 0x0
18858 #define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT                                                                  0x1
18859 #define CP_PQ_STATUS__DOORBELL_UPDATED_EN__SHIFT                                                              0x2
18860 #define CP_PQ_STATUS__DOORBELL_UPDATED_MODE__SHIFT                                                            0x3
18861 #define CP_PQ_STATUS__DOORBELL_UPDATED_MASK                                                                   0x00000001L
18862 #define CP_PQ_STATUS__DOORBELL_ENABLE_MASK                                                                    0x00000002L
18863 #define CP_PQ_STATUS__DOORBELL_UPDATED_EN_MASK                                                                0x00000004L
18864 #define CP_PQ_STATUS__DOORBELL_UPDATED_MODE_MASK                                                              0x00000008L
18865 //CP_CE_CS_PARTITION_INDEX
18866 #define CP_CE_CS_PARTITION_INDEX__CS1_INDEX__SHIFT                                                            0x0
18867 #define CP_CE_CS_PARTITION_INDEX__CS1_INDEX_MASK                                                              0x0001FFFFL
18868 //CP_MEC1_F32_INT_DIS
18869 #define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT                                                           0x0
18870 #define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT                                                              0x1
18871 #define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT                                                      0x2
18872 #define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT                                                            0x3
18873 #define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT                                                           0x4
18874 #define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT                                                       0x5
18875 #define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT                                                          0x6
18876 #define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT                                                         0x7
18877 #define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT                                                           0x8
18878 #define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT                                                              0x9
18879 #define CP_MEC1_F32_INT_DIS__GPF_INT_CPF__SHIFT                                                               0xa
18880 #define CP_MEC1_F32_INT_DIS__GPF_INT_DMA__SHIFT                                                               0xb
18881 #define CP_MEC1_F32_INT_DIS__GPF_INT_CPC__SHIFT                                                               0xc
18882 #define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT                                                        0xd
18883 #define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT                                                         0xe
18884 #define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT                                                       0xf
18885 #define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK                                                             0x00000001L
18886 #define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK                                                                0x00000002L
18887 #define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK                                                        0x00000004L
18888 #define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK                                                              0x00000008L
18889 #define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK                                                             0x00000010L
18890 #define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK                                                         0x00000020L
18891 #define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK                                                            0x00000040L
18892 #define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK                                                           0x00000080L
18893 #define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK                                                             0x00000100L
18894 #define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK                                                                0x00000200L
18895 #define CP_MEC1_F32_INT_DIS__GPF_INT_CPF_MASK                                                                 0x00000400L
18896 #define CP_MEC1_F32_INT_DIS__GPF_INT_DMA_MASK                                                                 0x00000800L
18897 #define CP_MEC1_F32_INT_DIS__GPF_INT_CPC_MASK                                                                 0x00001000L
18898 #define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK                                                          0x00002000L
18899 #define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK                                                           0x00004000L
18900 #define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK                                                         0x00008000L
18901 //CP_MEC2_F32_INT_DIS
18902 #define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT                                                           0x0
18903 #define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT                                                              0x1
18904 #define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT                                                      0x2
18905 #define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT                                                            0x3
18906 #define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT                                                           0x4
18907 #define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT                                                       0x5
18908 #define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT                                                          0x6
18909 #define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT                                                         0x7
18910 #define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT                                                           0x8
18911 #define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT                                                              0x9
18912 #define CP_MEC2_F32_INT_DIS__GPF_INT_CPF__SHIFT                                                               0xa
18913 #define CP_MEC2_F32_INT_DIS__GPF_INT_DMA__SHIFT                                                               0xb
18914 #define CP_MEC2_F32_INT_DIS__GPF_INT_CPC__SHIFT                                                               0xc
18915 #define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT                                                        0xd
18916 #define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT                                                         0xe
18917 #define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT                                                       0xf
18918 #define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK                                                             0x00000001L
18919 #define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK                                                                0x00000002L
18920 #define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK                                                        0x00000004L
18921 #define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK                                                              0x00000008L
18922 #define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK                                                             0x00000010L
18923 #define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK                                                         0x00000020L
18924 #define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK                                                            0x00000040L
18925 #define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK                                                           0x00000080L
18926 #define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK                                                             0x00000100L
18927 #define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK                                                                0x00000200L
18928 #define CP_MEC2_F32_INT_DIS__GPF_INT_CPF_MASK                                                                 0x00000400L
18929 #define CP_MEC2_F32_INT_DIS__GPF_INT_DMA_MASK                                                                 0x00000800L
18930 #define CP_MEC2_F32_INT_DIS__GPF_INT_CPC_MASK                                                                 0x00001000L
18931 #define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK                                                          0x00002000L
18932 #define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK                                                           0x00004000L
18933 #define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK                                                         0x00008000L
18934 //CP_VMID_STATUS
18935 #define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT                                                              0x0
18936 #define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT                                                              0x10
18937 #define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK                                                                0x0000FFFFL
18938 #define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK                                                                0xFFFF0000L
18939 //CPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO
18940 #define CPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT                                                        0xc
18941 #define CPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK                                                          0xFFFFF000L
18942 //CPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI
18943 #define CPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT                                                     0x0
18944 #define CPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK                                                       0x0000FFFFL
18945 //CPC_SUSPEND_CTX_SAVE_CONTROL
18946 #define CPC_SUSPEND_CTX_SAVE_CONTROL__POLICY__SHIFT                                                           0x3
18947 #define CPC_SUSPEND_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT                                                      0x17
18948 #define CPC_SUSPEND_CTX_SAVE_CONTROL__POLICY_MASK                                                             0x00000018L
18949 #define CPC_SUSPEND_CTX_SAVE_CONTROL__EXE_DISABLE_MASK                                                        0x00800000L
18950 //CPC_SUSPEND_CNTL_STACK_OFFSET
18951 #define CPC_SUSPEND_CNTL_STACK_OFFSET__OFFSET__SHIFT                                                          0x2
18952 #define CPC_SUSPEND_CNTL_STACK_OFFSET__OFFSET_MASK                                                            0x00007FFCL
18953 //CPC_SUSPEND_CNTL_STACK_SIZE
18954 #define CPC_SUSPEND_CNTL_STACK_SIZE__SIZE__SHIFT                                                              0xc
18955 #define CPC_SUSPEND_CNTL_STACK_SIZE__SIZE_MASK                                                                0x00007000L
18956 //CPC_SUSPEND_WG_STATE_OFFSET
18957 #define CPC_SUSPEND_WG_STATE_OFFSET__OFFSET__SHIFT                                                            0x2
18958 #define CPC_SUSPEND_WG_STATE_OFFSET__OFFSET_MASK                                                              0x01FFFFFCL
18959 //CPC_SUSPEND_CTX_SAVE_SIZE
18960 #define CPC_SUSPEND_CTX_SAVE_SIZE__SIZE__SHIFT                                                                0xc
18961 #define CPC_SUSPEND_CTX_SAVE_SIZE__SIZE_MASK                                                                  0x01FFF000L
18962 //CPC_OS_PIPES
18963 #define CPC_OS_PIPES__OS_PIPES__SHIFT                                                                         0x0
18964 #define CPC_OS_PIPES__OS_PIPES_MASK                                                                           0x000000FFL
18965 //CP_SUSPEND_RESUME_REQ
18966 #define CP_SUSPEND_RESUME_REQ__SUSPEND_REQ__SHIFT                                                             0x0
18967 #define CP_SUSPEND_RESUME_REQ__RESUME_REQ__SHIFT                                                              0x1
18968 #define CP_SUSPEND_RESUME_REQ__SUSPEND_REQ_MASK                                                               0x00000001L
18969 #define CP_SUSPEND_RESUME_REQ__RESUME_REQ_MASK                                                                0x00000002L
18970 //CP_SUSPEND_CNTL
18971 #define CP_SUSPEND_CNTL__SUSPEND_MODE__SHIFT                                                                  0x0
18972 #define CP_SUSPEND_CNTL__SUSPEND_ENABLE__SHIFT                                                                0x1
18973 #define CP_SUSPEND_CNTL__RESUME_LOCK__SHIFT                                                                   0x2
18974 #define CP_SUSPEND_CNTL__ACE_SUSPEND_ACTIVE__SHIFT                                                            0x3
18975 #define CP_SUSPEND_CNTL__SUSPEND_MODE_MASK                                                                    0x00000001L
18976 #define CP_SUSPEND_CNTL__SUSPEND_ENABLE_MASK                                                                  0x00000002L
18977 #define CP_SUSPEND_CNTL__RESUME_LOCK_MASK                                                                     0x00000004L
18978 #define CP_SUSPEND_CNTL__ACE_SUSPEND_ACTIVE_MASK                                                              0x00000008L
18979 //CP_IQ_WAIT_TIME3
18980 #define CP_IQ_WAIT_TIME3__SUSPEND_QUE__SHIFT                                                                  0x0
18981 #define CP_IQ_WAIT_TIME3__SUSPEND_QUE_MASK                                                                    0x000000FFL
18982 //CPC_DDID_BASE_ADDR_LO
18983 #define CPC_DDID_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT                                                            0x6
18984 #define CPC_DDID_BASE_ADDR_LO__BASE_ADDR_LO_MASK                                                              0xFFFFFFC0L
18985 //CP_DDID_BASE_ADDR_LO
18986 #define CP_DDID_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT                                                             0x6
18987 #define CP_DDID_BASE_ADDR_LO__BASE_ADDR_LO_MASK                                                               0xFFFFFFC0L
18988 //CPC_DDID_BASE_ADDR_HI
18989 #define CPC_DDID_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT                                                            0x0
18990 #define CPC_DDID_BASE_ADDR_HI__BASE_ADDR_HI_MASK                                                              0x0000FFFFL
18991 //CP_DDID_BASE_ADDR_HI
18992 #define CP_DDID_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT                                                             0x0
18993 #define CP_DDID_BASE_ADDR_HI__BASE_ADDR_HI_MASK                                                               0x0000FFFFL
18994 //CPC_DDID_CNTL
18995 #define CPC_DDID_CNTL__THRESHOLD__SHIFT                                                                       0x0
18996 #define CPC_DDID_CNTL__SIZE__SHIFT                                                                            0x10
18997 #define CPC_DDID_CNTL__POLICY__SHIFT                                                                          0x1c
18998 #define CPC_DDID_CNTL__MODE__SHIFT                                                                            0x1e
18999 #define CPC_DDID_CNTL__ENABLE__SHIFT                                                                          0x1f
19000 #define CPC_DDID_CNTL__THRESHOLD_MASK                                                                         0x000000FFL
19001 #define CPC_DDID_CNTL__SIZE_MASK                                                                              0x00010000L
19002 #define CPC_DDID_CNTL__POLICY_MASK                                                                            0x30000000L
19003 #define CPC_DDID_CNTL__MODE_MASK                                                                              0x40000000L
19004 #define CPC_DDID_CNTL__ENABLE_MASK                                                                            0x80000000L
19005 //CP_DDID_CNTL
19006 #define CP_DDID_CNTL__THRESHOLD__SHIFT                                                                        0x0
19007 #define CP_DDID_CNTL__SIZE__SHIFT                                                                             0x10
19008 #define CP_DDID_CNTL__VMID__SHIFT                                                                             0x14
19009 #define CP_DDID_CNTL__VMID_SEL__SHIFT                                                                         0x18
19010 #define CP_DDID_CNTL__POLICY__SHIFT                                                                           0x1c
19011 #define CP_DDID_CNTL__MODE__SHIFT                                                                             0x1e
19012 #define CP_DDID_CNTL__ENABLE__SHIFT                                                                           0x1f
19013 #define CP_DDID_CNTL__THRESHOLD_MASK                                                                          0x000000FFL
19014 #define CP_DDID_CNTL__SIZE_MASK                                                                               0x00010000L
19015 #define CP_DDID_CNTL__VMID_MASK                                                                               0x00F00000L
19016 #define CP_DDID_CNTL__VMID_SEL_MASK                                                                           0x01000000L
19017 #define CP_DDID_CNTL__POLICY_MASK                                                                             0x30000000L
19018 #define CP_DDID_CNTL__MODE_MASK                                                                               0x40000000L
19019 #define CP_DDID_CNTL__ENABLE_MASK                                                                             0x80000000L
19020 //CP_GFX_DDID_INFLIGHT_COUNT
19021 #define CP_GFX_DDID_INFLIGHT_COUNT__COUNT__SHIFT                                                              0x0
19022 #define CP_GFX_DDID_INFLIGHT_COUNT__COUNT_MASK                                                                0x0000FFFFL
19023 //CP_GFX_DDID_WPTR
19024 #define CP_GFX_DDID_WPTR__COUNT__SHIFT                                                                        0x0
19025 #define CP_GFX_DDID_WPTR__COUNT_MASK                                                                          0x0000FFFFL
19026 //CP_GFX_DDID_RPTR
19027 #define CP_GFX_DDID_RPTR__COUNT__SHIFT                                                                        0x0
19028 #define CP_GFX_DDID_RPTR__COUNT_MASK                                                                          0x0000FFFFL
19029 //CP_GFX_DDID_DELTA_RPT_COUNT
19030 #define CP_GFX_DDID_DELTA_RPT_COUNT__COUNT__SHIFT                                                             0x0
19031 #define CP_GFX_DDID_DELTA_RPT_COUNT__COUNT_MASK                                                               0x000000FFL
19032 //CP_GFX_HPD_STATUS0
19033 #define CP_GFX_HPD_STATUS0__QUEUE_STATE__SHIFT                                                                0x0
19034 #define CP_GFX_HPD_STATUS0__MAPPED_QUEUE__SHIFT                                                               0x5
19035 #define CP_GFX_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT                                                            0x8
19036 #define CP_GFX_HPD_STATUS0__FORCE_MAPPED_QUEUE__SHIFT                                                         0x10
19037 #define CP_GFX_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT                                                          0x14
19038 #define CP_GFX_HPD_STATUS0__SUSPEND_REQ__SHIFT                                                                0x1c
19039 #define CP_GFX_HPD_STATUS0__ENABLE_OVERIDE_QUEUEID__SHIFT                                                     0x1d
19040 #define CP_GFX_HPD_STATUS0__OVERIDE_QUEUEID__SHIFT                                                            0x1e
19041 #define CP_GFX_HPD_STATUS0__FORCE_QUEUE__SHIFT                                                                0x1f
19042 #define CP_GFX_HPD_STATUS0__QUEUE_STATE_MASK                                                                  0x0000001FL
19043 #define CP_GFX_HPD_STATUS0__MAPPED_QUEUE_MASK                                                                 0x000000E0L
19044 #define CP_GFX_HPD_STATUS0__QUEUE_AVAILABLE_MASK                                                              0x0000FF00L
19045 #define CP_GFX_HPD_STATUS0__FORCE_MAPPED_QUEUE_MASK                                                           0x00070000L
19046 #define CP_GFX_HPD_STATUS0__FORCE_QUEUE_STATE_MASK                                                            0x01F00000L
19047 #define CP_GFX_HPD_STATUS0__SUSPEND_REQ_MASK                                                                  0x10000000L
19048 #define CP_GFX_HPD_STATUS0__ENABLE_OVERIDE_QUEUEID_MASK                                                       0x20000000L
19049 #define CP_GFX_HPD_STATUS0__OVERIDE_QUEUEID_MASK                                                              0x40000000L
19050 #define CP_GFX_HPD_STATUS0__FORCE_QUEUE_MASK                                                                  0x80000000L
19051 //CP_GFX_HPD_CONTROL0
19052 #define CP_GFX_HPD_CONTROL0__SUSPEND_ENABLE__SHIFT                                                            0x0
19053 #define CP_GFX_HPD_CONTROL0__PIPE_HOLDING__SHIFT                                                              0x4
19054 #define CP_GFX_HPD_CONTROL0__SUSPEND_ENABLE_MASK                                                              0x00000001L
19055 #define CP_GFX_HPD_CONTROL0__PIPE_HOLDING_MASK                                                                0x00000010L
19056 //CP_GFX_HPD_OSPRE_FENCE_ADDR_LO
19057 #define CP_GFX_HPD_OSPRE_FENCE_ADDR_LO__ADDR_LO__SHIFT                                                        0x2
19058 #define CP_GFX_HPD_OSPRE_FENCE_ADDR_LO__ADDR_LO_MASK                                                          0xFFFFFFFCL
19059 //CP_GFX_HPD_OSPRE_FENCE_ADDR_HI
19060 #define CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__ADDR_HI__SHIFT                                                        0x0
19061 #define CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__RSVD__SHIFT                                                           0x10
19062 #define CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__ADDR_HI_MASK                                                          0x0000FFFFL
19063 #define CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__RSVD_MASK                                                             0xFFFF0000L
19064 //CP_GFX_HPD_OSPRE_FENCE_DATA_LO
19065 #define CP_GFX_HPD_OSPRE_FENCE_DATA_LO__DATA_LO__SHIFT                                                        0x0
19066 #define CP_GFX_HPD_OSPRE_FENCE_DATA_LO__DATA_LO_MASK                                                          0xFFFFFFFFL
19067 //CP_GFX_HPD_OSPRE_FENCE_DATA_HI
19068 #define CP_GFX_HPD_OSPRE_FENCE_DATA_HI__DATA_HI__SHIFT                                                        0x0
19069 #define CP_GFX_HPD_OSPRE_FENCE_DATA_HI__DATA_HI_MASK                                                          0xFFFFFFFFL
19070 //CP_GFX_INDEX_MUTEX
19071 #define CP_GFX_INDEX_MUTEX__REQUEST__SHIFT                                                                    0x0
19072 #define CP_GFX_INDEX_MUTEX__CLIENTID__SHIFT                                                                   0x1
19073 #define CP_GFX_INDEX_MUTEX__REQUEST_MASK                                                                      0x00000001L
19074 #define CP_GFX_INDEX_MUTEX__CLIENTID_MASK                                                                     0x0000000EL
19075 //CP_GFX_MQD_BASE_ADDR
19076 #define CP_GFX_MQD_BASE_ADDR__BASE_ADDR__SHIFT                                                                0x2
19077 #define CP_GFX_MQD_BASE_ADDR__BASE_ADDR_MASK                                                                  0xFFFFFFFCL
19078 //CP_GFX_MQD_BASE_ADDR_HI
19079 #define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT                                                          0x0
19080 #define CP_GFX_MQD_BASE_ADDR_HI__APP_VMID__SHIFT                                                              0x1c
19081 #define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK                                                            0x0000FFFFL
19082 #define CP_GFX_MQD_BASE_ADDR_HI__APP_VMID_MASK                                                                0xF0000000L
19083 //CP_GFX_HQD_ACTIVE
19084 #define CP_GFX_HQD_ACTIVE__ACTIVE__SHIFT                                                                      0x0
19085 #define CP_GFX_HQD_ACTIVE__ACTIVE_MASK                                                                        0x00000001L
19086 //CP_GFX_HQD_VMID
19087 #define CP_GFX_HQD_VMID__VMID__SHIFT                                                                          0x0
19088 #define CP_GFX_HQD_VMID__VMID_MASK                                                                            0x0000000FL
19089 //CP_GFX_HQD_QUEUE_PRIORITY
19090 #define CP_GFX_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT                                                      0x0
19091 #define CP_GFX_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK                                                        0x0000000FL
19092 //CP_GFX_HQD_QUANTUM
19093 #define CP_GFX_HQD_QUANTUM__QUANTUM_EN__SHIFT                                                                 0x0
19094 #define CP_GFX_HQD_QUANTUM__QUANTUM_SCALE__SHIFT                                                              0x3
19095 #define CP_GFX_HQD_QUANTUM__QUANTUM_DURATION__SHIFT                                                           0x8
19096 #define CP_GFX_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT                                                             0x1f
19097 #define CP_GFX_HQD_QUANTUM__QUANTUM_EN_MASK                                                                   0x00000001L
19098 #define CP_GFX_HQD_QUANTUM__QUANTUM_SCALE_MASK                                                                0x00000018L
19099 #define CP_GFX_HQD_QUANTUM__QUANTUM_DURATION_MASK                                                             0x0000FF00L
19100 #define CP_GFX_HQD_QUANTUM__QUANTUM_ACTIVE_MASK                                                               0x80000000L
19101 //CP_GFX_HQD_BASE
19102 #define CP_GFX_HQD_BASE__RB_BASE__SHIFT                                                                       0x0
19103 #define CP_GFX_HQD_BASE__RB_BASE_MASK                                                                         0xFFFFFFFFL
19104 //CP_GFX_HQD_BASE_HI
19105 #define CP_GFX_HQD_BASE_HI__RB_BASE_HI__SHIFT                                                                 0x0
19106 #define CP_GFX_HQD_BASE_HI__RB_BASE_HI_MASK                                                                   0x000000FFL
19107 //CP_GFX_HQD_RPTR
19108 #define CP_GFX_HQD_RPTR__RB_RPTR__SHIFT                                                                       0x0
19109 #define CP_GFX_HQD_RPTR__RB_RPTR_MASK                                                                         0x000FFFFFL
19110 //CP_GFX_HQD_RPTR_ADDR
19111 #define CP_GFX_HQD_RPTR_ADDR__RB_RPTR_ADDR__SHIFT                                                             0x2
19112 #define CP_GFX_HQD_RPTR_ADDR__RB_RPTR_ADDR_MASK                                                               0xFFFFFFFCL
19113 //CP_GFX_HQD_RPTR_ADDR_HI
19114 #define CP_GFX_HQD_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT                                                       0x0
19115 #define CP_GFX_HQD_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK                                                         0x0000FFFFL
19116 //CP_RB_WPTR_POLL_ADDR_LO
19117 #define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT                                                  0x2
19118 #define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK                                                    0xFFFFFFFCL
19119 //CP_RB_WPTR_POLL_ADDR_HI
19120 #define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT                                                  0x0
19121 #define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK                                                    0x0000FFFFL
19122 //CP_RB_DOORBELL_CONTROL
19123 #define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT                                                      0x1
19124 #define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT                                                        0x2
19125 #define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT                                                            0x1e
19126 #define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT                                                           0x1f
19127 #define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK                                                        0x00000002L
19128 #define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK                                                          0x0FFFFFFCL
19129 #define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK                                                              0x40000000L
19130 #define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK                                                             0x80000000L
19131 //CP_GFX_HQD_OFFSET
19132 #define CP_GFX_HQD_OFFSET__RB_OFFSET__SHIFT                                                                   0x0
19133 #define CP_GFX_HQD_OFFSET__DISABLE_RB_OFFSET__SHIFT                                                           0x1f
19134 #define CP_GFX_HQD_OFFSET__RB_OFFSET_MASK                                                                     0x000FFFFFL
19135 #define CP_GFX_HQD_OFFSET__DISABLE_RB_OFFSET_MASK                                                             0x80000000L
19136 //CP_GFX_HQD_CNTL
19137 #define CP_GFX_HQD_CNTL__RB_BUFSZ__SHIFT                                                                      0x0
19138 #define CP_GFX_HQD_CNTL__RB_BLKSZ__SHIFT                                                                      0x8
19139 #define CP_GFX_HQD_CNTL__BUF_SWAP__SHIFT                                                                      0x10
19140 #define CP_GFX_HQD_CNTL__MIN_AVAILSZ__SHIFT                                                                   0x14
19141 #define CP_GFX_HQD_CNTL__MIN_IB_AVAILSZ__SHIFT                                                                0x16
19142 #define CP_GFX_HQD_CNTL__CACHE_POLICY__SHIFT                                                                  0x18
19143 #define CP_GFX_HQD_CNTL__RB_VOLATILE__SHIFT                                                                   0x1a
19144 #define CP_GFX_HQD_CNTL__RB_NO_UPDATE__SHIFT                                                                  0x1b
19145 #define CP_GFX_HQD_CNTL__RB_EXE__SHIFT                                                                        0x1c
19146 #define CP_GFX_HQD_CNTL__KMD_QUEUE__SHIFT                                                                     0x1d
19147 #define CP_GFX_HQD_CNTL__CE_HQD_NEQ_RB_HQD__SHIFT                                                             0x1e
19148 #define CP_GFX_HQD_CNTL__RB_RPTR_WR_ENA__SHIFT                                                                0x1f
19149 #define CP_GFX_HQD_CNTL__RB_BUFSZ_MASK                                                                        0x0000003FL
19150 #define CP_GFX_HQD_CNTL__RB_BLKSZ_MASK                                                                        0x00003F00L
19151 #define CP_GFX_HQD_CNTL__BUF_SWAP_MASK                                                                        0x00030000L
19152 #define CP_GFX_HQD_CNTL__MIN_AVAILSZ_MASK                                                                     0x00300000L
19153 #define CP_GFX_HQD_CNTL__MIN_IB_AVAILSZ_MASK                                                                  0x00C00000L
19154 #define CP_GFX_HQD_CNTL__CACHE_POLICY_MASK                                                                    0x03000000L
19155 #define CP_GFX_HQD_CNTL__RB_VOLATILE_MASK                                                                     0x04000000L
19156 #define CP_GFX_HQD_CNTL__RB_NO_UPDATE_MASK                                                                    0x08000000L
19157 #define CP_GFX_HQD_CNTL__RB_EXE_MASK                                                                          0x10000000L
19158 #define CP_GFX_HQD_CNTL__KMD_QUEUE_MASK                                                                       0x20000000L
19159 #define CP_GFX_HQD_CNTL__CE_HQD_NEQ_RB_HQD_MASK                                                               0x40000000L
19160 #define CP_GFX_HQD_CNTL__RB_RPTR_WR_ENA_MASK                                                                  0x80000000L
19161 //CP_GFX_HQD_CSMD_RPTR
19162 #define CP_GFX_HQD_CSMD_RPTR__RB_RPTR__SHIFT                                                                  0x0
19163 #define CP_GFX_HQD_CSMD_RPTR__RB_RPTR_MASK                                                                    0x000FFFFFL
19164 //CP_GFX_HQD_WPTR
19165 #define CP_GFX_HQD_WPTR__RB_WPTR__SHIFT                                                                       0x0
19166 #define CP_GFX_HQD_WPTR__RB_WPTR_MASK                                                                         0xFFFFFFFFL
19167 //CP_GFX_HQD_WPTR_HI
19168 #define CP_GFX_HQD_WPTR_HI__RB_WPTR__SHIFT                                                                    0x0
19169 #define CP_GFX_HQD_WPTR_HI__RB_WPTR_MASK                                                                      0xFFFFFFFFL
19170 //CP_GFX_HQD_DEQUEUE_REQUEST
19171 #define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT                                                        0x0
19172 #define CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT                                                        0x4
19173 #define CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT                                                     0x9
19174 #define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT                                                     0xa
19175 #define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK                                                          0x00000001L
19176 #define CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK                                                          0x00000010L
19177 #define CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK                                                       0x00000200L
19178 #define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK                                                       0x00000400L
19179 //CP_GFX_HQD_MAPPED
19180 #define CP_GFX_HQD_MAPPED__MAPPED__SHIFT                                                                      0x0
19181 #define CP_GFX_HQD_MAPPED__MAPPED_MASK                                                                        0x00000001L
19182 //CP_GFX_HQD_QUE_MGR_CONTROL
19183 #define CP_GFX_HQD_QUE_MGR_CONTROL__CONTROL__SHIFT                                                            0x0
19184 #define CP_GFX_HQD_QUE_MGR_CONTROL__CONTROL_MASK                                                              0x00FFFFFFL
19185 //CP_GFX_HQD_HQ_STATUS0
19186 #define CP_GFX_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT                                                          0x0
19187 #define CP_GFX_HQD_HQ_STATUS0__OS_PREEMPT_STATUS__SHIFT                                                       0x4
19188 #define CP_GFX_HQD_HQ_STATUS0__PREEMPT_ACK__SHIFT                                                             0x6
19189 #define CP_GFX_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT                                                              0x1e
19190 #define CP_GFX_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK                                                            0x00000001L
19191 #define CP_GFX_HQD_HQ_STATUS0__OS_PREEMPT_STATUS_MASK                                                         0x00000030L
19192 #define CP_GFX_HQD_HQ_STATUS0__PREEMPT_ACK_MASK                                                               0x00000040L
19193 #define CP_GFX_HQD_HQ_STATUS0__QUEUE_IDLE_MASK                                                                0x40000000L
19194 //CP_GFX_HQD_HQ_CONTROL0
19195 #define CP_GFX_HQD_HQ_CONTROL0__COMMAND__SHIFT                                                                0x0
19196 #define CP_GFX_HQD_HQ_CONTROL0__COMMAND_MASK                                                                  0x0000000FL
19197 //CP_GFX_MQD_CONTROL
19198 #define CP_GFX_MQD_CONTROL__VMID__SHIFT                                                                       0x0
19199 #define CP_GFX_MQD_CONTROL__PRIV_STATE__SHIFT                                                                 0x8
19200 #define CP_GFX_MQD_CONTROL__PROCESSING_MQD__SHIFT                                                             0xc
19201 #define CP_GFX_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT                                                          0xd
19202 #define CP_GFX_MQD_CONTROL__EXE_DISABLE__SHIFT                                                                0x17
19203 #define CP_GFX_MQD_CONTROL__CACHE_POLICY__SHIFT                                                               0x18
19204 #define CP_GFX_MQD_CONTROL__VMID_MASK                                                                         0x0000000FL
19205 #define CP_GFX_MQD_CONTROL__PRIV_STATE_MASK                                                                   0x00000100L
19206 #define CP_GFX_MQD_CONTROL__PROCESSING_MQD_MASK                                                               0x00001000L
19207 #define CP_GFX_MQD_CONTROL__PROCESSING_MQD_EN_MASK                                                            0x00002000L
19208 #define CP_GFX_MQD_CONTROL__EXE_DISABLE_MASK                                                                  0x00800000L
19209 #define CP_GFX_MQD_CONTROL__CACHE_POLICY_MASK                                                                 0x03000000L
19210 //CP_HQD_GFX_CONTROL
19211 #define CP_HQD_GFX_CONTROL__MESSAGE__SHIFT                                                                    0x0
19212 #define CP_HQD_GFX_CONTROL__MISC__SHIFT                                                                       0x4
19213 #define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT                                                          0xf
19214 #define CP_HQD_GFX_CONTROL__MESSAGE_MASK                                                                      0x0000000FL
19215 #define CP_HQD_GFX_CONTROL__MISC_MASK                                                                         0x00007FF0L
19216 #define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN_MASK                                                            0x00008000L
19217 //CP_HQD_GFX_STATUS
19218 #define CP_HQD_GFX_STATUS__STATUS__SHIFT                                                                      0x0
19219 #define CP_HQD_GFX_STATUS__STATUS_MASK                                                                        0x0000FFFFL
19220 //CP_GFX_HQD_CE_RPTR_WR
19221 #define CP_GFX_HQD_CE_RPTR_WR__RB_RPTR_WR__SHIFT                                                              0x0
19222 #define CP_GFX_HQD_CE_RPTR_WR__RB_RPTR_WR_MASK                                                                0x000FFFFFL
19223 //CP_GFX_HQD_CE_BASE
19224 #define CP_GFX_HQD_CE_BASE__RB_BASE__SHIFT                                                                    0x0
19225 #define CP_GFX_HQD_CE_BASE__RB_BASE_MASK                                                                      0xFFFFFFFFL
19226 //CP_GFX_HQD_CE_BASE_HI
19227 #define CP_GFX_HQD_CE_BASE_HI__RB_BASE_HI__SHIFT                                                              0x0
19228 #define CP_GFX_HQD_CE_BASE_HI__RB_BASE_HI_MASK                                                                0x000000FFL
19229 //CP_GFX_HQD_CE_RPTR
19230 #define CP_GFX_HQD_CE_RPTR__RB_RPTR__SHIFT                                                                    0x0
19231 #define CP_GFX_HQD_CE_RPTR__RB_RPTR_MASK                                                                      0x000FFFFFL
19232 //CP_GFX_HQD_CE_RPTR_ADDR
19233 #define CP_GFX_HQD_CE_RPTR_ADDR__RB_RPTR_ADDR__SHIFT                                                          0x2
19234 #define CP_GFX_HQD_CE_RPTR_ADDR__RB_RPTR_ADDR_MASK                                                            0xFFFFFFFCL
19235 //CP_GFX_HQD_CE_RPTR_ADDR_HI
19236 #define CP_GFX_HQD_CE_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT                                                    0x0
19237 #define CP_GFX_HQD_CE_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK                                                      0x0000FFFFL
19238 //CP_GFX_HQD_CE_WPTR_POLL_ADDR_LO
19239 #define CP_GFX_HQD_CE_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT                                          0x2
19240 #define CP_GFX_HQD_CE_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK                                            0xFFFFFFFCL
19241 //CP_GFX_HQD_CE_WPTR_POLL_ADDR_HI
19242 #define CP_GFX_HQD_CE_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT                                          0x0
19243 #define CP_GFX_HQD_CE_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK                                            0x0000FFFFL
19244 //CP_GFX_HQD_CE_OFFSET
19245 #define CP_GFX_HQD_CE_OFFSET__RB_OFFSET__SHIFT                                                                0x0
19246 #define CP_GFX_HQD_CE_OFFSET__DISABLE_RB_OFFSET__SHIFT                                                        0x1f
19247 #define CP_GFX_HQD_CE_OFFSET__RB_OFFSET_MASK                                                                  0x000FFFFFL
19248 #define CP_GFX_HQD_CE_OFFSET__DISABLE_RB_OFFSET_MASK                                                          0x80000000L
19249 //CP_GFX_HQD_CE_CNTL
19250 #define CP_GFX_HQD_CE_CNTL__RB_BUFSZ__SHIFT                                                                   0x0
19251 #define CP_GFX_HQD_CE_CNTL__RB_BLKSZ__SHIFT                                                                   0x8
19252 #define CP_GFX_HQD_CE_CNTL__BUF_SWAP__SHIFT                                                                   0x10
19253 #define CP_GFX_HQD_CE_CNTL__MIN_AVAILSZ__SHIFT                                                                0x14
19254 #define CP_GFX_HQD_CE_CNTL__MIN_IB_AVAILSZ__SHIFT                                                             0x16
19255 #define CP_GFX_HQD_CE_CNTL__CACHE_POLICY__SHIFT                                                               0x18
19256 #define CP_GFX_HQD_CE_CNTL__RB_VOLATILE__SHIFT                                                                0x1a
19257 #define CP_GFX_HQD_CE_CNTL__RB_NO_UPDATE__SHIFT                                                               0x1b
19258 #define CP_GFX_HQD_CE_CNTL__RB_EXE__SHIFT                                                                     0x1c
19259 #define CP_GFX_HQD_CE_CNTL__RB_RPTR_WR_ENA__SHIFT                                                             0x1f
19260 #define CP_GFX_HQD_CE_CNTL__RB_BUFSZ_MASK                                                                     0x0000003FL
19261 #define CP_GFX_HQD_CE_CNTL__RB_BLKSZ_MASK                                                                     0x00003F00L
19262 #define CP_GFX_HQD_CE_CNTL__BUF_SWAP_MASK                                                                     0x00030000L
19263 #define CP_GFX_HQD_CE_CNTL__MIN_AVAILSZ_MASK                                                                  0x00300000L
19264 #define CP_GFX_HQD_CE_CNTL__MIN_IB_AVAILSZ_MASK                                                               0x00C00000L
19265 #define CP_GFX_HQD_CE_CNTL__CACHE_POLICY_MASK                                                                 0x03000000L
19266 #define CP_GFX_HQD_CE_CNTL__RB_VOLATILE_MASK                                                                  0x04000000L
19267 #define CP_GFX_HQD_CE_CNTL__RB_NO_UPDATE_MASK                                                                 0x08000000L
19268 #define CP_GFX_HQD_CE_CNTL__RB_EXE_MASK                                                                       0x10000000L
19269 #define CP_GFX_HQD_CE_CNTL__RB_RPTR_WR_ENA_MASK                                                               0x80000000L
19270 //CP_GFX_HQD_CE_CSMD_RPTR
19271 #define CP_GFX_HQD_CE_CSMD_RPTR__RB_RPTR__SHIFT                                                               0x0
19272 #define CP_GFX_HQD_CE_CSMD_RPTR__RB_RPTR_MASK                                                                 0x000FFFFFL
19273 //CP_GFX_HQD_CE_WPTR
19274 #define CP_GFX_HQD_CE_WPTR__RB_WPTR__SHIFT                                                                    0x0
19275 #define CP_GFX_HQD_CE_WPTR__RB_WPTR_MASK                                                                      0xFFFFFFFFL
19276 //CP_GFX_HQD_CE_WPTR_HI
19277 #define CP_GFX_HQD_CE_WPTR_HI__RB_WPTR__SHIFT                                                                 0x0
19278 #define CP_GFX_HQD_CE_WPTR_HI__RB_WPTR_MASK                                                                   0xFFFFFFFFL
19279 //CP_CE_DOORBELL_CONTROL
19280 #define CP_CE_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT                                                      0x1
19281 #define CP_CE_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT                                                        0x2
19282 #define CP_CE_DOORBELL_CONTROL__DOORBELL_EN__SHIFT                                                            0x1e
19283 #define CP_CE_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT                                                           0x1f
19284 #define CP_CE_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK                                                        0x00000002L
19285 #define CP_CE_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK                                                          0x0FFFFFFCL
19286 #define CP_CE_DOORBELL_CONTROL__DOORBELL_EN_MASK                                                              0x40000000L
19287 #define CP_CE_DOORBELL_CONTROL__DOORBELL_HIT_MASK                                                             0x80000000L
19288 //CP_DMA_WATCH0_ADDR_LO
19289 #define CP_DMA_WATCH0_ADDR_LO__RSVD__SHIFT                                                                    0x0
19290 #define CP_DMA_WATCH0_ADDR_LO__ADDR_LO__SHIFT                                                                 0x7
19291 #define CP_DMA_WATCH0_ADDR_LO__RSVD_MASK                                                                      0x0000007FL
19292 #define CP_DMA_WATCH0_ADDR_LO__ADDR_LO_MASK                                                                   0xFFFFFF80L
19293 //CP_DMA_WATCH0_ADDR_HI
19294 #define CP_DMA_WATCH0_ADDR_HI__ADDR_HI__SHIFT                                                                 0x0
19295 #define CP_DMA_WATCH0_ADDR_HI__RSVD__SHIFT                                                                    0x10
19296 #define CP_DMA_WATCH0_ADDR_HI__ADDR_HI_MASK                                                                   0x0000FFFFL
19297 #define CP_DMA_WATCH0_ADDR_HI__RSVD_MASK                                                                      0xFFFF0000L
19298 //CP_DMA_WATCH0_MASK
19299 #define CP_DMA_WATCH0_MASK__RSVD__SHIFT                                                                       0x0
19300 #define CP_DMA_WATCH0_MASK__MASK__SHIFT                                                                       0x7
19301 #define CP_DMA_WATCH0_MASK__RSVD_MASK                                                                         0x0000007FL
19302 #define CP_DMA_WATCH0_MASK__MASK_MASK                                                                         0xFFFFFF80L
19303 //CP_DMA_WATCH0_CNTL
19304 #define CP_DMA_WATCH0_CNTL__VMID__SHIFT                                                                       0x0
19305 #define CP_DMA_WATCH0_CNTL__RSVD1__SHIFT                                                                      0x4
19306 #define CP_DMA_WATCH0_CNTL__WATCH_READS__SHIFT                                                                0x8
19307 #define CP_DMA_WATCH0_CNTL__WATCH_WRITES__SHIFT                                                               0x9
19308 #define CP_DMA_WATCH0_CNTL__ANY_VMID__SHIFT                                                                   0xa
19309 #define CP_DMA_WATCH0_CNTL__RSVD2__SHIFT                                                                      0xb
19310 #define CP_DMA_WATCH0_CNTL__VMID_MASK                                                                         0x0000000FL
19311 #define CP_DMA_WATCH0_CNTL__RSVD1_MASK                                                                        0x000000F0L
19312 #define CP_DMA_WATCH0_CNTL__WATCH_READS_MASK                                                                  0x00000100L
19313 #define CP_DMA_WATCH0_CNTL__WATCH_WRITES_MASK                                                                 0x00000200L
19314 #define CP_DMA_WATCH0_CNTL__ANY_VMID_MASK                                                                     0x00000400L
19315 #define CP_DMA_WATCH0_CNTL__RSVD2_MASK                                                                        0xFFFFF800L
19316 //CP_DMA_WATCH1_ADDR_LO
19317 #define CP_DMA_WATCH1_ADDR_LO__RSVD__SHIFT                                                                    0x0
19318 #define CP_DMA_WATCH1_ADDR_LO__ADDR_LO__SHIFT                                                                 0x7
19319 #define CP_DMA_WATCH1_ADDR_LO__RSVD_MASK                                                                      0x0000007FL
19320 #define CP_DMA_WATCH1_ADDR_LO__ADDR_LO_MASK                                                                   0xFFFFFF80L
19321 //CP_DMA_WATCH1_ADDR_HI
19322 #define CP_DMA_WATCH1_ADDR_HI__ADDR_HI__SHIFT                                                                 0x0
19323 #define CP_DMA_WATCH1_ADDR_HI__RSVD__SHIFT                                                                    0x10
19324 #define CP_DMA_WATCH1_ADDR_HI__ADDR_HI_MASK                                                                   0x0000FFFFL
19325 #define CP_DMA_WATCH1_ADDR_HI__RSVD_MASK                                                                      0xFFFF0000L
19326 //CP_DMA_WATCH1_MASK
19327 #define CP_DMA_WATCH1_MASK__RSVD__SHIFT                                                                       0x0
19328 #define CP_DMA_WATCH1_MASK__MASK__SHIFT                                                                       0x7
19329 #define CP_DMA_WATCH1_MASK__RSVD_MASK                                                                         0x0000007FL
19330 #define CP_DMA_WATCH1_MASK__MASK_MASK                                                                         0xFFFFFF80L
19331 //CP_DMA_WATCH1_CNTL
19332 #define CP_DMA_WATCH1_CNTL__VMID__SHIFT                                                                       0x0
19333 #define CP_DMA_WATCH1_CNTL__RSVD1__SHIFT                                                                      0x4
19334 #define CP_DMA_WATCH1_CNTL__WATCH_READS__SHIFT                                                                0x8
19335 #define CP_DMA_WATCH1_CNTL__WATCH_WRITES__SHIFT                                                               0x9
19336 #define CP_DMA_WATCH1_CNTL__ANY_VMID__SHIFT                                                                   0xa
19337 #define CP_DMA_WATCH1_CNTL__RSVD2__SHIFT                                                                      0xb
19338 #define CP_DMA_WATCH1_CNTL__VMID_MASK                                                                         0x0000000FL
19339 #define CP_DMA_WATCH1_CNTL__RSVD1_MASK                                                                        0x000000F0L
19340 #define CP_DMA_WATCH1_CNTL__WATCH_READS_MASK                                                                  0x00000100L
19341 #define CP_DMA_WATCH1_CNTL__WATCH_WRITES_MASK                                                                 0x00000200L
19342 #define CP_DMA_WATCH1_CNTL__ANY_VMID_MASK                                                                     0x00000400L
19343 #define CP_DMA_WATCH1_CNTL__RSVD2_MASK                                                                        0xFFFFF800L
19344 //CP_DMA_WATCH2_ADDR_LO
19345 #define CP_DMA_WATCH2_ADDR_LO__RSVD__SHIFT                                                                    0x0
19346 #define CP_DMA_WATCH2_ADDR_LO__ADDR_LO__SHIFT                                                                 0x7
19347 #define CP_DMA_WATCH2_ADDR_LO__RSVD_MASK                                                                      0x0000007FL
19348 #define CP_DMA_WATCH2_ADDR_LO__ADDR_LO_MASK                                                                   0xFFFFFF80L
19349 //CP_DMA_WATCH2_ADDR_HI
19350 #define CP_DMA_WATCH2_ADDR_HI__ADDR_HI__SHIFT                                                                 0x0
19351 #define CP_DMA_WATCH2_ADDR_HI__RSVD__SHIFT                                                                    0x10
19352 #define CP_DMA_WATCH2_ADDR_HI__ADDR_HI_MASK                                                                   0x0000FFFFL
19353 #define CP_DMA_WATCH2_ADDR_HI__RSVD_MASK                                                                      0xFFFF0000L
19354 //CP_DMA_WATCH2_MASK
19355 #define CP_DMA_WATCH2_MASK__RSVD__SHIFT                                                                       0x0
19356 #define CP_DMA_WATCH2_MASK__MASK__SHIFT                                                                       0x7
19357 #define CP_DMA_WATCH2_MASK__RSVD_MASK                                                                         0x0000007FL
19358 #define CP_DMA_WATCH2_MASK__MASK_MASK                                                                         0xFFFFFF80L
19359 //CP_DMA_WATCH2_CNTL
19360 #define CP_DMA_WATCH2_CNTL__VMID__SHIFT                                                                       0x0
19361 #define CP_DMA_WATCH2_CNTL__RSVD1__SHIFT                                                                      0x4
19362 #define CP_DMA_WATCH2_CNTL__WATCH_READS__SHIFT                                                                0x8
19363 #define CP_DMA_WATCH2_CNTL__WATCH_WRITES__SHIFT                                                               0x9
19364 #define CP_DMA_WATCH2_CNTL__ANY_VMID__SHIFT                                                                   0xa
19365 #define CP_DMA_WATCH2_CNTL__RSVD2__SHIFT                                                                      0xb
19366 #define CP_DMA_WATCH2_CNTL__VMID_MASK                                                                         0x0000000FL
19367 #define CP_DMA_WATCH2_CNTL__RSVD1_MASK                                                                        0x000000F0L
19368 #define CP_DMA_WATCH2_CNTL__WATCH_READS_MASK                                                                  0x00000100L
19369 #define CP_DMA_WATCH2_CNTL__WATCH_WRITES_MASK                                                                 0x00000200L
19370 #define CP_DMA_WATCH2_CNTL__ANY_VMID_MASK                                                                     0x00000400L
19371 #define CP_DMA_WATCH2_CNTL__RSVD2_MASK                                                                        0xFFFFF800L
19372 //CP_DMA_WATCH3_ADDR_LO
19373 #define CP_DMA_WATCH3_ADDR_LO__RSVD__SHIFT                                                                    0x0
19374 #define CP_DMA_WATCH3_ADDR_LO__ADDR_LO__SHIFT                                                                 0x7
19375 #define CP_DMA_WATCH3_ADDR_LO__RSVD_MASK                                                                      0x0000007FL
19376 #define CP_DMA_WATCH3_ADDR_LO__ADDR_LO_MASK                                                                   0xFFFFFF80L
19377 //CP_DMA_WATCH3_ADDR_HI
19378 #define CP_DMA_WATCH3_ADDR_HI__ADDR_HI__SHIFT                                                                 0x0
19379 #define CP_DMA_WATCH3_ADDR_HI__RSVD__SHIFT                                                                    0x10
19380 #define CP_DMA_WATCH3_ADDR_HI__ADDR_HI_MASK                                                                   0x0000FFFFL
19381 #define CP_DMA_WATCH3_ADDR_HI__RSVD_MASK                                                                      0xFFFF0000L
19382 //CP_DMA_WATCH3_MASK
19383 #define CP_DMA_WATCH3_MASK__RSVD__SHIFT                                                                       0x0
19384 #define CP_DMA_WATCH3_MASK__MASK__SHIFT                                                                       0x7
19385 #define CP_DMA_WATCH3_MASK__RSVD_MASK                                                                         0x0000007FL
19386 #define CP_DMA_WATCH3_MASK__MASK_MASK                                                                         0xFFFFFF80L
19387 //CP_DMA_WATCH3_CNTL
19388 #define CP_DMA_WATCH3_CNTL__VMID__SHIFT                                                                       0x0
19389 #define CP_DMA_WATCH3_CNTL__RSVD1__SHIFT                                                                      0x4
19390 #define CP_DMA_WATCH3_CNTL__WATCH_READS__SHIFT                                                                0x8
19391 #define CP_DMA_WATCH3_CNTL__WATCH_WRITES__SHIFT                                                               0x9
19392 #define CP_DMA_WATCH3_CNTL__ANY_VMID__SHIFT                                                                   0xa
19393 #define CP_DMA_WATCH3_CNTL__RSVD2__SHIFT                                                                      0xb
19394 #define CP_DMA_WATCH3_CNTL__VMID_MASK                                                                         0x0000000FL
19395 #define CP_DMA_WATCH3_CNTL__RSVD1_MASK                                                                        0x000000F0L
19396 #define CP_DMA_WATCH3_CNTL__WATCH_READS_MASK                                                                  0x00000100L
19397 #define CP_DMA_WATCH3_CNTL__WATCH_WRITES_MASK                                                                 0x00000200L
19398 #define CP_DMA_WATCH3_CNTL__ANY_VMID_MASK                                                                     0x00000400L
19399 #define CP_DMA_WATCH3_CNTL__RSVD2_MASK                                                                        0xFFFFF800L
19400 //CP_DMA_WATCH_STAT_ADDR_LO
19401 #define CP_DMA_WATCH_STAT_ADDR_LO__ADDR_LO__SHIFT                                                             0x2
19402 #define CP_DMA_WATCH_STAT_ADDR_LO__ADDR_LO_MASK                                                               0xFFFFFFFCL
19403 //CP_DMA_WATCH_STAT_ADDR_HI
19404 #define CP_DMA_WATCH_STAT_ADDR_HI__ADDR_HI__SHIFT                                                             0x0
19405 #define CP_DMA_WATCH_STAT_ADDR_HI__ADDR_HI_MASK                                                               0x0000FFFFL
19406 //CP_DMA_WATCH_STAT
19407 #define CP_DMA_WATCH_STAT__VMID__SHIFT                                                                        0x0
19408 #define CP_DMA_WATCH_STAT__CLIENT_ID__SHIFT                                                                   0x8
19409 #define CP_DMA_WATCH_STAT__PIPE__SHIFT                                                                        0xc
19410 #define CP_DMA_WATCH_STAT__WATCH_ID__SHIFT                                                                    0x10
19411 #define CP_DMA_WATCH_STAT__RD_WR__SHIFT                                                                       0x14
19412 #define CP_DMA_WATCH_STAT__TRAP_FLAG__SHIFT                                                                   0x1f
19413 #define CP_DMA_WATCH_STAT__VMID_MASK                                                                          0x0000000FL
19414 #define CP_DMA_WATCH_STAT__CLIENT_ID_MASK                                                                     0x00000700L
19415 #define CP_DMA_WATCH_STAT__PIPE_MASK                                                                          0x00003000L
19416 #define CP_DMA_WATCH_STAT__WATCH_ID_MASK                                                                      0x00030000L
19417 #define CP_DMA_WATCH_STAT__RD_WR_MASK                                                                         0x00100000L
19418 #define CP_DMA_WATCH_STAT__TRAP_FLAG_MASK                                                                     0x80000000L
19419 //CP_PFP_JT_STAT
19420 #define CP_PFP_JT_STAT__JT_LOADED__SHIFT                                                                      0x0
19421 #define CP_PFP_JT_STAT__WR_MASK__SHIFT                                                                        0x10
19422 #define CP_PFP_JT_STAT__JT_LOADED_MASK                                                                        0x00000003L
19423 #define CP_PFP_JT_STAT__WR_MASK_MASK                                                                          0x00030000L
19424 //CP_CE_JT_STAT
19425 #define CP_CE_JT_STAT__JT_LOADED__SHIFT                                                                       0x0
19426 #define CP_CE_JT_STAT__WR_MASK__SHIFT                                                                         0x10
19427 #define CP_CE_JT_STAT__JT_LOADED_MASK                                                                         0x00000003L
19428 #define CP_CE_JT_STAT__WR_MASK_MASK                                                                           0x00030000L
19429 //CP_MEC_JT_STAT
19430 #define CP_MEC_JT_STAT__JT_LOADED__SHIFT                                                                      0x0
19431 #define CP_MEC_JT_STAT__WR_MASK__SHIFT                                                                        0x10
19432 #define CP_MEC_JT_STAT__JT_LOADED_MASK                                                                        0x000000FFL
19433 #define CP_MEC_JT_STAT__WR_MASK_MASK                                                                          0x00FF0000L
19434 //CP_RB_DOORBELL_CLEAR
19435 #define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE__SHIFT                                                             0x0
19436 #define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR__SHIFT                                             0x8
19437 #define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR__SHIFT                                            0x9
19438 #define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR__SHIFT                                                 0xa
19439 #define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR__SHIFT                                                0xb
19440 #define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR__SHIFT                                                 0xc
19441 #define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR__SHIFT                                                0xd
19442 #define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE_MASK                                                               0x00000007L
19443 #define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR_MASK                                               0x00000100L
19444 #define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR_MASK                                              0x00000200L
19445 #define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR_MASK                                                   0x00000400L
19446 #define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR_MASK                                                  0x00000800L
19447 #define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR_MASK                                                   0x00001000L
19448 #define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR_MASK                                                  0x00002000L
19449 //CP_RB0_ACTIVE
19450 #define CP_RB0_ACTIVE__ACTIVE__SHIFT                                                                          0x0
19451 #define CP_RB0_ACTIVE__ACTIVE_MASK                                                                            0x00000001L
19452 //CP_RB_ACTIVE
19453 #define CP_RB_ACTIVE__ACTIVE__SHIFT                                                                           0x0
19454 #define CP_RB_ACTIVE__ACTIVE_MASK                                                                             0x00000001L
19455 //CP_RB1_ACTIVE
19456 #define CP_RB1_ACTIVE__ACTIVE__SHIFT                                                                          0x0
19457 #define CP_RB1_ACTIVE__ACTIVE_MASK                                                                            0x00000001L
19458 //CP_RB_STATUS
19459 #define CP_RB_STATUS__DOORBELL_UPDATED__SHIFT                                                                 0x0
19460 #define CP_RB_STATUS__DOORBELL_ENABLE__SHIFT                                                                  0x1
19461 #define CP_RB_STATUS__DOORBELL_UPDATED_MASK                                                                   0x00000001L
19462 #define CP_RB_STATUS__DOORBELL_ENABLE_MASK                                                                    0x00000002L
19463 //CPG_RCIU_CAM_INDEX
19464 #define CPG_RCIU_CAM_INDEX__INDEX__SHIFT                                                                      0x0
19465 #define CPG_RCIU_CAM_INDEX__INDEX_MASK                                                                        0x0000001FL
19466 //CPG_RCIU_CAM_DATA
19467 #define CPG_RCIU_CAM_DATA__DATA__SHIFT                                                                        0x0
19468 #define CPG_RCIU_CAM_DATA__DATA_MASK                                                                          0xFFFFFFFFL
19469 //CPG_RCIU_CAM_DATA_PHASE0
19470 #define CPG_RCIU_CAM_DATA_PHASE0__ADDR__SHIFT                                                                 0x0
19471 #define CPG_RCIU_CAM_DATA_PHASE0__PIPE0_EN__SHIFT                                                             0x18
19472 #define CPG_RCIU_CAM_DATA_PHASE0__PIPE1_EN__SHIFT                                                             0x19
19473 #define CPG_RCIU_CAM_DATA_PHASE0__SKIP_WR__SHIFT                                                              0x1f
19474 #define CPG_RCIU_CAM_DATA_PHASE0__ADDR_MASK                                                                   0x0003FFFFL
19475 #define CPG_RCIU_CAM_DATA_PHASE0__PIPE0_EN_MASK                                                               0x01000000L
19476 #define CPG_RCIU_CAM_DATA_PHASE0__PIPE1_EN_MASK                                                               0x02000000L
19477 #define CPG_RCIU_CAM_DATA_PHASE0__SKIP_WR_MASK                                                                0x80000000L
19478 //CPG_RCIU_CAM_DATA_PHASE1
19479 #define CPG_RCIU_CAM_DATA_PHASE1__MASK__SHIFT                                                                 0x0
19480 #define CPG_RCIU_CAM_DATA_PHASE1__MASK_MASK                                                                   0xFFFFFFFFL
19481 //CPG_RCIU_CAM_DATA_PHASE2
19482 #define CPG_RCIU_CAM_DATA_PHASE2__VALUE__SHIFT                                                                0x0
19483 #define CPG_RCIU_CAM_DATA_PHASE2__VALUE_MASK                                                                  0xFFFFFFFFL
19484 //CPF_GCR_CNTL
19485 #define CPF_GCR_CNTL__GCR_GL_CMD__SHIFT                                                                       0x0
19486 #define CPF_GCR_CNTL__GCR_GL_CMD_MASK                                                                         0x0007FFFFL
19487 //CPG_UTCL1_STATUS
19488 #define CPG_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                               0x0
19489 #define CPG_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                               0x1
19490 #define CPG_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                 0x2
19491 #define CPG_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT                                                                0x8
19492 #define CPG_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT                                                                0x10
19493 #define CPG_UTCL1_STATUS__PRT_UTCL1ID__SHIFT                                                                  0x18
19494 #define CPG_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                 0x00000001L
19495 #define CPG_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                 0x00000002L
19496 #define CPG_UTCL1_STATUS__PRT_DETECTED_MASK                                                                   0x00000004L
19497 #define CPG_UTCL1_STATUS__FAULT_UTCL1ID_MASK                                                                  0x00003F00L
19498 #define CPG_UTCL1_STATUS__RETRY_UTCL1ID_MASK                                                                  0x003F0000L
19499 #define CPG_UTCL1_STATUS__PRT_UTCL1ID_MASK                                                                    0x3F000000L
19500 //CPC_UTCL1_STATUS
19501 #define CPC_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                               0x0
19502 #define CPC_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                               0x1
19503 #define CPC_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                 0x2
19504 #define CPC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT                                                                0x8
19505 #define CPC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT                                                                0x10
19506 #define CPC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT                                                                  0x18
19507 #define CPC_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                 0x00000001L
19508 #define CPC_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                 0x00000002L
19509 #define CPC_UTCL1_STATUS__PRT_DETECTED_MASK                                                                   0x00000004L
19510 #define CPC_UTCL1_STATUS__FAULT_UTCL1ID_MASK                                                                  0x00003F00L
19511 #define CPC_UTCL1_STATUS__RETRY_UTCL1ID_MASK                                                                  0x003F0000L
19512 #define CPC_UTCL1_STATUS__PRT_UTCL1ID_MASK                                                                    0x3F000000L
19513 //CPF_UTCL1_STATUS
19514 #define CPF_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                               0x0
19515 #define CPF_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                               0x1
19516 #define CPF_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                 0x2
19517 #define CPF_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT                                                                0x8
19518 #define CPF_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT                                                                0x10
19519 #define CPF_UTCL1_STATUS__PRT_UTCL1ID__SHIFT                                                                  0x18
19520 #define CPF_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                 0x00000001L
19521 #define CPF_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                 0x00000002L
19522 #define CPF_UTCL1_STATUS__PRT_DETECTED_MASK                                                                   0x00000004L
19523 #define CPF_UTCL1_STATUS__FAULT_UTCL1ID_MASK                                                                  0x00003F00L
19524 #define CPF_UTCL1_STATUS__RETRY_UTCL1ID_MASK                                                                  0x003F0000L
19525 #define CPF_UTCL1_STATUS__PRT_UTCL1ID_MASK                                                                    0x3F000000L
19526 //CP_SD_CNTL
19527 #define CP_SD_CNTL__CPF_EN__SHIFT                                                                             0x0
19528 #define CP_SD_CNTL__CPG_EN__SHIFT                                                                             0x1
19529 #define CP_SD_CNTL__CPC_EN__SHIFT                                                                             0x2
19530 #define CP_SD_CNTL__RLC_EN__SHIFT                                                                             0x3
19531 #define CP_SD_CNTL__SPI_EN__SHIFT                                                                             0x4
19532 #define CP_SD_CNTL__GE_EN__SHIFT                                                                              0x5
19533 #define CP_SD_CNTL__UTCL1_EN__SHIFT                                                                           0x6
19534 #define CP_SD_CNTL__RMI_EN__SHIFT                                                                             0x8
19535 #define CP_SD_CNTL__EA_EN__SHIFT                                                                              0x9
19536 #define CP_SD_CNTL__SDMA_EN__SHIFT                                                                            0xa
19537 #define CP_SD_CNTL__SD_VMIDVEC_OVERRIDE__SHIFT                                                                0x1f
19538 #define CP_SD_CNTL__CPF_EN_MASK                                                                               0x00000001L
19539 #define CP_SD_CNTL__CPG_EN_MASK                                                                               0x00000002L
19540 #define CP_SD_CNTL__CPC_EN_MASK                                                                               0x00000004L
19541 #define CP_SD_CNTL__RLC_EN_MASK                                                                               0x00000008L
19542 #define CP_SD_CNTL__SPI_EN_MASK                                                                               0x00000010L
19543 #define CP_SD_CNTL__GE_EN_MASK                                                                                0x00000020L
19544 #define CP_SD_CNTL__UTCL1_EN_MASK                                                                             0x00000040L
19545 #define CP_SD_CNTL__RMI_EN_MASK                                                                               0x00000100L
19546 #define CP_SD_CNTL__EA_EN_MASK                                                                                0x00000200L
19547 #define CP_SD_CNTL__SDMA_EN_MASK                                                                              0x00000400L
19548 #define CP_SD_CNTL__SD_VMIDVEC_OVERRIDE_MASK                                                                  0x80000000L
19549 //CP_SOFT_RESET_CNTL
19550 #define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET__SHIFT                                                        0x0
19551 #define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET__SHIFT                                                        0x1
19552 #define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET__SHIFT                                                          0x2
19553 #define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET__SHIFT                                                         0x3
19554 #define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET__SHIFT                                               0x4
19555 #define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET__SHIFT                                                      0x5
19556 #define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET__SHIFT                                                         0x6
19557 #define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET_MASK                                                          0x00000001L
19558 #define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET_MASK                                                          0x00000002L
19559 #define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET_MASK                                                            0x00000004L
19560 #define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET_MASK                                                           0x00000008L
19561 #define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET_MASK                                                 0x00000010L
19562 #define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET_MASK                                                        0x00000020L
19563 #define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET_MASK                                                           0x00000040L
19564 //CP_CPC_GFX_CNTL
19565 #define CP_CPC_GFX_CNTL__QUEUEID__SHIFT                                                                       0x0
19566 #define CP_CPC_GFX_CNTL__PIPEID__SHIFT                                                                        0x3
19567 #define CP_CPC_GFX_CNTL__MEID__SHIFT                                                                          0x5
19568 #define CP_CPC_GFX_CNTL__VALID__SHIFT                                                                         0x7
19569 #define CP_CPC_GFX_CNTL__QUEUEID_MASK                                                                         0x00000007L
19570 #define CP_CPC_GFX_CNTL__PIPEID_MASK                                                                          0x00000018L
19571 #define CP_CPC_GFX_CNTL__MEID_MASK                                                                            0x00000060L
19572 #define CP_CPC_GFX_CNTL__VALID_MASK                                                                           0x00000080L
19573 
19574 
19575 // addressBlock: gc_spipdec
19576 //SPI_ARB_PRIORITY
19577 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT                                                               0x0
19578 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT                                                               0x3
19579 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT                                                               0x6
19580 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT                                                               0x9
19581 #define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT                                                                 0xc
19582 #define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT                                                                 0xe
19583 #define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT                                                                 0x10
19584 #define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT                                                                 0x12
19585 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK                                                                 0x00000007L
19586 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK                                                                 0x00000038L
19587 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK                                                                 0x000001C0L
19588 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK                                                                 0x00000E00L
19589 #define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK                                                                   0x00003000L
19590 #define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK                                                                   0x0000C000L
19591 #define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK                                                                   0x00030000L
19592 #define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK                                                                   0x000C0000L
19593 //SPI_ARB_CYCLES_0
19594 #define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT                                                                 0x0
19595 #define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT                                                                 0x10
19596 #define SPI_ARB_CYCLES_0__TS0_DURATION_MASK                                                                   0x0000FFFFL
19597 #define SPI_ARB_CYCLES_0__TS1_DURATION_MASK                                                                   0xFFFF0000L
19598 //SPI_ARB_CYCLES_1
19599 #define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT                                                                 0x0
19600 #define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT                                                                 0x10
19601 #define SPI_ARB_CYCLES_1__TS2_DURATION_MASK                                                                   0x0000FFFFL
19602 #define SPI_ARB_CYCLES_1__TS3_DURATION_MASK                                                                   0xFFFF0000L
19603 //SPI_WCL_PIPE_PERCENT_GFX
19604 #define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT                                                                0x0
19605 #define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE__SHIFT                                                         0x7
19606 #define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT                                                         0xc
19607 #define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE__SHIFT                                                         0x11
19608 #define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT                                                         0x16
19609 #define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK                                                                  0x0000007FL
19610 #define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE_MASK                                                           0x00000F80L
19611 #define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK                                                           0x0001F000L
19612 #define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE_MASK                                                           0x003E0000L
19613 #define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK                                                           0x07C00000L
19614 //SPI_WCL_PIPE_PERCENT_HP3D
19615 #define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT                                                               0x0
19616 #define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT                                                        0xc
19617 #define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT                                                        0x16
19618 #define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK                                                                 0x0000007FL
19619 #define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK                                                          0x0001F000L
19620 #define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK                                                          0x07C00000L
19621 //SPI_WCL_PIPE_PERCENT_CS0
19622 #define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT                                                                0x0
19623 #define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK                                                                  0x7FL
19624 //SPI_WCL_PIPE_PERCENT_CS1
19625 #define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT                                                                0x0
19626 #define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK                                                                  0x7FL
19627 //SPI_WCL_PIPE_PERCENT_CS2
19628 #define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT                                                                0x0
19629 #define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK                                                                  0x7FL
19630 //SPI_WCL_PIPE_PERCENT_CS3
19631 #define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT                                                                0x0
19632 #define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK                                                                  0x7FL
19633 //SPI_WCL_PIPE_PERCENT_CS4
19634 #define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT                                                                0x0
19635 #define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK                                                                  0x7FL
19636 //SPI_WCL_PIPE_PERCENT_CS5
19637 #define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT                                                                0x0
19638 #define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK                                                                  0x7FL
19639 //SPI_WCL_PIPE_PERCENT_CS6
19640 #define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT                                                                0x0
19641 #define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK                                                                  0x7FL
19642 //SPI_WCL_PIPE_PERCENT_CS7
19643 #define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT                                                                0x0
19644 #define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK                                                                  0x7FL
19645 //SPI_COMPUTE_QUEUE_RESET
19646 #define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT                                                                 0x0
19647 #define SPI_COMPUTE_QUEUE_RESET__RESET_MASK                                                                   0x01L
19648 //SPI_RESOURCE_RESERVE_CU_0
19649 #define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT                                                                0x0
19650 #define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT                                                                0x4
19651 #define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT                                                                 0x8
19652 #define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT                                                               0xc
19653 #define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT                                                            0xf
19654 #define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK                                                                  0x0000000FL
19655 #define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK                                                                  0x000000F0L
19656 #define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK                                                                   0x00000F00L
19657 #define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK                                                                 0x00007000L
19658 #define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK                                                              0x00078000L
19659 //SPI_RESOURCE_RESERVE_CU_1
19660 #define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT                                                                0x0
19661 #define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT                                                                0x4
19662 #define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT                                                                 0x8
19663 #define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT                                                               0xc
19664 #define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT                                                            0xf
19665 #define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK                                                                  0x0000000FL
19666 #define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK                                                                  0x000000F0L
19667 #define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK                                                                   0x00000F00L
19668 #define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK                                                                 0x00007000L
19669 #define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK                                                              0x00078000L
19670 //SPI_RESOURCE_RESERVE_CU_2
19671 #define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT                                                                0x0
19672 #define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT                                                                0x4
19673 #define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT                                                                 0x8
19674 #define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT                                                               0xc
19675 #define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT                                                            0xf
19676 #define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK                                                                  0x0000000FL
19677 #define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK                                                                  0x000000F0L
19678 #define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK                                                                   0x00000F00L
19679 #define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK                                                                 0x00007000L
19680 #define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK                                                              0x00078000L
19681 //SPI_RESOURCE_RESERVE_CU_3
19682 #define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT                                                                0x0
19683 #define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT                                                                0x4
19684 #define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT                                                                 0x8
19685 #define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT                                                               0xc
19686 #define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT                                                            0xf
19687 #define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK                                                                  0x0000000FL
19688 #define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK                                                                  0x000000F0L
19689 #define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK                                                                   0x00000F00L
19690 #define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK                                                                 0x00007000L
19691 #define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK                                                              0x00078000L
19692 //SPI_RESOURCE_RESERVE_CU_4
19693 #define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT                                                                0x0
19694 #define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT                                                                0x4
19695 #define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT                                                                 0x8
19696 #define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT                                                               0xc
19697 #define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT                                                            0xf
19698 #define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK                                                                  0x0000000FL
19699 #define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK                                                                  0x000000F0L
19700 #define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK                                                                   0x00000F00L
19701 #define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK                                                                 0x00007000L
19702 #define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK                                                              0x00078000L
19703 //SPI_RESOURCE_RESERVE_CU_5
19704 #define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT                                                                0x0
19705 #define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT                                                                0x4
19706 #define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT                                                                 0x8
19707 #define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT                                                               0xc
19708 #define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT                                                            0xf
19709 #define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK                                                                  0x0000000FL
19710 #define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK                                                                  0x000000F0L
19711 #define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK                                                                   0x00000F00L
19712 #define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK                                                                 0x00007000L
19713 #define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK                                                              0x00078000L
19714 //SPI_RESOURCE_RESERVE_CU_6
19715 #define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT                                                                0x0
19716 #define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT                                                                0x4
19717 #define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT                                                                 0x8
19718 #define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT                                                               0xc
19719 #define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT                                                            0xf
19720 #define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK                                                                  0x0000000FL
19721 #define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK                                                                  0x000000F0L
19722 #define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK                                                                   0x00000F00L
19723 #define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK                                                                 0x00007000L
19724 #define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK                                                              0x00078000L
19725 //SPI_RESOURCE_RESERVE_CU_7
19726 #define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT                                                                0x0
19727 #define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT                                                                0x4
19728 #define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT                                                                 0x8
19729 #define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT                                                               0xc
19730 #define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT                                                            0xf
19731 #define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK                                                                  0x0000000FL
19732 #define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK                                                                  0x000000F0L
19733 #define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK                                                                   0x00000F00L
19734 #define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK                                                                 0x00007000L
19735 #define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK                                                              0x00078000L
19736 //SPI_RESOURCE_RESERVE_CU_8
19737 #define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT                                                                0x0
19738 #define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT                                                                0x4
19739 #define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT                                                                 0x8
19740 #define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT                                                               0xc
19741 #define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT                                                            0xf
19742 #define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK                                                                  0x0000000FL
19743 #define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK                                                                  0x000000F0L
19744 #define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK                                                                   0x00000F00L
19745 #define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK                                                                 0x00007000L
19746 #define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK                                                              0x00078000L
19747 //SPI_RESOURCE_RESERVE_CU_9
19748 #define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT                                                                0x0
19749 #define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT                                                                0x4
19750 #define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT                                                                 0x8
19751 #define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT                                                               0xc
19752 #define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT                                                            0xf
19753 #define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK                                                                  0x0000000FL
19754 #define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK                                                                  0x000000F0L
19755 #define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK                                                                   0x00000F00L
19756 #define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK                                                                 0x00007000L
19757 #define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK                                                              0x00078000L
19758 //SPI_RESOURCE_RESERVE_EN_CU_0
19759 #define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT                                                               0x0
19760 #define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT                                                        0x1
19761 #define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT                                                       0x10
19762 #define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT                                               0x18
19763 #define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK                                                                 0x00000001L
19764 #define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK                                                          0x0000FFFEL
19765 #define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK                                                         0x00FF0000L
19766 #define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
19767 //SPI_RESOURCE_RESERVE_EN_CU_1
19768 #define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT                                                               0x0
19769 #define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT                                                        0x1
19770 #define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT                                                       0x10
19771 #define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT                                               0x18
19772 #define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK                                                                 0x00000001L
19773 #define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK                                                          0x0000FFFEL
19774 #define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK                                                         0x00FF0000L
19775 #define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
19776 //SPI_RESOURCE_RESERVE_EN_CU_2
19777 #define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT                                                               0x0
19778 #define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT                                                        0x1
19779 #define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT                                                       0x10
19780 #define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT                                               0x18
19781 #define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK                                                                 0x00000001L
19782 #define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK                                                          0x0000FFFEL
19783 #define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK                                                         0x00FF0000L
19784 #define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
19785 //SPI_RESOURCE_RESERVE_EN_CU_3
19786 #define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT                                                               0x0
19787 #define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT                                                        0x1
19788 #define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT                                                       0x10
19789 #define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT                                               0x18
19790 #define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK                                                                 0x00000001L
19791 #define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK                                                          0x0000FFFEL
19792 #define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK                                                         0x00FF0000L
19793 #define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
19794 //SPI_RESOURCE_RESERVE_EN_CU_4
19795 #define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT                                                               0x0
19796 #define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT                                                        0x1
19797 #define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT                                                       0x10
19798 #define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT                                               0x18
19799 #define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK                                                                 0x00000001L
19800 #define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK                                                          0x0000FFFEL
19801 #define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK                                                         0x00FF0000L
19802 #define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
19803 //SPI_RESOURCE_RESERVE_EN_CU_5
19804 #define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT                                                               0x0
19805 #define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT                                                        0x1
19806 #define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT                                                       0x10
19807 #define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT                                               0x18
19808 #define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK                                                                 0x00000001L
19809 #define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK                                                          0x0000FFFEL
19810 #define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK                                                         0x00FF0000L
19811 #define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
19812 //SPI_RESOURCE_RESERVE_EN_CU_6
19813 #define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT                                                               0x0
19814 #define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT                                                        0x1
19815 #define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT                                                       0x10
19816 #define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT                                               0x18
19817 #define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK                                                                 0x00000001L
19818 #define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK                                                          0x0000FFFEL
19819 #define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK                                                         0x00FF0000L
19820 #define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
19821 //SPI_RESOURCE_RESERVE_EN_CU_7
19822 #define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT                                                               0x0
19823 #define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT                                                        0x1
19824 #define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT                                                       0x10
19825 #define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT                                               0x18
19826 #define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK                                                                 0x00000001L
19827 #define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK                                                          0x0000FFFEL
19828 #define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK                                                         0x00FF0000L
19829 #define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
19830 //SPI_RESOURCE_RESERVE_EN_CU_8
19831 #define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT                                                               0x0
19832 #define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT                                                        0x1
19833 #define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT                                                       0x10
19834 #define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT                                               0x18
19835 #define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK                                                                 0x00000001L
19836 #define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK                                                          0x0000FFFEL
19837 #define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK                                                         0x00FF0000L
19838 #define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
19839 //SPI_RESOURCE_RESERVE_EN_CU_9
19840 #define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT                                                               0x0
19841 #define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT                                                        0x1
19842 #define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT                                                       0x10
19843 #define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT                                               0x18
19844 #define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK                                                                 0x00000001L
19845 #define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK                                                          0x0000FFFEL
19846 #define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK                                                         0x00FF0000L
19847 #define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
19848 //SPI_RESOURCE_RESERVE_CU_10
19849 #define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT                                                               0x0
19850 #define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT                                                               0x4
19851 #define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT                                                                0x8
19852 #define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT                                                              0xc
19853 #define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT                                                           0xf
19854 #define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK                                                                 0x0000000FL
19855 #define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK                                                                 0x000000F0L
19856 #define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK                                                                  0x00000F00L
19857 #define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK                                                                0x00007000L
19858 #define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK                                                             0x00078000L
19859 //SPI_RESOURCE_RESERVE_CU_11
19860 #define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT                                                               0x0
19861 #define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT                                                               0x4
19862 #define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT                                                                0x8
19863 #define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT                                                              0xc
19864 #define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT                                                           0xf
19865 #define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK                                                                 0x0000000FL
19866 #define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK                                                                 0x000000F0L
19867 #define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK                                                                  0x00000F00L
19868 #define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK                                                                0x00007000L
19869 #define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK                                                             0x00078000L
19870 //SPI_RESOURCE_RESERVE_EN_CU_10
19871 #define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT                                                              0x0
19872 #define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT                                                       0x1
19873 #define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT                                                      0x10
19874 #define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT                                              0x18
19875 #define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK                                                                0x00000001L
19876 #define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK                                                         0x0000FFFEL
19877 #define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK                                                        0x00FF0000L
19878 #define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK                                                0x01000000L
19879 //SPI_RESOURCE_RESERVE_EN_CU_11
19880 #define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT                                                              0x0
19881 #define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT                                                       0x1
19882 #define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT                                                      0x10
19883 #define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT                                              0x18
19884 #define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK                                                                0x00000001L
19885 #define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK                                                         0x0000FFFEL
19886 #define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK                                                        0x00FF0000L
19887 #define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK                                                0x01000000L
19888 //SPI_RESOURCE_RESERVE_CU_12
19889 #define SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT                                                               0x0
19890 #define SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT                                                               0x4
19891 #define SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT                                                                0x8
19892 #define SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT                                                              0xc
19893 #define SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT                                                           0xf
19894 #define SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK                                                                 0x0000000FL
19895 #define SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK                                                                 0x000000F0L
19896 #define SPI_RESOURCE_RESERVE_CU_12__LDS_MASK                                                                  0x00000F00L
19897 #define SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK                                                                0x00007000L
19898 #define SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK                                                             0x00078000L
19899 //SPI_RESOURCE_RESERVE_CU_13
19900 #define SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT                                                               0x0
19901 #define SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT                                                               0x4
19902 #define SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT                                                                0x8
19903 #define SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT                                                              0xc
19904 #define SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT                                                           0xf
19905 #define SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK                                                                 0x0000000FL
19906 #define SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK                                                                 0x000000F0L
19907 #define SPI_RESOURCE_RESERVE_CU_13__LDS_MASK                                                                  0x00000F00L
19908 #define SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK                                                                0x00007000L
19909 #define SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK                                                             0x00078000L
19910 //SPI_RESOURCE_RESERVE_CU_14
19911 #define SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT                                                               0x0
19912 #define SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT                                                               0x4
19913 #define SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT                                                                0x8
19914 #define SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT                                                              0xc
19915 #define SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT                                                           0xf
19916 #define SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK                                                                 0x0000000FL
19917 #define SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK                                                                 0x000000F0L
19918 #define SPI_RESOURCE_RESERVE_CU_14__LDS_MASK                                                                  0x00000F00L
19919 #define SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK                                                                0x00007000L
19920 #define SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK                                                             0x00078000L
19921 //SPI_RESOURCE_RESERVE_CU_15
19922 #define SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT                                                               0x0
19923 #define SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT                                                               0x4
19924 #define SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT                                                                0x8
19925 #define SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT                                                              0xc
19926 #define SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT                                                           0xf
19927 #define SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK                                                                 0x0000000FL
19928 #define SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK                                                                 0x000000F0L
19929 #define SPI_RESOURCE_RESERVE_CU_15__LDS_MASK                                                                  0x00000F00L
19930 #define SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK                                                                0x00007000L
19931 #define SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK                                                             0x00078000L
19932 //SPI_RESOURCE_RESERVE_EN_CU_12
19933 #define SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT                                                              0x0
19934 #define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT                                                       0x1
19935 #define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT                                                      0x10
19936 #define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY__SHIFT                                              0x18
19937 #define SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK                                                                0x00000001L
19938 #define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK                                                         0x0000FFFEL
19939 #define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK                                                        0x00FF0000L
19940 #define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY_MASK                                                0x01000000L
19941 //SPI_RESOURCE_RESERVE_EN_CU_13
19942 #define SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT                                                              0x0
19943 #define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT                                                       0x1
19944 #define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT                                                      0x10
19945 #define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY__SHIFT                                              0x18
19946 #define SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK                                                                0x00000001L
19947 #define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK                                                         0x0000FFFEL
19948 #define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK                                                        0x00FF0000L
19949 #define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY_MASK                                                0x01000000L
19950 //SPI_RESOURCE_RESERVE_EN_CU_14
19951 #define SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT                                                              0x0
19952 #define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT                                                       0x1
19953 #define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT                                                      0x10
19954 #define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY__SHIFT                                              0x18
19955 #define SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK                                                                0x00000001L
19956 #define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK                                                         0x0000FFFEL
19957 #define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK                                                        0x00FF0000L
19958 #define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY_MASK                                                0x01000000L
19959 //SPI_RESOURCE_RESERVE_EN_CU_15
19960 #define SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT                                                              0x0
19961 #define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT                                                       0x1
19962 #define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT                                                      0x10
19963 #define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY__SHIFT                                              0x18
19964 #define SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK                                                                0x00000001L
19965 #define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK                                                         0x0000FFFEL
19966 #define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK                                                        0x00FF0000L
19967 #define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY_MASK                                                0x01000000L
19968 //SPI_COMPUTE_WF_CTX_SAVE
19969 #define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT                                                              0x0
19970 #define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT                                                      0x1
19971 #define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT                                                     0x2
19972 #define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT                                                          0x1e
19973 #define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT                                                             0x1f
19974 #define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK                                                                0x00000001L
19975 #define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK                                                        0x00000002L
19976 #define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK                                                       0x00000004L
19977 #define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK                                                            0x40000000L
19978 #define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK                                                               0x80000000L
19979 //SPI_ARB_CNTL_0
19980 #define SPI_ARB_CNTL_0__EXP_ARB_COL_WT__SHIFT                                                                 0x0
19981 #define SPI_ARB_CNTL_0__EXP_ARB_POS_WT__SHIFT                                                                 0x4
19982 #define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT__SHIFT                                                                 0x8
19983 #define SPI_ARB_CNTL_0__EXP_ARB_COL_WT_MASK                                                                   0x0000000FL
19984 #define SPI_ARB_CNTL_0__EXP_ARB_POS_WT_MASK                                                                   0x000000F0L
19985 #define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT_MASK                                                                   0x00000F00L
19986 //SPI_FEATURE_CTRL
19987 #define SPI_FEATURE_CTRL__CU_LOCKING_FAIRNESS_DISABLE__SHIFT                                                  0x0
19988 #define SPI_FEATURE_CTRL__ALLOCATION_RATE_THROTTLE_THRESHOLD__SHIFT                                           0x2
19989 #define SPI_FEATURE_CTRL__ACTIVE_HARD_LOCK_LIMIT__SHIFT                                                       0x7
19990 #define SPI_FEATURE_CTRL__LR_IMBALANCE_THRESHOLD__SHIFT                                                       0xc
19991 #define SPI_FEATURE_CTRL__RA_PIPE_DEPTH_THRESHOLD_ALLOC_STALL_EN__SHIFT                                       0x12
19992 #define SPI_FEATURE_CTRL__BUS_ACTIVITY_THRESHOLD_ALLOC_STALL_EN__SHIFT                                        0x13
19993 #define SPI_FEATURE_CTRL__BUS_ACTIVITY_THRESHOLD__SHIFT                                                       0x14
19994 #define SPI_FEATURE_CTRL__TUNNELING_WAVE_LIMIT__SHIFT                                                         0x1c
19995 #define SPI_FEATURE_CTRL__CU_LOCKING_FAIRNESS_DISABLE_MASK                                                    0x00000001L
19996 #define SPI_FEATURE_CTRL__ALLOCATION_RATE_THROTTLE_THRESHOLD_MASK                                             0x0000007CL
19997 #define SPI_FEATURE_CTRL__ACTIVE_HARD_LOCK_LIMIT_MASK                                                         0x00000F80L
19998 #define SPI_FEATURE_CTRL__LR_IMBALANCE_THRESHOLD_MASK                                                         0x0003F000L
19999 #define SPI_FEATURE_CTRL__RA_PIPE_DEPTH_THRESHOLD_ALLOC_STALL_EN_MASK                                         0x00040000L
20000 #define SPI_FEATURE_CTRL__BUS_ACTIVITY_THRESHOLD_ALLOC_STALL_EN_MASK                                          0x00080000L
20001 #define SPI_FEATURE_CTRL__BUS_ACTIVITY_THRESHOLD_MASK                                                         0x0FF00000L
20002 #define SPI_FEATURE_CTRL__TUNNELING_WAVE_LIMIT_MASK                                                           0xF0000000L
20003 //SPI_SHADER_RSRC_LIMIT_CTRL
20004 #define SPI_SHADER_RSRC_LIMIT_CTRL__WAVES_PER_SIMD32__SHIFT                                                   0x0
20005 #define SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_PER_SIMD32__SHIFT                                                    0x5
20006 #define SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_WRAP_DISABLE__SHIFT                                                  0xc
20007 #define SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT__SHIFT                                                      0xd
20008 #define SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT_HIERARCHY_LEVEL__SHIFT                                      0x13
20009 #define SPI_SHADER_RSRC_LIMIT_CTRL__LDS_LIMIT__SHIFT                                                          0x14
20010 #define SPI_SHADER_RSRC_LIMIT_CTRL__LDS_LIMIT_HIERARCHY_LEVEL__SHIFT                                          0x1c
20011 #define SPI_SHADER_RSRC_LIMIT_CTRL__PERFORMANCE_LIMIT_ENABLE__SHIFT                                           0x1f
20012 #define SPI_SHADER_RSRC_LIMIT_CTRL__WAVES_PER_SIMD32_MASK                                                     0x0000001FL
20013 #define SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_PER_SIMD32_MASK                                                      0x00000FE0L
20014 #define SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_WRAP_DISABLE_MASK                                                    0x00001000L
20015 #define SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT_MASK                                                        0x0007E000L
20016 #define SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT_HIERARCHY_LEVEL_MASK                                        0x00080000L
20017 #define SPI_SHADER_RSRC_LIMIT_CTRL__LDS_LIMIT_MASK                                                            0x0FF00000L
20018 #define SPI_SHADER_RSRC_LIMIT_CTRL__LDS_LIMIT_HIERARCHY_LEVEL_MASK                                            0x10000000L
20019 #define SPI_SHADER_RSRC_LIMIT_CTRL__PERFORMANCE_LIMIT_ENABLE_MASK                                             0x80000000L
20020 
20021 
20022 // addressBlock: gc_cpphqddec
20023 //CP_HPD_MES_ROQ_OFFSETS
20024 #define CP_HPD_MES_ROQ_OFFSETS__IQ_OFFSET__SHIFT                                                              0x0
20025 #define CP_HPD_MES_ROQ_OFFSETS__PQ_OFFSET__SHIFT                                                              0x8
20026 #define CP_HPD_MES_ROQ_OFFSETS__IB_OFFSET__SHIFT                                                              0x10
20027 #define CP_HPD_MES_ROQ_OFFSETS__IQ_OFFSET_MASK                                                                0x00000007L
20028 #define CP_HPD_MES_ROQ_OFFSETS__PQ_OFFSET_MASK                                                                0x00003F00L
20029 #define CP_HPD_MES_ROQ_OFFSETS__IB_OFFSET_MASK                                                                0x007F0000L
20030 //CP_HPD_ROQ_OFFSETS
20031 #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT                                                                  0x0
20032 #define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT                                                                  0x8
20033 #define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT                                                                  0x10
20034 #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK                                                                    0x00000007L
20035 #define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK                                                                    0x00003F00L
20036 #define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK                                                                    0x007F0000L
20037 //CP_HPD_STATUS0
20038 #define CP_HPD_STATUS0__QUEUE_STATE__SHIFT                                                                    0x0
20039 #define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT                                                                   0x5
20040 #define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT                                                                0x8
20041 #define CP_HPD_STATUS0__FETCHING_MQD__SHIFT                                                                   0x10
20042 #define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB__SHIFT                                                           0x11
20043 #define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ__SHIFT                                                             0x12
20044 #define CP_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT                                                              0x14
20045 #define CP_HPD_STATUS0__MASTER_QUEUE_IDLE_DIS__SHIFT                                                          0x1b
20046 #define CP_HPD_STATUS0__ENABLE_OFFLOAD_CHECK__SHIFT                                                           0x1c
20047 #define CP_HPD_STATUS0__FREEZE_QUEUE_STATE__SHIFT                                                             0x1e
20048 #define CP_HPD_STATUS0__FORCE_QUEUE__SHIFT                                                                    0x1f
20049 #define CP_HPD_STATUS0__QUEUE_STATE_MASK                                                                      0x0000001FL
20050 #define CP_HPD_STATUS0__MAPPED_QUEUE_MASK                                                                     0x000000E0L
20051 #define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK                                                                  0x0000FF00L
20052 #define CP_HPD_STATUS0__FETCHING_MQD_MASK                                                                     0x00010000L
20053 #define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB_MASK                                                             0x00020000L
20054 #define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ_MASK                                                               0x00040000L
20055 #define CP_HPD_STATUS0__FORCE_QUEUE_STATE_MASK                                                                0x01F00000L
20056 #define CP_HPD_STATUS0__MASTER_QUEUE_IDLE_DIS_MASK                                                            0x08000000L
20057 #define CP_HPD_STATUS0__ENABLE_OFFLOAD_CHECK_MASK                                                             0x30000000L
20058 #define CP_HPD_STATUS0__FREEZE_QUEUE_STATE_MASK                                                               0x40000000L
20059 #define CP_HPD_STATUS0__FORCE_QUEUE_MASK                                                                      0x80000000L
20060 //CP_HPD_UTCL1_CNTL
20061 #define CP_HPD_UTCL1_CNTL__SELECT__SHIFT                                                                      0x0
20062 #define CP_HPD_UTCL1_CNTL__SELECT_MASK                                                                        0x0000000FL
20063 //CP_HPD_UTCL1_ERROR
20064 #define CP_HPD_UTCL1_ERROR__ADDR_HI__SHIFT                                                                    0x0
20065 #define CP_HPD_UTCL1_ERROR__TYPE__SHIFT                                                                       0x10
20066 #define CP_HPD_UTCL1_ERROR__VMID__SHIFT                                                                       0x14
20067 #define CP_HPD_UTCL1_ERROR__ADDR_HI_MASK                                                                      0x0000FFFFL
20068 #define CP_HPD_UTCL1_ERROR__TYPE_MASK                                                                         0x00010000L
20069 #define CP_HPD_UTCL1_ERROR__VMID_MASK                                                                         0x00F00000L
20070 //CP_HPD_UTCL1_ERROR_ADDR
20071 #define CP_HPD_UTCL1_ERROR_ADDR__ADDR__SHIFT                                                                  0xc
20072 #define CP_HPD_UTCL1_ERROR_ADDR__ADDR_MASK                                                                    0xFFFFF000L
20073 //CP_MQD_BASE_ADDR
20074 #define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT                                                                    0x2
20075 #define CP_MQD_BASE_ADDR__BASE_ADDR_MASK                                                                      0xFFFFFFFCL
20076 //CP_MQD_BASE_ADDR_HI
20077 #define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT                                                              0x0
20078 #define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK                                                                0x0000FFFFL
20079 //CP_HQD_ACTIVE
20080 #define CP_HQD_ACTIVE__ACTIVE__SHIFT                                                                          0x0
20081 #define CP_HQD_ACTIVE__BUSY_GATE__SHIFT                                                                       0x1
20082 #define CP_HQD_ACTIVE__ACTIVE_MASK                                                                            0x00000001L
20083 #define CP_HQD_ACTIVE__BUSY_GATE_MASK                                                                         0x00000002L
20084 //CP_HQD_VMID
20085 #define CP_HQD_VMID__VMID__SHIFT                                                                              0x0
20086 #define CP_HQD_VMID__IB_VMID__SHIFT                                                                           0x8
20087 #define CP_HQD_VMID__VQID__SHIFT                                                                              0x10
20088 #define CP_HQD_VMID__VMID_MASK                                                                                0x0000000FL
20089 #define CP_HQD_VMID__IB_VMID_MASK                                                                             0x00000F00L
20090 #define CP_HQD_VMID__VQID_MASK                                                                                0x03FF0000L
20091 //CP_HQD_PERSISTENT_STATE
20092 #define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT                                                           0x0
20093 #define CP_HQD_PERSISTENT_STATE__SUSPEND_STATUS__SHIFT                                                        0x7
20094 #define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT                                                          0x8
20095 #define CP_HQD_PERSISTENT_STATE__WPP_CLAMP_EN__SHIFT                                                          0x14
20096 #define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN__SHIFT                                                     0x15
20097 #define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT                                                      0x16
20098 #define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN__SHIFT                                                      0x17
20099 #define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN__SHIFT                                                     0x18
20100 #define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN__SHIFT                                                      0x19
20101 #define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN__SHIFT                                                     0x1a
20102 #define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN__SHIFT                                                  0x1b
20103 #define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT                                                        0x1c
20104 #define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT                                                        0x1d
20105 #define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT                                                          0x1e
20106 #define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT                                                           0x1f
20107 #define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK                                                             0x00000001L
20108 #define CP_HQD_PERSISTENT_STATE__SUSPEND_STATUS_MASK                                                          0x00000080L
20109 #define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK                                                            0x0003FF00L
20110 #define CP_HQD_PERSISTENT_STATE__WPP_CLAMP_EN_MASK                                                            0x00100000L
20111 #define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN_MASK                                                       0x00200000L
20112 #define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN_MASK                                                        0x00400000L
20113 #define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN_MASK                                                        0x00800000L
20114 #define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN_MASK                                                       0x01000000L
20115 #define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN_MASK                                                        0x02000000L
20116 #define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN_MASK                                                       0x04000000L
20117 #define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN_MASK                                                    0x08000000L
20118 #define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK                                                          0x10000000L
20119 #define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK                                                          0x20000000L
20120 #define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK                                                            0x40000000L
20121 #define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK                                                             0x80000000L
20122 //CP_HQD_PIPE_PRIORITY
20123 #define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT                                                            0x0
20124 #define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK                                                              0x00000003L
20125 //CP_HQD_QUEUE_PRIORITY
20126 #define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT                                                          0x0
20127 #define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK                                                            0x0000000FL
20128 //CP_HQD_QUANTUM
20129 #define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT                                                                     0x0
20130 #define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT                                                                  0x4
20131 #define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT                                                               0x8
20132 #define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT                                                                 0x1f
20133 #define CP_HQD_QUANTUM__QUANTUM_EN_MASK                                                                       0x00000001L
20134 #define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK                                                                    0x00000010L
20135 #define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK                                                                 0x00003F00L
20136 #define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK                                                                   0x80000000L
20137 //CP_HQD_PQ_BASE
20138 #define CP_HQD_PQ_BASE__ADDR__SHIFT                                                                           0x0
20139 #define CP_HQD_PQ_BASE__ADDR_MASK                                                                             0xFFFFFFFFL
20140 //CP_HQD_PQ_BASE_HI
20141 #define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT                                                                     0x0
20142 #define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK                                                                       0x000000FFL
20143 //CP_HQD_PQ_RPTR
20144 #define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT                                                                0x0
20145 #define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK                                                                  0xFFFFFFFFL
20146 //CP_HQD_PQ_RPTR_REPORT_ADDR
20147 #define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT                                                   0x2
20148 #define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK                                                     0xFFFFFFFCL
20149 //CP_HQD_PQ_RPTR_REPORT_ADDR_HI
20150 #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT                                             0x0
20151 #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK                                               0x0000FFFFL
20152 //CP_HQD_PQ_WPTR_POLL_ADDR
20153 #define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT                                                            0x3
20154 #define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK                                                              0xFFFFFFF8L
20155 //CP_HQD_PQ_WPTR_POLL_ADDR_HI
20156 #define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT                                                      0x0
20157 #define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK                                                        0x0000FFFFL
20158 //CP_HQD_PQ_DOORBELL_CONTROL
20159 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT                                                      0x0
20160 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT                                                  0x1
20161 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT                                                    0x2
20162 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT                                                    0x1c
20163 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT                                                  0x1d
20164 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT                                                        0x1e
20165 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT                                                       0x1f
20166 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK                                                        0x00000001L
20167 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK                                                    0x00000002L
20168 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK                                                      0x0FFFFFFCL
20169 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK                                                      0x10000000L
20170 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK                                                    0x20000000L
20171 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK                                                          0x40000000L
20172 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK                                                         0x80000000L
20173 //CP_HQD_PQ_CONTROL
20174 #define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT                                                                  0x0
20175 #define CP_HQD_PQ_CONTROL__WPTR_CARRY__SHIFT                                                                  0x6
20176 #define CP_HQD_PQ_CONTROL__RPTR_CARRY__SHIFT                                                                  0x7
20177 #define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT                                                             0x8
20178 #define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT                                                               0xe
20179 #define CP_HQD_PQ_CONTROL__PQ_EMPTY__SHIFT                                                                    0xf
20180 #define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT                                                                 0x10
20181 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT                                                             0x12
20182 #define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT                                                              0x14
20183 #define CP_HQD_PQ_CONTROL__EXE_DISABLE__SHIFT                                                                 0x17
20184 #define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT                                                                0x18
20185 #define CP_HQD_PQ_CONTROL__PQ_VOLATILE__SHIFT                                                                 0x1a
20186 #define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT                                                              0x1b
20187 #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT                                                              0x1c
20188 #define CP_HQD_PQ_CONTROL__TUNNEL_DISPATCH__SHIFT                                                             0x1d
20189 #define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT                                                                  0x1e
20190 #define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT                                                                   0x1f
20191 #define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK                                                                    0x0000003FL
20192 #define CP_HQD_PQ_CONTROL__WPTR_CARRY_MASK                                                                    0x00000040L
20193 #define CP_HQD_PQ_CONTROL__RPTR_CARRY_MASK                                                                    0x00000080L
20194 #define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK                                                               0x00003F00L
20195 #define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN_MASK                                                                 0x00004000L
20196 #define CP_HQD_PQ_CONTROL__PQ_EMPTY_MASK                                                                      0x00008000L
20197 #define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK                                                                   0x00030000L
20198 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK                                                               0x000C0000L
20199 #define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK                                                                0x00300000L
20200 #define CP_HQD_PQ_CONTROL__EXE_DISABLE_MASK                                                                   0x00800000L
20201 #define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK                                                                  0x03000000L
20202 #define CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK                                                                   0x04000000L
20203 #define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK                                                                0x08000000L
20204 #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK                                                                0x10000000L
20205 #define CP_HQD_PQ_CONTROL__TUNNEL_DISPATCH_MASK                                                               0x20000000L
20206 #define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK                                                                    0x40000000L
20207 #define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK                                                                     0x80000000L
20208 //CP_HQD_IB_BASE_ADDR
20209 #define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT                                                              0x2
20210 #define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK                                                                0xFFFFFFFCL
20211 //CP_HQD_IB_BASE_ADDR_HI
20212 #define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT                                                        0x0
20213 #define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK                                                          0x0000FFFFL
20214 //CP_HQD_IB_RPTR
20215 #define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT                                                                0x0
20216 #define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK                                                                  0x000FFFFFL
20217 //CP_HQD_IB_CONTROL
20218 #define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT                                                                     0x0
20219 #define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT                                                           0x14
20220 #define CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT                                                              0x17
20221 #define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT                                                             0x18
20222 #define CP_HQD_IB_CONTROL__IB_VOLATILE__SHIFT                                                                 0x1a
20223 #define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT                                                               0x1f
20224 #define CP_HQD_IB_CONTROL__IB_SIZE_MASK                                                                       0x000FFFFFL
20225 #define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK                                                             0x00300000L
20226 #define CP_HQD_IB_CONTROL__IB_EXE_DISABLE_MASK                                                                0x00800000L
20227 #define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK                                                               0x03000000L
20228 #define CP_HQD_IB_CONTROL__IB_VOLATILE_MASK                                                                   0x04000000L
20229 #define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK                                                                 0x80000000L
20230 //CP_HQD_IQ_TIMER
20231 #define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT                                                                     0x0
20232 #define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT                                                                    0x8
20233 #define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT                                                              0xb
20234 #define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT                                                                0xc
20235 #define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT                                                                   0xe
20236 #define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT                                                                0x10
20237 #define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT                                                                 0x16
20238 #define CP_HQD_IQ_TIMER__EXE_DISABLE__SHIFT                                                                   0x17
20239 #define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT                                                                  0x18
20240 #define CP_HQD_IQ_TIMER__IQ_VOLATILE__SHIFT                                                                   0x1a
20241 #define CP_HQD_IQ_TIMER__QUEUE_TYPE__SHIFT                                                                    0x1b
20242 #define CP_HQD_IQ_TIMER__REARM_TIMER__SHIFT                                                                   0x1c
20243 #define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT                                                                 0x1d
20244 #define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT                                                                 0x1e
20245 #define CP_HQD_IQ_TIMER__ACTIVE__SHIFT                                                                        0x1f
20246 #define CP_HQD_IQ_TIMER__WAIT_TIME_MASK                                                                       0x000000FFL
20247 #define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK                                                                      0x00000700L
20248 #define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK                                                                0x00000800L
20249 #define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK                                                                  0x00003000L
20250 #define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK                                                                     0x0000C000L
20251 #define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK                                                                  0x003F0000L
20252 #define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK                                                                   0x00400000L
20253 #define CP_HQD_IQ_TIMER__EXE_DISABLE_MASK                                                                     0x00800000L
20254 #define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK                                                                    0x03000000L
20255 #define CP_HQD_IQ_TIMER__IQ_VOLATILE_MASK                                                                     0x04000000L
20256 #define CP_HQD_IQ_TIMER__QUEUE_TYPE_MASK                                                                      0x08000000L
20257 #define CP_HQD_IQ_TIMER__REARM_TIMER_MASK                                                                     0x10000000L
20258 #define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK                                                                   0x20000000L
20259 #define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK                                                                   0x40000000L
20260 #define CP_HQD_IQ_TIMER__ACTIVE_MASK                                                                          0x80000000L
20261 //CP_HQD_IQ_RPTR
20262 #define CP_HQD_IQ_RPTR__OFFSET__SHIFT                                                                         0x0
20263 #define CP_HQD_IQ_RPTR__OFFSET_MASK                                                                           0x0000003FL
20264 //CP_HQD_DEQUEUE_REQUEST
20265 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT                                                            0x0
20266 #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT                                                            0x4
20267 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT                                                            0x8
20268 #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT                                                         0x9
20269 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT                                                         0xa
20270 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK                                                              0x0000000FL
20271 #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK                                                              0x00000010L
20272 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK                                                              0x00000100L
20273 #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK                                                           0x00000200L
20274 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK                                                           0x00000400L
20275 //CP_HQD_DMA_OFFLOAD
20276 #define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT                                                                0x0
20277 #define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK                                                                  0x00000001L
20278 //CP_HQD_OFFLOAD
20279 #define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT                                                                    0x0
20280 #define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT                                                                 0x1
20281 #define CP_HQD_OFFLOAD__AQL_OFFLOAD__SHIFT                                                                    0x2
20282 #define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN__SHIFT                                                                 0x3
20283 #define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT                                                                    0x4
20284 #define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT                                                                 0x5
20285 #define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK                                                                      0x00000001L
20286 #define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK                                                                   0x00000002L
20287 #define CP_HQD_OFFLOAD__AQL_OFFLOAD_MASK                                                                      0x00000004L
20288 #define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN_MASK                                                                   0x00000008L
20289 #define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK                                                                      0x00000010L
20290 #define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK                                                                   0x00000020L
20291 //CP_HQD_SEMA_CMD
20292 #define CP_HQD_SEMA_CMD__RETRY__SHIFT                                                                         0x0
20293 #define CP_HQD_SEMA_CMD__RESULT__SHIFT                                                                        0x1
20294 #define CP_HQD_SEMA_CMD__POLLING_DIS__SHIFT                                                                   0x8
20295 #define CP_HQD_SEMA_CMD__MESSAGE_EN__SHIFT                                                                    0x9
20296 #define CP_HQD_SEMA_CMD__RETRY_MASK                                                                           0x00000001L
20297 #define CP_HQD_SEMA_CMD__RESULT_MASK                                                                          0x00000006L
20298 #define CP_HQD_SEMA_CMD__POLLING_DIS_MASK                                                                     0x00000100L
20299 #define CP_HQD_SEMA_CMD__MESSAGE_EN_MASK                                                                      0x00000200L
20300 //CP_HQD_MSG_TYPE
20301 #define CP_HQD_MSG_TYPE__ACTION__SHIFT                                                                        0x0
20302 #define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT                                                                    0x4
20303 #define CP_HQD_MSG_TYPE__ACTION_MASK                                                                          0x00000007L
20304 #define CP_HQD_MSG_TYPE__SAVE_STATE_MASK                                                                      0x00000070L
20305 //CP_HQD_ATOMIC0_PREOP_LO
20306 #define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT                                                      0x0
20307 #define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK                                                        0xFFFFFFFFL
20308 //CP_HQD_ATOMIC0_PREOP_HI
20309 #define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT                                                      0x0
20310 #define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK                                                        0xFFFFFFFFL
20311 //CP_HQD_ATOMIC1_PREOP_LO
20312 #define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT                                                      0x0
20313 #define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK                                                        0xFFFFFFFFL
20314 //CP_HQD_ATOMIC1_PREOP_HI
20315 #define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT                                                      0x0
20316 #define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK                                                        0xFFFFFFFFL
20317 //CP_HQD_HQ_SCHEDULER0
20318 #define CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT                                                                0x0
20319 #define CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK                                                                  0xFFFFFFFFL
20320 //CP_HQD_HQ_STATUS0
20321 #define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT                                                              0x0
20322 #define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT                                                           0x2
20323 #define CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT                                                                     0x4
20324 #define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT                                                            0x7
20325 #define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT                                                                  0x8
20326 #define CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT                                                                0x9
20327 #define CP_HQD_HQ_STATUS0__RSVR_29_10__SHIFT                                                                  0xa
20328 #define CP_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT                                                                  0x1e
20329 #define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN__SHIFT                                                           0x1f
20330 #define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK                                                                0x00000003L
20331 #define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK                                                             0x0000000CL
20332 #define CP_HQD_HQ_STATUS0__RSV_6_4_MASK                                                                       0x00000070L
20333 #define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK                                                              0x00000080L
20334 #define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK                                                                    0x00000100L
20335 #define CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK                                                                  0x00000200L
20336 #define CP_HQD_HQ_STATUS0__RSVR_29_10_MASK                                                                    0x3FFFFC00L
20337 #define CP_HQD_HQ_STATUS0__QUEUE_IDLE_MASK                                                                    0x40000000L
20338 #define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN_MASK                                                             0x80000000L
20339 //CP_HQD_HQ_CONTROL0
20340 #define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT                                                                    0x0
20341 #define CP_HQD_HQ_CONTROL0__CONTROL_MASK                                                                      0xFFFFFFFFL
20342 //CP_HQD_HQ_SCHEDULER1
20343 #define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT                                                                0x0
20344 #define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK                                                                  0xFFFFFFFFL
20345 //CP_MQD_CONTROL
20346 #define CP_MQD_CONTROL__VMID__SHIFT                                                                           0x0
20347 #define CP_MQD_CONTROL__PRIV_STATE__SHIFT                                                                     0x8
20348 #define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT                                                                 0xc
20349 #define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT                                                              0xd
20350 #define CP_MQD_CONTROL__EXE_DISABLE__SHIFT                                                                    0x17
20351 #define CP_MQD_CONTROL__CACHE_POLICY__SHIFT                                                                   0x18
20352 #define CP_MQD_CONTROL__MQD_VOLATILE__SHIFT                                                                   0x1a
20353 #define CP_MQD_CONTROL__VMID_MASK                                                                             0x0000000FL
20354 #define CP_MQD_CONTROL__PRIV_STATE_MASK                                                                       0x00000100L
20355 #define CP_MQD_CONTROL__PROCESSING_MQD_MASK                                                                   0x00001000L
20356 #define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK                                                                0x00002000L
20357 #define CP_MQD_CONTROL__EXE_DISABLE_MASK                                                                      0x00800000L
20358 #define CP_MQD_CONTROL__CACHE_POLICY_MASK                                                                     0x03000000L
20359 #define CP_MQD_CONTROL__MQD_VOLATILE_MASK                                                                     0x04000000L
20360 //CP_HQD_HQ_STATUS1
20361 #define CP_HQD_HQ_STATUS1__STATUS__SHIFT                                                                      0x0
20362 #define CP_HQD_HQ_STATUS1__STATUS_MASK                                                                        0xFFFFFFFFL
20363 //CP_HQD_HQ_CONTROL1
20364 #define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT                                                                    0x0
20365 #define CP_HQD_HQ_CONTROL1__CONTROL_MASK                                                                      0xFFFFFFFFL
20366 //CP_HQD_EOP_BASE_ADDR
20367 #define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT                                                                0x0
20368 #define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK                                                                  0xFFFFFFFFL
20369 //CP_HQD_EOP_BASE_ADDR_HI
20370 #define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT                                                          0x0
20371 #define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK                                                            0x000000FFL
20372 //CP_HQD_EOP_CONTROL
20373 #define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT                                                                   0x0
20374 #define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT                                                             0x8
20375 #define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT                                                             0xc
20376 #define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT                                                           0xd
20377 #define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT                                                           0xe
20378 #define CP_HQD_EOP_CONTROL__HALT_FETCHER__SHIFT                                                               0x15
20379 #define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN__SHIFT                                                            0x16
20380 #define CP_HQD_EOP_CONTROL__EXE_DISABLE__SHIFT                                                                0x17
20381 #define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT                                                               0x18
20382 #define CP_HQD_EOP_CONTROL__EOP_VOLATILE__SHIFT                                                               0x1a
20383 #define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT                                                             0x1d
20384 #define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT                                                               0x1f
20385 #define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK                                                                     0x0000003FL
20386 #define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK                                                               0x00000100L
20387 #define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK                                                               0x00001000L
20388 #define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK                                                             0x00002000L
20389 #define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK                                                             0x00004000L
20390 #define CP_HQD_EOP_CONTROL__HALT_FETCHER_MASK                                                                 0x00200000L
20391 #define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN_MASK                                                              0x00400000L
20392 #define CP_HQD_EOP_CONTROL__EXE_DISABLE_MASK                                                                  0x00800000L
20393 #define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK                                                                 0x03000000L
20394 #define CP_HQD_EOP_CONTROL__EOP_VOLATILE_MASK                                                                 0x04000000L
20395 #define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK                                                               0x60000000L
20396 #define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK                                                                 0x80000000L
20397 //CP_HQD_EOP_RPTR
20398 #define CP_HQD_EOP_RPTR__RPTR__SHIFT                                                                          0x0
20399 #define CP_HQD_EOP_RPTR__RESET_FETCHER__SHIFT                                                                 0x1c
20400 #define CP_HQD_EOP_RPTR__DEQUEUE_PEND__SHIFT                                                                  0x1d
20401 #define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT                                                             0x1e
20402 #define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT                                                                  0x1f
20403 #define CP_HQD_EOP_RPTR__RPTR_MASK                                                                            0x00001FFFL
20404 #define CP_HQD_EOP_RPTR__RESET_FETCHER_MASK                                                                   0x10000000L
20405 #define CP_HQD_EOP_RPTR__DEQUEUE_PEND_MASK                                                                    0x20000000L
20406 #define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK                                                               0x40000000L
20407 #define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK                                                                    0x80000000L
20408 //CP_HQD_EOP_WPTR
20409 #define CP_HQD_EOP_WPTR__WPTR__SHIFT                                                                          0x0
20410 #define CP_HQD_EOP_WPTR__EOP_EMPTY__SHIFT                                                                     0xf
20411 #define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT                                                                     0x10
20412 #define CP_HQD_EOP_WPTR__WPTR_MASK                                                                            0x00001FFFL
20413 #define CP_HQD_EOP_WPTR__EOP_EMPTY_MASK                                                                       0x00008000L
20414 #define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK                                                                       0x1FFF0000L
20415 //CP_HQD_EOP_EVENTS
20416 #define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT                                                                 0x0
20417 #define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT                                                       0x10
20418 #define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK                                                                   0x00000FFFL
20419 #define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK                                                         0x00010000L
20420 //CP_HQD_CTX_SAVE_BASE_ADDR_LO
20421 #define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT                                                             0xc
20422 #define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK                                                               0xFFFFF000L
20423 //CP_HQD_CTX_SAVE_BASE_ADDR_HI
20424 #define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT                                                          0x0
20425 #define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK                                                            0x0000FFFFL
20426 //CP_HQD_CTX_SAVE_CONTROL
20427 #define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT                                                                0x3
20428 #define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT                                                           0x17
20429 #define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK                                                                  0x00000018L
20430 #define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE_MASK                                                             0x00800000L
20431 //CP_HQD_CNTL_STACK_OFFSET
20432 #define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT                                                               0x2
20433 #define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK                                                                 0x00007FFCL
20434 //CP_HQD_CNTL_STACK_SIZE
20435 #define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT                                                                   0xc
20436 #define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK                                                                     0x00007000L
20437 //CP_HQD_WG_STATE_OFFSET
20438 #define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT                                                                 0x2
20439 #define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK                                                                   0x01FFFFFCL
20440 //CP_HQD_CTX_SAVE_SIZE
20441 #define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT                                                                     0xc
20442 #define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK                                                                       0x01FFF000L
20443 //CP_HQD_GDS_RESOURCE_STATE
20444 #define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT                                                         0x0
20445 #define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT                                                         0x1
20446 #define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT                                                            0x4
20447 #define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT                                                            0xc
20448 #define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK                                                           0x00000001L
20449 #define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK                                                           0x00000002L
20450 #define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK                                                              0x000003F0L
20451 #define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK                                                              0x0003F000L
20452 //CP_HQD_ERROR
20453 #define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT                                                                     0x0
20454 #define CP_HQD_ERROR__SUA_ERROR__SHIFT                                                                        0x4
20455 #define CP_HQD_ERROR__AQL_ERROR__SHIFT                                                                        0x5
20456 #define CP_HQD_ERROR__PQ_UTCL1_ERROR__SHIFT                                                                   0x8
20457 #define CP_HQD_ERROR__IB_UTCL1_ERROR__SHIFT                                                                   0x9
20458 #define CP_HQD_ERROR__EOP_UTCL1_ERROR__SHIFT                                                                  0xa
20459 #define CP_HQD_ERROR__IQ_UTCL1_ERROR__SHIFT                                                                   0xb
20460 #define CP_HQD_ERROR__RRPT_UTCL1_ERROR__SHIFT                                                                 0xc
20461 #define CP_HQD_ERROR__WPP_UTCL1_ERROR__SHIFT                                                                  0xd
20462 #define CP_HQD_ERROR__SEM_UTCL1_ERROR__SHIFT                                                                  0xe
20463 #define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT                                                              0xf
20464 #define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR__SHIFT                                                              0x10
20465 #define CP_HQD_ERROR__SR_UTCL1_ERROR__SHIFT                                                                   0x11
20466 #define CP_HQD_ERROR__QU_UTCL1_ERROR__SHIFT                                                                   0x12
20467 #define CP_HQD_ERROR__TC_UTCL1_ERROR__SHIFT                                                                   0x13
20468 #define CP_HQD_ERROR__EDC_ERROR_ID_MASK                                                                       0x0000000FL
20469 #define CP_HQD_ERROR__SUA_ERROR_MASK                                                                          0x00000010L
20470 #define CP_HQD_ERROR__AQL_ERROR_MASK                                                                          0x00000020L
20471 #define CP_HQD_ERROR__PQ_UTCL1_ERROR_MASK                                                                     0x00000100L
20472 #define CP_HQD_ERROR__IB_UTCL1_ERROR_MASK                                                                     0x00000200L
20473 #define CP_HQD_ERROR__EOP_UTCL1_ERROR_MASK                                                                    0x00000400L
20474 #define CP_HQD_ERROR__IQ_UTCL1_ERROR_MASK                                                                     0x00000800L
20475 #define CP_HQD_ERROR__RRPT_UTCL1_ERROR_MASK                                                                   0x00001000L
20476 #define CP_HQD_ERROR__WPP_UTCL1_ERROR_MASK                                                                    0x00002000L
20477 #define CP_HQD_ERROR__SEM_UTCL1_ERROR_MASK                                                                    0x00004000L
20478 #define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR_MASK                                                                0x00008000L
20479 #define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR_MASK                                                                0x00010000L
20480 #define CP_HQD_ERROR__SR_UTCL1_ERROR_MASK                                                                     0x00020000L
20481 #define CP_HQD_ERROR__QU_UTCL1_ERROR_MASK                                                                     0x00040000L
20482 #define CP_HQD_ERROR__TC_UTCL1_ERROR_MASK                                                                     0x00080000L
20483 //CP_HQD_EOP_WPTR_MEM
20484 #define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT                                                                      0x0
20485 #define CP_HQD_EOP_WPTR_MEM__WPTR_MASK                                                                        0x00001FFFL
20486 //CP_HQD_AQL_CONTROL
20487 #define CP_HQD_AQL_CONTROL__CONTROL0__SHIFT                                                                   0x0
20488 #define CP_HQD_AQL_CONTROL__CONTROL0_EN__SHIFT                                                                0xf
20489 #define CP_HQD_AQL_CONTROL__CONTROL1__SHIFT                                                                   0x10
20490 #define CP_HQD_AQL_CONTROL__CONTROL1_EN__SHIFT                                                                0x1f
20491 #define CP_HQD_AQL_CONTROL__CONTROL0_MASK                                                                     0x00007FFFL
20492 #define CP_HQD_AQL_CONTROL__CONTROL0_EN_MASK                                                                  0x00008000L
20493 #define CP_HQD_AQL_CONTROL__CONTROL1_MASK                                                                     0x7FFF0000L
20494 #define CP_HQD_AQL_CONTROL__CONTROL1_EN_MASK                                                                  0x80000000L
20495 //CP_HQD_PQ_WPTR_LO
20496 #define CP_HQD_PQ_WPTR_LO__OFFSET__SHIFT                                                                      0x0
20497 #define CP_HQD_PQ_WPTR_LO__OFFSET_MASK                                                                        0xFFFFFFFFL
20498 //CP_HQD_PQ_WPTR_HI
20499 #define CP_HQD_PQ_WPTR_HI__DATA__SHIFT                                                                        0x0
20500 #define CP_HQD_PQ_WPTR_HI__DATA_MASK                                                                          0xFFFFFFFFL
20501 //CP_HQD_SUSPEND_CNTL_STACK_OFFSET
20502 #define CP_HQD_SUSPEND_CNTL_STACK_OFFSET__OFFSET__SHIFT                                                       0x2
20503 #define CP_HQD_SUSPEND_CNTL_STACK_OFFSET__OFFSET_MASK                                                         0x00007FFCL
20504 //CP_HQD_SUSPEND_CNTL_STACK_DW_CNT
20505 #define CP_HQD_SUSPEND_CNTL_STACK_DW_CNT__CNT__SHIFT                                                          0x0
20506 #define CP_HQD_SUSPEND_CNTL_STACK_DW_CNT__CNT_MASK                                                            0x00001FFFL
20507 //CP_HQD_SUSPEND_WG_STATE_OFFSET
20508 #define CP_HQD_SUSPEND_WG_STATE_OFFSET__OFFSET__SHIFT                                                         0x2
20509 #define CP_HQD_SUSPEND_WG_STATE_OFFSET__OFFSET_MASK                                                           0x01FFFFFCL
20510 //CP_HQD_DDID_RPTR
20511 #define CP_HQD_DDID_RPTR__RPTR__SHIFT                                                                         0x0
20512 #define CP_HQD_DDID_RPTR__RPTR_MASK                                                                           0x000007FFL
20513 //CP_HQD_DDID_WPTR
20514 #define CP_HQD_DDID_WPTR__WPTR__SHIFT                                                                         0x0
20515 #define CP_HQD_DDID_WPTR__WPTR_MASK                                                                           0x000007FFL
20516 //CP_HQD_DDID_INFLIGHT_COUNT
20517 #define CP_HQD_DDID_INFLIGHT_COUNT__COUNT__SHIFT                                                              0x0
20518 #define CP_HQD_DDID_INFLIGHT_COUNT__COUNT_MASK                                                                0x0000FFFFL
20519 //CP_HQD_DDID_DELTA_RPT_COUNT
20520 #define CP_HQD_DDID_DELTA_RPT_COUNT__COUNT__SHIFT                                                             0x0
20521 #define CP_HQD_DDID_DELTA_RPT_COUNT__COUNT_MASK                                                               0x000000FFL
20522 //CP_HQD_DEQUEUE_STATUS
20523 #define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT__SHIFT                                                            0x0
20524 #define CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND__SHIFT                                                        0x4
20525 #define CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND_EN__SHIFT                                                     0x9
20526 #define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT_EN__SHIFT                                                         0xa
20527 #define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT_MASK                                                              0x0000000FL
20528 #define CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND_MASK                                                          0x00000010L
20529 #define CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND_EN_MASK                                                       0x00000200L
20530 #define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT_EN_MASK                                                           0x00000400L
20531 
20532 
20533 // addressBlock: gc_didtdec
20534 //DIDT_IND_INDEX
20535 #define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT                                                                 0x0
20536 #define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK                                                                   0xFFFFFFFFL
20537 //DIDT_IND_DATA
20538 #define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT                                                                   0x0
20539 #define DIDT_IND_DATA__DIDT_IND_DATA_MASK                                                                     0xFFFFFFFFL
20540 //DIDT_INDEX_AUTO_INCR_EN
20541 #define DIDT_INDEX_AUTO_INCR_EN__DIDT_INDEX_AUTO_INCR_EN__SHIFT                                               0x0
20542 #define DIDT_INDEX_AUTO_INCR_EN__DIDT_INDEX_AUTO_INCR_EN_MASK                                                 0x00000001L
20543 
20544 
20545 // addressBlock: gc_gccacdec
20546 //GC_CAC_CTRL_1
20547 #define GC_CAC_CTRL_1__CAC_WINDOW__SHIFT                                                                      0x0
20548 #define GC_CAC_CTRL_1__TDP_WINDOW__SHIFT                                                                      0x18
20549 #define GC_CAC_CTRL_1__CAC_WINDOW_MASK                                                                        0x00FFFFFFL
20550 #define GC_CAC_CTRL_1__TDP_WINDOW_MASK                                                                        0xFF000000L
20551 //GC_CAC_CTRL_2
20552 #define GC_CAC_CTRL_2__CAC_ENABLE__SHIFT                                                                      0x0
20553 #define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE__SHIFT                                                            0x1
20554 #define GC_CAC_CTRL_2__GC_LCAC_ENABLE__SHIFT                                                                  0x2
20555 #define GC_CAC_CTRL_2__SE_LCAC_ENABLE__SHIFT                                                                  0x3
20556 #define GC_CAC_CTRL_2__GC_CAC_INDEX_AUTO_INCR_EN__SHIFT                                                       0x4
20557 #define GC_CAC_CTRL_2__CAC_ENABLE_MASK                                                                        0x00000001L
20558 #define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE_MASK                                                              0x00000002L
20559 #define GC_CAC_CTRL_2__GC_LCAC_ENABLE_MASK                                                                    0x00000004L
20560 #define GC_CAC_CTRL_2__SE_LCAC_ENABLE_MASK                                                                    0x00000008L
20561 #define GC_CAC_CTRL_2__GC_CAC_INDEX_AUTO_INCR_EN_MASK                                                         0x00000010L
20562 //GC_CAC_AGGR_LOWER
20563 #define GC_CAC_AGGR_LOWER__AGGR_31_0__SHIFT                                                                   0x0
20564 #define GC_CAC_AGGR_LOWER__AGGR_31_0_MASK                                                                     0xFFFFFFFFL
20565 //GC_CAC_AGGR_UPPER
20566 #define GC_CAC_AGGR_UPPER__AGGR_63_32__SHIFT                                                                  0x0
20567 #define GC_CAC_AGGR_UPPER__AGGR_63_32_MASK                                                                    0xFFFFFFFFL
20568 //GC_CAC_SOFT_CTRL
20569 #define GC_CAC_SOFT_CTRL__SOFT_SNAP__SHIFT                                                                    0x0
20570 #define GC_CAC_SOFT_CTRL__UNUSED__SHIFT                                                                       0x1
20571 #define GC_CAC_SOFT_CTRL__SOFT_SNAP_MASK                                                                      0x00000001L
20572 #define GC_CAC_SOFT_CTRL__UNUSED_MASK                                                                         0xFFFFFFFEL
20573 //GC_DIDT_CTRL0
20574 #define GC_DIDT_CTRL0__DIDT_CTRL_EN__SHIFT                                                                    0x0
20575 #define GC_DIDT_CTRL0__PHASE_OFFSET__SHIFT                                                                    0x1
20576 #define GC_DIDT_CTRL0__DIDT_SW_RST__SHIFT                                                                     0x3
20577 #define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT                                                            0x4
20578 #define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                    0x5
20579 #define GC_DIDT_CTRL0__DIDT_CTRL_EN_MASK                                                                      0x00000001L
20580 #define GC_DIDT_CTRL0__PHASE_OFFSET_MASK                                                                      0x00000006L
20581 #define GC_DIDT_CTRL0__DIDT_SW_RST_MASK                                                                       0x00000008L
20582 #define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK                                                              0x00000010L
20583 #define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK                                                      0x000001E0L
20584 //GC_DIDT_CTRL1
20585 #define GC_DIDT_CTRL1__MIN_POWER__SHIFT                                                                       0x0
20586 #define GC_DIDT_CTRL1__MAX_POWER__SHIFT                                                                       0x10
20587 #define GC_DIDT_CTRL1__MIN_POWER_MASK                                                                         0x0000FFFFL
20588 #define GC_DIDT_CTRL1__MAX_POWER_MASK                                                                         0xFFFF0000L
20589 //GC_DIDT_CTRL2
20590 #define GC_DIDT_CTRL2__MAX_POWER_DELTA__SHIFT                                                                 0x0
20591 #define GC_DIDT_CTRL2__UNUSED_0__SHIFT                                                                        0xe
20592 #define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT                                                        0x10
20593 #define GC_DIDT_CTRL2__UNUSED_1__SHIFT                                                                        0x1a
20594 #define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT                                                        0x1b
20595 #define GC_DIDT_CTRL2__UNUSED_2__SHIFT                                                                        0x1f
20596 #define GC_DIDT_CTRL2__MAX_POWER_DELTA_MASK                                                                   0x00003FFFL
20597 #define GC_DIDT_CTRL2__UNUSED_0_MASK                                                                          0x0000C000L
20598 #define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK                                                          0x03FF0000L
20599 #define GC_DIDT_CTRL2__UNUSED_1_MASK                                                                          0x04000000L
20600 #define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK                                                          0x78000000L
20601 #define GC_DIDT_CTRL2__UNUSED_2_MASK                                                                          0x80000000L
20602 //GC_DIDT_WEIGHT
20603 #define GC_DIDT_WEIGHT__SQ_WEIGHT__SHIFT                                                                      0x0
20604 #define GC_DIDT_WEIGHT__DB_WEIGHT__SHIFT                                                                      0x8
20605 #define GC_DIDT_WEIGHT__TD_WEIGHT__SHIFT                                                                      0x10
20606 #define GC_DIDT_WEIGHT__TCP_WEIGHT__SHIFT                                                                     0x18
20607 #define GC_DIDT_WEIGHT__SQ_WEIGHT_MASK                                                                        0x000000FFL
20608 #define GC_DIDT_WEIGHT__DB_WEIGHT_MASK                                                                        0x0000FF00L
20609 #define GC_DIDT_WEIGHT__TD_WEIGHT_MASK                                                                        0x00FF0000L
20610 #define GC_DIDT_WEIGHT__TCP_WEIGHT_MASK                                                                       0xFF000000L
20611 //GC_THROTTLE_CTRL
20612 #define GC_THROTTLE_CTRL__THROTTLE_CTRL_SW_RST__SHIFT                                                         0x0
20613 #define GC_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT                                                              0x1
20614 #define GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT                                                              0x2
20615 #define GC_THROTTLE_CTRL__PWRBRK_POLARITY_CNTL__SHIFT                                                         0x3
20616 #define GC_THROTTLE_CTRL__PCC_STALL_EN__SHIFT                                                                 0x4
20617 #define GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT                                                                 0x5
20618 #define GC_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT                                                             0x6
20619 #define GC_THROTTLE_CTRL__GC_EDC_OVERRIDE__SHIFT                                                              0x7
20620 #define GC_THROTTLE_CTRL__PCC_OVERRIDE__SHIFT                                                                 0x8
20621 #define GC_THROTTLE_CTRL__PWRBRK_OVERRIDE__SHIFT                                                              0x9
20622 #define GC_THROTTLE_CTRL__GC_EDC_PERF_COUNTER_EN__SHIFT                                                       0xa
20623 #define GC_THROTTLE_CTRL__PCC_PERF_COUNTER_EN__SHIFT                                                          0xb
20624 #define GC_THROTTLE_CTRL__PWRBRK_PERF_COUNTER_EN__SHIFT                                                       0xc
20625 #define GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT                                                        0xd
20626 #define GC_THROTTLE_CTRL__FIXED_PATTERN_PERF_COUNTER_EN__SHIFT                                                0x17
20627 #define GC_THROTTLE_CTRL__LUT_HW_UPDATE__SHIFT                                                                0x1d
20628 #define GC_THROTTLE_CTRL__THROTTLE_CTRL_CLK_EN_OVERRIDE__SHIFT                                                0x1e
20629 #define GC_THROTTLE_CTRL__THROTTLE_CTRL_SW_RST_MASK                                                           0x00000001L
20630 #define GC_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK                                                                0x00000002L
20631 #define GC_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK                                                                0x00000004L
20632 #define GC_THROTTLE_CTRL__PWRBRK_POLARITY_CNTL_MASK                                                           0x00000008L
20633 #define GC_THROTTLE_CTRL__PCC_STALL_EN_MASK                                                                   0x00000010L
20634 #define GC_THROTTLE_CTRL__PATTERN_MODE_MASK                                                                   0x00000020L
20635 #define GC_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK                                                               0x00000040L
20636 #define GC_THROTTLE_CTRL__GC_EDC_OVERRIDE_MASK                                                                0x00000080L
20637 #define GC_THROTTLE_CTRL__PCC_OVERRIDE_MASK                                                                   0x00000100L
20638 #define GC_THROTTLE_CTRL__PWRBRK_OVERRIDE_MASK                                                                0x00000200L
20639 #define GC_THROTTLE_CTRL__GC_EDC_PERF_COUNTER_EN_MASK                                                         0x00000400L
20640 #define GC_THROTTLE_CTRL__PCC_PERF_COUNTER_EN_MASK                                                            0x00000800L
20641 #define GC_THROTTLE_CTRL__PWRBRK_PERF_COUNTER_EN_MASK                                                         0x00001000L
20642 #define GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL_MASK                                                          0x007FE000L
20643 #define GC_THROTTLE_CTRL__FIXED_PATTERN_PERF_COUNTER_EN_MASK                                                  0x00800000L
20644 #define GC_THROTTLE_CTRL__LUT_HW_UPDATE_MASK                                                                  0x20000000L
20645 #define GC_THROTTLE_CTRL__THROTTLE_CTRL_CLK_EN_OVERRIDE_MASK                                                  0x40000000L
20646 //GC_EDC_CTRL
20647 #define GC_EDC_CTRL__EDC_EN__SHIFT                                                                            0x0
20648 #define GC_EDC_CTRL__EDC_SW_RST__SHIFT                                                                        0x1
20649 #define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT                                                               0x2
20650 #define GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT                                                                   0x3
20651 #define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                       0x4
20652 #define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT                                                          0x9
20653 #define GC_EDC_CTRL__EDC_THROTTLE_PATTERN_BIT_NUMS__SHIFT                                                     0xa
20654 #define GC_EDC_CTRL__EDC_LEVEL_SEL__SHIFT                                                                     0xe
20655 #define GC_EDC_CTRL__EDC_EN_MASK                                                                              0x00000001L
20656 #define GC_EDC_CTRL__EDC_SW_RST_MASK                                                                          0x00000002L
20657 #define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK                                                                 0x00000004L
20658 #define GC_EDC_CTRL__EDC_FORCE_STALL_MASK                                                                     0x00000008L
20659 #define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK                                                         0x000001F0L
20660 #define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK                                                            0x00000200L
20661 #define GC_EDC_CTRL__EDC_THROTTLE_PATTERN_BIT_NUMS_MASK                                                       0x00003C00L
20662 #define GC_EDC_CTRL__EDC_LEVEL_SEL_MASK                                                                       0x00004000L
20663 //GC_EDC_THRESHOLD
20664 #define GC_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT                                                                0x0
20665 #define GC_EDC_THRESHOLD__EDC_THRESHOLD_MASK                                                                  0xFFFFFFFFL
20666 //GC_EDC_STATUS
20667 #define GC_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT                                                              0x0
20668 #define GC_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK                                                                0x00000007L
20669 //GC_EDC_OVERFLOW
20670 #define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT                                              0x0
20671 #define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT                                           0x1
20672 #define GC_EDC_OVERFLOW__PSM_COUNTER__SHIFT                                                                   0x12
20673 #define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK                                                0x00000001L
20674 #define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK                                             0x0001FFFEL
20675 #define GC_EDC_OVERFLOW__PSM_COUNTER_MASK                                                                     0xFFFC0000L
20676 //GC_EDC_ROLLING_POWER_DELTA
20677 #define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT                                            0x0
20678 #define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK                                              0xFFFFFFFFL
20679 //GC_THROTTLE_CTRL1
20680 #define GC_THROTTLE_CTRL1__PCC_FP_PROGRAM_STEP_EN__SHIFT                                                      0x0
20681 #define GC_THROTTLE_CTRL1__PCC_PROGRAM_MIN_STEP__SHIFT                                                        0x1
20682 #define GC_THROTTLE_CTRL1__PCC_PROGRAM_MAX_STEP__SHIFT                                                        0x5
20683 #define GC_THROTTLE_CTRL1__PCC_PROGRAM_UPWARDS_STEP_SIZE__SHIFT                                               0xa
20684 #define GC_THROTTLE_CTRL1__PWRBRK_FP_PROGRAM_STEP_EN__SHIFT                                                   0xd
20685 #define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MIN_STEP__SHIFT                                                     0xe
20686 #define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MAX_STEP__SHIFT                                                     0x12
20687 #define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_UPWARDS_STEP_SIZE__SHIFT                                            0x17
20688 #define GC_THROTTLE_CTRL1__PCC_FP_PROGRAM_STEP_EN_MASK                                                        0x00000001L
20689 #define GC_THROTTLE_CTRL1__PCC_PROGRAM_MIN_STEP_MASK                                                          0x0000001EL
20690 #define GC_THROTTLE_CTRL1__PCC_PROGRAM_MAX_STEP_MASK                                                          0x000003E0L
20691 #define GC_THROTTLE_CTRL1__PCC_PROGRAM_UPWARDS_STEP_SIZE_MASK                                                 0x00001C00L
20692 #define GC_THROTTLE_CTRL1__PWRBRK_FP_PROGRAM_STEP_EN_MASK                                                     0x00002000L
20693 #define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MIN_STEP_MASK                                                       0x0003C000L
20694 #define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MAX_STEP_MASK                                                       0x007C0000L
20695 #define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_UPWARDS_STEP_SIZE_MASK                                              0x03800000L
20696 //GC_THROTTLE_STATUS
20697 #define GC_THROTTLE_STATUS__FSM_STATE__SHIFT                                                                  0x0
20698 #define GC_THROTTLE_STATUS__PATTERN_INDEX__SHIFT                                                              0x4
20699 #define GC_THROTTLE_STATUS__FSM_STATE_MASK                                                                    0x0000000FL
20700 #define GC_THROTTLE_STATUS__PATTERN_INDEX_MASK                                                                0x000003F0L
20701 //EDC_PERF_COUNTER
20702 #define EDC_PERF_COUNTER__EDC_PERF_COUNTER__SHIFT                                                             0x0
20703 #define EDC_PERF_COUNTER__EDC_PERF_COUNTER_MASK                                                               0xFFFFFFFFL
20704 //PCC_PERF_COUNTER
20705 #define PCC_PERF_COUNTER__PCC_PERF_COUNTER__SHIFT                                                             0x0
20706 #define PCC_PERF_COUNTER__PCC_PERF_COUNTER_MASK                                                               0xFFFFFFFFL
20707 //PWRBRK_PERF_COUNTER
20708 #define PWRBRK_PERF_COUNTER__PWRBRK_PERF_COUNTER__SHIFT                                                       0x0
20709 #define PWRBRK_PERF_COUNTER__PWRBRK_PERF_COUNTER_MASK                                                         0xFFFFFFFFL
20710 //GC_CAC_IND_INDEX
20711 #define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR__SHIFT                                                              0x0
20712 #define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR_MASK                                                                0xFFFFFFFFL
20713 //GC_CAC_IND_DATA
20714 #define GC_CAC_IND_DATA__GC_CAC_IND_DATA__SHIFT                                                               0x0
20715 #define GC_CAC_IND_DATA__GC_CAC_IND_DATA_MASK                                                                 0xFFFFFFFFL
20716 //SE_CAC_IND_INDEX
20717 #define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR__SHIFT                                                              0x0
20718 #define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR_MASK                                                                0xFFFFFFFFL
20719 //SE_CAC_IND_DATA
20720 #define SE_CAC_IND_DATA__SE_CAC_IND_DATA__SHIFT                                                               0x0
20721 #define SE_CAC_IND_DATA__SE_CAC_IND_DATA_MASK                                                                 0xFFFFFFFFL
20722 
20723 
20724 // addressBlock: gc_tcpdec
20725 //TCP_WATCH0_ADDR_H
20726 #define TCP_WATCH0_ADDR_H__ADDR__SHIFT                                                                        0x0
20727 #define TCP_WATCH0_ADDR_H__ADDR_MASK                                                                          0x0000FFFFL
20728 //TCP_WATCH0_ADDR_L
20729 #define TCP_WATCH0_ADDR_L__ADDR__SHIFT                                                                        0x7
20730 #define TCP_WATCH0_ADDR_L__ADDR_MASK                                                                          0xFFFFFF80L
20731 //TCP_WATCH0_CNTL
20732 #define TCP_WATCH0_CNTL__MASK__SHIFT                                                                          0x0
20733 #define TCP_WATCH0_CNTL__VMID__SHIFT                                                                          0x18
20734 #define TCP_WATCH0_CNTL__MODE__SHIFT                                                                          0x1d
20735 #define TCP_WATCH0_CNTL__VALID__SHIFT                                                                         0x1f
20736 #define TCP_WATCH0_CNTL__MASK_MASK                                                                            0x007FFFFFL
20737 #define TCP_WATCH0_CNTL__VMID_MASK                                                                            0x0F000000L
20738 #define TCP_WATCH0_CNTL__MODE_MASK                                                                            0x60000000L
20739 #define TCP_WATCH0_CNTL__VALID_MASK                                                                           0x80000000L
20740 //TCP_WATCH1_ADDR_H
20741 #define TCP_WATCH1_ADDR_H__ADDR__SHIFT                                                                        0x0
20742 #define TCP_WATCH1_ADDR_H__ADDR_MASK                                                                          0x0000FFFFL
20743 //TCP_WATCH1_ADDR_L
20744 #define TCP_WATCH1_ADDR_L__ADDR__SHIFT                                                                        0x7
20745 #define TCP_WATCH1_ADDR_L__ADDR_MASK                                                                          0xFFFFFF80L
20746 //TCP_WATCH1_CNTL
20747 #define TCP_WATCH1_CNTL__MASK__SHIFT                                                                          0x0
20748 #define TCP_WATCH1_CNTL__VMID__SHIFT                                                                          0x18
20749 #define TCP_WATCH1_CNTL__MODE__SHIFT                                                                          0x1d
20750 #define TCP_WATCH1_CNTL__VALID__SHIFT                                                                         0x1f
20751 #define TCP_WATCH1_CNTL__MASK_MASK                                                                            0x007FFFFFL
20752 #define TCP_WATCH1_CNTL__VMID_MASK                                                                            0x0F000000L
20753 #define TCP_WATCH1_CNTL__MODE_MASK                                                                            0x60000000L
20754 #define TCP_WATCH1_CNTL__VALID_MASK                                                                           0x80000000L
20755 //TCP_WATCH2_ADDR_H
20756 #define TCP_WATCH2_ADDR_H__ADDR__SHIFT                                                                        0x0
20757 #define TCP_WATCH2_ADDR_H__ADDR_MASK                                                                          0x0000FFFFL
20758 //TCP_WATCH2_ADDR_L
20759 #define TCP_WATCH2_ADDR_L__ADDR__SHIFT                                                                        0x7
20760 #define TCP_WATCH2_ADDR_L__ADDR_MASK                                                                          0xFFFFFF80L
20761 //TCP_WATCH2_CNTL
20762 #define TCP_WATCH2_CNTL__MASK__SHIFT                                                                          0x0
20763 #define TCP_WATCH2_CNTL__VMID__SHIFT                                                                          0x18
20764 #define TCP_WATCH2_CNTL__MODE__SHIFT                                                                          0x1d
20765 #define TCP_WATCH2_CNTL__VALID__SHIFT                                                                         0x1f
20766 #define TCP_WATCH2_CNTL__MASK_MASK                                                                            0x007FFFFFL
20767 #define TCP_WATCH2_CNTL__VMID_MASK                                                                            0x0F000000L
20768 #define TCP_WATCH2_CNTL__MODE_MASK                                                                            0x60000000L
20769 #define TCP_WATCH2_CNTL__VALID_MASK                                                                           0x80000000L
20770 //TCP_WATCH3_ADDR_H
20771 #define TCP_WATCH3_ADDR_H__ADDR__SHIFT                                                                        0x0
20772 #define TCP_WATCH3_ADDR_H__ADDR_MASK                                                                          0x0000FFFFL
20773 //TCP_WATCH3_ADDR_L
20774 #define TCP_WATCH3_ADDR_L__ADDR__SHIFT                                                                        0x7
20775 #define TCP_WATCH3_ADDR_L__ADDR_MASK                                                                          0xFFFFFF80L
20776 //TCP_WATCH3_CNTL
20777 #define TCP_WATCH3_CNTL__MASK__SHIFT                                                                          0x0
20778 #define TCP_WATCH3_CNTL__VMID__SHIFT                                                                          0x18
20779 #define TCP_WATCH3_CNTL__MODE__SHIFT                                                                          0x1d
20780 #define TCP_WATCH3_CNTL__VALID__SHIFT                                                                         0x1f
20781 #define TCP_WATCH3_CNTL__MASK_MASK                                                                            0x007FFFFFL
20782 #define TCP_WATCH3_CNTL__VMID_MASK                                                                            0x0F000000L
20783 #define TCP_WATCH3_CNTL__MODE_MASK                                                                            0x60000000L
20784 #define TCP_WATCH3_CNTL__VALID_MASK                                                                           0x80000000L
20785 //TCP_CNTL2
20786 #define TCP_CNTL2__LS_DISABLE_CLOCKS__SHIFT                                                                   0x0
20787 #define TCP_CNTL2__TCPF_FMT_MGCG_DISABLE__SHIFT                                                               0x8
20788 #define TCP_CNTL2__TCPF_LATENCY_BYPASS_DISABLE__SHIFT                                                         0x9
20789 #define TCP_CNTL2__TCPI_WRITE_DATA_MGCG_DISABLE__SHIFT                                                        0xa
20790 #define TCP_CNTL2__TCPI_INNER_BLOCK_MGCG_DISABLE__SHIFT                                                       0xb
20791 #define TCP_CNTL2__TCPI_ADRS_IMG_CALC_MGCG_DISABLE__SHIFT                                                     0xc
20792 #define TCP_CNTL2__V64_COMBINE_ENABLE__SHIFT                                                                  0xd
20793 #define TCP_CNTL2__TAGRAM_ADDR_SWIZZLE_DISABLE__SHIFT                                                         0xe
20794 #define TCP_CNTL2__RETURN_ORDER_OVERRIDE__SHIFT                                                               0xf
20795 #define TCP_CNTL2__LS_DISABLE_CLOCKS_MASK                                                                     0x000000FFL
20796 #define TCP_CNTL2__TCPF_FMT_MGCG_DISABLE_MASK                                                                 0x00000100L
20797 #define TCP_CNTL2__TCPF_LATENCY_BYPASS_DISABLE_MASK                                                           0x00000200L
20798 #define TCP_CNTL2__TCPI_WRITE_DATA_MGCG_DISABLE_MASK                                                          0x00000400L
20799 #define TCP_CNTL2__TCPI_INNER_BLOCK_MGCG_DISABLE_MASK                                                         0x00000800L
20800 #define TCP_CNTL2__TCPI_ADRS_IMG_CALC_MGCG_DISABLE_MASK                                                       0x00001000L
20801 #define TCP_CNTL2__V64_COMBINE_ENABLE_MASK                                                                    0x00002000L
20802 #define TCP_CNTL2__TAGRAM_ADDR_SWIZZLE_DISABLE_MASK                                                           0x00004000L
20803 #define TCP_CNTL2__RETURN_ORDER_OVERRIDE_MASK                                                                 0x00008000L
20804 //TCP_UTCL0_CNTL1
20805 #define TCP_UTCL0_CNTL1__FORCE_4K_L2_RESP__SHIFT                                                              0x0
20806 #define TCP_UTCL0_CNTL1__GPUVM_64K_DEFAULT__SHIFT                                                             0x1
20807 #define TCP_UTCL0_CNTL1__GPUVM_PERM_MODE__SHIFT                                                               0x2
20808 #define TCP_UTCL0_CNTL1__RESP_MODE__SHIFT                                                                     0x3
20809 #define TCP_UTCL0_CNTL1__RESP_FAULT_MODE__SHIFT                                                               0x5
20810 #define TCP_UTCL0_CNTL1__CLIENTID__SHIFT                                                                      0x7
20811 #define TCP_UTCL0_CNTL1__REG_INV_VMID__SHIFT                                                                  0x13
20812 #define TCP_UTCL0_CNTL1__REG_INV_ALL_VMID__SHIFT                                                              0x17
20813 #define TCP_UTCL0_CNTL1__REG_INV_TOGGLE__SHIFT                                                                0x18
20814 #define TCP_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT                                                    0x19
20815 #define TCP_UTCL0_CNTL1__FORCE_MISS__SHIFT                                                                    0x1a
20816 #define TCP_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT                                                        0x1c
20817 #define TCP_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT                                                        0x1e
20818 #define TCP_UTCL0_CNTL1__FORCE_4K_L2_RESP_MASK                                                                0x00000001L
20819 #define TCP_UTCL0_CNTL1__GPUVM_64K_DEFAULT_MASK                                                               0x00000002L
20820 #define TCP_UTCL0_CNTL1__GPUVM_PERM_MODE_MASK                                                                 0x00000004L
20821 #define TCP_UTCL0_CNTL1__RESP_MODE_MASK                                                                       0x00000018L
20822 #define TCP_UTCL0_CNTL1__RESP_FAULT_MODE_MASK                                                                 0x00000060L
20823 #define TCP_UTCL0_CNTL1__CLIENTID_MASK                                                                        0x0000FF80L
20824 #define TCP_UTCL0_CNTL1__REG_INV_VMID_MASK                                                                    0x00780000L
20825 #define TCP_UTCL0_CNTL1__REG_INV_ALL_VMID_MASK                                                                0x00800000L
20826 #define TCP_UTCL0_CNTL1__REG_INV_TOGGLE_MASK                                                                  0x01000000L
20827 #define TCP_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK                                                      0x02000000L
20828 #define TCP_UTCL0_CNTL1__FORCE_MISS_MASK                                                                      0x04000000L
20829 #define TCP_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK                                                          0x30000000L
20830 #define TCP_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK                                                          0xC0000000L
20831 //TCP_UTCL0_CNTL2
20832 #define TCP_UTCL0_CNTL2__SPARE__SHIFT                                                                         0x0
20833 #define TCP_UTCL0_CNTL2__MTYPE_OVRD_DIS__SHIFT                                                                0x9
20834 #define TCP_UTCL0_CNTL2__ANY_LINE_VALID__SHIFT                                                                0xa
20835 #define TCP_UTCL0_CNTL2__GPUVM_INV_MODE__SHIFT                                                                0xc
20836 #define TCP_UTCL0_CNTL2__FORCE_SNOOP__SHIFT                                                                   0xe
20837 #define TCP_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT                                                           0xf
20838 #define TCP_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT                                                          0x1a
20839 #define TCP_UTCL0_CNTL2__PERM_MODE_OVRD__SHIFT                                                                0x1b
20840 #define TCP_UTCL0_CNTL2__LINE_INVALIDATE_OPT__SHIFT                                                           0x1c
20841 #define TCP_UTCL0_CNTL2__GPUVM_16K_DEFAULT__SHIFT                                                             0x1d
20842 #define TCP_UTCL0_CNTL2__SPARE_MASK                                                                           0x000000FFL
20843 #define TCP_UTCL0_CNTL2__MTYPE_OVRD_DIS_MASK                                                                  0x00000200L
20844 #define TCP_UTCL0_CNTL2__ANY_LINE_VALID_MASK                                                                  0x00000400L
20845 #define TCP_UTCL0_CNTL2__GPUVM_INV_MODE_MASK                                                                  0x00001000L
20846 #define TCP_UTCL0_CNTL2__FORCE_SNOOP_MASK                                                                     0x00004000L
20847 #define TCP_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK_MASK                                                             0x00008000L
20848 #define TCP_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K_MASK                                                            0x04000000L
20849 #define TCP_UTCL0_CNTL2__PERM_MODE_OVRD_MASK                                                                  0x08000000L
20850 #define TCP_UTCL0_CNTL2__LINE_INVALIDATE_OPT_MASK                                                             0x10000000L
20851 #define TCP_UTCL0_CNTL2__GPUVM_16K_DEFAULT_MASK                                                               0x20000000L
20852 //TCP_UTCL0_STATUS
20853 #define TCP_UTCL0_STATUS__FAULT_DETECTED__SHIFT                                                               0x0
20854 #define TCP_UTCL0_STATUS__RETRY_DETECTED__SHIFT                                                               0x1
20855 #define TCP_UTCL0_STATUS__PRT_DETECTED__SHIFT                                                                 0x2
20856 #define TCP_UTCL0_STATUS__FAULT_DETECTED_MASK                                                                 0x00000001L
20857 #define TCP_UTCL0_STATUS__RETRY_DETECTED_MASK                                                                 0x00000002L
20858 #define TCP_UTCL0_STATUS__PRT_DETECTED_MASK                                                                   0x00000004L
20859 //TCP_PERFCOUNTER_FILTER
20860 #define TCP_PERFCOUNTER_FILTER__BUFFER__SHIFT                                                                 0x0
20861 #define TCP_PERFCOUNTER_FILTER__FLAT__SHIFT                                                                   0x1
20862 #define TCP_PERFCOUNTER_FILTER__DIM__SHIFT                                                                    0x2
20863 #define TCP_PERFCOUNTER_FILTER__DATA_FORMAT__SHIFT                                                            0x5
20864 #define TCP_PERFCOUNTER_FILTER__NUM_FORMAT__SHIFT                                                             0xd
20865 #define TCP_PERFCOUNTER_FILTER__SW_MODE__SHIFT                                                                0x11
20866 #define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES__SHIFT                                                            0x16
20867 #define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE__SHIFT                                                            0x18
20868 #define TCP_PERFCOUNTER_FILTER__SLC__SHIFT                                                                    0x1b
20869 #define TCP_PERFCOUNTER_FILTER__DLC__SHIFT                                                                    0x1c
20870 #define TCP_PERFCOUNTER_FILTER__GLC__SHIFT                                                                    0x1d
20871 #define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE__SHIFT                                                     0x1e
20872 #define TCP_PERFCOUNTER_FILTER__BUFFER_MASK                                                                   0x00000001L
20873 #define TCP_PERFCOUNTER_FILTER__FLAT_MASK                                                                     0x00000002L
20874 #define TCP_PERFCOUNTER_FILTER__DIM_MASK                                                                      0x0000001CL
20875 #define TCP_PERFCOUNTER_FILTER__DATA_FORMAT_MASK                                                              0x00000FE0L
20876 #define TCP_PERFCOUNTER_FILTER__NUM_FORMAT_MASK                                                               0x0001E000L
20877 #define TCP_PERFCOUNTER_FILTER__SW_MODE_MASK                                                                  0x003E0000L
20878 #define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES_MASK                                                              0x00C00000L
20879 #define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE_MASK                                                              0x07000000L
20880 #define TCP_PERFCOUNTER_FILTER__SLC_MASK                                                                      0x08000000L
20881 #define TCP_PERFCOUNTER_FILTER__DLC_MASK                                                                      0x10000000L
20882 #define TCP_PERFCOUNTER_FILTER__GLC_MASK                                                                      0x20000000L
20883 #define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE_MASK                                                       0x40000000L
20884 //TCP_PERFCOUNTER_FILTER_EN
20885 #define TCP_PERFCOUNTER_FILTER_EN__BUFFER__SHIFT                                                              0x0
20886 #define TCP_PERFCOUNTER_FILTER_EN__FLAT__SHIFT                                                                0x1
20887 #define TCP_PERFCOUNTER_FILTER_EN__DIM__SHIFT                                                                 0x2
20888 #define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT__SHIFT                                                         0x3
20889 #define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT__SHIFT                                                          0x4
20890 #define TCP_PERFCOUNTER_FILTER_EN__SW_MODE__SHIFT                                                             0x5
20891 #define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES__SHIFT                                                         0x6
20892 #define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE__SHIFT                                                         0x7
20893 #define TCP_PERFCOUNTER_FILTER_EN__SLC__SHIFT                                                                 0x8
20894 #define TCP_PERFCOUNTER_FILTER_EN__DLC__SHIFT                                                                 0x9
20895 #define TCP_PERFCOUNTER_FILTER_EN__GLC__SHIFT                                                                 0xa
20896 #define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE__SHIFT                                                  0xb
20897 #define TCP_PERFCOUNTER_FILTER_EN__REQ_MODE__SHIFT                                                            0xc
20898 #define TCP_PERFCOUNTER_FILTER_EN__BUFFER_MASK                                                                0x00000001L
20899 #define TCP_PERFCOUNTER_FILTER_EN__FLAT_MASK                                                                  0x00000002L
20900 #define TCP_PERFCOUNTER_FILTER_EN__DIM_MASK                                                                   0x00000004L
20901 #define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT_MASK                                                           0x00000008L
20902 #define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT_MASK                                                            0x00000010L
20903 #define TCP_PERFCOUNTER_FILTER_EN__SW_MODE_MASK                                                               0x00000020L
20904 #define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES_MASK                                                           0x00000040L
20905 #define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE_MASK                                                           0x00000080L
20906 #define TCP_PERFCOUNTER_FILTER_EN__SLC_MASK                                                                   0x00000100L
20907 #define TCP_PERFCOUNTER_FILTER_EN__DLC_MASK                                                                   0x00000200L
20908 #define TCP_PERFCOUNTER_FILTER_EN__GLC_MASK                                                                   0x00000400L
20909 #define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE_MASK                                                    0x00000800L
20910 #define TCP_PERFCOUNTER_FILTER_EN__REQ_MODE_MASK                                                              0x00001000L
20911 //TCP_PERFCOUNTER_FILTER2
20912 #define TCP_PERFCOUNTER_FILTER2__REQ_MODE__SHIFT                                                              0x0
20913 #define TCP_PERFCOUNTER_FILTER2__REQ_MODE_MASK                                                                0x00000007L
20914 
20915 
20916 // addressBlock: gc_gdspdec
20917 //GDS_VMID0_BASE
20918 #define GDS_VMID0_BASE__BASE__SHIFT                                                                           0x0
20919 #define GDS_VMID0_BASE__UNUSED__SHIFT                                                                         0x10
20920 #define GDS_VMID0_BASE__BASE_MASK                                                                             0x0000FFFFL
20921 #define GDS_VMID0_BASE__UNUSED_MASK                                                                           0xFFFF0000L
20922 //GDS_VMID0_SIZE
20923 #define GDS_VMID0_SIZE__SIZE__SHIFT                                                                           0x0
20924 #define GDS_VMID0_SIZE__UNUSED__SHIFT                                                                         0x11
20925 #define GDS_VMID0_SIZE__SIZE_MASK                                                                             0x0001FFFFL
20926 #define GDS_VMID0_SIZE__UNUSED_MASK                                                                           0xFFFE0000L
20927 //GDS_VMID1_BASE
20928 #define GDS_VMID1_BASE__BASE__SHIFT                                                                           0x0
20929 #define GDS_VMID1_BASE__UNUSED__SHIFT                                                                         0x10
20930 #define GDS_VMID1_BASE__BASE_MASK                                                                             0x0000FFFFL
20931 #define GDS_VMID1_BASE__UNUSED_MASK                                                                           0xFFFF0000L
20932 //GDS_VMID1_SIZE
20933 #define GDS_VMID1_SIZE__SIZE__SHIFT                                                                           0x0
20934 #define GDS_VMID1_SIZE__UNUSED__SHIFT                                                                         0x11
20935 #define GDS_VMID1_SIZE__SIZE_MASK                                                                             0x0001FFFFL
20936 #define GDS_VMID1_SIZE__UNUSED_MASK                                                                           0xFFFE0000L
20937 //GDS_VMID2_BASE
20938 #define GDS_VMID2_BASE__BASE__SHIFT                                                                           0x0
20939 #define GDS_VMID2_BASE__UNUSED__SHIFT                                                                         0x10
20940 #define GDS_VMID2_BASE__BASE_MASK                                                                             0x0000FFFFL
20941 #define GDS_VMID2_BASE__UNUSED_MASK                                                                           0xFFFF0000L
20942 //GDS_VMID2_SIZE
20943 #define GDS_VMID2_SIZE__SIZE__SHIFT                                                                           0x0
20944 #define GDS_VMID2_SIZE__UNUSED__SHIFT                                                                         0x11
20945 #define GDS_VMID2_SIZE__SIZE_MASK                                                                             0x0001FFFFL
20946 #define GDS_VMID2_SIZE__UNUSED_MASK                                                                           0xFFFE0000L
20947 //GDS_VMID3_BASE
20948 #define GDS_VMID3_BASE__BASE__SHIFT                                                                           0x0
20949 #define GDS_VMID3_BASE__UNUSED__SHIFT                                                                         0x10
20950 #define GDS_VMID3_BASE__BASE_MASK                                                                             0x0000FFFFL
20951 #define GDS_VMID3_BASE__UNUSED_MASK                                                                           0xFFFF0000L
20952 //GDS_VMID3_SIZE
20953 #define GDS_VMID3_SIZE__SIZE__SHIFT                                                                           0x0
20954 #define GDS_VMID3_SIZE__UNUSED__SHIFT                                                                         0x11
20955 #define GDS_VMID3_SIZE__SIZE_MASK                                                                             0x0001FFFFL
20956 #define GDS_VMID3_SIZE__UNUSED_MASK                                                                           0xFFFE0000L
20957 //GDS_VMID4_BASE
20958 #define GDS_VMID4_BASE__BASE__SHIFT                                                                           0x0
20959 #define GDS_VMID4_BASE__UNUSED__SHIFT                                                                         0x10
20960 #define GDS_VMID4_BASE__BASE_MASK                                                                             0x0000FFFFL
20961 #define GDS_VMID4_BASE__UNUSED_MASK                                                                           0xFFFF0000L
20962 //GDS_VMID4_SIZE
20963 #define GDS_VMID4_SIZE__SIZE__SHIFT                                                                           0x0
20964 #define GDS_VMID4_SIZE__UNUSED__SHIFT                                                                         0x11
20965 #define GDS_VMID4_SIZE__SIZE_MASK                                                                             0x0001FFFFL
20966 #define GDS_VMID4_SIZE__UNUSED_MASK                                                                           0xFFFE0000L
20967 //GDS_VMID5_BASE
20968 #define GDS_VMID5_BASE__BASE__SHIFT                                                                           0x0
20969 #define GDS_VMID5_BASE__UNUSED__SHIFT                                                                         0x10
20970 #define GDS_VMID5_BASE__BASE_MASK                                                                             0x0000FFFFL
20971 #define GDS_VMID5_BASE__UNUSED_MASK                                                                           0xFFFF0000L
20972 //GDS_VMID5_SIZE
20973 #define GDS_VMID5_SIZE__SIZE__SHIFT                                                                           0x0
20974 #define GDS_VMID5_SIZE__UNUSED__SHIFT                                                                         0x11
20975 #define GDS_VMID5_SIZE__SIZE_MASK                                                                             0x0001FFFFL
20976 #define GDS_VMID5_SIZE__UNUSED_MASK                                                                           0xFFFE0000L
20977 //GDS_VMID6_BASE
20978 #define GDS_VMID6_BASE__BASE__SHIFT                                                                           0x0
20979 #define GDS_VMID6_BASE__UNUSED__SHIFT                                                                         0x10
20980 #define GDS_VMID6_BASE__BASE_MASK                                                                             0x0000FFFFL
20981 #define GDS_VMID6_BASE__UNUSED_MASK                                                                           0xFFFF0000L
20982 //GDS_VMID6_SIZE
20983 #define GDS_VMID6_SIZE__SIZE__SHIFT                                                                           0x0
20984 #define GDS_VMID6_SIZE__UNUSED__SHIFT                                                                         0x11
20985 #define GDS_VMID6_SIZE__SIZE_MASK                                                                             0x0001FFFFL
20986 #define GDS_VMID6_SIZE__UNUSED_MASK                                                                           0xFFFE0000L
20987 //GDS_VMID7_BASE
20988 #define GDS_VMID7_BASE__BASE__SHIFT                                                                           0x0
20989 #define GDS_VMID7_BASE__UNUSED__SHIFT                                                                         0x10
20990 #define GDS_VMID7_BASE__BASE_MASK                                                                             0x0000FFFFL
20991 #define GDS_VMID7_BASE__UNUSED_MASK                                                                           0xFFFF0000L
20992 //GDS_VMID7_SIZE
20993 #define GDS_VMID7_SIZE__SIZE__SHIFT                                                                           0x0
20994 #define GDS_VMID7_SIZE__UNUSED__SHIFT                                                                         0x11
20995 #define GDS_VMID7_SIZE__SIZE_MASK                                                                             0x0001FFFFL
20996 #define GDS_VMID7_SIZE__UNUSED_MASK                                                                           0xFFFE0000L
20997 //GDS_VMID8_BASE
20998 #define GDS_VMID8_BASE__BASE__SHIFT                                                                           0x0
20999 #define GDS_VMID8_BASE__UNUSED__SHIFT                                                                         0x10
21000 #define GDS_VMID8_BASE__BASE_MASK                                                                             0x0000FFFFL
21001 #define GDS_VMID8_BASE__UNUSED_MASK                                                                           0xFFFF0000L
21002 //GDS_VMID8_SIZE
21003 #define GDS_VMID8_SIZE__SIZE__SHIFT                                                                           0x0
21004 #define GDS_VMID8_SIZE__UNUSED__SHIFT                                                                         0x11
21005 #define GDS_VMID8_SIZE__SIZE_MASK                                                                             0x0001FFFFL
21006 #define GDS_VMID8_SIZE__UNUSED_MASK                                                                           0xFFFE0000L
21007 //GDS_VMID9_BASE
21008 #define GDS_VMID9_BASE__BASE__SHIFT                                                                           0x0
21009 #define GDS_VMID9_BASE__UNUSED__SHIFT                                                                         0x10
21010 #define GDS_VMID9_BASE__BASE_MASK                                                                             0x0000FFFFL
21011 #define GDS_VMID9_BASE__UNUSED_MASK                                                                           0xFFFF0000L
21012 //GDS_VMID9_SIZE
21013 #define GDS_VMID9_SIZE__SIZE__SHIFT                                                                           0x0
21014 #define GDS_VMID9_SIZE__UNUSED__SHIFT                                                                         0x11
21015 #define GDS_VMID9_SIZE__SIZE_MASK                                                                             0x0001FFFFL
21016 #define GDS_VMID9_SIZE__UNUSED_MASK                                                                           0xFFFE0000L
21017 //GDS_VMID10_BASE
21018 #define GDS_VMID10_BASE__BASE__SHIFT                                                                          0x0
21019 #define GDS_VMID10_BASE__UNUSED__SHIFT                                                                        0x10
21020 #define GDS_VMID10_BASE__BASE_MASK                                                                            0x0000FFFFL
21021 #define GDS_VMID10_BASE__UNUSED_MASK                                                                          0xFFFF0000L
21022 //GDS_VMID10_SIZE
21023 #define GDS_VMID10_SIZE__SIZE__SHIFT                                                                          0x0
21024 #define GDS_VMID10_SIZE__UNUSED__SHIFT                                                                        0x11
21025 #define GDS_VMID10_SIZE__SIZE_MASK                                                                            0x0001FFFFL
21026 #define GDS_VMID10_SIZE__UNUSED_MASK                                                                          0xFFFE0000L
21027 //GDS_VMID11_BASE
21028 #define GDS_VMID11_BASE__BASE__SHIFT                                                                          0x0
21029 #define GDS_VMID11_BASE__UNUSED__SHIFT                                                                        0x10
21030 #define GDS_VMID11_BASE__BASE_MASK                                                                            0x0000FFFFL
21031 #define GDS_VMID11_BASE__UNUSED_MASK                                                                          0xFFFF0000L
21032 //GDS_VMID11_SIZE
21033 #define GDS_VMID11_SIZE__SIZE__SHIFT                                                                          0x0
21034 #define GDS_VMID11_SIZE__UNUSED__SHIFT                                                                        0x11
21035 #define GDS_VMID11_SIZE__SIZE_MASK                                                                            0x0001FFFFL
21036 #define GDS_VMID11_SIZE__UNUSED_MASK                                                                          0xFFFE0000L
21037 //GDS_VMID12_BASE
21038 #define GDS_VMID12_BASE__BASE__SHIFT                                                                          0x0
21039 #define GDS_VMID12_BASE__UNUSED__SHIFT                                                                        0x10
21040 #define GDS_VMID12_BASE__BASE_MASK                                                                            0x0000FFFFL
21041 #define GDS_VMID12_BASE__UNUSED_MASK                                                                          0xFFFF0000L
21042 //GDS_VMID12_SIZE
21043 #define GDS_VMID12_SIZE__SIZE__SHIFT                                                                          0x0
21044 #define GDS_VMID12_SIZE__UNUSED__SHIFT                                                                        0x11
21045 #define GDS_VMID12_SIZE__SIZE_MASK                                                                            0x0001FFFFL
21046 #define GDS_VMID12_SIZE__UNUSED_MASK                                                                          0xFFFE0000L
21047 //GDS_VMID13_BASE
21048 #define GDS_VMID13_BASE__BASE__SHIFT                                                                          0x0
21049 #define GDS_VMID13_BASE__UNUSED__SHIFT                                                                        0x10
21050 #define GDS_VMID13_BASE__BASE_MASK                                                                            0x0000FFFFL
21051 #define GDS_VMID13_BASE__UNUSED_MASK                                                                          0xFFFF0000L
21052 //GDS_VMID13_SIZE
21053 #define GDS_VMID13_SIZE__SIZE__SHIFT                                                                          0x0
21054 #define GDS_VMID13_SIZE__UNUSED__SHIFT                                                                        0x11
21055 #define GDS_VMID13_SIZE__SIZE_MASK                                                                            0x0001FFFFL
21056 #define GDS_VMID13_SIZE__UNUSED_MASK                                                                          0xFFFE0000L
21057 //GDS_VMID14_BASE
21058 #define GDS_VMID14_BASE__BASE__SHIFT                                                                          0x0
21059 #define GDS_VMID14_BASE__UNUSED__SHIFT                                                                        0x10
21060 #define GDS_VMID14_BASE__BASE_MASK                                                                            0x0000FFFFL
21061 #define GDS_VMID14_BASE__UNUSED_MASK                                                                          0xFFFF0000L
21062 //GDS_VMID14_SIZE
21063 #define GDS_VMID14_SIZE__SIZE__SHIFT                                                                          0x0
21064 #define GDS_VMID14_SIZE__UNUSED__SHIFT                                                                        0x11
21065 #define GDS_VMID14_SIZE__SIZE_MASK                                                                            0x0001FFFFL
21066 #define GDS_VMID14_SIZE__UNUSED_MASK                                                                          0xFFFE0000L
21067 //GDS_VMID15_BASE
21068 #define GDS_VMID15_BASE__BASE__SHIFT                                                                          0x0
21069 #define GDS_VMID15_BASE__UNUSED__SHIFT                                                                        0x10
21070 #define GDS_VMID15_BASE__BASE_MASK                                                                            0x0000FFFFL
21071 #define GDS_VMID15_BASE__UNUSED_MASK                                                                          0xFFFF0000L
21072 //GDS_VMID15_SIZE
21073 #define GDS_VMID15_SIZE__SIZE__SHIFT                                                                          0x0
21074 #define GDS_VMID15_SIZE__UNUSED__SHIFT                                                                        0x11
21075 #define GDS_VMID15_SIZE__SIZE_MASK                                                                            0x0001FFFFL
21076 #define GDS_VMID15_SIZE__UNUSED_MASK                                                                          0xFFFE0000L
21077 //GDS_GWS_VMID0
21078 #define GDS_GWS_VMID0__BASE__SHIFT                                                                            0x0
21079 #define GDS_GWS_VMID0__UNUSED1__SHIFT                                                                         0x6
21080 #define GDS_GWS_VMID0__SIZE__SHIFT                                                                            0x10
21081 #define GDS_GWS_VMID0__UNUSED2__SHIFT                                                                         0x17
21082 #define GDS_GWS_VMID0__BASE_MASK                                                                              0x0000003FL
21083 #define GDS_GWS_VMID0__UNUSED1_MASK                                                                           0x0000FFC0L
21084 #define GDS_GWS_VMID0__SIZE_MASK                                                                              0x007F0000L
21085 #define GDS_GWS_VMID0__UNUSED2_MASK                                                                           0xFF800000L
21086 //GDS_GWS_VMID1
21087 #define GDS_GWS_VMID1__BASE__SHIFT                                                                            0x0
21088 #define GDS_GWS_VMID1__UNUSED1__SHIFT                                                                         0x6
21089 #define GDS_GWS_VMID1__SIZE__SHIFT                                                                            0x10
21090 #define GDS_GWS_VMID1__UNUSED2__SHIFT                                                                         0x17
21091 #define GDS_GWS_VMID1__BASE_MASK                                                                              0x0000003FL
21092 #define GDS_GWS_VMID1__UNUSED1_MASK                                                                           0x0000FFC0L
21093 #define GDS_GWS_VMID1__SIZE_MASK                                                                              0x007F0000L
21094 #define GDS_GWS_VMID1__UNUSED2_MASK                                                                           0xFF800000L
21095 //GDS_GWS_VMID2
21096 #define GDS_GWS_VMID2__BASE__SHIFT                                                                            0x0
21097 #define GDS_GWS_VMID2__UNUSED1__SHIFT                                                                         0x6
21098 #define GDS_GWS_VMID2__SIZE__SHIFT                                                                            0x10
21099 #define GDS_GWS_VMID2__UNUSED2__SHIFT                                                                         0x17
21100 #define GDS_GWS_VMID2__BASE_MASK                                                                              0x0000003FL
21101 #define GDS_GWS_VMID2__UNUSED1_MASK                                                                           0x0000FFC0L
21102 #define GDS_GWS_VMID2__SIZE_MASK                                                                              0x007F0000L
21103 #define GDS_GWS_VMID2__UNUSED2_MASK                                                                           0xFF800000L
21104 //GDS_GWS_VMID3
21105 #define GDS_GWS_VMID3__BASE__SHIFT                                                                            0x0
21106 #define GDS_GWS_VMID3__UNUSED1__SHIFT                                                                         0x6
21107 #define GDS_GWS_VMID3__SIZE__SHIFT                                                                            0x10
21108 #define GDS_GWS_VMID3__UNUSED2__SHIFT                                                                         0x17
21109 #define GDS_GWS_VMID3__BASE_MASK                                                                              0x0000003FL
21110 #define GDS_GWS_VMID3__UNUSED1_MASK                                                                           0x0000FFC0L
21111 #define GDS_GWS_VMID3__SIZE_MASK                                                                              0x007F0000L
21112 #define GDS_GWS_VMID3__UNUSED2_MASK                                                                           0xFF800000L
21113 //GDS_GWS_VMID4
21114 #define GDS_GWS_VMID4__BASE__SHIFT                                                                            0x0
21115 #define GDS_GWS_VMID4__UNUSED1__SHIFT                                                                         0x6
21116 #define GDS_GWS_VMID4__SIZE__SHIFT                                                                            0x10
21117 #define GDS_GWS_VMID4__UNUSED2__SHIFT                                                                         0x17
21118 #define GDS_GWS_VMID4__BASE_MASK                                                                              0x0000003FL
21119 #define GDS_GWS_VMID4__UNUSED1_MASK                                                                           0x0000FFC0L
21120 #define GDS_GWS_VMID4__SIZE_MASK                                                                              0x007F0000L
21121 #define GDS_GWS_VMID4__UNUSED2_MASK                                                                           0xFF800000L
21122 //GDS_GWS_VMID5
21123 #define GDS_GWS_VMID5__BASE__SHIFT                                                                            0x0
21124 #define GDS_GWS_VMID5__UNUSED1__SHIFT                                                                         0x6
21125 #define GDS_GWS_VMID5__SIZE__SHIFT                                                                            0x10
21126 #define GDS_GWS_VMID5__UNUSED2__SHIFT                                                                         0x17
21127 #define GDS_GWS_VMID5__BASE_MASK                                                                              0x0000003FL
21128 #define GDS_GWS_VMID5__UNUSED1_MASK                                                                           0x0000FFC0L
21129 #define GDS_GWS_VMID5__SIZE_MASK                                                                              0x007F0000L
21130 #define GDS_GWS_VMID5__UNUSED2_MASK                                                                           0xFF800000L
21131 //GDS_GWS_VMID6
21132 #define GDS_GWS_VMID6__BASE__SHIFT                                                                            0x0
21133 #define GDS_GWS_VMID6__UNUSED1__SHIFT                                                                         0x6
21134 #define GDS_GWS_VMID6__SIZE__SHIFT                                                                            0x10
21135 #define GDS_GWS_VMID6__UNUSED2__SHIFT                                                                         0x17
21136 #define GDS_GWS_VMID6__BASE_MASK                                                                              0x0000003FL
21137 #define GDS_GWS_VMID6__UNUSED1_MASK                                                                           0x0000FFC0L
21138 #define GDS_GWS_VMID6__SIZE_MASK                                                                              0x007F0000L
21139 #define GDS_GWS_VMID6__UNUSED2_MASK                                                                           0xFF800000L
21140 //GDS_GWS_VMID7
21141 #define GDS_GWS_VMID7__BASE__SHIFT                                                                            0x0
21142 #define GDS_GWS_VMID7__UNUSED1__SHIFT                                                                         0x6
21143 #define GDS_GWS_VMID7__SIZE__SHIFT                                                                            0x10
21144 #define GDS_GWS_VMID7__UNUSED2__SHIFT                                                                         0x17
21145 #define GDS_GWS_VMID7__BASE_MASK                                                                              0x0000003FL
21146 #define GDS_GWS_VMID7__UNUSED1_MASK                                                                           0x0000FFC0L
21147 #define GDS_GWS_VMID7__SIZE_MASK                                                                              0x007F0000L
21148 #define GDS_GWS_VMID7__UNUSED2_MASK                                                                           0xFF800000L
21149 //GDS_GWS_VMID8
21150 #define GDS_GWS_VMID8__BASE__SHIFT                                                                            0x0
21151 #define GDS_GWS_VMID8__UNUSED1__SHIFT                                                                         0x6
21152 #define GDS_GWS_VMID8__SIZE__SHIFT                                                                            0x10
21153 #define GDS_GWS_VMID8__UNUSED2__SHIFT                                                                         0x17
21154 #define GDS_GWS_VMID8__BASE_MASK                                                                              0x0000003FL
21155 #define GDS_GWS_VMID8__UNUSED1_MASK                                                                           0x0000FFC0L
21156 #define GDS_GWS_VMID8__SIZE_MASK                                                                              0x007F0000L
21157 #define GDS_GWS_VMID8__UNUSED2_MASK                                                                           0xFF800000L
21158 //GDS_GWS_VMID9
21159 #define GDS_GWS_VMID9__BASE__SHIFT                                                                            0x0
21160 #define GDS_GWS_VMID9__UNUSED1__SHIFT                                                                         0x6
21161 #define GDS_GWS_VMID9__SIZE__SHIFT                                                                            0x10
21162 #define GDS_GWS_VMID9__UNUSED2__SHIFT                                                                         0x17
21163 #define GDS_GWS_VMID9__BASE_MASK                                                                              0x0000003FL
21164 #define GDS_GWS_VMID9__UNUSED1_MASK                                                                           0x0000FFC0L
21165 #define GDS_GWS_VMID9__SIZE_MASK                                                                              0x007F0000L
21166 #define GDS_GWS_VMID9__UNUSED2_MASK                                                                           0xFF800000L
21167 //GDS_GWS_VMID10
21168 #define GDS_GWS_VMID10__BASE__SHIFT                                                                           0x0
21169 #define GDS_GWS_VMID10__UNUSED1__SHIFT                                                                        0x6
21170 #define GDS_GWS_VMID10__SIZE__SHIFT                                                                           0x10
21171 #define GDS_GWS_VMID10__UNUSED2__SHIFT                                                                        0x17
21172 #define GDS_GWS_VMID10__BASE_MASK                                                                             0x0000003FL
21173 #define GDS_GWS_VMID10__UNUSED1_MASK                                                                          0x0000FFC0L
21174 #define GDS_GWS_VMID10__SIZE_MASK                                                                             0x007F0000L
21175 #define GDS_GWS_VMID10__UNUSED2_MASK                                                                          0xFF800000L
21176 //GDS_GWS_VMID11
21177 #define GDS_GWS_VMID11__BASE__SHIFT                                                                           0x0
21178 #define GDS_GWS_VMID11__UNUSED1__SHIFT                                                                        0x6
21179 #define GDS_GWS_VMID11__SIZE__SHIFT                                                                           0x10
21180 #define GDS_GWS_VMID11__UNUSED2__SHIFT                                                                        0x17
21181 #define GDS_GWS_VMID11__BASE_MASK                                                                             0x0000003FL
21182 #define GDS_GWS_VMID11__UNUSED1_MASK                                                                          0x0000FFC0L
21183 #define GDS_GWS_VMID11__SIZE_MASK                                                                             0x007F0000L
21184 #define GDS_GWS_VMID11__UNUSED2_MASK                                                                          0xFF800000L
21185 //GDS_GWS_VMID12
21186 #define GDS_GWS_VMID12__BASE__SHIFT                                                                           0x0
21187 #define GDS_GWS_VMID12__UNUSED1__SHIFT                                                                        0x6
21188 #define GDS_GWS_VMID12__SIZE__SHIFT                                                                           0x10
21189 #define GDS_GWS_VMID12__UNUSED2__SHIFT                                                                        0x17
21190 #define GDS_GWS_VMID12__BASE_MASK                                                                             0x0000003FL
21191 #define GDS_GWS_VMID12__UNUSED1_MASK                                                                          0x0000FFC0L
21192 #define GDS_GWS_VMID12__SIZE_MASK                                                                             0x007F0000L
21193 #define GDS_GWS_VMID12__UNUSED2_MASK                                                                          0xFF800000L
21194 //GDS_GWS_VMID13
21195 #define GDS_GWS_VMID13__BASE__SHIFT                                                                           0x0
21196 #define GDS_GWS_VMID13__UNUSED1__SHIFT                                                                        0x6
21197 #define GDS_GWS_VMID13__SIZE__SHIFT                                                                           0x10
21198 #define GDS_GWS_VMID13__UNUSED2__SHIFT                                                                        0x17
21199 #define GDS_GWS_VMID13__BASE_MASK                                                                             0x0000003FL
21200 #define GDS_GWS_VMID13__UNUSED1_MASK                                                                          0x0000FFC0L
21201 #define GDS_GWS_VMID13__SIZE_MASK                                                                             0x007F0000L
21202 #define GDS_GWS_VMID13__UNUSED2_MASK                                                                          0xFF800000L
21203 //GDS_GWS_VMID14
21204 #define GDS_GWS_VMID14__BASE__SHIFT                                                                           0x0
21205 #define GDS_GWS_VMID14__UNUSED1__SHIFT                                                                        0x6
21206 #define GDS_GWS_VMID14__SIZE__SHIFT                                                                           0x10
21207 #define GDS_GWS_VMID14__UNUSED2__SHIFT                                                                        0x17
21208 #define GDS_GWS_VMID14__BASE_MASK                                                                             0x0000003FL
21209 #define GDS_GWS_VMID14__UNUSED1_MASK                                                                          0x0000FFC0L
21210 #define GDS_GWS_VMID14__SIZE_MASK                                                                             0x007F0000L
21211 #define GDS_GWS_VMID14__UNUSED2_MASK                                                                          0xFF800000L
21212 //GDS_GWS_VMID15
21213 #define GDS_GWS_VMID15__BASE__SHIFT                                                                           0x0
21214 #define GDS_GWS_VMID15__UNUSED1__SHIFT                                                                        0x6
21215 #define GDS_GWS_VMID15__SIZE__SHIFT                                                                           0x10
21216 #define GDS_GWS_VMID15__UNUSED2__SHIFT                                                                        0x17
21217 #define GDS_GWS_VMID15__BASE_MASK                                                                             0x0000003FL
21218 #define GDS_GWS_VMID15__UNUSED1_MASK                                                                          0x0000FFC0L
21219 #define GDS_GWS_VMID15__SIZE_MASK                                                                             0x007F0000L
21220 #define GDS_GWS_VMID15__UNUSED2_MASK                                                                          0xFF800000L
21221 //GDS_OA_VMID0
21222 #define GDS_OA_VMID0__MASK__SHIFT                                                                             0x0
21223 #define GDS_OA_VMID0__UNUSED__SHIFT                                                                           0x10
21224 #define GDS_OA_VMID0__MASK_MASK                                                                               0x0000FFFFL
21225 #define GDS_OA_VMID0__UNUSED_MASK                                                                             0xFFFF0000L
21226 //GDS_OA_VMID1
21227 #define GDS_OA_VMID1__MASK__SHIFT                                                                             0x0
21228 #define GDS_OA_VMID1__UNUSED__SHIFT                                                                           0x10
21229 #define GDS_OA_VMID1__MASK_MASK                                                                               0x0000FFFFL
21230 #define GDS_OA_VMID1__UNUSED_MASK                                                                             0xFFFF0000L
21231 //GDS_OA_VMID2
21232 #define GDS_OA_VMID2__MASK__SHIFT                                                                             0x0
21233 #define GDS_OA_VMID2__UNUSED__SHIFT                                                                           0x10
21234 #define GDS_OA_VMID2__MASK_MASK                                                                               0x0000FFFFL
21235 #define GDS_OA_VMID2__UNUSED_MASK                                                                             0xFFFF0000L
21236 //GDS_OA_VMID3
21237 #define GDS_OA_VMID3__MASK__SHIFT                                                                             0x0
21238 #define GDS_OA_VMID3__UNUSED__SHIFT                                                                           0x10
21239 #define GDS_OA_VMID3__MASK_MASK                                                                               0x0000FFFFL
21240 #define GDS_OA_VMID3__UNUSED_MASK                                                                             0xFFFF0000L
21241 //GDS_OA_VMID4
21242 #define GDS_OA_VMID4__MASK__SHIFT                                                                             0x0
21243 #define GDS_OA_VMID4__UNUSED__SHIFT                                                                           0x10
21244 #define GDS_OA_VMID4__MASK_MASK                                                                               0x0000FFFFL
21245 #define GDS_OA_VMID4__UNUSED_MASK                                                                             0xFFFF0000L
21246 //GDS_OA_VMID5
21247 #define GDS_OA_VMID5__MASK__SHIFT                                                                             0x0
21248 #define GDS_OA_VMID5__UNUSED__SHIFT                                                                           0x10
21249 #define GDS_OA_VMID5__MASK_MASK                                                                               0x0000FFFFL
21250 #define GDS_OA_VMID5__UNUSED_MASK                                                                             0xFFFF0000L
21251 //GDS_OA_VMID6
21252 #define GDS_OA_VMID6__MASK__SHIFT                                                                             0x0
21253 #define GDS_OA_VMID6__UNUSED__SHIFT                                                                           0x10
21254 #define GDS_OA_VMID6__MASK_MASK                                                                               0x0000FFFFL
21255 #define GDS_OA_VMID6__UNUSED_MASK                                                                             0xFFFF0000L
21256 //GDS_OA_VMID7
21257 #define GDS_OA_VMID7__MASK__SHIFT                                                                             0x0
21258 #define GDS_OA_VMID7__UNUSED__SHIFT                                                                           0x10
21259 #define GDS_OA_VMID7__MASK_MASK                                                                               0x0000FFFFL
21260 #define GDS_OA_VMID7__UNUSED_MASK                                                                             0xFFFF0000L
21261 //GDS_OA_VMID8
21262 #define GDS_OA_VMID8__MASK__SHIFT                                                                             0x0
21263 #define GDS_OA_VMID8__UNUSED__SHIFT                                                                           0x10
21264 #define GDS_OA_VMID8__MASK_MASK                                                                               0x0000FFFFL
21265 #define GDS_OA_VMID8__UNUSED_MASK                                                                             0xFFFF0000L
21266 //GDS_OA_VMID9
21267 #define GDS_OA_VMID9__MASK__SHIFT                                                                             0x0
21268 #define GDS_OA_VMID9__UNUSED__SHIFT                                                                           0x10
21269 #define GDS_OA_VMID9__MASK_MASK                                                                               0x0000FFFFL
21270 #define GDS_OA_VMID9__UNUSED_MASK                                                                             0xFFFF0000L
21271 //GDS_OA_VMID10
21272 #define GDS_OA_VMID10__MASK__SHIFT                                                                            0x0
21273 #define GDS_OA_VMID10__UNUSED__SHIFT                                                                          0x10
21274 #define GDS_OA_VMID10__MASK_MASK                                                                              0x0000FFFFL
21275 #define GDS_OA_VMID10__UNUSED_MASK                                                                            0xFFFF0000L
21276 //GDS_OA_VMID11
21277 #define GDS_OA_VMID11__MASK__SHIFT                                                                            0x0
21278 #define GDS_OA_VMID11__UNUSED__SHIFT                                                                          0x10
21279 #define GDS_OA_VMID11__MASK_MASK                                                                              0x0000FFFFL
21280 #define GDS_OA_VMID11__UNUSED_MASK                                                                            0xFFFF0000L
21281 //GDS_OA_VMID12
21282 #define GDS_OA_VMID12__MASK__SHIFT                                                                            0x0
21283 #define GDS_OA_VMID12__UNUSED__SHIFT                                                                          0x10
21284 #define GDS_OA_VMID12__MASK_MASK                                                                              0x0000FFFFL
21285 #define GDS_OA_VMID12__UNUSED_MASK                                                                            0xFFFF0000L
21286 //GDS_OA_VMID13
21287 #define GDS_OA_VMID13__MASK__SHIFT                                                                            0x0
21288 #define GDS_OA_VMID13__UNUSED__SHIFT                                                                          0x10
21289 #define GDS_OA_VMID13__MASK_MASK                                                                              0x0000FFFFL
21290 #define GDS_OA_VMID13__UNUSED_MASK                                                                            0xFFFF0000L
21291 //GDS_OA_VMID14
21292 #define GDS_OA_VMID14__MASK__SHIFT                                                                            0x0
21293 #define GDS_OA_VMID14__UNUSED__SHIFT                                                                          0x10
21294 #define GDS_OA_VMID14__MASK_MASK                                                                              0x0000FFFFL
21295 #define GDS_OA_VMID14__UNUSED_MASK                                                                            0xFFFF0000L
21296 //GDS_OA_VMID15
21297 #define GDS_OA_VMID15__MASK__SHIFT                                                                            0x0
21298 #define GDS_OA_VMID15__UNUSED__SHIFT                                                                          0x10
21299 #define GDS_OA_VMID15__MASK_MASK                                                                              0x0000FFFFL
21300 #define GDS_OA_VMID15__UNUSED_MASK                                                                            0xFFFF0000L
21301 //GDS_GWS_RESET0
21302 #define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT                                                                0x0
21303 #define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT                                                                0x1
21304 #define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT                                                                0x2
21305 #define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT                                                                0x3
21306 #define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT                                                                0x4
21307 #define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT                                                                0x5
21308 #define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT                                                                0x6
21309 #define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT                                                                0x7
21310 #define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT                                                                0x8
21311 #define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT                                                                0x9
21312 #define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT                                                               0xa
21313 #define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT                                                               0xb
21314 #define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT                                                               0xc
21315 #define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT                                                               0xd
21316 #define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT                                                               0xe
21317 #define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT                                                               0xf
21318 #define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT                                                               0x10
21319 #define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT                                                               0x11
21320 #define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT                                                               0x12
21321 #define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT                                                               0x13
21322 #define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT                                                               0x14
21323 #define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT                                                               0x15
21324 #define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT                                                               0x16
21325 #define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT                                                               0x17
21326 #define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT                                                               0x18
21327 #define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT                                                               0x19
21328 #define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT                                                               0x1a
21329 #define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT                                                               0x1b
21330 #define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT                                                               0x1c
21331 #define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT                                                               0x1d
21332 #define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT                                                               0x1e
21333 #define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT                                                               0x1f
21334 #define GDS_GWS_RESET0__RESOURCE0_RESET_MASK                                                                  0x00000001L
21335 #define GDS_GWS_RESET0__RESOURCE1_RESET_MASK                                                                  0x00000002L
21336 #define GDS_GWS_RESET0__RESOURCE2_RESET_MASK                                                                  0x00000004L
21337 #define GDS_GWS_RESET0__RESOURCE3_RESET_MASK                                                                  0x00000008L
21338 #define GDS_GWS_RESET0__RESOURCE4_RESET_MASK                                                                  0x00000010L
21339 #define GDS_GWS_RESET0__RESOURCE5_RESET_MASK                                                                  0x00000020L
21340 #define GDS_GWS_RESET0__RESOURCE6_RESET_MASK                                                                  0x00000040L
21341 #define GDS_GWS_RESET0__RESOURCE7_RESET_MASK                                                                  0x00000080L
21342 #define GDS_GWS_RESET0__RESOURCE8_RESET_MASK                                                                  0x00000100L
21343 #define GDS_GWS_RESET0__RESOURCE9_RESET_MASK                                                                  0x00000200L
21344 #define GDS_GWS_RESET0__RESOURCE10_RESET_MASK                                                                 0x00000400L
21345 #define GDS_GWS_RESET0__RESOURCE11_RESET_MASK                                                                 0x00000800L
21346 #define GDS_GWS_RESET0__RESOURCE12_RESET_MASK                                                                 0x00001000L
21347 #define GDS_GWS_RESET0__RESOURCE13_RESET_MASK                                                                 0x00002000L
21348 #define GDS_GWS_RESET0__RESOURCE14_RESET_MASK                                                                 0x00004000L
21349 #define GDS_GWS_RESET0__RESOURCE15_RESET_MASK                                                                 0x00008000L
21350 #define GDS_GWS_RESET0__RESOURCE16_RESET_MASK                                                                 0x00010000L
21351 #define GDS_GWS_RESET0__RESOURCE17_RESET_MASK                                                                 0x00020000L
21352 #define GDS_GWS_RESET0__RESOURCE18_RESET_MASK                                                                 0x00040000L
21353 #define GDS_GWS_RESET0__RESOURCE19_RESET_MASK                                                                 0x00080000L
21354 #define GDS_GWS_RESET0__RESOURCE20_RESET_MASK                                                                 0x00100000L
21355 #define GDS_GWS_RESET0__RESOURCE21_RESET_MASK                                                                 0x00200000L
21356 #define GDS_GWS_RESET0__RESOURCE22_RESET_MASK                                                                 0x00400000L
21357 #define GDS_GWS_RESET0__RESOURCE23_RESET_MASK                                                                 0x00800000L
21358 #define GDS_GWS_RESET0__RESOURCE24_RESET_MASK                                                                 0x01000000L
21359 #define GDS_GWS_RESET0__RESOURCE25_RESET_MASK                                                                 0x02000000L
21360 #define GDS_GWS_RESET0__RESOURCE26_RESET_MASK                                                                 0x04000000L
21361 #define GDS_GWS_RESET0__RESOURCE27_RESET_MASK                                                                 0x08000000L
21362 #define GDS_GWS_RESET0__RESOURCE28_RESET_MASK                                                                 0x10000000L
21363 #define GDS_GWS_RESET0__RESOURCE29_RESET_MASK                                                                 0x20000000L
21364 #define GDS_GWS_RESET0__RESOURCE30_RESET_MASK                                                                 0x40000000L
21365 #define GDS_GWS_RESET0__RESOURCE31_RESET_MASK                                                                 0x80000000L
21366 //GDS_GWS_RESET1
21367 #define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT                                                               0x0
21368 #define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT                                                               0x1
21369 #define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT                                                               0x2
21370 #define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT                                                               0x3
21371 #define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT                                                               0x4
21372 #define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT                                                               0x5
21373 #define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT                                                               0x6
21374 #define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT                                                               0x7
21375 #define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT                                                               0x8
21376 #define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT                                                               0x9
21377 #define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT                                                               0xa
21378 #define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT                                                               0xb
21379 #define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT                                                               0xc
21380 #define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT                                                               0xd
21381 #define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT                                                               0xe
21382 #define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT                                                               0xf
21383 #define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT                                                               0x10
21384 #define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT                                                               0x11
21385 #define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT                                                               0x12
21386 #define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT                                                               0x13
21387 #define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT                                                               0x14
21388 #define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT                                                               0x15
21389 #define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT                                                               0x16
21390 #define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT                                                               0x17
21391 #define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT                                                               0x18
21392 #define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT                                                               0x19
21393 #define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT                                                               0x1a
21394 #define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT                                                               0x1b
21395 #define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT                                                               0x1c
21396 #define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT                                                               0x1d
21397 #define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT                                                               0x1e
21398 #define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT                                                               0x1f
21399 #define GDS_GWS_RESET1__RESOURCE32_RESET_MASK                                                                 0x00000001L
21400 #define GDS_GWS_RESET1__RESOURCE33_RESET_MASK                                                                 0x00000002L
21401 #define GDS_GWS_RESET1__RESOURCE34_RESET_MASK                                                                 0x00000004L
21402 #define GDS_GWS_RESET1__RESOURCE35_RESET_MASK                                                                 0x00000008L
21403 #define GDS_GWS_RESET1__RESOURCE36_RESET_MASK                                                                 0x00000010L
21404 #define GDS_GWS_RESET1__RESOURCE37_RESET_MASK                                                                 0x00000020L
21405 #define GDS_GWS_RESET1__RESOURCE38_RESET_MASK                                                                 0x00000040L
21406 #define GDS_GWS_RESET1__RESOURCE39_RESET_MASK                                                                 0x00000080L
21407 #define GDS_GWS_RESET1__RESOURCE40_RESET_MASK                                                                 0x00000100L
21408 #define GDS_GWS_RESET1__RESOURCE41_RESET_MASK                                                                 0x00000200L
21409 #define GDS_GWS_RESET1__RESOURCE42_RESET_MASK                                                                 0x00000400L
21410 #define GDS_GWS_RESET1__RESOURCE43_RESET_MASK                                                                 0x00000800L
21411 #define GDS_GWS_RESET1__RESOURCE44_RESET_MASK                                                                 0x00001000L
21412 #define GDS_GWS_RESET1__RESOURCE45_RESET_MASK                                                                 0x00002000L
21413 #define GDS_GWS_RESET1__RESOURCE46_RESET_MASK                                                                 0x00004000L
21414 #define GDS_GWS_RESET1__RESOURCE47_RESET_MASK                                                                 0x00008000L
21415 #define GDS_GWS_RESET1__RESOURCE48_RESET_MASK                                                                 0x00010000L
21416 #define GDS_GWS_RESET1__RESOURCE49_RESET_MASK                                                                 0x00020000L
21417 #define GDS_GWS_RESET1__RESOURCE50_RESET_MASK                                                                 0x00040000L
21418 #define GDS_GWS_RESET1__RESOURCE51_RESET_MASK                                                                 0x00080000L
21419 #define GDS_GWS_RESET1__RESOURCE52_RESET_MASK                                                                 0x00100000L
21420 #define GDS_GWS_RESET1__RESOURCE53_RESET_MASK                                                                 0x00200000L
21421 #define GDS_GWS_RESET1__RESOURCE54_RESET_MASK                                                                 0x00400000L
21422 #define GDS_GWS_RESET1__RESOURCE55_RESET_MASK                                                                 0x00800000L
21423 #define GDS_GWS_RESET1__RESOURCE56_RESET_MASK                                                                 0x01000000L
21424 #define GDS_GWS_RESET1__RESOURCE57_RESET_MASK                                                                 0x02000000L
21425 #define GDS_GWS_RESET1__RESOURCE58_RESET_MASK                                                                 0x04000000L
21426 #define GDS_GWS_RESET1__RESOURCE59_RESET_MASK                                                                 0x08000000L
21427 #define GDS_GWS_RESET1__RESOURCE60_RESET_MASK                                                                 0x10000000L
21428 #define GDS_GWS_RESET1__RESOURCE61_RESET_MASK                                                                 0x20000000L
21429 #define GDS_GWS_RESET1__RESOURCE62_RESET_MASK                                                                 0x40000000L
21430 #define GDS_GWS_RESET1__RESOURCE63_RESET_MASK                                                                 0x80000000L
21431 //GDS_GWS_RESOURCE_RESET
21432 #define GDS_GWS_RESOURCE_RESET__RESET__SHIFT                                                                  0x0
21433 #define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT                                                            0x8
21434 #define GDS_GWS_RESOURCE_RESET__UNUSED__SHIFT                                                                 0x10
21435 #define GDS_GWS_RESOURCE_RESET__RESET_MASK                                                                    0x00000001L
21436 #define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK                                                              0x0000FF00L
21437 #define GDS_GWS_RESOURCE_RESET__UNUSED_MASK                                                                   0xFFFF0000L
21438 //GDS_COMPUTE_MAX_WAVE_ID
21439 #define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT                                                           0x0
21440 #define GDS_COMPUTE_MAX_WAVE_ID__UNUSED__SHIFT                                                                0xc
21441 #define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK                                                             0x00000FFFL
21442 #define GDS_COMPUTE_MAX_WAVE_ID__UNUSED_MASK                                                                  0xFFFFF000L
21443 //GDS_OA_RESET_MASK
21444 #define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT                                                       0x0
21445 #define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT                                                       0x1
21446 #define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT                                                                0x2
21447 #define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET__SHIFT                                                        0x3
21448 #define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT                                                             0x4
21449 #define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT                                                             0x5
21450 #define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT                                                             0x6
21451 #define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT                                                             0x7
21452 #define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT                                                             0x8
21453 #define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT                                                             0x9
21454 #define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT                                                             0xa
21455 #define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT                                                             0xb
21456 #define GDS_OA_RESET_MASK__UNUSED1__SHIFT                                                                     0xc
21457 #define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK                                                         0x00000001L
21458 #define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK                                                         0x00000002L
21459 #define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK                                                                  0x00000004L
21460 #define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET_MASK                                                          0x00000008L
21461 #define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK                                                               0x00000010L
21462 #define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK                                                               0x00000020L
21463 #define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK                                                               0x00000040L
21464 #define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK                                                               0x00000080L
21465 #define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK                                                               0x00000100L
21466 #define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK                                                               0x00000200L
21467 #define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK                                                               0x00000400L
21468 #define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK                                                               0x00000800L
21469 #define GDS_OA_RESET_MASK__UNUSED1_MASK                                                                       0xFFFFF000L
21470 //GDS_OA_RESET
21471 #define GDS_OA_RESET__RESET__SHIFT                                                                            0x0
21472 #define GDS_OA_RESET__PIPE_ID__SHIFT                                                                          0x8
21473 #define GDS_OA_RESET__UNUSED__SHIFT                                                                           0x10
21474 #define GDS_OA_RESET__RESET_MASK                                                                              0x00000001L
21475 #define GDS_OA_RESET__PIPE_ID_MASK                                                                            0x0000FF00L
21476 #define GDS_OA_RESET__UNUSED_MASK                                                                             0xFFFF0000L
21477 //GDS_ENHANCE2
21478 #define GDS_ENHANCE2__MISC__SHIFT                                                                             0x0
21479 #define GDS_ENHANCE2__RD_BUF_TAG_MISS__SHIFT                                                                  0x12
21480 #define GDS_ENHANCE2__GDSA_PC_CGTS_DIS__SHIFT                                                                 0x13
21481 #define GDS_ENHANCE2__GDSO_PC_CGTS_DIS__SHIFT                                                                 0x14
21482 #define GDS_ENHANCE2__WD_GDS_CSB_OVERRIDE__SHIFT                                                              0x15
21483 #define GDS_ENHANCE2__GDS_CLK_ENHANCE_DIS__SHIFT                                                              0x16
21484 #define GDS_ENHANCE2__DISABLE_LOGIC_ID_CLAMP__SHIFT                                                           0x17
21485 #define GDS_ENHANCE2__UNUSED__SHIFT                                                                           0x18
21486 #define GDS_ENHANCE2__MISC_MASK                                                                               0x0003FFFFL
21487 #define GDS_ENHANCE2__RD_BUF_TAG_MISS_MASK                                                                    0x00040000L
21488 #define GDS_ENHANCE2__GDSA_PC_CGTS_DIS_MASK                                                                   0x00080000L
21489 #define GDS_ENHANCE2__GDSO_PC_CGTS_DIS_MASK                                                                   0x00100000L
21490 #define GDS_ENHANCE2__WD_GDS_CSB_OVERRIDE_MASK                                                                0x00200000L
21491 #define GDS_ENHANCE2__GDS_CLK_ENHANCE_DIS_MASK                                                                0x00400000L
21492 #define GDS_ENHANCE2__DISABLE_LOGIC_ID_CLAMP_MASK                                                             0x00800000L
21493 #define GDS_ENHANCE2__UNUSED_MASK                                                                             0xFF000000L
21494 //GDS_OA_CGPG_RESTORE
21495 #define GDS_OA_CGPG_RESTORE__VMID__SHIFT                                                                      0x0
21496 #define GDS_OA_CGPG_RESTORE__MEID__SHIFT                                                                      0x8
21497 #define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT                                                                    0xc
21498 #define GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT                                                                   0x10
21499 #define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT                                                                    0x14
21500 #define GDS_OA_CGPG_RESTORE__VMID_MASK                                                                        0x000000FFL
21501 #define GDS_OA_CGPG_RESTORE__MEID_MASK                                                                        0x00000F00L
21502 #define GDS_OA_CGPG_RESTORE__PIPEID_MASK                                                                      0x0000F000L
21503 #define GDS_OA_CGPG_RESTORE__QUEUEID_MASK                                                                     0x000F0000L
21504 #define GDS_OA_CGPG_RESTORE__UNUSED_MASK                                                                      0xFFF00000L
21505 //GDS_CS_CTXSW_STATUS
21506 #define GDS_CS_CTXSW_STATUS__R__SHIFT                                                                         0x0
21507 #define GDS_CS_CTXSW_STATUS__W__SHIFT                                                                         0x1
21508 #define GDS_CS_CTXSW_STATUS__UNUSED__SHIFT                                                                    0x2
21509 #define GDS_CS_CTXSW_STATUS__R_MASK                                                                           0x00000001L
21510 #define GDS_CS_CTXSW_STATUS__W_MASK                                                                           0x00000002L
21511 #define GDS_CS_CTXSW_STATUS__UNUSED_MASK                                                                      0xFFFFFFFCL
21512 //GDS_CS_CTXSW_CNT0
21513 #define GDS_CS_CTXSW_CNT0__UPDN__SHIFT                                                                        0x0
21514 #define GDS_CS_CTXSW_CNT0__PTR__SHIFT                                                                         0x10
21515 #define GDS_CS_CTXSW_CNT0__UPDN_MASK                                                                          0x0000FFFFL
21516 #define GDS_CS_CTXSW_CNT0__PTR_MASK                                                                           0xFFFF0000L
21517 //GDS_CS_CTXSW_CNT1
21518 #define GDS_CS_CTXSW_CNT1__UPDN__SHIFT                                                                        0x0
21519 #define GDS_CS_CTXSW_CNT1__PTR__SHIFT                                                                         0x10
21520 #define GDS_CS_CTXSW_CNT1__UPDN_MASK                                                                          0x0000FFFFL
21521 #define GDS_CS_CTXSW_CNT1__PTR_MASK                                                                           0xFFFF0000L
21522 //GDS_CS_CTXSW_CNT2
21523 #define GDS_CS_CTXSW_CNT2__UPDN__SHIFT                                                                        0x0
21524 #define GDS_CS_CTXSW_CNT2__PTR__SHIFT                                                                         0x10
21525 #define GDS_CS_CTXSW_CNT2__UPDN_MASK                                                                          0x0000FFFFL
21526 #define GDS_CS_CTXSW_CNT2__PTR_MASK                                                                           0xFFFF0000L
21527 //GDS_CS_CTXSW_CNT3
21528 #define GDS_CS_CTXSW_CNT3__UPDN__SHIFT                                                                        0x0
21529 #define GDS_CS_CTXSW_CNT3__PTR__SHIFT                                                                         0x10
21530 #define GDS_CS_CTXSW_CNT3__UPDN_MASK                                                                          0x0000FFFFL
21531 #define GDS_CS_CTXSW_CNT3__PTR_MASK                                                                           0xFFFF0000L
21532 //GDS_GFX_CTXSW_STATUS
21533 #define GDS_GFX_CTXSW_STATUS__R__SHIFT                                                                        0x0
21534 #define GDS_GFX_CTXSW_STATUS__W__SHIFT                                                                        0x1
21535 #define GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT                                                                   0x2
21536 #define GDS_GFX_CTXSW_STATUS__R_MASK                                                                          0x00000001L
21537 #define GDS_GFX_CTXSW_STATUS__W_MASK                                                                          0x00000002L
21538 #define GDS_GFX_CTXSW_STATUS__UNUSED_MASK                                                                     0xFFFFFFFCL
21539 //GDS_VS_CTXSW_CNT0
21540 #define GDS_VS_CTXSW_CNT0__UPDN__SHIFT                                                                        0x0
21541 #define GDS_VS_CTXSW_CNT0__PTR__SHIFT                                                                         0x10
21542 #define GDS_VS_CTXSW_CNT0__UPDN_MASK                                                                          0x0000FFFFL
21543 #define GDS_VS_CTXSW_CNT0__PTR_MASK                                                                           0xFFFF0000L
21544 //GDS_VS_CTXSW_CNT1
21545 #define GDS_VS_CTXSW_CNT1__UPDN__SHIFT                                                                        0x0
21546 #define GDS_VS_CTXSW_CNT1__PTR__SHIFT                                                                         0x10
21547 #define GDS_VS_CTXSW_CNT1__UPDN_MASK                                                                          0x0000FFFFL
21548 #define GDS_VS_CTXSW_CNT1__PTR_MASK                                                                           0xFFFF0000L
21549 //GDS_VS_CTXSW_CNT2
21550 #define GDS_VS_CTXSW_CNT2__UPDN__SHIFT                                                                        0x0
21551 #define GDS_VS_CTXSW_CNT2__PTR__SHIFT                                                                         0x10
21552 #define GDS_VS_CTXSW_CNT2__UPDN_MASK                                                                          0x0000FFFFL
21553 #define GDS_VS_CTXSW_CNT2__PTR_MASK                                                                           0xFFFF0000L
21554 //GDS_VS_CTXSW_CNT3
21555 #define GDS_VS_CTXSW_CNT3__UPDN__SHIFT                                                                        0x0
21556 #define GDS_VS_CTXSW_CNT3__PTR__SHIFT                                                                         0x10
21557 #define GDS_VS_CTXSW_CNT3__UPDN_MASK                                                                          0x0000FFFFL
21558 #define GDS_VS_CTXSW_CNT3__PTR_MASK                                                                           0xFFFF0000L
21559 //GDS_PS_CTXSW_CNT0
21560 #define GDS_PS_CTXSW_CNT0__UPDN__SHIFT                                                                        0x0
21561 #define GDS_PS_CTXSW_CNT0__PTR__SHIFT                                                                         0x10
21562 #define GDS_PS_CTXSW_CNT0__UPDN_MASK                                                                          0x0000FFFFL
21563 #define GDS_PS_CTXSW_CNT0__PTR_MASK                                                                           0xFFFF0000L
21564 //GDS_PS_CTXSW_CNT1
21565 #define GDS_PS_CTXSW_CNT1__UPDN__SHIFT                                                                        0x0
21566 #define GDS_PS_CTXSW_CNT1__PTR__SHIFT                                                                         0x10
21567 #define GDS_PS_CTXSW_CNT1__UPDN_MASK                                                                          0x0000FFFFL
21568 #define GDS_PS_CTXSW_CNT1__PTR_MASK                                                                           0xFFFF0000L
21569 //GDS_PS_CTXSW_CNT2
21570 #define GDS_PS_CTXSW_CNT2__UPDN__SHIFT                                                                        0x0
21571 #define GDS_PS_CTXSW_CNT2__PTR__SHIFT                                                                         0x10
21572 #define GDS_PS_CTXSW_CNT2__UPDN_MASK                                                                          0x0000FFFFL
21573 #define GDS_PS_CTXSW_CNT2__PTR_MASK                                                                           0xFFFF0000L
21574 //GDS_PS_CTXSW_CNT3
21575 #define GDS_PS_CTXSW_CNT3__UPDN__SHIFT                                                                        0x0
21576 #define GDS_PS_CTXSW_CNT3__PTR__SHIFT                                                                         0x10
21577 #define GDS_PS_CTXSW_CNT3__UPDN_MASK                                                                          0x0000FFFFL
21578 #define GDS_PS_CTXSW_CNT3__PTR_MASK                                                                           0xFFFF0000L
21579 //GDS_PS_CTXSW_IDX
21580 #define GDS_PS_CTXSW_IDX__PACKER_ID__SHIFT                                                                    0x0
21581 #define GDS_PS_CTXSW_IDX__UNUSED__SHIFT                                                                       0x4
21582 #define GDS_PS_CTXSW_IDX__PACKER_ID_MASK                                                                      0x0000000FL
21583 #define GDS_PS_CTXSW_IDX__UNUSED_MASK                                                                         0xFFFFFFF0L
21584 //GDS_GS_CTXSW_CNT0
21585 #define GDS_GS_CTXSW_CNT0__UPDN__SHIFT                                                                        0x0
21586 #define GDS_GS_CTXSW_CNT0__PTR__SHIFT                                                                         0x10
21587 #define GDS_GS_CTXSW_CNT0__UPDN_MASK                                                                          0x0000FFFFL
21588 #define GDS_GS_CTXSW_CNT0__PTR_MASK                                                                           0xFFFF0000L
21589 //GDS_GS_CTXSW_CNT1
21590 #define GDS_GS_CTXSW_CNT1__UPDN__SHIFT                                                                        0x0
21591 #define GDS_GS_CTXSW_CNT1__PTR__SHIFT                                                                         0x10
21592 #define GDS_GS_CTXSW_CNT1__UPDN_MASK                                                                          0x0000FFFFL
21593 #define GDS_GS_CTXSW_CNT1__PTR_MASK                                                                           0xFFFF0000L
21594 //GDS_GS_CTXSW_CNT2
21595 #define GDS_GS_CTXSW_CNT2__UPDN__SHIFT                                                                        0x0
21596 #define GDS_GS_CTXSW_CNT2__PTR__SHIFT                                                                         0x10
21597 #define GDS_GS_CTXSW_CNT2__UPDN_MASK                                                                          0x0000FFFFL
21598 #define GDS_GS_CTXSW_CNT2__PTR_MASK                                                                           0xFFFF0000L
21599 //GDS_GS_CTXSW_CNT3
21600 #define GDS_GS_CTXSW_CNT3__UPDN__SHIFT                                                                        0x0
21601 #define GDS_GS_CTXSW_CNT3__PTR__SHIFT                                                                         0x10
21602 #define GDS_GS_CTXSW_CNT3__UPDN_MASK                                                                          0x0000FFFFL
21603 #define GDS_GS_CTXSW_CNT3__PTR_MASK                                                                           0xFFFF0000L
21604 
21605 
21606 // addressBlock: gc_gfxdec0
21607 //DB_RENDER_CONTROL
21608 #define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT                                                          0x0
21609 #define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT                                                        0x1
21610 #define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT                                                                  0x2
21611 #define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT                                                                0x3
21612 #define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT                                                          0x4
21613 #define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT                                                    0x5
21614 #define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT                                                      0x6
21615 #define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT                                                               0x7
21616 #define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT                                                                 0x8
21617 #define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT                                                           0xc
21618 #define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK                                                            0x00000001L
21619 #define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK                                                          0x00000002L
21620 #define DB_RENDER_CONTROL__DEPTH_COPY_MASK                                                                    0x00000004L
21621 #define DB_RENDER_CONTROL__STENCIL_COPY_MASK                                                                  0x00000008L
21622 #define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK                                                            0x00000010L
21623 #define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK                                                      0x00000020L
21624 #define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK                                                        0x00000040L
21625 #define DB_RENDER_CONTROL__COPY_CENTROID_MASK                                                                 0x00000080L
21626 #define DB_RENDER_CONTROL__COPY_SAMPLE_MASK                                                                   0x00000F00L
21627 #define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK                                                             0x00001000L
21628 //DB_COUNT_CONTROL
21629 #define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT                                                      0x0
21630 #define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT                                                         0x1
21631 #define DB_COUNT_CONTROL__DISABLE_CONSERVATIVE_ZPASS_COUNTS__SHIFT                                            0x2
21632 #define DB_COUNT_CONTROL__ENHANCED_CONSERVATIVE_ZPASS_COUNTS__SHIFT                                           0x3
21633 #define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT                                                                  0x4
21634 #define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT                                                                 0x8
21635 #define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT                                                                 0xc
21636 #define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT                                                                 0x10
21637 #define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT                                                                0x14
21638 #define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT                                                            0x18
21639 #define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT                                                             0x1c
21640 #define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK                                                        0x00000001L
21641 #define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK                                                           0x00000002L
21642 #define DB_COUNT_CONTROL__DISABLE_CONSERVATIVE_ZPASS_COUNTS_MASK                                              0x00000004L
21643 #define DB_COUNT_CONTROL__ENHANCED_CONSERVATIVE_ZPASS_COUNTS_MASK                                             0x00000008L
21644 #define DB_COUNT_CONTROL__SAMPLE_RATE_MASK                                                                    0x00000070L
21645 #define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK                                                                   0x00000F00L
21646 #define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK                                                                   0x0000F000L
21647 #define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK                                                                   0x000F0000L
21648 #define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK                                                                  0x00F00000L
21649 #define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK                                                              0x0F000000L
21650 #define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK                                                               0xF0000000L
21651 //DB_DEPTH_VIEW
21652 #define DB_DEPTH_VIEW__SLICE_START__SHIFT                                                                     0x0
21653 #define DB_DEPTH_VIEW__SLICE_START_HI__SHIFT                                                                  0xb
21654 #define DB_DEPTH_VIEW__SLICE_MAX__SHIFT                                                                       0xd
21655 #define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT                                                                     0x18
21656 #define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT                                                               0x19
21657 #define DB_DEPTH_VIEW__MIPID__SHIFT                                                                           0x1a
21658 #define DB_DEPTH_VIEW__SLICE_MAX_HI__SHIFT                                                                    0x1e
21659 #define DB_DEPTH_VIEW__SLICE_START_MASK                                                                       0x000007FFL
21660 #define DB_DEPTH_VIEW__SLICE_START_HI_MASK                                                                    0x00001800L
21661 #define DB_DEPTH_VIEW__SLICE_MAX_MASK                                                                         0x00FFE000L
21662 #define DB_DEPTH_VIEW__Z_READ_ONLY_MASK                                                                       0x01000000L
21663 #define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK                                                                 0x02000000L
21664 #define DB_DEPTH_VIEW__MIPID_MASK                                                                             0x3C000000L
21665 #define DB_DEPTH_VIEW__SLICE_MAX_HI_MASK                                                                      0xC0000000L
21666 //DB_RENDER_OVERRIDE
21667 #define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT                                                           0x0
21668 #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT                                                          0x2
21669 #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT                                                          0x4
21670 #define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT                                                       0x6
21671 #define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT                                                             0x7
21672 #define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT                                                       0x8
21673 #define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT                                                          0x9
21674 #define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT                                                           0xa
21675 #define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT                                                               0xb
21676 #define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT                                                         0xc
21677 #define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT                                                         0xd
21678 #define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT                                                    0xf
21679 #define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT                                                     0x10
21680 #define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT                                                           0x11
21681 #define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT                                                      0x12
21682 #define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT                                                         0x13
21683 #define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT                                                           0x15
21684 #define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT                                                    0x1a
21685 #define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT                                                              0x1b
21686 #define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT                                                        0x1c
21687 #define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT                                                              0x1d
21688 #define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT                                                        0x1e
21689 #define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT                                                       0x1f
21690 #define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK                                                             0x00000003L
21691 #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK                                                            0x0000000CL
21692 #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK                                                            0x00000030L
21693 #define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK                                                         0x00000040L
21694 #define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK                                                               0x00000080L
21695 #define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK                                                         0x00000100L
21696 #define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK                                                            0x00000200L
21697 #define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK                                                             0x00000400L
21698 #define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK                                                                 0x00000800L
21699 #define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK                                                           0x00001000L
21700 #define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK                                                           0x00006000L
21701 #define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK                                                      0x00008000L
21702 #define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK                                                       0x00010000L
21703 #define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK                                                             0x00020000L
21704 #define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK                                                        0x00040000L
21705 #define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK                                                           0x00180000L
21706 #define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK                                                             0x03E00000L
21707 #define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK                                                      0x04000000L
21708 #define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK                                                                0x08000000L
21709 #define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK                                                          0x10000000L
21710 #define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK                                                                0x20000000L
21711 #define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK                                                          0x40000000L
21712 #define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK                                                         0x80000000L
21713 //DB_RENDER_OVERRIDE2
21714 #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT                                              0x0
21715 #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT                                            0x2
21716 #define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT                                       0x5
21717 #define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT                                        0x6
21718 #define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT                                               0x7
21719 #define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT                                                     0x8
21720 #define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT                                                         0x9
21721 #define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT                                           0xa
21722 #define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT                                                 0xb
21723 #define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT                                                                 0xc
21724 #define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT                                                              0xf
21725 #define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT                                                              0x12
21726 #define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT                                                           0x15
21727 #define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT                                                         0x16
21728 #define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT                                                         0x17
21729 #define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL__SHIFT                                               0x19
21730 #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK                                                0x00000003L
21731 #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK                                              0x0000001CL
21732 #define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK                                         0x00000020L
21733 #define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK                                          0x00000040L
21734 #define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK                                                 0x00000080L
21735 #define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK                                                       0x00000100L
21736 #define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK                                                           0x00000200L
21737 #define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK                                             0x00000400L
21738 #define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK                                                   0x00000800L
21739 #define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK                                                                   0x00007000L
21740 #define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK                                                                0x00038000L
21741 #define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK                                                                0x001C0000L
21742 #define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK                                                             0x00200000L
21743 #define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK                                                           0x00400000L
21744 #define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK                                                           0x00800000L
21745 #define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL_MASK                                                 0x02000000L
21746 //DB_HTILE_DATA_BASE
21747 #define DB_HTILE_DATA_BASE__BASE_256B__SHIFT                                                                  0x0
21748 #define DB_HTILE_DATA_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
21749 //DB_DEPTH_SIZE_XY
21750 #define DB_DEPTH_SIZE_XY__X_MAX__SHIFT                                                                        0x0
21751 #define DB_DEPTH_SIZE_XY__Y_MAX__SHIFT                                                                        0x10
21752 #define DB_DEPTH_SIZE_XY__X_MAX_MASK                                                                          0x00003FFFL
21753 #define DB_DEPTH_SIZE_XY__Y_MAX_MASK                                                                          0x3FFF0000L
21754 //DB_DEPTH_BOUNDS_MIN
21755 #define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT                                                                       0x0
21756 #define DB_DEPTH_BOUNDS_MIN__MIN_MASK                                                                         0xFFFFFFFFL
21757 //DB_DEPTH_BOUNDS_MAX
21758 #define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT                                                                       0x0
21759 #define DB_DEPTH_BOUNDS_MAX__MAX_MASK                                                                         0xFFFFFFFFL
21760 //DB_STENCIL_CLEAR
21761 #define DB_STENCIL_CLEAR__CLEAR__SHIFT                                                                        0x0
21762 #define DB_STENCIL_CLEAR__CLEAR_MASK                                                                          0x000000FFL
21763 //DB_DEPTH_CLEAR
21764 #define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT                                                                    0x0
21765 #define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK                                                                      0xFFFFFFFFL
21766 //PA_SC_SCREEN_SCISSOR_TL
21767 #define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT                                                                  0x0
21768 #define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT                                                                  0x10
21769 #define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK                                                                    0x0000FFFFL
21770 #define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK                                                                    0xFFFF0000L
21771 //PA_SC_SCREEN_SCISSOR_BR
21772 #define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT                                                                  0x0
21773 #define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT                                                                  0x10
21774 #define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK                                                                    0x0000FFFFL
21775 #define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK                                                                    0xFFFF0000L
21776 //DB_DFSM_CONTROL
21777 #define DB_DFSM_CONTROL__PUNCHOUT_MODE__SHIFT                                                                 0x0
21778 #define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP__SHIFT                                                      0x2
21779 #define DB_DFSM_CONTROL__DISALLOW_OVERFLOW__SHIFT                                                             0x3
21780 #define DB_DFSM_CONTROL__PUNCHOUT_MODE_MASK                                                                   0x00000003L
21781 #define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP_MASK                                                        0x00000004L
21782 #define DB_DFSM_CONTROL__DISALLOW_OVERFLOW_MASK                                                               0x00000008L
21783 //DB_RESERVED_REG_2
21784 #define DB_RESERVED_REG_2__FIELD_1__SHIFT                                                                     0x0
21785 #define DB_RESERVED_REG_2__FIELD_2__SHIFT                                                                     0x4
21786 #define DB_RESERVED_REG_2__FIELD_3__SHIFT                                                                     0x8
21787 #define DB_RESERVED_REG_2__FIELD_4__SHIFT                                                                     0xd
21788 #define DB_RESERVED_REG_2__FIELD_5__SHIFT                                                                     0xf
21789 #define DB_RESERVED_REG_2__FIELD_6__SHIFT                                                                     0x11
21790 #define DB_RESERVED_REG_2__FIELD_7__SHIFT                                                                     0x13
21791 #define DB_RESERVED_REG_2__FIELD_8__SHIFT                                                                     0x1c
21792 #define DB_RESERVED_REG_2__FIELD_1_MASK                                                                       0x0000000FL
21793 #define DB_RESERVED_REG_2__FIELD_2_MASK                                                                       0x000000F0L
21794 #define DB_RESERVED_REG_2__FIELD_3_MASK                                                                       0x00001F00L
21795 #define DB_RESERVED_REG_2__FIELD_4_MASK                                                                       0x00006000L
21796 #define DB_RESERVED_REG_2__FIELD_5_MASK                                                                       0x00018000L
21797 #define DB_RESERVED_REG_2__FIELD_6_MASK                                                                       0x00060000L
21798 #define DB_RESERVED_REG_2__FIELD_7_MASK                                                                       0x00180000L
21799 #define DB_RESERVED_REG_2__FIELD_8_MASK                                                                       0xF0000000L
21800 //DB_Z_INFO
21801 #define DB_Z_INFO__FORMAT__SHIFT                                                                              0x0
21802 #define DB_Z_INFO__NUM_SAMPLES__SHIFT                                                                         0x2
21803 #define DB_Z_INFO__SW_MODE__SHIFT                                                                             0x4
21804 #define DB_Z_INFO__FAULT_BEHAVIOR__SHIFT                                                                      0x9
21805 #define DB_Z_INFO__ITERATE_FLUSH__SHIFT                                                                       0xb
21806 #define DB_Z_INFO__PARTIALLY_RESIDENT__SHIFT                                                                  0xc
21807 #define DB_Z_INFO__RESERVED_FIELD_1__SHIFT                                                                    0xd
21808 #define DB_Z_INFO__MAXMIP__SHIFT                                                                              0x10
21809 #define DB_Z_INFO__ITERATE_256__SHIFT                                                                         0x14
21810 #define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT                                                             0x17
21811 #define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT                                                                      0x1b
21812 #define DB_Z_INFO__READ_SIZE__SHIFT                                                                           0x1c
21813 #define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT                                                                 0x1d
21814 #define DB_Z_INFO__ZRANGE_PRECISION__SHIFT                                                                    0x1f
21815 #define DB_Z_INFO__FORMAT_MASK                                                                                0x00000003L
21816 #define DB_Z_INFO__NUM_SAMPLES_MASK                                                                           0x0000000CL
21817 #define DB_Z_INFO__SW_MODE_MASK                                                                               0x000001F0L
21818 #define DB_Z_INFO__FAULT_BEHAVIOR_MASK                                                                        0x00000600L
21819 #define DB_Z_INFO__ITERATE_FLUSH_MASK                                                                         0x00000800L
21820 #define DB_Z_INFO__PARTIALLY_RESIDENT_MASK                                                                    0x00001000L
21821 #define DB_Z_INFO__RESERVED_FIELD_1_MASK                                                                      0x0000E000L
21822 #define DB_Z_INFO__MAXMIP_MASK                                                                                0x000F0000L
21823 #define DB_Z_INFO__ITERATE_256_MASK                                                                           0x00100000L
21824 #define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK                                                               0x07800000L
21825 #define DB_Z_INFO__ALLOW_EXPCLEAR_MASK                                                                        0x08000000L
21826 #define DB_Z_INFO__READ_SIZE_MASK                                                                             0x10000000L
21827 #define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK                                                                   0x20000000L
21828 #define DB_Z_INFO__ZRANGE_PRECISION_MASK                                                                      0x80000000L
21829 //DB_STENCIL_INFO
21830 #define DB_STENCIL_INFO__FORMAT__SHIFT                                                                        0x0
21831 #define DB_STENCIL_INFO__SW_MODE__SHIFT                                                                       0x4
21832 #define DB_STENCIL_INFO__FAULT_BEHAVIOR__SHIFT                                                                0x9
21833 #define DB_STENCIL_INFO__ITERATE_FLUSH__SHIFT                                                                 0xb
21834 #define DB_STENCIL_INFO__PARTIALLY_RESIDENT__SHIFT                                                            0xc
21835 #define DB_STENCIL_INFO__RESERVED_FIELD_1__SHIFT                                                              0xd
21836 #define DB_STENCIL_INFO__ITERATE_256__SHIFT                                                                   0x14
21837 #define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT                                                                0x1b
21838 #define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT                                                          0x1d
21839 #define DB_STENCIL_INFO__FORMAT_MASK                                                                          0x00000001L
21840 #define DB_STENCIL_INFO__SW_MODE_MASK                                                                         0x000001F0L
21841 #define DB_STENCIL_INFO__FAULT_BEHAVIOR_MASK                                                                  0x00000600L
21842 #define DB_STENCIL_INFO__ITERATE_FLUSH_MASK                                                                   0x00000800L
21843 #define DB_STENCIL_INFO__PARTIALLY_RESIDENT_MASK                                                              0x00001000L
21844 #define DB_STENCIL_INFO__RESERVED_FIELD_1_MASK                                                                0x0000E000L
21845 #define DB_STENCIL_INFO__ITERATE_256_MASK                                                                     0x00100000L
21846 #define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK                                                                  0x08000000L
21847 #define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK                                                            0x20000000L
21848 //DB_Z_READ_BASE
21849 #define DB_Z_READ_BASE__BASE_256B__SHIFT                                                                      0x0
21850 #define DB_Z_READ_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
21851 //DB_STENCIL_READ_BASE
21852 #define DB_STENCIL_READ_BASE__BASE_256B__SHIFT                                                                0x0
21853 #define DB_STENCIL_READ_BASE__BASE_256B_MASK                                                                  0xFFFFFFFFL
21854 //DB_Z_WRITE_BASE
21855 #define DB_Z_WRITE_BASE__BASE_256B__SHIFT                                                                     0x0
21856 #define DB_Z_WRITE_BASE__BASE_256B_MASK                                                                       0xFFFFFFFFL
21857 //DB_STENCIL_WRITE_BASE
21858 #define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT                                                               0x0
21859 #define DB_STENCIL_WRITE_BASE__BASE_256B_MASK                                                                 0xFFFFFFFFL
21860 //DB_RESERVED_REG_1
21861 #define DB_RESERVED_REG_1__FIELD_1__SHIFT                                                                     0x0
21862 #define DB_RESERVED_REG_1__FIELD_2__SHIFT                                                                     0xb
21863 #define DB_RESERVED_REG_1__FIELD_1_MASK                                                                       0x000007FFL
21864 #define DB_RESERVED_REG_1__FIELD_2_MASK                                                                       0x003FF800L
21865 //DB_RESERVED_REG_3
21866 #define DB_RESERVED_REG_3__FIELD_1__SHIFT                                                                     0x0
21867 #define DB_RESERVED_REG_3__FIELD_1_MASK                                                                       0x003FFFFFL
21868 //DB_Z_READ_BASE_HI
21869 #define DB_Z_READ_BASE_HI__BASE_HI__SHIFT                                                                     0x0
21870 #define DB_Z_READ_BASE_HI__BASE_HI_MASK                                                                       0x000000FFL
21871 //DB_STENCIL_READ_BASE_HI
21872 #define DB_STENCIL_READ_BASE_HI__BASE_HI__SHIFT                                                               0x0
21873 #define DB_STENCIL_READ_BASE_HI__BASE_HI_MASK                                                                 0x000000FFL
21874 //DB_Z_WRITE_BASE_HI
21875 #define DB_Z_WRITE_BASE_HI__BASE_HI__SHIFT                                                                    0x0
21876 #define DB_Z_WRITE_BASE_HI__BASE_HI_MASK                                                                      0x000000FFL
21877 //DB_STENCIL_WRITE_BASE_HI
21878 #define DB_STENCIL_WRITE_BASE_HI__BASE_HI__SHIFT                                                              0x0
21879 #define DB_STENCIL_WRITE_BASE_HI__BASE_HI_MASK                                                                0x000000FFL
21880 //DB_HTILE_DATA_BASE_HI
21881 #define DB_HTILE_DATA_BASE_HI__BASE_HI__SHIFT                                                                 0x0
21882 #define DB_HTILE_DATA_BASE_HI__BASE_HI_MASK                                                                   0x000000FFL
21883 //DB_RMI_L2_CACHE_CONTROL
21884 #define DB_RMI_L2_CACHE_CONTROL__Z_WR_POLICY__SHIFT                                                           0x0
21885 #define DB_RMI_L2_CACHE_CONTROL__S_WR_POLICY__SHIFT                                                           0x2
21886 #define DB_RMI_L2_CACHE_CONTROL__HTILE_WR_POLICY__SHIFT                                                       0x4
21887 #define DB_RMI_L2_CACHE_CONTROL__ZPCPSD_WR_POLICY__SHIFT                                                      0x6
21888 #define DB_RMI_L2_CACHE_CONTROL__Z_RD_POLICY__SHIFT                                                           0x10
21889 #define DB_RMI_L2_CACHE_CONTROL__S_RD_POLICY__SHIFT                                                           0x12
21890 #define DB_RMI_L2_CACHE_CONTROL__HTILE_RD_POLICY__SHIFT                                                       0x14
21891 #define DB_RMI_L2_CACHE_CONTROL__Z_BIG_PAGE__SHIFT                                                            0x18
21892 #define DB_RMI_L2_CACHE_CONTROL__S_BIG_PAGE__SHIFT                                                            0x19
21893 #define DB_RMI_L2_CACHE_CONTROL__Z_WR_POLICY_MASK                                                             0x00000003L
21894 #define DB_RMI_L2_CACHE_CONTROL__S_WR_POLICY_MASK                                                             0x0000000CL
21895 #define DB_RMI_L2_CACHE_CONTROL__HTILE_WR_POLICY_MASK                                                         0x00000030L
21896 #define DB_RMI_L2_CACHE_CONTROL__ZPCPSD_WR_POLICY_MASK                                                        0x000000C0L
21897 #define DB_RMI_L2_CACHE_CONTROL__Z_RD_POLICY_MASK                                                             0x00030000L
21898 #define DB_RMI_L2_CACHE_CONTROL__S_RD_POLICY_MASK                                                             0x000C0000L
21899 #define DB_RMI_L2_CACHE_CONTROL__HTILE_RD_POLICY_MASK                                                         0x00300000L
21900 #define DB_RMI_L2_CACHE_CONTROL__Z_BIG_PAGE_MASK                                                              0x01000000L
21901 #define DB_RMI_L2_CACHE_CONTROL__S_BIG_PAGE_MASK                                                              0x02000000L
21902 //TA_BC_BASE_ADDR
21903 #define TA_BC_BASE_ADDR__ADDRESS__SHIFT                                                                       0x0
21904 #define TA_BC_BASE_ADDR__ADDRESS_MASK                                                                         0xFFFFFFFFL
21905 //TA_BC_BASE_ADDR_HI
21906 #define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT                                                                    0x0
21907 #define TA_BC_BASE_ADDR_HI__ADDRESS_MASK                                                                      0x000000FFL
21908 //COHER_DEST_BASE_HI_0
21909 #define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT                                                        0x0
21910 #define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK                                                          0x000000FFL
21911 //COHER_DEST_BASE_HI_1
21912 #define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT                                                        0x0
21913 #define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK                                                          0x000000FFL
21914 //COHER_DEST_BASE_HI_2
21915 #define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT                                                        0x0
21916 #define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK                                                          0x000000FFL
21917 //COHER_DEST_BASE_HI_3
21918 #define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT                                                        0x0
21919 #define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK                                                          0x000000FFL
21920 //COHER_DEST_BASE_2
21921 #define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT                                                              0x0
21922 #define COHER_DEST_BASE_2__DEST_BASE_256B_MASK                                                                0xFFFFFFFFL
21923 //COHER_DEST_BASE_3
21924 #define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT                                                              0x0
21925 #define COHER_DEST_BASE_3__DEST_BASE_256B_MASK                                                                0xFFFFFFFFL
21926 //PA_SC_WINDOW_OFFSET
21927 #define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT                                                           0x0
21928 #define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT                                                           0x10
21929 #define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK                                                             0x0000FFFFL
21930 #define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK                                                             0xFFFF0000L
21931 //PA_SC_WINDOW_SCISSOR_TL
21932 #define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT                                                                  0x0
21933 #define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT                                                                  0x10
21934 #define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                 0x1f
21935 #define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK                                                                    0x00007FFFL
21936 #define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK                                                                    0x7FFF0000L
21937 #define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK                                                   0x80000000L
21938 //PA_SC_WINDOW_SCISSOR_BR
21939 #define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT                                                                  0x0
21940 #define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT                                                                  0x10
21941 #define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK                                                                    0x00007FFFL
21942 #define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK                                                                    0x7FFF0000L
21943 //PA_SC_CLIPRECT_RULE
21944 #define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT                                                                 0x0
21945 #define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK                                                                   0x0000FFFFL
21946 //PA_SC_CLIPRECT_0_TL
21947 #define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT                                                                      0x0
21948 #define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT                                                                      0x10
21949 #define PA_SC_CLIPRECT_0_TL__TL_X_MASK                                                                        0x00007FFFL
21950 #define PA_SC_CLIPRECT_0_TL__TL_Y_MASK                                                                        0x7FFF0000L
21951 //PA_SC_CLIPRECT_0_BR
21952 #define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT                                                                      0x0
21953 #define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT                                                                      0x10
21954 #define PA_SC_CLIPRECT_0_BR__BR_X_MASK                                                                        0x00007FFFL
21955 #define PA_SC_CLIPRECT_0_BR__BR_Y_MASK                                                                        0x7FFF0000L
21956 //PA_SC_CLIPRECT_1_TL
21957 #define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT                                                                      0x0
21958 #define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT                                                                      0x10
21959 #define PA_SC_CLIPRECT_1_TL__TL_X_MASK                                                                        0x00007FFFL
21960 #define PA_SC_CLIPRECT_1_TL__TL_Y_MASK                                                                        0x7FFF0000L
21961 //PA_SC_CLIPRECT_1_BR
21962 #define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT                                                                      0x0
21963 #define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT                                                                      0x10
21964 #define PA_SC_CLIPRECT_1_BR__BR_X_MASK                                                                        0x00007FFFL
21965 #define PA_SC_CLIPRECT_1_BR__BR_Y_MASK                                                                        0x7FFF0000L
21966 //PA_SC_CLIPRECT_2_TL
21967 #define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT                                                                      0x0
21968 #define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT                                                                      0x10
21969 #define PA_SC_CLIPRECT_2_TL__TL_X_MASK                                                                        0x00007FFFL
21970 #define PA_SC_CLIPRECT_2_TL__TL_Y_MASK                                                                        0x7FFF0000L
21971 //PA_SC_CLIPRECT_2_BR
21972 #define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT                                                                      0x0
21973 #define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT                                                                      0x10
21974 #define PA_SC_CLIPRECT_2_BR__BR_X_MASK                                                                        0x00007FFFL
21975 #define PA_SC_CLIPRECT_2_BR__BR_Y_MASK                                                                        0x7FFF0000L
21976 //PA_SC_CLIPRECT_3_TL
21977 #define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT                                                                      0x0
21978 #define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT                                                                      0x10
21979 #define PA_SC_CLIPRECT_3_TL__TL_X_MASK                                                                        0x00007FFFL
21980 #define PA_SC_CLIPRECT_3_TL__TL_Y_MASK                                                                        0x7FFF0000L
21981 //PA_SC_CLIPRECT_3_BR
21982 #define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT                                                                      0x0
21983 #define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT                                                                      0x10
21984 #define PA_SC_CLIPRECT_3_BR__BR_X_MASK                                                                        0x00007FFFL
21985 #define PA_SC_CLIPRECT_3_BR__BR_Y_MASK                                                                        0x7FFF0000L
21986 //PA_SC_EDGERULE
21987 #define PA_SC_EDGERULE__ER_TRI__SHIFT                                                                         0x0
21988 #define PA_SC_EDGERULE__ER_POINT__SHIFT                                                                       0x4
21989 #define PA_SC_EDGERULE__ER_RECT__SHIFT                                                                        0x8
21990 #define PA_SC_EDGERULE__ER_LINE_LR__SHIFT                                                                     0xc
21991 #define PA_SC_EDGERULE__ER_LINE_RL__SHIFT                                                                     0x12
21992 #define PA_SC_EDGERULE__ER_LINE_TB__SHIFT                                                                     0x18
21993 #define PA_SC_EDGERULE__ER_LINE_BT__SHIFT                                                                     0x1c
21994 #define PA_SC_EDGERULE__ER_TRI_MASK                                                                           0x0000000FL
21995 #define PA_SC_EDGERULE__ER_POINT_MASK                                                                         0x000000F0L
21996 #define PA_SC_EDGERULE__ER_RECT_MASK                                                                          0x00000F00L
21997 #define PA_SC_EDGERULE__ER_LINE_LR_MASK                                                                       0x0003F000L
21998 #define PA_SC_EDGERULE__ER_LINE_RL_MASK                                                                       0x00FC0000L
21999 #define PA_SC_EDGERULE__ER_LINE_TB_MASK                                                                       0x0F000000L
22000 #define PA_SC_EDGERULE__ER_LINE_BT_MASK                                                                       0xF0000000L
22001 //PA_SU_HARDWARE_SCREEN_OFFSET
22002 #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT                                               0x0
22003 #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT                                               0x10
22004 #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK                                                 0x000001FFL
22005 #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK                                                 0x01FF0000L
22006 //CB_TARGET_MASK
22007 #define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT                                                                 0x0
22008 #define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT                                                                 0x4
22009 #define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT                                                                 0x8
22010 #define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT                                                                 0xc
22011 #define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT                                                                 0x10
22012 #define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT                                                                 0x14
22013 #define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT                                                                 0x18
22014 #define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT                                                                 0x1c
22015 #define CB_TARGET_MASK__TARGET0_ENABLE_MASK                                                                   0x0000000FL
22016 #define CB_TARGET_MASK__TARGET1_ENABLE_MASK                                                                   0x000000F0L
22017 #define CB_TARGET_MASK__TARGET2_ENABLE_MASK                                                                   0x00000F00L
22018 #define CB_TARGET_MASK__TARGET3_ENABLE_MASK                                                                   0x0000F000L
22019 #define CB_TARGET_MASK__TARGET4_ENABLE_MASK                                                                   0x000F0000L
22020 #define CB_TARGET_MASK__TARGET5_ENABLE_MASK                                                                   0x00F00000L
22021 #define CB_TARGET_MASK__TARGET6_ENABLE_MASK                                                                   0x0F000000L
22022 #define CB_TARGET_MASK__TARGET7_ENABLE_MASK                                                                   0xF0000000L
22023 //CB_SHADER_MASK
22024 #define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT                                                                 0x0
22025 #define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT                                                                 0x4
22026 #define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT                                                                 0x8
22027 #define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT                                                                 0xc
22028 #define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT                                                                 0x10
22029 #define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT                                                                 0x14
22030 #define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT                                                                 0x18
22031 #define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT                                                                 0x1c
22032 #define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK                                                                   0x0000000FL
22033 #define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK                                                                   0x000000F0L
22034 #define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK                                                                   0x00000F00L
22035 #define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK                                                                   0x0000F000L
22036 #define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK                                                                   0x000F0000L
22037 #define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK                                                                   0x00F00000L
22038 #define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK                                                                   0x0F000000L
22039 #define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK                                                                   0xF0000000L
22040 //PA_SC_GENERIC_SCISSOR_TL
22041 #define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT                                                                 0x0
22042 #define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT                                                                 0x10
22043 #define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
22044 #define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK                                                                   0x00007FFFL
22045 #define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK                                                                   0x7FFF0000L
22046 #define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
22047 //PA_SC_GENERIC_SCISSOR_BR
22048 #define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT                                                                 0x0
22049 #define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT                                                                 0x10
22050 #define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK                                                                   0x00007FFFL
22051 #define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK                                                                   0x7FFF0000L
22052 //COHER_DEST_BASE_0
22053 #define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT                                                              0x0
22054 #define COHER_DEST_BASE_0__DEST_BASE_256B_MASK                                                                0xFFFFFFFFL
22055 //COHER_DEST_BASE_1
22056 #define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT                                                              0x0
22057 #define COHER_DEST_BASE_1__DEST_BASE_256B_MASK                                                                0xFFFFFFFFL
22058 //PA_SC_VPORT_SCISSOR_0_TL
22059 #define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT                                                                 0x0
22060 #define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT                                                                 0x10
22061 #define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
22062 #define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK                                                                   0x00007FFFL
22063 #define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK                                                                   0x7FFF0000L
22064 #define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
22065 //PA_SC_VPORT_SCISSOR_0_BR
22066 #define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT                                                                 0x0
22067 #define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT                                                                 0x10
22068 #define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK                                                                   0x00007FFFL
22069 #define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK                                                                   0x7FFF0000L
22070 //PA_SC_VPORT_SCISSOR_1_TL
22071 #define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT                                                                 0x0
22072 #define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT                                                                 0x10
22073 #define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
22074 #define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK                                                                   0x00007FFFL
22075 #define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK                                                                   0x7FFF0000L
22076 #define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
22077 //PA_SC_VPORT_SCISSOR_1_BR
22078 #define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT                                                                 0x0
22079 #define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT                                                                 0x10
22080 #define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK                                                                   0x00007FFFL
22081 #define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK                                                                   0x7FFF0000L
22082 //PA_SC_VPORT_SCISSOR_2_TL
22083 #define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT                                                                 0x0
22084 #define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT                                                                 0x10
22085 #define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
22086 #define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK                                                                   0x00007FFFL
22087 #define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK                                                                   0x7FFF0000L
22088 #define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
22089 //PA_SC_VPORT_SCISSOR_2_BR
22090 #define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT                                                                 0x0
22091 #define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT                                                                 0x10
22092 #define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK                                                                   0x00007FFFL
22093 #define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK                                                                   0x7FFF0000L
22094 //PA_SC_VPORT_SCISSOR_3_TL
22095 #define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT                                                                 0x0
22096 #define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT                                                                 0x10
22097 #define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
22098 #define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK                                                                   0x00007FFFL
22099 #define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK                                                                   0x7FFF0000L
22100 #define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
22101 //PA_SC_VPORT_SCISSOR_3_BR
22102 #define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT                                                                 0x0
22103 #define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT                                                                 0x10
22104 #define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK                                                                   0x00007FFFL
22105 #define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK                                                                   0x7FFF0000L
22106 //PA_SC_VPORT_SCISSOR_4_TL
22107 #define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT                                                                 0x0
22108 #define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT                                                                 0x10
22109 #define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
22110 #define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK                                                                   0x00007FFFL
22111 #define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK                                                                   0x7FFF0000L
22112 #define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
22113 //PA_SC_VPORT_SCISSOR_4_BR
22114 #define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT                                                                 0x0
22115 #define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT                                                                 0x10
22116 #define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK                                                                   0x00007FFFL
22117 #define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK                                                                   0x7FFF0000L
22118 //PA_SC_VPORT_SCISSOR_5_TL
22119 #define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT                                                                 0x0
22120 #define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT                                                                 0x10
22121 #define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
22122 #define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK                                                                   0x00007FFFL
22123 #define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK                                                                   0x7FFF0000L
22124 #define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
22125 //PA_SC_VPORT_SCISSOR_5_BR
22126 #define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT                                                                 0x0
22127 #define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT                                                                 0x10
22128 #define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK                                                                   0x00007FFFL
22129 #define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK                                                                   0x7FFF0000L
22130 //PA_SC_VPORT_SCISSOR_6_TL
22131 #define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT                                                                 0x0
22132 #define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT                                                                 0x10
22133 #define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
22134 #define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK                                                                   0x00007FFFL
22135 #define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK                                                                   0x7FFF0000L
22136 #define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
22137 //PA_SC_VPORT_SCISSOR_6_BR
22138 #define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT                                                                 0x0
22139 #define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT                                                                 0x10
22140 #define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK                                                                   0x00007FFFL
22141 #define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK                                                                   0x7FFF0000L
22142 //PA_SC_VPORT_SCISSOR_7_TL
22143 #define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT                                                                 0x0
22144 #define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT                                                                 0x10
22145 #define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
22146 #define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK                                                                   0x00007FFFL
22147 #define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK                                                                   0x7FFF0000L
22148 #define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
22149 //PA_SC_VPORT_SCISSOR_7_BR
22150 #define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT                                                                 0x0
22151 #define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT                                                                 0x10
22152 #define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK                                                                   0x00007FFFL
22153 #define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK                                                                   0x7FFF0000L
22154 //PA_SC_VPORT_SCISSOR_8_TL
22155 #define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT                                                                 0x0
22156 #define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT                                                                 0x10
22157 #define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
22158 #define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK                                                                   0x00007FFFL
22159 #define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK                                                                   0x7FFF0000L
22160 #define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
22161 //PA_SC_VPORT_SCISSOR_8_BR
22162 #define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT                                                                 0x0
22163 #define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT                                                                 0x10
22164 #define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK                                                                   0x00007FFFL
22165 #define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK                                                                   0x7FFF0000L
22166 //PA_SC_VPORT_SCISSOR_9_TL
22167 #define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT                                                                 0x0
22168 #define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT                                                                 0x10
22169 #define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
22170 #define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK                                                                   0x00007FFFL
22171 #define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK                                                                   0x7FFF0000L
22172 #define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
22173 //PA_SC_VPORT_SCISSOR_9_BR
22174 #define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT                                                                 0x0
22175 #define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT                                                                 0x10
22176 #define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK                                                                   0x00007FFFL
22177 #define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK                                                                   0x7FFF0000L
22178 //PA_SC_VPORT_SCISSOR_10_TL
22179 #define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT                                                                0x0
22180 #define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT                                                                0x10
22181 #define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT                                               0x1f
22182 #define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK                                                                  0x00007FFFL
22183 #define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK                                                                  0x7FFF0000L
22184 #define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK                                                 0x80000000L
22185 //PA_SC_VPORT_SCISSOR_10_BR
22186 #define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT                                                                0x0
22187 #define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT                                                                0x10
22188 #define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK                                                                  0x00007FFFL
22189 #define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK                                                                  0x7FFF0000L
22190 //PA_SC_VPORT_SCISSOR_11_TL
22191 #define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT                                                                0x0
22192 #define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT                                                                0x10
22193 #define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT                                               0x1f
22194 #define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK                                                                  0x00007FFFL
22195 #define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK                                                                  0x7FFF0000L
22196 #define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK                                                 0x80000000L
22197 //PA_SC_VPORT_SCISSOR_11_BR
22198 #define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT                                                                0x0
22199 #define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT                                                                0x10
22200 #define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK                                                                  0x00007FFFL
22201 #define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK                                                                  0x7FFF0000L
22202 //PA_SC_VPORT_SCISSOR_12_TL
22203 #define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT                                                                0x0
22204 #define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT                                                                0x10
22205 #define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT                                               0x1f
22206 #define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK                                                                  0x00007FFFL
22207 #define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK                                                                  0x7FFF0000L
22208 #define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK                                                 0x80000000L
22209 //PA_SC_VPORT_SCISSOR_12_BR
22210 #define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT                                                                0x0
22211 #define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT                                                                0x10
22212 #define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK                                                                  0x00007FFFL
22213 #define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK                                                                  0x7FFF0000L
22214 //PA_SC_VPORT_SCISSOR_13_TL
22215 #define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT                                                                0x0
22216 #define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT                                                                0x10
22217 #define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT                                               0x1f
22218 #define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK                                                                  0x00007FFFL
22219 #define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK                                                                  0x7FFF0000L
22220 #define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK                                                 0x80000000L
22221 //PA_SC_VPORT_SCISSOR_13_BR
22222 #define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT                                                                0x0
22223 #define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT                                                                0x10
22224 #define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK                                                                  0x00007FFFL
22225 #define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK                                                                  0x7FFF0000L
22226 //PA_SC_VPORT_SCISSOR_14_TL
22227 #define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT                                                                0x0
22228 #define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT                                                                0x10
22229 #define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT                                               0x1f
22230 #define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK                                                                  0x00007FFFL
22231 #define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK                                                                  0x7FFF0000L
22232 #define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK                                                 0x80000000L
22233 //PA_SC_VPORT_SCISSOR_14_BR
22234 #define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT                                                                0x0
22235 #define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT                                                                0x10
22236 #define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK                                                                  0x00007FFFL
22237 #define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK                                                                  0x7FFF0000L
22238 //PA_SC_VPORT_SCISSOR_15_TL
22239 #define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT                                                                0x0
22240 #define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT                                                                0x10
22241 #define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT                                               0x1f
22242 #define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK                                                                  0x00007FFFL
22243 #define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK                                                                  0x7FFF0000L
22244 #define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK                                                 0x80000000L
22245 //PA_SC_VPORT_SCISSOR_15_BR
22246 #define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT                                                                0x0
22247 #define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT                                                                0x10
22248 #define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK                                                                  0x00007FFFL
22249 #define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK                                                                  0x7FFF0000L
22250 //PA_SC_VPORT_ZMIN_0
22251 #define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT                                                                 0x0
22252 #define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
22253 //PA_SC_VPORT_ZMAX_0
22254 #define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT                                                                 0x0
22255 #define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
22256 //PA_SC_VPORT_ZMIN_1
22257 #define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT                                                                 0x0
22258 #define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
22259 //PA_SC_VPORT_ZMAX_1
22260 #define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT                                                                 0x0
22261 #define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
22262 //PA_SC_VPORT_ZMIN_2
22263 #define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT                                                                 0x0
22264 #define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
22265 //PA_SC_VPORT_ZMAX_2
22266 #define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT                                                                 0x0
22267 #define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
22268 //PA_SC_VPORT_ZMIN_3
22269 #define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT                                                                 0x0
22270 #define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
22271 //PA_SC_VPORT_ZMAX_3
22272 #define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT                                                                 0x0
22273 #define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
22274 //PA_SC_VPORT_ZMIN_4
22275 #define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT                                                                 0x0
22276 #define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
22277 //PA_SC_VPORT_ZMAX_4
22278 #define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT                                                                 0x0
22279 #define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
22280 //PA_SC_VPORT_ZMIN_5
22281 #define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT                                                                 0x0
22282 #define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
22283 //PA_SC_VPORT_ZMAX_5
22284 #define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT                                                                 0x0
22285 #define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
22286 //PA_SC_VPORT_ZMIN_6
22287 #define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT                                                                 0x0
22288 #define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
22289 //PA_SC_VPORT_ZMAX_6
22290 #define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT                                                                 0x0
22291 #define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
22292 //PA_SC_VPORT_ZMIN_7
22293 #define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT                                                                 0x0
22294 #define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
22295 //PA_SC_VPORT_ZMAX_7
22296 #define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT                                                                 0x0
22297 #define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
22298 //PA_SC_VPORT_ZMIN_8
22299 #define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT                                                                 0x0
22300 #define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
22301 //PA_SC_VPORT_ZMAX_8
22302 #define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT                                                                 0x0
22303 #define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
22304 //PA_SC_VPORT_ZMIN_9
22305 #define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT                                                                 0x0
22306 #define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
22307 //PA_SC_VPORT_ZMAX_9
22308 #define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT                                                                 0x0
22309 #define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
22310 //PA_SC_VPORT_ZMIN_10
22311 #define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT                                                                0x0
22312 #define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK                                                                  0xFFFFFFFFL
22313 //PA_SC_VPORT_ZMAX_10
22314 #define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT                                                                0x0
22315 #define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK                                                                  0xFFFFFFFFL
22316 //PA_SC_VPORT_ZMIN_11
22317 #define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT                                                                0x0
22318 #define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK                                                                  0xFFFFFFFFL
22319 //PA_SC_VPORT_ZMAX_11
22320 #define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT                                                                0x0
22321 #define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK                                                                  0xFFFFFFFFL
22322 //PA_SC_VPORT_ZMIN_12
22323 #define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT                                                                0x0
22324 #define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK                                                                  0xFFFFFFFFL
22325 //PA_SC_VPORT_ZMAX_12
22326 #define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT                                                                0x0
22327 #define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK                                                                  0xFFFFFFFFL
22328 //PA_SC_VPORT_ZMIN_13
22329 #define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT                                                                0x0
22330 #define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK                                                                  0xFFFFFFFFL
22331 //PA_SC_VPORT_ZMAX_13
22332 #define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT                                                                0x0
22333 #define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK                                                                  0xFFFFFFFFL
22334 //PA_SC_VPORT_ZMIN_14
22335 #define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT                                                                0x0
22336 #define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK                                                                  0xFFFFFFFFL
22337 //PA_SC_VPORT_ZMAX_14
22338 #define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT                                                                0x0
22339 #define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK                                                                  0xFFFFFFFFL
22340 //PA_SC_VPORT_ZMIN_15
22341 #define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT                                                                0x0
22342 #define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK                                                                  0xFFFFFFFFL
22343 //PA_SC_VPORT_ZMAX_15
22344 #define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT                                                                0x0
22345 #define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK                                                                  0xFFFFFFFFL
22346 //PA_SC_RASTER_CONFIG
22347 #define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT                                                               0x0
22348 #define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT                                                               0x2
22349 #define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT                                                                  0x4
22350 #define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT                                                                   0x6
22351 #define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT                                                                   0x7
22352 #define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT                                                                   0x8
22353 #define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT                                                                  0xa
22354 #define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT                                                                  0xc
22355 #define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT                                                                 0xe
22356 #define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT                                                                    0x10
22357 #define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT                                                                   0x12
22358 #define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT                                                                   0x14
22359 #define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT                                                                    0x18
22360 #define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT                                                                   0x1a
22361 #define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT                                                                   0x1c
22362 #define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK                                                                 0x00000003L
22363 #define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK                                                                 0x0000000CL
22364 #define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK                                                                    0x00000030L
22365 #define PA_SC_RASTER_CONFIG__RB_XSEL_MASK                                                                     0x00000040L
22366 #define PA_SC_RASTER_CONFIG__RB_YSEL_MASK                                                                     0x00000080L
22367 #define PA_SC_RASTER_CONFIG__PKR_MAP_MASK                                                                     0x00000300L
22368 #define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK                                                                    0x00000C00L
22369 #define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK                                                                    0x00003000L
22370 #define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK                                                                   0x0000C000L
22371 #define PA_SC_RASTER_CONFIG__SC_MAP_MASK                                                                      0x00030000L
22372 #define PA_SC_RASTER_CONFIG__SC_XSEL_MASK                                                                     0x000C0000L
22373 #define PA_SC_RASTER_CONFIG__SC_YSEL_MASK                                                                     0x00300000L
22374 #define PA_SC_RASTER_CONFIG__SE_MAP_MASK                                                                      0x03000000L
22375 #define PA_SC_RASTER_CONFIG__SE_XSEL_MASK                                                                     0x0C000000L
22376 #define PA_SC_RASTER_CONFIG__SE_YSEL_MASK                                                                     0x30000000L
22377 //PA_SC_RASTER_CONFIG_1
22378 #define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT                                                             0x0
22379 #define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT                                                            0x2
22380 #define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT                                                            0x4
22381 #define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK                                                               0x00000003L
22382 #define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK                                                              0x0000000CL
22383 #define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK                                                              0x00000030L
22384 //PA_SC_SCREEN_EXTENT_CONTROL
22385 #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT                                                 0x0
22386 #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT                                                  0x2
22387 #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK                                                   0x00000003L
22388 #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK                                                    0x0000000CL
22389 //PA_SC_TILE_STEERING_OVERRIDE
22390 #define PA_SC_TILE_STEERING_OVERRIDE__ENABLE__SHIFT                                                           0x0
22391 #define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE__SHIFT                                                           0x1
22392 #define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE__SHIFT                                                    0x5
22393 #define PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING__SHIFT                               0x8
22394 #define PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT                                                           0xc
22395 #define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT                                                    0x10
22396 #define PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT                                                0x14
22397 #define PA_SC_TILE_STEERING_OVERRIDE__ENABLE_MASK                                                             0x00000001L
22398 #define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE_MASK                                                             0x00000006L
22399 #define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE_MASK                                                      0x00000060L
22400 #define PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING_MASK                                 0x00000100L
22401 #define PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK                                                             0x00003000L
22402 #define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK                                                      0x00030000L
22403 #define PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK                                                  0x00100000L
22404 //CP_PERFMON_CNTX_CNTL
22405 #define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT                                                           0x1f
22406 #define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK                                                             0x80000000L
22407 //CP_PIPEID
22408 #define CP_PIPEID__PIPE_ID__SHIFT                                                                             0x0
22409 #define CP_PIPEID__PIPE_ID_MASK                                                                               0x00000003L
22410 //CP_RINGID
22411 #define CP_RINGID__RINGID__SHIFT                                                                              0x0
22412 #define CP_RINGID__RINGID_MASK                                                                                0x00000003L
22413 //CP_VMID
22414 #define CP_VMID__VMID__SHIFT                                                                                  0x0
22415 #define CP_VMID__VMID_MASK                                                                                    0x0000000FL
22416 //PA_SC_RIGHT_VERT_GRID
22417 #define PA_SC_RIGHT_VERT_GRID__LEFT_QTR__SHIFT                                                                0x0
22418 #define PA_SC_RIGHT_VERT_GRID__LEFT_HALF__SHIFT                                                               0x8
22419 #define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF__SHIFT                                                              0x10
22420 #define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR__SHIFT                                                               0x18
22421 #define PA_SC_RIGHT_VERT_GRID__LEFT_QTR_MASK                                                                  0x000000FFL
22422 #define PA_SC_RIGHT_VERT_GRID__LEFT_HALF_MASK                                                                 0x0000FF00L
22423 #define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF_MASK                                                                0x00FF0000L
22424 #define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR_MASK                                                                 0xFF000000L
22425 //PA_SC_LEFT_VERT_GRID
22426 #define PA_SC_LEFT_VERT_GRID__LEFT_QTR__SHIFT                                                                 0x0
22427 #define PA_SC_LEFT_VERT_GRID__LEFT_HALF__SHIFT                                                                0x8
22428 #define PA_SC_LEFT_VERT_GRID__RIGHT_HALF__SHIFT                                                               0x10
22429 #define PA_SC_LEFT_VERT_GRID__RIGHT_QTR__SHIFT                                                                0x18
22430 #define PA_SC_LEFT_VERT_GRID__LEFT_QTR_MASK                                                                   0x000000FFL
22431 #define PA_SC_LEFT_VERT_GRID__LEFT_HALF_MASK                                                                  0x0000FF00L
22432 #define PA_SC_LEFT_VERT_GRID__RIGHT_HALF_MASK                                                                 0x00FF0000L
22433 #define PA_SC_LEFT_VERT_GRID__RIGHT_QTR_MASK                                                                  0xFF000000L
22434 //PA_SC_HORIZ_GRID
22435 #define PA_SC_HORIZ_GRID__TOP_QTR__SHIFT                                                                      0x0
22436 #define PA_SC_HORIZ_GRID__TOP_HALF__SHIFT                                                                     0x8
22437 #define PA_SC_HORIZ_GRID__BOT_HALF__SHIFT                                                                     0x10
22438 #define PA_SC_HORIZ_GRID__BOT_QTR__SHIFT                                                                      0x18
22439 #define PA_SC_HORIZ_GRID__TOP_QTR_MASK                                                                        0x000000FFL
22440 #define PA_SC_HORIZ_GRID__TOP_HALF_MASK                                                                       0x0000FF00L
22441 #define PA_SC_HORIZ_GRID__BOT_HALF_MASK                                                                       0x00FF0000L
22442 #define PA_SC_HORIZ_GRID__BOT_QTR_MASK                                                                        0xFF000000L
22443 //VGT_MAX_VTX_INDX
22444 #define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT                                                                     0x0
22445 #define VGT_MAX_VTX_INDX__MAX_INDX_MASK                                                                       0xFFFFFFFFL
22446 //VGT_MIN_VTX_INDX
22447 #define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT                                                                     0x0
22448 #define VGT_MIN_VTX_INDX__MIN_INDX_MASK                                                                       0xFFFFFFFFL
22449 //VGT_INDX_OFFSET
22450 #define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT                                                                   0x0
22451 #define VGT_INDX_OFFSET__INDX_OFFSET_MASK                                                                     0xFFFFFFFFL
22452 //VGT_MULTI_PRIM_IB_RESET_INDX
22453 #define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT                                                       0x0
22454 #define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK                                                         0xFFFFFFFFL
22455 //CB_RMI_GL2_CACHE_CONTROL
22456 #define CB_RMI_GL2_CACHE_CONTROL__CMASK_WR_POLICY__SHIFT                                                      0x0
22457 #define CB_RMI_GL2_CACHE_CONTROL__FMASK_WR_POLICY__SHIFT                                                      0x2
22458 #define CB_RMI_GL2_CACHE_CONTROL__DCC_WR_POLICY__SHIFT                                                        0x4
22459 #define CB_RMI_GL2_CACHE_CONTROL__COLOR_WR_POLICY__SHIFT                                                      0x6
22460 #define CB_RMI_GL2_CACHE_CONTROL__CMASK_RD_POLICY__SHIFT                                                      0x10
22461 #define CB_RMI_GL2_CACHE_CONTROL__FMASK_RD_POLICY__SHIFT                                                      0x12
22462 #define CB_RMI_GL2_CACHE_CONTROL__DCC_RD_POLICY__SHIFT                                                        0x14
22463 #define CB_RMI_GL2_CACHE_CONTROL__COLOR_RD_POLICY__SHIFT                                                      0x16
22464 #define CB_RMI_GL2_CACHE_CONTROL__FMASK_BIG_PAGE__SHIFT                                                       0x1e
22465 #define CB_RMI_GL2_CACHE_CONTROL__COLOR_BIG_PAGE__SHIFT                                                       0x1f
22466 #define CB_RMI_GL2_CACHE_CONTROL__CMASK_WR_POLICY_MASK                                                        0x00000003L
22467 #define CB_RMI_GL2_CACHE_CONTROL__FMASK_WR_POLICY_MASK                                                        0x0000000CL
22468 #define CB_RMI_GL2_CACHE_CONTROL__DCC_WR_POLICY_MASK                                                          0x00000030L
22469 #define CB_RMI_GL2_CACHE_CONTROL__COLOR_WR_POLICY_MASK                                                        0x000000C0L
22470 #define CB_RMI_GL2_CACHE_CONTROL__CMASK_RD_POLICY_MASK                                                        0x00030000L
22471 #define CB_RMI_GL2_CACHE_CONTROL__FMASK_RD_POLICY_MASK                                                        0x000C0000L
22472 #define CB_RMI_GL2_CACHE_CONTROL__DCC_RD_POLICY_MASK                                                          0x00300000L
22473 #define CB_RMI_GL2_CACHE_CONTROL__COLOR_RD_POLICY_MASK                                                        0x00C00000L
22474 #define CB_RMI_GL2_CACHE_CONTROL__FMASK_BIG_PAGE_MASK                                                         0x40000000L
22475 #define CB_RMI_GL2_CACHE_CONTROL__COLOR_BIG_PAGE_MASK                                                         0x80000000L
22476 //CB_BLEND_RED
22477 #define CB_BLEND_RED__BLEND_RED__SHIFT                                                                        0x0
22478 #define CB_BLEND_RED__BLEND_RED_MASK                                                                          0xFFFFFFFFL
22479 //CB_BLEND_GREEN
22480 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT                                                                    0x0
22481 #define CB_BLEND_GREEN__BLEND_GREEN_MASK                                                                      0xFFFFFFFFL
22482 //CB_BLEND_BLUE
22483 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT                                                                      0x0
22484 #define CB_BLEND_BLUE__BLEND_BLUE_MASK                                                                        0xFFFFFFFFL
22485 //CB_BLEND_ALPHA
22486 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT                                                                    0x0
22487 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK                                                                      0xFFFFFFFFL
22488 //CB_DCC_CONTROL
22489 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                                     0x0
22490 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT                                                   0x2
22491 #define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_AC01__SHIFT                                                   0x8
22492 #define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_SINGLE__SHIFT                                                 0x9
22493 #define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT                                                    0xa
22494 #define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_AC01__SHIFT                                                    0xc
22495 #define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_SINGLE__SHIFT                                                  0xd
22496 #define CB_DCC_CONTROL__ENABLE_ELIMFC_SKIP_OF_REG__SHIFT                                                      0xe
22497 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                       0x00000001L
22498 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK                                                     0x0000007CL
22499 #define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_AC01_MASK                                                     0x00000100L
22500 #define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_SINGLE_MASK                                                   0x00000200L
22501 #define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK                                                      0x00000400L
22502 #define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_AC01_MASK                                                      0x00001000L
22503 #define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_SINGLE_MASK                                                    0x00002000L
22504 #define CB_DCC_CONTROL__ENABLE_ELIMFC_SKIP_OF_REG_MASK                                                        0x00004000L
22505 //CB_COVERAGE_OUT_CONTROL
22506 #define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_ENABLE__SHIFT                                                   0x0
22507 #define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_MRT__SHIFT                                                      0x1
22508 #define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_CHANNEL__SHIFT                                                  0x4
22509 #define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_SAMPLES__SHIFT                                                  0x8
22510 #define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_ENABLE_MASK                                                     0x00000001L
22511 #define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_MRT_MASK                                                        0x0000000EL
22512 #define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_CHANNEL_MASK                                                    0x00000030L
22513 #define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_SAMPLES_MASK                                                    0x00000F00L
22514 //DB_STENCIL_CONTROL
22515 #define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT                                                                0x0
22516 #define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT                                                               0x4
22517 #define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT                                                               0x8
22518 #define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT                                                             0xc
22519 #define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT                                                            0x10
22520 #define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT                                                            0x14
22521 #define DB_STENCIL_CONTROL__STENCILFAIL_MASK                                                                  0x0000000FL
22522 #define DB_STENCIL_CONTROL__STENCILZPASS_MASK                                                                 0x000000F0L
22523 #define DB_STENCIL_CONTROL__STENCILZFAIL_MASK                                                                 0x00000F00L
22524 #define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK                                                               0x0000F000L
22525 #define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK                                                              0x000F0000L
22526 #define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK                                                              0x00F00000L
22527 //DB_STENCILREFMASK
22528 #define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT                                                              0x0
22529 #define DB_STENCILREFMASK__STENCILMASK__SHIFT                                                                 0x8
22530 #define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT                                                            0x10
22531 #define DB_STENCILREFMASK__STENCILOPVAL__SHIFT                                                                0x18
22532 #define DB_STENCILREFMASK__STENCILTESTVAL_MASK                                                                0x000000FFL
22533 #define DB_STENCILREFMASK__STENCILMASK_MASK                                                                   0x0000FF00L
22534 #define DB_STENCILREFMASK__STENCILWRITEMASK_MASK                                                              0x00FF0000L
22535 #define DB_STENCILREFMASK__STENCILOPVAL_MASK                                                                  0xFF000000L
22536 //DB_STENCILREFMASK_BF
22537 #define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT                                                        0x0
22538 #define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT                                                           0x8
22539 #define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT                                                      0x10
22540 #define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT                                                          0x18
22541 #define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK                                                          0x000000FFL
22542 #define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK                                                             0x0000FF00L
22543 #define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK                                                        0x00FF0000L
22544 #define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK                                                            0xFF000000L
22545 //PA_CL_VPORT_XSCALE
22546 #define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT                                                               0x0
22547 #define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK                                                                 0xFFFFFFFFL
22548 //PA_CL_VPORT_XOFFSET
22549 #define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT                                                             0x0
22550 #define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK                                                               0xFFFFFFFFL
22551 //PA_CL_VPORT_YSCALE
22552 #define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT                                                               0x0
22553 #define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK                                                                 0xFFFFFFFFL
22554 //PA_CL_VPORT_YOFFSET
22555 #define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT                                                             0x0
22556 #define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK                                                               0xFFFFFFFFL
22557 //PA_CL_VPORT_ZSCALE
22558 #define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT                                                               0x0
22559 #define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK                                                                 0xFFFFFFFFL
22560 //PA_CL_VPORT_ZOFFSET
22561 #define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT                                                             0x0
22562 #define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK                                                               0xFFFFFFFFL
22563 //PA_CL_VPORT_XSCALE_1
22564 #define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT                                                             0x0
22565 #define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
22566 //PA_CL_VPORT_XOFFSET_1
22567 #define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT                                                           0x0
22568 #define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
22569 //PA_CL_VPORT_YSCALE_1
22570 #define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT                                                             0x0
22571 #define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
22572 //PA_CL_VPORT_YOFFSET_1
22573 #define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT                                                           0x0
22574 #define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
22575 //PA_CL_VPORT_ZSCALE_1
22576 #define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT                                                             0x0
22577 #define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
22578 //PA_CL_VPORT_ZOFFSET_1
22579 #define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT                                                           0x0
22580 #define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
22581 //PA_CL_VPORT_XSCALE_2
22582 #define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT                                                             0x0
22583 #define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
22584 //PA_CL_VPORT_XOFFSET_2
22585 #define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT                                                           0x0
22586 #define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
22587 //PA_CL_VPORT_YSCALE_2
22588 #define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT                                                             0x0
22589 #define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
22590 //PA_CL_VPORT_YOFFSET_2
22591 #define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT                                                           0x0
22592 #define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
22593 //PA_CL_VPORT_ZSCALE_2
22594 #define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT                                                             0x0
22595 #define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
22596 //PA_CL_VPORT_ZOFFSET_2
22597 #define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT                                                           0x0
22598 #define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
22599 //PA_CL_VPORT_XSCALE_3
22600 #define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT                                                             0x0
22601 #define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
22602 //PA_CL_VPORT_XOFFSET_3
22603 #define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT                                                           0x0
22604 #define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
22605 //PA_CL_VPORT_YSCALE_3
22606 #define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT                                                             0x0
22607 #define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
22608 //PA_CL_VPORT_YOFFSET_3
22609 #define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT                                                           0x0
22610 #define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
22611 //PA_CL_VPORT_ZSCALE_3
22612 #define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT                                                             0x0
22613 #define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
22614 //PA_CL_VPORT_ZOFFSET_3
22615 #define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT                                                           0x0
22616 #define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
22617 //PA_CL_VPORT_XSCALE_4
22618 #define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT                                                             0x0
22619 #define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
22620 //PA_CL_VPORT_XOFFSET_4
22621 #define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT                                                           0x0
22622 #define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
22623 //PA_CL_VPORT_YSCALE_4
22624 #define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT                                                             0x0
22625 #define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
22626 //PA_CL_VPORT_YOFFSET_4
22627 #define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT                                                           0x0
22628 #define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
22629 //PA_CL_VPORT_ZSCALE_4
22630 #define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT                                                             0x0
22631 #define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
22632 //PA_CL_VPORT_ZOFFSET_4
22633 #define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT                                                           0x0
22634 #define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
22635 //PA_CL_VPORT_XSCALE_5
22636 #define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT                                                             0x0
22637 #define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
22638 //PA_CL_VPORT_XOFFSET_5
22639 #define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT                                                           0x0
22640 #define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
22641 //PA_CL_VPORT_YSCALE_5
22642 #define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT                                                             0x0
22643 #define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
22644 //PA_CL_VPORT_YOFFSET_5
22645 #define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT                                                           0x0
22646 #define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
22647 //PA_CL_VPORT_ZSCALE_5
22648 #define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT                                                             0x0
22649 #define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
22650 //PA_CL_VPORT_ZOFFSET_5
22651 #define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT                                                           0x0
22652 #define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
22653 //PA_CL_VPORT_XSCALE_6
22654 #define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT                                                             0x0
22655 #define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
22656 //PA_CL_VPORT_XOFFSET_6
22657 #define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT                                                           0x0
22658 #define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
22659 //PA_CL_VPORT_YSCALE_6
22660 #define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT                                                             0x0
22661 #define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
22662 //PA_CL_VPORT_YOFFSET_6
22663 #define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT                                                           0x0
22664 #define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
22665 //PA_CL_VPORT_ZSCALE_6
22666 #define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT                                                             0x0
22667 #define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
22668 //PA_CL_VPORT_ZOFFSET_6
22669 #define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT                                                           0x0
22670 #define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
22671 //PA_CL_VPORT_XSCALE_7
22672 #define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT                                                             0x0
22673 #define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
22674 //PA_CL_VPORT_XOFFSET_7
22675 #define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT                                                           0x0
22676 #define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
22677 //PA_CL_VPORT_YSCALE_7
22678 #define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT                                                             0x0
22679 #define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
22680 //PA_CL_VPORT_YOFFSET_7
22681 #define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT                                                           0x0
22682 #define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
22683 //PA_CL_VPORT_ZSCALE_7
22684 #define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT                                                             0x0
22685 #define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
22686 //PA_CL_VPORT_ZOFFSET_7
22687 #define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT                                                           0x0
22688 #define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
22689 //PA_CL_VPORT_XSCALE_8
22690 #define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT                                                             0x0
22691 #define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
22692 //PA_CL_VPORT_XOFFSET_8
22693 #define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT                                                           0x0
22694 #define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
22695 //PA_CL_VPORT_YSCALE_8
22696 #define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT                                                             0x0
22697 #define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
22698 //PA_CL_VPORT_YOFFSET_8
22699 #define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT                                                           0x0
22700 #define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
22701 //PA_CL_VPORT_ZSCALE_8
22702 #define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT                                                             0x0
22703 #define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
22704 //PA_CL_VPORT_ZOFFSET_8
22705 #define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT                                                           0x0
22706 #define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
22707 //PA_CL_VPORT_XSCALE_9
22708 #define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT                                                             0x0
22709 #define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
22710 //PA_CL_VPORT_XOFFSET_9
22711 #define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT                                                           0x0
22712 #define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
22713 //PA_CL_VPORT_YSCALE_9
22714 #define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT                                                             0x0
22715 #define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
22716 //PA_CL_VPORT_YOFFSET_9
22717 #define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT                                                           0x0
22718 #define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
22719 //PA_CL_VPORT_ZSCALE_9
22720 #define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT                                                             0x0
22721 #define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
22722 //PA_CL_VPORT_ZOFFSET_9
22723 #define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT                                                           0x0
22724 #define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
22725 //PA_CL_VPORT_XSCALE_10
22726 #define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT                                                            0x0
22727 #define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK                                                              0xFFFFFFFFL
22728 //PA_CL_VPORT_XOFFSET_10
22729 #define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT                                                          0x0
22730 #define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK                                                            0xFFFFFFFFL
22731 //PA_CL_VPORT_YSCALE_10
22732 #define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT                                                            0x0
22733 #define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK                                                              0xFFFFFFFFL
22734 //PA_CL_VPORT_YOFFSET_10
22735 #define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT                                                          0x0
22736 #define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK                                                            0xFFFFFFFFL
22737 //PA_CL_VPORT_ZSCALE_10
22738 #define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT                                                            0x0
22739 #define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK                                                              0xFFFFFFFFL
22740 //PA_CL_VPORT_ZOFFSET_10
22741 #define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT                                                          0x0
22742 #define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK                                                            0xFFFFFFFFL
22743 //PA_CL_VPORT_XSCALE_11
22744 #define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT                                                            0x0
22745 #define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK                                                              0xFFFFFFFFL
22746 //PA_CL_VPORT_XOFFSET_11
22747 #define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT                                                          0x0
22748 #define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK                                                            0xFFFFFFFFL
22749 //PA_CL_VPORT_YSCALE_11
22750 #define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT                                                            0x0
22751 #define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK                                                              0xFFFFFFFFL
22752 //PA_CL_VPORT_YOFFSET_11
22753 #define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT                                                          0x0
22754 #define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK                                                            0xFFFFFFFFL
22755 //PA_CL_VPORT_ZSCALE_11
22756 #define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT                                                            0x0
22757 #define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK                                                              0xFFFFFFFFL
22758 //PA_CL_VPORT_ZOFFSET_11
22759 #define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT                                                          0x0
22760 #define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK                                                            0xFFFFFFFFL
22761 //PA_CL_VPORT_XSCALE_12
22762 #define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT                                                            0x0
22763 #define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK                                                              0xFFFFFFFFL
22764 //PA_CL_VPORT_XOFFSET_12
22765 #define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT                                                          0x0
22766 #define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK                                                            0xFFFFFFFFL
22767 //PA_CL_VPORT_YSCALE_12
22768 #define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT                                                            0x0
22769 #define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK                                                              0xFFFFFFFFL
22770 //PA_CL_VPORT_YOFFSET_12
22771 #define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT                                                          0x0
22772 #define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK                                                            0xFFFFFFFFL
22773 //PA_CL_VPORT_ZSCALE_12
22774 #define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT                                                            0x0
22775 #define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK                                                              0xFFFFFFFFL
22776 //PA_CL_VPORT_ZOFFSET_12
22777 #define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT                                                          0x0
22778 #define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK                                                            0xFFFFFFFFL
22779 //PA_CL_VPORT_XSCALE_13
22780 #define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT                                                            0x0
22781 #define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK                                                              0xFFFFFFFFL
22782 //PA_CL_VPORT_XOFFSET_13
22783 #define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT                                                          0x0
22784 #define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK                                                            0xFFFFFFFFL
22785 //PA_CL_VPORT_YSCALE_13
22786 #define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT                                                            0x0
22787 #define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK                                                              0xFFFFFFFFL
22788 //PA_CL_VPORT_YOFFSET_13
22789 #define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT                                                          0x0
22790 #define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK                                                            0xFFFFFFFFL
22791 //PA_CL_VPORT_ZSCALE_13
22792 #define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT                                                            0x0
22793 #define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK                                                              0xFFFFFFFFL
22794 //PA_CL_VPORT_ZOFFSET_13
22795 #define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT                                                          0x0
22796 #define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK                                                            0xFFFFFFFFL
22797 //PA_CL_VPORT_XSCALE_14
22798 #define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT                                                            0x0
22799 #define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK                                                              0xFFFFFFFFL
22800 //PA_CL_VPORT_XOFFSET_14
22801 #define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT                                                          0x0
22802 #define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK                                                            0xFFFFFFFFL
22803 //PA_CL_VPORT_YSCALE_14
22804 #define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT                                                            0x0
22805 #define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK                                                              0xFFFFFFFFL
22806 //PA_CL_VPORT_YOFFSET_14
22807 #define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT                                                          0x0
22808 #define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK                                                            0xFFFFFFFFL
22809 //PA_CL_VPORT_ZSCALE_14
22810 #define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT                                                            0x0
22811 #define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK                                                              0xFFFFFFFFL
22812 //PA_CL_VPORT_ZOFFSET_14
22813 #define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT                                                          0x0
22814 #define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK                                                            0xFFFFFFFFL
22815 //PA_CL_VPORT_XSCALE_15
22816 #define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT                                                            0x0
22817 #define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK                                                              0xFFFFFFFFL
22818 //PA_CL_VPORT_XOFFSET_15
22819 #define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT                                                          0x0
22820 #define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK                                                            0xFFFFFFFFL
22821 //PA_CL_VPORT_YSCALE_15
22822 #define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT                                                            0x0
22823 #define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK                                                              0xFFFFFFFFL
22824 //PA_CL_VPORT_YOFFSET_15
22825 #define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT                                                          0x0
22826 #define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK                                                            0xFFFFFFFFL
22827 //PA_CL_VPORT_ZSCALE_15
22828 #define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT                                                            0x0
22829 #define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK                                                              0xFFFFFFFFL
22830 //PA_CL_VPORT_ZOFFSET_15
22831 #define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT                                                          0x0
22832 #define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK                                                            0xFFFFFFFFL
22833 //PA_CL_UCP_0_X
22834 #define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT                                                                   0x0
22835 #define PA_CL_UCP_0_X__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
22836 //PA_CL_UCP_0_Y
22837 #define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT                                                                   0x0
22838 #define PA_CL_UCP_0_Y__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
22839 //PA_CL_UCP_0_Z
22840 #define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT                                                                   0x0
22841 #define PA_CL_UCP_0_Z__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
22842 //PA_CL_UCP_0_W
22843 #define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT                                                                   0x0
22844 #define PA_CL_UCP_0_W__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
22845 //PA_CL_UCP_1_X
22846 #define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT                                                                   0x0
22847 #define PA_CL_UCP_1_X__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
22848 //PA_CL_UCP_1_Y
22849 #define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT                                                                   0x0
22850 #define PA_CL_UCP_1_Y__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
22851 //PA_CL_UCP_1_Z
22852 #define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT                                                                   0x0
22853 #define PA_CL_UCP_1_Z__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
22854 //PA_CL_UCP_1_W
22855 #define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT                                                                   0x0
22856 #define PA_CL_UCP_1_W__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
22857 //PA_CL_UCP_2_X
22858 #define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT                                                                   0x0
22859 #define PA_CL_UCP_2_X__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
22860 //PA_CL_UCP_2_Y
22861 #define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT                                                                   0x0
22862 #define PA_CL_UCP_2_Y__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
22863 //PA_CL_UCP_2_Z
22864 #define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT                                                                   0x0
22865 #define PA_CL_UCP_2_Z__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
22866 //PA_CL_UCP_2_W
22867 #define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT                                                                   0x0
22868 #define PA_CL_UCP_2_W__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
22869 //PA_CL_UCP_3_X
22870 #define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT                                                                   0x0
22871 #define PA_CL_UCP_3_X__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
22872 //PA_CL_UCP_3_Y
22873 #define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT                                                                   0x0
22874 #define PA_CL_UCP_3_Y__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
22875 //PA_CL_UCP_3_Z
22876 #define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT                                                                   0x0
22877 #define PA_CL_UCP_3_Z__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
22878 //PA_CL_UCP_3_W
22879 #define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT                                                                   0x0
22880 #define PA_CL_UCP_3_W__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
22881 //PA_CL_UCP_4_X
22882 #define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT                                                                   0x0
22883 #define PA_CL_UCP_4_X__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
22884 //PA_CL_UCP_4_Y
22885 #define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT                                                                   0x0
22886 #define PA_CL_UCP_4_Y__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
22887 //PA_CL_UCP_4_Z
22888 #define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT                                                                   0x0
22889 #define PA_CL_UCP_4_Z__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
22890 //PA_CL_UCP_4_W
22891 #define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT                                                                   0x0
22892 #define PA_CL_UCP_4_W__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
22893 //PA_CL_UCP_5_X
22894 #define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT                                                                   0x0
22895 #define PA_CL_UCP_5_X__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
22896 //PA_CL_UCP_5_Y
22897 #define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT                                                                   0x0
22898 #define PA_CL_UCP_5_Y__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
22899 //PA_CL_UCP_5_Z
22900 #define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT                                                                   0x0
22901 #define PA_CL_UCP_5_Z__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
22902 //PA_CL_UCP_5_W
22903 #define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT                                                                   0x0
22904 #define PA_CL_UCP_5_W__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
22905 //PA_CL_PROG_NEAR_CLIP_Z
22906 #define PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER__SHIFT                                                          0x0
22907 #define PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER_MASK                                                            0xFFFFFFFFL
22908 //SPI_PS_INPUT_CNTL_0
22909 #define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT                                                                    0x0
22910 #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT                                                               0x8
22911 #define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT                                                                0xa
22912 #define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT                                                                  0xd
22913 #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT                                                             0x11
22914 #define SPI_PS_INPUT_CNTL_0__DUP__SHIFT                                                                       0x12
22915 #define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT                                                          0x13
22916 #define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
22917 #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
22918 #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
22919 #define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT                                                               0x18
22920 #define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT                                                               0x19
22921 #define SPI_PS_INPUT_CNTL_0__OFFSET_MASK                                                                      0x0000003FL
22922 #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK                                                                 0x00000300L
22923 #define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK                                                                  0x00000400L
22924 #define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK                                                                    0x0001E000L
22925 #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK                                                               0x00020000L
22926 #define SPI_PS_INPUT_CNTL_0__DUP_MASK                                                                         0x00040000L
22927 #define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK                                                            0x00080000L
22928 #define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
22929 #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
22930 #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
22931 #define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK                                                                 0x01000000L
22932 #define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK                                                                 0x02000000L
22933 //SPI_PS_INPUT_CNTL_1
22934 #define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT                                                                    0x0
22935 #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT                                                               0x8
22936 #define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT                                                                0xa
22937 #define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT                                                                  0xd
22938 #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT                                                             0x11
22939 #define SPI_PS_INPUT_CNTL_1__DUP__SHIFT                                                                       0x12
22940 #define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT                                                          0x13
22941 #define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
22942 #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
22943 #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
22944 #define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT                                                               0x18
22945 #define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT                                                               0x19
22946 #define SPI_PS_INPUT_CNTL_1__OFFSET_MASK                                                                      0x0000003FL
22947 #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK                                                                 0x00000300L
22948 #define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK                                                                  0x00000400L
22949 #define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK                                                                    0x0001E000L
22950 #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK                                                               0x00020000L
22951 #define SPI_PS_INPUT_CNTL_1__DUP_MASK                                                                         0x00040000L
22952 #define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK                                                            0x00080000L
22953 #define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
22954 #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
22955 #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
22956 #define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK                                                                 0x01000000L
22957 #define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK                                                                 0x02000000L
22958 //SPI_PS_INPUT_CNTL_2
22959 #define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT                                                                    0x0
22960 #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT                                                               0x8
22961 #define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT                                                                0xa
22962 #define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT                                                                  0xd
22963 #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT                                                             0x11
22964 #define SPI_PS_INPUT_CNTL_2__DUP__SHIFT                                                                       0x12
22965 #define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT                                                          0x13
22966 #define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
22967 #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
22968 #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
22969 #define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT                                                               0x18
22970 #define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT                                                               0x19
22971 #define SPI_PS_INPUT_CNTL_2__OFFSET_MASK                                                                      0x0000003FL
22972 #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK                                                                 0x00000300L
22973 #define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK                                                                  0x00000400L
22974 #define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK                                                                    0x0001E000L
22975 #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK                                                               0x00020000L
22976 #define SPI_PS_INPUT_CNTL_2__DUP_MASK                                                                         0x00040000L
22977 #define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK                                                            0x00080000L
22978 #define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
22979 #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
22980 #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
22981 #define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK                                                                 0x01000000L
22982 #define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK                                                                 0x02000000L
22983 //SPI_PS_INPUT_CNTL_3
22984 #define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT                                                                    0x0
22985 #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT                                                               0x8
22986 #define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT                                                                0xa
22987 #define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT                                                                  0xd
22988 #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT                                                             0x11
22989 #define SPI_PS_INPUT_CNTL_3__DUP__SHIFT                                                                       0x12
22990 #define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT                                                          0x13
22991 #define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
22992 #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
22993 #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
22994 #define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT                                                               0x18
22995 #define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT                                                               0x19
22996 #define SPI_PS_INPUT_CNTL_3__OFFSET_MASK                                                                      0x0000003FL
22997 #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK                                                                 0x00000300L
22998 #define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK                                                                  0x00000400L
22999 #define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK                                                                    0x0001E000L
23000 #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK                                                               0x00020000L
23001 #define SPI_PS_INPUT_CNTL_3__DUP_MASK                                                                         0x00040000L
23002 #define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK                                                            0x00080000L
23003 #define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
23004 #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
23005 #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
23006 #define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK                                                                 0x01000000L
23007 #define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK                                                                 0x02000000L
23008 //SPI_PS_INPUT_CNTL_4
23009 #define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT                                                                    0x0
23010 #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT                                                               0x8
23011 #define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT                                                                0xa
23012 #define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT                                                                  0xd
23013 #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT                                                             0x11
23014 #define SPI_PS_INPUT_CNTL_4__DUP__SHIFT                                                                       0x12
23015 #define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT                                                          0x13
23016 #define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
23017 #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
23018 #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
23019 #define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT                                                               0x18
23020 #define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT                                                               0x19
23021 #define SPI_PS_INPUT_CNTL_4__OFFSET_MASK                                                                      0x0000003FL
23022 #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK                                                                 0x00000300L
23023 #define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK                                                                  0x00000400L
23024 #define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK                                                                    0x0001E000L
23025 #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK                                                               0x00020000L
23026 #define SPI_PS_INPUT_CNTL_4__DUP_MASK                                                                         0x00040000L
23027 #define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK                                                            0x00080000L
23028 #define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
23029 #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
23030 #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
23031 #define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK                                                                 0x01000000L
23032 #define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK                                                                 0x02000000L
23033 //SPI_PS_INPUT_CNTL_5
23034 #define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT                                                                    0x0
23035 #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT                                                               0x8
23036 #define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT                                                                0xa
23037 #define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT                                                                  0xd
23038 #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT                                                             0x11
23039 #define SPI_PS_INPUT_CNTL_5__DUP__SHIFT                                                                       0x12
23040 #define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT                                                          0x13
23041 #define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
23042 #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
23043 #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
23044 #define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT                                                               0x18
23045 #define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT                                                               0x19
23046 #define SPI_PS_INPUT_CNTL_5__OFFSET_MASK                                                                      0x0000003FL
23047 #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK                                                                 0x00000300L
23048 #define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK                                                                  0x00000400L
23049 #define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK                                                                    0x0001E000L
23050 #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK                                                               0x00020000L
23051 #define SPI_PS_INPUT_CNTL_5__DUP_MASK                                                                         0x00040000L
23052 #define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK                                                            0x00080000L
23053 #define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
23054 #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
23055 #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
23056 #define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK                                                                 0x01000000L
23057 #define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK                                                                 0x02000000L
23058 //SPI_PS_INPUT_CNTL_6
23059 #define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT                                                                    0x0
23060 #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT                                                               0x8
23061 #define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT                                                                0xa
23062 #define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT                                                                  0xd
23063 #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT                                                             0x11
23064 #define SPI_PS_INPUT_CNTL_6__DUP__SHIFT                                                                       0x12
23065 #define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT                                                          0x13
23066 #define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
23067 #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
23068 #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
23069 #define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT                                                               0x18
23070 #define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT                                                               0x19
23071 #define SPI_PS_INPUT_CNTL_6__OFFSET_MASK                                                                      0x0000003FL
23072 #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK                                                                 0x00000300L
23073 #define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK                                                                  0x00000400L
23074 #define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK                                                                    0x0001E000L
23075 #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK                                                               0x00020000L
23076 #define SPI_PS_INPUT_CNTL_6__DUP_MASK                                                                         0x00040000L
23077 #define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK                                                            0x00080000L
23078 #define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
23079 #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
23080 #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
23081 #define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK                                                                 0x01000000L
23082 #define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK                                                                 0x02000000L
23083 //SPI_PS_INPUT_CNTL_7
23084 #define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT                                                                    0x0
23085 #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT                                                               0x8
23086 #define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT                                                                0xa
23087 #define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT                                                                  0xd
23088 #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT                                                             0x11
23089 #define SPI_PS_INPUT_CNTL_7__DUP__SHIFT                                                                       0x12
23090 #define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT                                                          0x13
23091 #define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
23092 #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
23093 #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
23094 #define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT                                                               0x18
23095 #define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT                                                               0x19
23096 #define SPI_PS_INPUT_CNTL_7__OFFSET_MASK                                                                      0x0000003FL
23097 #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK                                                                 0x00000300L
23098 #define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK                                                                  0x00000400L
23099 #define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK                                                                    0x0001E000L
23100 #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK                                                               0x00020000L
23101 #define SPI_PS_INPUT_CNTL_7__DUP_MASK                                                                         0x00040000L
23102 #define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK                                                            0x00080000L
23103 #define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
23104 #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
23105 #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
23106 #define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK                                                                 0x01000000L
23107 #define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK                                                                 0x02000000L
23108 //SPI_PS_INPUT_CNTL_8
23109 #define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT                                                                    0x0
23110 #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT                                                               0x8
23111 #define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT                                                                0xa
23112 #define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT                                                                  0xd
23113 #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT                                                             0x11
23114 #define SPI_PS_INPUT_CNTL_8__DUP__SHIFT                                                                       0x12
23115 #define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT                                                          0x13
23116 #define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
23117 #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
23118 #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
23119 #define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT                                                               0x18
23120 #define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT                                                               0x19
23121 #define SPI_PS_INPUT_CNTL_8__OFFSET_MASK                                                                      0x0000003FL
23122 #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK                                                                 0x00000300L
23123 #define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK                                                                  0x00000400L
23124 #define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK                                                                    0x0001E000L
23125 #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK                                                               0x00020000L
23126 #define SPI_PS_INPUT_CNTL_8__DUP_MASK                                                                         0x00040000L
23127 #define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK                                                            0x00080000L
23128 #define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
23129 #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
23130 #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
23131 #define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK                                                                 0x01000000L
23132 #define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK                                                                 0x02000000L
23133 //SPI_PS_INPUT_CNTL_9
23134 #define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT                                                                    0x0
23135 #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT                                                               0x8
23136 #define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT                                                                0xa
23137 #define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT                                                                  0xd
23138 #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT                                                             0x11
23139 #define SPI_PS_INPUT_CNTL_9__DUP__SHIFT                                                                       0x12
23140 #define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT                                                          0x13
23141 #define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
23142 #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
23143 #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
23144 #define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT                                                               0x18
23145 #define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT                                                               0x19
23146 #define SPI_PS_INPUT_CNTL_9__OFFSET_MASK                                                                      0x0000003FL
23147 #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK                                                                 0x00000300L
23148 #define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK                                                                  0x00000400L
23149 #define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK                                                                    0x0001E000L
23150 #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK                                                               0x00020000L
23151 #define SPI_PS_INPUT_CNTL_9__DUP_MASK                                                                         0x00040000L
23152 #define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK                                                            0x00080000L
23153 #define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
23154 #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
23155 #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
23156 #define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK                                                                 0x01000000L
23157 #define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK                                                                 0x02000000L
23158 //SPI_PS_INPUT_CNTL_10
23159 #define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT                                                                   0x0
23160 #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT                                                              0x8
23161 #define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT                                                               0xa
23162 #define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT                                                                 0xd
23163 #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT                                                            0x11
23164 #define SPI_PS_INPUT_CNTL_10__DUP__SHIFT                                                                      0x12
23165 #define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT                                                         0x13
23166 #define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
23167 #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
23168 #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
23169 #define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT                                                              0x18
23170 #define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT                                                              0x19
23171 #define SPI_PS_INPUT_CNTL_10__OFFSET_MASK                                                                     0x0000003FL
23172 #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK                                                                0x00000300L
23173 #define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK                                                                 0x00000400L
23174 #define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK                                                                   0x0001E000L
23175 #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK                                                              0x00020000L
23176 #define SPI_PS_INPUT_CNTL_10__DUP_MASK                                                                        0x00040000L
23177 #define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK                                                           0x00080000L
23178 #define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
23179 #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
23180 #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
23181 #define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK                                                                0x01000000L
23182 #define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK                                                                0x02000000L
23183 //SPI_PS_INPUT_CNTL_11
23184 #define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT                                                                   0x0
23185 #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT                                                              0x8
23186 #define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT                                                               0xa
23187 #define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT                                                                 0xd
23188 #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT                                                            0x11
23189 #define SPI_PS_INPUT_CNTL_11__DUP__SHIFT                                                                      0x12
23190 #define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT                                                         0x13
23191 #define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
23192 #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
23193 #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
23194 #define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT                                                              0x18
23195 #define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT                                                              0x19
23196 #define SPI_PS_INPUT_CNTL_11__OFFSET_MASK                                                                     0x0000003FL
23197 #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK                                                                0x00000300L
23198 #define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK                                                                 0x00000400L
23199 #define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK                                                                   0x0001E000L
23200 #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK                                                              0x00020000L
23201 #define SPI_PS_INPUT_CNTL_11__DUP_MASK                                                                        0x00040000L
23202 #define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK                                                           0x00080000L
23203 #define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
23204 #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
23205 #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
23206 #define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK                                                                0x01000000L
23207 #define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK                                                                0x02000000L
23208 //SPI_PS_INPUT_CNTL_12
23209 #define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT                                                                   0x0
23210 #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT                                                              0x8
23211 #define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT                                                               0xa
23212 #define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT                                                                 0xd
23213 #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT                                                            0x11
23214 #define SPI_PS_INPUT_CNTL_12__DUP__SHIFT                                                                      0x12
23215 #define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT                                                         0x13
23216 #define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
23217 #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
23218 #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
23219 #define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT                                                              0x18
23220 #define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT                                                              0x19
23221 #define SPI_PS_INPUT_CNTL_12__OFFSET_MASK                                                                     0x0000003FL
23222 #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK                                                                0x00000300L
23223 #define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK                                                                 0x00000400L
23224 #define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK                                                                   0x0001E000L
23225 #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK                                                              0x00020000L
23226 #define SPI_PS_INPUT_CNTL_12__DUP_MASK                                                                        0x00040000L
23227 #define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK                                                           0x00080000L
23228 #define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
23229 #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
23230 #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
23231 #define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK                                                                0x01000000L
23232 #define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK                                                                0x02000000L
23233 //SPI_PS_INPUT_CNTL_13
23234 #define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT                                                                   0x0
23235 #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT                                                              0x8
23236 #define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT                                                               0xa
23237 #define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT                                                                 0xd
23238 #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT                                                            0x11
23239 #define SPI_PS_INPUT_CNTL_13__DUP__SHIFT                                                                      0x12
23240 #define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT                                                         0x13
23241 #define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
23242 #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
23243 #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
23244 #define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT                                                              0x18
23245 #define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT                                                              0x19
23246 #define SPI_PS_INPUT_CNTL_13__OFFSET_MASK                                                                     0x0000003FL
23247 #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK                                                                0x00000300L
23248 #define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK                                                                 0x00000400L
23249 #define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK                                                                   0x0001E000L
23250 #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK                                                              0x00020000L
23251 #define SPI_PS_INPUT_CNTL_13__DUP_MASK                                                                        0x00040000L
23252 #define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK                                                           0x00080000L
23253 #define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
23254 #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
23255 #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
23256 #define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK                                                                0x01000000L
23257 #define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK                                                                0x02000000L
23258 //SPI_PS_INPUT_CNTL_14
23259 #define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT                                                                   0x0
23260 #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT                                                              0x8
23261 #define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT                                                               0xa
23262 #define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT                                                                 0xd
23263 #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT                                                            0x11
23264 #define SPI_PS_INPUT_CNTL_14__DUP__SHIFT                                                                      0x12
23265 #define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT                                                         0x13
23266 #define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
23267 #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
23268 #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
23269 #define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT                                                              0x18
23270 #define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT                                                              0x19
23271 #define SPI_PS_INPUT_CNTL_14__OFFSET_MASK                                                                     0x0000003FL
23272 #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK                                                                0x00000300L
23273 #define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK                                                                 0x00000400L
23274 #define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK                                                                   0x0001E000L
23275 #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK                                                              0x00020000L
23276 #define SPI_PS_INPUT_CNTL_14__DUP_MASK                                                                        0x00040000L
23277 #define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK                                                           0x00080000L
23278 #define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
23279 #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
23280 #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
23281 #define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK                                                                0x01000000L
23282 #define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK                                                                0x02000000L
23283 //SPI_PS_INPUT_CNTL_15
23284 #define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT                                                                   0x0
23285 #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT                                                              0x8
23286 #define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT                                                               0xa
23287 #define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT                                                                 0xd
23288 #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT                                                            0x11
23289 #define SPI_PS_INPUT_CNTL_15__DUP__SHIFT                                                                      0x12
23290 #define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT                                                         0x13
23291 #define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
23292 #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
23293 #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
23294 #define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT                                                              0x18
23295 #define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT                                                              0x19
23296 #define SPI_PS_INPUT_CNTL_15__OFFSET_MASK                                                                     0x0000003FL
23297 #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK                                                                0x00000300L
23298 #define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK                                                                 0x00000400L
23299 #define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK                                                                   0x0001E000L
23300 #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK                                                              0x00020000L
23301 #define SPI_PS_INPUT_CNTL_15__DUP_MASK                                                                        0x00040000L
23302 #define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK                                                           0x00080000L
23303 #define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
23304 #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
23305 #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
23306 #define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK                                                                0x01000000L
23307 #define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK                                                                0x02000000L
23308 //SPI_PS_INPUT_CNTL_16
23309 #define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT                                                                   0x0
23310 #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT                                                              0x8
23311 #define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT                                                               0xa
23312 #define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT                                                                 0xd
23313 #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT                                                            0x11
23314 #define SPI_PS_INPUT_CNTL_16__DUP__SHIFT                                                                      0x12
23315 #define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT                                                         0x13
23316 #define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
23317 #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
23318 #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
23319 #define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT                                                              0x18
23320 #define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT                                                              0x19
23321 #define SPI_PS_INPUT_CNTL_16__OFFSET_MASK                                                                     0x0000003FL
23322 #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK                                                                0x00000300L
23323 #define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK                                                                 0x00000400L
23324 #define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK                                                                   0x0001E000L
23325 #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK                                                              0x00020000L
23326 #define SPI_PS_INPUT_CNTL_16__DUP_MASK                                                                        0x00040000L
23327 #define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK                                                           0x00080000L
23328 #define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
23329 #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
23330 #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
23331 #define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK                                                                0x01000000L
23332 #define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK                                                                0x02000000L
23333 //SPI_PS_INPUT_CNTL_17
23334 #define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT                                                                   0x0
23335 #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT                                                              0x8
23336 #define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT                                                               0xa
23337 #define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT                                                                 0xd
23338 #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT                                                            0x11
23339 #define SPI_PS_INPUT_CNTL_17__DUP__SHIFT                                                                      0x12
23340 #define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT                                                         0x13
23341 #define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
23342 #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
23343 #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
23344 #define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT                                                              0x18
23345 #define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT                                                              0x19
23346 #define SPI_PS_INPUT_CNTL_17__OFFSET_MASK                                                                     0x0000003FL
23347 #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK                                                                0x00000300L
23348 #define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK                                                                 0x00000400L
23349 #define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK                                                                   0x0001E000L
23350 #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK                                                              0x00020000L
23351 #define SPI_PS_INPUT_CNTL_17__DUP_MASK                                                                        0x00040000L
23352 #define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK                                                           0x00080000L
23353 #define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
23354 #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
23355 #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
23356 #define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK                                                                0x01000000L
23357 #define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK                                                                0x02000000L
23358 //SPI_PS_INPUT_CNTL_18
23359 #define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT                                                                   0x0
23360 #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT                                                              0x8
23361 #define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT                                                               0xa
23362 #define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT                                                                 0xd
23363 #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT                                                            0x11
23364 #define SPI_PS_INPUT_CNTL_18__DUP__SHIFT                                                                      0x12
23365 #define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT                                                         0x13
23366 #define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
23367 #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
23368 #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
23369 #define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT                                                              0x18
23370 #define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT                                                              0x19
23371 #define SPI_PS_INPUT_CNTL_18__OFFSET_MASK                                                                     0x0000003FL
23372 #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK                                                                0x00000300L
23373 #define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK                                                                 0x00000400L
23374 #define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK                                                                   0x0001E000L
23375 #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK                                                              0x00020000L
23376 #define SPI_PS_INPUT_CNTL_18__DUP_MASK                                                                        0x00040000L
23377 #define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK                                                           0x00080000L
23378 #define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
23379 #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
23380 #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
23381 #define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK                                                                0x01000000L
23382 #define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK                                                                0x02000000L
23383 //SPI_PS_INPUT_CNTL_19
23384 #define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT                                                                   0x0
23385 #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT                                                              0x8
23386 #define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT                                                               0xa
23387 #define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT                                                                 0xd
23388 #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT                                                            0x11
23389 #define SPI_PS_INPUT_CNTL_19__DUP__SHIFT                                                                      0x12
23390 #define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT                                                         0x13
23391 #define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
23392 #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
23393 #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
23394 #define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT                                                              0x18
23395 #define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT                                                              0x19
23396 #define SPI_PS_INPUT_CNTL_19__OFFSET_MASK                                                                     0x0000003FL
23397 #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK                                                                0x00000300L
23398 #define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK                                                                 0x00000400L
23399 #define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK                                                                   0x0001E000L
23400 #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK                                                              0x00020000L
23401 #define SPI_PS_INPUT_CNTL_19__DUP_MASK                                                                        0x00040000L
23402 #define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK                                                           0x00080000L
23403 #define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
23404 #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
23405 #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
23406 #define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK                                                                0x01000000L
23407 #define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK                                                                0x02000000L
23408 //SPI_PS_INPUT_CNTL_20
23409 #define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT                                                                   0x0
23410 #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT                                                              0x8
23411 #define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT                                                               0xa
23412 #define SPI_PS_INPUT_CNTL_20__DUP__SHIFT                                                                      0x12
23413 #define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT                                                         0x13
23414 #define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
23415 #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
23416 #define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT                                                              0x18
23417 #define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT                                                              0x19
23418 #define SPI_PS_INPUT_CNTL_20__OFFSET_MASK                                                                     0x0000003FL
23419 #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK                                                                0x00000300L
23420 #define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK                                                                 0x00000400L
23421 #define SPI_PS_INPUT_CNTL_20__DUP_MASK                                                                        0x00040000L
23422 #define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK                                                           0x00080000L
23423 #define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
23424 #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
23425 #define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK                                                                0x01000000L
23426 #define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK                                                                0x02000000L
23427 //SPI_PS_INPUT_CNTL_21
23428 #define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT                                                                   0x0
23429 #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT                                                              0x8
23430 #define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT                                                               0xa
23431 #define SPI_PS_INPUT_CNTL_21__DUP__SHIFT                                                                      0x12
23432 #define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT                                                         0x13
23433 #define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
23434 #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
23435 #define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT                                                              0x18
23436 #define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT                                                              0x19
23437 #define SPI_PS_INPUT_CNTL_21__OFFSET_MASK                                                                     0x0000003FL
23438 #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK                                                                0x00000300L
23439 #define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK                                                                 0x00000400L
23440 #define SPI_PS_INPUT_CNTL_21__DUP_MASK                                                                        0x00040000L
23441 #define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK                                                           0x00080000L
23442 #define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
23443 #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
23444 #define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK                                                                0x01000000L
23445 #define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK                                                                0x02000000L
23446 //SPI_PS_INPUT_CNTL_22
23447 #define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT                                                                   0x0
23448 #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT                                                              0x8
23449 #define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT                                                               0xa
23450 #define SPI_PS_INPUT_CNTL_22__DUP__SHIFT                                                                      0x12
23451 #define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT                                                         0x13
23452 #define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
23453 #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
23454 #define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT                                                              0x18
23455 #define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT                                                              0x19
23456 #define SPI_PS_INPUT_CNTL_22__OFFSET_MASK                                                                     0x0000003FL
23457 #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK                                                                0x00000300L
23458 #define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK                                                                 0x00000400L
23459 #define SPI_PS_INPUT_CNTL_22__DUP_MASK                                                                        0x00040000L
23460 #define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK                                                           0x00080000L
23461 #define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
23462 #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
23463 #define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK                                                                0x01000000L
23464 #define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK                                                                0x02000000L
23465 //SPI_PS_INPUT_CNTL_23
23466 #define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT                                                                   0x0
23467 #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT                                                              0x8
23468 #define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT                                                               0xa
23469 #define SPI_PS_INPUT_CNTL_23__DUP__SHIFT                                                                      0x12
23470 #define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT                                                         0x13
23471 #define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
23472 #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
23473 #define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT                                                              0x18
23474 #define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT                                                              0x19
23475 #define SPI_PS_INPUT_CNTL_23__OFFSET_MASK                                                                     0x0000003FL
23476 #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK                                                                0x00000300L
23477 #define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK                                                                 0x00000400L
23478 #define SPI_PS_INPUT_CNTL_23__DUP_MASK                                                                        0x00040000L
23479 #define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK                                                           0x00080000L
23480 #define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
23481 #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
23482 #define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK                                                                0x01000000L
23483 #define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK                                                                0x02000000L
23484 //SPI_PS_INPUT_CNTL_24
23485 #define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT                                                                   0x0
23486 #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT                                                              0x8
23487 #define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT                                                               0xa
23488 #define SPI_PS_INPUT_CNTL_24__DUP__SHIFT                                                                      0x12
23489 #define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT                                                         0x13
23490 #define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
23491 #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
23492 #define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT                                                              0x18
23493 #define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT                                                              0x19
23494 #define SPI_PS_INPUT_CNTL_24__OFFSET_MASK                                                                     0x0000003FL
23495 #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK                                                                0x00000300L
23496 #define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK                                                                 0x00000400L
23497 #define SPI_PS_INPUT_CNTL_24__DUP_MASK                                                                        0x00040000L
23498 #define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK                                                           0x00080000L
23499 #define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
23500 #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
23501 #define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK                                                                0x01000000L
23502 #define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK                                                                0x02000000L
23503 //SPI_PS_INPUT_CNTL_25
23504 #define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT                                                                   0x0
23505 #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT                                                              0x8
23506 #define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT                                                               0xa
23507 #define SPI_PS_INPUT_CNTL_25__DUP__SHIFT                                                                      0x12
23508 #define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT                                                         0x13
23509 #define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
23510 #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
23511 #define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT                                                              0x18
23512 #define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT                                                              0x19
23513 #define SPI_PS_INPUT_CNTL_25__OFFSET_MASK                                                                     0x0000003FL
23514 #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK                                                                0x00000300L
23515 #define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK                                                                 0x00000400L
23516 #define SPI_PS_INPUT_CNTL_25__DUP_MASK                                                                        0x00040000L
23517 #define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK                                                           0x00080000L
23518 #define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
23519 #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
23520 #define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK                                                                0x01000000L
23521 #define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK                                                                0x02000000L
23522 //SPI_PS_INPUT_CNTL_26
23523 #define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT                                                                   0x0
23524 #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT                                                              0x8
23525 #define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT                                                               0xa
23526 #define SPI_PS_INPUT_CNTL_26__DUP__SHIFT                                                                      0x12
23527 #define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT                                                         0x13
23528 #define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
23529 #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
23530 #define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT                                                              0x18
23531 #define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT                                                              0x19
23532 #define SPI_PS_INPUT_CNTL_26__OFFSET_MASK                                                                     0x0000003FL
23533 #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK                                                                0x00000300L
23534 #define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK                                                                 0x00000400L
23535 #define SPI_PS_INPUT_CNTL_26__DUP_MASK                                                                        0x00040000L
23536 #define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK                                                           0x00080000L
23537 #define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
23538 #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
23539 #define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK                                                                0x01000000L
23540 #define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK                                                                0x02000000L
23541 //SPI_PS_INPUT_CNTL_27
23542 #define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT                                                                   0x0
23543 #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT                                                              0x8
23544 #define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT                                                               0xa
23545 #define SPI_PS_INPUT_CNTL_27__DUP__SHIFT                                                                      0x12
23546 #define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT                                                         0x13
23547 #define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
23548 #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
23549 #define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT                                                              0x18
23550 #define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT                                                              0x19
23551 #define SPI_PS_INPUT_CNTL_27__OFFSET_MASK                                                                     0x0000003FL
23552 #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK                                                                0x00000300L
23553 #define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK                                                                 0x00000400L
23554 #define SPI_PS_INPUT_CNTL_27__DUP_MASK                                                                        0x00040000L
23555 #define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK                                                           0x00080000L
23556 #define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
23557 #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
23558 #define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK                                                                0x01000000L
23559 #define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK                                                                0x02000000L
23560 //SPI_PS_INPUT_CNTL_28
23561 #define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT                                                                   0x0
23562 #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT                                                              0x8
23563 #define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT                                                               0xa
23564 #define SPI_PS_INPUT_CNTL_28__DUP__SHIFT                                                                      0x12
23565 #define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT                                                         0x13
23566 #define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
23567 #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
23568 #define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT                                                              0x18
23569 #define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT                                                              0x19
23570 #define SPI_PS_INPUT_CNTL_28__OFFSET_MASK                                                                     0x0000003FL
23571 #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK                                                                0x00000300L
23572 #define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK                                                                 0x00000400L
23573 #define SPI_PS_INPUT_CNTL_28__DUP_MASK                                                                        0x00040000L
23574 #define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK                                                           0x00080000L
23575 #define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
23576 #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
23577 #define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK                                                                0x01000000L
23578 #define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK                                                                0x02000000L
23579 //SPI_PS_INPUT_CNTL_29
23580 #define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT                                                                   0x0
23581 #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT                                                              0x8
23582 #define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT                                                               0xa
23583 #define SPI_PS_INPUT_CNTL_29__DUP__SHIFT                                                                      0x12
23584 #define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT                                                         0x13
23585 #define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
23586 #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
23587 #define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT                                                              0x18
23588 #define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT                                                              0x19
23589 #define SPI_PS_INPUT_CNTL_29__OFFSET_MASK                                                                     0x0000003FL
23590 #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK                                                                0x00000300L
23591 #define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK                                                                 0x00000400L
23592 #define SPI_PS_INPUT_CNTL_29__DUP_MASK                                                                        0x00040000L
23593 #define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK                                                           0x00080000L
23594 #define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
23595 #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
23596 #define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK                                                                0x01000000L
23597 #define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK                                                                0x02000000L
23598 //SPI_PS_INPUT_CNTL_30
23599 #define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT                                                                   0x0
23600 #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT                                                              0x8
23601 #define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT                                                               0xa
23602 #define SPI_PS_INPUT_CNTL_30__DUP__SHIFT                                                                      0x12
23603 #define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT                                                         0x13
23604 #define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
23605 #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
23606 #define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT                                                              0x18
23607 #define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT                                                              0x19
23608 #define SPI_PS_INPUT_CNTL_30__OFFSET_MASK                                                                     0x0000003FL
23609 #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK                                                                0x00000300L
23610 #define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK                                                                 0x00000400L
23611 #define SPI_PS_INPUT_CNTL_30__DUP_MASK                                                                        0x00040000L
23612 #define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK                                                           0x00080000L
23613 #define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
23614 #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
23615 #define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK                                                                0x01000000L
23616 #define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK                                                                0x02000000L
23617 //SPI_PS_INPUT_CNTL_31
23618 #define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT                                                                   0x0
23619 #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT                                                              0x8
23620 #define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT                                                               0xa
23621 #define SPI_PS_INPUT_CNTL_31__DUP__SHIFT                                                                      0x12
23622 #define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT                                                         0x13
23623 #define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
23624 #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
23625 #define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT                                                              0x18
23626 #define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT                                                              0x19
23627 #define SPI_PS_INPUT_CNTL_31__OFFSET_MASK                                                                     0x0000003FL
23628 #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK                                                                0x00000300L
23629 #define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK                                                                 0x00000400L
23630 #define SPI_PS_INPUT_CNTL_31__DUP_MASK                                                                        0x00040000L
23631 #define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK                                                           0x00080000L
23632 #define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
23633 #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
23634 #define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK                                                                0x01000000L
23635 #define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK                                                                0x02000000L
23636 //SPI_VS_OUT_CONFIG
23637 #define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT                                                             0x1
23638 #define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT                                                                0x6
23639 #define SPI_VS_OUT_CONFIG__NO_PC_EXPORT__SHIFT                                                                0x7
23640 #define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK                                                               0x0000003EL
23641 #define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK                                                                  0x00000040L
23642 #define SPI_VS_OUT_CONFIG__NO_PC_EXPORT_MASK                                                                  0x00000080L
23643 //SPI_PS_INPUT_ENA
23644 #define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT                                                             0x0
23645 #define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT                                                             0x1
23646 #define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT                                                           0x2
23647 #define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT                                                         0x3
23648 #define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT                                                            0x4
23649 #define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT                                                            0x5
23650 #define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT                                                          0x6
23651 #define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT                                                         0x7
23652 #define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT                                                              0x8
23653 #define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT                                                              0x9
23654 #define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT                                                              0xa
23655 #define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT                                                              0xb
23656 #define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT                                                               0xc
23657 #define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT                                                                0xd
23658 #define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT                                                          0xe
23659 #define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT                                                             0xf
23660 #define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK                                                               0x00000001L
23661 #define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK                                                               0x00000002L
23662 #define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK                                                             0x00000004L
23663 #define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK                                                           0x00000008L
23664 #define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK                                                              0x00000010L
23665 #define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK                                                              0x00000020L
23666 #define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK                                                            0x00000040L
23667 #define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK                                                           0x00000080L
23668 #define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK                                                                0x00000100L
23669 #define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK                                                                0x00000200L
23670 #define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK                                                                0x00000400L
23671 #define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK                                                                0x00000800L
23672 #define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK                                                                 0x00001000L
23673 #define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK                                                                  0x00002000L
23674 #define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK                                                            0x00004000L
23675 #define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK                                                               0x00008000L
23676 //SPI_PS_INPUT_ADDR
23677 #define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT                                                            0x0
23678 #define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT                                                            0x1
23679 #define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT                                                          0x2
23680 #define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT                                                        0x3
23681 #define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT                                                           0x4
23682 #define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT                                                           0x5
23683 #define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT                                                         0x6
23684 #define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT                                                        0x7
23685 #define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT                                                             0x8
23686 #define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT                                                             0x9
23687 #define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT                                                             0xa
23688 #define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT                                                             0xb
23689 #define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT                                                              0xc
23690 #define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT                                                               0xd
23691 #define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT                                                         0xe
23692 #define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT                                                            0xf
23693 #define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK                                                              0x00000001L
23694 #define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK                                                              0x00000002L
23695 #define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK                                                            0x00000004L
23696 #define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK                                                          0x00000008L
23697 #define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK                                                             0x00000010L
23698 #define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK                                                             0x00000020L
23699 #define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK                                                           0x00000040L
23700 #define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK                                                          0x00000080L
23701 #define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK                                                               0x00000100L
23702 #define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK                                                               0x00000200L
23703 #define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK                                                               0x00000400L
23704 #define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK                                                               0x00000800L
23705 #define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK                                                                0x00001000L
23706 #define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK                                                                 0x00002000L
23707 #define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK                                                           0x00004000L
23708 #define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK                                                              0x00008000L
23709 //SPI_INTERP_CONTROL_0
23710 #define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT                                                           0x0
23711 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT                                                           0x1
23712 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT                                                        0x2
23713 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT                                                        0x5
23714 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT                                                        0x8
23715 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT                                                        0xb
23716 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT                                                         0xe
23717 #define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK                                                             0x00000001L
23718 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK                                                             0x00000002L
23719 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK                                                          0x0000001CL
23720 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK                                                          0x000000E0L
23721 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK                                                          0x00000700L
23722 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK                                                          0x00003800L
23723 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK                                                           0x00004000L
23724 //SPI_PS_IN_CONTROL
23725 #define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT                                                                  0x0
23726 #define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT                                                                   0x6
23727 #define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN__SHIFT                                                            0x7
23728 #define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC__SHIFT                                                             0x8
23729 #define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT                                                         0xe
23730 #define SPI_PS_IN_CONTROL__PS_W32_EN__SHIFT                                                                   0xf
23731 #define SPI_PS_IN_CONTROL__NUM_INTERP_MASK                                                                    0x0000003FL
23732 #define SPI_PS_IN_CONTROL__PARAM_GEN_MASK                                                                     0x00000040L
23733 #define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN_MASK                                                              0x00000080L
23734 #define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC_MASK                                                               0x00000100L
23735 #define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK                                                           0x00004000L
23736 #define SPI_PS_IN_CONTROL__PS_W32_EN_MASK                                                                     0x00008000L
23737 //SPI_BARYC_CNTL
23738 #define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT                                                              0x0
23739 #define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT                                                            0x4
23740 #define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT                                                             0x8
23741 #define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT                                                           0xc
23742 #define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT                                                             0x10
23743 #define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT                                                                  0x14
23744 #define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT                                                            0x18
23745 #define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK                                                                0x00000001L
23746 #define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK                                                              0x00000010L
23747 #define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK                                                               0x00000100L
23748 #define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK                                                             0x00001000L
23749 #define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK                                                               0x00030000L
23750 #define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK                                                                    0x00100000L
23751 #define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK                                                              0x01000000L
23752 //SPI_TMPRING_SIZE
23753 #define SPI_TMPRING_SIZE__WAVES__SHIFT                                                                        0x0
23754 #define SPI_TMPRING_SIZE__WAVESIZE__SHIFT                                                                     0xc
23755 #define SPI_TMPRING_SIZE__WAVES_MASK                                                                          0x00000FFFL
23756 #define SPI_TMPRING_SIZE__WAVESIZE_MASK                                                                       0x01FFF000L
23757 //SPI_SHADER_IDX_FORMAT
23758 #define SPI_SHADER_IDX_FORMAT__IDX0_EXPORT_FORMAT__SHIFT                                                      0x0
23759 #define SPI_SHADER_IDX_FORMAT__IDX0_EXPORT_FORMAT_MASK                                                        0x0000000FL
23760 //SPI_SHADER_POS_FORMAT
23761 #define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT                                                      0x0
23762 #define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT                                                      0x4
23763 #define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT                                                      0x8
23764 #define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT                                                      0xc
23765 #define SPI_SHADER_POS_FORMAT__POS4_EXPORT_FORMAT__SHIFT                                                      0x10
23766 #define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK                                                        0x0000000FL
23767 #define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK                                                        0x000000F0L
23768 #define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK                                                        0x00000F00L
23769 #define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK                                                        0x0000F000L
23770 #define SPI_SHADER_POS_FORMAT__POS4_EXPORT_FORMAT_MASK                                                        0x000F0000L
23771 //SPI_SHADER_Z_FORMAT
23772 #define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT                                                           0x0
23773 #define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK                                                             0x0000000FL
23774 //SPI_SHADER_COL_FORMAT
23775 #define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT                                                      0x0
23776 #define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT                                                      0x4
23777 #define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT                                                      0x8
23778 #define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT                                                      0xc
23779 #define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT                                                      0x10
23780 #define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT                                                      0x14
23781 #define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT                                                      0x18
23782 #define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT                                                      0x1c
23783 #define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK                                                        0x0000000FL
23784 #define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK                                                        0x000000F0L
23785 #define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK                                                        0x00000F00L
23786 #define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK                                                        0x0000F000L
23787 #define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK                                                        0x000F0000L
23788 #define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK                                                        0x00F00000L
23789 #define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK                                                        0x0F000000L
23790 #define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK                                                        0xF0000000L
23791 //SX_PS_DOWNCONVERT
23792 #define SX_PS_DOWNCONVERT__MRT0__SHIFT                                                                        0x0
23793 #define SX_PS_DOWNCONVERT__MRT1__SHIFT                                                                        0x4
23794 #define SX_PS_DOWNCONVERT__MRT2__SHIFT                                                                        0x8
23795 #define SX_PS_DOWNCONVERT__MRT3__SHIFT                                                                        0xc
23796 #define SX_PS_DOWNCONVERT__MRT4__SHIFT                                                                        0x10
23797 #define SX_PS_DOWNCONVERT__MRT5__SHIFT                                                                        0x14
23798 #define SX_PS_DOWNCONVERT__MRT6__SHIFT                                                                        0x18
23799 #define SX_PS_DOWNCONVERT__MRT7__SHIFT                                                                        0x1c
23800 #define SX_PS_DOWNCONVERT__MRT0_MASK                                                                          0x0000000FL
23801 #define SX_PS_DOWNCONVERT__MRT1_MASK                                                                          0x000000F0L
23802 #define SX_PS_DOWNCONVERT__MRT2_MASK                                                                          0x00000F00L
23803 #define SX_PS_DOWNCONVERT__MRT3_MASK                                                                          0x0000F000L
23804 #define SX_PS_DOWNCONVERT__MRT4_MASK                                                                          0x000F0000L
23805 #define SX_PS_DOWNCONVERT__MRT5_MASK                                                                          0x00F00000L
23806 #define SX_PS_DOWNCONVERT__MRT6_MASK                                                                          0x0F000000L
23807 #define SX_PS_DOWNCONVERT__MRT7_MASK                                                                          0xF0000000L
23808 //SX_BLEND_OPT_EPSILON
23809 #define SX_BLEND_OPT_EPSILON__MRT0_EPSILON__SHIFT                                                             0x0
23810 #define SX_BLEND_OPT_EPSILON__MRT1_EPSILON__SHIFT                                                             0x4
23811 #define SX_BLEND_OPT_EPSILON__MRT2_EPSILON__SHIFT                                                             0x8
23812 #define SX_BLEND_OPT_EPSILON__MRT3_EPSILON__SHIFT                                                             0xc
23813 #define SX_BLEND_OPT_EPSILON__MRT4_EPSILON__SHIFT                                                             0x10
23814 #define SX_BLEND_OPT_EPSILON__MRT5_EPSILON__SHIFT                                                             0x14
23815 #define SX_BLEND_OPT_EPSILON__MRT6_EPSILON__SHIFT                                                             0x18
23816 #define SX_BLEND_OPT_EPSILON__MRT7_EPSILON__SHIFT                                                             0x1c
23817 #define SX_BLEND_OPT_EPSILON__MRT0_EPSILON_MASK                                                               0x0000000FL
23818 #define SX_BLEND_OPT_EPSILON__MRT1_EPSILON_MASK                                                               0x000000F0L
23819 #define SX_BLEND_OPT_EPSILON__MRT2_EPSILON_MASK                                                               0x00000F00L
23820 #define SX_BLEND_OPT_EPSILON__MRT3_EPSILON_MASK                                                               0x0000F000L
23821 #define SX_BLEND_OPT_EPSILON__MRT4_EPSILON_MASK                                                               0x000F0000L
23822 #define SX_BLEND_OPT_EPSILON__MRT5_EPSILON_MASK                                                               0x00F00000L
23823 #define SX_BLEND_OPT_EPSILON__MRT6_EPSILON_MASK                                                               0x0F000000L
23824 #define SX_BLEND_OPT_EPSILON__MRT7_EPSILON_MASK                                                               0xF0000000L
23825 //SX_BLEND_OPT_CONTROL
23826 #define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE__SHIFT                                                   0x0
23827 #define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE__SHIFT                                                   0x1
23828 #define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE__SHIFT                                                   0x4
23829 #define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE__SHIFT                                                   0x5
23830 #define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE__SHIFT                                                   0x8
23831 #define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE__SHIFT                                                   0x9
23832 #define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE__SHIFT                                                   0xc
23833 #define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE__SHIFT                                                   0xd
23834 #define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE__SHIFT                                                   0x10
23835 #define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE__SHIFT                                                   0x11
23836 #define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE__SHIFT                                                   0x14
23837 #define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE__SHIFT                                                   0x15
23838 #define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE__SHIFT                                                   0x18
23839 #define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE__SHIFT                                                   0x19
23840 #define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE__SHIFT                                                   0x1c
23841 #define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE__SHIFT                                                   0x1d
23842 #define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE__SHIFT                                                   0x1f
23843 #define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE_MASK                                                     0x00000001L
23844 #define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE_MASK                                                     0x00000002L
23845 #define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE_MASK                                                     0x00000010L
23846 #define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE_MASK                                                     0x00000020L
23847 #define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE_MASK                                                     0x00000100L
23848 #define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE_MASK                                                     0x00000200L
23849 #define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE_MASK                                                     0x00001000L
23850 #define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE_MASK                                                     0x00002000L
23851 #define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE_MASK                                                     0x00010000L
23852 #define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE_MASK                                                     0x00020000L
23853 #define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE_MASK                                                     0x00100000L
23854 #define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE_MASK                                                     0x00200000L
23855 #define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE_MASK                                                     0x01000000L
23856 #define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE_MASK                                                     0x02000000L
23857 #define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE_MASK                                                     0x10000000L
23858 #define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE_MASK                                                     0x20000000L
23859 #define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE_MASK                                                     0x80000000L
23860 //SX_MRT0_BLEND_OPT
23861 #define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT__SHIFT                                                               0x0
23862 #define SX_MRT0_BLEND_OPT__COLOR_DST_OPT__SHIFT                                                               0x4
23863 #define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN__SHIFT                                                              0x8
23864 #define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT__SHIFT                                                               0x10
23865 #define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT__SHIFT                                                               0x14
23866 #define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN__SHIFT                                                              0x18
23867 #define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT_MASK                                                                 0x00000007L
23868 #define SX_MRT0_BLEND_OPT__COLOR_DST_OPT_MASK                                                                 0x00000070L
23869 #define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN_MASK                                                                0x00000700L
23870 #define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT_MASK                                                                 0x00070000L
23871 #define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT_MASK                                                                 0x00700000L
23872 #define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN_MASK                                                                0x07000000L
23873 //SX_MRT1_BLEND_OPT
23874 #define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT__SHIFT                                                               0x0
23875 #define SX_MRT1_BLEND_OPT__COLOR_DST_OPT__SHIFT                                                               0x4
23876 #define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN__SHIFT                                                              0x8
23877 #define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT__SHIFT                                                               0x10
23878 #define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT__SHIFT                                                               0x14
23879 #define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN__SHIFT                                                              0x18
23880 #define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT_MASK                                                                 0x00000007L
23881 #define SX_MRT1_BLEND_OPT__COLOR_DST_OPT_MASK                                                                 0x00000070L
23882 #define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN_MASK                                                                0x00000700L
23883 #define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT_MASK                                                                 0x00070000L
23884 #define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT_MASK                                                                 0x00700000L
23885 #define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN_MASK                                                                0x07000000L
23886 //SX_MRT2_BLEND_OPT
23887 #define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT__SHIFT                                                               0x0
23888 #define SX_MRT2_BLEND_OPT__COLOR_DST_OPT__SHIFT                                                               0x4
23889 #define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN__SHIFT                                                              0x8
23890 #define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT__SHIFT                                                               0x10
23891 #define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT__SHIFT                                                               0x14
23892 #define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN__SHIFT                                                              0x18
23893 #define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT_MASK                                                                 0x00000007L
23894 #define SX_MRT2_BLEND_OPT__COLOR_DST_OPT_MASK                                                                 0x00000070L
23895 #define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN_MASK                                                                0x00000700L
23896 #define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT_MASK                                                                 0x00070000L
23897 #define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT_MASK                                                                 0x00700000L
23898 #define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN_MASK                                                                0x07000000L
23899 //SX_MRT3_BLEND_OPT
23900 #define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT__SHIFT                                                               0x0
23901 #define SX_MRT3_BLEND_OPT__COLOR_DST_OPT__SHIFT                                                               0x4
23902 #define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN__SHIFT                                                              0x8
23903 #define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT__SHIFT                                                               0x10
23904 #define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT__SHIFT                                                               0x14
23905 #define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN__SHIFT                                                              0x18
23906 #define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT_MASK                                                                 0x00000007L
23907 #define SX_MRT3_BLEND_OPT__COLOR_DST_OPT_MASK                                                                 0x00000070L
23908 #define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN_MASK                                                                0x00000700L
23909 #define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT_MASK                                                                 0x00070000L
23910 #define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT_MASK                                                                 0x00700000L
23911 #define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN_MASK                                                                0x07000000L
23912 //SX_MRT4_BLEND_OPT
23913 #define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT__SHIFT                                                               0x0
23914 #define SX_MRT4_BLEND_OPT__COLOR_DST_OPT__SHIFT                                                               0x4
23915 #define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN__SHIFT                                                              0x8
23916 #define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT__SHIFT                                                               0x10
23917 #define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT__SHIFT                                                               0x14
23918 #define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN__SHIFT                                                              0x18
23919 #define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT_MASK                                                                 0x00000007L
23920 #define SX_MRT4_BLEND_OPT__COLOR_DST_OPT_MASK                                                                 0x00000070L
23921 #define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN_MASK                                                                0x00000700L
23922 #define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT_MASK                                                                 0x00070000L
23923 #define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT_MASK                                                                 0x00700000L
23924 #define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN_MASK                                                                0x07000000L
23925 //SX_MRT5_BLEND_OPT
23926 #define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT__SHIFT                                                               0x0
23927 #define SX_MRT5_BLEND_OPT__COLOR_DST_OPT__SHIFT                                                               0x4
23928 #define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN__SHIFT                                                              0x8
23929 #define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT__SHIFT                                                               0x10
23930 #define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT__SHIFT                                                               0x14
23931 #define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN__SHIFT                                                              0x18
23932 #define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT_MASK                                                                 0x00000007L
23933 #define SX_MRT5_BLEND_OPT__COLOR_DST_OPT_MASK                                                                 0x00000070L
23934 #define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN_MASK                                                                0x00000700L
23935 #define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT_MASK                                                                 0x00070000L
23936 #define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT_MASK                                                                 0x00700000L
23937 #define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN_MASK                                                                0x07000000L
23938 //SX_MRT6_BLEND_OPT
23939 #define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT__SHIFT                                                               0x0
23940 #define SX_MRT6_BLEND_OPT__COLOR_DST_OPT__SHIFT                                                               0x4
23941 #define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN__SHIFT                                                              0x8
23942 #define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT__SHIFT                                                               0x10
23943 #define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT__SHIFT                                                               0x14
23944 #define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN__SHIFT                                                              0x18
23945 #define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT_MASK                                                                 0x00000007L
23946 #define SX_MRT6_BLEND_OPT__COLOR_DST_OPT_MASK                                                                 0x00000070L
23947 #define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN_MASK                                                                0x00000700L
23948 #define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT_MASK                                                                 0x00070000L
23949 #define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT_MASK                                                                 0x00700000L
23950 #define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN_MASK                                                                0x07000000L
23951 //SX_MRT7_BLEND_OPT
23952 #define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT__SHIFT                                                               0x0
23953 #define SX_MRT7_BLEND_OPT__COLOR_DST_OPT__SHIFT                                                               0x4
23954 #define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN__SHIFT                                                              0x8
23955 #define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT__SHIFT                                                               0x10
23956 #define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT__SHIFT                                                               0x14
23957 #define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN__SHIFT                                                              0x18
23958 #define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT_MASK                                                                 0x00000007L
23959 #define SX_MRT7_BLEND_OPT__COLOR_DST_OPT_MASK                                                                 0x00000070L
23960 #define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN_MASK                                                                0x00000700L
23961 #define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT_MASK                                                                 0x00070000L
23962 #define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT_MASK                                                                 0x00700000L
23963 #define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN_MASK                                                                0x07000000L
23964 //CB_BLEND0_CONTROL
23965 #define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
23966 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
23967 #define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
23968 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
23969 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
23970 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
23971 #define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
23972 #define CB_BLEND0_CONTROL__ENABLE__SHIFT                                                                      0x1e
23973 #define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
23974 #define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
23975 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
23976 #define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
23977 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
23978 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
23979 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
23980 #define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
23981 #define CB_BLEND0_CONTROL__ENABLE_MASK                                                                        0x40000000L
23982 #define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
23983 //CB_BLEND1_CONTROL
23984 #define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
23985 #define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
23986 #define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
23987 #define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
23988 #define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
23989 #define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
23990 #define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
23991 #define CB_BLEND1_CONTROL__ENABLE__SHIFT                                                                      0x1e
23992 #define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
23993 #define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
23994 #define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
23995 #define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
23996 #define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
23997 #define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
23998 #define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
23999 #define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
24000 #define CB_BLEND1_CONTROL__ENABLE_MASK                                                                        0x40000000L
24001 #define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
24002 //CB_BLEND2_CONTROL
24003 #define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
24004 #define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
24005 #define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
24006 #define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
24007 #define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
24008 #define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
24009 #define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
24010 #define CB_BLEND2_CONTROL__ENABLE__SHIFT                                                                      0x1e
24011 #define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
24012 #define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
24013 #define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
24014 #define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
24015 #define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
24016 #define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
24017 #define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
24018 #define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
24019 #define CB_BLEND2_CONTROL__ENABLE_MASK                                                                        0x40000000L
24020 #define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
24021 //CB_BLEND3_CONTROL
24022 #define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
24023 #define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
24024 #define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
24025 #define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
24026 #define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
24027 #define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
24028 #define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
24029 #define CB_BLEND3_CONTROL__ENABLE__SHIFT                                                                      0x1e
24030 #define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
24031 #define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
24032 #define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
24033 #define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
24034 #define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
24035 #define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
24036 #define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
24037 #define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
24038 #define CB_BLEND3_CONTROL__ENABLE_MASK                                                                        0x40000000L
24039 #define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
24040 //CB_BLEND4_CONTROL
24041 #define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
24042 #define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
24043 #define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
24044 #define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
24045 #define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
24046 #define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
24047 #define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
24048 #define CB_BLEND4_CONTROL__ENABLE__SHIFT                                                                      0x1e
24049 #define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
24050 #define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
24051 #define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
24052 #define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
24053 #define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
24054 #define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
24055 #define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
24056 #define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
24057 #define CB_BLEND4_CONTROL__ENABLE_MASK                                                                        0x40000000L
24058 #define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
24059 //CB_BLEND5_CONTROL
24060 #define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
24061 #define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
24062 #define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
24063 #define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
24064 #define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
24065 #define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
24066 #define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
24067 #define CB_BLEND5_CONTROL__ENABLE__SHIFT                                                                      0x1e
24068 #define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
24069 #define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
24070 #define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
24071 #define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
24072 #define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
24073 #define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
24074 #define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
24075 #define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
24076 #define CB_BLEND5_CONTROL__ENABLE_MASK                                                                        0x40000000L
24077 #define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
24078 //CB_BLEND6_CONTROL
24079 #define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
24080 #define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
24081 #define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
24082 #define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
24083 #define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
24084 #define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
24085 #define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
24086 #define CB_BLEND6_CONTROL__ENABLE__SHIFT                                                                      0x1e
24087 #define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
24088 #define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
24089 #define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
24090 #define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
24091 #define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
24092 #define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
24093 #define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
24094 #define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
24095 #define CB_BLEND6_CONTROL__ENABLE_MASK                                                                        0x40000000L
24096 #define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
24097 //CB_BLEND7_CONTROL
24098 #define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
24099 #define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
24100 #define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
24101 #define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
24102 #define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
24103 #define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
24104 #define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
24105 #define CB_BLEND7_CONTROL__ENABLE__SHIFT                                                                      0x1e
24106 #define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
24107 #define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
24108 #define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
24109 #define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
24110 #define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
24111 #define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
24112 #define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
24113 #define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
24114 #define CB_BLEND7_CONTROL__ENABLE_MASK                                                                        0x40000000L
24115 #define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
24116 //CS_COPY_STATE
24117 #define CS_COPY_STATE__SRC_STATE_ID__SHIFT                                                                    0x0
24118 #define CS_COPY_STATE__SRC_STATE_ID_MASK                                                                      0x00000007L
24119 //GFX_COPY_STATE
24120 #define GFX_COPY_STATE__SRC_STATE_ID__SHIFT                                                                   0x0
24121 #define GFX_COPY_STATE__SRC_STATE_ID_MASK                                                                     0x00000007L
24122 //PA_CL_POINT_X_RAD
24123 #define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT                                                               0x0
24124 #define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK                                                                 0xFFFFFFFFL
24125 //PA_CL_POINT_Y_RAD
24126 #define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT                                                               0x0
24127 #define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK                                                                 0xFFFFFFFFL
24128 //PA_CL_POINT_SIZE
24129 #define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT                                                                0x0
24130 #define PA_CL_POINT_SIZE__DATA_REGISTER_MASK                                                                  0xFFFFFFFFL
24131 //PA_CL_POINT_CULL_RAD
24132 #define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT                                                            0x0
24133 #define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK                                                              0xFFFFFFFFL
24134 //VGT_DMA_BASE_HI
24135 #define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT                                                                     0x0
24136 #define VGT_DMA_BASE_HI__BASE_ADDR_MASK                                                                       0x0000FFFFL
24137 //VGT_DMA_BASE
24138 #define VGT_DMA_BASE__BASE_ADDR__SHIFT                                                                        0x0
24139 #define VGT_DMA_BASE__BASE_ADDR_MASK                                                                          0xFFFFFFFFL
24140 //VGT_DRAW_INITIATOR
24141 #define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT                                                              0x0
24142 #define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT                                                                 0x2
24143 #define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT                                                             0x4
24144 #define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT                                                                    0x5
24145 #define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT                                                                 0x6
24146 #define VGT_DRAW_INITIATOR__UNROLLED_INST__SHIFT                                                              0x7
24147 #define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC__SHIFT                                                           0x8
24148 #define VGT_DRAW_INITIATOR__REG_RT_INDEX__SHIFT                                                               0x1d
24149 #define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK                                                                0x00000003L
24150 #define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK                                                                   0x0000000CL
24151 #define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK                                                               0x00000010L
24152 #define VGT_DRAW_INITIATOR__NOT_EOP_MASK                                                                      0x00000020L
24153 #define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK                                                                   0x00000040L
24154 #define VGT_DRAW_INITIATOR__UNROLLED_INST_MASK                                                                0x00000080L
24155 #define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC_MASK                                                             0x00000100L
24156 #define VGT_DRAW_INITIATOR__REG_RT_INDEX_MASK                                                                 0xE0000000L
24157 //VGT_IMMED_DATA
24158 #define VGT_IMMED_DATA__DATA__SHIFT                                                                           0x0
24159 #define VGT_IMMED_DATA__DATA_MASK                                                                             0xFFFFFFFFL
24160 //VGT_EVENT_ADDRESS_REG
24161 #define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT                                                             0x0
24162 #define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK                                                               0x0FFFFFFFL
24163 //GE_MAX_OUTPUT_PER_SUBGROUP
24164 #define GE_MAX_OUTPUT_PER_SUBGROUP__MAX_VERTS_PER_SUBGROUP__SHIFT                                             0x0
24165 #define GE_MAX_OUTPUT_PER_SUBGROUP__MAX_VERTS_PER_SUBGROUP_MASK                                               0x000003FFL
24166 //DB_DEPTH_CONTROL
24167 #define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT                                                               0x0
24168 #define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT                                                                     0x1
24169 #define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT                                                               0x2
24170 #define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT                                                          0x3
24171 #define DB_DEPTH_CONTROL__ZFUNC__SHIFT                                                                        0x4
24172 #define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT                                                              0x7
24173 #define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT                                                                  0x8
24174 #define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT                                                               0x14
24175 #define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT                                            0x1e
24176 #define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT                                           0x1f
24177 #define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK                                                                 0x00000001L
24178 #define DB_DEPTH_CONTROL__Z_ENABLE_MASK                                                                       0x00000002L
24179 #define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK                                                                 0x00000004L
24180 #define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK                                                            0x00000008L
24181 #define DB_DEPTH_CONTROL__ZFUNC_MASK                                                                          0x00000070L
24182 #define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK                                                                0x00000080L
24183 #define DB_DEPTH_CONTROL__STENCILFUNC_MASK                                                                    0x00000700L
24184 #define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK                                                                 0x00700000L
24185 #define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK                                              0x40000000L
24186 #define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK                                             0x80000000L
24187 //DB_EQAA
24188 #define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT                                                                    0x0
24189 #define DB_EQAA__PS_ITER_SAMPLES__SHIFT                                                                       0x4
24190 #define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT                                                               0x8
24191 #define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT                                                             0xc
24192 #define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT                                                            0x10
24193 #define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT                                                                 0x11
24194 #define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT                                                                    0x12
24195 #define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT                                                                     0x13
24196 #define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT                                                            0x14
24197 #define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT                                                            0x15
24198 #define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT                                                              0x18
24199 #define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT                                                        0x1b
24200 #define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK                                                                      0x00000007L
24201 #define DB_EQAA__PS_ITER_SAMPLES_MASK                                                                         0x00000070L
24202 #define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK                                                                 0x00000700L
24203 #define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK                                                               0x00007000L
24204 #define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK                                                              0x00010000L
24205 #define DB_EQAA__INCOHERENT_EQAA_READS_MASK                                                                   0x00020000L
24206 #define DB_EQAA__INTERPOLATE_COMP_Z_MASK                                                                      0x00040000L
24207 #define DB_EQAA__INTERPOLATE_SRC_Z_MASK                                                                       0x00080000L
24208 #define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK                                                              0x00100000L
24209 #define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK                                                              0x00200000L
24210 #define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK                                                                0x07000000L
24211 #define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK                                                          0x08000000L
24212 //CB_COLOR_CONTROL
24213 #define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD__SHIFT                                                            0x0
24214 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT                                                               0x3
24215 #define CB_COLOR_CONTROL__MODE__SHIFT                                                                         0x4
24216 #define CB_COLOR_CONTROL__ROP3__SHIFT                                                                         0x10
24217 #define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD_MASK                                                              0x00000001L
24218 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK                                                                 0x00000008L
24219 #define CB_COLOR_CONTROL__MODE_MASK                                                                           0x00000070L
24220 #define CB_COLOR_CONTROL__ROP3_MASK                                                                           0x00FF0000L
24221 //DB_SHADER_CONTROL
24222 #define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT                                                             0x0
24223 #define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT                                              0x1
24224 #define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT                                                0x2
24225 #define DB_SHADER_CONTROL__Z_ORDER__SHIFT                                                                     0x4
24226 #define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT                                                                 0x6
24227 #define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT                                                     0x7
24228 #define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT                                                          0x8
24229 #define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT                                                           0x9
24230 #define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT                                                                0xa
24231 #define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT                                                       0xb
24232 #define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT                                                         0xc
24233 #define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT                                                       0xd
24234 #define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE__SHIFT                                                           0xf
24235 #define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER__SHIFT                                              0x10
24236 #define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED__SHIFT                                                          0x11
24237 #define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES__SHIFT                                                    0x14
24238 #define DB_SHADER_CONTROL__PRE_SHADER_DEPTH_COVERAGE_ENABLE__SHIFT                                            0x17
24239 #define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK                                                               0x00000001L
24240 #define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK                                                0x00000002L
24241 #define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK                                                  0x00000004L
24242 #define DB_SHADER_CONTROL__Z_ORDER_MASK                                                                       0x00000030L
24243 #define DB_SHADER_CONTROL__KILL_ENABLE_MASK                                                                   0x00000040L
24244 #define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK                                                       0x00000080L
24245 #define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK                                                            0x00000100L
24246 #define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK                                                             0x00000200L
24247 #define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK                                                                  0x00000400L
24248 #define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK                                                         0x00000800L
24249 #define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK                                                           0x00001000L
24250 #define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK                                                         0x00006000L
24251 #define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE_MASK                                                             0x00008000L
24252 #define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER_MASK                                                0x00010000L
24253 #define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED_MASK                                                            0x00020000L
24254 #define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES_MASK                                                      0x00700000L
24255 #define DB_SHADER_CONTROL__PRE_SHADER_DEPTH_COVERAGE_ENABLE_MASK                                              0x00800000L
24256 //PA_CL_CLIP_CNTL
24257 #define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT                                                                     0x0
24258 #define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT                                                                     0x1
24259 #define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT                                                                     0x2
24260 #define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT                                                                     0x3
24261 #define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT                                                                     0x4
24262 #define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT                                                                     0x5
24263 #define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT                                                            0xd
24264 #define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT                                                                   0xe
24265 #define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT                                                                  0x10
24266 #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT                                                             0x11
24267 #define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT                                                        0x12
24268 #define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT                                                             0x13
24269 #define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT                                                           0x14
24270 #define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT                                                                   0x15
24271 #define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT                                                         0x16
24272 #define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT                                                       0x18
24273 #define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT                                                     0x19
24274 #define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT                                                            0x1a
24275 #define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT                                                             0x1b
24276 #define PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA__SHIFT                                                           0x1c
24277 #define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK                                                                       0x00000001L
24278 #define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK                                                                       0x00000002L
24279 #define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK                                                                       0x00000004L
24280 #define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK                                                                       0x00000008L
24281 #define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK                                                                       0x00000010L
24282 #define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK                                                                       0x00000020L
24283 #define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK                                                              0x00002000L
24284 #define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK                                                                     0x0000C000L
24285 #define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK                                                                    0x00010000L
24286 #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK                                                               0x00020000L
24287 #define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK                                                          0x00040000L
24288 #define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK                                                               0x00080000L
24289 #define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK                                                             0x00100000L
24290 #define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK                                                                     0x00200000L
24291 #define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK                                                           0x00400000L
24292 #define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK                                                         0x01000000L
24293 #define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK                                                       0x02000000L
24294 #define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK                                                              0x04000000L
24295 #define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK                                                               0x08000000L
24296 #define PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA_MASK                                                             0x10000000L
24297 //PA_SU_SC_MODE_CNTL
24298 #define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT                                                                 0x0
24299 #define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT                                                                  0x1
24300 #define PA_SU_SC_MODE_CNTL__FACE__SHIFT                                                                       0x2
24301 #define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT                                                                  0x3
24302 #define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT                                                       0x5
24303 #define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT                                                        0x8
24304 #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT                                                   0xb
24305 #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT                                                    0xc
24306 #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT                                                    0xd
24307 #define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT                                                   0x10
24308 #define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT                                                         0x13
24309 #define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT                                                             0x14
24310 #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT                                                          0x15
24311 #define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF__SHIFT                                      0x16
24312 #define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION__SHIFT                                                     0x17
24313 #define PA_SU_SC_MODE_CNTL__KEEP_TOGETHER_ENABLE__SHIFT                                                       0x18
24314 #define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK                                                                   0x00000001L
24315 #define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK                                                                    0x00000002L
24316 #define PA_SU_SC_MODE_CNTL__FACE_MASK                                                                         0x00000004L
24317 #define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK                                                                    0x00000018L
24318 #define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK                                                         0x000000E0L
24319 #define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK                                                          0x00000700L
24320 #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK                                                     0x00000800L
24321 #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK                                                      0x00001000L
24322 #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK                                                      0x00002000L
24323 #define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK                                                     0x00010000L
24324 #define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK                                                           0x00080000L
24325 #define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK                                                               0x00100000L
24326 #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK                                                            0x00200000L
24327 #define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF_MASK                                        0x00400000L
24328 #define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION_MASK                                                       0x00800000L
24329 #define PA_SU_SC_MODE_CNTL__KEEP_TOGETHER_ENABLE_MASK                                                         0x01000000L
24330 //PA_CL_VTE_CNTL
24331 #define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT                                                              0x0
24332 #define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT                                                             0x1
24333 #define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT                                                              0x2
24334 #define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT                                                             0x3
24335 #define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT                                                              0x4
24336 #define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT                                                             0x5
24337 #define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT                                                                     0x8
24338 #define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT                                                                      0x9
24339 #define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT                                                                     0xa
24340 #define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT                                                                0xb
24341 #define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK                                                                0x00000001L
24342 #define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK                                                               0x00000002L
24343 #define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK                                                                0x00000004L
24344 #define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK                                                               0x00000008L
24345 #define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK                                                                0x00000010L
24346 #define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK                                                               0x00000020L
24347 #define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK                                                                       0x00000100L
24348 #define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK                                                                        0x00000200L
24349 #define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK                                                                       0x00000400L
24350 #define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK                                                                  0x00000800L
24351 //PA_CL_VS_OUT_CNTL
24352 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT                                                             0x0
24353 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT                                                             0x1
24354 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT                                                             0x2
24355 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT                                                             0x3
24356 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT                                                             0x4
24357 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT                                                             0x5
24358 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT                                                             0x6
24359 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT                                                             0x7
24360 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT                                                             0x8
24361 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT                                                             0x9
24362 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT                                                             0xa
24363 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT                                                             0xb
24364 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT                                                             0xc
24365 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT                                                             0xd
24366 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT                                                             0xe
24367 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT                                                             0xf
24368 #define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT                                                          0x10
24369 #define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT                                                           0x11
24370 #define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT                                                  0x12
24371 #define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT                                                       0x13
24372 #define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT                                                           0x14
24373 #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT                                                         0x15
24374 #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT                                                      0x16
24375 #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT                                                      0x17
24376 #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT                                                    0x18
24377 #define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT                                                         0x19
24378 #define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID__SHIFT                                                      0x1a
24379 #define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT                                                          0x1b
24380 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK                                                               0x00000001L
24381 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK                                                               0x00000002L
24382 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK                                                               0x00000004L
24383 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK                                                               0x00000008L
24384 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK                                                               0x00000010L
24385 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK                                                               0x00000020L
24386 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK                                                               0x00000040L
24387 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK                                                               0x00000080L
24388 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK                                                               0x00000100L
24389 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK                                                               0x00000200L
24390 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK                                                               0x00000400L
24391 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK                                                               0x00000800L
24392 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK                                                               0x00001000L
24393 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK                                                               0x00002000L
24394 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK                                                               0x00004000L
24395 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK                                                               0x00008000L
24396 #define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK                                                            0x00010000L
24397 #define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK                                                             0x00020000L
24398 #define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK                                                    0x00040000L
24399 #define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK                                                         0x00080000L
24400 #define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK                                                             0x00100000L
24401 #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK                                                           0x00200000L
24402 #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK                                                        0x00400000L
24403 #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK                                                        0x00800000L
24404 #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK                                                      0x01000000L
24405 #define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK                                                           0x02000000L
24406 #define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID_MASK                                                        0x04000000L
24407 #define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK                                                            0x08000000L
24408 //PA_CL_NANINF_CNTL
24409 #define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT                                                          0x0
24410 #define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT                                                           0x1
24411 #define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT                                                           0x2
24412 #define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT                                                           0x3
24413 #define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT                                                           0x4
24414 #define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT                                                            0x5
24415 #define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT                                                            0x6
24416 #define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT                                                        0x7
24417 #define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT                                                            0x8
24418 #define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT                                                            0x9
24419 #define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT                                                             0xa
24420 #define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT                                                             0xb
24421 #define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT                                                             0xc
24422 #define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT                                                             0xd
24423 #define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT                                                    0xe
24424 #define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT                                                         0x14
24425 #define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK                                                            0x00000001L
24426 #define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK                                                             0x00000002L
24427 #define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK                                                             0x00000004L
24428 #define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK                                                             0x00000008L
24429 #define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK                                                             0x00000010L
24430 #define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK                                                              0x00000020L
24431 #define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK                                                              0x00000040L
24432 #define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK                                                          0x00000080L
24433 #define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK                                                              0x00000100L
24434 #define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK                                                              0x00000200L
24435 #define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK                                                               0x00000400L
24436 #define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK                                                               0x00000800L
24437 #define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK                                                               0x00001000L
24438 #define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK                                                               0x00002000L
24439 #define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK                                                      0x00004000L
24440 #define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK                                                           0x00100000L
24441 //PA_SU_LINE_STIPPLE_CNTL
24442 #define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT                                                    0x0
24443 #define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT                                                    0x2
24444 #define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT                                                      0x3
24445 #define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT                                                        0x4
24446 #define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK                                                      0x00000003L
24447 #define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK                                                      0x00000004L
24448 #define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK                                                        0x00000008L
24449 #define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK                                                          0x00000010L
24450 //PA_SU_LINE_STIPPLE_SCALE
24451 #define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT                                                   0x0
24452 #define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK                                                     0xFFFFFFFFL
24453 //PA_SU_PRIM_FILTER_CNTL
24454 #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT                                                0x0
24455 #define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT                                                    0x1
24456 #define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT                                                   0x2
24457 #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT                                               0x3
24458 #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT                                                    0x4
24459 #define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT                                                        0x5
24460 #define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT                                                       0x6
24461 #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT                                                   0x7
24462 #define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT                                                   0x8
24463 #define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT                                                   0x1e
24464 #define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT                                                  0x1f
24465 #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK                                                  0x00000001L
24466 #define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK                                                      0x00000002L
24467 #define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK                                                     0x00000004L
24468 #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK                                                 0x00000008L
24469 #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK                                                      0x00000010L
24470 #define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK                                                          0x00000020L
24471 #define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK                                                         0x00000040L
24472 #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK                                                     0x00000080L
24473 #define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK                                                     0x0000FF00L
24474 #define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK                                                     0x40000000L
24475 #define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK                                                    0x80000000L
24476 //PA_SU_SMALL_PRIM_FILTER_CNTL
24477 #define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE__SHIFT                                         0x0
24478 #define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT                                          0x1
24479 #define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT                                              0x2
24480 #define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT                                             0x3
24481 #define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT                                         0x4
24482 #define PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE__SHIFT                                                     0x5
24483 #define PA_SU_SMALL_PRIM_FILTER_CNTL__SC_1XMSAA_COMPATIBLE_DISABLE__SHIFT                                     0x6
24484 #define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE_MASK                                           0x00000001L
24485 #define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK                                            0x00000002L
24486 #define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK                                                0x00000004L
24487 #define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK                                               0x00000008L
24488 #define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK                                           0x00000010L
24489 #define PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE_MASK                                                       0x00000020L
24490 #define PA_SU_SMALL_PRIM_FILTER_CNTL__SC_1XMSAA_COMPATIBLE_DISABLE_MASK                                       0x00000040L
24491 //PA_CL_OBJPRIM_ID_CNTL
24492 #define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL__SHIFT                                                              0x0
24493 #define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID__SHIFT                                                       0x1
24494 #define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL_MASK                                                                0x00000001L
24495 #define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID_MASK                                                         0x00000002L
24496 //PA_CL_NGG_CNTL
24497 #define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF__SHIFT                                                               0x0
24498 #define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA__SHIFT                                                        0x1
24499 #define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF_MASK                                                                 0x00000001L
24500 #define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA_MASK                                                          0x00000002L
24501 //PA_SU_OVER_RASTERIZATION_CNTL
24502 #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES__SHIFT                                        0x0
24503 #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES__SHIFT                                            0x1
24504 #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS__SHIFT                                           0x2
24505 #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES__SHIFT                                       0x3
24506 #define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW__SHIFT                                                0x4
24507 #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES_MASK                                          0x00000001L
24508 #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES_MASK                                              0x00000002L
24509 #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS_MASK                                             0x00000004L
24510 #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES_MASK                                         0x00000008L
24511 #define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW_MASK                                                  0x00000010L
24512 //PA_STEREO_CNTL
24513 #define PA_STEREO_CNTL__STEREO_MODE__SHIFT                                                                    0x1
24514 #define PA_STEREO_CNTL__RT_SLICE_MODE__SHIFT                                                                  0x5
24515 #define PA_STEREO_CNTL__RT_SLICE_OFFSET__SHIFT                                                                0x8
24516 #define PA_STEREO_CNTL__VP_ID_MODE__SHIFT                                                                     0x10
24517 #define PA_STEREO_CNTL__VP_ID_OFFSET__SHIFT                                                                   0x13
24518 #define PA_STEREO_CNTL__STEREO_MODE_MASK                                                                      0x0000001EL
24519 #define PA_STEREO_CNTL__RT_SLICE_MODE_MASK                                                                    0x000000E0L
24520 #define PA_STEREO_CNTL__RT_SLICE_OFFSET_MASK                                                                  0x00000F00L
24521 #define PA_STEREO_CNTL__VP_ID_MODE_MASK                                                                       0x00070000L
24522 #define PA_STEREO_CNTL__VP_ID_OFFSET_MASK                                                                     0x00780000L
24523 //PA_STATE_STEREO_X
24524 #define PA_STATE_STEREO_X__STEREO_X_OFFSET__SHIFT                                                             0x0
24525 #define PA_STATE_STEREO_X__STEREO_X_OFFSET_MASK                                                               0xFFFFFFFFL
24526 //PA_SU_POINT_SIZE
24527 #define PA_SU_POINT_SIZE__HEIGHT__SHIFT                                                                       0x0
24528 #define PA_SU_POINT_SIZE__WIDTH__SHIFT                                                                        0x10
24529 #define PA_SU_POINT_SIZE__HEIGHT_MASK                                                                         0x0000FFFFL
24530 #define PA_SU_POINT_SIZE__WIDTH_MASK                                                                          0xFFFF0000L
24531 //PA_SU_POINT_MINMAX
24532 #define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT                                                                   0x0
24533 #define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT                                                                   0x10
24534 #define PA_SU_POINT_MINMAX__MIN_SIZE_MASK                                                                     0x0000FFFFL
24535 #define PA_SU_POINT_MINMAX__MAX_SIZE_MASK                                                                     0xFFFF0000L
24536 //PA_SU_LINE_CNTL
24537 #define PA_SU_LINE_CNTL__WIDTH__SHIFT                                                                         0x0
24538 #define PA_SU_LINE_CNTL__WIDTH_MASK                                                                           0x0000FFFFL
24539 //PA_SC_LINE_STIPPLE
24540 #define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT                                                               0x0
24541 #define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT                                                               0x10
24542 #define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT                                                          0x1c
24543 #define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT                                                            0x1d
24544 #define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK                                                                 0x0000FFFFL
24545 #define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK                                                                 0x00FF0000L
24546 #define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK                                                            0x10000000L
24547 #define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK                                                              0x60000000L
24548 //VGT_OUTPUT_PATH_CNTL
24549 #define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT                                                              0x0
24550 #define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK                                                                0x00000007L
24551 //VGT_HOS_CNTL
24552 #define VGT_HOS_CNTL__TESS_MODE__SHIFT                                                                        0x0
24553 #define VGT_HOS_CNTL__TESS_MODE_MASK                                                                          0x00000003L
24554 //VGT_HOS_MAX_TESS_LEVEL
24555 #define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT                                                               0x0
24556 #define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK                                                                 0xFFFFFFFFL
24557 //VGT_HOS_MIN_TESS_LEVEL
24558 #define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT                                                               0x0
24559 #define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK                                                                 0xFFFFFFFFL
24560 //VGT_HOS_REUSE_DEPTH
24561 #define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT                                                               0x0
24562 #define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK                                                                 0x000000FFL
24563 //VGT_GROUP_PRIM_TYPE
24564 #define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT                                                                 0x0
24565 #define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT                                                              0xe
24566 #define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT                                                              0xf
24567 #define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT                                                                0x10
24568 #define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK                                                                   0x0000001FL
24569 #define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK                                                                0x00004000L
24570 #define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK                                                                0x00008000L
24571 #define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK                                                                  0x00070000L
24572 //VGT_GROUP_FIRST_DECR
24573 #define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT                                                               0x0
24574 #define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK                                                                 0x0000000FL
24575 //VGT_GROUP_DECR
24576 #define VGT_GROUP_DECR__DECR__SHIFT                                                                           0x0
24577 #define VGT_GROUP_DECR__DECR_MASK                                                                             0x0000000FL
24578 //VGT_GROUP_VECT_0_CNTL
24579 #define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT                                                               0x0
24580 #define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT                                                               0x1
24581 #define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT                                                               0x2
24582 #define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT                                                               0x3
24583 #define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT                                                                  0x8
24584 #define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT                                                                   0x10
24585 #define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK                                                                 0x00000001L
24586 #define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK                                                                 0x00000002L
24587 #define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK                                                                 0x00000004L
24588 #define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK                                                                 0x00000008L
24589 #define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK                                                                    0x0000FF00L
24590 #define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK                                                                     0x00FF0000L
24591 //VGT_GROUP_VECT_1_CNTL
24592 #define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT                                                               0x0
24593 #define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT                                                               0x1
24594 #define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT                                                               0x2
24595 #define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT                                                               0x3
24596 #define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT                                                                  0x8
24597 #define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT                                                                   0x10
24598 #define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK                                                                 0x00000001L
24599 #define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK                                                                 0x00000002L
24600 #define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK                                                                 0x00000004L
24601 #define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK                                                                 0x00000008L
24602 #define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK                                                                    0x0000FF00L
24603 #define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK                                                                     0x00FF0000L
24604 //VGT_GROUP_VECT_0_FMT_CNTL
24605 #define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT                                                              0x0
24606 #define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT                                                            0x4
24607 #define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT                                                              0x8
24608 #define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT                                                            0xc
24609 #define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT                                                              0x10
24610 #define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT                                                            0x14
24611 #define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT                                                              0x18
24612 #define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT                                                            0x1c
24613 #define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK                                                                0x0000000FL
24614 #define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK                                                              0x000000F0L
24615 #define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK                                                                0x00000F00L
24616 #define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK                                                              0x0000F000L
24617 #define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK                                                                0x000F0000L
24618 #define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK                                                              0x00F00000L
24619 #define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK                                                                0x0F000000L
24620 #define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK                                                              0xF0000000L
24621 //VGT_GROUP_VECT_1_FMT_CNTL
24622 #define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT                                                              0x0
24623 #define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT                                                            0x4
24624 #define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT                                                              0x8
24625 #define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT                                                            0xc
24626 #define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT                                                              0x10
24627 #define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT                                                            0x14
24628 #define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT                                                              0x18
24629 #define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT                                                            0x1c
24630 #define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK                                                                0x0000000FL
24631 #define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK                                                              0x000000F0L
24632 #define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK                                                                0x00000F00L
24633 #define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK                                                              0x0000F000L
24634 #define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK                                                                0x000F0000L
24635 #define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK                                                              0x00F00000L
24636 #define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK                                                                0x0F000000L
24637 #define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK                                                              0xF0000000L
24638 //VGT_GS_MODE
24639 #define VGT_GS_MODE__MODE__SHIFT                                                                              0x0
24640 #define VGT_GS_MODE__RESERVED_0__SHIFT                                                                        0x3
24641 #define VGT_GS_MODE__CUT_MODE__SHIFT                                                                          0x4
24642 #define VGT_GS_MODE__RESERVED_1__SHIFT                                                                        0x6
24643 #define VGT_GS_MODE__GS_C_PACK_EN__SHIFT                                                                      0xb
24644 #define VGT_GS_MODE__RESERVED_2__SHIFT                                                                        0xc
24645 #define VGT_GS_MODE__ES_PASSTHRU__SHIFT                                                                       0xd
24646 #define VGT_GS_MODE__COMPUTE_MODE__SHIFT                                                                      0xe
24647 #define VGT_GS_MODE__FAST_COMPUTE_MODE__SHIFT                                                                 0xf
24648 #define VGT_GS_MODE__ELEMENT_INFO_EN__SHIFT                                                                   0x10
24649 #define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT                                                                0x11
24650 #define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT                                                                     0x12
24651 #define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT                                                                 0x13
24652 #define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT                                                                 0x14
24653 #define VGT_GS_MODE__ONCHIP__SHIFT                                                                            0x15
24654 #define VGT_GS_MODE__MODE_MASK                                                                                0x00000007L
24655 #define VGT_GS_MODE__RESERVED_0_MASK                                                                          0x00000008L
24656 #define VGT_GS_MODE__CUT_MODE_MASK                                                                            0x00000030L
24657 #define VGT_GS_MODE__RESERVED_1_MASK                                                                          0x000007C0L
24658 #define VGT_GS_MODE__GS_C_PACK_EN_MASK                                                                        0x00000800L
24659 #define VGT_GS_MODE__RESERVED_2_MASK                                                                          0x00001000L
24660 #define VGT_GS_MODE__ES_PASSTHRU_MASK                                                                         0x00002000L
24661 #define VGT_GS_MODE__COMPUTE_MODE_MASK                                                                        0x00004000L
24662 #define VGT_GS_MODE__FAST_COMPUTE_MODE_MASK                                                                   0x00008000L
24663 #define VGT_GS_MODE__ELEMENT_INFO_EN_MASK                                                                     0x00010000L
24664 #define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK                                                                  0x00020000L
24665 #define VGT_GS_MODE__SUPPRESS_CUTS_MASK                                                                       0x00040000L
24666 #define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK                                                                   0x00080000L
24667 #define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK                                                                   0x00100000L
24668 #define VGT_GS_MODE__ONCHIP_MASK                                                                              0x00600000L
24669 //VGT_GS_ONCHIP_CNTL
24670 #define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT                                                        0x0
24671 #define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT                                                        0xb
24672 #define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP__SHIFT                                                    0x16
24673 #define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK                                                          0x000007FFL
24674 #define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK                                                          0x003FF800L
24675 #define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP_MASK                                                      0xFFC00000L
24676 //PA_SC_MODE_CNTL_0
24677 #define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT                                                                 0x0
24678 #define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT                                                        0x1
24679 #define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT                                                         0x2
24680 #define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT                                                    0x3
24681 #define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD__SHIFT                                                        0x4
24682 #define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE__SHIFT                                                      0x5
24683 #define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB__SHIFT                                               0x6
24684 #define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK                                                                   0x00000001L
24685 #define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK                                                          0x00000002L
24686 #define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK                                                           0x00000004L
24687 #define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK                                                      0x00000008L
24688 #define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD_MASK                                                          0x00000010L
24689 #define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE_MASK                                                        0x00000020L
24690 #define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB_MASK                                                 0x00000040L
24691 //PA_SC_MODE_CNTL_1
24692 #define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT                                                                   0x0
24693 #define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT                                                              0x1
24694 #define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT                                                    0x2
24695 #define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT                                                           0x3
24696 #define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT                                                             0x4
24697 #define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT                                                 0x7
24698 #define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT                                                      0x8
24699 #define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT                                                          0x9
24700 #define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT                                                       0xa
24701 #define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT                                                             0xb
24702 #define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT                                                             0xc
24703 #define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT                                                             0xd
24704 #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT                                                          0xe
24705 #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT                                                   0xf
24706 #define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT                                                              0x10
24707 #define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT                                     0x11
24708 #define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT                                                  0x12
24709 #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT                                                      0x13
24710 #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT                                                             0x14
24711 #define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT                                               0x18
24712 #define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT                                                     0x19
24713 #define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT                                                        0x1a
24714 #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT                                               0x1b
24715 #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT                                                     0x1c
24716 #define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK                                                                     0x00000001L
24717 #define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK                                                                0x00000002L
24718 #define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK                                                      0x00000004L
24719 #define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK                                                             0x00000008L
24720 #define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK                                                               0x00000070L
24721 #define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK                                                   0x00000080L
24722 #define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK                                                        0x00000100L
24723 #define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK                                                            0x00000200L
24724 #define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK                                                         0x00000400L
24725 #define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK                                                               0x00000800L
24726 #define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK                                                               0x00001000L
24727 #define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK                                                               0x00002000L
24728 #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK                                                            0x00004000L
24729 #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK                                                     0x00008000L
24730 #define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK                                                                0x00010000L
24731 #define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK                                       0x00020000L
24732 #define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK                                                    0x00040000L
24733 #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK                                                        0x00080000L
24734 #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK                                                               0x00F00000L
24735 #define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK                                                 0x01000000L
24736 #define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK                                                       0x02000000L
24737 #define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK                                                          0x04000000L
24738 #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK                                                 0x08000000L
24739 #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK                                                       0x70000000L
24740 //VGT_ENHANCE
24741 #define VGT_ENHANCE__MISC__SHIFT                                                                              0x0
24742 #define VGT_ENHANCE__MISC_MASK                                                                                0xFFFFFFFFL
24743 //VGT_GS_PER_ES
24744 #define VGT_GS_PER_ES__GS_PER_ES__SHIFT                                                                       0x0
24745 #define VGT_GS_PER_ES__GS_PER_ES_MASK                                                                         0x000007FFL
24746 //VGT_ES_PER_GS
24747 #define VGT_ES_PER_GS__ES_PER_GS__SHIFT                                                                       0x0
24748 #define VGT_ES_PER_GS__ES_PER_GS_MASK                                                                         0x000007FFL
24749 //VGT_GS_PER_VS
24750 #define VGT_GS_PER_VS__GS_PER_VS__SHIFT                                                                       0x0
24751 #define VGT_GS_PER_VS__GS_PER_VS_MASK                                                                         0x0000000FL
24752 //VGT_GSVS_RING_OFFSET_1
24753 #define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT                                                                 0x0
24754 #define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK                                                                   0x00007FFFL
24755 //VGT_GSVS_RING_OFFSET_2
24756 #define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT                                                                 0x0
24757 #define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK                                                                   0x00007FFFL
24758 //VGT_GSVS_RING_OFFSET_3
24759 #define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT                                                                 0x0
24760 #define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK                                                                   0x00007FFFL
24761 //VGT_GS_OUT_PRIM_TYPE
24762 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT                                                             0x0
24763 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT                                                           0x8
24764 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT                                                           0x10
24765 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT                                                           0x16
24766 #define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT                                                   0x1f
24767 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK                                                               0x0000003FL
24768 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK                                                             0x00003F00L
24769 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK                                                             0x003F0000L
24770 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK                                                             0x0FC00000L
24771 #define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK                                                     0x80000000L
24772 //IA_ENHANCE
24773 #define IA_ENHANCE__MISC__SHIFT                                                                               0x0
24774 #define IA_ENHANCE__MISC_MASK                                                                                 0xFFFFFFFFL
24775 //VGT_DMA_SIZE
24776 #define VGT_DMA_SIZE__NUM_INDICES__SHIFT                                                                      0x0
24777 #define VGT_DMA_SIZE__NUM_INDICES_MASK                                                                        0xFFFFFFFFL
24778 //VGT_DMA_MAX_SIZE
24779 #define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT                                                                     0x0
24780 #define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK                                                                       0xFFFFFFFFL
24781 //VGT_DMA_INDEX_TYPE
24782 #define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT                                                                 0x0
24783 #define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT                                                                  0x2
24784 #define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT                                                                   0x4
24785 #define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT                                                               0x6
24786 #define VGT_DMA_INDEX_TYPE__ATC__SHIFT                                                                        0x8
24787 #define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT                                                                    0x9
24788 #define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT                                                                   0xa
24789 #define VGT_DMA_INDEX_TYPE__MTYPE__SHIFT                                                                      0xb
24790 #define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK                                                                   0x00000003L
24791 #define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK                                                                    0x0000000CL
24792 #define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK                                                                     0x00000030L
24793 #define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK                                                                 0x000000C0L
24794 #define VGT_DMA_INDEX_TYPE__ATC_MASK                                                                          0x00000100L
24795 #define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK                                                                      0x00000200L
24796 #define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK                                                                     0x00000400L
24797 #define VGT_DMA_INDEX_TYPE__MTYPE_MASK                                                                        0x00003800L
24798 //WD_ENHANCE
24799 #define WD_ENHANCE__MISC__SHIFT                                                                               0x0
24800 #define WD_ENHANCE__MISC_MASK                                                                                 0xFFFFFFFFL
24801 //VGT_PRIMITIVEID_EN
24802 #define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT                                                             0x0
24803 #define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT                                                       0x1
24804 #define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE__SHIFT                                                   0x2
24805 #define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK                                                               0x00000001L
24806 #define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK                                                         0x00000002L
24807 #define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE_MASK                                                     0x00000004L
24808 //VGT_DMA_NUM_INSTANCES
24809 #define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT                                                           0x0
24810 #define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK                                                             0xFFFFFFFFL
24811 //VGT_PRIMITIVEID_RESET
24812 #define VGT_PRIMITIVEID_RESET__VALUE__SHIFT                                                                   0x0
24813 #define VGT_PRIMITIVEID_RESET__VALUE_MASK                                                                     0xFFFFFFFFL
24814 //VGT_EVENT_INITIATOR
24815 #define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT                                                                0x0
24816 #define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT                                                                0xa
24817 #define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT                                                            0x1b
24818 #define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK                                                                  0x0000003FL
24819 #define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK                                                                  0x07FFFC00L
24820 #define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK                                                              0x08000000L
24821 //VGT_MULTI_PRIM_IB_RESET_EN
24822 #define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT                                                           0x0
24823 #define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT                                                     0x1
24824 #define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK                                                             0x00000001L
24825 #define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK                                                       0x00000002L
24826 //VGT_DRAW_PAYLOAD_CNTL
24827 #define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN__SHIFT                                                           0x0
24828 #define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX__SHIFT                                                         0x1
24829 #define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN__SHIFT                                                       0x2
24830 #define VGT_DRAW_PAYLOAD_CNTL__EN_PRIM_PAYLOAD__SHIFT                                                         0x3
24831 #define VGT_DRAW_PAYLOAD_CNTL__EN_DRAW_VP__SHIFT                                                              0x4
24832 #define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN_MASK                                                             0x00000001L
24833 #define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX_MASK                                                           0x00000002L
24834 #define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN_MASK                                                         0x00000004L
24835 #define VGT_DRAW_PAYLOAD_CNTL__EN_PRIM_PAYLOAD_MASK                                                           0x00000008L
24836 #define VGT_DRAW_PAYLOAD_CNTL__EN_DRAW_VP_MASK                                                                0x00000010L
24837 //VGT_INSTANCE_STEP_RATE_0
24838 #define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT                                                            0x0
24839 #define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK                                                              0xFFFFFFFFL
24840 //VGT_INSTANCE_STEP_RATE_1
24841 #define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT                                                            0x0
24842 #define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK                                                              0xFFFFFFFFL
24843 //IA_MULTI_VGT_PARAM
24844 #define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT                                                             0x0
24845 #define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT                                                         0x10
24846 #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT                                                              0x11
24847 #define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT                                                         0x12
24848 #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT                                                              0x13
24849 #define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT                                                           0x14
24850 #define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK                                                               0x0000FFFFL
24851 #define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK                                                           0x00010000L
24852 #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK                                                                0x00020000L
24853 #define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK                                                           0x00040000L
24854 #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK                                                                0x00080000L
24855 #define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK                                                             0x00100000L
24856 //VGT_ESGS_RING_ITEMSIZE
24857 #define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT                                                               0x0
24858 #define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK                                                                 0x00007FFFL
24859 //VGT_GSVS_RING_ITEMSIZE
24860 #define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT                                                               0x0
24861 #define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK                                                                 0x00007FFFL
24862 //VGT_REUSE_OFF
24863 #define VGT_REUSE_OFF__REUSE_OFF__SHIFT                                                                       0x0
24864 #define VGT_REUSE_OFF__REUSE_OFF_MASK                                                                         0x00000001L
24865 //VGT_VTX_CNT_EN
24866 #define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT                                                                     0x0
24867 #define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK                                                                       0x00000001L
24868 //DB_HTILE_SURFACE
24869 #define DB_HTILE_SURFACE__RESERVED_FIELD_1__SHIFT                                                             0x0
24870 #define DB_HTILE_SURFACE__FULL_CACHE__SHIFT                                                                   0x1
24871 #define DB_HTILE_SURFACE__RESERVED_FIELD_2__SHIFT                                                             0x2
24872 #define DB_HTILE_SURFACE__RESERVED_FIELD_3__SHIFT                                                             0x3
24873 #define DB_HTILE_SURFACE__RESERVED_FIELD_4__SHIFT                                                             0x4
24874 #define DB_HTILE_SURFACE__RESERVED_FIELD_5__SHIFT                                                             0xa
24875 #define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT                                                      0x10
24876 #define DB_HTILE_SURFACE__RESERVED_FIELD_6__SHIFT                                                             0x11
24877 #define DB_HTILE_SURFACE__PIPE_ALIGNED__SHIFT                                                                 0x12
24878 #define DB_HTILE_SURFACE__RESERVED_FIELD_1_MASK                                                               0x00000001L
24879 #define DB_HTILE_SURFACE__FULL_CACHE_MASK                                                                     0x00000002L
24880 #define DB_HTILE_SURFACE__RESERVED_FIELD_2_MASK                                                               0x00000004L
24881 #define DB_HTILE_SURFACE__RESERVED_FIELD_3_MASK                                                               0x00000008L
24882 #define DB_HTILE_SURFACE__RESERVED_FIELD_4_MASK                                                               0x000003F0L
24883 #define DB_HTILE_SURFACE__RESERVED_FIELD_5_MASK                                                               0x0000FC00L
24884 #define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK                                                        0x00010000L
24885 #define DB_HTILE_SURFACE__RESERVED_FIELD_6_MASK                                                               0x00020000L
24886 #define DB_HTILE_SURFACE__PIPE_ALIGNED_MASK                                                                   0x00040000L
24887 //DB_SRESULTS_COMPARE_STATE0
24888 #define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT                                                       0x0
24889 #define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT                                                      0x4
24890 #define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT                                                       0xc
24891 #define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT                                                            0x18
24892 #define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK                                                         0x00000007L
24893 #define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK                                                        0x00000FF0L
24894 #define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK                                                         0x000FF000L
24895 #define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK                                                              0x01000000L
24896 //DB_SRESULTS_COMPARE_STATE1
24897 #define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT                                                       0x0
24898 #define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT                                                      0x4
24899 #define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT                                                       0xc
24900 #define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT                                                            0x18
24901 #define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK                                                         0x00000007L
24902 #define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK                                                        0x00000FF0L
24903 #define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK                                                         0x000FF000L
24904 #define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK                                                              0x01000000L
24905 //DB_PRELOAD_CONTROL
24906 #define DB_PRELOAD_CONTROL__START_X__SHIFT                                                                    0x0
24907 #define DB_PRELOAD_CONTROL__START_Y__SHIFT                                                                    0x8
24908 #define DB_PRELOAD_CONTROL__MAX_X__SHIFT                                                                      0x10
24909 #define DB_PRELOAD_CONTROL__MAX_Y__SHIFT                                                                      0x18
24910 #define DB_PRELOAD_CONTROL__START_X_MASK                                                                      0x000000FFL
24911 #define DB_PRELOAD_CONTROL__START_Y_MASK                                                                      0x0000FF00L
24912 #define DB_PRELOAD_CONTROL__MAX_X_MASK                                                                        0x00FF0000L
24913 #define DB_PRELOAD_CONTROL__MAX_Y_MASK                                                                        0xFF000000L
24914 //VGT_STRMOUT_BUFFER_SIZE_0
24915 #define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT                                                                0x0
24916 #define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK                                                                  0xFFFFFFFFL
24917 //VGT_STRMOUT_VTX_STRIDE_0
24918 #define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT                                                               0x0
24919 #define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK                                                                 0x000003FFL
24920 //VGT_STRMOUT_BUFFER_OFFSET_0
24921 #define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT                                                            0x0
24922 #define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK                                                              0xFFFFFFFFL
24923 //VGT_STRMOUT_BUFFER_SIZE_1
24924 #define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT                                                                0x0
24925 #define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK                                                                  0xFFFFFFFFL
24926 //VGT_STRMOUT_VTX_STRIDE_1
24927 #define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT                                                               0x0
24928 #define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK                                                                 0x000003FFL
24929 //VGT_STRMOUT_BUFFER_OFFSET_1
24930 #define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT                                                            0x0
24931 #define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK                                                              0xFFFFFFFFL
24932 //VGT_STRMOUT_BUFFER_SIZE_2
24933 #define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT                                                                0x0
24934 #define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK                                                                  0xFFFFFFFFL
24935 //VGT_STRMOUT_VTX_STRIDE_2
24936 #define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT                                                               0x0
24937 #define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK                                                                 0x000003FFL
24938 //VGT_STRMOUT_BUFFER_OFFSET_2
24939 #define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT                                                            0x0
24940 #define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK                                                              0xFFFFFFFFL
24941 //VGT_STRMOUT_BUFFER_SIZE_3
24942 #define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT                                                                0x0
24943 #define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK                                                                  0xFFFFFFFFL
24944 //VGT_STRMOUT_VTX_STRIDE_3
24945 #define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT                                                               0x0
24946 #define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK                                                                 0x000003FFL
24947 //VGT_STRMOUT_BUFFER_OFFSET_3
24948 #define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT                                                            0x0
24949 #define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK                                                              0xFFFFFFFFL
24950 //VGT_STRMOUT_DRAW_OPAQUE_OFFSET
24951 #define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT                                                         0x0
24952 #define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK                                                           0xFFFFFFFFL
24953 //VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
24954 #define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT                                               0x0
24955 #define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK                                                 0xFFFFFFFFL
24956 //VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
24957 #define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT                                           0x0
24958 #define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK                                             0x000001FFL
24959 //VGT_GS_MAX_VERT_OUT
24960 #define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT                                                              0x0
24961 #define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK                                                                0x000007FFL
24962 //GE_NGG_SUBGRP_CNTL
24963 #define GE_NGG_SUBGRP_CNTL__PRIM_AMP_FACTOR__SHIFT                                                            0x0
24964 #define GE_NGG_SUBGRP_CNTL__THDS_PER_SUBGRP__SHIFT                                                            0x9
24965 #define GE_NGG_SUBGRP_CNTL__PRIM_AMP_FACTOR_MASK                                                              0x000001FFL
24966 #define GE_NGG_SUBGRP_CNTL__THDS_PER_SUBGRP_MASK                                                              0x0003FE00L
24967 //VGT_TESS_DISTRIBUTION
24968 #define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT                                                           0x0
24969 #define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT                                                               0x8
24970 #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT                                                              0x10
24971 #define VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT                                                             0x18
24972 #define VGT_TESS_DISTRIBUTION__TRAP_SPLIT__SHIFT                                                              0x1d
24973 #define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK                                                             0x000000FFL
24974 #define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK                                                                 0x0000FF00L
24975 #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK                                                                0x00FF0000L
24976 #define VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK                                                               0x1F000000L
24977 #define VGT_TESS_DISTRIBUTION__TRAP_SPLIT_MASK                                                                0xE0000000L
24978 //VGT_SHADER_STAGES_EN
24979 #define VGT_SHADER_STAGES_EN__LS_EN__SHIFT                                                                    0x0
24980 #define VGT_SHADER_STAGES_EN__HS_EN__SHIFT                                                                    0x2
24981 #define VGT_SHADER_STAGES_EN__ES_EN__SHIFT                                                                    0x3
24982 #define VGT_SHADER_STAGES_EN__GS_EN__SHIFT                                                                    0x5
24983 #define VGT_SHADER_STAGES_EN__VS_EN__SHIFT                                                                    0x6
24984 #define VGT_SHADER_STAGES_EN__DYNAMIC_HS__SHIFT                                                               0x8
24985 #define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN__SHIFT                                                         0x9
24986 #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT                                                      0xa
24987 #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1__SHIFT                                                      0xb
24988 #define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT                                                            0xc
24989 #define VGT_SHADER_STAGES_EN__PRIMGEN_EN__SHIFT                                                               0xd
24990 #define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE__SHIFT                                                          0xe
24991 #define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE__SHIFT                                                      0xf
24992 #define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH__SHIFT                                                           0x13
24993 #define VGT_SHADER_STAGES_EN__HS_W32_EN__SHIFT                                                                0x15
24994 #define VGT_SHADER_STAGES_EN__GS_W32_EN__SHIFT                                                                0x16
24995 #define VGT_SHADER_STAGES_EN__VS_W32_EN__SHIFT                                                                0x17
24996 #define VGT_SHADER_STAGES_EN__NGG_WAVE_ID_EN__SHIFT                                                           0x18
24997 #define VGT_SHADER_STAGES_EN__PRIMGEN_PASSTHRU_EN__SHIFT                                                      0x19
24998 #define VGT_SHADER_STAGES_EN__LS_EN_MASK                                                                      0x00000003L
24999 #define VGT_SHADER_STAGES_EN__HS_EN_MASK                                                                      0x00000004L
25000 #define VGT_SHADER_STAGES_EN__ES_EN_MASK                                                                      0x00000018L
25001 #define VGT_SHADER_STAGES_EN__GS_EN_MASK                                                                      0x00000020L
25002 #define VGT_SHADER_STAGES_EN__VS_EN_MASK                                                                      0x000000C0L
25003 #define VGT_SHADER_STAGES_EN__DYNAMIC_HS_MASK                                                                 0x00000100L
25004 #define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN_MASK                                                           0x00000200L
25005 #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0_MASK                                                        0x00000400L
25006 #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1_MASK                                                        0x00000800L
25007 #define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK                                                              0x00001000L
25008 #define VGT_SHADER_STAGES_EN__PRIMGEN_EN_MASK                                                                 0x00002000L
25009 #define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE_MASK                                                            0x00004000L
25010 #define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE_MASK                                                        0x00078000L
25011 #define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH_MASK                                                             0x00180000L
25012 #define VGT_SHADER_STAGES_EN__HS_W32_EN_MASK                                                                  0x00200000L
25013 #define VGT_SHADER_STAGES_EN__GS_W32_EN_MASK                                                                  0x00400000L
25014 #define VGT_SHADER_STAGES_EN__VS_W32_EN_MASK                                                                  0x00800000L
25015 #define VGT_SHADER_STAGES_EN__NGG_WAVE_ID_EN_MASK                                                             0x01000000L
25016 #define VGT_SHADER_STAGES_EN__PRIMGEN_PASSTHRU_EN_MASK                                                        0x02000000L
25017 //VGT_LS_HS_CONFIG
25018 #define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT                                                                  0x0
25019 #define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT                                                              0x8
25020 #define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT                                                             0xe
25021 #define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK                                                                    0x000000FFL
25022 #define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK                                                                0x00003F00L
25023 #define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK                                                               0x000FC000L
25024 //VGT_GS_VERT_ITEMSIZE
25025 #define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT                                                                 0x0
25026 #define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK                                                                   0x00007FFFL
25027 //VGT_GS_VERT_ITEMSIZE_1
25028 #define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT                                                               0x0
25029 #define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK                                                                 0x00007FFFL
25030 //VGT_GS_VERT_ITEMSIZE_2
25031 #define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT                                                               0x0
25032 #define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK                                                                 0x00007FFFL
25033 //VGT_GS_VERT_ITEMSIZE_3
25034 #define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT                                                               0x0
25035 #define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK                                                                 0x00007FFFL
25036 //VGT_TF_PARAM
25037 #define VGT_TF_PARAM__TYPE__SHIFT                                                                             0x0
25038 #define VGT_TF_PARAM__PARTITIONING__SHIFT                                                                     0x2
25039 #define VGT_TF_PARAM__TOPOLOGY__SHIFT                                                                         0x5
25040 #define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT                                                              0x8
25041 #define VGT_TF_PARAM__DEPRECATED__SHIFT                                                                       0x9
25042 #define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD__SHIFT                                                            0xa
25043 #define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT                                                                   0xe
25044 #define VGT_TF_PARAM__RDREQ_POLICY__SHIFT                                                                     0xf
25045 #define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT                                                                0x11
25046 #define VGT_TF_PARAM__DETECT_ONE__SHIFT                                                                       0x13
25047 #define VGT_TF_PARAM__DETECT_ZERO__SHIFT                                                                      0x14
25048 #define VGT_TF_PARAM__MTYPE__SHIFT                                                                            0x17
25049 #define VGT_TF_PARAM__TYPE_MASK                                                                               0x00000003L
25050 #define VGT_TF_PARAM__PARTITIONING_MASK                                                                       0x0000001CL
25051 #define VGT_TF_PARAM__TOPOLOGY_MASK                                                                           0x000000E0L
25052 #define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK                                                                0x00000100L
25053 #define VGT_TF_PARAM__DEPRECATED_MASK                                                                         0x00000200L
25054 #define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD_MASK                                                              0x00003C00L
25055 #define VGT_TF_PARAM__DISABLE_DONUTS_MASK                                                                     0x00004000L
25056 #define VGT_TF_PARAM__RDREQ_POLICY_MASK                                                                       0x00018000L
25057 #define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK                                                                  0x00060000L
25058 #define VGT_TF_PARAM__DETECT_ONE_MASK                                                                         0x00080000L
25059 #define VGT_TF_PARAM__DETECT_ZERO_MASK                                                                        0x00100000L
25060 #define VGT_TF_PARAM__MTYPE_MASK                                                                              0x03800000L
25061 //DB_ALPHA_TO_MASK
25062 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT                                                         0x0
25063 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT                                                        0x8
25064 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT                                                        0xa
25065 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT                                                        0xc
25066 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT                                                        0xe
25067 #define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT                                                                 0x10
25068 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK                                                           0x00000001L
25069 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK                                                          0x00000300L
25070 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK                                                          0x00000C00L
25071 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK                                                          0x00003000L
25072 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK                                                          0x0000C000L
25073 #define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK                                                                   0x00010000L
25074 //VGT_DISPATCH_DRAW_INDEX
25075 #define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT                                                           0x0
25076 #define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK                                                             0xFFFFFFFFL
25077 //PA_SU_POLY_OFFSET_DB_FMT_CNTL
25078 #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT                                     0x0
25079 #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT                                     0x8
25080 #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK                                       0x000000FFL
25081 #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK                                       0x00000100L
25082 //PA_SU_POLY_OFFSET_CLAMP
25083 #define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT                                                                 0x0
25084 #define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK                                                                   0xFFFFFFFFL
25085 //PA_SU_POLY_OFFSET_FRONT_SCALE
25086 #define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT                                                           0x0
25087 #define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK                                                             0xFFFFFFFFL
25088 //PA_SU_POLY_OFFSET_FRONT_OFFSET
25089 #define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT                                                         0x0
25090 #define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK                                                           0xFFFFFFFFL
25091 //PA_SU_POLY_OFFSET_BACK_SCALE
25092 #define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT                                                            0x0
25093 #define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK                                                              0xFFFFFFFFL
25094 //PA_SU_POLY_OFFSET_BACK_OFFSET
25095 #define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT                                                          0x0
25096 #define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK                                                            0xFFFFFFFFL
25097 //VGT_GS_INSTANCE_CNT
25098 #define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT                                                                    0x0
25099 #define VGT_GS_INSTANCE_CNT__CNT__SHIFT                                                                       0x2
25100 #define VGT_GS_INSTANCE_CNT__EN_MAX_VERT_OUT_PER_GS_INSTANCE__SHIFT                                           0x1f
25101 #define VGT_GS_INSTANCE_CNT__ENABLE_MASK                                                                      0x00000001L
25102 #define VGT_GS_INSTANCE_CNT__CNT_MASK                                                                         0x000001FCL
25103 #define VGT_GS_INSTANCE_CNT__EN_MAX_VERT_OUT_PER_GS_INSTANCE_MASK                                             0x80000000L
25104 //VGT_STRMOUT_CONFIG
25105 #define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT                                                             0x0
25106 #define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT                                                             0x1
25107 #define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT                                                             0x2
25108 #define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT                                                             0x3
25109 #define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT                                                                0x4
25110 #define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT__SHIFT                                                        0x7
25111 #define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT                                                           0x8
25112 #define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT                                                       0x1f
25113 #define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK                                                               0x00000001L
25114 #define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK                                                               0x00000002L
25115 #define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK                                                               0x00000004L
25116 #define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK                                                               0x00000008L
25117 #define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK                                                                  0x00000070L
25118 #define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT_MASK                                                          0x00000080L
25119 #define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK                                                             0x00000F00L
25120 #define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK                                                         0x80000000L
25121 //VGT_STRMOUT_BUFFER_CONFIG
25122 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT                                                  0x0
25123 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT                                                  0x4
25124 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT                                                  0x8
25125 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT                                                  0xc
25126 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK                                                    0x0000000FL
25127 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK                                                    0x000000F0L
25128 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK                                                    0x00000F00L
25129 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK                                                    0x0000F000L
25130 //VGT_DMA_EVENT_INITIATOR
25131 #define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE__SHIFT                                                            0x0
25132 #define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI__SHIFT                                                            0xa
25133 #define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT                                                        0x1b
25134 #define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE_MASK                                                              0x0000003FL
25135 #define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI_MASK                                                              0x07FFFC00L
25136 #define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT_MASK                                                          0x08000000L
25137 //PA_SC_CENTROID_PRIORITY_0
25138 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT                                                          0x0
25139 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT                                                          0x4
25140 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT                                                          0x8
25141 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT                                                          0xc
25142 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT                                                          0x10
25143 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT                                                          0x14
25144 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT                                                          0x18
25145 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT                                                          0x1c
25146 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK                                                            0x0000000FL
25147 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK                                                            0x000000F0L
25148 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK                                                            0x00000F00L
25149 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK                                                            0x0000F000L
25150 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK                                                            0x000F0000L
25151 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK                                                            0x00F00000L
25152 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK                                                            0x0F000000L
25153 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK                                                            0xF0000000L
25154 //PA_SC_CENTROID_PRIORITY_1
25155 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT                                                          0x0
25156 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT                                                          0x4
25157 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT                                                         0x8
25158 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT                                                         0xc
25159 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT                                                         0x10
25160 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT                                                         0x14
25161 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT                                                         0x18
25162 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT                                                         0x1c
25163 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK                                                            0x0000000FL
25164 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK                                                            0x000000F0L
25165 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK                                                           0x00000F00L
25166 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK                                                           0x0000F000L
25167 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK                                                           0x000F0000L
25168 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK                                                           0x00F00000L
25169 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK                                                           0x0F000000L
25170 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK                                                           0xF0000000L
25171 //PA_SC_LINE_CNTL
25172 #define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT                                                             0x9
25173 #define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT                                                                    0xa
25174 #define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT                                                      0xb
25175 #define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT                                                         0xc
25176 #define PA_SC_LINE_CNTL__EXTRA_DX_DY_PRECISION__SHIFT                                                         0xd
25177 #define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK                                                               0x00000200L
25178 #define PA_SC_LINE_CNTL__LAST_PIXEL_MASK                                                                      0x00000400L
25179 #define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK                                                        0x00000800L
25180 #define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK                                                           0x00001000L
25181 #define PA_SC_LINE_CNTL__EXTRA_DX_DY_PRECISION_MASK                                                           0x00002000L
25182 //PA_SC_AA_CONFIG
25183 #define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT                                                              0x0
25184 #define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT                                                         0x4
25185 #define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT                                                               0xd
25186 #define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT                                                          0x14
25187 #define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT                                                        0x18
25188 #define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT__SHIFT                                                     0x1a
25189 #define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK                                                                0x00000007L
25190 #define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK                                                           0x00000010L
25191 #define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK                                                                 0x0001E000L
25192 #define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK                                                            0x00700000L
25193 #define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK                                                          0x03000000L
25194 #define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT_MASK                                                       0x0C000000L
25195 //PA_SU_VTX_CNTL
25196 #define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT                                                                     0x0
25197 #define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT                                                                     0x1
25198 #define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT                                                                     0x3
25199 #define PA_SU_VTX_CNTL__PIX_CENTER_MASK                                                                       0x00000001L
25200 #define PA_SU_VTX_CNTL__ROUND_MODE_MASK                                                                       0x00000006L
25201 #define PA_SU_VTX_CNTL__QUANT_MODE_MASK                                                                       0x00000038L
25202 //PA_CL_GB_VERT_CLIP_ADJ
25203 #define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT                                                          0x0
25204 #define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK                                                            0xFFFFFFFFL
25205 //PA_CL_GB_VERT_DISC_ADJ
25206 #define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT                                                          0x0
25207 #define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK                                                            0xFFFFFFFFL
25208 //PA_CL_GB_HORZ_CLIP_ADJ
25209 #define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT                                                          0x0
25210 #define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK                                                            0xFFFFFFFFL
25211 //PA_CL_GB_HORZ_DISC_ADJ
25212 #define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT                                                          0x0
25213 #define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK                                                            0xFFFFFFFFL
25214 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
25215 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT                                                        0x0
25216 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT                                                        0x4
25217 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT                                                        0x8
25218 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT                                                        0xc
25219 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT                                                        0x10
25220 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT                                                        0x14
25221 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT                                                        0x18
25222 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT                                                        0x1c
25223 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK                                                          0x0000000FL
25224 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK                                                          0x000000F0L
25225 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK                                                          0x00000F00L
25226 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK                                                          0x0000F000L
25227 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK                                                          0x000F0000L
25228 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK                                                          0x00F00000L
25229 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK                                                          0x0F000000L
25230 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK                                                          0xF0000000L
25231 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
25232 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT                                                        0x0
25233 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT                                                        0x4
25234 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT                                                        0x8
25235 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT                                                        0xc
25236 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT                                                        0x10
25237 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT                                                        0x14
25238 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT                                                        0x18
25239 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT                                                        0x1c
25240 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK                                                          0x0000000FL
25241 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK                                                          0x000000F0L
25242 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK                                                          0x00000F00L
25243 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK                                                          0x0000F000L
25244 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK                                                          0x000F0000L
25245 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK                                                          0x00F00000L
25246 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK                                                          0x0F000000L
25247 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK                                                          0xF0000000L
25248 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2
25249 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT                                                        0x0
25250 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT                                                        0x4
25251 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT                                                        0x8
25252 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT                                                        0xc
25253 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT                                                       0x10
25254 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT                                                       0x14
25255 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT                                                       0x18
25256 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT                                                       0x1c
25257 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK                                                          0x0000000FL
25258 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK                                                          0x000000F0L
25259 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK                                                          0x00000F00L
25260 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK                                                          0x0000F000L
25261 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK                                                         0x000F0000L
25262 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK                                                         0x00F00000L
25263 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK                                                         0x0F000000L
25264 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK                                                         0xF0000000L
25265 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3
25266 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT                                                       0x0
25267 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT                                                       0x4
25268 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT                                                       0x8
25269 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT                                                       0xc
25270 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT                                                       0x10
25271 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT                                                       0x14
25272 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT                                                       0x18
25273 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT                                                       0x1c
25274 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK                                                         0x0000000FL
25275 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK                                                         0x000000F0L
25276 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK                                                         0x00000F00L
25277 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK                                                         0x0000F000L
25278 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK                                                         0x000F0000L
25279 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK                                                         0x00F00000L
25280 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK                                                         0x0F000000L
25281 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK                                                         0xF0000000L
25282 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
25283 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT                                                        0x0
25284 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT                                                        0x4
25285 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT                                                        0x8
25286 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT                                                        0xc
25287 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT                                                        0x10
25288 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT                                                        0x14
25289 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT                                                        0x18
25290 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT                                                        0x1c
25291 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK                                                          0x0000000FL
25292 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK                                                          0x000000F0L
25293 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK                                                          0x00000F00L
25294 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK                                                          0x0000F000L
25295 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK                                                          0x000F0000L
25296 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK                                                          0x00F00000L
25297 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK                                                          0x0F000000L
25298 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK                                                          0xF0000000L
25299 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
25300 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT                                                        0x0
25301 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT                                                        0x4
25302 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT                                                        0x8
25303 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT                                                        0xc
25304 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT                                                        0x10
25305 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT                                                        0x14
25306 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT                                                        0x18
25307 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT                                                        0x1c
25308 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK                                                          0x0000000FL
25309 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK                                                          0x000000F0L
25310 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK                                                          0x00000F00L
25311 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK                                                          0x0000F000L
25312 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK                                                          0x000F0000L
25313 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK                                                          0x00F00000L
25314 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK                                                          0x0F000000L
25315 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK                                                          0xF0000000L
25316 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2
25317 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT                                                        0x0
25318 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT                                                        0x4
25319 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT                                                        0x8
25320 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT                                                        0xc
25321 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT                                                       0x10
25322 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT                                                       0x14
25323 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT                                                       0x18
25324 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT                                                       0x1c
25325 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK                                                          0x0000000FL
25326 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK                                                          0x000000F0L
25327 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK                                                          0x00000F00L
25328 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK                                                          0x0000F000L
25329 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK                                                         0x000F0000L
25330 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK                                                         0x00F00000L
25331 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK                                                         0x0F000000L
25332 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK                                                         0xF0000000L
25333 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3
25334 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT                                                       0x0
25335 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT                                                       0x4
25336 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT                                                       0x8
25337 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT                                                       0xc
25338 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT                                                       0x10
25339 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT                                                       0x14
25340 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT                                                       0x18
25341 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT                                                       0x1c
25342 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK                                                         0x0000000FL
25343 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK                                                         0x000000F0L
25344 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK                                                         0x00000F00L
25345 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK                                                         0x0000F000L
25346 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK                                                         0x000F0000L
25347 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK                                                         0x00F00000L
25348 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK                                                         0x0F000000L
25349 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK                                                         0xF0000000L
25350 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
25351 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT                                                        0x0
25352 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT                                                        0x4
25353 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT                                                        0x8
25354 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT                                                        0xc
25355 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT                                                        0x10
25356 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT                                                        0x14
25357 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT                                                        0x18
25358 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT                                                        0x1c
25359 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK                                                          0x0000000FL
25360 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK                                                          0x000000F0L
25361 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK                                                          0x00000F00L
25362 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK                                                          0x0000F000L
25363 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK                                                          0x000F0000L
25364 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK                                                          0x00F00000L
25365 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK                                                          0x0F000000L
25366 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK                                                          0xF0000000L
25367 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
25368 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT                                                        0x0
25369 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT                                                        0x4
25370 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT                                                        0x8
25371 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT                                                        0xc
25372 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT                                                        0x10
25373 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT                                                        0x14
25374 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT                                                        0x18
25375 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT                                                        0x1c
25376 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK                                                          0x0000000FL
25377 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK                                                          0x000000F0L
25378 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK                                                          0x00000F00L
25379 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK                                                          0x0000F000L
25380 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK                                                          0x000F0000L
25381 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK                                                          0x00F00000L
25382 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK                                                          0x0F000000L
25383 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK                                                          0xF0000000L
25384 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2
25385 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT                                                        0x0
25386 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT                                                        0x4
25387 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT                                                        0x8
25388 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT                                                        0xc
25389 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT                                                       0x10
25390 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT                                                       0x14
25391 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT                                                       0x18
25392 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT                                                       0x1c
25393 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK                                                          0x0000000FL
25394 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK                                                          0x000000F0L
25395 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK                                                          0x00000F00L
25396 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK                                                          0x0000F000L
25397 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK                                                         0x000F0000L
25398 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK                                                         0x00F00000L
25399 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK                                                         0x0F000000L
25400 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK                                                         0xF0000000L
25401 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3
25402 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT                                                       0x0
25403 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT                                                       0x4
25404 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT                                                       0x8
25405 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT                                                       0xc
25406 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT                                                       0x10
25407 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT                                                       0x14
25408 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT                                                       0x18
25409 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT                                                       0x1c
25410 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK                                                         0x0000000FL
25411 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK                                                         0x000000F0L
25412 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK                                                         0x00000F00L
25413 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK                                                         0x0000F000L
25414 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK                                                         0x000F0000L
25415 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK                                                         0x00F00000L
25416 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK                                                         0x0F000000L
25417 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK                                                         0xF0000000L
25418 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
25419 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT                                                        0x0
25420 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT                                                        0x4
25421 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT                                                        0x8
25422 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT                                                        0xc
25423 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT                                                        0x10
25424 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT                                                        0x14
25425 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT                                                        0x18
25426 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT                                                        0x1c
25427 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK                                                          0x0000000FL
25428 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK                                                          0x000000F0L
25429 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK                                                          0x00000F00L
25430 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK                                                          0x0000F000L
25431 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK                                                          0x000F0000L
25432 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK                                                          0x00F00000L
25433 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK                                                          0x0F000000L
25434 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK                                                          0xF0000000L
25435 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
25436 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT                                                        0x0
25437 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT                                                        0x4
25438 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT                                                        0x8
25439 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT                                                        0xc
25440 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT                                                        0x10
25441 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT                                                        0x14
25442 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT                                                        0x18
25443 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT                                                        0x1c
25444 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK                                                          0x0000000FL
25445 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK                                                          0x000000F0L
25446 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK                                                          0x00000F00L
25447 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK                                                          0x0000F000L
25448 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK                                                          0x000F0000L
25449 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK                                                          0x00F00000L
25450 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK                                                          0x0F000000L
25451 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK                                                          0xF0000000L
25452 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2
25453 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT                                                        0x0
25454 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT                                                        0x4
25455 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT                                                        0x8
25456 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT                                                        0xc
25457 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT                                                       0x10
25458 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT                                                       0x14
25459 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT                                                       0x18
25460 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT                                                       0x1c
25461 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK                                                          0x0000000FL
25462 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK                                                          0x000000F0L
25463 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK                                                          0x00000F00L
25464 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK                                                          0x0000F000L
25465 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK                                                         0x000F0000L
25466 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK                                                         0x00F00000L
25467 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK                                                         0x0F000000L
25468 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK                                                         0xF0000000L
25469 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3
25470 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT                                                       0x0
25471 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT                                                       0x4
25472 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT                                                       0x8
25473 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT                                                       0xc
25474 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT                                                       0x10
25475 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT                                                       0x14
25476 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT                                                       0x18
25477 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT                                                       0x1c
25478 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK                                                         0x0000000FL
25479 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK                                                         0x000000F0L
25480 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK                                                         0x00000F00L
25481 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK                                                         0x0000F000L
25482 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK                                                         0x000F0000L
25483 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK                                                         0x00F00000L
25484 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK                                                         0x0F000000L
25485 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK                                                         0xF0000000L
25486 //PA_SC_AA_MASK_X0Y0_X1Y0
25487 #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT                                                          0x0
25488 #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT                                                          0x10
25489 #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK                                                            0x0000FFFFL
25490 #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK                                                            0xFFFF0000L
25491 //PA_SC_AA_MASK_X0Y1_X1Y1
25492 #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT                                                          0x0
25493 #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT                                                          0x10
25494 #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK                                                            0x0000FFFFL
25495 #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK                                                            0xFFFF0000L
25496 //PA_SC_SHADER_CONTROL
25497 #define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES__SHIFT                                             0x0
25498 #define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID__SHIFT                                                    0x2
25499 #define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION__SHIFT                                                 0x3
25500 #define PA_SC_SHADER_CONTROL__WAVE_BREAK_REGION_SIZE__SHIFT                                                   0x5
25501 #define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES_MASK                                               0x00000003L
25502 #define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID_MASK                                                      0x00000004L
25503 #define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION_MASK                                                   0x00000008L
25504 #define PA_SC_SHADER_CONTROL__WAVE_BREAK_REGION_SIZE_MASK                                                     0x00000060L
25505 //PA_SC_BINNER_CNTL_0
25506 #define PA_SC_BINNER_CNTL_0__BINNING_MODE__SHIFT                                                              0x0
25507 #define PA_SC_BINNER_CNTL_0__BIN_SIZE_X__SHIFT                                                                0x2
25508 #define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y__SHIFT                                                                0x3
25509 #define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND__SHIFT                                                         0x4
25510 #define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND__SHIFT                                                         0x7
25511 #define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN__SHIFT                                                    0xa
25512 #define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN__SHIFT                                                 0xd
25513 #define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM__SHIFT                                                     0x12
25514 #define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT                                                           0x13
25515 #define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION__SHIFT                                                     0x1b
25516 #define PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION__SHIFT                                               0x1c
25517 #define PA_SC_BINNER_CNTL_0__BIN_MAPPING_MODE__SHIFT                                                          0x1d
25518 #define PA_SC_BINNER_CNTL_0__BINNING_MODE_MASK                                                                0x00000003L
25519 #define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_MASK                                                                  0x00000004L
25520 #define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_MASK                                                                  0x00000008L
25521 #define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND_MASK                                                           0x00000070L
25522 #define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND_MASK                                                           0x00000380L
25523 #define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN_MASK                                                      0x00001C00L
25524 #define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN_MASK                                                   0x0003E000L
25525 #define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM_MASK                                                       0x00040000L
25526 #define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH_MASK                                                             0x07F80000L
25527 #define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION_MASK                                                       0x08000000L
25528 #define PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION_MASK                                                 0x10000000L
25529 #define PA_SC_BINNER_CNTL_0__BIN_MAPPING_MODE_MASK                                                            0x60000000L
25530 //PA_SC_BINNER_CNTL_1
25531 #define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT__SHIFT                                                           0x0
25532 #define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH__SHIFT                                                        0x10
25533 #define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT_MASK                                                             0x0000FFFFL
25534 #define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH_MASK                                                          0xFFFF0000L
25535 //PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
25536 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE__SHIFT                                        0x0
25537 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT__SHIFT                                 0x1
25538 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE__SHIFT                                       0x5
25539 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT__SHIFT                                0x6
25540 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE__SHIFT                           0xa
25541 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT__SHIFT                                          0xb
25542 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET__SHIFT                                          0xc
25543 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL__SHIFT                      0xd
25544 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL__SHIFT                     0xe
25545 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE__SHIFT             0xf
25546 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE__SHIFT                                 0x10
25547 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT                     0x12
25548 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT                     0x13
25549 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE__SHIFT                               0x14
25550 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE__SHIFT                                 0x15
25551 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE__SHIFT                                     0x16
25552 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE__SHIFT                                    0x17
25553 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE__SHIFT                                0x18
25554 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MULT__SHIFT                                 0x19
25555 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_PBB_MULT__SHIFT                             0x1b
25556 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE_MASK                                          0x00000001L
25557 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT_MASK                                   0x0000001EL
25558 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE_MASK                                         0x00000020L
25559 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT_MASK                                  0x000003C0L
25560 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE_MASK                             0x00000400L
25561 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT_MASK                                            0x00000800L
25562 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET_MASK                                            0x00001000L
25563 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL_MASK                        0x00002000L
25564 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL_MASK                       0x00004000L
25565 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE_MASK               0x00008000L
25566 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE_MASK                                   0x00030000L
25567 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK                       0x00040000L
25568 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK                       0x00080000L
25569 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE_MASK                                 0x00100000L
25570 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE_MASK                                   0x00200000L
25571 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE_MASK                                       0x00400000L
25572 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE_MASK                                      0x00800000L
25573 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE_MASK                                  0x01000000L
25574 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MULT_MASK                                   0x06000000L
25575 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_PBB_MULT_MASK                               0x18000000L
25576 //PA_SC_NGG_MODE_CNTL
25577 #define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE__SHIFT                                                      0x0
25578 #define PA_SC_NGG_MODE_CNTL__MAX_FPOVS_IN_WAVE__SHIFT                                                         0x10
25579 #define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE_MASK                                                        0x000007FFL
25580 #define PA_SC_NGG_MODE_CNTL__MAX_FPOVS_IN_WAVE_MASK                                                           0x00FF0000L
25581 //VGT_VERTEX_REUSE_BLOCK_CNTL
25582 #define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT                                                   0x0
25583 #define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK                                                     0x000000FFL
25584 //VGT_OUT_DEALLOC_CNTL
25585 #define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT                                                             0x0
25586 #define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK                                                               0x0000007FL
25587 //CB_COLOR0_BASE
25588 #define CB_COLOR0_BASE__BASE_256B__SHIFT                                                                      0x0
25589 #define CB_COLOR0_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
25590 //CB_COLOR0_PITCH
25591 #define CB_COLOR0_PITCH__TILE_MAX__SHIFT                                                                      0x0
25592 #define CB_COLOR0_PITCH__FMASK_TILE_MAX__SHIFT                                                                0x14
25593 #define CB_COLOR0_PITCH__TILE_MAX_MASK                                                                        0x000007FFL
25594 #define CB_COLOR0_PITCH__FMASK_TILE_MAX_MASK                                                                  0x7FF00000L
25595 //CB_COLOR0_SLICE
25596 #define CB_COLOR0_SLICE__TILE_MAX__SHIFT                                                                      0x0
25597 #define CB_COLOR0_SLICE__TILE_MAX_MASK                                                                        0x003FFFFFL
25598 //CB_COLOR0_VIEW
25599 #define CB_COLOR0_VIEW__SLICE_START__SHIFT                                                                    0x0
25600 #define CB_COLOR0_VIEW__SLICE_MAX__SHIFT                                                                      0xd
25601 #define CB_COLOR0_VIEW__MIP_LEVEL__SHIFT                                                                      0x1a
25602 #define CB_COLOR0_VIEW__SLICE_START_MASK                                                                      0x00001FFFL
25603 #define CB_COLOR0_VIEW__SLICE_MAX_MASK                                                                        0x03FFE000L
25604 #define CB_COLOR0_VIEW__MIP_LEVEL_MASK                                                                        0x3C000000L
25605 //CB_COLOR0_INFO
25606 #define CB_COLOR0_INFO__ENDIAN__SHIFT                                                                         0x0
25607 #define CB_COLOR0_INFO__FORMAT__SHIFT                                                                         0x2
25608 #define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT                                                                 0x7
25609 #define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
25610 #define CB_COLOR0_INFO__COMP_SWAP__SHIFT                                                                      0xb
25611 #define CB_COLOR0_INFO__FAST_CLEAR__SHIFT                                                                     0xd
25612 #define CB_COLOR0_INFO__COMPRESSION__SHIFT                                                                    0xe
25613 #define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
25614 #define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
25615 #define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
25616 #define CB_COLOR0_INFO__ROUND_MODE__SHIFT                                                                     0x12
25617 #define CB_COLOR0_INFO__CMASK_IS_LINEAR__SHIFT                                                                0x13
25618 #define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
25619 #define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
25620 #define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
25621 #define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
25622 #define CB_COLOR0_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
25623 #define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
25624 #define CB_COLOR0_INFO__ALT_TILE_MODE__SHIFT                                                                  0x1f
25625 #define CB_COLOR0_INFO__ENDIAN_MASK                                                                           0x00000003L
25626 #define CB_COLOR0_INFO__FORMAT_MASK                                                                           0x0000007CL
25627 #define CB_COLOR0_INFO__LINEAR_GENERAL_MASK                                                                   0x00000080L
25628 #define CB_COLOR0_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
25629 #define CB_COLOR0_INFO__COMP_SWAP_MASK                                                                        0x00001800L
25630 #define CB_COLOR0_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
25631 #define CB_COLOR0_INFO__COMPRESSION_MASK                                                                      0x00004000L
25632 #define CB_COLOR0_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
25633 #define CB_COLOR0_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
25634 #define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
25635 #define CB_COLOR0_INFO__ROUND_MODE_MASK                                                                       0x00040000L
25636 #define CB_COLOR0_INFO__CMASK_IS_LINEAR_MASK                                                                  0x00080000L
25637 #define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
25638 #define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
25639 #define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
25640 #define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
25641 #define CB_COLOR0_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
25642 #define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
25643 #define CB_COLOR0_INFO__ALT_TILE_MODE_MASK                                                                    0x80000000L
25644 //CB_COLOR0_ATTRIB
25645 #define CB_COLOR0_ATTRIB__TILE_MODE_INDEX__SHIFT                                                              0x0
25646 #define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT                                                        0x5
25647 #define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT                                                            0xa
25648 #define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
25649 #define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
25650 #define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
25651 #define CB_COLOR0_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT                                                    0x12
25652 #define CB_COLOR0_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT                                                0x13
25653 #define CB_COLOR0_ATTRIB__TILE_MODE_INDEX_MASK                                                                0x0000001FL
25654 #define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX_MASK                                                          0x000003E0L
25655 #define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT_MASK                                                              0x00000C00L
25656 #define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
25657 #define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
25658 #define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
25659 #define CB_COLOR0_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK                                                      0x00040000L
25660 #define CB_COLOR0_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK                                                  0x00080000L
25661 //CB_COLOR0_DCC_CONTROL
25662 #define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
25663 #define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
25664 #define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
25665 #define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
25666 #define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
25667 #define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
25668 #define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
25669 #define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
25670 #define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
25671 #define CB_COLOR0_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT                                             0x12
25672 #define CB_COLOR0_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT                                        0x13
25673 #define CB_COLOR0_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT                                                 0x14
25674 #define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
25675 #define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
25676 #define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
25677 #define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
25678 #define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
25679 #define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
25680 #define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
25681 #define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
25682 #define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
25683 #define CB_COLOR0_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK                                               0x00040000L
25684 #define CB_COLOR0_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK                                          0x00080000L
25685 #define CB_COLOR0_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK                                                   0x00100000L
25686 //CB_COLOR0_CMASK
25687 #define CB_COLOR0_CMASK__BASE_256B__SHIFT                                                                     0x0
25688 #define CB_COLOR0_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
25689 //CB_COLOR0_CMASK_SLICE
25690 #define CB_COLOR0_CMASK_SLICE__TILE_MAX__SHIFT                                                                0x0
25691 #define CB_COLOR0_CMASK_SLICE__TILE_MAX_MASK                                                                  0x00003FFFL
25692 //CB_COLOR0_FMASK
25693 #define CB_COLOR0_FMASK__BASE_256B__SHIFT                                                                     0x0
25694 #define CB_COLOR0_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
25695 //CB_COLOR0_FMASK_SLICE
25696 #define CB_COLOR0_FMASK_SLICE__TILE_MAX__SHIFT                                                                0x0
25697 #define CB_COLOR0_FMASK_SLICE__TILE_MAX_MASK                                                                  0x003FFFFFL
25698 //CB_COLOR0_CLEAR_WORD0
25699 #define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
25700 #define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
25701 //CB_COLOR0_CLEAR_WORD1
25702 #define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
25703 #define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
25704 //CB_COLOR0_DCC_BASE
25705 #define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
25706 #define CB_COLOR0_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
25707 //CB_COLOR1_BASE
25708 #define CB_COLOR1_BASE__BASE_256B__SHIFT                                                                      0x0
25709 #define CB_COLOR1_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
25710 //CB_COLOR1_PITCH
25711 #define CB_COLOR1_PITCH__TILE_MAX__SHIFT                                                                      0x0
25712 #define CB_COLOR1_PITCH__FMASK_TILE_MAX__SHIFT                                                                0x14
25713 #define CB_COLOR1_PITCH__TILE_MAX_MASK                                                                        0x000007FFL
25714 #define CB_COLOR1_PITCH__FMASK_TILE_MAX_MASK                                                                  0x7FF00000L
25715 //CB_COLOR1_SLICE
25716 #define CB_COLOR1_SLICE__TILE_MAX__SHIFT                                                                      0x0
25717 #define CB_COLOR1_SLICE__TILE_MAX_MASK                                                                        0x003FFFFFL
25718 //CB_COLOR1_VIEW
25719 #define CB_COLOR1_VIEW__SLICE_START__SHIFT                                                                    0x0
25720 #define CB_COLOR1_VIEW__SLICE_MAX__SHIFT                                                                      0xd
25721 #define CB_COLOR1_VIEW__MIP_LEVEL__SHIFT                                                                      0x1a
25722 #define CB_COLOR1_VIEW__SLICE_START_MASK                                                                      0x00001FFFL
25723 #define CB_COLOR1_VIEW__SLICE_MAX_MASK                                                                        0x03FFE000L
25724 #define CB_COLOR1_VIEW__MIP_LEVEL_MASK                                                                        0x3C000000L
25725 //CB_COLOR1_INFO
25726 #define CB_COLOR1_INFO__ENDIAN__SHIFT                                                                         0x0
25727 #define CB_COLOR1_INFO__FORMAT__SHIFT                                                                         0x2
25728 #define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT                                                                 0x7
25729 #define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
25730 #define CB_COLOR1_INFO__COMP_SWAP__SHIFT                                                                      0xb
25731 #define CB_COLOR1_INFO__FAST_CLEAR__SHIFT                                                                     0xd
25732 #define CB_COLOR1_INFO__COMPRESSION__SHIFT                                                                    0xe
25733 #define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
25734 #define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
25735 #define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
25736 #define CB_COLOR1_INFO__ROUND_MODE__SHIFT                                                                     0x12
25737 #define CB_COLOR1_INFO__CMASK_IS_LINEAR__SHIFT                                                                0x13
25738 #define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
25739 #define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
25740 #define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
25741 #define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
25742 #define CB_COLOR1_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
25743 #define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
25744 #define CB_COLOR1_INFO__ALT_TILE_MODE__SHIFT                                                                  0x1f
25745 #define CB_COLOR1_INFO__ENDIAN_MASK                                                                           0x00000003L
25746 #define CB_COLOR1_INFO__FORMAT_MASK                                                                           0x0000007CL
25747 #define CB_COLOR1_INFO__LINEAR_GENERAL_MASK                                                                   0x00000080L
25748 #define CB_COLOR1_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
25749 #define CB_COLOR1_INFO__COMP_SWAP_MASK                                                                        0x00001800L
25750 #define CB_COLOR1_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
25751 #define CB_COLOR1_INFO__COMPRESSION_MASK                                                                      0x00004000L
25752 #define CB_COLOR1_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
25753 #define CB_COLOR1_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
25754 #define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
25755 #define CB_COLOR1_INFO__ROUND_MODE_MASK                                                                       0x00040000L
25756 #define CB_COLOR1_INFO__CMASK_IS_LINEAR_MASK                                                                  0x00080000L
25757 #define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
25758 #define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
25759 #define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
25760 #define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
25761 #define CB_COLOR1_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
25762 #define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
25763 #define CB_COLOR1_INFO__ALT_TILE_MODE_MASK                                                                    0x80000000L
25764 //CB_COLOR1_ATTRIB
25765 #define CB_COLOR1_ATTRIB__TILE_MODE_INDEX__SHIFT                                                              0x0
25766 #define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT                                                        0x5
25767 #define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT                                                            0xa
25768 #define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
25769 #define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
25770 #define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
25771 #define CB_COLOR1_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT                                                    0x12
25772 #define CB_COLOR1_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT                                                0x13
25773 #define CB_COLOR1_ATTRIB__TILE_MODE_INDEX_MASK                                                                0x0000001FL
25774 #define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX_MASK                                                          0x000003E0L
25775 #define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT_MASK                                                              0x00000C00L
25776 #define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
25777 #define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
25778 #define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
25779 #define CB_COLOR1_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK                                                      0x00040000L
25780 #define CB_COLOR1_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK                                                  0x00080000L
25781 //CB_COLOR1_DCC_CONTROL
25782 #define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
25783 #define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
25784 #define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
25785 #define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
25786 #define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
25787 #define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
25788 #define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
25789 #define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
25790 #define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
25791 #define CB_COLOR1_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT                                             0x12
25792 #define CB_COLOR1_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT                                        0x13
25793 #define CB_COLOR1_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT                                                 0x14
25794 #define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
25795 #define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
25796 #define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
25797 #define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
25798 #define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
25799 #define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
25800 #define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
25801 #define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
25802 #define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
25803 #define CB_COLOR1_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK                                               0x00040000L
25804 #define CB_COLOR1_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK                                          0x00080000L
25805 #define CB_COLOR1_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK                                                   0x00100000L
25806 //CB_COLOR1_CMASK
25807 #define CB_COLOR1_CMASK__BASE_256B__SHIFT                                                                     0x0
25808 #define CB_COLOR1_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
25809 //CB_COLOR1_CMASK_SLICE
25810 #define CB_COLOR1_CMASK_SLICE__TILE_MAX__SHIFT                                                                0x0
25811 #define CB_COLOR1_CMASK_SLICE__TILE_MAX_MASK                                                                  0x00003FFFL
25812 //CB_COLOR1_FMASK
25813 #define CB_COLOR1_FMASK__BASE_256B__SHIFT                                                                     0x0
25814 #define CB_COLOR1_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
25815 //CB_COLOR1_FMASK_SLICE
25816 #define CB_COLOR1_FMASK_SLICE__TILE_MAX__SHIFT                                                                0x0
25817 #define CB_COLOR1_FMASK_SLICE__TILE_MAX_MASK                                                                  0x003FFFFFL
25818 //CB_COLOR1_CLEAR_WORD0
25819 #define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
25820 #define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
25821 //CB_COLOR1_CLEAR_WORD1
25822 #define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
25823 #define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
25824 //CB_COLOR1_DCC_BASE
25825 #define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
25826 #define CB_COLOR1_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
25827 //CB_COLOR2_BASE
25828 #define CB_COLOR2_BASE__BASE_256B__SHIFT                                                                      0x0
25829 #define CB_COLOR2_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
25830 //CB_COLOR2_PITCH
25831 #define CB_COLOR2_PITCH__TILE_MAX__SHIFT                                                                      0x0
25832 #define CB_COLOR2_PITCH__FMASK_TILE_MAX__SHIFT                                                                0x14
25833 #define CB_COLOR2_PITCH__TILE_MAX_MASK                                                                        0x000007FFL
25834 #define CB_COLOR2_PITCH__FMASK_TILE_MAX_MASK                                                                  0x7FF00000L
25835 //CB_COLOR2_SLICE
25836 #define CB_COLOR2_SLICE__TILE_MAX__SHIFT                                                                      0x0
25837 #define CB_COLOR2_SLICE__TILE_MAX_MASK                                                                        0x003FFFFFL
25838 //CB_COLOR2_VIEW
25839 #define CB_COLOR2_VIEW__SLICE_START__SHIFT                                                                    0x0
25840 #define CB_COLOR2_VIEW__SLICE_MAX__SHIFT                                                                      0xd
25841 #define CB_COLOR2_VIEW__MIP_LEVEL__SHIFT                                                                      0x1a
25842 #define CB_COLOR2_VIEW__SLICE_START_MASK                                                                      0x00001FFFL
25843 #define CB_COLOR2_VIEW__SLICE_MAX_MASK                                                                        0x03FFE000L
25844 #define CB_COLOR2_VIEW__MIP_LEVEL_MASK                                                                        0x3C000000L
25845 //CB_COLOR2_INFO
25846 #define CB_COLOR2_INFO__ENDIAN__SHIFT                                                                         0x0
25847 #define CB_COLOR2_INFO__FORMAT__SHIFT                                                                         0x2
25848 #define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT                                                                 0x7
25849 #define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
25850 #define CB_COLOR2_INFO__COMP_SWAP__SHIFT                                                                      0xb
25851 #define CB_COLOR2_INFO__FAST_CLEAR__SHIFT                                                                     0xd
25852 #define CB_COLOR2_INFO__COMPRESSION__SHIFT                                                                    0xe
25853 #define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
25854 #define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
25855 #define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
25856 #define CB_COLOR2_INFO__ROUND_MODE__SHIFT                                                                     0x12
25857 #define CB_COLOR2_INFO__CMASK_IS_LINEAR__SHIFT                                                                0x13
25858 #define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
25859 #define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
25860 #define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
25861 #define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
25862 #define CB_COLOR2_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
25863 #define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
25864 #define CB_COLOR2_INFO__ALT_TILE_MODE__SHIFT                                                                  0x1f
25865 #define CB_COLOR2_INFO__ENDIAN_MASK                                                                           0x00000003L
25866 #define CB_COLOR2_INFO__FORMAT_MASK                                                                           0x0000007CL
25867 #define CB_COLOR2_INFO__LINEAR_GENERAL_MASK                                                                   0x00000080L
25868 #define CB_COLOR2_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
25869 #define CB_COLOR2_INFO__COMP_SWAP_MASK                                                                        0x00001800L
25870 #define CB_COLOR2_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
25871 #define CB_COLOR2_INFO__COMPRESSION_MASK                                                                      0x00004000L
25872 #define CB_COLOR2_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
25873 #define CB_COLOR2_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
25874 #define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
25875 #define CB_COLOR2_INFO__ROUND_MODE_MASK                                                                       0x00040000L
25876 #define CB_COLOR2_INFO__CMASK_IS_LINEAR_MASK                                                                  0x00080000L
25877 #define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
25878 #define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
25879 #define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
25880 #define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
25881 #define CB_COLOR2_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
25882 #define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
25883 #define CB_COLOR2_INFO__ALT_TILE_MODE_MASK                                                                    0x80000000L
25884 //CB_COLOR2_ATTRIB
25885 #define CB_COLOR2_ATTRIB__TILE_MODE_INDEX__SHIFT                                                              0x0
25886 #define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT                                                        0x5
25887 #define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT                                                            0xa
25888 #define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
25889 #define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
25890 #define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
25891 #define CB_COLOR2_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT                                                    0x12
25892 #define CB_COLOR2_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT                                                0x13
25893 #define CB_COLOR2_ATTRIB__TILE_MODE_INDEX_MASK                                                                0x0000001FL
25894 #define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX_MASK                                                          0x000003E0L
25895 #define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT_MASK                                                              0x00000C00L
25896 #define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
25897 #define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
25898 #define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
25899 #define CB_COLOR2_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK                                                      0x00040000L
25900 #define CB_COLOR2_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK                                                  0x00080000L
25901 //CB_COLOR2_DCC_CONTROL
25902 #define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
25903 #define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
25904 #define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
25905 #define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
25906 #define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
25907 #define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
25908 #define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
25909 #define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
25910 #define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
25911 #define CB_COLOR2_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT                                             0x12
25912 #define CB_COLOR2_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT                                        0x13
25913 #define CB_COLOR2_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT                                                 0x14
25914 #define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
25915 #define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
25916 #define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
25917 #define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
25918 #define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
25919 #define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
25920 #define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
25921 #define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
25922 #define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
25923 #define CB_COLOR2_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK                                               0x00040000L
25924 #define CB_COLOR2_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK                                          0x00080000L
25925 #define CB_COLOR2_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK                                                   0x00100000L
25926 //CB_COLOR2_CMASK
25927 #define CB_COLOR2_CMASK__BASE_256B__SHIFT                                                                     0x0
25928 #define CB_COLOR2_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
25929 //CB_COLOR2_CMASK_SLICE
25930 #define CB_COLOR2_CMASK_SLICE__TILE_MAX__SHIFT                                                                0x0
25931 #define CB_COLOR2_CMASK_SLICE__TILE_MAX_MASK                                                                  0x00003FFFL
25932 //CB_COLOR2_FMASK
25933 #define CB_COLOR2_FMASK__BASE_256B__SHIFT                                                                     0x0
25934 #define CB_COLOR2_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
25935 //CB_COLOR2_FMASK_SLICE
25936 #define CB_COLOR2_FMASK_SLICE__TILE_MAX__SHIFT                                                                0x0
25937 #define CB_COLOR2_FMASK_SLICE__TILE_MAX_MASK                                                                  0x003FFFFFL
25938 //CB_COLOR2_CLEAR_WORD0
25939 #define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
25940 #define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
25941 //CB_COLOR2_CLEAR_WORD1
25942 #define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
25943 #define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
25944 //CB_COLOR2_DCC_BASE
25945 #define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
25946 #define CB_COLOR2_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
25947 //CB_COLOR3_BASE
25948 #define CB_COLOR3_BASE__BASE_256B__SHIFT                                                                      0x0
25949 #define CB_COLOR3_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
25950 //CB_COLOR3_PITCH
25951 #define CB_COLOR3_PITCH__TILE_MAX__SHIFT                                                                      0x0
25952 #define CB_COLOR3_PITCH__FMASK_TILE_MAX__SHIFT                                                                0x14
25953 #define CB_COLOR3_PITCH__TILE_MAX_MASK                                                                        0x000007FFL
25954 #define CB_COLOR3_PITCH__FMASK_TILE_MAX_MASK                                                                  0x7FF00000L
25955 //CB_COLOR3_SLICE
25956 #define CB_COLOR3_SLICE__TILE_MAX__SHIFT                                                                      0x0
25957 #define CB_COLOR3_SLICE__TILE_MAX_MASK                                                                        0x003FFFFFL
25958 //CB_COLOR3_VIEW
25959 #define CB_COLOR3_VIEW__SLICE_START__SHIFT                                                                    0x0
25960 #define CB_COLOR3_VIEW__SLICE_MAX__SHIFT                                                                      0xd
25961 #define CB_COLOR3_VIEW__MIP_LEVEL__SHIFT                                                                      0x1a
25962 #define CB_COLOR3_VIEW__SLICE_START_MASK                                                                      0x00001FFFL
25963 #define CB_COLOR3_VIEW__SLICE_MAX_MASK                                                                        0x03FFE000L
25964 #define CB_COLOR3_VIEW__MIP_LEVEL_MASK                                                                        0x3C000000L
25965 //CB_COLOR3_INFO
25966 #define CB_COLOR3_INFO__ENDIAN__SHIFT                                                                         0x0
25967 #define CB_COLOR3_INFO__FORMAT__SHIFT                                                                         0x2
25968 #define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT                                                                 0x7
25969 #define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
25970 #define CB_COLOR3_INFO__COMP_SWAP__SHIFT                                                                      0xb
25971 #define CB_COLOR3_INFO__FAST_CLEAR__SHIFT                                                                     0xd
25972 #define CB_COLOR3_INFO__COMPRESSION__SHIFT                                                                    0xe
25973 #define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
25974 #define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
25975 #define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
25976 #define CB_COLOR3_INFO__ROUND_MODE__SHIFT                                                                     0x12
25977 #define CB_COLOR3_INFO__CMASK_IS_LINEAR__SHIFT                                                                0x13
25978 #define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
25979 #define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
25980 #define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
25981 #define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
25982 #define CB_COLOR3_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
25983 #define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
25984 #define CB_COLOR3_INFO__ALT_TILE_MODE__SHIFT                                                                  0x1f
25985 #define CB_COLOR3_INFO__ENDIAN_MASK                                                                           0x00000003L
25986 #define CB_COLOR3_INFO__FORMAT_MASK                                                                           0x0000007CL
25987 #define CB_COLOR3_INFO__LINEAR_GENERAL_MASK                                                                   0x00000080L
25988 #define CB_COLOR3_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
25989 #define CB_COLOR3_INFO__COMP_SWAP_MASK                                                                        0x00001800L
25990 #define CB_COLOR3_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
25991 #define CB_COLOR3_INFO__COMPRESSION_MASK                                                                      0x00004000L
25992 #define CB_COLOR3_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
25993 #define CB_COLOR3_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
25994 #define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
25995 #define CB_COLOR3_INFO__ROUND_MODE_MASK                                                                       0x00040000L
25996 #define CB_COLOR3_INFO__CMASK_IS_LINEAR_MASK                                                                  0x00080000L
25997 #define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
25998 #define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
25999 #define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
26000 #define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
26001 #define CB_COLOR3_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
26002 #define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
26003 #define CB_COLOR3_INFO__ALT_TILE_MODE_MASK                                                                    0x80000000L
26004 //CB_COLOR3_ATTRIB
26005 #define CB_COLOR3_ATTRIB__TILE_MODE_INDEX__SHIFT                                                              0x0
26006 #define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT                                                        0x5
26007 #define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT                                                            0xa
26008 #define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
26009 #define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
26010 #define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
26011 #define CB_COLOR3_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT                                                    0x12
26012 #define CB_COLOR3_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT                                                0x13
26013 #define CB_COLOR3_ATTRIB__TILE_MODE_INDEX_MASK                                                                0x0000001FL
26014 #define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX_MASK                                                          0x000003E0L
26015 #define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT_MASK                                                              0x00000C00L
26016 #define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
26017 #define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
26018 #define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
26019 #define CB_COLOR3_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK                                                      0x00040000L
26020 #define CB_COLOR3_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK                                                  0x00080000L
26021 //CB_COLOR3_DCC_CONTROL
26022 #define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
26023 #define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
26024 #define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
26025 #define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
26026 #define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
26027 #define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
26028 #define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
26029 #define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
26030 #define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
26031 #define CB_COLOR3_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT                                             0x12
26032 #define CB_COLOR3_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT                                        0x13
26033 #define CB_COLOR3_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT                                                 0x14
26034 #define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
26035 #define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
26036 #define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
26037 #define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
26038 #define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
26039 #define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
26040 #define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
26041 #define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
26042 #define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
26043 #define CB_COLOR3_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK                                               0x00040000L
26044 #define CB_COLOR3_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK                                          0x00080000L
26045 #define CB_COLOR3_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK                                                   0x00100000L
26046 //CB_COLOR3_CMASK
26047 #define CB_COLOR3_CMASK__BASE_256B__SHIFT                                                                     0x0
26048 #define CB_COLOR3_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
26049 //CB_COLOR3_CMASK_SLICE
26050 #define CB_COLOR3_CMASK_SLICE__TILE_MAX__SHIFT                                                                0x0
26051 #define CB_COLOR3_CMASK_SLICE__TILE_MAX_MASK                                                                  0x00003FFFL
26052 //CB_COLOR3_FMASK
26053 #define CB_COLOR3_FMASK__BASE_256B__SHIFT                                                                     0x0
26054 #define CB_COLOR3_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
26055 //CB_COLOR3_FMASK_SLICE
26056 #define CB_COLOR3_FMASK_SLICE__TILE_MAX__SHIFT                                                                0x0
26057 #define CB_COLOR3_FMASK_SLICE__TILE_MAX_MASK                                                                  0x003FFFFFL
26058 //CB_COLOR3_CLEAR_WORD0
26059 #define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
26060 #define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
26061 //CB_COLOR3_CLEAR_WORD1
26062 #define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
26063 #define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
26064 //CB_COLOR3_DCC_BASE
26065 #define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
26066 #define CB_COLOR3_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
26067 //CB_COLOR4_BASE
26068 #define CB_COLOR4_BASE__BASE_256B__SHIFT                                                                      0x0
26069 #define CB_COLOR4_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
26070 //CB_COLOR4_PITCH
26071 #define CB_COLOR4_PITCH__TILE_MAX__SHIFT                                                                      0x0
26072 #define CB_COLOR4_PITCH__FMASK_TILE_MAX__SHIFT                                                                0x14
26073 #define CB_COLOR4_PITCH__TILE_MAX_MASK                                                                        0x000007FFL
26074 #define CB_COLOR4_PITCH__FMASK_TILE_MAX_MASK                                                                  0x7FF00000L
26075 //CB_COLOR4_SLICE
26076 #define CB_COLOR4_SLICE__TILE_MAX__SHIFT                                                                      0x0
26077 #define CB_COLOR4_SLICE__TILE_MAX_MASK                                                                        0x003FFFFFL
26078 //CB_COLOR4_VIEW
26079 #define CB_COLOR4_VIEW__SLICE_START__SHIFT                                                                    0x0
26080 #define CB_COLOR4_VIEW__SLICE_MAX__SHIFT                                                                      0xd
26081 #define CB_COLOR4_VIEW__MIP_LEVEL__SHIFT                                                                      0x1a
26082 #define CB_COLOR4_VIEW__SLICE_START_MASK                                                                      0x00001FFFL
26083 #define CB_COLOR4_VIEW__SLICE_MAX_MASK                                                                        0x03FFE000L
26084 #define CB_COLOR4_VIEW__MIP_LEVEL_MASK                                                                        0x3C000000L
26085 //CB_COLOR4_INFO
26086 #define CB_COLOR4_INFO__ENDIAN__SHIFT                                                                         0x0
26087 #define CB_COLOR4_INFO__FORMAT__SHIFT                                                                         0x2
26088 #define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT                                                                 0x7
26089 #define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
26090 #define CB_COLOR4_INFO__COMP_SWAP__SHIFT                                                                      0xb
26091 #define CB_COLOR4_INFO__FAST_CLEAR__SHIFT                                                                     0xd
26092 #define CB_COLOR4_INFO__COMPRESSION__SHIFT                                                                    0xe
26093 #define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
26094 #define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
26095 #define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
26096 #define CB_COLOR4_INFO__ROUND_MODE__SHIFT                                                                     0x12
26097 #define CB_COLOR4_INFO__CMASK_IS_LINEAR__SHIFT                                                                0x13
26098 #define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
26099 #define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
26100 #define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
26101 #define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
26102 #define CB_COLOR4_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
26103 #define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
26104 #define CB_COLOR4_INFO__ALT_TILE_MODE__SHIFT                                                                  0x1f
26105 #define CB_COLOR4_INFO__ENDIAN_MASK                                                                           0x00000003L
26106 #define CB_COLOR4_INFO__FORMAT_MASK                                                                           0x0000007CL
26107 #define CB_COLOR4_INFO__LINEAR_GENERAL_MASK                                                                   0x00000080L
26108 #define CB_COLOR4_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
26109 #define CB_COLOR4_INFO__COMP_SWAP_MASK                                                                        0x00001800L
26110 #define CB_COLOR4_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
26111 #define CB_COLOR4_INFO__COMPRESSION_MASK                                                                      0x00004000L
26112 #define CB_COLOR4_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
26113 #define CB_COLOR4_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
26114 #define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
26115 #define CB_COLOR4_INFO__ROUND_MODE_MASK                                                                       0x00040000L
26116 #define CB_COLOR4_INFO__CMASK_IS_LINEAR_MASK                                                                  0x00080000L
26117 #define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
26118 #define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
26119 #define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
26120 #define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
26121 #define CB_COLOR4_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
26122 #define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
26123 #define CB_COLOR4_INFO__ALT_TILE_MODE_MASK                                                                    0x80000000L
26124 //CB_COLOR4_ATTRIB
26125 #define CB_COLOR4_ATTRIB__TILE_MODE_INDEX__SHIFT                                                              0x0
26126 #define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT                                                        0x5
26127 #define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT                                                            0xa
26128 #define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
26129 #define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
26130 #define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
26131 #define CB_COLOR4_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT                                                    0x12
26132 #define CB_COLOR4_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT                                                0x13
26133 #define CB_COLOR4_ATTRIB__TILE_MODE_INDEX_MASK                                                                0x0000001FL
26134 #define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX_MASK                                                          0x000003E0L
26135 #define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT_MASK                                                              0x00000C00L
26136 #define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
26137 #define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
26138 #define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
26139 #define CB_COLOR4_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK                                                      0x00040000L
26140 #define CB_COLOR4_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK                                                  0x00080000L
26141 //CB_COLOR4_DCC_CONTROL
26142 #define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
26143 #define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
26144 #define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
26145 #define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
26146 #define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
26147 #define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
26148 #define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
26149 #define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
26150 #define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
26151 #define CB_COLOR4_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT                                             0x12
26152 #define CB_COLOR4_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT                                        0x13
26153 #define CB_COLOR4_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT                                                 0x14
26154 #define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
26155 #define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
26156 #define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
26157 #define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
26158 #define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
26159 #define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
26160 #define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
26161 #define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
26162 #define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
26163 #define CB_COLOR4_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK                                               0x00040000L
26164 #define CB_COLOR4_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK                                          0x00080000L
26165 #define CB_COLOR4_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK                                                   0x00100000L
26166 //CB_COLOR4_CMASK
26167 #define CB_COLOR4_CMASK__BASE_256B__SHIFT                                                                     0x0
26168 #define CB_COLOR4_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
26169 //CB_COLOR4_CMASK_SLICE
26170 #define CB_COLOR4_CMASK_SLICE__TILE_MAX__SHIFT                                                                0x0
26171 #define CB_COLOR4_CMASK_SLICE__TILE_MAX_MASK                                                                  0x00003FFFL
26172 //CB_COLOR4_FMASK
26173 #define CB_COLOR4_FMASK__BASE_256B__SHIFT                                                                     0x0
26174 #define CB_COLOR4_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
26175 //CB_COLOR4_FMASK_SLICE
26176 #define CB_COLOR4_FMASK_SLICE__TILE_MAX__SHIFT                                                                0x0
26177 #define CB_COLOR4_FMASK_SLICE__TILE_MAX_MASK                                                                  0x003FFFFFL
26178 //CB_COLOR4_CLEAR_WORD0
26179 #define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
26180 #define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
26181 //CB_COLOR4_CLEAR_WORD1
26182 #define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
26183 #define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
26184 //CB_COLOR4_DCC_BASE
26185 #define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
26186 #define CB_COLOR4_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
26187 //CB_COLOR5_BASE
26188 #define CB_COLOR5_BASE__BASE_256B__SHIFT                                                                      0x0
26189 #define CB_COLOR5_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
26190 //CB_COLOR5_PITCH
26191 #define CB_COLOR5_PITCH__TILE_MAX__SHIFT                                                                      0x0
26192 #define CB_COLOR5_PITCH__FMASK_TILE_MAX__SHIFT                                                                0x14
26193 #define CB_COLOR5_PITCH__TILE_MAX_MASK                                                                        0x000007FFL
26194 #define CB_COLOR5_PITCH__FMASK_TILE_MAX_MASK                                                                  0x7FF00000L
26195 //CB_COLOR5_SLICE
26196 #define CB_COLOR5_SLICE__TILE_MAX__SHIFT                                                                      0x0
26197 #define CB_COLOR5_SLICE__TILE_MAX_MASK                                                                        0x003FFFFFL
26198 //CB_COLOR5_VIEW
26199 #define CB_COLOR5_VIEW__SLICE_START__SHIFT                                                                    0x0
26200 #define CB_COLOR5_VIEW__SLICE_MAX__SHIFT                                                                      0xd
26201 #define CB_COLOR5_VIEW__MIP_LEVEL__SHIFT                                                                      0x1a
26202 #define CB_COLOR5_VIEW__SLICE_START_MASK                                                                      0x00001FFFL
26203 #define CB_COLOR5_VIEW__SLICE_MAX_MASK                                                                        0x03FFE000L
26204 #define CB_COLOR5_VIEW__MIP_LEVEL_MASK                                                                        0x3C000000L
26205 //CB_COLOR5_INFO
26206 #define CB_COLOR5_INFO__ENDIAN__SHIFT                                                                         0x0
26207 #define CB_COLOR5_INFO__FORMAT__SHIFT                                                                         0x2
26208 #define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT                                                                 0x7
26209 #define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
26210 #define CB_COLOR5_INFO__COMP_SWAP__SHIFT                                                                      0xb
26211 #define CB_COLOR5_INFO__FAST_CLEAR__SHIFT                                                                     0xd
26212 #define CB_COLOR5_INFO__COMPRESSION__SHIFT                                                                    0xe
26213 #define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
26214 #define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
26215 #define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
26216 #define CB_COLOR5_INFO__ROUND_MODE__SHIFT                                                                     0x12
26217 #define CB_COLOR5_INFO__CMASK_IS_LINEAR__SHIFT                                                                0x13
26218 #define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
26219 #define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
26220 #define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
26221 #define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
26222 #define CB_COLOR5_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
26223 #define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
26224 #define CB_COLOR5_INFO__ALT_TILE_MODE__SHIFT                                                                  0x1f
26225 #define CB_COLOR5_INFO__ENDIAN_MASK                                                                           0x00000003L
26226 #define CB_COLOR5_INFO__FORMAT_MASK                                                                           0x0000007CL
26227 #define CB_COLOR5_INFO__LINEAR_GENERAL_MASK                                                                   0x00000080L
26228 #define CB_COLOR5_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
26229 #define CB_COLOR5_INFO__COMP_SWAP_MASK                                                                        0x00001800L
26230 #define CB_COLOR5_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
26231 #define CB_COLOR5_INFO__COMPRESSION_MASK                                                                      0x00004000L
26232 #define CB_COLOR5_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
26233 #define CB_COLOR5_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
26234 #define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
26235 #define CB_COLOR5_INFO__ROUND_MODE_MASK                                                                       0x00040000L
26236 #define CB_COLOR5_INFO__CMASK_IS_LINEAR_MASK                                                                  0x00080000L
26237 #define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
26238 #define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
26239 #define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
26240 #define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
26241 #define CB_COLOR5_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
26242 #define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
26243 #define CB_COLOR5_INFO__ALT_TILE_MODE_MASK                                                                    0x80000000L
26244 //CB_COLOR5_ATTRIB
26245 #define CB_COLOR5_ATTRIB__TILE_MODE_INDEX__SHIFT                                                              0x0
26246 #define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT                                                        0x5
26247 #define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT                                                            0xa
26248 #define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
26249 #define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
26250 #define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
26251 #define CB_COLOR5_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT                                                    0x12
26252 #define CB_COLOR5_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT                                                0x13
26253 #define CB_COLOR5_ATTRIB__TILE_MODE_INDEX_MASK                                                                0x0000001FL
26254 #define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX_MASK                                                          0x000003E0L
26255 #define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT_MASK                                                              0x00000C00L
26256 #define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
26257 #define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
26258 #define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
26259 #define CB_COLOR5_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK                                                      0x00040000L
26260 #define CB_COLOR5_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK                                                  0x00080000L
26261 //CB_COLOR5_DCC_CONTROL
26262 #define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
26263 #define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
26264 #define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
26265 #define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
26266 #define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
26267 #define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
26268 #define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
26269 #define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
26270 #define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
26271 #define CB_COLOR5_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT                                             0x12
26272 #define CB_COLOR5_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT                                        0x13
26273 #define CB_COLOR5_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT                                                 0x14
26274 #define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
26275 #define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
26276 #define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
26277 #define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
26278 #define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
26279 #define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
26280 #define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
26281 #define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
26282 #define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
26283 #define CB_COLOR5_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK                                               0x00040000L
26284 #define CB_COLOR5_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK                                          0x00080000L
26285 #define CB_COLOR5_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK                                                   0x00100000L
26286 //CB_COLOR5_CMASK
26287 #define CB_COLOR5_CMASK__BASE_256B__SHIFT                                                                     0x0
26288 #define CB_COLOR5_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
26289 //CB_COLOR5_CMASK_SLICE
26290 #define CB_COLOR5_CMASK_SLICE__TILE_MAX__SHIFT                                                                0x0
26291 #define CB_COLOR5_CMASK_SLICE__TILE_MAX_MASK                                                                  0x00003FFFL
26292 //CB_COLOR5_FMASK
26293 #define CB_COLOR5_FMASK__BASE_256B__SHIFT                                                                     0x0
26294 #define CB_COLOR5_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
26295 //CB_COLOR5_FMASK_SLICE
26296 #define CB_COLOR5_FMASK_SLICE__TILE_MAX__SHIFT                                                                0x0
26297 #define CB_COLOR5_FMASK_SLICE__TILE_MAX_MASK                                                                  0x003FFFFFL
26298 //CB_COLOR5_CLEAR_WORD0
26299 #define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
26300 #define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
26301 //CB_COLOR5_CLEAR_WORD1
26302 #define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
26303 #define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
26304 //CB_COLOR5_DCC_BASE
26305 #define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
26306 #define CB_COLOR5_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
26307 //CB_COLOR6_BASE
26308 #define CB_COLOR6_BASE__BASE_256B__SHIFT                                                                      0x0
26309 #define CB_COLOR6_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
26310 //CB_COLOR6_PITCH
26311 #define CB_COLOR6_PITCH__TILE_MAX__SHIFT                                                                      0x0
26312 #define CB_COLOR6_PITCH__FMASK_TILE_MAX__SHIFT                                                                0x14
26313 #define CB_COLOR6_PITCH__TILE_MAX_MASK                                                                        0x000007FFL
26314 #define CB_COLOR6_PITCH__FMASK_TILE_MAX_MASK                                                                  0x7FF00000L
26315 //CB_COLOR6_SLICE
26316 #define CB_COLOR6_SLICE__TILE_MAX__SHIFT                                                                      0x0
26317 #define CB_COLOR6_SLICE__TILE_MAX_MASK                                                                        0x003FFFFFL
26318 //CB_COLOR6_VIEW
26319 #define CB_COLOR6_VIEW__SLICE_START__SHIFT                                                                    0x0
26320 #define CB_COLOR6_VIEW__SLICE_MAX__SHIFT                                                                      0xd
26321 #define CB_COLOR6_VIEW__MIP_LEVEL__SHIFT                                                                      0x1a
26322 #define CB_COLOR6_VIEW__SLICE_START_MASK                                                                      0x00001FFFL
26323 #define CB_COLOR6_VIEW__SLICE_MAX_MASK                                                                        0x03FFE000L
26324 #define CB_COLOR6_VIEW__MIP_LEVEL_MASK                                                                        0x3C000000L
26325 //CB_COLOR6_INFO
26326 #define CB_COLOR6_INFO__ENDIAN__SHIFT                                                                         0x0
26327 #define CB_COLOR6_INFO__FORMAT__SHIFT                                                                         0x2
26328 #define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT                                                                 0x7
26329 #define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
26330 #define CB_COLOR6_INFO__COMP_SWAP__SHIFT                                                                      0xb
26331 #define CB_COLOR6_INFO__FAST_CLEAR__SHIFT                                                                     0xd
26332 #define CB_COLOR6_INFO__COMPRESSION__SHIFT                                                                    0xe
26333 #define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
26334 #define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
26335 #define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
26336 #define CB_COLOR6_INFO__ROUND_MODE__SHIFT                                                                     0x12
26337 #define CB_COLOR6_INFO__CMASK_IS_LINEAR__SHIFT                                                                0x13
26338 #define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
26339 #define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
26340 #define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
26341 #define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
26342 #define CB_COLOR6_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
26343 #define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
26344 #define CB_COLOR6_INFO__ALT_TILE_MODE__SHIFT                                                                  0x1f
26345 #define CB_COLOR6_INFO__ENDIAN_MASK                                                                           0x00000003L
26346 #define CB_COLOR6_INFO__FORMAT_MASK                                                                           0x0000007CL
26347 #define CB_COLOR6_INFO__LINEAR_GENERAL_MASK                                                                   0x00000080L
26348 #define CB_COLOR6_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
26349 #define CB_COLOR6_INFO__COMP_SWAP_MASK                                                                        0x00001800L
26350 #define CB_COLOR6_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
26351 #define CB_COLOR6_INFO__COMPRESSION_MASK                                                                      0x00004000L
26352 #define CB_COLOR6_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
26353 #define CB_COLOR6_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
26354 #define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
26355 #define CB_COLOR6_INFO__ROUND_MODE_MASK                                                                       0x00040000L
26356 #define CB_COLOR6_INFO__CMASK_IS_LINEAR_MASK                                                                  0x00080000L
26357 #define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
26358 #define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
26359 #define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
26360 #define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
26361 #define CB_COLOR6_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
26362 #define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
26363 #define CB_COLOR6_INFO__ALT_TILE_MODE_MASK                                                                    0x80000000L
26364 //CB_COLOR6_ATTRIB
26365 #define CB_COLOR6_ATTRIB__TILE_MODE_INDEX__SHIFT                                                              0x0
26366 #define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT                                                        0x5
26367 #define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT                                                            0xa
26368 #define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
26369 #define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
26370 #define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
26371 #define CB_COLOR6_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT                                                    0x12
26372 #define CB_COLOR6_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT                                                0x13
26373 #define CB_COLOR6_ATTRIB__TILE_MODE_INDEX_MASK                                                                0x0000001FL
26374 #define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX_MASK                                                          0x000003E0L
26375 #define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT_MASK                                                              0x00000C00L
26376 #define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
26377 #define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
26378 #define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
26379 #define CB_COLOR6_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK                                                      0x00040000L
26380 #define CB_COLOR6_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK                                                  0x00080000L
26381 //CB_COLOR6_DCC_CONTROL
26382 #define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
26383 #define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
26384 #define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
26385 #define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
26386 #define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
26387 #define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
26388 #define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
26389 #define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
26390 #define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
26391 #define CB_COLOR6_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT                                             0x12
26392 #define CB_COLOR6_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT                                        0x13
26393 #define CB_COLOR6_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT                                                 0x14
26394 #define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
26395 #define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
26396 #define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
26397 #define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
26398 #define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
26399 #define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
26400 #define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
26401 #define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
26402 #define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
26403 #define CB_COLOR6_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK                                               0x00040000L
26404 #define CB_COLOR6_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK                                          0x00080000L
26405 #define CB_COLOR6_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK                                                   0x00100000L
26406 //CB_COLOR6_CMASK
26407 #define CB_COLOR6_CMASK__BASE_256B__SHIFT                                                                     0x0
26408 #define CB_COLOR6_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
26409 //CB_COLOR6_CMASK_SLICE
26410 #define CB_COLOR6_CMASK_SLICE__TILE_MAX__SHIFT                                                                0x0
26411 #define CB_COLOR6_CMASK_SLICE__TILE_MAX_MASK                                                                  0x00003FFFL
26412 //CB_COLOR6_FMASK
26413 #define CB_COLOR6_FMASK__BASE_256B__SHIFT                                                                     0x0
26414 #define CB_COLOR6_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
26415 //CB_COLOR6_FMASK_SLICE
26416 #define CB_COLOR6_FMASK_SLICE__TILE_MAX__SHIFT                                                                0x0
26417 #define CB_COLOR6_FMASK_SLICE__TILE_MAX_MASK                                                                  0x003FFFFFL
26418 //CB_COLOR6_CLEAR_WORD0
26419 #define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
26420 #define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
26421 //CB_COLOR6_CLEAR_WORD1
26422 #define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
26423 #define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
26424 //CB_COLOR6_DCC_BASE
26425 #define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
26426 #define CB_COLOR6_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
26427 //CB_COLOR7_BASE
26428 #define CB_COLOR7_BASE__BASE_256B__SHIFT                                                                      0x0
26429 #define CB_COLOR7_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
26430 //CB_COLOR7_PITCH
26431 #define CB_COLOR7_PITCH__TILE_MAX__SHIFT                                                                      0x0
26432 #define CB_COLOR7_PITCH__FMASK_TILE_MAX__SHIFT                                                                0x14
26433 #define CB_COLOR7_PITCH__TILE_MAX_MASK                                                                        0x000007FFL
26434 #define CB_COLOR7_PITCH__FMASK_TILE_MAX_MASK                                                                  0x7FF00000L
26435 //CB_COLOR7_SLICE
26436 #define CB_COLOR7_SLICE__TILE_MAX__SHIFT                                                                      0x0
26437 #define CB_COLOR7_SLICE__TILE_MAX_MASK                                                                        0x003FFFFFL
26438 //CB_COLOR7_VIEW
26439 #define CB_COLOR7_VIEW__SLICE_START__SHIFT                                                                    0x0
26440 #define CB_COLOR7_VIEW__SLICE_MAX__SHIFT                                                                      0xd
26441 #define CB_COLOR7_VIEW__MIP_LEVEL__SHIFT                                                                      0x1a
26442 #define CB_COLOR7_VIEW__SLICE_START_MASK                                                                      0x00001FFFL
26443 #define CB_COLOR7_VIEW__SLICE_MAX_MASK                                                                        0x03FFE000L
26444 #define CB_COLOR7_VIEW__MIP_LEVEL_MASK                                                                        0x3C000000L
26445 //CB_COLOR7_INFO
26446 #define CB_COLOR7_INFO__ENDIAN__SHIFT                                                                         0x0
26447 #define CB_COLOR7_INFO__FORMAT__SHIFT                                                                         0x2
26448 #define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT                                                                 0x7
26449 #define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
26450 #define CB_COLOR7_INFO__COMP_SWAP__SHIFT                                                                      0xb
26451 #define CB_COLOR7_INFO__FAST_CLEAR__SHIFT                                                                     0xd
26452 #define CB_COLOR7_INFO__COMPRESSION__SHIFT                                                                    0xe
26453 #define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
26454 #define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
26455 #define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
26456 #define CB_COLOR7_INFO__ROUND_MODE__SHIFT                                                                     0x12
26457 #define CB_COLOR7_INFO__CMASK_IS_LINEAR__SHIFT                                                                0x13
26458 #define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
26459 #define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
26460 #define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
26461 #define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
26462 #define CB_COLOR7_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
26463 #define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
26464 #define CB_COLOR7_INFO__ALT_TILE_MODE__SHIFT                                                                  0x1f
26465 #define CB_COLOR7_INFO__ENDIAN_MASK                                                                           0x00000003L
26466 #define CB_COLOR7_INFO__FORMAT_MASK                                                                           0x0000007CL
26467 #define CB_COLOR7_INFO__LINEAR_GENERAL_MASK                                                                   0x00000080L
26468 #define CB_COLOR7_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
26469 #define CB_COLOR7_INFO__COMP_SWAP_MASK                                                                        0x00001800L
26470 #define CB_COLOR7_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
26471 #define CB_COLOR7_INFO__COMPRESSION_MASK                                                                      0x00004000L
26472 #define CB_COLOR7_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
26473 #define CB_COLOR7_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
26474 #define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
26475 #define CB_COLOR7_INFO__ROUND_MODE_MASK                                                                       0x00040000L
26476 #define CB_COLOR7_INFO__CMASK_IS_LINEAR_MASK                                                                  0x00080000L
26477 #define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
26478 #define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
26479 #define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
26480 #define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
26481 #define CB_COLOR7_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
26482 #define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
26483 #define CB_COLOR7_INFO__ALT_TILE_MODE_MASK                                                                    0x80000000L
26484 //CB_COLOR7_ATTRIB
26485 #define CB_COLOR7_ATTRIB__TILE_MODE_INDEX__SHIFT                                                              0x0
26486 #define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT                                                        0x5
26487 #define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT                                                            0xa
26488 #define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
26489 #define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
26490 #define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
26491 #define CB_COLOR7_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT                                                    0x12
26492 #define CB_COLOR7_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT                                                0x13
26493 #define CB_COLOR7_ATTRIB__TILE_MODE_INDEX_MASK                                                                0x0000001FL
26494 #define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX_MASK                                                          0x000003E0L
26495 #define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT_MASK                                                              0x00000C00L
26496 #define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
26497 #define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
26498 #define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
26499 #define CB_COLOR7_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK                                                      0x00040000L
26500 #define CB_COLOR7_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK                                                  0x00080000L
26501 //CB_COLOR7_DCC_CONTROL
26502 #define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
26503 #define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
26504 #define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
26505 #define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
26506 #define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
26507 #define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
26508 #define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
26509 #define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
26510 #define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
26511 #define CB_COLOR7_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT                                             0x12
26512 #define CB_COLOR7_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT                                        0x13
26513 #define CB_COLOR7_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT                                                 0x14
26514 #define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
26515 #define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
26516 #define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
26517 #define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
26518 #define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
26519 #define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
26520 #define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
26521 #define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
26522 #define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
26523 #define CB_COLOR7_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK                                               0x00040000L
26524 #define CB_COLOR7_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK                                          0x00080000L
26525 #define CB_COLOR7_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK                                                   0x00100000L
26526 //CB_COLOR7_CMASK
26527 #define CB_COLOR7_CMASK__BASE_256B__SHIFT                                                                     0x0
26528 #define CB_COLOR7_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
26529 //CB_COLOR7_CMASK_SLICE
26530 #define CB_COLOR7_CMASK_SLICE__TILE_MAX__SHIFT                                                                0x0
26531 #define CB_COLOR7_CMASK_SLICE__TILE_MAX_MASK                                                                  0x00003FFFL
26532 //CB_COLOR7_FMASK
26533 #define CB_COLOR7_FMASK__BASE_256B__SHIFT                                                                     0x0
26534 #define CB_COLOR7_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
26535 //CB_COLOR7_FMASK_SLICE
26536 #define CB_COLOR7_FMASK_SLICE__TILE_MAX__SHIFT                                                                0x0
26537 #define CB_COLOR7_FMASK_SLICE__TILE_MAX_MASK                                                                  0x003FFFFFL
26538 //CB_COLOR7_CLEAR_WORD0
26539 #define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
26540 #define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
26541 //CB_COLOR7_CLEAR_WORD1
26542 #define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
26543 #define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
26544 //CB_COLOR7_DCC_BASE
26545 #define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
26546 #define CB_COLOR7_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
26547 //CB_COLOR0_BASE_EXT
26548 #define CB_COLOR0_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
26549 #define CB_COLOR0_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
26550 //CB_COLOR1_BASE_EXT
26551 #define CB_COLOR1_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
26552 #define CB_COLOR1_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
26553 //CB_COLOR2_BASE_EXT
26554 #define CB_COLOR2_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
26555 #define CB_COLOR2_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
26556 //CB_COLOR3_BASE_EXT
26557 #define CB_COLOR3_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
26558 #define CB_COLOR3_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
26559 //CB_COLOR4_BASE_EXT
26560 #define CB_COLOR4_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
26561 #define CB_COLOR4_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
26562 //CB_COLOR5_BASE_EXT
26563 #define CB_COLOR5_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
26564 #define CB_COLOR5_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
26565 //CB_COLOR6_BASE_EXT
26566 #define CB_COLOR6_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
26567 #define CB_COLOR6_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
26568 //CB_COLOR7_BASE_EXT
26569 #define CB_COLOR7_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
26570 #define CB_COLOR7_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
26571 //CB_COLOR0_CMASK_BASE_EXT
26572 #define CB_COLOR0_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
26573 #define CB_COLOR0_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
26574 //CB_COLOR1_CMASK_BASE_EXT
26575 #define CB_COLOR1_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
26576 #define CB_COLOR1_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
26577 //CB_COLOR2_CMASK_BASE_EXT
26578 #define CB_COLOR2_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
26579 #define CB_COLOR2_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
26580 //CB_COLOR3_CMASK_BASE_EXT
26581 #define CB_COLOR3_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
26582 #define CB_COLOR3_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
26583 //CB_COLOR4_CMASK_BASE_EXT
26584 #define CB_COLOR4_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
26585 #define CB_COLOR4_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
26586 //CB_COLOR5_CMASK_BASE_EXT
26587 #define CB_COLOR5_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
26588 #define CB_COLOR5_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
26589 //CB_COLOR6_CMASK_BASE_EXT
26590 #define CB_COLOR6_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
26591 #define CB_COLOR6_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
26592 //CB_COLOR7_CMASK_BASE_EXT
26593 #define CB_COLOR7_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
26594 #define CB_COLOR7_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
26595 //CB_COLOR0_FMASK_BASE_EXT
26596 #define CB_COLOR0_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
26597 #define CB_COLOR0_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
26598 //CB_COLOR1_FMASK_BASE_EXT
26599 #define CB_COLOR1_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
26600 #define CB_COLOR1_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
26601 //CB_COLOR2_FMASK_BASE_EXT
26602 #define CB_COLOR2_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
26603 #define CB_COLOR2_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
26604 //CB_COLOR3_FMASK_BASE_EXT
26605 #define CB_COLOR3_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
26606 #define CB_COLOR3_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
26607 //CB_COLOR4_FMASK_BASE_EXT
26608 #define CB_COLOR4_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
26609 #define CB_COLOR4_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
26610 //CB_COLOR5_FMASK_BASE_EXT
26611 #define CB_COLOR5_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
26612 #define CB_COLOR5_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
26613 //CB_COLOR6_FMASK_BASE_EXT
26614 #define CB_COLOR6_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
26615 #define CB_COLOR6_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
26616 //CB_COLOR7_FMASK_BASE_EXT
26617 #define CB_COLOR7_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
26618 #define CB_COLOR7_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
26619 //CB_COLOR0_DCC_BASE_EXT
26620 #define CB_COLOR0_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
26621 #define CB_COLOR0_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
26622 //CB_COLOR1_DCC_BASE_EXT
26623 #define CB_COLOR1_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
26624 #define CB_COLOR1_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
26625 //CB_COLOR2_DCC_BASE_EXT
26626 #define CB_COLOR2_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
26627 #define CB_COLOR2_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
26628 //CB_COLOR3_DCC_BASE_EXT
26629 #define CB_COLOR3_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
26630 #define CB_COLOR3_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
26631 //CB_COLOR4_DCC_BASE_EXT
26632 #define CB_COLOR4_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
26633 #define CB_COLOR4_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
26634 //CB_COLOR5_DCC_BASE_EXT
26635 #define CB_COLOR5_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
26636 #define CB_COLOR5_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
26637 //CB_COLOR6_DCC_BASE_EXT
26638 #define CB_COLOR6_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
26639 #define CB_COLOR6_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
26640 //CB_COLOR7_DCC_BASE_EXT
26641 #define CB_COLOR7_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
26642 #define CB_COLOR7_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
26643 //CB_COLOR0_ATTRIB2
26644 #define CB_COLOR0_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
26645 #define CB_COLOR0_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
26646 #define CB_COLOR0_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
26647 #define CB_COLOR0_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
26648 #define CB_COLOR0_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
26649 #define CB_COLOR0_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
26650 //CB_COLOR1_ATTRIB2
26651 #define CB_COLOR1_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
26652 #define CB_COLOR1_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
26653 #define CB_COLOR1_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
26654 #define CB_COLOR1_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
26655 #define CB_COLOR1_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
26656 #define CB_COLOR1_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
26657 //CB_COLOR2_ATTRIB2
26658 #define CB_COLOR2_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
26659 #define CB_COLOR2_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
26660 #define CB_COLOR2_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
26661 #define CB_COLOR2_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
26662 #define CB_COLOR2_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
26663 #define CB_COLOR2_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
26664 //CB_COLOR3_ATTRIB2
26665 #define CB_COLOR3_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
26666 #define CB_COLOR3_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
26667 #define CB_COLOR3_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
26668 #define CB_COLOR3_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
26669 #define CB_COLOR3_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
26670 #define CB_COLOR3_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
26671 //CB_COLOR4_ATTRIB2
26672 #define CB_COLOR4_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
26673 #define CB_COLOR4_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
26674 #define CB_COLOR4_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
26675 #define CB_COLOR4_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
26676 #define CB_COLOR4_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
26677 #define CB_COLOR4_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
26678 //CB_COLOR5_ATTRIB2
26679 #define CB_COLOR5_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
26680 #define CB_COLOR5_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
26681 #define CB_COLOR5_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
26682 #define CB_COLOR5_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
26683 #define CB_COLOR5_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
26684 #define CB_COLOR5_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
26685 //CB_COLOR6_ATTRIB2
26686 #define CB_COLOR6_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
26687 #define CB_COLOR6_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
26688 #define CB_COLOR6_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
26689 #define CB_COLOR6_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
26690 #define CB_COLOR6_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
26691 #define CB_COLOR6_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
26692 //CB_COLOR7_ATTRIB2
26693 #define CB_COLOR7_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
26694 #define CB_COLOR7_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
26695 #define CB_COLOR7_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
26696 #define CB_COLOR7_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
26697 #define CB_COLOR7_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
26698 #define CB_COLOR7_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
26699 //CB_COLOR0_ATTRIB3
26700 #define CB_COLOR0_ATTRIB3__MIP0_DEPTH__SHIFT                                                                  0x0
26701 #define CB_COLOR0_ATTRIB3__META_LINEAR__SHIFT                                                                 0xd
26702 #define CB_COLOR0_ATTRIB3__COLOR_SW_MODE__SHIFT                                                               0xe
26703 #define CB_COLOR0_ATTRIB3__FMASK_SW_MODE__SHIFT                                                               0x13
26704 #define CB_COLOR0_ATTRIB3__RESOURCE_TYPE__SHIFT                                                               0x18
26705 #define CB_COLOR0_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT                                                          0x1a
26706 #define CB_COLOR0_ATTRIB3__RESOURCE_LEVEL__SHIFT                                                              0x1b
26707 #define CB_COLOR0_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT                                                            0x1e
26708 #define CB_COLOR0_ATTRIB3__MIP0_DEPTH_MASK                                                                    0x00001FFFL
26709 #define CB_COLOR0_ATTRIB3__META_LINEAR_MASK                                                                   0x00002000L
26710 #define CB_COLOR0_ATTRIB3__COLOR_SW_MODE_MASK                                                                 0x0007C000L
26711 #define CB_COLOR0_ATTRIB3__FMASK_SW_MODE_MASK                                                                 0x00F80000L
26712 #define CB_COLOR0_ATTRIB3__RESOURCE_TYPE_MASK                                                                 0x03000000L
26713 #define CB_COLOR0_ATTRIB3__CMASK_PIPE_ALIGNED_MASK                                                            0x04000000L
26714 #define CB_COLOR0_ATTRIB3__RESOURCE_LEVEL_MASK                                                                0x38000000L
26715 #define CB_COLOR0_ATTRIB3__DCC_PIPE_ALIGNED_MASK                                                              0x40000000L
26716 //CB_COLOR1_ATTRIB3
26717 #define CB_COLOR1_ATTRIB3__MIP0_DEPTH__SHIFT                                                                  0x0
26718 #define CB_COLOR1_ATTRIB3__META_LINEAR__SHIFT                                                                 0xd
26719 #define CB_COLOR1_ATTRIB3__COLOR_SW_MODE__SHIFT                                                               0xe
26720 #define CB_COLOR1_ATTRIB3__FMASK_SW_MODE__SHIFT                                                               0x13
26721 #define CB_COLOR1_ATTRIB3__RESOURCE_TYPE__SHIFT                                                               0x18
26722 #define CB_COLOR1_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT                                                          0x1a
26723 #define CB_COLOR1_ATTRIB3__RESOURCE_LEVEL__SHIFT                                                              0x1b
26724 #define CB_COLOR1_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT                                                            0x1e
26725 #define CB_COLOR1_ATTRIB3__MIP0_DEPTH_MASK                                                                    0x00001FFFL
26726 #define CB_COLOR1_ATTRIB3__META_LINEAR_MASK                                                                   0x00002000L
26727 #define CB_COLOR1_ATTRIB3__COLOR_SW_MODE_MASK                                                                 0x0007C000L
26728 #define CB_COLOR1_ATTRIB3__FMASK_SW_MODE_MASK                                                                 0x00F80000L
26729 #define CB_COLOR1_ATTRIB3__RESOURCE_TYPE_MASK                                                                 0x03000000L
26730 #define CB_COLOR1_ATTRIB3__CMASK_PIPE_ALIGNED_MASK                                                            0x04000000L
26731 #define CB_COLOR1_ATTRIB3__RESOURCE_LEVEL_MASK                                                                0x38000000L
26732 #define CB_COLOR1_ATTRIB3__DCC_PIPE_ALIGNED_MASK                                                              0x40000000L
26733 //CB_COLOR2_ATTRIB3
26734 #define CB_COLOR2_ATTRIB3__MIP0_DEPTH__SHIFT                                                                  0x0
26735 #define CB_COLOR2_ATTRIB3__META_LINEAR__SHIFT                                                                 0xd
26736 #define CB_COLOR2_ATTRIB3__COLOR_SW_MODE__SHIFT                                                               0xe
26737 #define CB_COLOR2_ATTRIB3__FMASK_SW_MODE__SHIFT                                                               0x13
26738 #define CB_COLOR2_ATTRIB3__RESOURCE_TYPE__SHIFT                                                               0x18
26739 #define CB_COLOR2_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT                                                          0x1a
26740 #define CB_COLOR2_ATTRIB3__RESOURCE_LEVEL__SHIFT                                                              0x1b
26741 #define CB_COLOR2_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT                                                            0x1e
26742 #define CB_COLOR2_ATTRIB3__MIP0_DEPTH_MASK                                                                    0x00001FFFL
26743 #define CB_COLOR2_ATTRIB3__META_LINEAR_MASK                                                                   0x00002000L
26744 #define CB_COLOR2_ATTRIB3__COLOR_SW_MODE_MASK                                                                 0x0007C000L
26745 #define CB_COLOR2_ATTRIB3__FMASK_SW_MODE_MASK                                                                 0x00F80000L
26746 #define CB_COLOR2_ATTRIB3__RESOURCE_TYPE_MASK                                                                 0x03000000L
26747 #define CB_COLOR2_ATTRIB3__CMASK_PIPE_ALIGNED_MASK                                                            0x04000000L
26748 #define CB_COLOR2_ATTRIB3__RESOURCE_LEVEL_MASK                                                                0x38000000L
26749 #define CB_COLOR2_ATTRIB3__DCC_PIPE_ALIGNED_MASK                                                              0x40000000L
26750 //CB_COLOR3_ATTRIB3
26751 #define CB_COLOR3_ATTRIB3__MIP0_DEPTH__SHIFT                                                                  0x0
26752 #define CB_COLOR3_ATTRIB3__META_LINEAR__SHIFT                                                                 0xd
26753 #define CB_COLOR3_ATTRIB3__COLOR_SW_MODE__SHIFT                                                               0xe
26754 #define CB_COLOR3_ATTRIB3__FMASK_SW_MODE__SHIFT                                                               0x13
26755 #define CB_COLOR3_ATTRIB3__RESOURCE_TYPE__SHIFT                                                               0x18
26756 #define CB_COLOR3_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT                                                          0x1a
26757 #define CB_COLOR3_ATTRIB3__RESOURCE_LEVEL__SHIFT                                                              0x1b
26758 #define CB_COLOR3_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT                                                            0x1e
26759 #define CB_COLOR3_ATTRIB3__MIP0_DEPTH_MASK                                                                    0x00001FFFL
26760 #define CB_COLOR3_ATTRIB3__META_LINEAR_MASK                                                                   0x00002000L
26761 #define CB_COLOR3_ATTRIB3__COLOR_SW_MODE_MASK                                                                 0x0007C000L
26762 #define CB_COLOR3_ATTRIB3__FMASK_SW_MODE_MASK                                                                 0x00F80000L
26763 #define CB_COLOR3_ATTRIB3__RESOURCE_TYPE_MASK                                                                 0x03000000L
26764 #define CB_COLOR3_ATTRIB3__CMASK_PIPE_ALIGNED_MASK                                                            0x04000000L
26765 #define CB_COLOR3_ATTRIB3__RESOURCE_LEVEL_MASK                                                                0x38000000L
26766 #define CB_COLOR3_ATTRIB3__DCC_PIPE_ALIGNED_MASK                                                              0x40000000L
26767 //CB_COLOR4_ATTRIB3
26768 #define CB_COLOR4_ATTRIB3__MIP0_DEPTH__SHIFT                                                                  0x0
26769 #define CB_COLOR4_ATTRIB3__META_LINEAR__SHIFT                                                                 0xd
26770 #define CB_COLOR4_ATTRIB3__COLOR_SW_MODE__SHIFT                                                               0xe
26771 #define CB_COLOR4_ATTRIB3__FMASK_SW_MODE__SHIFT                                                               0x13
26772 #define CB_COLOR4_ATTRIB3__RESOURCE_TYPE__SHIFT                                                               0x18
26773 #define CB_COLOR4_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT                                                          0x1a
26774 #define CB_COLOR4_ATTRIB3__RESOURCE_LEVEL__SHIFT                                                              0x1b
26775 #define CB_COLOR4_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT                                                            0x1e
26776 #define CB_COLOR4_ATTRIB3__MIP0_DEPTH_MASK                                                                    0x00001FFFL
26777 #define CB_COLOR4_ATTRIB3__META_LINEAR_MASK                                                                   0x00002000L
26778 #define CB_COLOR4_ATTRIB3__COLOR_SW_MODE_MASK                                                                 0x0007C000L
26779 #define CB_COLOR4_ATTRIB3__FMASK_SW_MODE_MASK                                                                 0x00F80000L
26780 #define CB_COLOR4_ATTRIB3__RESOURCE_TYPE_MASK                                                                 0x03000000L
26781 #define CB_COLOR4_ATTRIB3__CMASK_PIPE_ALIGNED_MASK                                                            0x04000000L
26782 #define CB_COLOR4_ATTRIB3__RESOURCE_LEVEL_MASK                                                                0x38000000L
26783 #define CB_COLOR4_ATTRIB3__DCC_PIPE_ALIGNED_MASK                                                              0x40000000L
26784 //CB_COLOR5_ATTRIB3
26785 #define CB_COLOR5_ATTRIB3__MIP0_DEPTH__SHIFT                                                                  0x0
26786 #define CB_COLOR5_ATTRIB3__META_LINEAR__SHIFT                                                                 0xd
26787 #define CB_COLOR5_ATTRIB3__COLOR_SW_MODE__SHIFT                                                               0xe
26788 #define CB_COLOR5_ATTRIB3__FMASK_SW_MODE__SHIFT                                                               0x13
26789 #define CB_COLOR5_ATTRIB3__RESOURCE_TYPE__SHIFT                                                               0x18
26790 #define CB_COLOR5_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT                                                          0x1a
26791 #define CB_COLOR5_ATTRIB3__RESOURCE_LEVEL__SHIFT                                                              0x1b
26792 #define CB_COLOR5_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT                                                            0x1e
26793 #define CB_COLOR5_ATTRIB3__MIP0_DEPTH_MASK                                                                    0x00001FFFL
26794 #define CB_COLOR5_ATTRIB3__META_LINEAR_MASK                                                                   0x00002000L
26795 #define CB_COLOR5_ATTRIB3__COLOR_SW_MODE_MASK                                                                 0x0007C000L
26796 #define CB_COLOR5_ATTRIB3__FMASK_SW_MODE_MASK                                                                 0x00F80000L
26797 #define CB_COLOR5_ATTRIB3__RESOURCE_TYPE_MASK                                                                 0x03000000L
26798 #define CB_COLOR5_ATTRIB3__CMASK_PIPE_ALIGNED_MASK                                                            0x04000000L
26799 #define CB_COLOR5_ATTRIB3__RESOURCE_LEVEL_MASK                                                                0x38000000L
26800 #define CB_COLOR5_ATTRIB3__DCC_PIPE_ALIGNED_MASK                                                              0x40000000L
26801 //CB_COLOR6_ATTRIB3
26802 #define CB_COLOR6_ATTRIB3__MIP0_DEPTH__SHIFT                                                                  0x0
26803 #define CB_COLOR6_ATTRIB3__META_LINEAR__SHIFT                                                                 0xd
26804 #define CB_COLOR6_ATTRIB3__COLOR_SW_MODE__SHIFT                                                               0xe
26805 #define CB_COLOR6_ATTRIB3__FMASK_SW_MODE__SHIFT                                                               0x13
26806 #define CB_COLOR6_ATTRIB3__RESOURCE_TYPE__SHIFT                                                               0x18
26807 #define CB_COLOR6_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT                                                          0x1a
26808 #define CB_COLOR6_ATTRIB3__RESOURCE_LEVEL__SHIFT                                                              0x1b
26809 #define CB_COLOR6_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT                                                            0x1e
26810 #define CB_COLOR6_ATTRIB3__MIP0_DEPTH_MASK                                                                    0x00001FFFL
26811 #define CB_COLOR6_ATTRIB3__META_LINEAR_MASK                                                                   0x00002000L
26812 #define CB_COLOR6_ATTRIB3__COLOR_SW_MODE_MASK                                                                 0x0007C000L
26813 #define CB_COLOR6_ATTRIB3__FMASK_SW_MODE_MASK                                                                 0x00F80000L
26814 #define CB_COLOR6_ATTRIB3__RESOURCE_TYPE_MASK                                                                 0x03000000L
26815 #define CB_COLOR6_ATTRIB3__CMASK_PIPE_ALIGNED_MASK                                                            0x04000000L
26816 #define CB_COLOR6_ATTRIB3__RESOURCE_LEVEL_MASK                                                                0x38000000L
26817 #define CB_COLOR6_ATTRIB3__DCC_PIPE_ALIGNED_MASK                                                              0x40000000L
26818 //CB_COLOR7_ATTRIB3
26819 #define CB_COLOR7_ATTRIB3__MIP0_DEPTH__SHIFT                                                                  0x0
26820 #define CB_COLOR7_ATTRIB3__META_LINEAR__SHIFT                                                                 0xd
26821 #define CB_COLOR7_ATTRIB3__COLOR_SW_MODE__SHIFT                                                               0xe
26822 #define CB_COLOR7_ATTRIB3__FMASK_SW_MODE__SHIFT                                                               0x13
26823 #define CB_COLOR7_ATTRIB3__RESOURCE_TYPE__SHIFT                                                               0x18
26824 #define CB_COLOR7_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT                                                          0x1a
26825 #define CB_COLOR7_ATTRIB3__RESOURCE_LEVEL__SHIFT                                                              0x1b
26826 #define CB_COLOR7_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT                                                            0x1e
26827 #define CB_COLOR7_ATTRIB3__MIP0_DEPTH_MASK                                                                    0x00001FFFL
26828 #define CB_COLOR7_ATTRIB3__META_LINEAR_MASK                                                                   0x00002000L
26829 #define CB_COLOR7_ATTRIB3__COLOR_SW_MODE_MASK                                                                 0x0007C000L
26830 #define CB_COLOR7_ATTRIB3__FMASK_SW_MODE_MASK                                                                 0x00F80000L
26831 #define CB_COLOR7_ATTRIB3__RESOURCE_TYPE_MASK                                                                 0x03000000L
26832 #define CB_COLOR7_ATTRIB3__CMASK_PIPE_ALIGNED_MASK                                                            0x04000000L
26833 #define CB_COLOR7_ATTRIB3__RESOURCE_LEVEL_MASK                                                                0x38000000L
26834 #define CB_COLOR7_ATTRIB3__DCC_PIPE_ALIGNED_MASK                                                              0x40000000L
26835 
26836 
26837 // addressBlock: gc_gfxudec
26838 //CP_EOP_DONE_ADDR_LO
26839 #define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT                                                                   0x2
26840 #define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK                                                                     0xFFFFFFFCL
26841 //CP_EOP_DONE_ADDR_HI
26842 #define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT                                                                   0x0
26843 #define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK                                                                     0x0000FFFFL
26844 //CP_EOP_DONE_DATA_LO
26845 #define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT                                                                   0x0
26846 #define CP_EOP_DONE_DATA_LO__DATA_LO_MASK                                                                     0xFFFFFFFFL
26847 //CP_EOP_DONE_DATA_HI
26848 #define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT                                                                   0x0
26849 #define CP_EOP_DONE_DATA_HI__DATA_HI_MASK                                                                     0xFFFFFFFFL
26850 //CP_EOP_LAST_FENCE_LO
26851 #define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT                                                            0x0
26852 #define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK                                                              0xFFFFFFFFL
26853 //CP_EOP_LAST_FENCE_HI
26854 #define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT                                                            0x0
26855 #define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK                                                              0xFFFFFFFFL
26856 //CP_STREAM_OUT_ADDR_LO
26857 #define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT                                                      0x2
26858 #define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK                                                        0xFFFFFFFCL
26859 //CP_STREAM_OUT_ADDR_HI
26860 #define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT                                                      0x0
26861 #define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK                                                        0x0000FFFFL
26862 //CP_NUM_PRIM_WRITTEN_COUNT0_LO
26863 #define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT                                        0x0
26864 #define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK                                          0xFFFFFFFFL
26865 //CP_NUM_PRIM_WRITTEN_COUNT0_HI
26866 #define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT                                        0x0
26867 #define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK                                          0xFFFFFFFFL
26868 //CP_NUM_PRIM_NEEDED_COUNT0_LO
26869 #define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT                                          0x0
26870 #define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK                                            0xFFFFFFFFL
26871 //CP_NUM_PRIM_NEEDED_COUNT0_HI
26872 #define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT                                          0x0
26873 #define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK                                            0xFFFFFFFFL
26874 //CP_NUM_PRIM_WRITTEN_COUNT1_LO
26875 #define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT                                        0x0
26876 #define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK                                          0xFFFFFFFFL
26877 //CP_NUM_PRIM_WRITTEN_COUNT1_HI
26878 #define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT                                        0x0
26879 #define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK                                          0xFFFFFFFFL
26880 //CP_NUM_PRIM_NEEDED_COUNT1_LO
26881 #define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT                                          0x0
26882 #define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK                                            0xFFFFFFFFL
26883 //CP_NUM_PRIM_NEEDED_COUNT1_HI
26884 #define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT                                          0x0
26885 #define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK                                            0xFFFFFFFFL
26886 //CP_NUM_PRIM_WRITTEN_COUNT2_LO
26887 #define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT                                        0x0
26888 #define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK                                          0xFFFFFFFFL
26889 //CP_NUM_PRIM_WRITTEN_COUNT2_HI
26890 #define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT                                        0x0
26891 #define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK                                          0xFFFFFFFFL
26892 //CP_NUM_PRIM_NEEDED_COUNT2_LO
26893 #define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT                                          0x0
26894 #define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK                                            0xFFFFFFFFL
26895 //CP_NUM_PRIM_NEEDED_COUNT2_HI
26896 #define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT                                          0x0
26897 #define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK                                            0xFFFFFFFFL
26898 //CP_NUM_PRIM_WRITTEN_COUNT3_LO
26899 #define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT                                        0x0
26900 #define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK                                          0xFFFFFFFFL
26901 //CP_NUM_PRIM_WRITTEN_COUNT3_HI
26902 #define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT                                        0x0
26903 #define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK                                          0xFFFFFFFFL
26904 //CP_NUM_PRIM_NEEDED_COUNT3_LO
26905 #define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT                                          0x0
26906 #define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK                                            0xFFFFFFFFL
26907 //CP_NUM_PRIM_NEEDED_COUNT3_HI
26908 #define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT                                          0x0
26909 #define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK                                            0xFFFFFFFFL
26910 //CP_PIPE_STATS_ADDR_LO
26911 #define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT                                                      0x2
26912 #define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK                                                        0xFFFFFFFCL
26913 //CP_PIPE_STATS_ADDR_HI
26914 #define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT                                                      0x0
26915 #define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK                                                        0x0000FFFFL
26916 //CP_VGT_IAVERT_COUNT_LO
26917 #define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT                                                        0x0
26918 #define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK                                                          0xFFFFFFFFL
26919 //CP_VGT_IAVERT_COUNT_HI
26920 #define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT                                                        0x0
26921 #define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK                                                          0xFFFFFFFFL
26922 //CP_VGT_IAPRIM_COUNT_LO
26923 #define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT                                                        0x0
26924 #define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK                                                          0xFFFFFFFFL
26925 //CP_VGT_IAPRIM_COUNT_HI
26926 #define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT                                                        0x0
26927 #define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK                                                          0xFFFFFFFFL
26928 //CP_VGT_GSPRIM_COUNT_LO
26929 #define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT                                                        0x0
26930 #define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK                                                          0xFFFFFFFFL
26931 //CP_VGT_GSPRIM_COUNT_HI
26932 #define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT                                                        0x0
26933 #define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK                                                          0xFFFFFFFFL
26934 //CP_VGT_VSINVOC_COUNT_LO
26935 #define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT                                                      0x0
26936 #define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK                                                        0xFFFFFFFFL
26937 //CP_VGT_VSINVOC_COUNT_HI
26938 #define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT                                                      0x0
26939 #define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK                                                        0xFFFFFFFFL
26940 //CP_VGT_GSINVOC_COUNT_LO
26941 #define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT                                                      0x0
26942 #define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK                                                        0xFFFFFFFFL
26943 //CP_VGT_GSINVOC_COUNT_HI
26944 #define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT                                                      0x0
26945 #define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK                                                        0xFFFFFFFFL
26946 //CP_VGT_HSINVOC_COUNT_LO
26947 #define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT                                                      0x0
26948 #define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK                                                        0xFFFFFFFFL
26949 //CP_VGT_HSINVOC_COUNT_HI
26950 #define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT                                                      0x0
26951 #define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK                                                        0xFFFFFFFFL
26952 //CP_VGT_DSINVOC_COUNT_LO
26953 #define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT                                                      0x0
26954 #define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK                                                        0xFFFFFFFFL
26955 //CP_VGT_DSINVOC_COUNT_HI
26956 #define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT                                                      0x0
26957 #define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK                                                        0xFFFFFFFFL
26958 //CP_PA_CINVOC_COUNT_LO
26959 #define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT                                                         0x0
26960 #define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK                                                           0xFFFFFFFFL
26961 //CP_PA_CINVOC_COUNT_HI
26962 #define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT                                                         0x0
26963 #define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK                                                           0xFFFFFFFFL
26964 //CP_PA_CPRIM_COUNT_LO
26965 #define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT                                                           0x0
26966 #define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK                                                             0xFFFFFFFFL
26967 //CP_PA_CPRIM_COUNT_HI
26968 #define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT                                                           0x0
26969 #define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK                                                             0xFFFFFFFFL
26970 //CP_SC_PSINVOC_COUNT0_LO
26971 #define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT                                                     0x0
26972 #define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK                                                       0xFFFFFFFFL
26973 //CP_SC_PSINVOC_COUNT0_HI
26974 #define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT                                                     0x0
26975 #define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK                                                       0xFFFFFFFFL
26976 //CP_SC_PSINVOC_COUNT1_LO
26977 #define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT                                                              0x0
26978 #define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK                                                                0xFFFFFFFFL
26979 //CP_SC_PSINVOC_COUNT1_HI
26980 #define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT                                                              0x0
26981 #define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK                                                                0xFFFFFFFFL
26982 //CP_VGT_CSINVOC_COUNT_LO
26983 #define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT                                                      0x0
26984 #define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK                                                        0xFFFFFFFFL
26985 //CP_VGT_CSINVOC_COUNT_HI
26986 #define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT                                                      0x0
26987 #define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK                                                        0xFFFFFFFFL
26988 //CP_EOP_DONE_DOORBELL
26989 #define CP_EOP_DONE_DOORBELL__DOORBELL_OFFSET__SHIFT                                                          0x2
26990 #define CP_EOP_DONE_DOORBELL__DOORBELL_OFFSET_MASK                                                            0x0FFFFFFCL
26991 //CP_STREAM_OUT_DOORBELL
26992 #define CP_STREAM_OUT_DOORBELL__DOORBELL_OFFSET__SHIFT                                                        0x2
26993 #define CP_STREAM_OUT_DOORBELL__DOORBELL_OFFSET_MASK                                                          0x0FFFFFFCL
26994 //CP_SEM_DOORBELL
26995 #define CP_SEM_DOORBELL__DOORBELL_OFFSET__SHIFT                                                               0x2
26996 #define CP_SEM_DOORBELL__DOORBELL_OFFSET_MASK                                                                 0x0FFFFFFCL
26997 //CP_PIPE_STATS_CONTROL
26998 #define CP_PIPE_STATS_CONTROL__CACHE_POLICY__SHIFT                                                            0x19
26999 #define CP_PIPE_STATS_CONTROL__CACHE_POLICY_MASK                                                              0x06000000L
27000 //CP_STREAM_OUT_CONTROL
27001 #define CP_STREAM_OUT_CONTROL__CACHE_POLICY__SHIFT                                                            0x19
27002 #define CP_STREAM_OUT_CONTROL__CACHE_POLICY_MASK                                                              0x06000000L
27003 //CP_STRMOUT_CNTL
27004 #define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT                                                            0x0
27005 #define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK                                                              0x00000001L
27006 //SCRATCH_REG0
27007 #define SCRATCH_REG0__SCRATCH_REG0__SHIFT                                                                     0x0
27008 #define SCRATCH_REG0__SCRATCH_REG0_MASK                                                                       0xFFFFFFFFL
27009 //SCRATCH_REG1
27010 #define SCRATCH_REG1__SCRATCH_REG1__SHIFT                                                                     0x0
27011 #define SCRATCH_REG1__SCRATCH_REG1_MASK                                                                       0xFFFFFFFFL
27012 //SCRATCH_REG2
27013 #define SCRATCH_REG2__SCRATCH_REG2__SHIFT                                                                     0x0
27014 #define SCRATCH_REG2__SCRATCH_REG2_MASK                                                                       0xFFFFFFFFL
27015 //SCRATCH_REG3
27016 #define SCRATCH_REG3__SCRATCH_REG3__SHIFT                                                                     0x0
27017 #define SCRATCH_REG3__SCRATCH_REG3_MASK                                                                       0xFFFFFFFFL
27018 //SCRATCH_REG4
27019 #define SCRATCH_REG4__SCRATCH_REG4__SHIFT                                                                     0x0
27020 #define SCRATCH_REG4__SCRATCH_REG4_MASK                                                                       0xFFFFFFFFL
27021 //SCRATCH_REG5
27022 #define SCRATCH_REG5__SCRATCH_REG5__SHIFT                                                                     0x0
27023 #define SCRATCH_REG5__SCRATCH_REG5_MASK                                                                       0xFFFFFFFFL
27024 //SCRATCH_REG6
27025 #define SCRATCH_REG6__SCRATCH_REG6__SHIFT                                                                     0x0
27026 #define SCRATCH_REG6__SCRATCH_REG6_MASK                                                                       0xFFFFFFFFL
27027 //SCRATCH_REG7
27028 #define SCRATCH_REG7__SCRATCH_REG7__SHIFT                                                                     0x0
27029 #define SCRATCH_REG7__SCRATCH_REG7_MASK                                                                       0xFFFFFFFFL
27030 //CP_PIPE_STATS_DOORBELL
27031 #define CP_PIPE_STATS_DOORBELL__DOORBELL_OFFSET__SHIFT                                                        0x2
27032 #define CP_PIPE_STATS_DOORBELL__DOORBELL_OFFSET_MASK                                                          0x0FFFFFFCL
27033 //CP_APPEND_DDID_CNT
27034 #define CP_APPEND_DDID_CNT__DATA__SHIFT                                                                       0x0
27035 #define CP_APPEND_DDID_CNT__DATA_MASK                                                                         0x000000FFL
27036 //CP_APPEND_DATA_HI
27037 #define CP_APPEND_DATA_HI__DATA__SHIFT                                                                        0x0
27038 #define CP_APPEND_DATA_HI__DATA_MASK                                                                          0xFFFFFFFFL
27039 //CP_APPEND_LAST_CS_FENCE_HI
27040 #define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE__SHIFT                                                         0x0
27041 #define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE_MASK                                                           0xFFFFFFFFL
27042 //CP_APPEND_LAST_PS_FENCE_HI
27043 #define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE__SHIFT                                                         0x0
27044 #define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE_MASK                                                           0xFFFFFFFFL
27045 //SCRATCH_UMSK
27046 #define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT                                                                    0x0
27047 #define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT                                                                    0x10
27048 #define SCRATCH_UMSK__OBSOLETE_UMSK_MASK                                                                      0x000000FFL
27049 #define SCRATCH_UMSK__OBSOLETE_SWAP_MASK                                                                      0x00030000L
27050 //SCRATCH_ADDR
27051 #define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT                                                                    0x0
27052 #define SCRATCH_ADDR__OBSOLETE_ADDR_MASK                                                                      0xFFFFFFFFL
27053 //CP_PFP_ATOMIC_PREOP_LO
27054 #define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT                                                        0x0
27055 #define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK                                                          0xFFFFFFFFL
27056 //CP_PFP_ATOMIC_PREOP_HI
27057 #define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT                                                        0x0
27058 #define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK                                                          0xFFFFFFFFL
27059 //CP_PFP_GDS_ATOMIC0_PREOP_LO
27060 #define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT                                              0x0
27061 #define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK                                                0xFFFFFFFFL
27062 //CP_PFP_GDS_ATOMIC0_PREOP_HI
27063 #define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT                                              0x0
27064 #define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK                                                0xFFFFFFFFL
27065 //CP_PFP_GDS_ATOMIC1_PREOP_LO
27066 #define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT                                              0x0
27067 #define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK                                                0xFFFFFFFFL
27068 //CP_PFP_GDS_ATOMIC1_PREOP_HI
27069 #define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT                                              0x0
27070 #define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK                                                0xFFFFFFFFL
27071 //CP_APPEND_ADDR_LO
27072 #define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT                                                                 0x2
27073 #define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK                                                                   0xFFFFFFFCL
27074 //CP_APPEND_ADDR_HI
27075 #define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT                                                                 0x0
27076 #define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT                                                                   0x10
27077 #define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT                                                                0x19
27078 #define CP_APPEND_ADDR_HI__COMMAND__SHIFT                                                                     0x1d
27079 #define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK                                                                   0x0000FFFFL
27080 #define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK                                                                     0x00010000L
27081 #define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK                                                                  0x06000000L
27082 #define CP_APPEND_ADDR_HI__COMMAND_MASK                                                                       0xE0000000L
27083 //CP_APPEND_DATA
27084 #define CP_APPEND_DATA__DATA__SHIFT                                                                           0x0
27085 #define CP_APPEND_DATA__DATA_MASK                                                                             0xFFFFFFFFL
27086 //CP_APPEND_DATA_LO
27087 #define CP_APPEND_DATA_LO__DATA__SHIFT                                                                        0x0
27088 #define CP_APPEND_DATA_LO__DATA_MASK                                                                          0xFFFFFFFFL
27089 //CP_APPEND_LAST_CS_FENCE
27090 #define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT                                                            0x0
27091 #define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK                                                              0xFFFFFFFFL
27092 //CP_APPEND_LAST_CS_FENCE_LO
27093 #define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE__SHIFT                                                         0x0
27094 #define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE_MASK                                                           0xFFFFFFFFL
27095 //CP_APPEND_LAST_PS_FENCE
27096 #define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT                                                            0x0
27097 #define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK                                                              0xFFFFFFFFL
27098 //CP_APPEND_LAST_PS_FENCE_LO
27099 #define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE__SHIFT                                                         0x0
27100 #define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE_MASK                                                           0xFFFFFFFFL
27101 //CP_ATOMIC_PREOP_LO
27102 #define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT                                                            0x0
27103 #define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK                                                              0xFFFFFFFFL
27104 //CP_ME_ATOMIC_PREOP_LO
27105 #define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT                                                         0x0
27106 #define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK                                                           0xFFFFFFFFL
27107 //CP_ATOMIC_PREOP_HI
27108 #define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT                                                            0x0
27109 #define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK                                                              0xFFFFFFFFL
27110 //CP_ME_ATOMIC_PREOP_HI
27111 #define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT                                                         0x0
27112 #define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK                                                           0xFFFFFFFFL
27113 //CP_GDS_ATOMIC0_PREOP_LO
27114 #define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT                                                  0x0
27115 #define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK                                                    0xFFFFFFFFL
27116 //CP_ME_GDS_ATOMIC0_PREOP_LO
27117 #define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT                                               0x0
27118 #define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK                                                 0xFFFFFFFFL
27119 //CP_GDS_ATOMIC0_PREOP_HI
27120 #define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT                                                  0x0
27121 #define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK                                                    0xFFFFFFFFL
27122 //CP_ME_GDS_ATOMIC0_PREOP_HI
27123 #define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT                                               0x0
27124 #define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK                                                 0xFFFFFFFFL
27125 //CP_GDS_ATOMIC1_PREOP_LO
27126 #define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT                                                  0x0
27127 #define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK                                                    0xFFFFFFFFL
27128 //CP_ME_GDS_ATOMIC1_PREOP_LO
27129 #define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT                                               0x0
27130 #define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK                                                 0xFFFFFFFFL
27131 //CP_GDS_ATOMIC1_PREOP_HI
27132 #define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT                                                  0x0
27133 #define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK                                                    0xFFFFFFFFL
27134 //CP_ME_GDS_ATOMIC1_PREOP_HI
27135 #define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT                                               0x0
27136 #define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK                                                 0xFFFFFFFFL
27137 //CP_ME_MC_WADDR_LO
27138 #define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT                                                              0x2
27139 #define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK                                                                0xFFFFFFFCL
27140 //CP_ME_MC_WADDR_HI
27141 #define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT                                                              0x0
27142 #define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT                                                                0x16
27143 #define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK                                                                0x0000FFFFL
27144 #define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK                                                                  0x00C00000L
27145 //CP_ME_MC_WDATA_LO
27146 #define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT                                                              0x0
27147 #define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK                                                                0xFFFFFFFFL
27148 //CP_ME_MC_WDATA_HI
27149 #define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT                                                              0x0
27150 #define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK                                                                0xFFFFFFFFL
27151 //CP_ME_MC_RADDR_LO
27152 #define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT                                                              0x2
27153 #define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK                                                                0xFFFFFFFCL
27154 //CP_ME_MC_RADDR_HI
27155 #define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT                                                              0x0
27156 #define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT                                                                0x16
27157 #define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK                                                                0x0000FFFFL
27158 #define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK                                                                  0x00C00000L
27159 //CP_SEM_WAIT_TIMER
27160 #define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT                                                              0x0
27161 #define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK                                                                0xFFFFFFFFL
27162 //CP_SIG_SEM_ADDR_LO
27163 #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT                                                              0x0
27164 #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT                                                                0x3
27165 #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK                                                                0x00000003L
27166 #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK                                                                  0xFFFFFFF8L
27167 //CP_SIG_SEM_ADDR_HI
27168 #define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT                                                                0x0
27169 #define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT                                                            0x10
27170 #define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT                                                            0x14
27171 #define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT                                                            0x18
27172 #define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT                                                                 0x1d
27173 #define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK                                                                  0x0000FFFFL
27174 #define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK                                                              0x00010000L
27175 #define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK                                                              0x00100000L
27176 #define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK                                                              0x03000000L
27177 #define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK                                                                   0xE0000000L
27178 //CP_WAIT_REG_MEM_TIMEOUT
27179 #define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT                                                  0x0
27180 #define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK                                                    0xFFFFFFFFL
27181 //CP_WAIT_SEM_ADDR_LO
27182 #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT                                                             0x0
27183 #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT                                                               0x3
27184 #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK                                                               0x00000003L
27185 #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK                                                                 0xFFFFFFF8L
27186 //CP_WAIT_SEM_ADDR_HI
27187 #define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT                                                               0x0
27188 #define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT                                                           0x10
27189 #define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT                                                           0x14
27190 #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT                                                           0x18
27191 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT                                                                0x1d
27192 #define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK                                                                 0x0000FFFFL
27193 #define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK                                                             0x00010000L
27194 #define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK                                                             0x00100000L
27195 #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK                                                             0x03000000L
27196 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK                                                                  0xE0000000L
27197 //CP_DMA_PFP_CONTROL
27198 #define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR__SHIFT                                                               0xa
27199 #define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT                                                           0xd
27200 #define CP_DMA_PFP_CONTROL__SRC_VOLATLE__SHIFT                                                                0xf
27201 #define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT                                                                 0x14
27202 #define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT                                                           0x19
27203 #define CP_DMA_PFP_CONTROL__DST_VOLATLE__SHIFT                                                                0x1b
27204 #define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT                                                                 0x1d
27205 #define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR_MASK                                                                 0x00000400L
27206 #define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK                                                             0x00006000L
27207 #define CP_DMA_PFP_CONTROL__SRC_VOLATLE_MASK                                                                  0x00008000L
27208 #define CP_DMA_PFP_CONTROL__DST_SELECT_MASK                                                                   0x00300000L
27209 #define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK                                                             0x06000000L
27210 #define CP_DMA_PFP_CONTROL__DST_VOLATLE_MASK                                                                  0x08000000L
27211 #define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK                                                                   0x60000000L
27212 //CP_DMA_ME_CONTROL
27213 #define CP_DMA_ME_CONTROL__MEMLOG_CLEAR__SHIFT                                                                0xa
27214 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT                                                            0xd
27215 #define CP_DMA_ME_CONTROL__SRC_VOLATLE__SHIFT                                                                 0xf
27216 #define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT                                                                  0x14
27217 #define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT                                                            0x19
27218 #define CP_DMA_ME_CONTROL__DST_VOLATLE__SHIFT                                                                 0x1b
27219 #define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT                                                                  0x1d
27220 #define CP_DMA_ME_CONTROL__MEMLOG_CLEAR_MASK                                                                  0x00000400L
27221 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK                                                              0x00006000L
27222 #define CP_DMA_ME_CONTROL__SRC_VOLATLE_MASK                                                                   0x00008000L
27223 #define CP_DMA_ME_CONTROL__DST_SELECT_MASK                                                                    0x00300000L
27224 #define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK                                                              0x06000000L
27225 #define CP_DMA_ME_CONTROL__DST_VOLATLE_MASK                                                                   0x08000000L
27226 #define CP_DMA_ME_CONTROL__SRC_SELECT_MASK                                                                    0x60000000L
27227 //CP_COHER_BASE_HI
27228 #define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT                                                           0x0
27229 #define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK                                                             0x000000FFL
27230 //CP_COHER_START_DELAY
27231 #define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT                                                        0x0
27232 #define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK                                                          0x0000003FL
27233 //CP_COHER_CNTL
27234 #define CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT                                                                0x3
27235 #define CP_COHER_CNTL__TC_WC_ACTION_ENA__SHIFT                                                                0x4
27236 #define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA__SHIFT                                                      0x5
27237 #define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT                                                             0xf
27238 #define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT                                                                0x12
27239 #define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT                                                                 0x16
27240 #define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT                                                                   0x17
27241 #define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT                                                                   0x19
27242 #define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT                                                                   0x1a
27243 #define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT                                                            0x1b
27244 #define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT                                                        0x1c
27245 #define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT                                                            0x1d
27246 #define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT                                                         0x1e
27247 #define CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK                                                                  0x00000008L
27248 #define CP_COHER_CNTL__TC_WC_ACTION_ENA_MASK                                                                  0x00000010L
27249 #define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA_MASK                                                        0x00000020L
27250 #define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK                                                               0x00008000L
27251 #define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK                                                                  0x00040000L
27252 #define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK                                                                   0x00400000L
27253 #define CP_COHER_CNTL__TC_ACTION_ENA_MASK                                                                     0x00800000L
27254 #define CP_COHER_CNTL__CB_ACTION_ENA_MASK                                                                     0x02000000L
27255 #define CP_COHER_CNTL__DB_ACTION_ENA_MASK                                                                     0x04000000L
27256 #define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK                                                              0x08000000L
27257 #define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK                                                          0x10000000L
27258 #define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK                                                              0x20000000L
27259 #define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK                                                           0x40000000L
27260 //CP_COHER_SIZE
27261 #define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT                                                                 0x0
27262 #define CP_COHER_SIZE__COHER_SIZE_256B_MASK                                                                   0xFFFFFFFFL
27263 //CP_COHER_BASE
27264 #define CP_COHER_BASE__COHER_BASE_256B__SHIFT                                                                 0x0
27265 #define CP_COHER_BASE__COHER_BASE_256B_MASK                                                                   0xFFFFFFFFL
27266 //CP_COHER_STATUS
27267 #define CP_COHER_STATUS__MEID__SHIFT                                                                          0x18
27268 #define CP_COHER_STATUS__STATUS__SHIFT                                                                        0x1f
27269 #define CP_COHER_STATUS__MEID_MASK                                                                            0x03000000L
27270 #define CP_COHER_STATUS__STATUS_MASK                                                                          0x80000000L
27271 //CP_DMA_ME_SRC_ADDR
27272 #define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT                                                                   0x0
27273 #define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK                                                                     0xFFFFFFFFL
27274 //CP_DMA_ME_SRC_ADDR_HI
27275 #define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT                                                             0x0
27276 #define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK                                                               0x0000FFFFL
27277 //CP_DMA_ME_DST_ADDR
27278 #define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT                                                                   0x0
27279 #define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK                                                                     0xFFFFFFFFL
27280 //CP_DMA_ME_DST_ADDR_HI
27281 #define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT                                                             0x0
27282 #define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK                                                               0x0000FFFFL
27283 //CP_DMA_ME_COMMAND
27284 #define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT                                                                  0x0
27285 #define CP_DMA_ME_COMMAND__SAS__SHIFT                                                                         0x1a
27286 #define CP_DMA_ME_COMMAND__DAS__SHIFT                                                                         0x1b
27287 #define CP_DMA_ME_COMMAND__SAIC__SHIFT                                                                        0x1c
27288 #define CP_DMA_ME_COMMAND__DAIC__SHIFT                                                                        0x1d
27289 #define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT                                                                    0x1e
27290 #define CP_DMA_ME_COMMAND__DIS_WC__SHIFT                                                                      0x1f
27291 #define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK                                                                    0x03FFFFFFL
27292 #define CP_DMA_ME_COMMAND__SAS_MASK                                                                           0x04000000L
27293 #define CP_DMA_ME_COMMAND__DAS_MASK                                                                           0x08000000L
27294 #define CP_DMA_ME_COMMAND__SAIC_MASK                                                                          0x10000000L
27295 #define CP_DMA_ME_COMMAND__DAIC_MASK                                                                          0x20000000L
27296 #define CP_DMA_ME_COMMAND__RAW_WAIT_MASK                                                                      0x40000000L
27297 #define CP_DMA_ME_COMMAND__DIS_WC_MASK                                                                        0x80000000L
27298 //CP_DMA_PFP_SRC_ADDR
27299 #define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT                                                                  0x0
27300 #define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK                                                                    0xFFFFFFFFL
27301 //CP_DMA_PFP_SRC_ADDR_HI
27302 #define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT                                                            0x0
27303 #define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK                                                              0x0000FFFFL
27304 //CP_DMA_PFP_DST_ADDR
27305 #define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT                                                                  0x0
27306 #define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK                                                                    0xFFFFFFFFL
27307 //CP_DMA_PFP_DST_ADDR_HI
27308 #define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT                                                            0x0
27309 #define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK                                                              0x0000FFFFL
27310 //CP_DMA_PFP_COMMAND
27311 #define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT                                                                 0x0
27312 #define CP_DMA_PFP_COMMAND__SAS__SHIFT                                                                        0x1a
27313 #define CP_DMA_PFP_COMMAND__DAS__SHIFT                                                                        0x1b
27314 #define CP_DMA_PFP_COMMAND__SAIC__SHIFT                                                                       0x1c
27315 #define CP_DMA_PFP_COMMAND__DAIC__SHIFT                                                                       0x1d
27316 #define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT                                                                   0x1e
27317 #define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT                                                                     0x1f
27318 #define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK                                                                   0x03FFFFFFL
27319 #define CP_DMA_PFP_COMMAND__SAS_MASK                                                                          0x04000000L
27320 #define CP_DMA_PFP_COMMAND__DAS_MASK                                                                          0x08000000L
27321 #define CP_DMA_PFP_COMMAND__SAIC_MASK                                                                         0x10000000L
27322 #define CP_DMA_PFP_COMMAND__DAIC_MASK                                                                         0x20000000L
27323 #define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK                                                                     0x40000000L
27324 #define CP_DMA_PFP_COMMAND__DIS_WC_MASK                                                                       0x80000000L
27325 //CP_DMA_CNTL
27326 #define CP_DMA_CNTL__UTCL1_FAULT_CONTROL__SHIFT                                                               0x0
27327 #define CP_DMA_CNTL__WATCH_CONTROL__SHIFT                                                                     0x1
27328 #define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT                                                                       0x4
27329 #define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT                                                                      0x10
27330 #define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT                                                                    0x1c
27331 #define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT                                                                     0x1d
27332 #define CP_DMA_CNTL__PIO_COUNT__SHIFT                                                                         0x1e
27333 #define CP_DMA_CNTL__UTCL1_FAULT_CONTROL_MASK                                                                 0x00000001L
27334 #define CP_DMA_CNTL__WATCH_CONTROL_MASK                                                                       0x00000002L
27335 #define CP_DMA_CNTL__MIN_AVAILSZ_MASK                                                                         0x00000030L
27336 #define CP_DMA_CNTL__BUFFER_DEPTH_MASK                                                                        0x01FF0000L
27337 #define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK                                                                      0x10000000L
27338 #define CP_DMA_CNTL__PIO_FIFO_FULL_MASK                                                                       0x20000000L
27339 #define CP_DMA_CNTL__PIO_COUNT_MASK                                                                           0xC0000000L
27340 //CP_DMA_READ_TAGS
27341 #define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT                                                                 0x0
27342 #define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT                                                           0x1c
27343 #define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK                                                                   0x03FFFFFFL
27344 #define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK                                                             0x10000000L
27345 //CP_COHER_SIZE_HI
27346 #define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT                                                           0x0
27347 #define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK                                                             0x000000FFL
27348 //CP_PFP_IB_CONTROL
27349 #define CP_PFP_IB_CONTROL__IB_EN__SHIFT                                                                       0x0
27350 #define CP_PFP_IB_CONTROL__IB_EN_MASK                                                                         0x000000FFL
27351 //CP_PFP_LOAD_CONTROL
27352 #define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT                                                             0x0
27353 #define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT                                                               0x1
27354 #define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT                                                             0x10
27355 #define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT                                                              0x18
27356 #define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK                                                               0x00000001L
27357 #define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK                                                                 0x00000002L
27358 #define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK                                                               0x00010000L
27359 #define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK                                                                0x01000000L
27360 //CP_SCRATCH_INDEX
27361 #define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT                                                                0x0
27362 #define CP_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT                                                     0x1f
27363 #define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK                                                                  0x000000FFL
27364 #define CP_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK                                                       0x80000000L
27365 //CP_SCRATCH_DATA
27366 #define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT                                                                  0x0
27367 #define CP_SCRATCH_DATA__SCRATCH_DATA_MASK                                                                    0xFFFFFFFFL
27368 //CP_RB_OFFSET
27369 #define CP_RB_OFFSET__RB_OFFSET__SHIFT                                                                        0x0
27370 #define CP_RB_OFFSET__RB_OFFSET_MASK                                                                          0x000FFFFFL
27371 //CP_IB1_OFFSET
27372 #define CP_IB1_OFFSET__IB1_OFFSET__SHIFT                                                                      0x0
27373 #define CP_IB1_OFFSET__IB1_OFFSET_MASK                                                                        0x000FFFFFL
27374 //CP_IB2_OFFSET
27375 #define CP_IB2_OFFSET__IB2_OFFSET__SHIFT                                                                      0x0
27376 #define CP_IB2_OFFSET__IB2_OFFSET_MASK                                                                        0x000FFFFFL
27377 //CP_IB1_PREAMBLE_BEGIN
27378 #define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT                                                      0x0
27379 #define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK                                                        0x000FFFFFL
27380 //CP_IB1_PREAMBLE_END
27381 #define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT                                                          0x0
27382 #define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK                                                            0x000FFFFFL
27383 //CP_IB2_PREAMBLE_BEGIN
27384 #define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT                                                      0x0
27385 #define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK                                                        0x000FFFFFL
27386 //CP_IB2_PREAMBLE_END
27387 #define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT                                                          0x0
27388 #define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK                                                            0x000FFFFFL
27389 //CP_CE_IB1_OFFSET
27390 #define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT                                                                   0x0
27391 #define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK                                                                     0x000FFFFFL
27392 //CP_CE_IB2_OFFSET
27393 #define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT                                                                   0x0
27394 #define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK                                                                     0x000FFFFFL
27395 //CP_CE_COUNTER
27396 #define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT                                                              0x0
27397 #define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK                                                                0xFFFFFFFFL
27398 //CP_DMA_ME_CMD_ADDR_LO
27399 #define CP_DMA_ME_CMD_ADDR_LO__RSVD__SHIFT                                                                    0x0
27400 #define CP_DMA_ME_CMD_ADDR_LO__ADDR_LO__SHIFT                                                                 0x2
27401 #define CP_DMA_ME_CMD_ADDR_LO__RSVD_MASK                                                                      0x00000003L
27402 #define CP_DMA_ME_CMD_ADDR_LO__ADDR_LO_MASK                                                                   0xFFFFFFFCL
27403 //CP_DMA_ME_CMD_ADDR_HI
27404 #define CP_DMA_ME_CMD_ADDR_HI__ADDR_HI__SHIFT                                                                 0x0
27405 #define CP_DMA_ME_CMD_ADDR_HI__RSVD__SHIFT                                                                    0x10
27406 #define CP_DMA_ME_CMD_ADDR_HI__ADDR_HI_MASK                                                                   0x0000FFFFL
27407 #define CP_DMA_ME_CMD_ADDR_HI__RSVD_MASK                                                                      0xFFFF0000L
27408 //CP_DMA_PFP_CMD_ADDR_LO
27409 #define CP_DMA_PFP_CMD_ADDR_LO__RSVD__SHIFT                                                                   0x0
27410 #define CP_DMA_PFP_CMD_ADDR_LO__ADDR_LO__SHIFT                                                                0x2
27411 #define CP_DMA_PFP_CMD_ADDR_LO__RSVD_MASK                                                                     0x00000003L
27412 #define CP_DMA_PFP_CMD_ADDR_LO__ADDR_LO_MASK                                                                  0xFFFFFFFCL
27413 //CP_DMA_PFP_CMD_ADDR_HI
27414 #define CP_DMA_PFP_CMD_ADDR_HI__ADDR_HI__SHIFT                                                                0x0
27415 #define CP_DMA_PFP_CMD_ADDR_HI__RSVD__SHIFT                                                                   0x10
27416 #define CP_DMA_PFP_CMD_ADDR_HI__ADDR_HI_MASK                                                                  0x0000FFFFL
27417 #define CP_DMA_PFP_CMD_ADDR_HI__RSVD_MASK                                                                     0xFFFF0000L
27418 //CP_APPEND_CMD_ADDR_LO
27419 #define CP_APPEND_CMD_ADDR_LO__RSVD__SHIFT                                                                    0x0
27420 #define CP_APPEND_CMD_ADDR_LO__ADDR_LO__SHIFT                                                                 0x2
27421 #define CP_APPEND_CMD_ADDR_LO__RSVD_MASK                                                                      0x00000003L
27422 #define CP_APPEND_CMD_ADDR_LO__ADDR_LO_MASK                                                                   0xFFFFFFFCL
27423 //CP_APPEND_CMD_ADDR_HI
27424 #define CP_APPEND_CMD_ADDR_HI__ADDR_HI__SHIFT                                                                 0x0
27425 #define CP_APPEND_CMD_ADDR_HI__RSVD__SHIFT                                                                    0x10
27426 #define CP_APPEND_CMD_ADDR_HI__ADDR_HI_MASK                                                                   0x0000FFFFL
27427 #define CP_APPEND_CMD_ADDR_HI__RSVD_MASK                                                                      0xFFFF0000L
27428 //CP_CE_INIT_CMD_BUFSZ
27429 #define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ__SHIFT                                                           0x0
27430 #define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ_MASK                                                             0x00000FFFL
27431 //CP_CE_IB1_CMD_BUFSZ
27432 #define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT                                                             0x0
27433 #define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK                                                               0x000FFFFFL
27434 //CP_CE_IB2_CMD_BUFSZ
27435 #define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT                                                             0x0
27436 #define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK                                                               0x000FFFFFL
27437 //CP_IB1_CMD_BUFSZ
27438 #define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT                                                                0x0
27439 #define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK                                                                  0x000FFFFFL
27440 //CP_IB2_CMD_BUFSZ
27441 #define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT                                                                0x0
27442 #define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK                                                                  0x000FFFFFL
27443 //CP_ST_CMD_BUFSZ
27444 #define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ__SHIFT                                                                  0x0
27445 #define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ_MASK                                                                    0x000FFFFFL
27446 //CP_CE_INIT_BASE_LO
27447 #define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT                                                               0x5
27448 #define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK                                                                 0xFFFFFFE0L
27449 //CP_CE_INIT_BASE_HI
27450 #define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT                                                               0x0
27451 #define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK                                                                 0x0000FFFFL
27452 //CP_CE_INIT_BUFSZ
27453 #define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT                                                                   0x0
27454 #define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK                                                                     0x00000FFFL
27455 //CP_CE_IB1_BASE_LO
27456 #define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT                                                                 0x2
27457 #define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK                                                                   0xFFFFFFFCL
27458 //CP_CE_IB1_BASE_HI
27459 #define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT                                                                 0x0
27460 #define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK                                                                   0x0000FFFFL
27461 //CP_CE_IB1_BUFSZ
27462 #define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT                                                                     0x0
27463 #define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK                                                                       0x000FFFFFL
27464 //CP_CE_IB2_BASE_LO
27465 #define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT                                                                 0x2
27466 #define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK                                                                   0xFFFFFFFCL
27467 //CP_CE_IB2_BASE_HI
27468 #define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT                                                                 0x0
27469 #define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK                                                                   0x0000FFFFL
27470 //CP_CE_IB2_BUFSZ
27471 #define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT                                                                     0x0
27472 #define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK                                                                       0x000FFFFFL
27473 //CP_IB1_BASE_LO
27474 #define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT                                                                    0x2
27475 #define CP_IB1_BASE_LO__IB1_BASE_LO_MASK                                                                      0xFFFFFFFCL
27476 //CP_IB1_BASE_HI
27477 #define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT                                                                    0x0
27478 #define CP_IB1_BASE_HI__IB1_BASE_HI_MASK                                                                      0x0000FFFFL
27479 //CP_IB1_BUFSZ
27480 #define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT                                                                        0x0
27481 #define CP_IB1_BUFSZ__IB1_BUFSZ_MASK                                                                          0x000FFFFFL
27482 //CP_IB2_BASE_LO
27483 #define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT                                                                    0x2
27484 #define CP_IB2_BASE_LO__IB2_BASE_LO_MASK                                                                      0xFFFFFFFCL
27485 //CP_IB2_BASE_HI
27486 #define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT                                                                    0x0
27487 #define CP_IB2_BASE_HI__IB2_BASE_HI_MASK                                                                      0x0000FFFFL
27488 //CP_IB2_BUFSZ
27489 #define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT                                                                        0x0
27490 #define CP_IB2_BUFSZ__IB2_BUFSZ_MASK                                                                          0x000FFFFFL
27491 //CP_ST_BASE_LO
27492 #define CP_ST_BASE_LO__ST_BASE_LO__SHIFT                                                                      0x2
27493 #define CP_ST_BASE_LO__ST_BASE_LO_MASK                                                                        0xFFFFFFFCL
27494 //CP_ST_BASE_HI
27495 #define CP_ST_BASE_HI__ST_BASE_HI__SHIFT                                                                      0x0
27496 #define CP_ST_BASE_HI__ST_BASE_HI_MASK                                                                        0x0000FFFFL
27497 //CP_ST_BUFSZ
27498 #define CP_ST_BUFSZ__ST_BUFSZ__SHIFT                                                                          0x0
27499 #define CP_ST_BUFSZ__ST_BUFSZ_MASK                                                                            0x000FFFFFL
27500 //CP_EOP_DONE_EVENT_CNTL
27501 #define CP_EOP_DONE_EVENT_CNTL__GCR_CNTL__SHIFT                                                               0xc
27502 #define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY__SHIFT                                                           0x19
27503 #define CP_EOP_DONE_EVENT_CNTL__EOP_VOLATILE__SHIFT                                                           0x1b
27504 #define CP_EOP_DONE_EVENT_CNTL__EXECUTE__SHIFT                                                                0x1c
27505 #define CP_EOP_DONE_EVENT_CNTL__GCR_CNTL_MASK                                                                 0x00FFF000L
27506 #define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY_MASK                                                             0x06000000L
27507 #define CP_EOP_DONE_EVENT_CNTL__EOP_VOLATILE_MASK                                                             0x08000000L
27508 #define CP_EOP_DONE_EVENT_CNTL__EXECUTE_MASK                                                                  0x10000000L
27509 //CP_EOP_DONE_DATA_CNTL
27510 #define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT                                                                 0x10
27511 #define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT                                                                 0x18
27512 #define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT                                                                0x1d
27513 #define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK                                                                   0x00030000L
27514 #define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK                                                                   0x07000000L
27515 #define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK                                                                  0xE0000000L
27516 //CP_EOP_DONE_CNTX_ID
27517 #define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT                                                                   0x0
27518 #define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK                                                                     0xFFFFFFFFL
27519 //CP_DB_BASE_LO
27520 #define CP_DB_BASE_LO__DB_BASE_LO__SHIFT                                                                      0x2
27521 #define CP_DB_BASE_LO__DB_BASE_LO_MASK                                                                        0xFFFFFFFCL
27522 //CP_DB_BASE_HI
27523 #define CP_DB_BASE_HI__DB_BASE_HI__SHIFT                                                                      0x0
27524 #define CP_DB_BASE_HI__DB_BASE_HI_MASK                                                                        0x0000FFFFL
27525 //CP_DB_BUFSZ
27526 #define CP_DB_BUFSZ__DB_BUFSZ__SHIFT                                                                          0x0
27527 #define CP_DB_BUFSZ__DB_BUFSZ_MASK                                                                            0x000FFFFFL
27528 //CP_DB_CMD_BUFSZ
27529 #define CP_DB_CMD_BUFSZ__DB_CMD_REQSZ__SHIFT                                                                  0x0
27530 #define CP_DB_CMD_BUFSZ__DB_CMD_REQSZ_MASK                                                                    0x000FFFFFL
27531 //CP_CE_DB_BASE_LO
27532 #define CP_CE_DB_BASE_LO__DB_BASE_LO__SHIFT                                                                   0x2
27533 #define CP_CE_DB_BASE_LO__DB_BASE_LO_MASK                                                                     0xFFFFFFFCL
27534 //CP_CE_DB_BASE_HI
27535 #define CP_CE_DB_BASE_HI__DB_BASE_HI__SHIFT                                                                   0x0
27536 #define CP_CE_DB_BASE_HI__DB_BASE_HI_MASK                                                                     0x0000FFFFL
27537 //CP_CE_DB_BUFSZ
27538 #define CP_CE_DB_BUFSZ__DB_BUFSZ__SHIFT                                                                       0x0
27539 #define CP_CE_DB_BUFSZ__DB_BUFSZ_MASK                                                                         0x000FFFFFL
27540 //CP_CE_DB_CMD_BUFSZ
27541 #define CP_CE_DB_CMD_BUFSZ__DB_CMD_REQSZ__SHIFT                                                               0x0
27542 #define CP_CE_DB_CMD_BUFSZ__DB_CMD_REQSZ_MASK                                                                 0x000FFFFFL
27543 //CP_PFP_COMPLETION_STATUS
27544 #define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT                                                               0x0
27545 #define CP_PFP_COMPLETION_STATUS__STATUS_MASK                                                                 0x00000003L
27546 //CP_CE_COMPLETION_STATUS
27547 #define CP_CE_COMPLETION_STATUS__STATUS__SHIFT                                                                0x0
27548 #define CP_CE_COMPLETION_STATUS__STATUS_MASK                                                                  0x00000003L
27549 //CP_PRED_NOT_VISIBLE
27550 #define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT                                                               0x0
27551 #define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK                                                                 0x00000001L
27552 //CP_PFP_METADATA_BASE_ADDR
27553 #define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT                                                             0x0
27554 #define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK                                                               0xFFFFFFFFL
27555 //CP_PFP_METADATA_BASE_ADDR_HI
27556 #define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT                                                          0x0
27557 #define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK                                                            0x0000FFFFL
27558 //CP_CE_METADATA_BASE_ADDR
27559 #define CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT                                                              0x0
27560 #define CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK                                                                0xFFFFFFFFL
27561 //CP_CE_METADATA_BASE_ADDR_HI
27562 #define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT                                                           0x0
27563 #define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK                                                             0x0000FFFFL
27564 //CP_DRAW_INDX_INDR_ADDR
27565 #define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT                                                                0x0
27566 #define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK                                                                  0xFFFFFFFFL
27567 //CP_DRAW_INDX_INDR_ADDR_HI
27568 #define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT                                                             0x0
27569 #define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK                                                               0x0000FFFFL
27570 //CP_DISPATCH_INDR_ADDR
27571 #define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT                                                                 0x0
27572 #define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK                                                                   0xFFFFFFFFL
27573 //CP_DISPATCH_INDR_ADDR_HI
27574 #define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT                                                              0x0
27575 #define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK                                                                0x0000FFFFL
27576 //CP_INDEX_BASE_ADDR
27577 #define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT                                                                    0x0
27578 #define CP_INDEX_BASE_ADDR__ADDR_LO_MASK                                                                      0xFFFFFFFFL
27579 //CP_INDEX_BASE_ADDR_HI
27580 #define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT                                                                 0x0
27581 #define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK                                                                   0x0000FFFFL
27582 //CP_INDEX_TYPE
27583 #define CP_INDEX_TYPE__INDEX_TYPE__SHIFT                                                                      0x0
27584 #define CP_INDEX_TYPE__INDEX_TYPE_MASK                                                                        0x00000003L
27585 //CP_GDS_BKUP_ADDR
27586 #define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT                                                                      0x0
27587 #define CP_GDS_BKUP_ADDR__ADDR_LO_MASK                                                                        0xFFFFFFFFL
27588 //CP_GDS_BKUP_ADDR_HI
27589 #define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT                                                                   0x0
27590 #define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK                                                                     0x0000FFFFL
27591 //CP_SAMPLE_STATUS
27592 #define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT                                                                0x0
27593 #define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT                                                             0x1
27594 #define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT                                                              0x2
27595 #define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT                                                               0x3
27596 #define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT                                                           0x4
27597 #define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT                                                            0x5
27598 #define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT                                                         0x6
27599 #define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT                                                         0x7
27600 #define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK                                                                  0x00000001L
27601 #define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK                                                               0x00000002L
27602 #define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK                                                                0x00000004L
27603 #define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK                                                                 0x00000008L
27604 #define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK                                                             0x00000010L
27605 #define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK                                                              0x00000020L
27606 #define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK                                                           0x00000040L
27607 #define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK                                                           0x00000080L
27608 //CP_ME_COHER_CNTL
27609 #define CP_ME_COHER_CNTL__DEST_BASE_0_ENA__SHIFT                                                              0x0
27610 #define CP_ME_COHER_CNTL__DEST_BASE_1_ENA__SHIFT                                                              0x1
27611 #define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT                                                            0x6
27612 #define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT                                                            0x7
27613 #define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT                                                            0x8
27614 #define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT                                                            0x9
27615 #define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT                                                            0xa
27616 #define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT                                                            0xb
27617 #define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT                                                            0xc
27618 #define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT                                                            0xd
27619 #define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT                                                             0xe
27620 #define CP_ME_COHER_CNTL__DEST_BASE_2_ENA__SHIFT                                                              0x13
27621 #define CP_ME_COHER_CNTL__DEST_BASE_3_ENA__SHIFT                                                              0x15
27622 #define CP_ME_COHER_CNTL__DEST_BASE_0_ENA_MASK                                                                0x00000001L
27623 #define CP_ME_COHER_CNTL__DEST_BASE_1_ENA_MASK                                                                0x00000002L
27624 #define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA_MASK                                                              0x00000040L
27625 #define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA_MASK                                                              0x00000080L
27626 #define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA_MASK                                                              0x00000100L
27627 #define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA_MASK                                                              0x00000200L
27628 #define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA_MASK                                                              0x00000400L
27629 #define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA_MASK                                                              0x00000800L
27630 #define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA_MASK                                                              0x00001000L
27631 #define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA_MASK                                                              0x00002000L
27632 #define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA_MASK                                                               0x00004000L
27633 #define CP_ME_COHER_CNTL__DEST_BASE_2_ENA_MASK                                                                0x00080000L
27634 #define CP_ME_COHER_CNTL__DEST_BASE_3_ENA_MASK                                                                0x00200000L
27635 //CP_ME_COHER_SIZE
27636 #define CP_ME_COHER_SIZE__COHER_SIZE_256B__SHIFT                                                              0x0
27637 #define CP_ME_COHER_SIZE__COHER_SIZE_256B_MASK                                                                0xFFFFFFFFL
27638 //CP_ME_COHER_SIZE_HI
27639 #define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT                                                        0x0
27640 #define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK                                                          0x000000FFL
27641 //CP_ME_COHER_BASE
27642 #define CP_ME_COHER_BASE__COHER_BASE_256B__SHIFT                                                              0x0
27643 #define CP_ME_COHER_BASE__COHER_BASE_256B_MASK                                                                0xFFFFFFFFL
27644 //CP_ME_COHER_BASE_HI
27645 #define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT                                                        0x0
27646 #define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B_MASK                                                          0x000000FFL
27647 //CP_ME_COHER_STATUS
27648 #define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT                                                          0x0
27649 #define CP_ME_COHER_STATUS__STATUS__SHIFT                                                                     0x1f
27650 #define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX_MASK                                                            0x000000FFL
27651 #define CP_ME_COHER_STATUS__STATUS_MASK                                                                       0x80000000L
27652 //RLC_GPM_PERF_COUNT_0
27653 #define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT                                                              0x0
27654 #define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT                                                                 0x4
27655 #define RLC_GPM_PERF_COUNT_0__SA_INDEX__SHIFT                                                                 0x8
27656 #define RLC_GPM_PERF_COUNT_0__WGP_INDEX__SHIFT                                                                0xc
27657 #define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT                                                                0x10
27658 #define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT                                                                   0x12
27659 #define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT                                                                   0x14
27660 #define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT                                                                 0x15
27661 #define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK                                                                0x0000000FL
27662 #define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK                                                                   0x000000F0L
27663 #define RLC_GPM_PERF_COUNT_0__SA_INDEX_MASK                                                                   0x00000F00L
27664 #define RLC_GPM_PERF_COUNT_0__WGP_INDEX_MASK                                                                  0x0000F000L
27665 #define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK                                                                  0x00030000L
27666 #define RLC_GPM_PERF_COUNT_0__UNUSED_MASK                                                                     0x000C0000L
27667 #define RLC_GPM_PERF_COUNT_0__ENABLE_MASK                                                                     0x00100000L
27668 #define RLC_GPM_PERF_COUNT_0__RESERVED_MASK                                                                   0xFFE00000L
27669 //RLC_GPM_PERF_COUNT_1
27670 #define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT                                                              0x0
27671 #define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT                                                                 0x4
27672 #define RLC_GPM_PERF_COUNT_1__SA_INDEX__SHIFT                                                                 0x8
27673 #define RLC_GPM_PERF_COUNT_1__WGP_INDEX__SHIFT                                                                0xc
27674 #define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT                                                                0x10
27675 #define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT                                                                   0x12
27676 #define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT                                                                   0x14
27677 #define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT                                                                 0x15
27678 #define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK                                                                0x0000000FL
27679 #define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK                                                                   0x000000F0L
27680 #define RLC_GPM_PERF_COUNT_1__SA_INDEX_MASK                                                                   0x00000F00L
27681 #define RLC_GPM_PERF_COUNT_1__WGP_INDEX_MASK                                                                  0x0000F000L
27682 #define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK                                                                  0x00030000L
27683 #define RLC_GPM_PERF_COUNT_1__UNUSED_MASK                                                                     0x000C0000L
27684 #define RLC_GPM_PERF_COUNT_1__ENABLE_MASK                                                                     0x00100000L
27685 #define RLC_GPM_PERF_COUNT_1__RESERVED_MASK                                                                   0xFFE00000L
27686 //GRBM_GFX_INDEX
27687 #define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT                                                                 0x0
27688 #define GRBM_GFX_INDEX__SA_INDEX__SHIFT                                                                       0x8
27689 #define GRBM_GFX_INDEX__SE_INDEX__SHIFT                                                                       0x10
27690 #define GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT                                                            0x1d
27691 #define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT                                                      0x1e
27692 #define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT                                                            0x1f
27693 #define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK                                                                   0x000000FFL
27694 #define GRBM_GFX_INDEX__SA_INDEX_MASK                                                                         0x0000FF00L
27695 #define GRBM_GFX_INDEX__SE_INDEX_MASK                                                                         0x00FF0000L
27696 #define GRBM_GFX_INDEX__SA_BROADCAST_WRITES_MASK                                                              0x20000000L
27697 #define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK                                                        0x40000000L
27698 #define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK                                                              0x80000000L
27699 //VGT_ESGS_RING_SIZE_UMD
27700 #define VGT_ESGS_RING_SIZE_UMD__MEM_SIZE__SHIFT                                                               0x0
27701 #define VGT_ESGS_RING_SIZE_UMD__MEM_SIZE_MASK                                                                 0xFFFFFFFFL
27702 //VGT_GSVS_RING_SIZE_UMD
27703 #define VGT_GSVS_RING_SIZE_UMD__MEM_SIZE__SHIFT                                                               0x0
27704 #define VGT_GSVS_RING_SIZE_UMD__MEM_SIZE_MASK                                                                 0xFFFFFFFFL
27705 //VGT_PRIMITIVE_TYPE
27706 #define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT                                                                  0x0
27707 #define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK                                                                    0x0000003FL
27708 //VGT_INDEX_TYPE
27709 #define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT                                                                     0x0
27710 #define VGT_INDEX_TYPE__INDEX_TYPE_MASK                                                                       0x00000003L
27711 //VGT_STRMOUT_BUFFER_FILLED_SIZE_0
27712 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT                                                         0x0
27713 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK                                                           0xFFFFFFFFL
27714 //VGT_STRMOUT_BUFFER_FILLED_SIZE_1
27715 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT                                                         0x0
27716 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK                                                           0xFFFFFFFFL
27717 //VGT_STRMOUT_BUFFER_FILLED_SIZE_2
27718 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT                                                         0x0
27719 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK                                                           0xFFFFFFFFL
27720 //VGT_STRMOUT_BUFFER_FILLED_SIZE_3
27721 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT                                                         0x0
27722 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK                                                           0xFFFFFFFFL
27723 //GE_MIN_VTX_INDX
27724 #define GE_MIN_VTX_INDX__MIN_INDX__SHIFT                                                                      0x0
27725 #define GE_MIN_VTX_INDX__MIN_INDX_MASK                                                                        0xFFFFFFFFL
27726 //GE_INDX_OFFSET
27727 #define GE_INDX_OFFSET__INDX_OFFSET__SHIFT                                                                    0x0
27728 #define GE_INDX_OFFSET__INDX_OFFSET_MASK                                                                      0xFFFFFFFFL
27729 //GE_MULTI_PRIM_IB_RESET_EN
27730 #define GE_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT                                                            0x0
27731 #define GE_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT                                                      0x1
27732 #define GE_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK                                                              0x00000001L
27733 #define GE_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK                                                        0x00000002L
27734 //VGT_NUM_INDICES
27735 #define VGT_NUM_INDICES__NUM_INDICES__SHIFT                                                                   0x0
27736 #define VGT_NUM_INDICES__NUM_INDICES_MASK                                                                     0xFFFFFFFFL
27737 //VGT_NUM_INSTANCES
27738 #define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT                                                               0x0
27739 #define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK                                                                 0xFFFFFFFFL
27740 //VGT_TF_RING_SIZE_UMD
27741 #define VGT_TF_RING_SIZE_UMD__SIZE__SHIFT                                                                     0x0
27742 #define VGT_TF_RING_SIZE_UMD__SIZE_MASK                                                                       0x0000FFFFL
27743 //VGT_HS_OFFCHIP_PARAM_UMD
27744 #define VGT_HS_OFFCHIP_PARAM_UMD__OFFCHIP_BUFFERING__SHIFT                                                    0x0
27745 #define VGT_HS_OFFCHIP_PARAM_UMD__OFFCHIP_GRANULARITY__SHIFT                                                  0x9
27746 #define VGT_HS_OFFCHIP_PARAM_UMD__OFFCHIP_BUFFERING_MASK                                                      0x000001FFL
27747 #define VGT_HS_OFFCHIP_PARAM_UMD__OFFCHIP_GRANULARITY_MASK                                                    0x00000600L
27748 //VGT_TF_MEMORY_BASE_UMD
27749 #define VGT_TF_MEMORY_BASE_UMD__BASE__SHIFT                                                                   0x0
27750 #define VGT_TF_MEMORY_BASE_UMD__BASE_MASK                                                                     0xFFFFFFFFL
27751 //GE_DMA_FIRST_INDEX
27752 #define GE_DMA_FIRST_INDEX__FIRST_INDEX__SHIFT                                                                0x0
27753 #define GE_DMA_FIRST_INDEX__FIRST_INDEX_MASK                                                                  0xFFFFFFFFL
27754 //WD_POS_BUF_BASE
27755 #define WD_POS_BUF_BASE__BASE__SHIFT                                                                          0x0
27756 #define WD_POS_BUF_BASE__BASE_MASK                                                                            0xFFFFFFFFL
27757 //WD_POS_BUF_BASE_HI
27758 #define WD_POS_BUF_BASE_HI__BASE_HI__SHIFT                                                                    0x0
27759 #define WD_POS_BUF_BASE_HI__BASE_HI_MASK                                                                      0x000000FFL
27760 //WD_CNTL_SB_BUF_BASE
27761 #define WD_CNTL_SB_BUF_BASE__BASE__SHIFT                                                                      0x0
27762 #define WD_CNTL_SB_BUF_BASE__BASE_MASK                                                                        0xFFFFFFFFL
27763 //WD_CNTL_SB_BUF_BASE_HI
27764 #define WD_CNTL_SB_BUF_BASE_HI__BASE_HI__SHIFT                                                                0x0
27765 #define WD_CNTL_SB_BUF_BASE_HI__BASE_HI_MASK                                                                  0x000000FFL
27766 //WD_INDEX_BUF_BASE
27767 #define WD_INDEX_BUF_BASE__BASE__SHIFT                                                                        0x0
27768 #define WD_INDEX_BUF_BASE__BASE_MASK                                                                          0xFFFFFFFFL
27769 //WD_INDEX_BUF_BASE_HI
27770 #define WD_INDEX_BUF_BASE_HI__BASE_HI__SHIFT                                                                  0x0
27771 #define WD_INDEX_BUF_BASE_HI__BASE_HI_MASK                                                                    0x000000FFL
27772 //IA_MULTI_VGT_PARAM_PIPED
27773 #define IA_MULTI_VGT_PARAM_PIPED__PRIMGROUP_SIZE__SHIFT                                                       0x0
27774 #define IA_MULTI_VGT_PARAM_PIPED__PARTIAL_VS_WAVE_ON__SHIFT                                                   0x10
27775 #define IA_MULTI_VGT_PARAM_PIPED__SWITCH_ON_EOP__SHIFT                                                        0x11
27776 #define IA_MULTI_VGT_PARAM_PIPED__PARTIAL_ES_WAVE_ON__SHIFT                                                   0x12
27777 #define IA_MULTI_VGT_PARAM_PIPED__SWITCH_ON_EOI__SHIFT                                                        0x13
27778 #define IA_MULTI_VGT_PARAM_PIPED__WD_SWITCH_ON_EOP__SHIFT                                                     0x14
27779 #define IA_MULTI_VGT_PARAM_PIPED__EN_INST_OPT_BASIC__SHIFT                                                    0x15
27780 #define IA_MULTI_VGT_PARAM_PIPED__EN_INST_OPT_ADV__SHIFT                                                      0x16
27781 #define IA_MULTI_VGT_PARAM_PIPED__HW_USE_ONLY__SHIFT                                                          0x17
27782 #define IA_MULTI_VGT_PARAM_PIPED__PRIMGROUP_SIZE_MASK                                                         0x0000FFFFL
27783 #define IA_MULTI_VGT_PARAM_PIPED__PARTIAL_VS_WAVE_ON_MASK                                                     0x00010000L
27784 #define IA_MULTI_VGT_PARAM_PIPED__SWITCH_ON_EOP_MASK                                                          0x00020000L
27785 #define IA_MULTI_VGT_PARAM_PIPED__PARTIAL_ES_WAVE_ON_MASK                                                     0x00040000L
27786 #define IA_MULTI_VGT_PARAM_PIPED__SWITCH_ON_EOI_MASK                                                          0x00080000L
27787 #define IA_MULTI_VGT_PARAM_PIPED__WD_SWITCH_ON_EOP_MASK                                                       0x00100000L
27788 #define IA_MULTI_VGT_PARAM_PIPED__EN_INST_OPT_BASIC_MASK                                                      0x00200000L
27789 #define IA_MULTI_VGT_PARAM_PIPED__EN_INST_OPT_ADV_MASK                                                        0x00400000L
27790 #define IA_MULTI_VGT_PARAM_PIPED__HW_USE_ONLY_MASK                                                            0x00800000L
27791 //GE_MAX_VTX_INDX
27792 #define GE_MAX_VTX_INDX__MAX_INDX__SHIFT                                                                      0x0
27793 #define GE_MAX_VTX_INDX__MAX_INDX_MASK                                                                        0xFFFFFFFFL
27794 //VGT_INSTANCE_BASE_ID
27795 #define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID__SHIFT                                                         0x0
27796 #define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID_MASK                                                           0xFFFFFFFFL
27797 //GE_CNTL
27798 #define GE_CNTL__PRIM_GRP_SIZE__SHIFT                                                                         0x0
27799 #define GE_CNTL__VERT_GRP_SIZE__SHIFT                                                                         0x9
27800 #define GE_CNTL__BREAK_WAVE_AT_EOI__SHIFT                                                                     0x12
27801 #define GE_CNTL__PACKET_TO_ONE_PA__SHIFT                                                                      0x13
27802 #define GE_CNTL__PRIM_GRP_SIZE_MASK                                                                           0x000001FFL
27803 #define GE_CNTL__VERT_GRP_SIZE_MASK                                                                           0x0003FE00L
27804 #define GE_CNTL__BREAK_WAVE_AT_EOI_MASK                                                                       0x00040000L
27805 #define GE_CNTL__PACKET_TO_ONE_PA_MASK                                                                        0x00080000L
27806 //GE_USER_VGPR1
27807 #define GE_USER_VGPR1__DATA__SHIFT                                                                            0x0
27808 #define GE_USER_VGPR1__DATA_MASK                                                                              0xFFFFFFFFL
27809 //GE_USER_VGPR2
27810 #define GE_USER_VGPR2__DATA__SHIFT                                                                            0x0
27811 #define GE_USER_VGPR2__DATA_MASK                                                                              0xFFFFFFFFL
27812 //GE_USER_VGPR3
27813 #define GE_USER_VGPR3__DATA__SHIFT                                                                            0x0
27814 #define GE_USER_VGPR3__DATA_MASK                                                                              0xFFFFFFFFL
27815 //GE_STEREO_CNTL
27816 #define GE_STEREO_CNTL__RT_SLICE__SHIFT                                                                       0x0
27817 #define GE_STEREO_CNTL__VIEWPORT__SHIFT                                                                       0x3
27818 #define GE_STEREO_CNTL__EN_STEREO__SHIFT                                                                      0x8
27819 #define GE_STEREO_CNTL__RT_SLICE_MASK                                                                         0x00000007L
27820 #define GE_STEREO_CNTL__VIEWPORT_MASK                                                                         0x00000078L
27821 #define GE_STEREO_CNTL__EN_STEREO_MASK                                                                        0x00000100L
27822 //GE_PC_ALLOC
27823 #define GE_PC_ALLOC__OVERSUB_EN__SHIFT                                                                        0x0
27824 #define GE_PC_ALLOC__NUM_PC_LINES__SHIFT                                                                      0x1
27825 #define GE_PC_ALLOC__OVERSUB_EN_MASK                                                                          0x00000001L
27826 #define GE_PC_ALLOC__NUM_PC_LINES_MASK                                                                        0x000007FEL
27827 //VGT_TF_MEMORY_BASE_HI_UMD
27828 #define VGT_TF_MEMORY_BASE_HI_UMD__BASE_HI__SHIFT                                                             0x0
27829 #define VGT_TF_MEMORY_BASE_HI_UMD__BASE_HI_MASK                                                               0x000000FFL
27830 //GE_USER_VGPR_EN
27831 #define GE_USER_VGPR_EN__EN_USER_VGPR1__SHIFT                                                                 0x0
27832 #define GE_USER_VGPR_EN__EN_USER_VGPR2__SHIFT                                                                 0x1
27833 #define GE_USER_VGPR_EN__EN_USER_VGPR3__SHIFT                                                                 0x2
27834 #define GE_USER_VGPR_EN__EN_USER_VGPR1_MASK                                                                   0x00000001L
27835 #define GE_USER_VGPR_EN__EN_USER_VGPR2_MASK                                                                   0x00000002L
27836 #define GE_USER_VGPR_EN__EN_USER_VGPR3_MASK                                                                   0x00000004L
27837 //PA_SU_LINE_STIPPLE_VALUE
27838 #define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT                                                   0x0
27839 #define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK                                                     0x00FFFFFFL
27840 //PA_SC_LINE_STIPPLE_STATE
27841 #define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT                                                          0x0
27842 #define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT                                                        0x8
27843 #define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK                                                            0x0000000FL
27844 #define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK                                                          0x0000FF00L
27845 //PA_SC_SCREEN_EXTENT_MIN_0
27846 #define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT                                                                   0x0
27847 #define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT                                                                   0x10
27848 #define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK                                                                     0x0000FFFFL
27849 #define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK                                                                     0xFFFF0000L
27850 //PA_SC_SCREEN_EXTENT_MAX_0
27851 #define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT                                                                   0x0
27852 #define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT                                                                   0x10
27853 #define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK                                                                     0x0000FFFFL
27854 #define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK                                                                     0xFFFF0000L
27855 //PA_SC_SCREEN_EXTENT_MIN_1
27856 #define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT                                                                   0x0
27857 #define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT                                                                   0x10
27858 #define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK                                                                     0x0000FFFFL
27859 #define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK                                                                     0xFFFF0000L
27860 //PA_SC_SCREEN_EXTENT_MAX_1
27861 #define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT                                                                   0x0
27862 #define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT                                                                   0x10
27863 #define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK                                                                     0x0000FFFFL
27864 #define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK                                                                     0xFFFF0000L
27865 //PA_SC_P3D_TRAP_SCREEN_HV_EN
27866 #define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT                                              0x0
27867 #define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT                                       0x1
27868 #define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK                                                0x00000001L
27869 #define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK                                         0x00000002L
27870 //PA_SC_P3D_TRAP_SCREEN_H
27871 #define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT                                                               0x0
27872 #define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK                                                                 0x00003FFFL
27873 //PA_SC_P3D_TRAP_SCREEN_V
27874 #define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT                                                               0x0
27875 #define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK                                                                 0x00003FFFL
27876 //PA_SC_P3D_TRAP_SCREEN_OCCURRENCE
27877 #define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT                                                        0x0
27878 #define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK                                                          0x0000FFFFL
27879 //PA_SC_P3D_TRAP_SCREEN_COUNT
27880 #define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT                                                             0x0
27881 #define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK                                                               0x0000FFFFL
27882 //PA_SC_HP3D_TRAP_SCREEN_HV_EN
27883 #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT                                             0x0
27884 #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT                                      0x1
27885 #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK                                               0x00000001L
27886 #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK                                        0x00000002L
27887 //PA_SC_HP3D_TRAP_SCREEN_H
27888 #define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT                                                              0x0
27889 #define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK                                                                0x00003FFFL
27890 //PA_SC_HP3D_TRAP_SCREEN_V
27891 #define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT                                                              0x0
27892 #define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK                                                                0x00003FFFL
27893 //PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE
27894 #define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT                                                       0x0
27895 #define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK                                                         0x0000FFFFL
27896 //PA_SC_HP3D_TRAP_SCREEN_COUNT
27897 #define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT                                                            0x0
27898 #define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK                                                              0x0000FFFFL
27899 //PA_SC_TRAP_SCREEN_HV_EN
27900 #define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT                                                  0x0
27901 #define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT                                           0x1
27902 #define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK                                                    0x00000001L
27903 #define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK                                             0x00000002L
27904 //PA_SC_TRAP_SCREEN_H
27905 #define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT                                                                   0x0
27906 #define PA_SC_TRAP_SCREEN_H__X_COORD_MASK                                                                     0x00003FFFL
27907 //PA_SC_TRAP_SCREEN_V
27908 #define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT                                                                   0x0
27909 #define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK                                                                     0x00003FFFL
27910 //PA_SC_TRAP_SCREEN_OCCURRENCE
27911 #define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT                                                            0x0
27912 #define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK                                                              0x0000FFFFL
27913 //PA_SC_TRAP_SCREEN_COUNT
27914 #define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT                                                                 0x0
27915 #define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK                                                                   0x0000FFFFL
27916 //SQ_THREAD_TRACE_USERDATA_0
27917 #define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT                                                               0x0
27918 #define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK                                                                 0xFFFFFFFFL
27919 //SQ_THREAD_TRACE_USERDATA_1
27920 #define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT                                                               0x0
27921 #define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK                                                                 0xFFFFFFFFL
27922 //SQ_THREAD_TRACE_USERDATA_2
27923 #define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT                                                               0x0
27924 #define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK                                                                 0xFFFFFFFFL
27925 //SQ_THREAD_TRACE_USERDATA_3
27926 #define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT                                                               0x0
27927 #define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK                                                                 0xFFFFFFFFL
27928 //SQ_THREAD_TRACE_USERDATA_4
27929 #define SQ_THREAD_TRACE_USERDATA_4__DATA__SHIFT                                                               0x0
27930 #define SQ_THREAD_TRACE_USERDATA_4__DATA_MASK                                                                 0xFFFFFFFFL
27931 //SQ_THREAD_TRACE_USERDATA_5
27932 #define SQ_THREAD_TRACE_USERDATA_5__DATA__SHIFT                                                               0x0
27933 #define SQ_THREAD_TRACE_USERDATA_5__DATA_MASK                                                                 0xFFFFFFFFL
27934 //SQ_THREAD_TRACE_USERDATA_6
27935 #define SQ_THREAD_TRACE_USERDATA_6__DATA__SHIFT                                                               0x0
27936 #define SQ_THREAD_TRACE_USERDATA_6__DATA_MASK                                                                 0xFFFFFFFFL
27937 //SQ_THREAD_TRACE_USERDATA_7
27938 #define SQ_THREAD_TRACE_USERDATA_7__DATA__SHIFT                                                               0x0
27939 #define SQ_THREAD_TRACE_USERDATA_7__DATA_MASK                                                                 0xFFFFFFFFL
27940 //SQC_CACHES
27941 #define SQC_CACHES__TARGET_INST__SHIFT                                                                        0x0
27942 #define SQC_CACHES__TARGET_DATA__SHIFT                                                                        0x1
27943 #define SQC_CACHES__INVALIDATE__SHIFT                                                                         0x2
27944 #define SQC_CACHES__WRITEBACK__SHIFT                                                                          0x3
27945 #define SQC_CACHES__VOL__SHIFT                                                                                0x4
27946 #define SQC_CACHES__COMPLETE__SHIFT                                                                           0x10
27947 #define SQC_CACHES__L2_WB_POLICY__SHIFT                                                                       0x11
27948 #define SQC_CACHES__TARGET_INST_MASK                                                                          0x00000001L
27949 #define SQC_CACHES__TARGET_DATA_MASK                                                                          0x00000002L
27950 #define SQC_CACHES__INVALIDATE_MASK                                                                           0x00000004L
27951 #define SQC_CACHES__WRITEBACK_MASK                                                                            0x00000008L
27952 #define SQC_CACHES__VOL_MASK                                                                                  0x00000010L
27953 #define SQC_CACHES__COMPLETE_MASK                                                                             0x00010000L
27954 #define SQC_CACHES__L2_WB_POLICY_MASK                                                                         0x00060000L
27955 //SQC_WRITEBACK
27956 #define SQC_WRITEBACK__DWB__SHIFT                                                                             0x0
27957 #define SQC_WRITEBACK__DIRTY__SHIFT                                                                           0x1
27958 #define SQC_WRITEBACK__DWB_MASK                                                                               0x00000001L
27959 #define SQC_WRITEBACK__DIRTY_MASK                                                                             0x00000002L
27960 //TA_CS_BC_BASE_ADDR
27961 #define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT                                                                    0x0
27962 #define TA_CS_BC_BASE_ADDR__ADDRESS_MASK                                                                      0xFFFFFFFFL
27963 //TA_CS_BC_BASE_ADDR_HI
27964 #define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT                                                                 0x0
27965 #define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK                                                                   0x000000FFL
27966 //DB_OCCLUSION_COUNT0_LOW
27967 #define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT                                                             0x0
27968 #define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK                                                               0xFFFFFFFFL
27969 //DB_OCCLUSION_COUNT0_HI
27970 #define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT                                                               0x0
27971 #define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK                                                                 0x7FFFFFFFL
27972 //DB_OCCLUSION_COUNT1_LOW
27973 #define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT                                                             0x0
27974 #define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK                                                               0xFFFFFFFFL
27975 //DB_OCCLUSION_COUNT1_HI
27976 #define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT                                                               0x0
27977 #define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK                                                                 0x7FFFFFFFL
27978 //DB_OCCLUSION_COUNT2_LOW
27979 #define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT                                                             0x0
27980 #define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK                                                               0xFFFFFFFFL
27981 //DB_OCCLUSION_COUNT2_HI
27982 #define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT                                                               0x0
27983 #define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK                                                                 0x7FFFFFFFL
27984 //DB_OCCLUSION_COUNT3_LOW
27985 #define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT                                                             0x0
27986 #define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK                                                               0xFFFFFFFFL
27987 //DB_OCCLUSION_COUNT3_HI
27988 #define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT                                                               0x0
27989 #define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK                                                                 0x7FFFFFFFL
27990 //DB_ZPASS_COUNT_LOW
27991 #define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT                                                                  0x0
27992 #define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK                                                                    0xFFFFFFFFL
27993 //DB_ZPASS_COUNT_HI
27994 #define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT                                                                    0x0
27995 #define DB_ZPASS_COUNT_HI__COUNT_HI_MASK                                                                      0x7FFFFFFFL
27996 //GDS_RD_ADDR
27997 #define GDS_RD_ADDR__READ_ADDR__SHIFT                                                                         0x0
27998 #define GDS_RD_ADDR__READ_ADDR_MASK                                                                           0xFFFFFFFFL
27999 //GDS_RD_DATA
28000 #define GDS_RD_DATA__READ_DATA__SHIFT                                                                         0x0
28001 #define GDS_RD_DATA__READ_DATA_MASK                                                                           0xFFFFFFFFL
28002 //GDS_RD_BURST_ADDR
28003 #define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT                                                                  0x0
28004 #define GDS_RD_BURST_ADDR__BURST_ADDR_MASK                                                                    0xFFFFFFFFL
28005 //GDS_RD_BURST_COUNT
28006 #define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT                                                                0x0
28007 #define GDS_RD_BURST_COUNT__BURST_COUNT_MASK                                                                  0xFFFFFFFFL
28008 //GDS_RD_BURST_DATA
28009 #define GDS_RD_BURST_DATA__BURST_DATA__SHIFT                                                                  0x0
28010 #define GDS_RD_BURST_DATA__BURST_DATA_MASK                                                                    0xFFFFFFFFL
28011 //GDS_WR_ADDR
28012 #define GDS_WR_ADDR__WRITE_ADDR__SHIFT                                                                        0x0
28013 #define GDS_WR_ADDR__WRITE_ADDR_MASK                                                                          0xFFFFFFFFL
28014 //GDS_WR_DATA
28015 #define GDS_WR_DATA__WRITE_DATA__SHIFT                                                                        0x0
28016 #define GDS_WR_DATA__WRITE_DATA_MASK                                                                          0xFFFFFFFFL
28017 //GDS_WR_BURST_ADDR
28018 #define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT                                                                  0x0
28019 #define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK                                                                    0xFFFFFFFFL
28020 //GDS_WR_BURST_DATA
28021 #define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT                                                                  0x0
28022 #define GDS_WR_BURST_DATA__WRITE_DATA_MASK                                                                    0xFFFFFFFFL
28023 //GDS_WRITE_COMPLETE
28024 #define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT                                                             0x0
28025 #define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK                                                               0xFFFFFFFFL
28026 //GDS_ATOM_CNTL
28027 #define GDS_ATOM_CNTL__AINC__SHIFT                                                                            0x0
28028 #define GDS_ATOM_CNTL__UNUSED1__SHIFT                                                                         0x6
28029 #define GDS_ATOM_CNTL__DMODE__SHIFT                                                                           0x8
28030 #define GDS_ATOM_CNTL__UNUSED2__SHIFT                                                                         0xa
28031 #define GDS_ATOM_CNTL__AINC_MASK                                                                              0x0000003FL
28032 #define GDS_ATOM_CNTL__UNUSED1_MASK                                                                           0x000000C0L
28033 #define GDS_ATOM_CNTL__DMODE_MASK                                                                             0x00000300L
28034 #define GDS_ATOM_CNTL__UNUSED2_MASK                                                                           0xFFFFFC00L
28035 //GDS_ATOM_COMPLETE
28036 #define GDS_ATOM_COMPLETE__COMPLETE__SHIFT                                                                    0x0
28037 #define GDS_ATOM_COMPLETE__UNUSED__SHIFT                                                                      0x1
28038 #define GDS_ATOM_COMPLETE__COMPLETE_MASK                                                                      0x00000001L
28039 #define GDS_ATOM_COMPLETE__UNUSED_MASK                                                                        0xFFFFFFFEL
28040 //GDS_ATOM_BASE
28041 #define GDS_ATOM_BASE__BASE__SHIFT                                                                            0x0
28042 #define GDS_ATOM_BASE__UNUSED__SHIFT                                                                          0x10
28043 #define GDS_ATOM_BASE__BASE_MASK                                                                              0x0000FFFFL
28044 #define GDS_ATOM_BASE__UNUSED_MASK                                                                            0xFFFF0000L
28045 //GDS_ATOM_SIZE
28046 #define GDS_ATOM_SIZE__SIZE__SHIFT                                                                            0x0
28047 #define GDS_ATOM_SIZE__UNUSED__SHIFT                                                                          0x10
28048 #define GDS_ATOM_SIZE__SIZE_MASK                                                                              0x0000FFFFL
28049 #define GDS_ATOM_SIZE__UNUSED_MASK                                                                            0xFFFF0000L
28050 //GDS_ATOM_OFFSET0
28051 #define GDS_ATOM_OFFSET0__OFFSET0__SHIFT                                                                      0x0
28052 #define GDS_ATOM_OFFSET0__UNUSED__SHIFT                                                                       0x8
28053 #define GDS_ATOM_OFFSET0__OFFSET0_MASK                                                                        0x000000FFL
28054 #define GDS_ATOM_OFFSET0__UNUSED_MASK                                                                         0xFFFFFF00L
28055 //GDS_ATOM_OFFSET1
28056 #define GDS_ATOM_OFFSET1__OFFSET1__SHIFT                                                                      0x0
28057 #define GDS_ATOM_OFFSET1__UNUSED__SHIFT                                                                       0x8
28058 #define GDS_ATOM_OFFSET1__OFFSET1_MASK                                                                        0x000000FFL
28059 #define GDS_ATOM_OFFSET1__UNUSED_MASK                                                                         0xFFFFFF00L
28060 //GDS_ATOM_DST
28061 #define GDS_ATOM_DST__DST__SHIFT                                                                              0x0
28062 #define GDS_ATOM_DST__DST_MASK                                                                                0xFFFFFFFFL
28063 //GDS_ATOM_OP
28064 #define GDS_ATOM_OP__OP__SHIFT                                                                                0x0
28065 #define GDS_ATOM_OP__UNUSED__SHIFT                                                                            0x8
28066 #define GDS_ATOM_OP__OP_MASK                                                                                  0x000000FFL
28067 #define GDS_ATOM_OP__UNUSED_MASK                                                                              0xFFFFFF00L
28068 //GDS_ATOM_SRC0
28069 #define GDS_ATOM_SRC0__DATA__SHIFT                                                                            0x0
28070 #define GDS_ATOM_SRC0__DATA_MASK                                                                              0xFFFFFFFFL
28071 //GDS_ATOM_SRC0_U
28072 #define GDS_ATOM_SRC0_U__DATA__SHIFT                                                                          0x0
28073 #define GDS_ATOM_SRC0_U__DATA_MASK                                                                            0xFFFFFFFFL
28074 //GDS_ATOM_SRC1
28075 #define GDS_ATOM_SRC1__DATA__SHIFT                                                                            0x0
28076 #define GDS_ATOM_SRC1__DATA_MASK                                                                              0xFFFFFFFFL
28077 //GDS_ATOM_SRC1_U
28078 #define GDS_ATOM_SRC1_U__DATA__SHIFT                                                                          0x0
28079 #define GDS_ATOM_SRC1_U__DATA_MASK                                                                            0xFFFFFFFFL
28080 //GDS_ATOM_READ0
28081 #define GDS_ATOM_READ0__DATA__SHIFT                                                                           0x0
28082 #define GDS_ATOM_READ0__DATA_MASK                                                                             0xFFFFFFFFL
28083 //GDS_ATOM_READ0_U
28084 #define GDS_ATOM_READ0_U__DATA__SHIFT                                                                         0x0
28085 #define GDS_ATOM_READ0_U__DATA_MASK                                                                           0xFFFFFFFFL
28086 //GDS_ATOM_READ1
28087 #define GDS_ATOM_READ1__DATA__SHIFT                                                                           0x0
28088 #define GDS_ATOM_READ1__DATA_MASK                                                                             0xFFFFFFFFL
28089 //GDS_ATOM_READ1_U
28090 #define GDS_ATOM_READ1_U__DATA__SHIFT                                                                         0x0
28091 #define GDS_ATOM_READ1_U__DATA_MASK                                                                           0xFFFFFFFFL
28092 //GDS_GWS_RESOURCE_CNTL
28093 #define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT                                                                   0x0
28094 #define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT                                                                  0x6
28095 #define GDS_GWS_RESOURCE_CNTL__INDEX_MASK                                                                     0x0000003FL
28096 #define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK                                                                    0xFFFFFFC0L
28097 //GDS_GWS_RESOURCE
28098 #define GDS_GWS_RESOURCE__FLAG__SHIFT                                                                         0x0
28099 #define GDS_GWS_RESOURCE__COUNTER__SHIFT                                                                      0x1
28100 #define GDS_GWS_RESOURCE__TYPE__SHIFT                                                                         0xd
28101 #define GDS_GWS_RESOURCE__DED__SHIFT                                                                          0xe
28102 #define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT                                                                  0xf
28103 #define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT                                                                   0x10
28104 #define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT                                                                   0x1b
28105 #define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT                                                                    0x1c
28106 #define GDS_GWS_RESOURCE__HALTED__SHIFT                                                                       0x1d
28107 #define GDS_GWS_RESOURCE__UNUSED1__SHIFT                                                                      0x1e
28108 #define GDS_GWS_RESOURCE__FLAG_MASK                                                                           0x00000001L
28109 #define GDS_GWS_RESOURCE__COUNTER_MASK                                                                        0x00001FFEL
28110 #define GDS_GWS_RESOURCE__TYPE_MASK                                                                           0x00002000L
28111 #define GDS_GWS_RESOURCE__DED_MASK                                                                            0x00004000L
28112 #define GDS_GWS_RESOURCE__RELEASE_ALL_MASK                                                                    0x00008000L
28113 #define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK                                                                     0x07FF0000L
28114 #define GDS_GWS_RESOURCE__HEAD_VALID_MASK                                                                     0x08000000L
28115 #define GDS_GWS_RESOURCE__HEAD_FLAG_MASK                                                                      0x10000000L
28116 #define GDS_GWS_RESOURCE__HALTED_MASK                                                                         0x20000000L
28117 #define GDS_GWS_RESOURCE__UNUSED1_MASK                                                                        0xC0000000L
28118 //GDS_GWS_RESOURCE_CNT
28119 #define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT                                                             0x0
28120 #define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT                                                                   0x10
28121 #define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK                                                               0x0000FFFFL
28122 #define GDS_GWS_RESOURCE_CNT__UNUSED_MASK                                                                     0xFFFF0000L
28123 //GDS_OA_CNTL
28124 #define GDS_OA_CNTL__INDEX__SHIFT                                                                             0x0
28125 #define GDS_OA_CNTL__UNUSED__SHIFT                                                                            0x4
28126 #define GDS_OA_CNTL__INDEX_MASK                                                                               0x0000000FL
28127 #define GDS_OA_CNTL__UNUSED_MASK                                                                              0xFFFFFFF0L
28128 //GDS_OA_COUNTER
28129 #define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT                                                                0x0
28130 #define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK                                                                  0xFFFFFFFFL
28131 //GDS_OA_ADDRESS
28132 #define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT                                                                     0x0
28133 #define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT                                                                   0x10
28134 #define GDS_OA_ADDRESS__CRAWLER__SHIFT                                                                        0x14
28135 #define GDS_OA_ADDRESS__UNUSED__SHIFT                                                                         0x18
28136 #define GDS_OA_ADDRESS__NO_ALLOC__SHIFT                                                                       0x1e
28137 #define GDS_OA_ADDRESS__ENABLE__SHIFT                                                                         0x1f
28138 #define GDS_OA_ADDRESS__DS_ADDRESS_MASK                                                                       0x0000FFFFL
28139 #define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK                                                                     0x000F0000L
28140 #define GDS_OA_ADDRESS__CRAWLER_MASK                                                                          0x00F00000L
28141 #define GDS_OA_ADDRESS__UNUSED_MASK                                                                           0x3F000000L
28142 #define GDS_OA_ADDRESS__NO_ALLOC_MASK                                                                         0x40000000L
28143 #define GDS_OA_ADDRESS__ENABLE_MASK                                                                           0x80000000L
28144 //GDS_OA_INCDEC
28145 #define GDS_OA_INCDEC__VALUE__SHIFT                                                                           0x0
28146 #define GDS_OA_INCDEC__INCDEC__SHIFT                                                                          0x1f
28147 #define GDS_OA_INCDEC__VALUE_MASK                                                                             0x7FFFFFFFL
28148 #define GDS_OA_INCDEC__INCDEC_MASK                                                                            0x80000000L
28149 //GDS_OA_RING_SIZE
28150 #define GDS_OA_RING_SIZE__RING_SIZE__SHIFT                                                                    0x0
28151 #define GDS_OA_RING_SIZE__RING_SIZE_MASK                                                                      0xFFFFFFFFL
28152 //SPI_CONFIG_CNTL_REMAP
28153 #define SPI_CONFIG_CNTL_REMAP__RESERVED__SHIFT                                                                0x0
28154 #define SPI_CONFIG_CNTL_REMAP__RESERVED_MASK                                                                  0xFFFFFFFFL
28155 //SPI_CONFIG_CNTL_1_REMAP
28156 #define SPI_CONFIG_CNTL_1_REMAP__RESERVED__SHIFT                                                              0x0
28157 #define SPI_CONFIG_CNTL_1_REMAP__RESERVED_MASK                                                                0xFFFFFFFFL
28158 //SPI_CONFIG_CNTL_2_REMAP
28159 #define SPI_CONFIG_CNTL_2_REMAP__RESERVED__SHIFT                                                              0x0
28160 #define SPI_CONFIG_CNTL_2_REMAP__RESERVED_MASK                                                                0xFFFFFFFFL
28161 //SPI_WAVE_LIMIT_CNTL_REMAP
28162 #define SPI_WAVE_LIMIT_CNTL_REMAP__RESERVED__SHIFT                                                            0x0
28163 #define SPI_WAVE_LIMIT_CNTL_REMAP__RESERVED_MASK                                                              0xFFFFFFFFL
28164 
28165 
28166 // addressBlock: gc_cprs64dec
28167 //CP_MES_PRGRM_CNTR_START
28168 #define CP_MES_PRGRM_CNTR_START__IP_START__SHIFT                                                              0x0
28169 #define CP_MES_PRGRM_CNTR_START__IP_START_MASK                                                                0x000FFFFFL
28170 //CP_MES_INTR_ROUTINE_START
28171 #define CP_MES_INTR_ROUTINE_START__IR_START__SHIFT                                                            0x0
28172 #define CP_MES_INTR_ROUTINE_START__IR_START_MASK                                                              0xFFFFFFFFL
28173 //CP_MES_MTVEC_LO
28174 #define CP_MES_MTVEC_LO__ADDR_LO__SHIFT                                                                       0x0
28175 #define CP_MES_MTVEC_LO__ADDR_LO_MASK                                                                         0xFFFFFFFFL
28176 //CP_MES_MTVEC_HI
28177 #define CP_MES_MTVEC_HI__ADDR_LO__SHIFT                                                                       0x0
28178 #define CP_MES_MTVEC_HI__ADDR_LO_MASK                                                                         0xFFFFFFFFL
28179 //CP_MES_CNTL
28180 #define CP_MES_CNTL__MES_INVALIDATE_ICACHE__SHIFT                                                             0x4
28181 #define CP_MES_CNTL__MES_PIPE0_RESET__SHIFT                                                                   0x10
28182 #define CP_MES_CNTL__MES_PIPE1_RESET__SHIFT                                                                   0x11
28183 #define CP_MES_CNTL__MES_PIPE2_RESET__SHIFT                                                                   0x12
28184 #define CP_MES_CNTL__MES_PIPE3_RESET__SHIFT                                                                   0x13
28185 #define CP_MES_CNTL__MES_PIPE0_ACTIVE__SHIFT                                                                  0x1a
28186 #define CP_MES_CNTL__MES_PIPE1_ACTIVE__SHIFT                                                                  0x1b
28187 #define CP_MES_CNTL__MES_PIPE2_ACTIVE__SHIFT                                                                  0x1c
28188 #define CP_MES_CNTL__MES_PIPE3_ACTIVE__SHIFT                                                                  0x1d
28189 #define CP_MES_CNTL__MES_HALT__SHIFT                                                                          0x1e
28190 #define CP_MES_CNTL__MES_STEP__SHIFT                                                                          0x1f
28191 #define CP_MES_CNTL__MES_INVALIDATE_ICACHE_MASK                                                               0x00000010L
28192 #define CP_MES_CNTL__MES_PIPE0_RESET_MASK                                                                     0x00010000L
28193 #define CP_MES_CNTL__MES_PIPE1_RESET_MASK                                                                     0x00020000L
28194 #define CP_MES_CNTL__MES_PIPE2_RESET_MASK                                                                     0x00040000L
28195 #define CP_MES_CNTL__MES_PIPE3_RESET_MASK                                                                     0x00080000L
28196 #define CP_MES_CNTL__MES_PIPE0_ACTIVE_MASK                                                                    0x04000000L
28197 #define CP_MES_CNTL__MES_PIPE1_ACTIVE_MASK                                                                    0x08000000L
28198 #define CP_MES_CNTL__MES_PIPE2_ACTIVE_MASK                                                                    0x10000000L
28199 #define CP_MES_CNTL__MES_PIPE3_ACTIVE_MASK                                                                    0x20000000L
28200 #define CP_MES_CNTL__MES_HALT_MASK                                                                            0x40000000L
28201 #define CP_MES_CNTL__MES_STEP_MASK                                                                            0x80000000L
28202 //CP_MES_PIPE_PRIORITY_CNTS
28203 #define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT                                                       0x0
28204 #define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT                                                      0x8
28205 #define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT                                                      0x10
28206 #define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT                                                       0x18
28207 #define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK                                                         0x000000FFL
28208 #define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK                                                        0x0000FF00L
28209 #define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK                                                        0x00FF0000L
28210 #define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK                                                         0xFF000000L
28211 //CP_MES_PIPE0_PRIORITY
28212 #define CP_MES_PIPE0_PRIORITY__PRIORITY__SHIFT                                                                0x0
28213 #define CP_MES_PIPE0_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
28214 //CP_MES_PIPE1_PRIORITY
28215 #define CP_MES_PIPE1_PRIORITY__PRIORITY__SHIFT                                                                0x0
28216 #define CP_MES_PIPE1_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
28217 //CP_MES_PIPE2_PRIORITY
28218 #define CP_MES_PIPE2_PRIORITY__PRIORITY__SHIFT                                                                0x0
28219 #define CP_MES_PIPE2_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
28220 //CP_MES_PIPE3_PRIORITY
28221 #define CP_MES_PIPE3_PRIORITY__PRIORITY__SHIFT                                                                0x0
28222 #define CP_MES_PIPE3_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
28223 //CP_MES_HEADER_DUMP
28224 #define CP_MES_HEADER_DUMP__HEADER_DUMP__SHIFT                                                                0x0
28225 #define CP_MES_HEADER_DUMP__HEADER_DUMP_MASK                                                                  0xFFFFFFFFL
28226 //CP_MES_MIE_LO
28227 #define CP_MES_MIE_LO__MES_INT__SHIFT                                                                         0x0
28228 #define CP_MES_MIE_LO__MES_INT_MASK                                                                           0xFFFFFFFFL
28229 //CP_MES_MIE_HI
28230 #define CP_MES_MIE_HI__MES_INT__SHIFT                                                                         0x0
28231 #define CP_MES_MIE_HI__MES_INT_MASK                                                                           0xFFFFFFFFL
28232 //CP_MES_INTERRUPT
28233 #define CP_MES_INTERRUPT__MES_INT__SHIFT                                                                      0x0
28234 #define CP_MES_INTERRUPT__PENDING_INTERRUPT__SHIFT                                                            0x10
28235 #define CP_MES_INTERRUPT__MES_INT_MASK                                                                        0x0000FFFFL
28236 #define CP_MES_INTERRUPT__PENDING_INTERRUPT_MASK                                                              0xFFFF0000L
28237 //CP_MES_SCRATCH_INDEX
28238 #define CP_MES_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT                                                            0x0
28239 #define CP_MES_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT                                                 0x1f
28240 #define CP_MES_SCRATCH_INDEX__SCRATCH_INDEX_MASK                                                              0x000001FFL
28241 #define CP_MES_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK                                                   0x80000000L
28242 //CP_MES_SCRATCH_DATA
28243 #define CP_MES_SCRATCH_DATA__SCRATCH_DATA__SHIFT                                                              0x0
28244 #define CP_MES_SCRATCH_DATA__SCRATCH_DATA_MASK                                                                0xFFFFFFFFL
28245 //CP_MES_INSTR_PNTR
28246 #define CP_MES_INSTR_PNTR__INSTR_PNTR__SHIFT                                                                  0x0
28247 #define CP_MES_INSTR_PNTR__INSTR_PNTR_MASK                                                                    0x000FFFFFL
28248 //CP_MES_MSCRATCH_HI
28249 #define CP_MES_MSCRATCH_HI__DATA__SHIFT                                                                       0x0
28250 #define CP_MES_MSCRATCH_HI__DATA_MASK                                                                         0xFFFFFFFFL
28251 //CP_MES_MSCRATCH_LO
28252 #define CP_MES_MSCRATCH_LO__DATA__SHIFT                                                                       0x0
28253 #define CP_MES_MSCRATCH_LO__DATA_MASK                                                                         0xFFFFFFFFL
28254 //CP_MES_MSTATUS_LO
28255 #define CP_MES_MSTATUS_LO__STATUS_LO__SHIFT                                                                   0x0
28256 #define CP_MES_MSTATUS_LO__STATUS_LO_MASK                                                                     0xFFFFFFFFL
28257 //CP_MES_MSTATUS_HI
28258 #define CP_MES_MSTATUS_HI__STATUS_HI__SHIFT                                                                   0x0
28259 #define CP_MES_MSTATUS_HI__STATUS_HI_MASK                                                                     0xFFFFFFFFL
28260 //CP_MES_MEPC_LO
28261 #define CP_MES_MEPC_LO__MEPC_LO__SHIFT                                                                        0x0
28262 #define CP_MES_MEPC_LO__MEPC_LO_MASK                                                                          0xFFFFFFFFL
28263 //CP_MES_MEPC_HI
28264 #define CP_MES_MEPC_HI__MEPC_HI__SHIFT                                                                        0x0
28265 #define CP_MES_MEPC_HI__MEPC_HI_MASK                                                                          0xFFFFFFFFL
28266 //CP_MES_MCAUSE_LO
28267 #define CP_MES_MCAUSE_LO__CAUSE_LO__SHIFT                                                                     0x0
28268 #define CP_MES_MCAUSE_LO__CAUSE_LO_MASK                                                                       0xFFFFFFFFL
28269 //CP_MES_MCAUSE_HI
28270 #define CP_MES_MCAUSE_HI__CAUSE_HI__SHIFT                                                                     0x0
28271 #define CP_MES_MCAUSE_HI__CAUSE_HI_MASK                                                                       0xFFFFFFFFL
28272 //CP_MES_MBADADDR_LO
28273 #define CP_MES_MBADADDR_LO__ADDR_LO__SHIFT                                                                    0x0
28274 #define CP_MES_MBADADDR_LO__ADDR_LO_MASK                                                                      0xFFFFFFFFL
28275 //CP_MES_MBADADDR_HI
28276 #define CP_MES_MBADADDR_HI__ADDR_HI__SHIFT                                                                    0x0
28277 #define CP_MES_MBADADDR_HI__ADDR_HI_MASK                                                                      0xFFFFFFFFL
28278 //CP_MES_MIP_LO
28279 #define CP_MES_MIP_LO__MIP_LO__SHIFT                                                                          0x0
28280 #define CP_MES_MIP_LO__MIP_LO_MASK                                                                            0xFFFFFFFFL
28281 //CP_MES_MIP_HI
28282 #define CP_MES_MIP_HI__MIP_HI__SHIFT                                                                          0x0
28283 #define CP_MES_MIP_HI__MIP_HI_MASK                                                                            0xFFFFFFFFL
28284 //CP_MES_MCYCLE_LO
28285 #define CP_MES_MCYCLE_LO__CYCLE_LO__SHIFT                                                                     0x0
28286 #define CP_MES_MCYCLE_LO__CYCLE_LO_MASK                                                                       0xFFFFFFFFL
28287 //CP_MES_MCYCLE_HI
28288 #define CP_MES_MCYCLE_HI__CYCLE_HI__SHIFT                                                                     0x0
28289 #define CP_MES_MCYCLE_HI__CYCLE_HI_MASK                                                                       0xFFFFFFFFL
28290 //CP_MES_MTIME_LO
28291 #define CP_MES_MTIME_LO__TIME_LO__SHIFT                                                                       0x0
28292 #define CP_MES_MTIME_LO__TIME_LO_MASK                                                                         0xFFFFFFFFL
28293 //CP_MES_MTIME_HI
28294 #define CP_MES_MTIME_HI__TIME_HI__SHIFT                                                                       0x0
28295 #define CP_MES_MTIME_HI__TIME_HI_MASK                                                                         0xFFFFFFFFL
28296 //CP_MES_MINSTRET_LO
28297 #define CP_MES_MINSTRET_LO__INSTRET_LO__SHIFT                                                                 0x0
28298 #define CP_MES_MINSTRET_LO__INSTRET_LO_MASK                                                                   0xFFFFFFFFL
28299 //CP_MES_MINSTRET_HI
28300 #define CP_MES_MINSTRET_HI__INSTRET_HI__SHIFT                                                                 0x0
28301 #define CP_MES_MINSTRET_HI__INSTRET_HI_MASK                                                                   0xFFFFFFFFL
28302 //CP_MES_MISA_LO
28303 #define CP_MES_MISA_LO__MISA_LO__SHIFT                                                                        0x0
28304 #define CP_MES_MISA_LO__MISA_LO_MASK                                                                          0xFFFFFFFFL
28305 //CP_MES_MISA_HI
28306 #define CP_MES_MISA_HI__MISA_HI__SHIFT                                                                        0x0
28307 #define CP_MES_MISA_HI__MISA_HI_MASK                                                                          0xFFFFFFFFL
28308 //CP_MES_MVENDORID_LO
28309 #define CP_MES_MVENDORID_LO__MVENDORID_LO__SHIFT                                                              0x0
28310 #define CP_MES_MVENDORID_LO__MVENDORID_LO_MASK                                                                0xFFFFFFFFL
28311 //CP_MES_MVENDORID_HI
28312 #define CP_MES_MVENDORID_HI__MVENDORID_HI__SHIFT                                                              0x0
28313 #define CP_MES_MVENDORID_HI__MVENDORID_HI_MASK                                                                0xFFFFFFFFL
28314 //CP_MES_MARCHID_LO
28315 #define CP_MES_MARCHID_LO__MARCHID_LO__SHIFT                                                                  0x0
28316 #define CP_MES_MARCHID_LO__MARCHID_LO_MASK                                                                    0xFFFFFFFFL
28317 //CP_MES_MARCHID_HI
28318 #define CP_MES_MARCHID_HI__MARCHID_HI__SHIFT                                                                  0x0
28319 #define CP_MES_MARCHID_HI__MARCHID_HI_MASK                                                                    0xFFFFFFFFL
28320 //CP_MES_MIMPID_LO
28321 #define CP_MES_MIMPID_LO__MIMPID_LO__SHIFT                                                                    0x0
28322 #define CP_MES_MIMPID_LO__MIMPID_LO_MASK                                                                      0xFFFFFFFFL
28323 //CP_MES_MIMPID_HI
28324 #define CP_MES_MIMPID_HI__MIMPID_HI__SHIFT                                                                    0x0
28325 #define CP_MES_MIMPID_HI__MIMPID_HI_MASK                                                                      0xFFFFFFFFL
28326 //CP_MES_MHARTID_LO
28327 #define CP_MES_MHARTID_LO__MHARTID_LO__SHIFT                                                                  0x0
28328 #define CP_MES_MHARTID_LO__MHARTID_LO_MASK                                                                    0xFFFFFFFFL
28329 //CP_MES_MHARTID_HI
28330 #define CP_MES_MHARTID_HI__MHARTID_HI__SHIFT                                                                  0x0
28331 #define CP_MES_MHARTID_HI__MHARTID_HI_MASK                                                                    0xFFFFFFFFL
28332 //CP_MES_DC_BASE_CNTL
28333 #define CP_MES_DC_BASE_CNTL__VMID__SHIFT                                                                      0x0
28334 #define CP_MES_DC_BASE_CNTL__CACHE_POLICY__SHIFT                                                              0x18
28335 #define CP_MES_DC_BASE_CNTL__VMID_MASK                                                                        0x0000000FL
28336 #define CP_MES_DC_BASE_CNTL__CACHE_POLICY_MASK                                                                0x03000000L
28337 //CP_MES_DC_OP_CNTL
28338 #define CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE__SHIFT                                                           0x0
28339 #define CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE__SHIFT                                                  0x1
28340 #define CP_MES_DC_OP_CNTL__BYPASS_ALL__SHIFT                                                                  0x2
28341 #define CP_MES_DC_OP_CNTL__BYPASS_UNCACHED__SHIFT                                                             0x3
28342 #define CP_MES_DC_OP_CNTL__PRIME_DCACHE__SHIFT                                                                0x4
28343 #define CP_MES_DC_OP_CNTL__DCACHE_PRIMED__SHIFT                                                               0x5
28344 #define CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE_MASK                                                             0x00000001L
28345 #define CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE_MASK                                                    0x00000002L
28346 #define CP_MES_DC_OP_CNTL__BYPASS_ALL_MASK                                                                    0x00000004L
28347 #define CP_MES_DC_OP_CNTL__BYPASS_UNCACHED_MASK                                                               0x00000008L
28348 #define CP_MES_DC_OP_CNTL__PRIME_DCACHE_MASK                                                                  0x00000010L
28349 #define CP_MES_DC_OP_CNTL__DCACHE_PRIMED_MASK                                                                 0x00000020L
28350 //CP_MES_MTIMECMP_LO
28351 #define CP_MES_MTIMECMP_LO__TIME_LO__SHIFT                                                                    0x0
28352 #define CP_MES_MTIMECMP_LO__TIME_LO_MASK                                                                      0xFFFFFFFFL
28353 //CP_MES_MTIMECMP_HI
28354 #define CP_MES_MTIMECMP_HI__TIME_HI__SHIFT                                                                    0x0
28355 #define CP_MES_MTIMECMP_HI__TIME_HI_MASK                                                                      0xFFFFFFFFL
28356 //CP_MES_PROCESS_QUANTUM_PIPE0
28357 #define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_DURATION__SHIFT                                                 0x0
28358 #define CP_MES_PROCESS_QUANTUM_PIPE0__TIMER_EXPIRED__SHIFT                                                    0x1c
28359 #define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_SCALE__SHIFT                                                    0x1d
28360 #define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_EN__SHIFT                                                       0x1f
28361 #define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_DURATION_MASK                                                   0x0FFFFFFFL
28362 #define CP_MES_PROCESS_QUANTUM_PIPE0__TIMER_EXPIRED_MASK                                                      0x10000000L
28363 #define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_SCALE_MASK                                                      0x60000000L
28364 #define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_EN_MASK                                                         0x80000000L
28365 //CP_MES_PROCESS_QUANTUM_PIPE1
28366 #define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_DURATION__SHIFT                                                 0x0
28367 #define CP_MES_PROCESS_QUANTUM_PIPE1__TIMER_EXPIRED__SHIFT                                                    0x1c
28368 #define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_SCALE__SHIFT                                                    0x1d
28369 #define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_EN__SHIFT                                                       0x1f
28370 #define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_DURATION_MASK                                                   0x0FFFFFFFL
28371 #define CP_MES_PROCESS_QUANTUM_PIPE1__TIMER_EXPIRED_MASK                                                      0x10000000L
28372 #define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_SCALE_MASK                                                      0x60000000L
28373 #define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_EN_MASK                                                         0x80000000L
28374 //CP_MES_DOORBELL_CONTROL1
28375 #define CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT                                                      0x2
28376 #define CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT                                                          0x1e
28377 #define CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT__SHIFT                                                         0x1f
28378 #define CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK                                                        0x0FFFFFFCL
28379 #define CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK                                                            0x40000000L
28380 #define CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK                                                           0x80000000L
28381 //CP_MES_DOORBELL_CONTROL2
28382 #define CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT                                                      0x2
28383 #define CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT                                                          0x1e
28384 #define CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT__SHIFT                                                         0x1f
28385 #define CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK                                                        0x0FFFFFFCL
28386 #define CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK                                                            0x40000000L
28387 #define CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK                                                           0x80000000L
28388 //CP_MES_DOORBELL_CONTROL3
28389 #define CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT                                                      0x2
28390 #define CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT                                                          0x1e
28391 #define CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT__SHIFT                                                         0x1f
28392 #define CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK                                                        0x0FFFFFFCL
28393 #define CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK                                                            0x40000000L
28394 #define CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK                                                           0x80000000L
28395 //CP_MES_DOORBELL_CONTROL4
28396 #define CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT                                                      0x2
28397 #define CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT                                                          0x1e
28398 #define CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT__SHIFT                                                         0x1f
28399 #define CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK                                                        0x0FFFFFFCL
28400 #define CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK                                                            0x40000000L
28401 #define CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK                                                           0x80000000L
28402 //CP_MES_DOORBELL_CONTROL5
28403 #define CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT                                                      0x2
28404 #define CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT                                                          0x1e
28405 #define CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT__SHIFT                                                         0x1f
28406 #define CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK                                                        0x0FFFFFFCL
28407 #define CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK                                                            0x40000000L
28408 #define CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK                                                           0x80000000L
28409 //CP_MES_DOORBELL_CONTROL6
28410 #define CP_MES_DOORBELL_CONTROL6__DOORBELL_OFFSET__SHIFT                                                      0x2
28411 #define CP_MES_DOORBELL_CONTROL6__DOORBELL_EN__SHIFT                                                          0x1e
28412 #define CP_MES_DOORBELL_CONTROL6__DOORBELL_HIT__SHIFT                                                         0x1f
28413 #define CP_MES_DOORBELL_CONTROL6__DOORBELL_OFFSET_MASK                                                        0x0FFFFFFCL
28414 #define CP_MES_DOORBELL_CONTROL6__DOORBELL_EN_MASK                                                            0x40000000L
28415 #define CP_MES_DOORBELL_CONTROL6__DOORBELL_HIT_MASK                                                           0x80000000L
28416 //CP_MES_GP0_LO
28417 #define CP_MES_GP0_LO__PG_VIRT_HALTED__SHIFT                                                                  0x0
28418 #define CP_MES_GP0_LO__DATA__SHIFT                                                                            0x1
28419 #define CP_MES_GP0_LO__PG_VIRT_HALTED_MASK                                                                    0x00000001L
28420 #define CP_MES_GP0_LO__DATA_MASK                                                                              0xFFFFFFFEL
28421 //CP_MES_GP0_HI
28422 #define CP_MES_GP0_HI__M_RET_ADDR__SHIFT                                                                      0x0
28423 #define CP_MES_GP0_HI__M_RET_ADDR_MASK                                                                        0xFFFFFFFFL
28424 //CP_MES_GP1_LO
28425 #define CP_MES_GP1_LO__RD_WR_SELECT_LO__SHIFT                                                                 0x0
28426 #define CP_MES_GP1_LO__RD_WR_SELECT_LO_MASK                                                                   0xFFFFFFFFL
28427 //CP_MES_GP1_HI
28428 #define CP_MES_GP1_HI__RD_WR_SELECT_HI__SHIFT                                                                 0x0
28429 #define CP_MES_GP1_HI__RD_WR_SELECT_HI_MASK                                                                   0xFFFFFFFFL
28430 //CP_MES_GP2_LO
28431 #define CP_MES_GP2_LO__STACK_PNTR_LO__SHIFT                                                                   0x0
28432 #define CP_MES_GP2_LO__STACK_PNTR_LO_MASK                                                                     0xFFFFFFFFL
28433 //CP_MES_GP2_HI
28434 #define CP_MES_GP2_HI__STACK_PNTR_HI__SHIFT                                                                   0x0
28435 #define CP_MES_GP2_HI__STACK_PNTR_HI_MASK                                                                     0xFFFFFFFFL
28436 //CP_MES_GP3_LO
28437 #define CP_MES_GP3_LO__DATA__SHIFT                                                                            0x0
28438 #define CP_MES_GP3_LO__DATA_MASK                                                                              0xFFFFFFFFL
28439 //CP_MES_GP3_HI
28440 #define CP_MES_GP3_HI__DATA__SHIFT                                                                            0x0
28441 #define CP_MES_GP3_HI__DATA_MASK                                                                              0xFFFFFFFFL
28442 //CP_MES_GP4_LO
28443 #define CP_MES_GP4_LO__DATA__SHIFT                                                                            0x0
28444 #define CP_MES_GP4_LO__DATA_MASK                                                                              0xFFFFFFFFL
28445 //CP_MES_GP4_HI
28446 #define CP_MES_GP4_HI__DATA__SHIFT                                                                            0x0
28447 #define CP_MES_GP4_HI__DATA_MASK                                                                              0xFFFFFFFFL
28448 //CP_MES_GP5_LO
28449 #define CP_MES_GP5_LO__PG_VIRT_HALTED__SHIFT                                                                  0x0
28450 #define CP_MES_GP5_LO__DATA__SHIFT                                                                            0x1
28451 #define CP_MES_GP5_LO__PG_VIRT_HALTED_MASK                                                                    0x00000001L
28452 #define CP_MES_GP5_LO__DATA_MASK                                                                              0xFFFFFFFEL
28453 //CP_MES_GP5_HI
28454 #define CP_MES_GP5_HI__M_RET_ADDR__SHIFT                                                                      0x0
28455 #define CP_MES_GP5_HI__M_RET_ADDR_MASK                                                                        0xFFFFFFFFL
28456 //CP_MES_GP6_LO
28457 #define CP_MES_GP6_LO__RD_WR_SELECT_LO__SHIFT                                                                 0x0
28458 #define CP_MES_GP6_LO__RD_WR_SELECT_LO_MASK                                                                   0xFFFFFFFFL
28459 //CP_MES_GP6_HI
28460 #define CP_MES_GP6_HI__RD_WR_SELECT_HI__SHIFT                                                                 0x0
28461 #define CP_MES_GP6_HI__RD_WR_SELECT_HI_MASK                                                                   0xFFFFFFFFL
28462 //CP_MES_GP7_LO
28463 #define CP_MES_GP7_LO__STACK_PNTR_LO__SHIFT                                                                   0x0
28464 #define CP_MES_GP7_LO__STACK_PNTR_LO_MASK                                                                     0xFFFFFFFFL
28465 //CP_MES_GP7_HI
28466 #define CP_MES_GP7_HI__STACK_PNTR_HI__SHIFT                                                                   0x0
28467 #define CP_MES_GP7_HI__STACK_PNTR_HI_MASK                                                                     0xFFFFFFFFL
28468 //CP_MES_GP8_LO
28469 #define CP_MES_GP8_LO__DATA__SHIFT                                                                            0x0
28470 #define CP_MES_GP8_LO__DATA_MASK                                                                              0xFFFFFFFFL
28471 //CP_MES_GP8_HI
28472 #define CP_MES_GP8_HI__DATA__SHIFT                                                                            0x0
28473 #define CP_MES_GP8_HI__DATA_MASK                                                                              0xFFFFFFFFL
28474 //CP_MES_GP9_LO
28475 #define CP_MES_GP9_LO__DATA__SHIFT                                                                            0x0
28476 #define CP_MES_GP9_LO__DATA_MASK                                                                              0xFFFFFFFFL
28477 //CP_MES_GP9_HI
28478 #define CP_MES_GP9_HI__DATA__SHIFT                                                                            0x0
28479 #define CP_MES_GP9_HI__DATA_MASK                                                                              0xFFFFFFFFL
28480 //CP_MES_DM_INDEX_ADDR
28481 #define CP_MES_DM_INDEX_ADDR__ADDR__SHIFT                                                                     0x0
28482 #define CP_MES_DM_INDEX_ADDR__ADDR_MASK                                                                       0xFFFFFFFFL
28483 //CP_MES_DM_INDEX_DATA
28484 #define CP_MES_DM_INDEX_DATA__DATA__SHIFT                                                                     0x0
28485 #define CP_MES_DM_INDEX_DATA__DATA_MASK                                                                       0xFFFFFFFFL
28486 //CP_MES_DMCONTROL
28487 #define CP_MES_DMCONTROL__CONTROL__SHIFT                                                                      0x0
28488 #define CP_MES_DMCONTROL__CONTROL_MASK                                                                        0xFFFFFFFFL
28489 //CP_MES_DMINFO
28490 #define CP_MES_DMINFO__INFO__SHIFT                                                                            0x0
28491 #define CP_MES_DMINFO__INFO_MASK                                                                              0xFFFFFFFFL
28492 //CP_MES_SETHALTNOTIFICATION
28493 #define CP_MES_SETHALTNOTIFICATION__SETHALT__SHIFT                                                            0x0
28494 #define CP_MES_SETHALTNOTIFICATION__SETHALT_MASK                                                              0xFFFFFFFFL
28495 //CP_MES_TSELCT_LOW
28496 #define CP_MES_TSELCT_LOW__TSELECT__SHIFT                                                                     0x0
28497 #define CP_MES_TSELCT_LOW__TSELECT_MASK                                                                       0xFFFFFFFFL
28498 //CP_MES_TSELCT_HIGH
28499 #define CP_MES_TSELCT_HIGH__TSELECT__SHIFT                                                                    0x0
28500 #define CP_MES_TSELCT_HIGH__TSELECT_MASK                                                                      0xFFFFFFFFL
28501 //CP_MES_TDATA1_LOW
28502 #define CP_MES_TDATA1_LOW__DATA__SHIFT                                                                        0x0
28503 #define CP_MES_TDATA1_LOW__DATA_MASK                                                                          0xFFFFFFFFL
28504 //CP_MES_TDATA1_HIGH
28505 #define CP_MES_TDATA1_HIGH__DATA__SHIFT                                                                       0x0
28506 #define CP_MES_TDATA1_HIGH__DATA_MASK                                                                         0xFFFFFFFFL
28507 //CP_MES_TDATA2_LOW
28508 #define CP_MES_TDATA2_LOW__DATA__SHIFT                                                                        0x0
28509 #define CP_MES_TDATA2_LOW__DATA_MASK                                                                          0xFFFFFFFFL
28510 //CP_MES_TDATA2_HIGH
28511 #define CP_MES_TDATA2_HIGH__DATA__SHIFT                                                                       0x0
28512 #define CP_MES_TDATA2_HIGH__DATA_MASK                                                                         0xFFFFFFFFL
28513 //CP_MES_TDATA3_LOW
28514 #define CP_MES_TDATA3_LOW__DATA__SHIFT                                                                        0x0
28515 #define CP_MES_TDATA3_LOW__DATA_MASK                                                                          0xFFFFFFFFL
28516 //CP_MES_TDATA3_HIH
28517 #define CP_MES_TDATA3_HIH__DATA__SHIFT                                                                        0x0
28518 #define CP_MES_TDATA3_HIH__DATA_MASK                                                                          0xFFFFFFFFL
28519 //CP_MES_DCSR
28520 #define CP_MES_DCSR__CSR__SHIFT                                                                               0x0
28521 #define CP_MES_DCSR__CSR_MASK                                                                                 0xFFFFFFFFL
28522 //CP_MES_DPC_LOW
28523 #define CP_MES_DPC_LOW__INSTR_PNTR__SHIFT                                                                     0x0
28524 #define CP_MES_DPC_LOW__INSTR_PNTR_MASK                                                                       0xFFFFFFFFL
28525 //CP_MES_DPC_HIGH
28526 #define CP_MES_DPC_HIGH__INSTR_PNTR__SHIFT                                                                    0x0
28527 #define CP_MES_DPC_HIGH__INSTR_PNTR_MASK                                                                      0xFFFFFFFFL
28528 //CP_MES_DSCRATCH_LOW
28529 #define CP_MES_DSCRATCH_LOW__DATA__SHIFT                                                                      0x0
28530 #define CP_MES_DSCRATCH_LOW__DATA_MASK                                                                        0xFFFFFFFFL
28531 //CP_MES_DSCRATCH_HIGH
28532 #define CP_MES_DSCRATCH_HIGH__DATA__SHIFT                                                                     0x0
28533 #define CP_MES_DSCRATCH_HIGH__DATA_MASK                                                                       0xFFFFFFFFL
28534 //CP_MES_PERFCOUNT_CNTL
28535 #define CP_MES_PERFCOUNT_CNTL__EVENT_SEL__SHIFT                                                               0x0
28536 #define CP_MES_PERFCOUNT_CNTL__EVENT_SEL_MASK                                                                 0x00000007L
28537 
28538 
28539 // addressBlock: gc_gusdec
28540 //GUS_IO_RD_COMBINE_FLUSH
28541 #define GUS_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                          0x0
28542 #define GUS_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                          0x4
28543 #define GUS_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                          0x8
28544 #define GUS_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                          0xc
28545 #define GUS_IO_RD_COMBINE_FLUSH__GROUP4_TIMER__SHIFT                                                          0x10
28546 #define GUS_IO_RD_COMBINE_FLUSH__GROUP5_TIMER__SHIFT                                                          0x14
28547 #define GUS_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                            0x0000000FL
28548 #define GUS_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                            0x000000F0L
28549 #define GUS_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                            0x00000F00L
28550 #define GUS_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                            0x0000F000L
28551 #define GUS_IO_RD_COMBINE_FLUSH__GROUP4_TIMER_MASK                                                            0x000F0000L
28552 #define GUS_IO_RD_COMBINE_FLUSH__GROUP5_TIMER_MASK                                                            0x00F00000L
28553 //GUS_IO_WR_COMBINE_FLUSH
28554 #define GUS_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                          0x0
28555 #define GUS_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                          0x4
28556 #define GUS_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                          0x8
28557 #define GUS_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                          0xc
28558 #define GUS_IO_WR_COMBINE_FLUSH__GROUP4_TIMER__SHIFT                                                          0x10
28559 #define GUS_IO_WR_COMBINE_FLUSH__GROUP5_TIMER__SHIFT                                                          0x14
28560 #define GUS_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                            0x0000000FL
28561 #define GUS_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                            0x000000F0L
28562 #define GUS_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                            0x00000F00L
28563 #define GUS_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                            0x0000F000L
28564 #define GUS_IO_WR_COMBINE_FLUSH__GROUP4_TIMER_MASK                                                            0x000F0000L
28565 #define GUS_IO_WR_COMBINE_FLUSH__GROUP5_TIMER_MASK                                                            0x00F00000L
28566 //GUS_IO_RD_PRI_AGE_RATE
28567 #define GUS_IO_RD_PRI_AGE_RATE__GROUP0_AGING_RATE__SHIFT                                                      0x0
28568 #define GUS_IO_RD_PRI_AGE_RATE__GROUP1_AGING_RATE__SHIFT                                                      0x3
28569 #define GUS_IO_RD_PRI_AGE_RATE__GROUP2_AGING_RATE__SHIFT                                                      0x6
28570 #define GUS_IO_RD_PRI_AGE_RATE__GROUP3_AGING_RATE__SHIFT                                                      0x9
28571 #define GUS_IO_RD_PRI_AGE_RATE__GROUP4_AGING_RATE__SHIFT                                                      0xc
28572 #define GUS_IO_RD_PRI_AGE_RATE__GROUP5_AGING_RATE__SHIFT                                                      0xf
28573 #define GUS_IO_RD_PRI_AGE_RATE__GROUP0_AGING_RATE_MASK                                                        0x00000007L
28574 #define GUS_IO_RD_PRI_AGE_RATE__GROUP1_AGING_RATE_MASK                                                        0x00000038L
28575 #define GUS_IO_RD_PRI_AGE_RATE__GROUP2_AGING_RATE_MASK                                                        0x000001C0L
28576 #define GUS_IO_RD_PRI_AGE_RATE__GROUP3_AGING_RATE_MASK                                                        0x00000E00L
28577 #define GUS_IO_RD_PRI_AGE_RATE__GROUP4_AGING_RATE_MASK                                                        0x00007000L
28578 #define GUS_IO_RD_PRI_AGE_RATE__GROUP5_AGING_RATE_MASK                                                        0x00038000L
28579 //GUS_IO_WR_PRI_AGE_RATE
28580 #define GUS_IO_WR_PRI_AGE_RATE__GROUP0_AGING_RATE__SHIFT                                                      0x0
28581 #define GUS_IO_WR_PRI_AGE_RATE__GROUP1_AGING_RATE__SHIFT                                                      0x3
28582 #define GUS_IO_WR_PRI_AGE_RATE__GROUP2_AGING_RATE__SHIFT                                                      0x6
28583 #define GUS_IO_WR_PRI_AGE_RATE__GROUP3_AGING_RATE__SHIFT                                                      0x9
28584 #define GUS_IO_WR_PRI_AGE_RATE__GROUP4_AGING_RATE__SHIFT                                                      0xc
28585 #define GUS_IO_WR_PRI_AGE_RATE__GROUP5_AGING_RATE__SHIFT                                                      0xf
28586 #define GUS_IO_WR_PRI_AGE_RATE__GROUP0_AGING_RATE_MASK                                                        0x00000007L
28587 #define GUS_IO_WR_PRI_AGE_RATE__GROUP1_AGING_RATE_MASK                                                        0x00000038L
28588 #define GUS_IO_WR_PRI_AGE_RATE__GROUP2_AGING_RATE_MASK                                                        0x000001C0L
28589 #define GUS_IO_WR_PRI_AGE_RATE__GROUP3_AGING_RATE_MASK                                                        0x00000E00L
28590 #define GUS_IO_WR_PRI_AGE_RATE__GROUP4_AGING_RATE_MASK                                                        0x00007000L
28591 #define GUS_IO_WR_PRI_AGE_RATE__GROUP5_AGING_RATE_MASK                                                        0x00038000L
28592 //GUS_IO_RD_PRI_AGE_COEFF
28593 #define GUS_IO_RD_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT__SHIFT                                                0x0
28594 #define GUS_IO_RD_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT__SHIFT                                                0x3
28595 #define GUS_IO_RD_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT__SHIFT                                                0x6
28596 #define GUS_IO_RD_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT__SHIFT                                                0x9
28597 #define GUS_IO_RD_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT__SHIFT                                                0xc
28598 #define GUS_IO_RD_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT__SHIFT                                                0xf
28599 #define GUS_IO_RD_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT_MASK                                                  0x00000007L
28600 #define GUS_IO_RD_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT_MASK                                                  0x00000038L
28601 #define GUS_IO_RD_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT_MASK                                                  0x000001C0L
28602 #define GUS_IO_RD_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT_MASK                                                  0x00000E00L
28603 #define GUS_IO_RD_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT_MASK                                                  0x00007000L
28604 #define GUS_IO_RD_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT_MASK                                                  0x00038000L
28605 //GUS_IO_WR_PRI_AGE_COEFF
28606 #define GUS_IO_WR_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT__SHIFT                                                0x0
28607 #define GUS_IO_WR_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT__SHIFT                                                0x3
28608 #define GUS_IO_WR_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT__SHIFT                                                0x6
28609 #define GUS_IO_WR_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT__SHIFT                                                0x9
28610 #define GUS_IO_WR_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT__SHIFT                                                0xc
28611 #define GUS_IO_WR_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT__SHIFT                                                0xf
28612 #define GUS_IO_WR_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT_MASK                                                  0x00000007L
28613 #define GUS_IO_WR_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT_MASK                                                  0x00000038L
28614 #define GUS_IO_WR_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT_MASK                                                  0x000001C0L
28615 #define GUS_IO_WR_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT_MASK                                                  0x00000E00L
28616 #define GUS_IO_WR_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT_MASK                                                  0x00007000L
28617 #define GUS_IO_WR_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT_MASK                                                  0x00038000L
28618 //GUS_IO_RD_PRI_QUEUING
28619 #define GUS_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                              0x0
28620 #define GUS_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                              0x3
28621 #define GUS_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                              0x6
28622 #define GUS_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                              0x9
28623 #define GUS_IO_RD_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT__SHIFT                                              0xc
28624 #define GUS_IO_RD_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT__SHIFT                                              0xf
28625 #define GUS_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                                0x00000007L
28626 #define GUS_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                                0x00000038L
28627 #define GUS_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                                0x000001C0L
28628 #define GUS_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                                0x00000E00L
28629 #define GUS_IO_RD_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT_MASK                                                0x00007000L
28630 #define GUS_IO_RD_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT_MASK                                                0x00038000L
28631 //GUS_IO_WR_PRI_QUEUING
28632 #define GUS_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                              0x0
28633 #define GUS_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                              0x3
28634 #define GUS_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                              0x6
28635 #define GUS_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                              0x9
28636 #define GUS_IO_WR_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT__SHIFT                                              0xc
28637 #define GUS_IO_WR_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT__SHIFT                                              0xf
28638 #define GUS_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                                0x00000007L
28639 #define GUS_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                                0x00000038L
28640 #define GUS_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                                0x000001C0L
28641 #define GUS_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                                0x00000E00L
28642 #define GUS_IO_WR_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT_MASK                                                0x00007000L
28643 #define GUS_IO_WR_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT_MASK                                                0x00038000L
28644 //GUS_IO_RD_PRI_FIXED
28645 #define GUS_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                  0x0
28646 #define GUS_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                  0x3
28647 #define GUS_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                  0x6
28648 #define GUS_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                  0x9
28649 #define GUS_IO_RD_PRI_FIXED__GROUP4_FIXED_COEFFICIENT__SHIFT                                                  0xc
28650 #define GUS_IO_RD_PRI_FIXED__GROUP5_FIXED_COEFFICIENT__SHIFT                                                  0xf
28651 #define GUS_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                    0x00000007L
28652 #define GUS_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                    0x00000038L
28653 #define GUS_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                    0x000001C0L
28654 #define GUS_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                    0x00000E00L
28655 #define GUS_IO_RD_PRI_FIXED__GROUP4_FIXED_COEFFICIENT_MASK                                                    0x00007000L
28656 #define GUS_IO_RD_PRI_FIXED__GROUP5_FIXED_COEFFICIENT_MASK                                                    0x00038000L
28657 //GUS_IO_WR_PRI_FIXED
28658 #define GUS_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                  0x0
28659 #define GUS_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                  0x3
28660 #define GUS_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                  0x6
28661 #define GUS_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                  0x9
28662 #define GUS_IO_WR_PRI_FIXED__GROUP4_FIXED_COEFFICIENT__SHIFT                                                  0xc
28663 #define GUS_IO_WR_PRI_FIXED__GROUP5_FIXED_COEFFICIENT__SHIFT                                                  0xf
28664 #define GUS_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                    0x00000007L
28665 #define GUS_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                    0x00000038L
28666 #define GUS_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                    0x000001C0L
28667 #define GUS_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                    0x00000E00L
28668 #define GUS_IO_WR_PRI_FIXED__GROUP4_FIXED_COEFFICIENT_MASK                                                    0x00007000L
28669 #define GUS_IO_WR_PRI_FIXED__GROUP5_FIXED_COEFFICIENT_MASK                                                    0x00038000L
28670 //GUS_IO_RD_PRI_URGENCY_COEFF
28671 #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT__SHIFT                                        0x0
28672 #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT__SHIFT                                        0x3
28673 #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT__SHIFT                                        0x6
28674 #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT__SHIFT                                        0x9
28675 #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT__SHIFT                                        0xc
28676 #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT__SHIFT                                        0xf
28677 #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT_MASK                                          0x00000007L
28678 #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT_MASK                                          0x00000038L
28679 #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT_MASK                                          0x000001C0L
28680 #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT_MASK                                          0x00000E00L
28681 #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT_MASK                                          0x00007000L
28682 #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT_MASK                                          0x00038000L
28683 //GUS_IO_WR_PRI_URGENCY_COEFF
28684 #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT__SHIFT                                        0x0
28685 #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT__SHIFT                                        0x3
28686 #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT__SHIFT                                        0x6
28687 #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT__SHIFT                                        0x9
28688 #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT__SHIFT                                        0xc
28689 #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT__SHIFT                                        0xf
28690 #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT_MASK                                          0x00000007L
28691 #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT_MASK                                          0x00000038L
28692 #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT_MASK                                          0x000001C0L
28693 #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT_MASK                                          0x00000E00L
28694 #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT_MASK                                          0x00007000L
28695 #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT_MASK                                          0x00038000L
28696 //GUS_IO_RD_PRI_URGENCY_MODE
28697 #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE__SHIFT                                                0x0
28698 #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE__SHIFT                                                0x1
28699 #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE__SHIFT                                                0x2
28700 #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE__SHIFT                                                0x3
28701 #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE__SHIFT                                                0x4
28702 #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE__SHIFT                                                0x5
28703 #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE_MASK                                                  0x00000001L
28704 #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE_MASK                                                  0x00000002L
28705 #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE_MASK                                                  0x00000004L
28706 #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE_MASK                                                  0x00000008L
28707 #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE_MASK                                                  0x00000010L
28708 #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE_MASK                                                  0x00000020L
28709 //GUS_IO_WR_PRI_URGENCY_MODE
28710 #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE__SHIFT                                                0x0
28711 #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE__SHIFT                                                0x1
28712 #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE__SHIFT                                                0x2
28713 #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE__SHIFT                                                0x3
28714 #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE__SHIFT                                                0x4
28715 #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE__SHIFT                                                0x5
28716 #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE_MASK                                                  0x00000001L
28717 #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE_MASK                                                  0x00000002L
28718 #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE_MASK                                                  0x00000004L
28719 #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE_MASK                                                  0x00000008L
28720 #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE_MASK                                                  0x00000010L
28721 #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE_MASK                                                  0x00000020L
28722 //GUS_IO_RD_PRI_QUANT_PRI1
28723 #define GUS_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                     0x0
28724 #define GUS_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                     0x8
28725 #define GUS_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                     0x10
28726 #define GUS_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                     0x18
28727 #define GUS_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                       0x000000FFL
28728 #define GUS_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                       0x0000FF00L
28729 #define GUS_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                       0x00FF0000L
28730 #define GUS_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                       0xFF000000L
28731 //GUS_IO_RD_PRI_QUANT_PRI2
28732 #define GUS_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                     0x0
28733 #define GUS_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                     0x8
28734 #define GUS_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                     0x10
28735 #define GUS_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                     0x18
28736 #define GUS_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                       0x000000FFL
28737 #define GUS_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                       0x0000FF00L
28738 #define GUS_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                       0x00FF0000L
28739 #define GUS_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                       0xFF000000L
28740 //GUS_IO_RD_PRI_QUANT_PRI3
28741 #define GUS_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                     0x0
28742 #define GUS_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                     0x8
28743 #define GUS_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                     0x10
28744 #define GUS_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                     0x18
28745 #define GUS_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                       0x000000FFL
28746 #define GUS_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                       0x0000FF00L
28747 #define GUS_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                       0x00FF0000L
28748 #define GUS_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                       0xFF000000L
28749 //GUS_IO_RD_PRI_QUANT_PRI4
28750 #define GUS_IO_RD_PRI_QUANT_PRI4__GROUP0_THRESHOLD__SHIFT                                                     0x0
28751 #define GUS_IO_RD_PRI_QUANT_PRI4__GROUP1_THRESHOLD__SHIFT                                                     0x8
28752 #define GUS_IO_RD_PRI_QUANT_PRI4__GROUP2_THRESHOLD__SHIFT                                                     0x10
28753 #define GUS_IO_RD_PRI_QUANT_PRI4__GROUP3_THRESHOLD__SHIFT                                                     0x18
28754 #define GUS_IO_RD_PRI_QUANT_PRI4__GROUP0_THRESHOLD_MASK                                                       0x000000FFL
28755 #define GUS_IO_RD_PRI_QUANT_PRI4__GROUP1_THRESHOLD_MASK                                                       0x0000FF00L
28756 #define GUS_IO_RD_PRI_QUANT_PRI4__GROUP2_THRESHOLD_MASK                                                       0x00FF0000L
28757 #define GUS_IO_RD_PRI_QUANT_PRI4__GROUP3_THRESHOLD_MASK                                                       0xFF000000L
28758 //GUS_IO_WR_PRI_QUANT_PRI1
28759 #define GUS_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                     0x0
28760 #define GUS_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                     0x8
28761 #define GUS_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                     0x10
28762 #define GUS_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                     0x18
28763 #define GUS_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                       0x000000FFL
28764 #define GUS_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                       0x0000FF00L
28765 #define GUS_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                       0x00FF0000L
28766 #define GUS_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                       0xFF000000L
28767 //GUS_IO_WR_PRI_QUANT_PRI2
28768 #define GUS_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                     0x0
28769 #define GUS_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                     0x8
28770 #define GUS_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                     0x10
28771 #define GUS_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                     0x18
28772 #define GUS_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                       0x000000FFL
28773 #define GUS_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                       0x0000FF00L
28774 #define GUS_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                       0x00FF0000L
28775 #define GUS_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                       0xFF000000L
28776 //GUS_IO_WR_PRI_QUANT_PRI3
28777 #define GUS_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                     0x0
28778 #define GUS_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                     0x8
28779 #define GUS_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                     0x10
28780 #define GUS_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                     0x18
28781 #define GUS_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                       0x000000FFL
28782 #define GUS_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                       0x0000FF00L
28783 #define GUS_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                       0x00FF0000L
28784 #define GUS_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                       0xFF000000L
28785 //GUS_IO_WR_PRI_QUANT_PRI4
28786 #define GUS_IO_WR_PRI_QUANT_PRI4__GROUP0_THRESHOLD__SHIFT                                                     0x0
28787 #define GUS_IO_WR_PRI_QUANT_PRI4__GROUP1_THRESHOLD__SHIFT                                                     0x8
28788 #define GUS_IO_WR_PRI_QUANT_PRI4__GROUP2_THRESHOLD__SHIFT                                                     0x10
28789 #define GUS_IO_WR_PRI_QUANT_PRI4__GROUP3_THRESHOLD__SHIFT                                                     0x18
28790 #define GUS_IO_WR_PRI_QUANT_PRI4__GROUP0_THRESHOLD_MASK                                                       0x000000FFL
28791 #define GUS_IO_WR_PRI_QUANT_PRI4__GROUP1_THRESHOLD_MASK                                                       0x0000FF00L
28792 #define GUS_IO_WR_PRI_QUANT_PRI4__GROUP2_THRESHOLD_MASK                                                       0x00FF0000L
28793 #define GUS_IO_WR_PRI_QUANT_PRI4__GROUP3_THRESHOLD_MASK                                                       0xFF000000L
28794 //GUS_IO_RD_PRI_QUANT1_PRI1
28795 #define GUS_IO_RD_PRI_QUANT1_PRI1__GROUP4_THRESHOLD__SHIFT                                                    0x0
28796 #define GUS_IO_RD_PRI_QUANT1_PRI1__GROUP5_THRESHOLD__SHIFT                                                    0x8
28797 #define GUS_IO_RD_PRI_QUANT1_PRI1__GROUP4_THRESHOLD_MASK                                                      0x000000FFL
28798 #define GUS_IO_RD_PRI_QUANT1_PRI1__GROUP5_THRESHOLD_MASK                                                      0x0000FF00L
28799 //GUS_IO_RD_PRI_QUANT1_PRI2
28800 #define GUS_IO_RD_PRI_QUANT1_PRI2__GROUP4_THRESHOLD__SHIFT                                                    0x0
28801 #define GUS_IO_RD_PRI_QUANT1_PRI2__GROUP5_THRESHOLD__SHIFT                                                    0x8
28802 #define GUS_IO_RD_PRI_QUANT1_PRI2__GROUP4_THRESHOLD_MASK                                                      0x000000FFL
28803 #define GUS_IO_RD_PRI_QUANT1_PRI2__GROUP5_THRESHOLD_MASK                                                      0x0000FF00L
28804 //GUS_IO_RD_PRI_QUANT1_PRI3
28805 #define GUS_IO_RD_PRI_QUANT1_PRI3__GROUP4_THRESHOLD__SHIFT                                                    0x0
28806 #define GUS_IO_RD_PRI_QUANT1_PRI3__GROUP5_THRESHOLD__SHIFT                                                    0x8
28807 #define GUS_IO_RD_PRI_QUANT1_PRI3__GROUP4_THRESHOLD_MASK                                                      0x000000FFL
28808 #define GUS_IO_RD_PRI_QUANT1_PRI3__GROUP5_THRESHOLD_MASK                                                      0x0000FF00L
28809 //GUS_IO_RD_PRI_QUANT1_PRI4
28810 #define GUS_IO_RD_PRI_QUANT1_PRI4__GROUP4_THRESHOLD__SHIFT                                                    0x0
28811 #define GUS_IO_RD_PRI_QUANT1_PRI4__GROUP5_THRESHOLD__SHIFT                                                    0x8
28812 #define GUS_IO_RD_PRI_QUANT1_PRI4__GROUP4_THRESHOLD_MASK                                                      0x000000FFL
28813 #define GUS_IO_RD_PRI_QUANT1_PRI4__GROUP5_THRESHOLD_MASK                                                      0x0000FF00L
28814 //GUS_IO_WR_PRI_QUANT1_PRI1
28815 #define GUS_IO_WR_PRI_QUANT1_PRI1__GROUP4_THRESHOLD__SHIFT                                                    0x0
28816 #define GUS_IO_WR_PRI_QUANT1_PRI1__GROUP5_THRESHOLD__SHIFT                                                    0x8
28817 #define GUS_IO_WR_PRI_QUANT1_PRI1__GROUP4_THRESHOLD_MASK                                                      0x000000FFL
28818 #define GUS_IO_WR_PRI_QUANT1_PRI1__GROUP5_THRESHOLD_MASK                                                      0x0000FF00L
28819 //GUS_IO_WR_PRI_QUANT1_PRI2
28820 #define GUS_IO_WR_PRI_QUANT1_PRI2__GROUP4_THRESHOLD__SHIFT                                                    0x0
28821 #define GUS_IO_WR_PRI_QUANT1_PRI2__GROUP5_THRESHOLD__SHIFT                                                    0x8
28822 #define GUS_IO_WR_PRI_QUANT1_PRI2__GROUP4_THRESHOLD_MASK                                                      0x000000FFL
28823 #define GUS_IO_WR_PRI_QUANT1_PRI2__GROUP5_THRESHOLD_MASK                                                      0x0000FF00L
28824 //GUS_IO_WR_PRI_QUANT1_PRI3
28825 #define GUS_IO_WR_PRI_QUANT1_PRI3__GROUP4_THRESHOLD__SHIFT                                                    0x0
28826 #define GUS_IO_WR_PRI_QUANT1_PRI3__GROUP5_THRESHOLD__SHIFT                                                    0x8
28827 #define GUS_IO_WR_PRI_QUANT1_PRI3__GROUP4_THRESHOLD_MASK                                                      0x000000FFL
28828 #define GUS_IO_WR_PRI_QUANT1_PRI3__GROUP5_THRESHOLD_MASK                                                      0x0000FF00L
28829 //GUS_IO_WR_PRI_QUANT1_PRI4
28830 #define GUS_IO_WR_PRI_QUANT1_PRI4__GROUP4_THRESHOLD__SHIFT                                                    0x0
28831 #define GUS_IO_WR_PRI_QUANT1_PRI4__GROUP5_THRESHOLD__SHIFT                                                    0x8
28832 #define GUS_IO_WR_PRI_QUANT1_PRI4__GROUP4_THRESHOLD_MASK                                                      0x000000FFL
28833 #define GUS_IO_WR_PRI_QUANT1_PRI4__GROUP5_THRESHOLD_MASK                                                      0x0000FF00L
28834 //GUS_DRAM_COMBINE_FLUSH
28835 #define GUS_DRAM_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                           0x0
28836 #define GUS_DRAM_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                           0x4
28837 #define GUS_DRAM_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                           0x8
28838 #define GUS_DRAM_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                           0xc
28839 #define GUS_DRAM_COMBINE_FLUSH__GROUP4_TIMER__SHIFT                                                           0x10
28840 #define GUS_DRAM_COMBINE_FLUSH__GROUP5_TIMER__SHIFT                                                           0x14
28841 #define GUS_DRAM_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                             0x0000000FL
28842 #define GUS_DRAM_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                             0x000000F0L
28843 #define GUS_DRAM_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                             0x00000F00L
28844 #define GUS_DRAM_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                             0x0000F000L
28845 #define GUS_DRAM_COMBINE_FLUSH__GROUP4_TIMER_MASK                                                             0x000F0000L
28846 #define GUS_DRAM_COMBINE_FLUSH__GROUP5_TIMER_MASK                                                             0x00F00000L
28847 //GUS_DRAM_COMBINE_RD_WR_EN
28848 #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP0_TIMER__SHIFT                                                        0x0
28849 #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP1_TIMER__SHIFT                                                        0x2
28850 #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP2_TIMER__SHIFT                                                        0x4
28851 #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP3_TIMER__SHIFT                                                        0x6
28852 #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP4_TIMER__SHIFT                                                        0x8
28853 #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP5_TIMER__SHIFT                                                        0xa
28854 #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP0_TIMER_MASK                                                          0x00000003L
28855 #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP1_TIMER_MASK                                                          0x0000000CL
28856 #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP2_TIMER_MASK                                                          0x00000030L
28857 #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP3_TIMER_MASK                                                          0x000000C0L
28858 #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP4_TIMER_MASK                                                          0x00000300L
28859 #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP5_TIMER_MASK                                                          0x00000C00L
28860 //GUS_DRAM_PRI_AGE_RATE
28861 #define GUS_DRAM_PRI_AGE_RATE__GROUP0_AGING_RATE__SHIFT                                                       0x0
28862 #define GUS_DRAM_PRI_AGE_RATE__GROUP1_AGING_RATE__SHIFT                                                       0x3
28863 #define GUS_DRAM_PRI_AGE_RATE__GROUP2_AGING_RATE__SHIFT                                                       0x6
28864 #define GUS_DRAM_PRI_AGE_RATE__GROUP3_AGING_RATE__SHIFT                                                       0x9
28865 #define GUS_DRAM_PRI_AGE_RATE__GROUP4_AGING_RATE__SHIFT                                                       0xc
28866 #define GUS_DRAM_PRI_AGE_RATE__GROUP5_AGING_RATE__SHIFT                                                       0xf
28867 #define GUS_DRAM_PRI_AGE_RATE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
28868 #define GUS_DRAM_PRI_AGE_RATE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
28869 #define GUS_DRAM_PRI_AGE_RATE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
28870 #define GUS_DRAM_PRI_AGE_RATE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
28871 #define GUS_DRAM_PRI_AGE_RATE__GROUP4_AGING_RATE_MASK                                                         0x00007000L
28872 #define GUS_DRAM_PRI_AGE_RATE__GROUP5_AGING_RATE_MASK                                                         0x00038000L
28873 //GUS_DRAM_PRI_AGE_COEFF
28874 #define GUS_DRAM_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT__SHIFT                                                 0x0
28875 #define GUS_DRAM_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT__SHIFT                                                 0x3
28876 #define GUS_DRAM_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT__SHIFT                                                 0x6
28877 #define GUS_DRAM_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT__SHIFT                                                 0x9
28878 #define GUS_DRAM_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT__SHIFT                                                 0xc
28879 #define GUS_DRAM_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT__SHIFT                                                 0xf
28880 #define GUS_DRAM_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT_MASK                                                   0x00000007L
28881 #define GUS_DRAM_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT_MASK                                                   0x00000038L
28882 #define GUS_DRAM_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT_MASK                                                   0x000001C0L
28883 #define GUS_DRAM_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT_MASK                                                   0x00000E00L
28884 #define GUS_DRAM_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT_MASK                                                   0x00007000L
28885 #define GUS_DRAM_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT_MASK                                                   0x00038000L
28886 //GUS_DRAM_PRI_QUEUING
28887 #define GUS_DRAM_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                               0x0
28888 #define GUS_DRAM_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                               0x3
28889 #define GUS_DRAM_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                               0x6
28890 #define GUS_DRAM_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                               0x9
28891 #define GUS_DRAM_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT__SHIFT                                               0xc
28892 #define GUS_DRAM_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT__SHIFT                                               0xf
28893 #define GUS_DRAM_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                                 0x00000007L
28894 #define GUS_DRAM_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                                 0x00000038L
28895 #define GUS_DRAM_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                                 0x000001C0L
28896 #define GUS_DRAM_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                                 0x00000E00L
28897 #define GUS_DRAM_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT_MASK                                                 0x00007000L
28898 #define GUS_DRAM_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT_MASK                                                 0x00038000L
28899 //GUS_DRAM_PRI_FIXED
28900 #define GUS_DRAM_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                   0x0
28901 #define GUS_DRAM_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                   0x3
28902 #define GUS_DRAM_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                   0x6
28903 #define GUS_DRAM_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                   0x9
28904 #define GUS_DRAM_PRI_FIXED__GROUP4_FIXED_COEFFICIENT__SHIFT                                                   0xc
28905 #define GUS_DRAM_PRI_FIXED__GROUP5_FIXED_COEFFICIENT__SHIFT                                                   0xf
28906 #define GUS_DRAM_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                     0x00000007L
28907 #define GUS_DRAM_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                     0x00000038L
28908 #define GUS_DRAM_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                     0x000001C0L
28909 #define GUS_DRAM_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                     0x00000E00L
28910 #define GUS_DRAM_PRI_FIXED__GROUP4_FIXED_COEFFICIENT_MASK                                                     0x00007000L
28911 #define GUS_DRAM_PRI_FIXED__GROUP5_FIXED_COEFFICIENT_MASK                                                     0x00038000L
28912 //GUS_DRAM_PRI_URGENCY_COEFF
28913 #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT__SHIFT                                         0x0
28914 #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT__SHIFT                                         0x3
28915 #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT__SHIFT                                         0x6
28916 #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT__SHIFT                                         0x9
28917 #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT__SHIFT                                         0xc
28918 #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT__SHIFT                                         0xf
28919 #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT_MASK                                           0x00000007L
28920 #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT_MASK                                           0x00000038L
28921 #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT_MASK                                           0x000001C0L
28922 #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT_MASK                                           0x00000E00L
28923 #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT_MASK                                           0x00007000L
28924 #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT_MASK                                           0x00038000L
28925 //GUS_DRAM_PRI_URGENCY_MODE
28926 #define GUS_DRAM_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE__SHIFT                                                 0x0
28927 #define GUS_DRAM_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE__SHIFT                                                 0x1
28928 #define GUS_DRAM_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE__SHIFT                                                 0x2
28929 #define GUS_DRAM_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE__SHIFT                                                 0x3
28930 #define GUS_DRAM_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE__SHIFT                                                 0x4
28931 #define GUS_DRAM_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE__SHIFT                                                 0x5
28932 #define GUS_DRAM_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE_MASK                                                   0x00000001L
28933 #define GUS_DRAM_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE_MASK                                                   0x00000002L
28934 #define GUS_DRAM_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE_MASK                                                   0x00000004L
28935 #define GUS_DRAM_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE_MASK                                                   0x00000008L
28936 #define GUS_DRAM_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE_MASK                                                   0x00000010L
28937 #define GUS_DRAM_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE_MASK                                                   0x00000020L
28938 //GUS_DRAM_PRI_QUANT_PRI1
28939 #define GUS_DRAM_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                      0x0
28940 #define GUS_DRAM_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                      0x8
28941 #define GUS_DRAM_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                      0x10
28942 #define GUS_DRAM_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                      0x18
28943 #define GUS_DRAM_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                        0x000000FFL
28944 #define GUS_DRAM_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                        0x0000FF00L
28945 #define GUS_DRAM_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                        0x00FF0000L
28946 #define GUS_DRAM_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                        0xFF000000L
28947 //GUS_DRAM_PRI_QUANT_PRI2
28948 #define GUS_DRAM_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                      0x0
28949 #define GUS_DRAM_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                      0x8
28950 #define GUS_DRAM_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                      0x10
28951 #define GUS_DRAM_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                      0x18
28952 #define GUS_DRAM_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                        0x000000FFL
28953 #define GUS_DRAM_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                        0x0000FF00L
28954 #define GUS_DRAM_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                        0x00FF0000L
28955 #define GUS_DRAM_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                        0xFF000000L
28956 //GUS_DRAM_PRI_QUANT_PRI3
28957 #define GUS_DRAM_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                      0x0
28958 #define GUS_DRAM_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                      0x8
28959 #define GUS_DRAM_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                      0x10
28960 #define GUS_DRAM_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                      0x18
28961 #define GUS_DRAM_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                        0x000000FFL
28962 #define GUS_DRAM_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                        0x0000FF00L
28963 #define GUS_DRAM_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                        0x00FF0000L
28964 #define GUS_DRAM_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                        0xFF000000L
28965 //GUS_DRAM_PRI_QUANT_PRI4
28966 #define GUS_DRAM_PRI_QUANT_PRI4__GROUP0_THRESHOLD__SHIFT                                                      0x0
28967 #define GUS_DRAM_PRI_QUANT_PRI4__GROUP1_THRESHOLD__SHIFT                                                      0x8
28968 #define GUS_DRAM_PRI_QUANT_PRI4__GROUP2_THRESHOLD__SHIFT                                                      0x10
28969 #define GUS_DRAM_PRI_QUANT_PRI4__GROUP3_THRESHOLD__SHIFT                                                      0x18
28970 #define GUS_DRAM_PRI_QUANT_PRI4__GROUP0_THRESHOLD_MASK                                                        0x000000FFL
28971 #define GUS_DRAM_PRI_QUANT_PRI4__GROUP1_THRESHOLD_MASK                                                        0x0000FF00L
28972 #define GUS_DRAM_PRI_QUANT_PRI4__GROUP2_THRESHOLD_MASK                                                        0x00FF0000L
28973 #define GUS_DRAM_PRI_QUANT_PRI4__GROUP3_THRESHOLD_MASK                                                        0xFF000000L
28974 //GUS_DRAM_PRI_QUANT_PRI5
28975 #define GUS_DRAM_PRI_QUANT_PRI5__GROUP0_THRESHOLD__SHIFT                                                      0x0
28976 #define GUS_DRAM_PRI_QUANT_PRI5__GROUP1_THRESHOLD__SHIFT                                                      0x8
28977 #define GUS_DRAM_PRI_QUANT_PRI5__GROUP2_THRESHOLD__SHIFT                                                      0x10
28978 #define GUS_DRAM_PRI_QUANT_PRI5__GROUP3_THRESHOLD__SHIFT                                                      0x18
28979 #define GUS_DRAM_PRI_QUANT_PRI5__GROUP0_THRESHOLD_MASK                                                        0x000000FFL
28980 #define GUS_DRAM_PRI_QUANT_PRI5__GROUP1_THRESHOLD_MASK                                                        0x0000FF00L
28981 #define GUS_DRAM_PRI_QUANT_PRI5__GROUP2_THRESHOLD_MASK                                                        0x00FF0000L
28982 #define GUS_DRAM_PRI_QUANT_PRI5__GROUP3_THRESHOLD_MASK                                                        0xFF000000L
28983 //GUS_DRAM_PRI_QUANT1_PRI1
28984 #define GUS_DRAM_PRI_QUANT1_PRI1__GROUP4_THRESHOLD__SHIFT                                                     0x0
28985 #define GUS_DRAM_PRI_QUANT1_PRI1__GROUP5_THRESHOLD__SHIFT                                                     0x8
28986 #define GUS_DRAM_PRI_QUANT1_PRI1__GROUP4_THRESHOLD_MASK                                                       0x000000FFL
28987 #define GUS_DRAM_PRI_QUANT1_PRI1__GROUP5_THRESHOLD_MASK                                                       0x0000FF00L
28988 //GUS_DRAM_PRI_QUANT1_PRI2
28989 #define GUS_DRAM_PRI_QUANT1_PRI2__GROUP4_THRESHOLD__SHIFT                                                     0x0
28990 #define GUS_DRAM_PRI_QUANT1_PRI2__GROUP5_THRESHOLD__SHIFT                                                     0x8
28991 #define GUS_DRAM_PRI_QUANT1_PRI2__GROUP4_THRESHOLD_MASK                                                       0x000000FFL
28992 #define GUS_DRAM_PRI_QUANT1_PRI2__GROUP5_THRESHOLD_MASK                                                       0x0000FF00L
28993 //GUS_DRAM_PRI_QUANT1_PRI3
28994 #define GUS_DRAM_PRI_QUANT1_PRI3__GROUP4_THRESHOLD__SHIFT                                                     0x0
28995 #define GUS_DRAM_PRI_QUANT1_PRI3__GROUP5_THRESHOLD__SHIFT                                                     0x8
28996 #define GUS_DRAM_PRI_QUANT1_PRI3__GROUP4_THRESHOLD_MASK                                                       0x000000FFL
28997 #define GUS_DRAM_PRI_QUANT1_PRI3__GROUP5_THRESHOLD_MASK                                                       0x0000FF00L
28998 //GUS_DRAM_PRI_QUANT1_PRI4
28999 #define GUS_DRAM_PRI_QUANT1_PRI4__GROUP4_THRESHOLD__SHIFT                                                     0x0
29000 #define GUS_DRAM_PRI_QUANT1_PRI4__GROUP5_THRESHOLD__SHIFT                                                     0x8
29001 #define GUS_DRAM_PRI_QUANT1_PRI4__GROUP4_THRESHOLD_MASK                                                       0x000000FFL
29002 #define GUS_DRAM_PRI_QUANT1_PRI4__GROUP5_THRESHOLD_MASK                                                       0x0000FF00L
29003 //GUS_DRAM_PRI_QUANT1_PRI5
29004 #define GUS_DRAM_PRI_QUANT1_PRI5__GROUP4_THRESHOLD__SHIFT                                                     0x0
29005 #define GUS_DRAM_PRI_QUANT1_PRI5__GROUP5_THRESHOLD__SHIFT                                                     0x8
29006 #define GUS_DRAM_PRI_QUANT1_PRI5__GROUP4_THRESHOLD_MASK                                                       0x000000FFL
29007 #define GUS_DRAM_PRI_QUANT1_PRI5__GROUP5_THRESHOLD_MASK                                                       0x0000FF00L
29008 //GUS_IO_GROUP_BURST
29009 #define GUS_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT                                                                0x0
29010 #define GUS_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT                                                                0x8
29011 #define GUS_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT                                                                0x10
29012 #define GUS_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT                                                                0x18
29013 #define GUS_IO_GROUP_BURST__RD_LIMIT_LO_MASK                                                                  0x000000FFL
29014 #define GUS_IO_GROUP_BURST__RD_LIMIT_HI_MASK                                                                  0x0000FF00L
29015 #define GUS_IO_GROUP_BURST__WR_LIMIT_LO_MASK                                                                  0x00FF0000L
29016 #define GUS_IO_GROUP_BURST__WR_LIMIT_HI_MASK                                                                  0xFF000000L
29017 //GUS_DRAM_GROUP_BURST
29018 #define GUS_DRAM_GROUP_BURST__DRAM_LIMIT_LO__SHIFT                                                            0x0
29019 #define GUS_DRAM_GROUP_BURST__DRAM_LIMIT_HI__SHIFT                                                            0x8
29020 #define GUS_DRAM_GROUP_BURST__DRAM_LIMIT_LO_MASK                                                              0x000000FFL
29021 #define GUS_DRAM_GROUP_BURST__DRAM_LIMIT_HI_MASK                                                              0x0000FF00L
29022 //GUS_SDP_ARB_FINAL
29023 #define GUS_SDP_ARB_FINAL__HI_DRAM_BURST_LIMIT__SHIFT                                                         0x0
29024 #define GUS_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT                                                            0x5
29025 #define GUS_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT                                                              0xa
29026 #define GUS_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT                                                      0xf
29027 #define GUS_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT                                                           0x11
29028 #define GUS_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT                                                            0x12
29029 #define GUS_SDP_ARB_FINAL__HI_DRAM_BURST_LIMIT_MASK                                                           0x0000001FL
29030 #define GUS_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK                                                              0x000003E0L
29031 #define GUS_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK                                                                0x00007C00L
29032 #define GUS_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK                                                        0x00018000L
29033 #define GUS_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK                                                             0x00020000L
29034 #define GUS_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK                                                              0x00040000L
29035 //GUS_SDP_QOS_VC_PRIORITY
29036 #define GUS_SDP_QOS_VC_PRIORITY__VC2_IORD__SHIFT                                                              0x0
29037 #define GUS_SDP_QOS_VC_PRIORITY__VC3_IOWR__SHIFT                                                              0x4
29038 #define GUS_SDP_QOS_VC_PRIORITY__VC4_DRAM__SHIFT                                                              0x8
29039 #define GUS_SDP_QOS_VC_PRIORITY__VC4_HI_DRAM__SHIFT                                                           0xc
29040 #define GUS_SDP_QOS_VC_PRIORITY__VC2_IORD_MASK                                                                0x0000000FL
29041 #define GUS_SDP_QOS_VC_PRIORITY__VC3_IOWR_MASK                                                                0x000000F0L
29042 #define GUS_SDP_QOS_VC_PRIORITY__VC4_DRAM_MASK                                                                0x00000F00L
29043 #define GUS_SDP_QOS_VC_PRIORITY__VC4_HI_DRAM_MASK                                                             0x0000F000L
29044 //GUS_SDP_CREDITS
29045 #define GUS_SDP_CREDITS__TAG_LIMIT__SHIFT                                                                     0x0
29046 #define GUS_SDP_CREDITS__WR_RESP_CREDITS__SHIFT                                                               0x8
29047 #define GUS_SDP_CREDITS__RD_RESP_CREDITS__SHIFT                                                               0x10
29048 #define GUS_SDP_CREDITS__TAG_LIMIT_MASK                                                                       0x000000FFL
29049 #define GUS_SDP_CREDITS__WR_RESP_CREDITS_MASK                                                                 0x00007F00L
29050 #define GUS_SDP_CREDITS__RD_RESP_CREDITS_MASK                                                                 0x007F0000L
29051 //GUS_SDP_TAG_RESERVE0
29052 #define GUS_SDP_TAG_RESERVE0__VC0__SHIFT                                                                      0x0
29053 #define GUS_SDP_TAG_RESERVE0__VC1__SHIFT                                                                      0x8
29054 #define GUS_SDP_TAG_RESERVE0__VC2__SHIFT                                                                      0x10
29055 #define GUS_SDP_TAG_RESERVE0__VC3__SHIFT                                                                      0x18
29056 #define GUS_SDP_TAG_RESERVE0__VC0_MASK                                                                        0x000000FFL
29057 #define GUS_SDP_TAG_RESERVE0__VC1_MASK                                                                        0x0000FF00L
29058 #define GUS_SDP_TAG_RESERVE0__VC2_MASK                                                                        0x00FF0000L
29059 #define GUS_SDP_TAG_RESERVE0__VC3_MASK                                                                        0xFF000000L
29060 //GUS_SDP_TAG_RESERVE1
29061 #define GUS_SDP_TAG_RESERVE1__VC4__SHIFT                                                                      0x0
29062 #define GUS_SDP_TAG_RESERVE1__VC5__SHIFT                                                                      0x8
29063 #define GUS_SDP_TAG_RESERVE1__VC6__SHIFT                                                                      0x10
29064 #define GUS_SDP_TAG_RESERVE1__VC7__SHIFT                                                                      0x18
29065 #define GUS_SDP_TAG_RESERVE1__VC4_MASK                                                                        0x000000FFL
29066 #define GUS_SDP_TAG_RESERVE1__VC5_MASK                                                                        0x0000FF00L
29067 #define GUS_SDP_TAG_RESERVE1__VC6_MASK                                                                        0x00FF0000L
29068 #define GUS_SDP_TAG_RESERVE1__VC7_MASK                                                                        0xFF000000L
29069 //GUS_SDP_VCC_RESERVE0
29070 #define GUS_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT                                                              0x0
29071 #define GUS_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT                                                              0x6
29072 #define GUS_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT                                                              0xc
29073 #define GUS_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT                                                              0x12
29074 #define GUS_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT                                                              0x18
29075 #define GUS_SDP_VCC_RESERVE0__VC0_CREDITS_MASK                                                                0x0000003FL
29076 #define GUS_SDP_VCC_RESERVE0__VC1_CREDITS_MASK                                                                0x00000FC0L
29077 #define GUS_SDP_VCC_RESERVE0__VC2_CREDITS_MASK                                                                0x0003F000L
29078 #define GUS_SDP_VCC_RESERVE0__VC3_CREDITS_MASK                                                                0x00FC0000L
29079 #define GUS_SDP_VCC_RESERVE0__VC4_CREDITS_MASK                                                                0x3F000000L
29080 //GUS_SDP_VCC_RESERVE1
29081 #define GUS_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT                                                              0x0
29082 #define GUS_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT                                                              0x6
29083 #define GUS_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT                                                              0xc
29084 #define GUS_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                          0x1f
29085 #define GUS_SDP_VCC_RESERVE1__VC5_CREDITS_MASK                                                                0x0000003FL
29086 #define GUS_SDP_VCC_RESERVE1__VC6_CREDITS_MASK                                                                0x00000FC0L
29087 #define GUS_SDP_VCC_RESERVE1__VC7_CREDITS_MASK                                                                0x0003F000L
29088 #define GUS_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK                                                            0x80000000L
29089 //GUS_SDP_VCD_RESERVE0
29090 #define GUS_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT                                                              0x0
29091 #define GUS_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT                                                              0x6
29092 #define GUS_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT                                                              0xc
29093 #define GUS_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT                                                              0x12
29094 #define GUS_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT                                                              0x18
29095 #define GUS_SDP_VCD_RESERVE0__VC0_CREDITS_MASK                                                                0x0000003FL
29096 #define GUS_SDP_VCD_RESERVE0__VC1_CREDITS_MASK                                                                0x00000FC0L
29097 #define GUS_SDP_VCD_RESERVE0__VC2_CREDITS_MASK                                                                0x0003F000L
29098 #define GUS_SDP_VCD_RESERVE0__VC3_CREDITS_MASK                                                                0x00FC0000L
29099 #define GUS_SDP_VCD_RESERVE0__VC4_CREDITS_MASK                                                                0x3F000000L
29100 //GUS_SDP_VCD_RESERVE1
29101 #define GUS_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT                                                              0x0
29102 #define GUS_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT                                                              0x6
29103 #define GUS_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT                                                              0xc
29104 #define GUS_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                          0x1f
29105 #define GUS_SDP_VCD_RESERVE1__VC5_CREDITS_MASK                                                                0x0000003FL
29106 #define GUS_SDP_VCD_RESERVE1__VC6_CREDITS_MASK                                                                0x00000FC0L
29107 #define GUS_SDP_VCD_RESERVE1__VC7_CREDITS_MASK                                                                0x0003F000L
29108 #define GUS_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK                                                            0x80000000L
29109 //GUS_SDP_REQ_CNTL
29110 #define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT                                                    0x0
29111 #define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT                                                   0x1
29112 #define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT                                                  0x2
29113 #define GUS_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT                                                      0x3
29114 #define GUS_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT                                                            0x4
29115 #define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK                                                      0x00000001L
29116 #define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK                                                     0x00000002L
29117 #define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK                                                    0x00000004L
29118 #define GUS_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK                                                        0x00000008L
29119 #define GUS_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK                                                              0x00000010L
29120 //GUS_MISC
29121 #define GUS_MISC__RELATIVE_PRI_IN_DRAM_ARB__SHIFT                                                             0x0
29122 #define GUS_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT                                                            0x1
29123 #define GUS_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT                                                            0x2
29124 #define GUS_MISC__EARLY_SDP_ORIGDATA__SHIFT                                                                   0x3
29125 #define GUS_MISC__LINKMGR_DYNAMIC_MODE__SHIFT                                                                 0x4
29126 #define GUS_MISC__LINKMGR_HALT_THRESHOLD__SHIFT                                                               0x6
29127 #define GUS_MISC__LINKMGR_RECONNECT_DELAY__SHIFT                                                              0x8
29128 #define GUS_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT                                                               0xa
29129 #define GUS_MISC__SEND0_IOWR_ONLY__SHIFT                                                                      0xf
29130 #define GUS_MISC__RELATIVE_PRI_IN_DRAM_ARB_MASK                                                               0x00000001L
29131 #define GUS_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK                                                              0x00000002L
29132 #define GUS_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK                                                              0x00000004L
29133 #define GUS_MISC__EARLY_SDP_ORIGDATA_MASK                                                                     0x00000008L
29134 #define GUS_MISC__LINKMGR_DYNAMIC_MODE_MASK                                                                   0x00000030L
29135 #define GUS_MISC__LINKMGR_HALT_THRESHOLD_MASK                                                                 0x000000C0L
29136 #define GUS_MISC__LINKMGR_RECONNECT_DELAY_MASK                                                                0x00000300L
29137 #define GUS_MISC__LINKMGR_IDLE_THRESHOLD_MASK                                                                 0x00007C00L
29138 #define GUS_MISC__SEND0_IOWR_ONLY_MASK                                                                        0x00008000L
29139 //GUS_LATENCY_SAMPLING
29140 #define GUS_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT                                                            0x0
29141 #define GUS_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT                                                            0x1
29142 #define GUS_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT                                                              0x2
29143 #define GUS_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT                                                              0x3
29144 #define GUS_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT                                                            0x4
29145 #define GUS_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT                                                            0x5
29146 #define GUS_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT                                                           0x6
29147 #define GUS_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT                                                           0x7
29148 #define GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT                                                      0x8
29149 #define GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT                                                      0x9
29150 #define GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT                                                    0xa
29151 #define GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT                                                    0xb
29152 #define GUS_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT                                                              0xc
29153 #define GUS_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT                                                              0x14
29154 #define GUS_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK                                                              0x00000001L
29155 #define GUS_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK                                                              0x00000002L
29156 #define GUS_LATENCY_SAMPLING__SAMPLER0_IO_MASK                                                                0x00000004L
29157 #define GUS_LATENCY_SAMPLING__SAMPLER1_IO_MASK                                                                0x00000008L
29158 #define GUS_LATENCY_SAMPLING__SAMPLER0_READ_MASK                                                              0x00000010L
29159 #define GUS_LATENCY_SAMPLING__SAMPLER1_READ_MASK                                                              0x00000020L
29160 #define GUS_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK                                                             0x00000040L
29161 #define GUS_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK                                                             0x00000080L
29162 #define GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK                                                        0x00000100L
29163 #define GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK                                                        0x00000200L
29164 #define GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK                                                      0x00000400L
29165 #define GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK                                                      0x00000800L
29166 #define GUS_LATENCY_SAMPLING__SAMPLER0_VC_MASK                                                                0x000FF000L
29167 #define GUS_LATENCY_SAMPLING__SAMPLER1_VC_MASK                                                                0x0FF00000L
29168 //GUS_PERFCOUNTER_LO
29169 #define GUS_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                                 0x0
29170 #define GUS_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                   0xFFFFFFFFL
29171 //GUS_PERFCOUNTER_HI
29172 #define GUS_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                                 0x0
29173 #define GUS_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                              0x10
29174 #define GUS_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                   0x0000FFFFL
29175 #define GUS_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                                0xFFFF0000L
29176 //GUS_PERFCOUNTER0_CFG
29177 #define GUS_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                                 0x0
29178 #define GUS_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                             0x8
29179 #define GUS_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                                0x18
29180 #define GUS_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                   0x1c
29181 #define GUS_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                    0x1d
29182 #define GUS_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                   0x000000FFL
29183 #define GUS_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                               0x0000FF00L
29184 #define GUS_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                  0x0F000000L
29185 #define GUS_PERFCOUNTER0_CFG__ENABLE_MASK                                                                     0x10000000L
29186 #define GUS_PERFCOUNTER0_CFG__CLEAR_MASK                                                                      0x20000000L
29187 //GUS_PERFCOUNTER1_CFG
29188 #define GUS_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                                 0x0
29189 #define GUS_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                             0x8
29190 #define GUS_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                                0x18
29191 #define GUS_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                   0x1c
29192 #define GUS_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                    0x1d
29193 #define GUS_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                   0x000000FFL
29194 #define GUS_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                               0x0000FF00L
29195 #define GUS_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                  0x0F000000L
29196 #define GUS_PERFCOUNTER1_CFG__ENABLE_MASK                                                                     0x10000000L
29197 #define GUS_PERFCOUNTER1_CFG__CLEAR_MASK                                                                      0x20000000L
29198 //GUS_PERFCOUNTER_RSLT_CNTL
29199 #define GUS_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                                 0x0
29200 #define GUS_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                       0x8
29201 #define GUS_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                        0x10
29202 #define GUS_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                          0x18
29203 #define GUS_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                           0x19
29204 #define GUS_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                                0x1a
29205 #define GUS_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                   0x0000000FL
29206 #define GUS_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                         0x0000FF00L
29207 #define GUS_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                          0x00FF0000L
29208 #define GUS_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                            0x01000000L
29209 #define GUS_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                             0x02000000L
29210 #define GUS_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                  0x04000000L
29211 //GUS_ERR_STATUS
29212 #define GUS_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT                                                               0x0
29213 #define GUS_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT                                                               0x4
29214 #define GUS_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT                                                           0x8
29215 #define GUS_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT                                                     0xa
29216 #define GUS_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT                                                             0xb
29217 #define GUS_ERR_STATUS__BUSY_ON_ERROR__SHIFT                                                                  0xc
29218 #define GUS_ERR_STATUS__FUE_FLAG__SHIFT                                                                       0xd
29219 #define GUS_ERR_STATUS__SDP_RDRSP_STATUS_MASK                                                                 0x0000000FL
29220 #define GUS_ERR_STATUS__SDP_WRRSP_STATUS_MASK                                                                 0x000000F0L
29221 #define GUS_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK                                                             0x00000300L
29222 #define GUS_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK                                                       0x00000400L
29223 #define GUS_ERR_STATUS__CLEAR_ERROR_STATUS_MASK                                                               0x00000800L
29224 #define GUS_ERR_STATUS__BUSY_ON_ERROR_MASK                                                                    0x00001000L
29225 #define GUS_ERR_STATUS__FUE_FLAG_MASK                                                                         0x00002000L
29226 //GUS_MISC2
29227 #define GUS_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT                                                             0x0
29228 #define GUS_MISC2__CH_L1_RO_MASK__SHIFT                                                                       0x1
29229 #define GUS_MISC2__SA0_L1_RO_MASK__SHIFT                                                                      0x2
29230 #define GUS_MISC2__SA1_L1_RO_MASK__SHIFT                                                                      0x3
29231 #define GUS_MISC2__SA2_L1_RO_MASK__SHIFT                                                                      0x4
29232 #define GUS_MISC2__SA3_L1_RO_MASK__SHIFT                                                                      0x5
29233 #define GUS_MISC2__CH_L1_PERF_MASK__SHIFT                                                                     0x6
29234 #define GUS_MISC2__SA0_L1_PERF_MASK__SHIFT                                                                    0x7
29235 #define GUS_MISC2__SA1_L1_PERF_MASK__SHIFT                                                                    0x8
29236 #define GUS_MISC2__SA2_L1_PERF_MASK__SHIFT                                                                    0x9
29237 #define GUS_MISC2__SA3_L1_PERF_MASK__SHIFT                                                                    0xa
29238 #define GUS_MISC2__FP_ATOMICS_ENABLE__SHIFT                                                                   0xb
29239 #define GUS_MISC2__L1_RET_CLKEN__SHIFT                                                                        0xc
29240 #define GUS_MISC2__FGCLKEN_HIGH__SHIFT                                                                        0xd
29241 #define GUS_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK                                                               0x00000001L
29242 #define GUS_MISC2__CH_L1_RO_MASK_MASK                                                                         0x00000002L
29243 #define GUS_MISC2__SA0_L1_RO_MASK_MASK                                                                        0x00000004L
29244 #define GUS_MISC2__SA1_L1_RO_MASK_MASK                                                                        0x00000008L
29245 #define GUS_MISC2__SA2_L1_RO_MASK_MASK                                                                        0x00000010L
29246 #define GUS_MISC2__SA3_L1_RO_MASK_MASK                                                                        0x00000020L
29247 #define GUS_MISC2__CH_L1_PERF_MASK_MASK                                                                       0x00000040L
29248 #define GUS_MISC2__SA0_L1_PERF_MASK_MASK                                                                      0x00000080L
29249 #define GUS_MISC2__SA1_L1_PERF_MASK_MASK                                                                      0x00000100L
29250 #define GUS_MISC2__SA2_L1_PERF_MASK_MASK                                                                      0x00000200L
29251 #define GUS_MISC2__SA3_L1_PERF_MASK_MASK                                                                      0x00000400L
29252 #define GUS_MISC2__FP_ATOMICS_ENABLE_MASK                                                                     0x00000800L
29253 #define GUS_MISC2__L1_RET_CLKEN_MASK                                                                          0x00001000L
29254 #define GUS_MISC2__FGCLKEN_HIGH_MASK                                                                          0x00002000L
29255 //GUS_SDP_BACKDOOR_CMDCREDITS0
29256 #define GUS_SDP_BACKDOOR_CMDCREDITS0__CREDITS_RECEIVED__SHIFT                                                 0x0
29257 #define GUS_SDP_BACKDOOR_CMDCREDITS0__CREDITS_RECEIVED_MASK                                                   0xFFFFFFFFL
29258 //GUS_SDP_BACKDOOR_CMDCREDITS1
29259 #define GUS_SDP_BACKDOOR_CMDCREDITS1__CREDITS_RECEIVED__SHIFT                                                 0x0
29260 #define GUS_SDP_BACKDOOR_CMDCREDITS1__CREDITS_RECEIVED_MASK                                                   0x7FFFFFFFL
29261 //GUS_SDP_BACKDOOR_DATACREDITS0
29262 #define GUS_SDP_BACKDOOR_DATACREDITS0__CREDITS_RECEIVED__SHIFT                                                0x0
29263 #define GUS_SDP_BACKDOOR_DATACREDITS0__CREDITS_RECEIVED_MASK                                                  0xFFFFFFFFL
29264 //GUS_SDP_BACKDOOR_DATACREDITS1
29265 #define GUS_SDP_BACKDOOR_DATACREDITS1__CREDITS_RECEIVED__SHIFT                                                0x0
29266 #define GUS_SDP_BACKDOOR_DATACREDITS1__CREDITS_RECEIVED_MASK                                                  0x7FFFFFFFL
29267 //GUS_SDP_BACKDOOR_MISCCREDITS
29268 #define GUS_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED__SHIFT                                           0x0
29269 #define GUS_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED__SHIFT                                           0x8
29270 #define GUS_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED_MASK                                             0x000000FFL
29271 #define GUS_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED_MASK                                             0x0000FF00L
29272 //GUS_SDP_ENABLE
29273 #define GUS_SDP_ENABLE__ENABLE__SHIFT                                                                         0x0
29274 #define GUS_SDP_ENABLE__ENABLE_MASK                                                                           0x00000001L
29275 //GUS_L1_CH0_CMD_IN
29276 #define GUS_L1_CH0_CMD_IN__COUNT__SHIFT                                                                       0x0
29277 #define GUS_L1_CH0_CMD_IN__COUNT_MASK                                                                         0xFFFFFFFFL
29278 //GUS_L1_CH0_CMD_OUT
29279 #define GUS_L1_CH0_CMD_OUT__COUNT__SHIFT                                                                      0x0
29280 #define GUS_L1_CH0_CMD_OUT__COUNT_MASK                                                                        0xFFFFFFFFL
29281 //GUS_L1_CH0_DATA_IN
29282 #define GUS_L1_CH0_DATA_IN__COUNT__SHIFT                                                                      0x0
29283 #define GUS_L1_CH0_DATA_IN__COUNT_MASK                                                                        0xFFFFFFFFL
29284 //GUS_L1_CH0_DATA_OUT
29285 #define GUS_L1_CH0_DATA_OUT__COUNT__SHIFT                                                                     0x0
29286 #define GUS_L1_CH0_DATA_OUT__COUNT_MASK                                                                       0xFFFFFFFFL
29287 //GUS_L1_CH1_CMD_IN
29288 #define GUS_L1_CH1_CMD_IN__COUNT__SHIFT                                                                       0x0
29289 #define GUS_L1_CH1_CMD_IN__COUNT_MASK                                                                         0xFFFFFFFFL
29290 //GUS_L1_CH1_CMD_OUT
29291 #define GUS_L1_CH1_CMD_OUT__COUNT__SHIFT                                                                      0x0
29292 #define GUS_L1_CH1_CMD_OUT__COUNT_MASK                                                                        0xFFFFFFFFL
29293 //GUS_L1_CH1_DATA_IN
29294 #define GUS_L1_CH1_DATA_IN__COUNT__SHIFT                                                                      0x0
29295 #define GUS_L1_CH1_DATA_IN__COUNT_MASK                                                                        0xFFFFFFFFL
29296 //GUS_L1_CH1_DATA_OUT
29297 #define GUS_L1_CH1_DATA_OUT__COUNT__SHIFT                                                                     0x0
29298 #define GUS_L1_CH1_DATA_OUT__COUNT_MASK                                                                       0xFFFFFFFFL
29299 //GUS_L1_SA0_CMD_IN
29300 #define GUS_L1_SA0_CMD_IN__COUNT__SHIFT                                                                       0x0
29301 #define GUS_L1_SA0_CMD_IN__COUNT_MASK                                                                         0xFFFFFFFFL
29302 //GUS_L1_SA0_CMD_OUT
29303 #define GUS_L1_SA0_CMD_OUT__COUNT__SHIFT                                                                      0x0
29304 #define GUS_L1_SA0_CMD_OUT__COUNT_MASK                                                                        0xFFFFFFFFL
29305 //GUS_L1_SA0_DATA_IN
29306 #define GUS_L1_SA0_DATA_IN__COUNT__SHIFT                                                                      0x0
29307 #define GUS_L1_SA0_DATA_IN__COUNT_MASK                                                                        0xFFFFFFFFL
29308 //GUS_L1_SA0_DATA_OUT
29309 #define GUS_L1_SA0_DATA_OUT__COUNT__SHIFT                                                                     0x0
29310 #define GUS_L1_SA0_DATA_OUT__COUNT_MASK                                                                       0xFFFFFFFFL
29311 //GUS_L1_SA0_DATA_U_IN
29312 #define GUS_L1_SA0_DATA_U_IN__COUNT__SHIFT                                                                    0x0
29313 #define GUS_L1_SA0_DATA_U_IN__COUNT_MASK                                                                      0xFFFFFFFFL
29314 //GUS_L1_SA0_DATA_U_OUT
29315 #define GUS_L1_SA0_DATA_U_OUT__COUNT__SHIFT                                                                   0x0
29316 #define GUS_L1_SA0_DATA_U_OUT__COUNT_MASK                                                                     0xFFFFFFFFL
29317 //GUS_L1_SA1_CMD_IN
29318 #define GUS_L1_SA1_CMD_IN__COUNT__SHIFT                                                                       0x0
29319 #define GUS_L1_SA1_CMD_IN__COUNT_MASK                                                                         0xFFFFFFFFL
29320 //GUS_L1_SA1_CMD_OUT
29321 #define GUS_L1_SA1_CMD_OUT__COUNT__SHIFT                                                                      0x0
29322 #define GUS_L1_SA1_CMD_OUT__COUNT_MASK                                                                        0xFFFFFFFFL
29323 //GUS_L1_SA1_DATA_IN
29324 #define GUS_L1_SA1_DATA_IN__COUNT__SHIFT                                                                      0x0
29325 #define GUS_L1_SA1_DATA_IN__COUNT_MASK                                                                        0xFFFFFFFFL
29326 //GUS_L1_SA1_DATA_OUT
29327 #define GUS_L1_SA1_DATA_OUT__COUNT__SHIFT                                                                     0x0
29328 #define GUS_L1_SA1_DATA_OUT__COUNT_MASK                                                                       0xFFFFFFFFL
29329 //GUS_L1_SA1_DATA_U_IN
29330 #define GUS_L1_SA1_DATA_U_IN__COUNT__SHIFT                                                                    0x0
29331 #define GUS_L1_SA1_DATA_U_IN__COUNT_MASK                                                                      0xFFFFFFFFL
29332 //GUS_L1_SA1_DATA_U_OUT
29333 #define GUS_L1_SA1_DATA_U_OUT__COUNT__SHIFT                                                                   0x0
29334 #define GUS_L1_SA1_DATA_U_OUT__COUNT_MASK                                                                     0xFFFFFFFFL
29335 //GUS_L1_SA2_CMD_IN
29336 #define GUS_L1_SA2_CMD_IN__COUNT__SHIFT                                                                       0x0
29337 #define GUS_L1_SA2_CMD_IN__COUNT_MASK                                                                         0xFFFFFFFFL
29338 //GUS_L1_SA2_CMD_OUT
29339 #define GUS_L1_SA2_CMD_OUT__COUNT__SHIFT                                                                      0x0
29340 #define GUS_L1_SA2_CMD_OUT__COUNT_MASK                                                                        0xFFFFFFFFL
29341 //GUS_L1_SA2_DATA_IN
29342 #define GUS_L1_SA2_DATA_IN__COUNT__SHIFT                                                                      0x0
29343 #define GUS_L1_SA2_DATA_IN__COUNT_MASK                                                                        0xFFFFFFFFL
29344 //GUS_L1_SA2_DATA_OUT
29345 #define GUS_L1_SA2_DATA_OUT__COUNT__SHIFT                                                                     0x0
29346 #define GUS_L1_SA2_DATA_OUT__COUNT_MASK                                                                       0xFFFFFFFFL
29347 //GUS_L1_SA2_DATA_U_IN
29348 #define GUS_L1_SA2_DATA_U_IN__COUNT__SHIFT                                                                    0x0
29349 #define GUS_L1_SA2_DATA_U_IN__COUNT_MASK                                                                      0xFFFFFFFFL
29350 //GUS_L1_SA2_DATA_U_OUT
29351 #define GUS_L1_SA2_DATA_U_OUT__COUNT__SHIFT                                                                   0x0
29352 #define GUS_L1_SA2_DATA_U_OUT__COUNT_MASK                                                                     0xFFFFFFFFL
29353 //GUS_L1_SA3_CMD_IN
29354 #define GUS_L1_SA3_CMD_IN__COUNT__SHIFT                                                                       0x0
29355 #define GUS_L1_SA3_CMD_IN__COUNT_MASK                                                                         0xFFFFFFFFL
29356 //GUS_L1_SA3_CMD_OUT
29357 #define GUS_L1_SA3_CMD_OUT__COUNT__SHIFT                                                                      0x0
29358 #define GUS_L1_SA3_CMD_OUT__COUNT_MASK                                                                        0xFFFFFFFFL
29359 //GUS_L1_SA3_DATA_IN
29360 #define GUS_L1_SA3_DATA_IN__COUNT__SHIFT                                                                      0x0
29361 #define GUS_L1_SA3_DATA_IN__COUNT_MASK                                                                        0xFFFFFFFFL
29362 //GUS_L1_SA3_DATA_OUT
29363 #define GUS_L1_SA3_DATA_OUT__COUNT__SHIFT                                                                     0x0
29364 #define GUS_L1_SA3_DATA_OUT__COUNT_MASK                                                                       0xFFFFFFFFL
29365 //GUS_L1_SA3_DATA_U_IN
29366 #define GUS_L1_SA3_DATA_U_IN__COUNT__SHIFT                                                                    0x0
29367 #define GUS_L1_SA3_DATA_U_IN__COUNT_MASK                                                                      0xFFFFFFFFL
29368 //GUS_L1_SA3_DATA_U_OUT
29369 #define GUS_L1_SA3_DATA_U_OUT__COUNT__SHIFT                                                                   0x0
29370 #define GUS_L1_SA3_DATA_U_OUT__COUNT_MASK                                                                     0xFFFFFFFFL
29371 //GUS_MISC3
29372 //GUS_WRRSP_FIFO_CNTL
29373 #define GUS_WRRSP_FIFO_CNTL__THRESHOLD__SHIFT                                                                 0x0
29374 #define GUS_WRRSP_FIFO_CNTL__THRESHOLD_MASK                                                                   0x0000003FL
29375 
29376 
29377 // addressBlock: gc_gl1dec
29378 //GL1_ARB_CTRL
29379 #define GL1_ARB_CTRL__NUM_MEM_PIPES__SHIFT                                                                    0x0
29380 #define GL1_ARB_CTRL__NUM_MEM_PIPES_MASK                                                                      0x00000007L
29381 //GL1_DRAM_BURST_MASK
29382 #define GL1_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK__SHIFT                                                      0x0
29383 #define GL1_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK_MASK                                                        0x000000FFL
29384 //GL1_ARB_STATUS
29385 #define GL1_ARB_STATUS__REQ_ARB_BUSY__SHIFT                                                                   0x0
29386 #define GL1_ARB_STATUS__RET_ARB_BUSY__SHIFT                                                                   0x1
29387 #define GL1_ARB_STATUS__REQ_ARB_BUSY_MASK                                                                     0x00000001L
29388 #define GL1_ARB_STATUS__RET_ARB_BUSY_MASK                                                                     0x00000002L
29389 //GL1_DRAM_BURST_CTRL
29390 #define GL1_DRAM_BURST_CTRL__MAX_DRAM_BURST__SHIFT                                                            0x0
29391 #define GL1_DRAM_BURST_CTRL__BURST_DISABLE__SHIFT                                                             0x3
29392 #define GL1_DRAM_BURST_CTRL__GATHER_64B_MEMORY_BURST_DISABLE__SHIFT                                           0x4
29393 #define GL1_DRAM_BURST_CTRL__GATHER_64B_IO_BURST_DISABLE__SHIFT                                               0x5
29394 #define GL1_DRAM_BURST_CTRL__MAX_DRAM_BURST_MASK                                                              0x00000007L
29395 #define GL1_DRAM_BURST_CTRL__BURST_DISABLE_MASK                                                               0x00000008L
29396 #define GL1_DRAM_BURST_CTRL__GATHER_64B_MEMORY_BURST_DISABLE_MASK                                             0x00000010L
29397 #define GL1_DRAM_BURST_CTRL__GATHER_64B_IO_BURST_DISABLE_MASK                                                 0x00000020L
29398 //GL1_PIPE_STEER
29399 #define GL1_PIPE_STEER__PIPE0__SHIFT                                                                          0x0
29400 #define GL1_PIPE_STEER__PIPE1__SHIFT                                                                          0x2
29401 #define GL1_PIPE_STEER__PIPE2__SHIFT                                                                          0x4
29402 #define GL1_PIPE_STEER__PIPE3__SHIFT                                                                          0x6
29403 #define GL1_PIPE_STEER__PIPE4__SHIFT                                                                          0x8
29404 #define GL1_PIPE_STEER__PIPE5__SHIFT                                                                          0xa
29405 #define GL1_PIPE_STEER__PIPE6__SHIFT                                                                          0xc
29406 #define GL1_PIPE_STEER__PIPE7__SHIFT                                                                          0xe
29407 #define GL1_PIPE_STEER__PIPE8__SHIFT                                                                          0x10
29408 #define GL1_PIPE_STEER__PIPE9__SHIFT                                                                          0x12
29409 #define GL1_PIPE_STEER__PIPE10__SHIFT                                                                         0x14
29410 #define GL1_PIPE_STEER__PIPE11__SHIFT                                                                         0x16
29411 #define GL1_PIPE_STEER__PIPE12__SHIFT                                                                         0x18
29412 #define GL1_PIPE_STEER__PIPE13__SHIFT                                                                         0x1a
29413 #define GL1_PIPE_STEER__PIPE14__SHIFT                                                                         0x1c
29414 #define GL1_PIPE_STEER__PIPE15__SHIFT                                                                         0x1e
29415 #define GL1_PIPE_STEER__PIPE0_MASK                                                                            0x00000003L
29416 #define GL1_PIPE_STEER__PIPE1_MASK                                                                            0x0000000CL
29417 #define GL1_PIPE_STEER__PIPE2_MASK                                                                            0x00000030L
29418 #define GL1_PIPE_STEER__PIPE3_MASK                                                                            0x000000C0L
29419 #define GL1_PIPE_STEER__PIPE4_MASK                                                                            0x00000300L
29420 #define GL1_PIPE_STEER__PIPE5_MASK                                                                            0x00000C00L
29421 #define GL1_PIPE_STEER__PIPE6_MASK                                                                            0x00003000L
29422 #define GL1_PIPE_STEER__PIPE7_MASK                                                                            0x0000C000L
29423 #define GL1_PIPE_STEER__PIPE8_MASK                                                                            0x00030000L
29424 #define GL1_PIPE_STEER__PIPE9_MASK                                                                            0x000C0000L
29425 #define GL1_PIPE_STEER__PIPE10_MASK                                                                           0x00300000L
29426 #define GL1_PIPE_STEER__PIPE11_MASK                                                                           0x00C00000L
29427 #define GL1_PIPE_STEER__PIPE12_MASK                                                                           0x03000000L
29428 #define GL1_PIPE_STEER__PIPE13_MASK                                                                           0x0C000000L
29429 #define GL1_PIPE_STEER__PIPE14_MASK                                                                           0x30000000L
29430 #define GL1_PIPE_STEER__PIPE15_MASK                                                                           0xC0000000L
29431 //GL1C_CTRL
29432 #define GL1C_CTRL__FORCE_MISS__SHIFT                                                                          0x0
29433 #define GL1C_CTRL__FORCE_HIT__SHIFT                                                                           0x1
29434 #define GL1C_CTRL__NOFILL_32B__SHIFT                                                                          0x2
29435 #define GL1C_CTRL__NOFILL_64B__SHIFT                                                                          0x3
29436 #define GL1C_CTRL__LATENCY_FIFO_SIZE__SHIFT                                                                   0x4
29437 #define GL1C_CTRL__ACK_QUEUE_DISABLE__SHIFT                                                                   0x8
29438 #define GL1C_CTRL__RMI_META_READ_MISS_QUEUE_DISABLE__SHIFT                                                    0x9
29439 #define GL1C_CTRL__HIT_QUEUE_DISABLE__SHIFT                                                                   0xa
29440 #define GL1C_CTRL__FORCE_MISS_MASK                                                                            0x00000001L
29441 #define GL1C_CTRL__FORCE_HIT_MASK                                                                             0x00000002L
29442 #define GL1C_CTRL__NOFILL_32B_MASK                                                                            0x00000004L
29443 #define GL1C_CTRL__NOFILL_64B_MASK                                                                            0x00000008L
29444 #define GL1C_CTRL__LATENCY_FIFO_SIZE_MASK                                                                     0x000000F0L
29445 #define GL1C_CTRL__ACK_QUEUE_DISABLE_MASK                                                                     0x00000100L
29446 #define GL1C_CTRL__RMI_META_READ_MISS_QUEUE_DISABLE_MASK                                                      0x00000200L
29447 #define GL1C_CTRL__HIT_QUEUE_DISABLE_MASK                                                                     0x00000400L
29448 //GL1C_STATUS
29449 #define GL1C_STATUS__INPUT_BUFFER_VC0_FIFO_FULL__SHIFT                                                        0x0
29450 #define GL1C_STATUS__OUTPUT_FIFOS_BUSY__SHIFT                                                                 0x1
29451 #define GL1C_STATUS__SRC_DATA_FIFO_VC0_FULL__SHIFT                                                            0x2
29452 #define GL1C_STATUS__GL2_REQ_VC0_STALL__SHIFT                                                                 0x3
29453 #define GL1C_STATUS__GL2_DATA_VC0_STALL__SHIFT                                                                0x4
29454 #define GL1C_STATUS__GL2_REQ_VC1_STALL__SHIFT                                                                 0x5
29455 #define GL1C_STATUS__GL2_DATA_VC1_STALL__SHIFT                                                                0x6
29456 #define GL1C_STATUS__INPUT_BUFFER_VC0_BUSY__SHIFT                                                             0x7
29457 #define GL1C_STATUS__SRC_DATA_FIFO_VC0_BUSY__SHIFT                                                            0x8
29458 #define GL1C_STATUS__GL2_RH_BUSY__SHIFT                                                                       0x9
29459 #define GL1C_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT                                                           0xa
29460 #define GL1C_STATUS__LATENCY_FIFO_FULL_STALL__SHIFT                                                           0x14
29461 #define GL1C_STATUS__TAG_STALL__SHIFT                                                                         0x15
29462 #define GL1C_STATUS__TAG_BUSY__SHIFT                                                                          0x16
29463 #define GL1C_STATUS__TAG_ACK_STALL__SHIFT                                                                     0x17
29464 #define GL1C_STATUS__TAG_GCR_INV_STALL__SHIFT                                                                 0x18
29465 #define GL1C_STATUS__TAG_NO_AVAILABLE_LINE_TO_EVICT_STALL__SHIFT                                              0x19
29466 #define GL1C_STATUS__TAG_EVICT__SHIFT                                                                         0x1a
29467 #define GL1C_STATUS__TAG_REQUEST_STATE_OPERATION__SHIFT                                                       0x1b
29468 #define GL1C_STATUS__TRACKER_LAST_SET_MATCHES_CURRENT_SET__SHIFT                                              0x1f
29469 #define GL1C_STATUS__INPUT_BUFFER_VC0_FIFO_FULL_MASK                                                          0x00000001L
29470 #define GL1C_STATUS__OUTPUT_FIFOS_BUSY_MASK                                                                   0x00000002L
29471 #define GL1C_STATUS__SRC_DATA_FIFO_VC0_FULL_MASK                                                              0x00000004L
29472 #define GL1C_STATUS__GL2_REQ_VC0_STALL_MASK                                                                   0x00000008L
29473 #define GL1C_STATUS__GL2_DATA_VC0_STALL_MASK                                                                  0x00000010L
29474 #define GL1C_STATUS__GL2_REQ_VC1_STALL_MASK                                                                   0x00000020L
29475 #define GL1C_STATUS__GL2_DATA_VC1_STALL_MASK                                                                  0x00000040L
29476 #define GL1C_STATUS__INPUT_BUFFER_VC0_BUSY_MASK                                                               0x00000080L
29477 #define GL1C_STATUS__SRC_DATA_FIFO_VC0_BUSY_MASK                                                              0x00000100L
29478 #define GL1C_STATUS__GL2_RH_BUSY_MASK                                                                         0x00000200L
29479 #define GL1C_STATUS__NUM_REQ_PENDING_FROM_L2_MASK                                                             0x000FFC00L
29480 #define GL1C_STATUS__LATENCY_FIFO_FULL_STALL_MASK                                                             0x00100000L
29481 #define GL1C_STATUS__TAG_STALL_MASK                                                                           0x00200000L
29482 #define GL1C_STATUS__TAG_BUSY_MASK                                                                            0x00400000L
29483 #define GL1C_STATUS__TAG_ACK_STALL_MASK                                                                       0x00800000L
29484 #define GL1C_STATUS__TAG_GCR_INV_STALL_MASK                                                                   0x01000000L
29485 #define GL1C_STATUS__TAG_NO_AVAILABLE_LINE_TO_EVICT_STALL_MASK                                                0x02000000L
29486 #define GL1C_STATUS__TAG_EVICT_MASK                                                                           0x04000000L
29487 #define GL1C_STATUS__TAG_REQUEST_STATE_OPERATION_MASK                                                         0x78000000L
29488 #define GL1C_STATUS__TRACKER_LAST_SET_MATCHES_CURRENT_SET_MASK                                                0x80000000L
29489 
29490 
29491 // addressBlock: gc_chdec
29492 //CH_ARB_CTRL
29493 #define CH_ARB_CTRL__NUM_MEM_PIPES__SHIFT                                                                     0x0
29494 #define CH_ARB_CTRL__UC_IO_WR_PATH__SHIFT                                                                     0x3
29495 #define CH_ARB_CTRL__NUM_MEM_PIPES_MASK                                                                       0x00000007L
29496 #define CH_ARB_CTRL__UC_IO_WR_PATH_MASK                                                                       0x00000008L
29497 //CH_DRAM_BURST_MASK
29498 #define CH_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK__SHIFT                                                       0x0
29499 #define CH_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK_MASK                                                         0x000000FFL
29500 //CH_ARB_STATUS
29501 #define CH_ARB_STATUS__REQ_ARB_BUSY__SHIFT                                                                    0x0
29502 #define CH_ARB_STATUS__RET_ARB_BUSY__SHIFT                                                                    0x1
29503 #define CH_ARB_STATUS__REQ_ARB_BUSY_MASK                                                                      0x00000001L
29504 #define CH_ARB_STATUS__RET_ARB_BUSY_MASK                                                                      0x00000002L
29505 //CH_DRAM_BURST_CTRL
29506 #define CH_DRAM_BURST_CTRL__MAX_DRAM_BURST__SHIFT                                                             0x0
29507 #define CH_DRAM_BURST_CTRL__BURST_DISABLE__SHIFT                                                              0x3
29508 #define CH_DRAM_BURST_CTRL__GATHER_64B_MEMORY_BURST_DISABLE__SHIFT                                            0x4
29509 #define CH_DRAM_BURST_CTRL__GATHER_64B_IO_BURST_DISABLE__SHIFT                                                0x5
29510 #define CH_DRAM_BURST_CTRL__MAX_DRAM_BURST_MASK                                                               0x00000007L
29511 #define CH_DRAM_BURST_CTRL__BURST_DISABLE_MASK                                                                0x00000008L
29512 #define CH_DRAM_BURST_CTRL__GATHER_64B_MEMORY_BURST_DISABLE_MASK                                              0x00000010L
29513 #define CH_DRAM_BURST_CTRL__GATHER_64B_IO_BURST_DISABLE_MASK                                                  0x00000020L
29514 //CH_PIPE_STEER
29515 #define CH_PIPE_STEER__PIPE0__SHIFT                                                                           0x0
29516 #define CH_PIPE_STEER__PIPE1__SHIFT                                                                           0x2
29517 #define CH_PIPE_STEER__PIPE2__SHIFT                                                                           0x4
29518 #define CH_PIPE_STEER__PIPE3__SHIFT                                                                           0x6
29519 #define CH_PIPE_STEER__PIPE4__SHIFT                                                                           0x8
29520 #define CH_PIPE_STEER__PIPE5__SHIFT                                                                           0xa
29521 #define CH_PIPE_STEER__PIPE6__SHIFT                                                                           0xc
29522 #define CH_PIPE_STEER__PIPE7__SHIFT                                                                           0xe
29523 #define CH_PIPE_STEER__PIPE8__SHIFT                                                                           0x10
29524 #define CH_PIPE_STEER__PIPE9__SHIFT                                                                           0x12
29525 #define CH_PIPE_STEER__PIPE10__SHIFT                                                                          0x14
29526 #define CH_PIPE_STEER__PIPE11__SHIFT                                                                          0x16
29527 #define CH_PIPE_STEER__PIPE12__SHIFT                                                                          0x18
29528 #define CH_PIPE_STEER__PIPE13__SHIFT                                                                          0x1a
29529 #define CH_PIPE_STEER__PIPE14__SHIFT                                                                          0x1c
29530 #define CH_PIPE_STEER__PIPE15__SHIFT                                                                          0x1e
29531 #define CH_PIPE_STEER__PIPE0_MASK                                                                             0x00000003L
29532 #define CH_PIPE_STEER__PIPE1_MASK                                                                             0x0000000CL
29533 #define CH_PIPE_STEER__PIPE2_MASK                                                                             0x00000030L
29534 #define CH_PIPE_STEER__PIPE3_MASK                                                                             0x000000C0L
29535 #define CH_PIPE_STEER__PIPE4_MASK                                                                             0x00000300L
29536 #define CH_PIPE_STEER__PIPE5_MASK                                                                             0x00000C00L
29537 #define CH_PIPE_STEER__PIPE6_MASK                                                                             0x00003000L
29538 #define CH_PIPE_STEER__PIPE7_MASK                                                                             0x0000C000L
29539 #define CH_PIPE_STEER__PIPE8_MASK                                                                             0x00030000L
29540 #define CH_PIPE_STEER__PIPE9_MASK                                                                             0x000C0000L
29541 #define CH_PIPE_STEER__PIPE10_MASK                                                                            0x00300000L
29542 #define CH_PIPE_STEER__PIPE11_MASK                                                                            0x00C00000L
29543 #define CH_PIPE_STEER__PIPE12_MASK                                                                            0x03000000L
29544 #define CH_PIPE_STEER__PIPE13_MASK                                                                            0x0C000000L
29545 #define CH_PIPE_STEER__PIPE14_MASK                                                                            0x30000000L
29546 #define CH_PIPE_STEER__PIPE15_MASK                                                                            0xC0000000L
29547 //CH_VC5_ENABLE
29548 #define CH_VC5_ENABLE__UTCL2_VC5_ENABLE__SHIFT                                                                0x1
29549 #define CH_VC5_ENABLE__UTCL2_VC5_ENABLE_MASK                                                                  0x00000002L
29550 //CHC_CTRL
29551 #define CHC_CTRL__BUFFER_DEPTH_MAX__SHIFT                                                                     0x0
29552 #define CHC_CTRL__BUFFER_DEPTH_MAX_MASK                                                                       0x0000000FL
29553 //CHC_STATUS
29554 #define CHC_STATUS__INPUT_BUFFER_VC0_FIFO_FULL__SHIFT                                                         0x0
29555 #define CHC_STATUS__OUTPUT_FIFOS_BUSY__SHIFT                                                                  0x1
29556 #define CHC_STATUS__SRC_DATA_FIFO_VC0_FULL__SHIFT                                                             0x2
29557 #define CHC_STATUS__GL2_REQ_VC0_STALL__SHIFT                                                                  0x3
29558 #define CHC_STATUS__GL2_DATA_VC0_STALL__SHIFT                                                                 0x4
29559 #define CHC_STATUS__GL2_REQ_VC1_STALL__SHIFT                                                                  0x5
29560 #define CHC_STATUS__GL2_DATA_VC1_STALL__SHIFT                                                                 0x6
29561 #define CHC_STATUS__INPUT_BUFFER_VC0_BUSY__SHIFT                                                              0x7
29562 #define CHC_STATUS__SRC_DATA_FIFO_VC0_BUSY__SHIFT                                                             0x8
29563 #define CHC_STATUS__GL2_RH_BUSY__SHIFT                                                                        0x9
29564 #define CHC_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT                                                            0xa
29565 #define CHC_STATUS__VIRTUAL_FIFO_FULL_STALL__SHIFT                                                            0x14
29566 #define CHC_STATUS__REQUEST_TRACKER_BUFFER_STALL__SHIFT                                                       0x15
29567 #define CHC_STATUS__REQUEST_TRACKER_BUSY__SHIFT                                                               0x16
29568 #define CHC_STATUS__BUFFER_FULL__SHIFT                                                                        0x17
29569 #define CHC_STATUS__INPUT_BUFFER_VC0_FIFO_FULL_MASK                                                           0x00000001L
29570 #define CHC_STATUS__OUTPUT_FIFOS_BUSY_MASK                                                                    0x00000002L
29571 #define CHC_STATUS__SRC_DATA_FIFO_VC0_FULL_MASK                                                               0x00000004L
29572 #define CHC_STATUS__GL2_REQ_VC0_STALL_MASK                                                                    0x00000008L
29573 #define CHC_STATUS__GL2_DATA_VC0_STALL_MASK                                                                   0x00000010L
29574 #define CHC_STATUS__GL2_REQ_VC1_STALL_MASK                                                                    0x00000020L
29575 #define CHC_STATUS__GL2_DATA_VC1_STALL_MASK                                                                   0x00000040L
29576 #define CHC_STATUS__INPUT_BUFFER_VC0_BUSY_MASK                                                                0x00000080L
29577 #define CHC_STATUS__SRC_DATA_FIFO_VC0_BUSY_MASK                                                               0x00000100L
29578 #define CHC_STATUS__GL2_RH_BUSY_MASK                                                                          0x00000200L
29579 #define CHC_STATUS__NUM_REQ_PENDING_FROM_L2_MASK                                                              0x000FFC00L
29580 #define CHC_STATUS__VIRTUAL_FIFO_FULL_STALL_MASK                                                              0x00100000L
29581 #define CHC_STATUS__REQUEST_TRACKER_BUFFER_STALL_MASK                                                         0x00200000L
29582 #define CHC_STATUS__REQUEST_TRACKER_BUSY_MASK                                                                 0x00400000L
29583 #define CHC_STATUS__BUFFER_FULL_MASK                                                                          0x00800000L
29584 //CHCG_CTRL
29585 #define CHCG_CTRL__BUFFER_DEPTH_MAX__SHIFT                                                                    0x0
29586 #define CHCG_CTRL__VC0_BUFFER_DEPTH_MAX__SHIFT                                                                0x4
29587 #define CHCG_CTRL__BUFFER_DEPTH_MAX_MASK                                                                      0x0000000FL
29588 #define CHCG_CTRL__VC0_BUFFER_DEPTH_MAX_MASK                                                                  0x000000F0L
29589 //CHCG_STATUS
29590 #define CHCG_STATUS__INPUT_BUFFER_VC0_FIFO_FULL__SHIFT                                                        0x0
29591 #define CHCG_STATUS__OUTPUT_FIFOS_BUSY__SHIFT                                                                 0x1
29592 #define CHCG_STATUS__SRC_DATA_FIFO_VC0_FULL__SHIFT                                                            0x2
29593 #define CHCG_STATUS__GL2_REQ_VC0_STALL__SHIFT                                                                 0x3
29594 #define CHCG_STATUS__GL2_DATA_VC0_STALL__SHIFT                                                                0x4
29595 #define CHCG_STATUS__GL2_REQ_VC1_STALL__SHIFT                                                                 0x5
29596 #define CHCG_STATUS__GL2_DATA_VC1_STALL__SHIFT                                                                0x6
29597 #define CHCG_STATUS__INPUT_BUFFER_VC0_BUSY__SHIFT                                                             0x7
29598 #define CHCG_STATUS__SRC_DATA_FIFO_VC0_BUSY__SHIFT                                                            0x8
29599 #define CHCG_STATUS__GL2_RH_BUSY__SHIFT                                                                       0x9
29600 #define CHCG_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT                                                           0xa
29601 #define CHCG_STATUS__VIRTUAL_FIFO_FULL_STALL__SHIFT                                                           0x14
29602 #define CHCG_STATUS__REQUEST_TRACKER_BUFFER_STALL__SHIFT                                                      0x15
29603 #define CHCG_STATUS__REQUEST_TRACKER_BUSY__SHIFT                                                              0x16
29604 #define CHCG_STATUS__BUFFER_FULL__SHIFT                                                                       0x17
29605 #define CHCG_STATUS__INPUT_BUFFER_VC1_BUSY__SHIFT                                                             0x18
29606 #define CHCG_STATUS__SRC_DATA_FIFO_VC1_BUSY__SHIFT                                                            0x19
29607 #define CHCG_STATUS__INPUT_BUFFER_VC1_FIFO_FULL__SHIFT                                                        0x1a
29608 #define CHCG_STATUS__SRC_DATA_FIFO_VC1_FULL__SHIFT                                                            0x1b
29609 #define CHCG_STATUS__INPUT_BUFFER_VC0_FIFO_FULL_MASK                                                          0x00000001L
29610 #define CHCG_STATUS__OUTPUT_FIFOS_BUSY_MASK                                                                   0x00000002L
29611 #define CHCG_STATUS__SRC_DATA_FIFO_VC0_FULL_MASK                                                              0x00000004L
29612 #define CHCG_STATUS__GL2_REQ_VC0_STALL_MASK                                                                   0x00000008L
29613 #define CHCG_STATUS__GL2_DATA_VC0_STALL_MASK                                                                  0x00000010L
29614 #define CHCG_STATUS__GL2_REQ_VC1_STALL_MASK                                                                   0x00000020L
29615 #define CHCG_STATUS__GL2_DATA_VC1_STALL_MASK                                                                  0x00000040L
29616 #define CHCG_STATUS__INPUT_BUFFER_VC0_BUSY_MASK                                                               0x00000080L
29617 #define CHCG_STATUS__SRC_DATA_FIFO_VC0_BUSY_MASK                                                              0x00000100L
29618 #define CHCG_STATUS__GL2_RH_BUSY_MASK                                                                         0x00000200L
29619 #define CHCG_STATUS__NUM_REQ_PENDING_FROM_L2_MASK                                                             0x000FFC00L
29620 #define CHCG_STATUS__VIRTUAL_FIFO_FULL_STALL_MASK                                                             0x00100000L
29621 #define CHCG_STATUS__REQUEST_TRACKER_BUFFER_STALL_MASK                                                        0x00200000L
29622 #define CHCG_STATUS__REQUEST_TRACKER_BUSY_MASK                                                                0x00400000L
29623 #define CHCG_STATUS__BUFFER_FULL_MASK                                                                         0x00800000L
29624 #define CHCG_STATUS__INPUT_BUFFER_VC1_BUSY_MASK                                                               0x01000000L
29625 #define CHCG_STATUS__SRC_DATA_FIFO_VC1_BUSY_MASK                                                              0x02000000L
29626 #define CHCG_STATUS__INPUT_BUFFER_VC1_FIFO_FULL_MASK                                                          0x04000000L
29627 #define CHCG_STATUS__SRC_DATA_FIFO_VC1_FULL_MASK                                                              0x08000000L
29628 
29629 
29630 // addressBlock: gc_gl2dec
29631 //GL2C_CTRL
29632 #define GL2C_CTRL__CACHE_SIZE__SHIFT                                                                          0x0
29633 #define GL2C_CTRL__RATE__SHIFT                                                                                0x2
29634 #define GL2C_CTRL__WRITEBACK_MARGIN__SHIFT                                                                    0x4
29635 #define GL2C_CTRL__METADATA_LATENCY_FIFO_SIZE__SHIFT                                                          0x8
29636 #define GL2C_CTRL__SRC_FIFO_SIZE__SHIFT                                                                       0xc
29637 #define GL2C_CTRL__LATENCY_FIFO_SIZE__SHIFT                                                                   0x10
29638 #define GL2C_CTRL__METADATA_TO_HI_PRIORITY__SHIFT                                                             0x14
29639 #define GL2C_CTRL__LINEAR_SET_HASH__SHIFT                                                                     0x15
29640 #define GL2C_CTRL__FORCE_HIT_QUEUE_POP__SHIFT                                                                 0x16
29641 #define GL2C_CTRL__MDC_SIZE__SHIFT                                                                            0x18
29642 #define GL2C_CTRL__METADATA_TO_HIT_QUEUE__SHIFT                                                               0x1a
29643 #define GL2C_CTRL__IGNORE_FULLY_WRITTEN__SHIFT                                                                0x1b
29644 #define GL2C_CTRL__MDC_SIDEBAND_FIFO_SIZE__SHIFT                                                              0x1c
29645 #define GL2C_CTRL__CACHE_SIZE_MASK                                                                            0x00000003L
29646 #define GL2C_CTRL__RATE_MASK                                                                                  0x0000000CL
29647 #define GL2C_CTRL__WRITEBACK_MARGIN_MASK                                                                      0x000000F0L
29648 #define GL2C_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK                                                            0x00000F00L
29649 #define GL2C_CTRL__SRC_FIFO_SIZE_MASK                                                                         0x0000F000L
29650 #define GL2C_CTRL__LATENCY_FIFO_SIZE_MASK                                                                     0x000F0000L
29651 #define GL2C_CTRL__METADATA_TO_HI_PRIORITY_MASK                                                               0x00100000L
29652 #define GL2C_CTRL__LINEAR_SET_HASH_MASK                                                                       0x00200000L
29653 #define GL2C_CTRL__FORCE_HIT_QUEUE_POP_MASK                                                                   0x00C00000L
29654 #define GL2C_CTRL__MDC_SIZE_MASK                                                                              0x03000000L
29655 #define GL2C_CTRL__METADATA_TO_HIT_QUEUE_MASK                                                                 0x04000000L
29656 #define GL2C_CTRL__IGNORE_FULLY_WRITTEN_MASK                                                                  0x08000000L
29657 #define GL2C_CTRL__MDC_SIDEBAND_FIFO_SIZE_MASK                                                                0xF0000000L
29658 //GL2C_CTRL2
29659 #define GL2C_CTRL2__PROBE_FIFO_SIZE__SHIFT                                                                    0x0
29660 #define GL2C_CTRL2__ADDR_MATCH_DISABLE__SHIFT                                                                 0x4
29661 #define GL2C_CTRL2__FILL_SIZE_32__SHIFT                                                                       0x5
29662 #define GL2C_CTRL2__RB_TO_HI_PRIORITY__SHIFT                                                                  0x6
29663 #define GL2C_CTRL2__HIT_UNDER_MISS_DISABLE__SHIFT                                                             0x7
29664 #define GL2C_CTRL2__RO_DISABLE__SHIFT                                                                         0x8
29665 #define GL2C_CTRL2__FORCE_MDC_INV__SHIFT                                                                      0x9
29666 #define GL2C_CTRL2__GCR_ARB_CTRL__SHIFT                                                                       0xa
29667 #define GL2C_CTRL2__GCR_ALL_SET__SHIFT                                                                        0xd
29668 #define GL2C_CTRL2__MDC_PF_BLOCK__SHIFT                                                                       0xe
29669 #define GL2C_CTRL2__MDC_PF_MAX_SIZE__SHIFT                                                                    0x10
29670 #define GL2C_CTRL2__FILL_SIZE_64__SHIFT                                                                       0x11
29671 #define GL2C_CTRL2__USE_EA_EARLYWRRET_ON_WRITEBACK__SHIFT                                                     0x12
29672 #define GL2C_CTRL2__WRITEBACK_ALL_WAIT_FOR_ALL_EA_WRITE_COMPLETE__SHIFT                                       0x13
29673 #define GL2C_CTRL2__METADATA_VOLATILE_EN__SHIFT                                                               0x14
29674 #define GL2C_CTRL2__RB_VOLATILE_EN__SHIFT                                                                     0x15
29675 #define GL2C_CTRL2__PROBE_UNSHARED_EN__SHIFT                                                                  0x16
29676 #define GL2C_CTRL2__MAX_MIN_CTRL__SHIFT                                                                       0x17
29677 #define GL2C_CTRL2__MDC_PF_LINEAR_METADATA__SHIFT                                                             0x19
29678 #define GL2C_CTRL2__MDC_UC_TO_C_RO_EN__SHIFT                                                                  0x1a
29679 #define GL2C_CTRL2__MDC_PF_MIN_PAGE_SIZE__SHIFT                                                               0x1b
29680 #define GL2C_CTRL2__MDC_PF_DISABLE__SHIFT                                                                     0x1d
29681 #define GL2C_CTRL2__PROBE_FIFO_SIZE_MASK                                                                      0x0000000FL
29682 #define GL2C_CTRL2__ADDR_MATCH_DISABLE_MASK                                                                   0x00000010L
29683 #define GL2C_CTRL2__FILL_SIZE_32_MASK                                                                         0x00000020L
29684 #define GL2C_CTRL2__RB_TO_HI_PRIORITY_MASK                                                                    0x00000040L
29685 #define GL2C_CTRL2__HIT_UNDER_MISS_DISABLE_MASK                                                               0x00000080L
29686 #define GL2C_CTRL2__RO_DISABLE_MASK                                                                           0x00000100L
29687 #define GL2C_CTRL2__FORCE_MDC_INV_MASK                                                                        0x00000200L
29688 #define GL2C_CTRL2__GCR_ARB_CTRL_MASK                                                                         0x00001C00L
29689 #define GL2C_CTRL2__GCR_ALL_SET_MASK                                                                          0x00002000L
29690 #define GL2C_CTRL2__MDC_PF_BLOCK_MASK                                                                         0x0000C000L
29691 #define GL2C_CTRL2__MDC_PF_MAX_SIZE_MASK                                                                      0x00010000L
29692 #define GL2C_CTRL2__FILL_SIZE_64_MASK                                                                         0x00020000L
29693 #define GL2C_CTRL2__USE_EA_EARLYWRRET_ON_WRITEBACK_MASK                                                       0x00040000L
29694 #define GL2C_CTRL2__WRITEBACK_ALL_WAIT_FOR_ALL_EA_WRITE_COMPLETE_MASK                                         0x00080000L
29695 #define GL2C_CTRL2__METADATA_VOLATILE_EN_MASK                                                                 0x00100000L
29696 #define GL2C_CTRL2__RB_VOLATILE_EN_MASK                                                                       0x00200000L
29697 #define GL2C_CTRL2__PROBE_UNSHARED_EN_MASK                                                                    0x00400000L
29698 #define GL2C_CTRL2__MAX_MIN_CTRL_MASK                                                                         0x01800000L
29699 #define GL2C_CTRL2__MDC_PF_LINEAR_METADATA_MASK                                                               0x02000000L
29700 #define GL2C_CTRL2__MDC_UC_TO_C_RO_EN_MASK                                                                    0x04000000L
29701 #define GL2C_CTRL2__MDC_PF_MIN_PAGE_SIZE_MASK                                                                 0x18000000L
29702 #define GL2C_CTRL2__MDC_PF_DISABLE_MASK                                                                       0xE0000000L
29703 //GL2C_STATUS
29704 #define GL2C_STATUS__NONCACHEABLE_FLOAT_ATOMIC__SHIFT                                                         0x0
29705 #define GL2C_STATUS__BC_COMPRESSED_WRITE_ATOMIC__SHIFT                                                        0x1
29706 #define GL2C_STATUS__COMPRESSED_GEN1_INVALID_SIZE__SHIFT                                                      0x2
29707 #define GL2C_STATUS__COMPRESSED_GEN0__SHIFT                                                                   0x3
29708 #define GL2C_STATUS__NONCACHEABLE_FLOAT_ATOMIC_MASK                                                           0x00000001L
29709 #define GL2C_STATUS__BC_COMPRESSED_WRITE_ATOMIC_MASK                                                          0x00000002L
29710 #define GL2C_STATUS__COMPRESSED_GEN1_INVALID_SIZE_MASK                                                        0x00000004L
29711 #define GL2C_STATUS__COMPRESSED_GEN0_MASK                                                                     0x00000008L
29712 //GL2C_ADDR_MATCH_MASK
29713 #define GL2C_ADDR_MATCH_MASK__ADDR_MASK__SHIFT                                                                0x0
29714 #define GL2C_ADDR_MATCH_MASK__ADDR_MASK_MASK                                                                  0xFFFFFFFFL
29715 //GL2C_ADDR_MATCH_SIZE
29716 #define GL2C_ADDR_MATCH_SIZE__MAX_COUNT__SHIFT                                                                0x0
29717 #define GL2C_ADDR_MATCH_SIZE__MAX_COUNT_MASK                                                                  0x00000007L
29718 //GL2C_WBINVL2
29719 #define GL2C_WBINVL2__DONE__SHIFT                                                                             0x4
29720 #define GL2C_WBINVL2__DONE_MASK                                                                               0x00000010L
29721 //GL2C_SOFT_RESET
29722 #define GL2C_SOFT_RESET__HALT_FOR_RESET__SHIFT                                                                0x0
29723 #define GL2C_SOFT_RESET__HALT_FOR_RESET_MASK                                                                  0x00000001L
29724 //GL2C_CM_CTRL0
29725 #define GL2C_CM_CTRL0__HASH_MASK__SHIFT                                                                       0x0
29726 #define GL2C_CM_CTRL0__HASH_MASK_MASK                                                                         0xFFFFFFFFL
29727 //GL2C_CM_CTRL1
29728 #define GL2C_CM_CTRL1__HASH_MASK__SHIFT                                                                       0x0
29729 #define GL2C_CM_CTRL1__BURST_TIMER__SHIFT                                                                     0x8
29730 #define GL2C_CM_CTRL1__RVF_SIZE__SHIFT                                                                        0x10
29731 #define GL2C_CM_CTRL1__WRITE_COH_MODE__SHIFT                                                                  0x17
29732 #define GL2C_CM_CTRL1__MDC_ARB_MODE__SHIFT                                                                    0x19
29733 #define GL2C_CM_CTRL1__READ_REQ_ONLY__SHIFT                                                                   0x1a
29734 #define GL2C_CM_CTRL1__COMP_TO_CONSTANT_EN__SHIFT                                                             0x1b
29735 #define GL2C_CM_CTRL1__COMP_TO_SINGLE_EN__SHIFT                                                               0x1c
29736 #define GL2C_CM_CTRL1__BURST_MODE__SHIFT                                                                      0x1d
29737 #define GL2C_CM_CTRL1__UNCOMP_READBACK_FILTER__SHIFT                                                          0x1e
29738 #define GL2C_CM_CTRL1__WAIT_ATOMIC_RECOMP_WRITE__SHIFT                                                        0x1f
29739 #define GL2C_CM_CTRL1__HASH_MASK_MASK                                                                         0x0000000FL
29740 #define GL2C_CM_CTRL1__BURST_TIMER_MASK                                                                       0x0000FF00L
29741 #define GL2C_CM_CTRL1__RVF_SIZE_MASK                                                                          0x000F0000L
29742 #define GL2C_CM_CTRL1__WRITE_COH_MODE_MASK                                                                    0x01800000L
29743 #define GL2C_CM_CTRL1__MDC_ARB_MODE_MASK                                                                      0x02000000L
29744 #define GL2C_CM_CTRL1__READ_REQ_ONLY_MASK                                                                     0x04000000L
29745 #define GL2C_CM_CTRL1__COMP_TO_CONSTANT_EN_MASK                                                               0x08000000L
29746 #define GL2C_CM_CTRL1__COMP_TO_SINGLE_EN_MASK                                                                 0x10000000L
29747 #define GL2C_CM_CTRL1__BURST_MODE_MASK                                                                        0x20000000L
29748 #define GL2C_CM_CTRL1__UNCOMP_READBACK_FILTER_MASK                                                            0x40000000L
29749 #define GL2C_CM_CTRL1__WAIT_ATOMIC_RECOMP_WRITE_MASK                                                          0x80000000L
29750 //GL2C_CM_STALL
29751 #define GL2C_CM_STALL__QUEUE__SHIFT                                                                           0x0
29752 #define GL2C_CM_STALL__QUEUE_MASK                                                                             0xFFFFFFFFL
29753 //GL2C_MDC_PF_FLAG_CTRL
29754 #define GL2C_MDC_PF_FLAG_CTRL__TIMER__SHIFT                                                                   0x0
29755 #define GL2C_MDC_PF_FLAG_CTRL__TIMER_MASK                                                                     0xFFFFFFFFL
29756 //GL2C_CM_CTRL2
29757 #define GL2C_CM_CTRL2__READ_BURST_TIMER__SHIFT                                                                0x0
29758 #define GL2C_CM_CTRL2__READ_BURST_TIMER_MASK                                                                  0x000000FFL
29759 //GL2C_CTRL3
29760 #define GL2C_CTRL3__METADATA_MTYPE_COHERENCY__SHIFT                                                           0x0
29761 #define GL2C_CTRL3__MDC_PF_COLOR_USE_REQ_METADATA__SHIFT                                                      0x2
29762 #define GL2C_CTRL3__METADATA_NOFILL__SHIFT                                                                    0x3
29763 #define GL2C_CTRL3__METADATA_NEXT_CL_PREFETCH__SHIFT                                                          0x4
29764 #define GL2C_CTRL3__COMPRESSED_ATOMICS_AVOID_EA_READ__SHIFT                                                   0x5
29765 #define GL2C_CTRL3__HTILE_TO_HI_PRIORITY__SHIFT                                                               0x6
29766 #define GL2C_CTRL3__UNCACHED_WRITE_ATOMIC_TO_UC_WRITE__SHIFT                                                  0x7
29767 #define GL2C_CTRL3__IO_CHANNEL_ENABLE__SHIFT                                                                  0x8
29768 #define GL2C_CTRL3__FMASK_TO_HI_PRIORITY__SHIFT                                                               0x9
29769 #define GL2C_CTRL3__DCC_CMASK_TO_HI_PRIORITY__SHIFT                                                           0xa
29770 #define GL2C_CTRL3__BANK_LINEAR_HASH_ENABLE__SHIFT                                                            0xb
29771 #define GL2C_CTRL3__COMP_TO_CONST_CAM_CHECK_ENABLE__SHIFT                                                     0xc
29772 #define GL2C_CTRL3__FGCG_OVERRIDE__SHIFT                                                                      0xf
29773 #define GL2C_CTRL3__SCRATCH__SHIFT                                                                            0x10
29774 #define GL2C_CTRL3__METADATA_MTYPE_COHERENCY_MASK                                                             0x00000003L
29775 #define GL2C_CTRL3__MDC_PF_COLOR_USE_REQ_METADATA_MASK                                                        0x00000004L
29776 #define GL2C_CTRL3__METADATA_NOFILL_MASK                                                                      0x00000008L
29777 #define GL2C_CTRL3__METADATA_NEXT_CL_PREFETCH_MASK                                                            0x00000010L
29778 #define GL2C_CTRL3__COMPRESSED_ATOMICS_AVOID_EA_READ_MASK                                                     0x00000020L
29779 #define GL2C_CTRL3__HTILE_TO_HI_PRIORITY_MASK                                                                 0x00000040L
29780 #define GL2C_CTRL3__UNCACHED_WRITE_ATOMIC_TO_UC_WRITE_MASK                                                    0x00000080L
29781 #define GL2C_CTRL3__IO_CHANNEL_ENABLE_MASK                                                                    0x00000100L
29782 #define GL2C_CTRL3__FMASK_TO_HI_PRIORITY_MASK                                                                 0x00000200L
29783 #define GL2C_CTRL3__DCC_CMASK_TO_HI_PRIORITY_MASK                                                             0x00000400L
29784 #define GL2C_CTRL3__BANK_LINEAR_HASH_ENABLE_MASK                                                              0x00000800L
29785 #define GL2C_CTRL3__COMP_TO_CONST_CAM_CHECK_ENABLE_MASK                                                       0x00001000L
29786 #define GL2C_CTRL3__FGCG_OVERRIDE_MASK                                                                        0x00008000L
29787 #define GL2C_CTRL3__SCRATCH_MASK                                                                              0xFFFF0000L
29788 //GL2C_LB_CTR_CTRL
29789 #define GL2C_LB_CTR_CTRL__START__SHIFT                                                                        0x0
29790 #define GL2C_LB_CTR_CTRL__LOAD__SHIFT                                                                         0x1
29791 #define GL2C_LB_CTR_CTRL__CLEAR__SHIFT                                                                        0x2
29792 #define GL2C_LB_CTR_CTRL__PERF_CNTR_EN_OVERRIDE__SHIFT                                                        0x1f
29793 #define GL2C_LB_CTR_CTRL__START_MASK                                                                          0x00000001L
29794 #define GL2C_LB_CTR_CTRL__LOAD_MASK                                                                           0x00000002L
29795 #define GL2C_LB_CTR_CTRL__CLEAR_MASK                                                                          0x00000004L
29796 #define GL2C_LB_CTR_CTRL__PERF_CNTR_EN_OVERRIDE_MASK                                                          0x80000000L
29797 //GL2C_LB_DATA0
29798 #define GL2C_LB_DATA0__DATA__SHIFT                                                                            0x0
29799 #define GL2C_LB_DATA0__DATA_MASK                                                                              0xFFFFFFFFL
29800 //GL2C_LB_DATA1
29801 #define GL2C_LB_DATA1__DATA__SHIFT                                                                            0x0
29802 #define GL2C_LB_DATA1__DATA_MASK                                                                              0xFFFFFFFFL
29803 //GL2C_LB_DATA2
29804 #define GL2C_LB_DATA2__DATA__SHIFT                                                                            0x0
29805 #define GL2C_LB_DATA2__DATA_MASK                                                                              0xFFFFFFFFL
29806 //GL2C_LB_DATA3
29807 #define GL2C_LB_DATA3__DATA__SHIFT                                                                            0x0
29808 #define GL2C_LB_DATA3__DATA_MASK                                                                              0xFFFFFFFFL
29809 //GL2C_LB_CTR_SEL0
29810 #define GL2C_LB_CTR_SEL0__SEL0__SHIFT                                                                         0x0
29811 #define GL2C_LB_CTR_SEL0__DIV0__SHIFT                                                                         0xf
29812 #define GL2C_LB_CTR_SEL0__SEL1__SHIFT                                                                         0x10
29813 #define GL2C_LB_CTR_SEL0__DIV1__SHIFT                                                                         0x1f
29814 #define GL2C_LB_CTR_SEL0__SEL0_MASK                                                                           0x000000FFL
29815 #define GL2C_LB_CTR_SEL0__DIV0_MASK                                                                           0x00008000L
29816 #define GL2C_LB_CTR_SEL0__SEL1_MASK                                                                           0x00FF0000L
29817 #define GL2C_LB_CTR_SEL0__DIV1_MASK                                                                           0x80000000L
29818 //GL2C_LB_CTR_SEL1
29819 #define GL2C_LB_CTR_SEL1__SEL2__SHIFT                                                                         0x0
29820 #define GL2C_LB_CTR_SEL1__DIV2__SHIFT                                                                         0xf
29821 #define GL2C_LB_CTR_SEL1__SEL3__SHIFT                                                                         0x10
29822 #define GL2C_LB_CTR_SEL1__DIV3__SHIFT                                                                         0x1f
29823 #define GL2C_LB_CTR_SEL1__SEL2_MASK                                                                           0x000000FFL
29824 #define GL2C_LB_CTR_SEL1__DIV2_MASK                                                                           0x00008000L
29825 #define GL2C_LB_CTR_SEL1__SEL3_MASK                                                                           0x00FF0000L
29826 #define GL2C_LB_CTR_SEL1__DIV3_MASK                                                                           0x80000000L
29827 //GL2A_ADDR_MATCH_CTRL
29828 #define GL2A_ADDR_MATCH_CTRL__DISABLE__SHIFT                                                                  0x0
29829 #define GL2A_ADDR_MATCH_CTRL__DISABLE_MASK                                                                    0xFFFFFFFFL
29830 //GL2A_ADDR_MATCH_MASK
29831 #define GL2A_ADDR_MATCH_MASK__ADDR_MASK__SHIFT                                                                0x0
29832 #define GL2A_ADDR_MATCH_MASK__ADDR_MASK_MASK                                                                  0xFFFFFFFFL
29833 //GL2A_ADDR_MATCH_SIZE
29834 #define GL2A_ADDR_MATCH_SIZE__MAX_COUNT__SHIFT                                                                0x0
29835 #define GL2A_ADDR_MATCH_SIZE__MAX_COUNT_MASK                                                                  0x00000007L
29836 //GL2A_PRIORITY_CTRL
29837 #define GL2A_PRIORITY_CTRL__DISABLE__SHIFT                                                                    0x0
29838 #define GL2A_PRIORITY_CTRL__DISABLE_MASK                                                                      0xFFFFFFFFL
29839 //GL2A_CTRL
29840 #define GL2A_CTRL__RTN_ARB_TIMER_RESET_VALUE__SHIFT                                                           0x0
29841 #define GL2A_CTRL__STAY_ON_BURST__SHIFT                                                                       0x1
29842 #define GL2A_CTRL__RTN_ARB_TIMER_RESET_VALUE_MASK                                                             0x00000001L
29843 #define GL2A_CTRL__STAY_ON_BURST_MASK                                                                         0x00000002L
29844 //GL2_PIPE_STEER_0
29845 #define GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q0__SHIFT                                                         0x0
29846 #define GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q0__SHIFT                                                         0x4
29847 #define GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q0__SHIFT                                                         0x8
29848 #define GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q0__SHIFT                                                         0xc
29849 #define GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q1__SHIFT                                                         0x10
29850 #define GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q1__SHIFT                                                         0x14
29851 #define GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q1__SHIFT                                                         0x18
29852 #define GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q1__SHIFT                                                         0x1c
29853 #define GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q0_MASK                                                           0x00000007L
29854 #define GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q0_MASK                                                           0x00000070L
29855 #define GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q0_MASK                                                           0x00000700L
29856 #define GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q0_MASK                                                           0x00007000L
29857 #define GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q1_MASK                                                           0x00070000L
29858 #define GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q1_MASK                                                           0x00700000L
29859 #define GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q1_MASK                                                           0x07000000L
29860 #define GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q1_MASK                                                           0x70000000L
29861 //GL2_PIPE_STEER_1
29862 #define GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q2__SHIFT                                                         0x0
29863 #define GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q2__SHIFT                                                         0x4
29864 #define GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q2__SHIFT                                                         0x8
29865 #define GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q2__SHIFT                                                         0xc
29866 #define GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q3__SHIFT                                                         0x10
29867 #define GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q3__SHIFT                                                         0x14
29868 #define GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q3__SHIFT                                                         0x18
29869 #define GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q3__SHIFT                                                         0x1c
29870 #define GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q2_MASK                                                           0x00000007L
29871 #define GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q2_MASK                                                           0x00000070L
29872 #define GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q2_MASK                                                           0x00000700L
29873 #define GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q2_MASK                                                           0x00007000L
29874 #define GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q3_MASK                                                           0x00070000L
29875 #define GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q3_MASK                                                           0x00700000L
29876 #define GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q3_MASK                                                           0x07000000L
29877 #define GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q3_MASK                                                           0x70000000L
29878 
29879 
29880 // addressBlock: gc_perfddec
29881 //CPG_PERFCOUNTER1_LO
29882 #define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
29883 #define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
29884 //CPG_PERFCOUNTER1_HI
29885 #define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
29886 #define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
29887 //CPG_PERFCOUNTER0_LO
29888 #define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
29889 #define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
29890 //CPG_PERFCOUNTER0_HI
29891 #define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
29892 #define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
29893 //CPC_PERFCOUNTER1_LO
29894 #define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
29895 #define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
29896 //CPC_PERFCOUNTER1_HI
29897 #define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
29898 #define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
29899 //CPC_PERFCOUNTER0_LO
29900 #define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
29901 #define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
29902 //CPC_PERFCOUNTER0_HI
29903 #define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
29904 #define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
29905 //CPF_PERFCOUNTER1_LO
29906 #define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
29907 #define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
29908 //CPF_PERFCOUNTER1_HI
29909 #define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
29910 #define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
29911 //CPF_PERFCOUNTER0_LO
29912 #define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
29913 #define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
29914 //CPF_PERFCOUNTER0_HI
29915 #define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
29916 #define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
29917 //CPF_LATENCY_STATS_DATA
29918 #define CPF_LATENCY_STATS_DATA__DATA__SHIFT                                                                   0x0
29919 #define CPF_LATENCY_STATS_DATA__DATA_MASK                                                                     0xFFFFFFFFL
29920 //CPG_LATENCY_STATS_DATA
29921 #define CPG_LATENCY_STATS_DATA__DATA__SHIFT                                                                   0x0
29922 #define CPG_LATENCY_STATS_DATA__DATA_MASK                                                                     0xFFFFFFFFL
29923 //CPC_LATENCY_STATS_DATA
29924 #define CPC_LATENCY_STATS_DATA__DATA__SHIFT                                                                   0x0
29925 #define CPC_LATENCY_STATS_DATA__DATA_MASK                                                                     0xFFFFFFFFL
29926 //GRBM_PERFCOUNTER0_LO
29927 #define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
29928 #define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
29929 //GRBM_PERFCOUNTER0_HI
29930 #define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
29931 #define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
29932 //GRBM_PERFCOUNTER1_LO
29933 #define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
29934 #define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
29935 //GRBM_PERFCOUNTER1_HI
29936 #define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
29937 #define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
29938 //GRBM_SE0_PERFCOUNTER_LO
29939 #define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT                                                        0x0
29940 #define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK                                                          0xFFFFFFFFL
29941 //GRBM_SE0_PERFCOUNTER_HI
29942 #define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT                                                        0x0
29943 #define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK                                                          0xFFFFFFFFL
29944 //GRBM_SE1_PERFCOUNTER_LO
29945 #define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT                                                        0x0
29946 #define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK                                                          0xFFFFFFFFL
29947 //GRBM_SE1_PERFCOUNTER_HI
29948 #define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT                                                        0x0
29949 #define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK                                                          0xFFFFFFFFL
29950 //GRBM_SE2_PERFCOUNTER_LO
29951 #define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT                                                        0x0
29952 #define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK                                                          0xFFFFFFFFL
29953 //GRBM_SE2_PERFCOUNTER_HI
29954 #define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT                                                        0x0
29955 #define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK                                                          0xFFFFFFFFL
29956 //GRBM_SE3_PERFCOUNTER_LO
29957 #define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT                                                        0x0
29958 #define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK                                                          0xFFFFFFFFL
29959 //GRBM_SE3_PERFCOUNTER_HI
29960 #define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT                                                        0x0
29961 #define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK                                                          0xFFFFFFFFL
29962 //GE_PERFCOUNTER0_LO
29963 #define GE_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
29964 #define GE_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
29965 //GE_PERFCOUNTER0_HI
29966 #define GE_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
29967 #define GE_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
29968 //GE_PERFCOUNTER1_LO
29969 #define GE_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
29970 #define GE_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
29971 //GE_PERFCOUNTER1_HI
29972 #define GE_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
29973 #define GE_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
29974 //GE_PERFCOUNTER2_LO
29975 #define GE_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
29976 #define GE_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
29977 //GE_PERFCOUNTER2_HI
29978 #define GE_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
29979 #define GE_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
29980 //GE_PERFCOUNTER3_LO
29981 #define GE_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
29982 #define GE_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
29983 //GE_PERFCOUNTER3_HI
29984 #define GE_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
29985 #define GE_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
29986 //GE_PERFCOUNTER4_LO
29987 #define GE_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
29988 #define GE_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
29989 //GE_PERFCOUNTER4_HI
29990 #define GE_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
29991 #define GE_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
29992 //GE_PERFCOUNTER5_LO
29993 #define GE_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
29994 #define GE_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
29995 //GE_PERFCOUNTER5_HI
29996 #define GE_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
29997 #define GE_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
29998 //GE_PERFCOUNTER6_LO
29999 #define GE_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
30000 #define GE_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
30001 //GE_PERFCOUNTER6_HI
30002 #define GE_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
30003 #define GE_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
30004 //GE_PERFCOUNTER7_LO
30005 #define GE_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
30006 #define GE_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
30007 //GE_PERFCOUNTER7_HI
30008 #define GE_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
30009 #define GE_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
30010 //GE_PERFCOUNTER8_LO
30011 #define GE_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
30012 #define GE_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
30013 //GE_PERFCOUNTER8_HI
30014 #define GE_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
30015 #define GE_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
30016 //GE_PERFCOUNTER9_LO
30017 #define GE_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
30018 #define GE_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
30019 //GE_PERFCOUNTER9_HI
30020 #define GE_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
30021 #define GE_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
30022 //GE_PERFCOUNTER10_LO
30023 #define GE_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30024 #define GE_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30025 //GE_PERFCOUNTER10_HI
30026 #define GE_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30027 #define GE_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30028 //GE_PERFCOUNTER11_LO
30029 #define GE_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30030 #define GE_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30031 //GE_PERFCOUNTER11_HI
30032 #define GE_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30033 #define GE_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30034 //PA_SU_PERFCOUNTER0_LO
30035 #define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
30036 #define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
30037 //PA_SU_PERFCOUNTER0_HI
30038 #define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
30039 #define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                            0x0000FFFFL
30040 //PA_SU_PERFCOUNTER1_LO
30041 #define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
30042 #define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
30043 //PA_SU_PERFCOUNTER1_HI
30044 #define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
30045 #define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                            0x0000FFFFL
30046 //PA_SU_PERFCOUNTER2_LO
30047 #define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
30048 #define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
30049 //PA_SU_PERFCOUNTER2_HI
30050 #define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
30051 #define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                            0x0000FFFFL
30052 //PA_SU_PERFCOUNTER3_LO
30053 #define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
30054 #define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
30055 //PA_SU_PERFCOUNTER3_HI
30056 #define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
30057 #define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                            0x0000FFFFL
30058 //PA_SC_PERFCOUNTER0_LO
30059 #define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
30060 #define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
30061 //PA_SC_PERFCOUNTER0_HI
30062 #define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
30063 #define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
30064 //PA_SC_PERFCOUNTER1_LO
30065 #define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
30066 #define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
30067 //PA_SC_PERFCOUNTER1_HI
30068 #define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
30069 #define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
30070 //PA_SC_PERFCOUNTER2_LO
30071 #define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
30072 #define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
30073 //PA_SC_PERFCOUNTER2_HI
30074 #define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
30075 #define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
30076 //PA_SC_PERFCOUNTER3_LO
30077 #define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
30078 #define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
30079 //PA_SC_PERFCOUNTER3_HI
30080 #define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
30081 #define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
30082 //PA_SC_PERFCOUNTER4_LO
30083 #define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
30084 #define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
30085 //PA_SC_PERFCOUNTER4_HI
30086 #define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
30087 #define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
30088 //PA_SC_PERFCOUNTER5_LO
30089 #define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
30090 #define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
30091 //PA_SC_PERFCOUNTER5_HI
30092 #define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
30093 #define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
30094 //PA_SC_PERFCOUNTER6_LO
30095 #define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
30096 #define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
30097 //PA_SC_PERFCOUNTER6_HI
30098 #define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
30099 #define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
30100 //PA_SC_PERFCOUNTER7_LO
30101 #define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
30102 #define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
30103 //PA_SC_PERFCOUNTER7_HI
30104 #define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
30105 #define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
30106 //SPI_PERFCOUNTER0_HI
30107 #define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30108 #define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30109 //SPI_PERFCOUNTER0_LO
30110 #define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30111 #define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30112 //SPI_PERFCOUNTER1_HI
30113 #define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30114 #define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30115 //SPI_PERFCOUNTER1_LO
30116 #define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30117 #define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30118 //SPI_PERFCOUNTER2_HI
30119 #define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30120 #define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30121 //SPI_PERFCOUNTER2_LO
30122 #define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30123 #define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30124 //SPI_PERFCOUNTER3_HI
30125 #define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30126 #define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30127 //SPI_PERFCOUNTER3_LO
30128 #define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30129 #define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30130 //SPI_PERFCOUNTER4_HI
30131 #define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30132 #define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30133 //SPI_PERFCOUNTER4_LO
30134 #define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30135 #define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30136 //SPI_PERFCOUNTER5_HI
30137 #define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30138 #define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30139 //SPI_PERFCOUNTER5_LO
30140 #define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30141 #define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30142 //SQ_PERFCOUNTER0_LO
30143 #define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
30144 #define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
30145 //SQ_PERFCOUNTER0_HI
30146 #define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
30147 #define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
30148 //SQ_PERFCOUNTER1_LO
30149 #define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
30150 #define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
30151 //SQ_PERFCOUNTER1_HI
30152 #define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
30153 #define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
30154 //SQ_PERFCOUNTER2_LO
30155 #define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
30156 #define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
30157 //SQ_PERFCOUNTER2_HI
30158 #define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
30159 #define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
30160 //SQ_PERFCOUNTER3_LO
30161 #define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
30162 #define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
30163 //SQ_PERFCOUNTER3_HI
30164 #define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
30165 #define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
30166 //SQ_PERFCOUNTER4_LO
30167 #define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
30168 #define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
30169 //SQ_PERFCOUNTER4_HI
30170 #define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
30171 #define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
30172 //SQ_PERFCOUNTER5_LO
30173 #define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
30174 #define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
30175 //SQ_PERFCOUNTER5_HI
30176 #define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
30177 #define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
30178 //SQ_PERFCOUNTER6_LO
30179 #define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
30180 #define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
30181 //SQ_PERFCOUNTER6_HI
30182 #define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
30183 #define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
30184 //SQ_PERFCOUNTER7_LO
30185 #define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
30186 #define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
30187 //SQ_PERFCOUNTER7_HI
30188 #define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
30189 #define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
30190 //SQ_PERFCOUNTER8_LO
30191 #define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
30192 #define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
30193 //SQ_PERFCOUNTER8_HI
30194 #define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
30195 #define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
30196 //SQ_PERFCOUNTER9_LO
30197 #define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
30198 #define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
30199 //SQ_PERFCOUNTER9_HI
30200 #define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
30201 #define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
30202 //SQ_PERFCOUNTER10_LO
30203 #define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30204 #define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30205 //SQ_PERFCOUNTER10_HI
30206 #define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30207 #define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30208 //SQ_PERFCOUNTER11_LO
30209 #define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30210 #define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30211 //SQ_PERFCOUNTER11_HI
30212 #define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30213 #define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30214 //SQ_PERFCOUNTER12_LO
30215 #define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30216 #define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30217 //SQ_PERFCOUNTER12_HI
30218 #define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30219 #define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30220 //SQ_PERFCOUNTER13_LO
30221 #define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30222 #define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30223 //SQ_PERFCOUNTER13_HI
30224 #define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30225 #define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30226 //SQ_PERFCOUNTER14_LO
30227 #define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30228 #define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30229 //SQ_PERFCOUNTER14_HI
30230 #define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30231 #define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30232 //SQ_PERFCOUNTER15_LO
30233 #define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30234 #define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30235 //SQ_PERFCOUNTER15_HI
30236 #define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30237 #define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30238 //SX_PERFCOUNTER0_LO
30239 #define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
30240 #define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
30241 //SX_PERFCOUNTER0_HI
30242 #define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
30243 #define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
30244 //SX_PERFCOUNTER1_LO
30245 #define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
30246 #define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
30247 //SX_PERFCOUNTER1_HI
30248 #define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
30249 #define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
30250 //SX_PERFCOUNTER2_LO
30251 #define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
30252 #define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
30253 //SX_PERFCOUNTER2_HI
30254 #define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
30255 #define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
30256 //SX_PERFCOUNTER3_LO
30257 #define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
30258 #define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
30259 //SX_PERFCOUNTER3_HI
30260 #define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
30261 #define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
30262 //GCEA_PERFCOUNTER2_LO
30263 #define GCEA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
30264 #define GCEA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
30265 //GCEA_PERFCOUNTER2_HI
30266 #define GCEA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
30267 #define GCEA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
30268 //GDS_PERFCOUNTER0_LO
30269 #define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30270 #define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30271 //GDS_PERFCOUNTER0_HI
30272 #define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30273 #define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30274 //GDS_PERFCOUNTER1_LO
30275 #define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30276 #define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30277 //GDS_PERFCOUNTER1_HI
30278 #define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30279 #define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30280 //GDS_PERFCOUNTER2_LO
30281 #define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30282 #define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30283 //GDS_PERFCOUNTER2_HI
30284 #define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30285 #define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30286 //GDS_PERFCOUNTER3_LO
30287 #define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30288 #define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30289 //GDS_PERFCOUNTER3_HI
30290 #define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30291 #define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30292 //TA_PERFCOUNTER0_LO
30293 #define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
30294 #define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
30295 //TA_PERFCOUNTER0_HI
30296 #define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
30297 #define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
30298 //TA_PERFCOUNTER1_LO
30299 #define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
30300 #define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
30301 //TA_PERFCOUNTER1_HI
30302 #define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
30303 #define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
30304 //TD_PERFCOUNTER0_LO
30305 #define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
30306 #define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
30307 //TD_PERFCOUNTER0_HI
30308 #define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
30309 #define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
30310 //TD_PERFCOUNTER1_LO
30311 #define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
30312 #define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
30313 //TD_PERFCOUNTER1_HI
30314 #define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
30315 #define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
30316 //TCP_PERFCOUNTER0_LO
30317 #define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30318 #define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30319 //TCP_PERFCOUNTER0_HI
30320 #define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30321 #define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30322 //TCP_PERFCOUNTER1_LO
30323 #define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30324 #define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30325 //TCP_PERFCOUNTER1_HI
30326 #define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30327 #define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30328 //TCP_PERFCOUNTER2_LO
30329 #define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30330 #define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30331 //TCP_PERFCOUNTER2_HI
30332 #define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30333 #define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30334 //TCP_PERFCOUNTER3_LO
30335 #define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30336 #define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30337 //TCP_PERFCOUNTER3_HI
30338 #define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30339 #define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30340 //GL2C_PERFCOUNTER0_LO
30341 #define GL2C_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
30342 #define GL2C_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
30343 //GL2C_PERFCOUNTER0_HI
30344 #define GL2C_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
30345 #define GL2C_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
30346 //GL2C_PERFCOUNTER1_LO
30347 #define GL2C_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
30348 #define GL2C_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
30349 //GL2C_PERFCOUNTER1_HI
30350 #define GL2C_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
30351 #define GL2C_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
30352 //GL2C_PERFCOUNTER2_LO
30353 #define GL2C_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
30354 #define GL2C_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
30355 //GL2C_PERFCOUNTER2_HI
30356 #define GL2C_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
30357 #define GL2C_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
30358 //GL2C_PERFCOUNTER3_LO
30359 #define GL2C_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
30360 #define GL2C_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
30361 //GL2C_PERFCOUNTER3_HI
30362 #define GL2C_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
30363 #define GL2C_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
30364 //GL2A_PERFCOUNTER0_LO
30365 #define GL2A_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
30366 #define GL2A_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
30367 //GL2A_PERFCOUNTER0_HI
30368 #define GL2A_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
30369 #define GL2A_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
30370 //GL2A_PERFCOUNTER1_LO
30371 #define GL2A_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
30372 #define GL2A_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
30373 //GL2A_PERFCOUNTER1_HI
30374 #define GL2A_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
30375 #define GL2A_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
30376 //GL2A_PERFCOUNTER2_LO
30377 #define GL2A_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
30378 #define GL2A_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
30379 //GL2A_PERFCOUNTER2_HI
30380 #define GL2A_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
30381 #define GL2A_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
30382 //GL2A_PERFCOUNTER3_LO
30383 #define GL2A_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
30384 #define GL2A_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
30385 //GL2A_PERFCOUNTER3_HI
30386 #define GL2A_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
30387 #define GL2A_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
30388 //GL1C_PERFCOUNTER0_LO
30389 #define GL1C_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
30390 #define GL1C_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
30391 //GL1C_PERFCOUNTER0_HI
30392 #define GL1C_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
30393 #define GL1C_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
30394 //GL1C_PERFCOUNTER1_LO
30395 #define GL1C_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
30396 #define GL1C_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
30397 //GL1C_PERFCOUNTER1_HI
30398 #define GL1C_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
30399 #define GL1C_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
30400 //GL1C_PERFCOUNTER2_LO
30401 #define GL1C_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
30402 #define GL1C_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
30403 //GL1C_PERFCOUNTER2_HI
30404 #define GL1C_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
30405 #define GL1C_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
30406 //GL1C_PERFCOUNTER3_LO
30407 #define GL1C_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
30408 #define GL1C_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
30409 //GL1C_PERFCOUNTER3_HI
30410 #define GL1C_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
30411 #define GL1C_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
30412 //CHC_PERFCOUNTER0_LO
30413 #define CHC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30414 #define CHC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30415 //CHC_PERFCOUNTER0_HI
30416 #define CHC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30417 #define CHC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30418 //CHC_PERFCOUNTER1_LO
30419 #define CHC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30420 #define CHC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30421 //CHC_PERFCOUNTER1_HI
30422 #define CHC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30423 #define CHC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30424 //CHC_PERFCOUNTER2_LO
30425 #define CHC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30426 #define CHC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30427 //CHC_PERFCOUNTER2_HI
30428 #define CHC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30429 #define CHC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30430 //CHC_PERFCOUNTER3_LO
30431 #define CHC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30432 #define CHC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30433 //CHC_PERFCOUNTER3_HI
30434 #define CHC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30435 #define CHC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30436 //CHCG_PERFCOUNTER0_LO
30437 #define CHCG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
30438 #define CHCG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
30439 //CHCG_PERFCOUNTER0_HI
30440 #define CHCG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
30441 #define CHCG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
30442 //CHCG_PERFCOUNTER1_LO
30443 #define CHCG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
30444 #define CHCG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
30445 //CHCG_PERFCOUNTER1_HI
30446 #define CHCG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
30447 #define CHCG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
30448 //CHCG_PERFCOUNTER2_LO
30449 #define CHCG_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
30450 #define CHCG_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
30451 //CHCG_PERFCOUNTER2_HI
30452 #define CHCG_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
30453 #define CHCG_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
30454 //CHCG_PERFCOUNTER3_LO
30455 #define CHCG_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
30456 #define CHCG_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
30457 //CHCG_PERFCOUNTER3_HI
30458 #define CHCG_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
30459 #define CHCG_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
30460 //CB_PERFCOUNTER0_LO
30461 #define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
30462 #define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
30463 //CB_PERFCOUNTER0_HI
30464 #define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
30465 #define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
30466 //CB_PERFCOUNTER1_LO
30467 #define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
30468 #define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
30469 //CB_PERFCOUNTER1_HI
30470 #define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
30471 #define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
30472 //CB_PERFCOUNTER2_LO
30473 #define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
30474 #define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
30475 //CB_PERFCOUNTER2_HI
30476 #define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
30477 #define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
30478 //CB_PERFCOUNTER3_LO
30479 #define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
30480 #define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
30481 //CB_PERFCOUNTER3_HI
30482 #define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
30483 #define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
30484 //DB_PERFCOUNTER0_LO
30485 #define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
30486 #define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
30487 //DB_PERFCOUNTER0_HI
30488 #define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
30489 #define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
30490 //DB_PERFCOUNTER1_LO
30491 #define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
30492 #define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
30493 //DB_PERFCOUNTER1_HI
30494 #define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
30495 #define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
30496 //DB_PERFCOUNTER2_LO
30497 #define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
30498 #define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
30499 //DB_PERFCOUNTER2_HI
30500 #define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
30501 #define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
30502 //DB_PERFCOUNTER3_LO
30503 #define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
30504 #define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
30505 //DB_PERFCOUNTER3_HI
30506 #define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
30507 #define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
30508 //RLC_PERFCOUNTER0_LO
30509 #define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30510 #define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30511 //RLC_PERFCOUNTER0_HI
30512 #define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30513 #define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30514 //RLC_PERFCOUNTER1_LO
30515 #define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30516 #define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30517 //RLC_PERFCOUNTER1_HI
30518 #define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30519 #define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30520 //RMI_PERFCOUNTER0_LO
30521 #define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30522 #define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30523 //RMI_PERFCOUNTER0_HI
30524 #define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30525 #define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30526 //RMI_PERFCOUNTER1_LO
30527 #define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30528 #define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30529 //RMI_PERFCOUNTER1_HI
30530 #define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30531 #define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30532 //RMI_PERFCOUNTER2_LO
30533 #define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30534 #define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30535 //RMI_PERFCOUNTER2_HI
30536 #define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30537 #define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30538 //RMI_PERFCOUNTER3_LO
30539 #define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30540 #define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30541 //RMI_PERFCOUNTER3_HI
30542 #define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30543 #define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30544 //UTCL1_PERFCOUNTER0_LO
30545 #define UTCL1_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
30546 #define UTCL1_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
30547 //UTCL1_PERFCOUNTER0_HI
30548 #define UTCL1_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
30549 #define UTCL1_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
30550 //UTCL1_PERFCOUNTER1_LO
30551 #define UTCL1_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
30552 #define UTCL1_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
30553 //UTCL1_PERFCOUNTER1_HI
30554 #define UTCL1_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
30555 #define UTCL1_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
30556 //GCR_PERFCOUNTER0_LO
30557 #define GCR_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30558 #define GCR_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30559 //GCR_PERFCOUNTER0_HI
30560 #define GCR_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30561 #define GCR_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30562 //GCR_PERFCOUNTER1_LO
30563 #define GCR_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30564 #define GCR_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30565 //GCR_PERFCOUNTER1_HI
30566 #define GCR_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30567 #define GCR_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30568 //PA_PH_PERFCOUNTER0_LO
30569 #define PA_PH_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
30570 #define PA_PH_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
30571 //PA_PH_PERFCOUNTER0_HI
30572 #define PA_PH_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
30573 #define PA_PH_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
30574 //PA_PH_PERFCOUNTER1_LO
30575 #define PA_PH_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
30576 #define PA_PH_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
30577 //PA_PH_PERFCOUNTER1_HI
30578 #define PA_PH_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
30579 #define PA_PH_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
30580 //PA_PH_PERFCOUNTER2_LO
30581 #define PA_PH_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
30582 #define PA_PH_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
30583 //PA_PH_PERFCOUNTER2_HI
30584 #define PA_PH_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
30585 #define PA_PH_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
30586 //PA_PH_PERFCOUNTER3_LO
30587 #define PA_PH_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
30588 #define PA_PH_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
30589 //PA_PH_PERFCOUNTER3_HI
30590 #define PA_PH_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
30591 #define PA_PH_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
30592 //PA_PH_PERFCOUNTER4_LO
30593 #define PA_PH_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
30594 #define PA_PH_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
30595 //PA_PH_PERFCOUNTER4_HI
30596 #define PA_PH_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
30597 #define PA_PH_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
30598 //PA_PH_PERFCOUNTER5_LO
30599 #define PA_PH_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
30600 #define PA_PH_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
30601 //PA_PH_PERFCOUNTER5_HI
30602 #define PA_PH_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
30603 #define PA_PH_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
30604 //PA_PH_PERFCOUNTER6_LO
30605 #define PA_PH_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
30606 #define PA_PH_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
30607 //PA_PH_PERFCOUNTER6_HI
30608 #define PA_PH_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
30609 #define PA_PH_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
30610 //PA_PH_PERFCOUNTER7_LO
30611 #define PA_PH_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
30612 #define PA_PH_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
30613 //PA_PH_PERFCOUNTER7_HI
30614 #define PA_PH_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
30615 #define PA_PH_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
30616 //GL1A_PERFCOUNTER0_LO
30617 #define GL1A_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
30618 #define GL1A_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
30619 //GL1A_PERFCOUNTER0_HI
30620 #define GL1A_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
30621 #define GL1A_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
30622 //GL1A_PERFCOUNTER1_LO
30623 #define GL1A_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
30624 #define GL1A_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
30625 //GL1A_PERFCOUNTER1_HI
30626 #define GL1A_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
30627 #define GL1A_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
30628 //GL1A_PERFCOUNTER2_LO
30629 #define GL1A_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
30630 #define GL1A_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
30631 //GL1A_PERFCOUNTER2_HI
30632 #define GL1A_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
30633 #define GL1A_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
30634 //GL1A_PERFCOUNTER3_LO
30635 #define GL1A_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
30636 #define GL1A_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
30637 //GL1A_PERFCOUNTER3_HI
30638 #define GL1A_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
30639 #define GL1A_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
30640 //CHA_PERFCOUNTER0_LO
30641 #define CHA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30642 #define CHA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30643 //CHA_PERFCOUNTER0_HI
30644 #define CHA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30645 #define CHA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30646 //CHA_PERFCOUNTER1_LO
30647 #define CHA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30648 #define CHA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30649 //CHA_PERFCOUNTER1_HI
30650 #define CHA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30651 #define CHA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30652 //CHA_PERFCOUNTER2_LO
30653 #define CHA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30654 #define CHA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30655 //CHA_PERFCOUNTER2_HI
30656 #define CHA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30657 #define CHA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30658 //CHA_PERFCOUNTER3_LO
30659 #define CHA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30660 #define CHA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30661 //CHA_PERFCOUNTER3_HI
30662 #define CHA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30663 #define CHA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30664 //GUS_PERFCOUNTER2_LO
30665 #define GUS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
30666 #define GUS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
30667 //GUS_PERFCOUNTER2_HI
30668 #define GUS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
30669 #define GUS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
30670 
30671 
30672 // addressBlock: gc_gcatcl2pfcntrdec
30673 //GC_ATC_L2_PERFCOUNTER_LO
30674 #define GC_ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                           0x0
30675 #define GC_ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK                                                             0xFFFFFFFFL
30676 //GC_ATC_L2_PERFCOUNTER_HI
30677 #define GC_ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                           0x0
30678 #define GC_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                        0x10
30679 #define GC_ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK                                                             0x0000FFFFL
30680 #define GC_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                          0xFFFF0000L
30681 
30682 
30683 // addressBlock: gc_gcvml2prdec
30684 //GCMC_VM_L2_PERFCOUNTER_LO
30685 #define GCMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                          0x0
30686 #define GCMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK                                                            0xFFFFFFFFL
30687 //GCMC_VM_L2_PERFCOUNTER_HI
30688 #define GCMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                          0x0
30689 #define GCMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                       0x10
30690 #define GCMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK                                                            0x0000FFFFL
30691 #define GCMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                         0xFFFF0000L
30692 
30693 
30694 // addressBlock: gc_gcvml2perfddec
30695 //GCVML2_PERFCOUNTER2_0_LO
30696 #define GCVML2_PERFCOUNTER2_0_LO__PERFCOUNTER_LO__SHIFT                                                       0x0
30697 #define GCVML2_PERFCOUNTER2_0_LO__PERFCOUNTER_LO_MASK                                                         0xFFFFFFFFL
30698 //GCVML2_PERFCOUNTER2_1_LO
30699 #define GCVML2_PERFCOUNTER2_1_LO__PERFCOUNTER_LO__SHIFT                                                       0x0
30700 #define GCVML2_PERFCOUNTER2_1_LO__PERFCOUNTER_LO_MASK                                                         0xFFFFFFFFL
30701 //GCVML2_PERFCOUNTER2_0_HI
30702 #define GCVML2_PERFCOUNTER2_0_HI__PERFCOUNTER_HI__SHIFT                                                       0x0
30703 #define GCVML2_PERFCOUNTER2_0_HI__PERFCOUNTER_HI_MASK                                                         0xFFFFFFFFL
30704 //GCVML2_PERFCOUNTER2_1_HI
30705 #define GCVML2_PERFCOUNTER2_1_HI__PERFCOUNTER_HI__SHIFT                                                       0x0
30706 #define GCVML2_PERFCOUNTER2_1_HI__PERFCOUNTER_HI_MASK                                                         0xFFFFFFFFL
30707 
30708 
30709 // addressBlock: gc_gcatcl2perfddec
30710 //GC_ATC_L2_PERFCOUNTER2_LO
30711 #define GC_ATC_L2_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                      0x0
30712 #define GC_ATC_L2_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                        0xFFFFFFFFL
30713 //GC_ATC_L2_PERFCOUNTER2_HI
30714 #define GC_ATC_L2_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                      0x0
30715 #define GC_ATC_L2_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                        0xFFFFFFFFL
30716 
30717 
30718 // addressBlock: gc_perfsdec
30719 //CPG_PERFCOUNTER1_SELECT
30720 #define CPG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
30721 #define CPG_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                             0xa
30722 #define CPG_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT                                                              0x14
30723 #define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT                                                            0x18
30724 #define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT                                                            0x1c
30725 #define CPG_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000003FFL
30726 #define CPG_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
30727 #define CPG_PERFCOUNTER1_SELECT__SPM_MODE_MASK                                                                0x00F00000L
30728 #define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK                                                              0x0F000000L
30729 #define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK                                                              0xF0000000L
30730 //CPG_PERFCOUNTER0_SELECT1
30731 #define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
30732 #define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
30733 #define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT                                                           0x18
30734 #define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT                                                           0x1c
30735 #define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
30736 #define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
30737 #define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK                                                             0x0F000000L
30738 #define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK                                                             0xF0000000L
30739 //CPG_PERFCOUNTER0_SELECT
30740 #define CPG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
30741 #define CPG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
30742 #define CPG_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT                                                              0x14
30743 #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT                                                            0x18
30744 #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT                                                            0x1c
30745 #define CPG_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000003FFL
30746 #define CPG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
30747 #define CPG_PERFCOUNTER0_SELECT__SPM_MODE_MASK                                                                0x00F00000L
30748 #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK                                                              0x0F000000L
30749 #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK                                                              0xF0000000L
30750 //CPC_PERFCOUNTER1_SELECT
30751 #define CPC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
30752 #define CPC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                             0xa
30753 #define CPC_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT                                                              0x14
30754 #define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT                                                            0x18
30755 #define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT                                                            0x1c
30756 #define CPC_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000003FFL
30757 #define CPC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
30758 #define CPC_PERFCOUNTER1_SELECT__SPM_MODE_MASK                                                                0x00F00000L
30759 #define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK                                                              0x0F000000L
30760 #define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK                                                              0xF0000000L
30761 //CPC_PERFCOUNTER0_SELECT1
30762 #define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
30763 #define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
30764 #define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT                                                           0x18
30765 #define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT                                                           0x1c
30766 #define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
30767 #define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
30768 #define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK                                                             0x0F000000L
30769 #define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK                                                             0xF0000000L
30770 //CPF_PERFCOUNTER1_SELECT
30771 #define CPF_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
30772 #define CPF_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                             0xa
30773 #define CPF_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT                                                              0x14
30774 #define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT                                                            0x18
30775 #define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT                                                            0x1c
30776 #define CPF_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000003FFL
30777 #define CPF_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
30778 #define CPF_PERFCOUNTER1_SELECT__SPM_MODE_MASK                                                                0x00F00000L
30779 #define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK                                                              0x0F000000L
30780 #define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK                                                              0xF0000000L
30781 //CPF_PERFCOUNTER0_SELECT1
30782 #define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
30783 #define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
30784 #define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT                                                           0x18
30785 #define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT                                                           0x1c
30786 #define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
30787 #define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
30788 #define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK                                                             0x0F000000L
30789 #define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK                                                             0xF0000000L
30790 //CPF_PERFCOUNTER0_SELECT
30791 #define CPF_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
30792 #define CPF_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
30793 #define CPF_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT                                                              0x14
30794 #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT                                                            0x18
30795 #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT                                                            0x1c
30796 #define CPF_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000003FFL
30797 #define CPF_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
30798 #define CPF_PERFCOUNTER0_SELECT__SPM_MODE_MASK                                                                0x00F00000L
30799 #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK                                                              0x0F000000L
30800 #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK                                                              0xF0000000L
30801 //CP_PERFMON_CNTL
30802 #define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                                 0x0
30803 #define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT                                                             0x4
30804 #define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT                                                           0x8
30805 #define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT                                                         0xa
30806 #define CP_PERFMON_CNTL__PERFMON_STATE_MASK                                                                   0x0000000FL
30807 #define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK                                                               0x000000F0L
30808 #define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK                                                             0x00000300L
30809 #define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK                                                           0x00000400L
30810 //CPC_PERFCOUNTER0_SELECT
30811 #define CPC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
30812 #define CPC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
30813 #define CPC_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT                                                              0x14
30814 #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT                                                            0x18
30815 #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT                                                            0x1c
30816 #define CPC_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000003FFL
30817 #define CPC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
30818 #define CPC_PERFCOUNTER0_SELECT__SPM_MODE_MASK                                                                0x00F00000L
30819 #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK                                                              0x0F000000L
30820 #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK                                                              0xF0000000L
30821 //CPF_TC_PERF_COUNTER_WINDOW_SELECT
30822 #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT                                                       0x0
30823 #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT                                                      0x1e
30824 #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT                                                      0x1f
30825 #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK                                                         0x00000007L
30826 #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK                                                        0x40000000L
30827 #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK                                                        0x80000000L
30828 //CPG_TC_PERF_COUNTER_WINDOW_SELECT
30829 #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT                                                       0x0
30830 #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT                                                      0x1e
30831 #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT                                                      0x1f
30832 #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK                                                         0x0000001FL
30833 #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK                                                        0x40000000L
30834 #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK                                                        0x80000000L
30835 //CPF_LATENCY_STATS_SELECT
30836 #define CPF_LATENCY_STATS_SELECT__INDEX__SHIFT                                                                0x0
30837 #define CPF_LATENCY_STATS_SELECT__CLEAR__SHIFT                                                                0x1e
30838 #define CPF_LATENCY_STATS_SELECT__ENABLE__SHIFT                                                               0x1f
30839 #define CPF_LATENCY_STATS_SELECT__INDEX_MASK                                                                  0x0000000FL
30840 #define CPF_LATENCY_STATS_SELECT__CLEAR_MASK                                                                  0x40000000L
30841 #define CPF_LATENCY_STATS_SELECT__ENABLE_MASK                                                                 0x80000000L
30842 //CPG_LATENCY_STATS_SELECT
30843 #define CPG_LATENCY_STATS_SELECT__INDEX__SHIFT                                                                0x0
30844 #define CPG_LATENCY_STATS_SELECT__CLEAR__SHIFT                                                                0x1e
30845 #define CPG_LATENCY_STATS_SELECT__ENABLE__SHIFT                                                               0x1f
30846 #define CPG_LATENCY_STATS_SELECT__INDEX_MASK                                                                  0x0000001FL
30847 #define CPG_LATENCY_STATS_SELECT__CLEAR_MASK                                                                  0x40000000L
30848 #define CPG_LATENCY_STATS_SELECT__ENABLE_MASK                                                                 0x80000000L
30849 //CPC_LATENCY_STATS_SELECT
30850 #define CPC_LATENCY_STATS_SELECT__INDEX__SHIFT                                                                0x0
30851 #define CPC_LATENCY_STATS_SELECT__CLEAR__SHIFT                                                                0x1e
30852 #define CPC_LATENCY_STATS_SELECT__ENABLE__SHIFT                                                               0x1f
30853 #define CPC_LATENCY_STATS_SELECT__INDEX_MASK                                                                  0x0000000FL
30854 #define CPC_LATENCY_STATS_SELECT__CLEAR_MASK                                                                  0x40000000L
30855 #define CPC_LATENCY_STATS_SELECT__ENABLE_MASK                                                                 0x80000000L
30856 //CP_DRAW_OBJECT
30857 #define CP_DRAW_OBJECT__OBJECT__SHIFT                                                                         0x0
30858 #define CP_DRAW_OBJECT__OBJECT_MASK                                                                           0xFFFFFFFFL
30859 //CP_DRAW_OBJECT_COUNTER
30860 #define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT                                                                  0x0
30861 #define CP_DRAW_OBJECT_COUNTER__COUNT_MASK                                                                    0x0000FFFFL
30862 //CP_DRAW_WINDOW_MASK_HI
30863 #define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT                                                         0x0
30864 #define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK                                                           0xFFFFFFFFL
30865 //CP_DRAW_WINDOW_HI
30866 #define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT                                                                   0x0
30867 #define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK                                                                     0xFFFFFFFFL
30868 //CP_DRAW_WINDOW_LO
30869 #define CP_DRAW_WINDOW_LO__MIN__SHIFT                                                                         0x0
30870 #define CP_DRAW_WINDOW_LO__MAX__SHIFT                                                                         0x10
30871 #define CP_DRAW_WINDOW_LO__MIN_MASK                                                                           0x0000FFFFL
30872 #define CP_DRAW_WINDOW_LO__MAX_MASK                                                                           0xFFFF0000L
30873 //CP_DRAW_WINDOW_CNTL
30874 #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT                                                0x0
30875 #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT                                                0x1
30876 #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT                                                    0x2
30877 #define CP_DRAW_WINDOW_CNTL__MODE__SHIFT                                                                      0x8
30878 #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK                                                  0x00000001L
30879 #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK                                                  0x00000002L
30880 #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK                                                      0x00000004L
30881 #define CP_DRAW_WINDOW_CNTL__MODE_MASK                                                                        0x00000100L
30882 //GRBM_PERFCOUNTER0_SELECT
30883 #define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                             0x0
30884 #define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT                                           0xa
30885 #define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT                                           0xb
30886 #define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT                                            0xd
30887 #define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT                                            0xe
30888 #define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT                                           0x10
30889 #define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT                                            0x11
30890 #define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT                                            0x12
30891 #define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT                                          0x13
30892 #define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT                                            0x14
30893 #define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT                                            0x15
30894 #define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT                                            0x16
30895 #define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT                                           0x18
30896 #define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT                                           0x19
30897 #define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT                                           0x1a
30898 #define GRBM_PERFCOUNTER0_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT                                           0x1b
30899 #define GRBM_PERFCOUNTER0_SELECT__GE_BUSY_USER_DEFINED_MASK__SHIFT                                            0x1c
30900 #define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT                                         0x1d
30901 #define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT                                            0x1e
30902 #define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT                                           0x1f
30903 #define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                               0x0000003FL
30904 #define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK                                             0x00000400L
30905 #define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK                                             0x00000800L
30906 #define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK                                              0x00002000L
30907 #define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK                                              0x00004000L
30908 #define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK                                             0x00010000L
30909 #define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK                                              0x00020000L
30910 #define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK                                              0x00040000L
30911 #define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK                                            0x00080000L
30912 #define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK                                              0x00100000L
30913 #define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK                                              0x00200000L
30914 #define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK                                              0x00400000L
30915 #define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK                                             0x01000000L
30916 #define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK                                             0x02000000L
30917 #define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK                                             0x04000000L
30918 #define GRBM_PERFCOUNTER0_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK                                             0x08000000L
30919 #define GRBM_PERFCOUNTER0_SELECT__GE_BUSY_USER_DEFINED_MASK_MASK                                              0x10000000L
30920 #define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK                                           0x20000000L
30921 #define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK                                              0x40000000L
30922 #define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK                                             0x80000000L
30923 //GRBM_PERFCOUNTER1_SELECT
30924 #define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                             0x0
30925 #define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT                                           0xa
30926 #define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT                                           0xb
30927 #define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT                                            0xd
30928 #define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT                                            0xe
30929 #define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT                                           0x10
30930 #define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT                                            0x11
30931 #define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT                                            0x12
30932 #define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT                                          0x13
30933 #define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT                                            0x14
30934 #define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT                                            0x15
30935 #define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT                                            0x16
30936 #define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT                                           0x18
30937 #define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT                                           0x19
30938 #define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT                                           0x1a
30939 #define GRBM_PERFCOUNTER1_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT                                           0x1b
30940 #define GRBM_PERFCOUNTER1_SELECT__GE_BUSY_USER_DEFINED_MASK__SHIFT                                            0x1c
30941 #define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT                                         0x1d
30942 #define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT                                            0x1e
30943 #define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT                                           0x1f
30944 #define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                               0x0000003FL
30945 #define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK                                             0x00000400L
30946 #define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK                                             0x00000800L
30947 #define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK                                              0x00002000L
30948 #define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK                                              0x00004000L
30949 #define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK                                             0x00010000L
30950 #define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK                                              0x00020000L
30951 #define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK                                              0x00040000L
30952 #define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK                                            0x00080000L
30953 #define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK                                              0x00100000L
30954 #define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK                                              0x00200000L
30955 #define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK                                              0x00400000L
30956 #define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK                                             0x01000000L
30957 #define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK                                             0x02000000L
30958 #define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK                                             0x04000000L
30959 #define GRBM_PERFCOUNTER1_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK                                             0x08000000L
30960 #define GRBM_PERFCOUNTER1_SELECT__GE_BUSY_USER_DEFINED_MASK_MASK                                              0x10000000L
30961 #define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK                                           0x20000000L
30962 #define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK                                              0x40000000L
30963 #define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK                                             0x80000000L
30964 //GRBM_SE0_PERFCOUNTER_SELECT
30965 #define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT                                                          0x0
30966 #define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xa
30967 #define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xb
30968 #define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT                                         0xc
30969 #define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT                                         0xd
30970 #define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT                                        0xf
30971 #define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT                                         0x10
30972 #define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x11
30973 #define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x12
30974 #define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT                                         0x14
30975 #define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x15
30976 #define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x16
30977 #define GRBM_SE0_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT                                      0x17
30978 #define GRBM_SE0_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT                                        0x18
30979 #define GRBM_SE0_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT                                      0x19
30980 #define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK                                                            0x0000003FL
30981 #define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000400L
30982 #define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000800L
30983 #define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK                                           0x00001000L
30984 #define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK                                           0x00002000L
30985 #define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK                                          0x00008000L
30986 #define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK                                           0x00010000L
30987 #define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK                                           0x00020000L
30988 #define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK                                           0x00040000L
30989 #define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK                                           0x00100000L
30990 #define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK                                          0x00200000L
30991 #define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK                                          0x00400000L
30992 #define GRBM_SE0_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK                                        0x00800000L
30993 #define GRBM_SE0_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK                                          0x01000000L
30994 #define GRBM_SE0_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK                                        0x02000000L
30995 //GRBM_SE1_PERFCOUNTER_SELECT
30996 #define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT                                                          0x0
30997 #define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xa
30998 #define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xb
30999 #define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT                                         0xc
31000 #define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT                                         0xd
31001 #define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT                                        0xf
31002 #define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT                                         0x10
31003 #define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x11
31004 #define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x12
31005 #define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT                                         0x14
31006 #define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x15
31007 #define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x16
31008 #define GRBM_SE1_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT                                      0x17
31009 #define GRBM_SE1_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT                                        0x18
31010 #define GRBM_SE1_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT                                      0x19
31011 #define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK                                                            0x0000003FL
31012 #define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000400L
31013 #define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000800L
31014 #define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK                                           0x00001000L
31015 #define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK                                           0x00002000L
31016 #define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK                                          0x00008000L
31017 #define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK                                           0x00010000L
31018 #define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK                                           0x00020000L
31019 #define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK                                           0x00040000L
31020 #define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK                                           0x00100000L
31021 #define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK                                          0x00200000L
31022 #define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK                                          0x00400000L
31023 #define GRBM_SE1_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK                                        0x00800000L
31024 #define GRBM_SE1_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK                                          0x01000000L
31025 #define GRBM_SE1_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK                                        0x02000000L
31026 //GRBM_SE2_PERFCOUNTER_SELECT
31027 #define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT                                                          0x0
31028 #define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xa
31029 #define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xb
31030 #define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT                                         0xc
31031 #define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT                                         0xd
31032 #define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT                                        0xf
31033 #define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT                                         0x10
31034 #define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x11
31035 #define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x12
31036 #define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT                                         0x14
31037 #define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x15
31038 #define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x16
31039 #define GRBM_SE2_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT                                      0x17
31040 #define GRBM_SE2_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT                                        0x18
31041 #define GRBM_SE2_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT                                      0x19
31042 #define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK                                                            0x0000003FL
31043 #define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000400L
31044 #define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000800L
31045 #define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK                                           0x00001000L
31046 #define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK                                           0x00002000L
31047 #define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK                                          0x00008000L
31048 #define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK                                           0x00010000L
31049 #define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK                                           0x00020000L
31050 #define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK                                           0x00040000L
31051 #define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK                                           0x00100000L
31052 #define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK                                          0x00200000L
31053 #define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK                                          0x00400000L
31054 #define GRBM_SE2_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK                                        0x00800000L
31055 #define GRBM_SE2_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK                                          0x01000000L
31056 #define GRBM_SE2_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK                                        0x02000000L
31057 //GRBM_SE3_PERFCOUNTER_SELECT
31058 #define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT                                                          0x0
31059 #define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xa
31060 #define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xb
31061 #define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT                                         0xc
31062 #define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT                                         0xd
31063 #define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT                                        0xf
31064 #define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT                                         0x10
31065 #define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x11
31066 #define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x12
31067 #define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT                                         0x14
31068 #define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x15
31069 #define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x16
31070 #define GRBM_SE3_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT                                      0x17
31071 #define GRBM_SE3_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT                                        0x18
31072 #define GRBM_SE3_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT                                      0x19
31073 #define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK                                                            0x0000003FL
31074 #define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000400L
31075 #define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000800L
31076 #define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK                                           0x00001000L
31077 #define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK                                           0x00002000L
31078 #define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK                                          0x00008000L
31079 #define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK                                           0x00010000L
31080 #define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK                                           0x00020000L
31081 #define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK                                           0x00040000L
31082 #define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK                                           0x00100000L
31083 #define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK                                          0x00200000L
31084 #define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK                                          0x00400000L
31085 #define GRBM_SE3_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK                                        0x00800000L
31086 #define GRBM_SE3_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK                                          0x01000000L
31087 #define GRBM_SE3_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK                                        0x02000000L
31088 //GRBM_PERFCOUNTER0_SELECT_HI
31089 #define GRBM_PERFCOUNTER0_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT                                      0x1
31090 #define GRBM_PERFCOUNTER0_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK__SHIFT                                      0x2
31091 #define GRBM_PERFCOUNTER0_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK__SHIFT                                       0x3
31092 #define GRBM_PERFCOUNTER0_SELECT_HI__CH_BUSY_USER_DEFINED_MASK__SHIFT                                         0x4
31093 #define GRBM_PERFCOUNTER0_SELECT_HI__PH_BUSY_USER_DEFINED_MASK__SHIFT                                         0x5
31094 #define GRBM_PERFCOUNTER0_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK__SHIFT                                        0x6
31095 #define GRBM_PERFCOUNTER0_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK__SHIFT                                        0x7
31096 #define GRBM_PERFCOUNTER0_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT                                      0x8
31097 #define GRBM_PERFCOUNTER0_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK_MASK                                        0x00000002L
31098 #define GRBM_PERFCOUNTER0_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK_MASK                                        0x00000004L
31099 #define GRBM_PERFCOUNTER0_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK_MASK                                         0x00000008L
31100 #define GRBM_PERFCOUNTER0_SELECT_HI__CH_BUSY_USER_DEFINED_MASK_MASK                                           0x00000010L
31101 #define GRBM_PERFCOUNTER0_SELECT_HI__PH_BUSY_USER_DEFINED_MASK_MASK                                           0x00000020L
31102 #define GRBM_PERFCOUNTER0_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK_MASK                                          0x00000040L
31103 #define GRBM_PERFCOUNTER0_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK_MASK                                          0x00000080L
31104 #define GRBM_PERFCOUNTER0_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK_MASK                                        0x00000100L
31105 //GRBM_PERFCOUNTER1_SELECT_HI
31106 #define GRBM_PERFCOUNTER1_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT                                      0x1
31107 #define GRBM_PERFCOUNTER1_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK__SHIFT                                      0x2
31108 #define GRBM_PERFCOUNTER1_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK__SHIFT                                       0x3
31109 #define GRBM_PERFCOUNTER1_SELECT_HI__CH_BUSY_USER_DEFINED_MASK__SHIFT                                         0x4
31110 #define GRBM_PERFCOUNTER1_SELECT_HI__PH_BUSY_USER_DEFINED_MASK__SHIFT                                         0x5
31111 #define GRBM_PERFCOUNTER1_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK__SHIFT                                        0x6
31112 #define GRBM_PERFCOUNTER1_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK__SHIFT                                        0x7
31113 #define GRBM_PERFCOUNTER1_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT                                      0x8
31114 #define GRBM_PERFCOUNTER1_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK_MASK                                        0x00000002L
31115 #define GRBM_PERFCOUNTER1_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK_MASK                                        0x00000004L
31116 #define GRBM_PERFCOUNTER1_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK_MASK                                         0x00000008L
31117 #define GRBM_PERFCOUNTER1_SELECT_HI__CH_BUSY_USER_DEFINED_MASK_MASK                                           0x00000010L
31118 #define GRBM_PERFCOUNTER1_SELECT_HI__PH_BUSY_USER_DEFINED_MASK_MASK                                           0x00000020L
31119 #define GRBM_PERFCOUNTER1_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK_MASK                                          0x00000040L
31120 #define GRBM_PERFCOUNTER1_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK_MASK                                          0x00000080L
31121 #define GRBM_PERFCOUNTER1_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK_MASK                                        0x00000100L
31122 //GE_PERFCOUNTER0_SELECT
31123 #define GE_PERFCOUNTER0_SELECT__PERF_SEL0__SHIFT                                                              0x0
31124 #define GE_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                              0xa
31125 #define GE_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                              0x14
31126 #define GE_PERFCOUNTER0_SELECT__PERF_MODE0__SHIFT                                                             0x18
31127 #define GE_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                             0x1c
31128 #define GE_PERFCOUNTER0_SELECT__PERF_SEL0_MASK                                                                0x000003FFL
31129 #define GE_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                                0x000FFC00L
31130 #define GE_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
31131 #define GE_PERFCOUNTER0_SELECT__PERF_MODE0_MASK                                                               0x0F000000L
31132 #define GE_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                               0xF0000000L
31133 //GE_PERFCOUNTER0_SELECT1
31134 #define GE_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                             0x0
31135 #define GE_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                             0xa
31136 #define GE_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                            0x18
31137 #define GE_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                            0x1c
31138 #define GE_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                               0x000003FFL
31139 #define GE_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                               0x000FFC00L
31140 #define GE_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                              0x0F000000L
31141 #define GE_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                              0xF0000000L
31142 //GE_PERFCOUNTER1_SELECT
31143 #define GE_PERFCOUNTER1_SELECT__PERF_SEL0__SHIFT                                                              0x0
31144 #define GE_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                              0xa
31145 #define GE_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                              0x14
31146 #define GE_PERFCOUNTER1_SELECT__PERF_MODE0__SHIFT                                                             0x18
31147 #define GE_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                             0x1c
31148 #define GE_PERFCOUNTER1_SELECT__PERF_SEL0_MASK                                                                0x000003FFL
31149 #define GE_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                                0x000FFC00L
31150 #define GE_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
31151 #define GE_PERFCOUNTER1_SELECT__PERF_MODE0_MASK                                                               0x0F000000L
31152 #define GE_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                               0xF0000000L
31153 //GE_PERFCOUNTER1_SELECT1
31154 #define GE_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                             0x0
31155 #define GE_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                             0xa
31156 #define GE_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                            0x18
31157 #define GE_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                            0x1c
31158 #define GE_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                               0x000003FFL
31159 #define GE_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                               0x000FFC00L
31160 #define GE_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                              0x0F000000L
31161 #define GE_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                              0xF0000000L
31162 //GE_PERFCOUNTER2_SELECT
31163 #define GE_PERFCOUNTER2_SELECT__PERF_SEL0__SHIFT                                                              0x0
31164 #define GE_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT                                                              0xa
31165 #define GE_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                              0x14
31166 #define GE_PERFCOUNTER2_SELECT__PERF_MODE0__SHIFT                                                             0x18
31167 #define GE_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT                                                             0x1c
31168 #define GE_PERFCOUNTER2_SELECT__PERF_SEL0_MASK                                                                0x000003FFL
31169 #define GE_PERFCOUNTER2_SELECT__PERF_SEL1_MASK                                                                0x000FFC00L
31170 #define GE_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
31171 #define GE_PERFCOUNTER2_SELECT__PERF_MODE0_MASK                                                               0x0F000000L
31172 #define GE_PERFCOUNTER2_SELECT__PERF_MODE1_MASK                                                               0xF0000000L
31173 //GE_PERFCOUNTER2_SELECT1
31174 #define GE_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT                                                             0x0
31175 #define GE_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT                                                             0xa
31176 #define GE_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT                                                            0x18
31177 #define GE_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT                                                            0x1c
31178 #define GE_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK                                                               0x000003FFL
31179 #define GE_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK                                                               0x000FFC00L
31180 #define GE_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK                                                              0x0F000000L
31181 #define GE_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK                                                              0xF0000000L
31182 //GE_PERFCOUNTER3_SELECT
31183 #define GE_PERFCOUNTER3_SELECT__PERF_SEL0__SHIFT                                                              0x0
31184 #define GE_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT                                                              0xa
31185 #define GE_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                              0x14
31186 #define GE_PERFCOUNTER3_SELECT__PERF_MODE0__SHIFT                                                             0x18
31187 #define GE_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT                                                             0x1c
31188 #define GE_PERFCOUNTER3_SELECT__PERF_SEL0_MASK                                                                0x000003FFL
31189 #define GE_PERFCOUNTER3_SELECT__PERF_SEL1_MASK                                                                0x000FFC00L
31190 #define GE_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
31191 #define GE_PERFCOUNTER3_SELECT__PERF_MODE0_MASK                                                               0x0F000000L
31192 #define GE_PERFCOUNTER3_SELECT__PERF_MODE1_MASK                                                               0xF0000000L
31193 //GE_PERFCOUNTER3_SELECT1
31194 #define GE_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT                                                             0x0
31195 #define GE_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT                                                             0xa
31196 #define GE_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT                                                            0x18
31197 #define GE_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT                                                            0x1c
31198 #define GE_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK                                                               0x000003FFL
31199 #define GE_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK                                                               0x000FFC00L
31200 #define GE_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK                                                              0x0F000000L
31201 #define GE_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK                                                              0xF0000000L
31202 //GE_PERFCOUNTER4_SELECT
31203 #define GE_PERFCOUNTER4_SELECT__PERF_SEL0__SHIFT                                                              0x0
31204 #define GE_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT                                                              0x1c
31205 #define GE_PERFCOUNTER4_SELECT__PERF_SEL0_MASK                                                                0x000003FFL
31206 #define GE_PERFCOUNTER4_SELECT__PERF_MODE_MASK                                                                0xF0000000L
31207 //GE_PERFCOUNTER5_SELECT
31208 #define GE_PERFCOUNTER5_SELECT__PERF_SEL0__SHIFT                                                              0x0
31209 #define GE_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT                                                              0x1c
31210 #define GE_PERFCOUNTER5_SELECT__PERF_SEL0_MASK                                                                0x000003FFL
31211 #define GE_PERFCOUNTER5_SELECT__PERF_MODE_MASK                                                                0xF0000000L
31212 //GE_PERFCOUNTER6_SELECT
31213 #define GE_PERFCOUNTER6_SELECT__PERF_SEL0__SHIFT                                                              0x0
31214 #define GE_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT                                                              0x1c
31215 #define GE_PERFCOUNTER6_SELECT__PERF_SEL0_MASK                                                                0x000003FFL
31216 #define GE_PERFCOUNTER6_SELECT__PERF_MODE_MASK                                                                0xF0000000L
31217 //GE_PERFCOUNTER7_SELECT
31218 #define GE_PERFCOUNTER7_SELECT__PERF_SEL0__SHIFT                                                              0x0
31219 #define GE_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT                                                              0x1c
31220 #define GE_PERFCOUNTER7_SELECT__PERF_SEL0_MASK                                                                0x000003FFL
31221 #define GE_PERFCOUNTER7_SELECT__PERF_MODE_MASK                                                                0xF0000000L
31222 //GE_PERFCOUNTER8_SELECT
31223 #define GE_PERFCOUNTER8_SELECT__PERF_SEL0__SHIFT                                                              0x0
31224 #define GE_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT                                                              0x1c
31225 #define GE_PERFCOUNTER8_SELECT__PERF_SEL0_MASK                                                                0x000003FFL
31226 #define GE_PERFCOUNTER8_SELECT__PERF_MODE_MASK                                                                0xF0000000L
31227 //GE_PERFCOUNTER9_SELECT
31228 #define GE_PERFCOUNTER9_SELECT__PERF_SEL0__SHIFT                                                              0x0
31229 #define GE_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT                                                              0x1c
31230 #define GE_PERFCOUNTER9_SELECT__PERF_SEL0_MASK                                                                0x000003FFL
31231 #define GE_PERFCOUNTER9_SELECT__PERF_MODE_MASK                                                                0xF0000000L
31232 //GE_PERFCOUNTER10_SELECT
31233 #define GE_PERFCOUNTER10_SELECT__PERF_SEL0__SHIFT                                                             0x0
31234 #define GE_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT                                                             0x1c
31235 #define GE_PERFCOUNTER10_SELECT__PERF_SEL0_MASK                                                               0x000003FFL
31236 #define GE_PERFCOUNTER10_SELECT__PERF_MODE_MASK                                                               0xF0000000L
31237 //GE_PERFCOUNTER11_SELECT
31238 #define GE_PERFCOUNTER11_SELECT__PERF_SEL0__SHIFT                                                             0x0
31239 #define GE_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT                                                             0x1c
31240 #define GE_PERFCOUNTER11_SELECT__PERF_SEL0_MASK                                                               0x000003FFL
31241 #define GE_PERFCOUNTER11_SELECT__PERF_MODE_MASK                                                               0xF0000000L
31242 //PA_SU_PERFCOUNTER0_SELECT
31243 #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                            0x0
31244 #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                           0xa
31245 #define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                           0x14
31246 #define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                          0x18
31247 #define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                           0x1c
31248 #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                              0x000003FFL
31249 #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
31250 #define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
31251 #define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                            0x0F000000L
31252 #define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                             0xF0000000L
31253 //PA_SU_PERFCOUNTER0_SELECT1
31254 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                          0x0
31255 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                          0xa
31256 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                         0x18
31257 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                         0x1c
31258 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
31259 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
31260 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                           0x0F000000L
31261 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                           0xF0000000L
31262 //PA_SU_PERFCOUNTER1_SELECT
31263 #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                            0x0
31264 #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                           0xa
31265 #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                           0x14
31266 #define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                          0x18
31267 #define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                           0x1c
31268 #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                              0x000003FFL
31269 #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
31270 #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
31271 #define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                            0x0F000000L
31272 #define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                             0xF0000000L
31273 //PA_SU_PERFCOUNTER1_SELECT1
31274 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                          0x0
31275 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                          0xa
31276 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                         0x18
31277 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                         0x1c
31278 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
31279 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
31280 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                           0x0F000000L
31281 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                           0xF0000000L
31282 //PA_SU_PERFCOUNTER2_SELECT
31283 #define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                            0x0
31284 #define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT                                                           0xa
31285 #define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                           0x14
31286 #define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT                                                          0x18
31287 #define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                           0x1c
31288 #define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                              0x000003FFL
31289 #define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
31290 #define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
31291 #define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE1_MASK                                                            0x0F000000L
31292 #define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                             0xF0000000L
31293 //PA_SU_PERFCOUNTER2_SELECT1
31294 #define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT                                                          0x0
31295 #define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT                                                          0xa
31296 #define PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT                                                         0x18
31297 #define PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT                                                         0x1c
31298 #define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
31299 #define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
31300 #define PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK                                                           0x0F000000L
31301 #define PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK                                                           0xF0000000L
31302 //PA_SU_PERFCOUNTER3_SELECT
31303 #define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                            0x0
31304 #define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT                                                           0xa
31305 #define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                           0x14
31306 #define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT                                                          0x18
31307 #define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                           0x1c
31308 #define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                              0x000003FFL
31309 #define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
31310 #define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
31311 #define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE1_MASK                                                            0x0F000000L
31312 #define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                             0xF0000000L
31313 //PA_SU_PERFCOUNTER3_SELECT1
31314 #define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT                                                          0x0
31315 #define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT                                                          0xa
31316 #define PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT                                                         0x18
31317 #define PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT                                                         0x1c
31318 #define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
31319 #define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
31320 #define PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK                                                           0x0F000000L
31321 #define PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK                                                           0xF0000000L
31322 //PA_SC_PERFCOUNTER0_SELECT
31323 #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                            0x0
31324 #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                           0xa
31325 #define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                           0x14
31326 #define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                          0x18
31327 #define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                           0x1c
31328 #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                              0x000003FFL
31329 #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
31330 #define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
31331 #define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                            0x0F000000L
31332 #define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                             0xF0000000L
31333 //PA_SC_PERFCOUNTER0_SELECT1
31334 #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                          0x0
31335 #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                          0xa
31336 #define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                         0x18
31337 #define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                         0x1c
31338 #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
31339 #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
31340 #define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                           0x0F000000L
31341 #define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                           0xF0000000L
31342 //PA_SC_PERFCOUNTER1_SELECT
31343 #define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                            0x0
31344 #define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                              0x000003FFL
31345 //PA_SC_PERFCOUNTER2_SELECT
31346 #define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                            0x0
31347 #define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                              0x000003FFL
31348 //PA_SC_PERFCOUNTER3_SELECT
31349 #define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                            0x0
31350 #define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                              0x000003FFL
31351 //PA_SC_PERFCOUNTER4_SELECT
31352 #define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT                                                            0x0
31353 #define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK                                                              0x000003FFL
31354 //PA_SC_PERFCOUNTER5_SELECT
31355 #define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT                                                            0x0
31356 #define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK                                                              0x000003FFL
31357 //PA_SC_PERFCOUNTER6_SELECT
31358 #define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT                                                            0x0
31359 #define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK                                                              0x000003FFL
31360 //PA_SC_PERFCOUNTER7_SELECT
31361 #define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT                                                            0x0
31362 #define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK                                                              0x000003FFL
31363 //SPI_PERFCOUNTER0_SELECT
31364 #define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
31365 #define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
31366 #define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                             0x14
31367 #define SPI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                            0x18
31368 #define SPI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                             0x1c
31369 #define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000003FFL
31370 #define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
31371 #define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
31372 #define SPI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
31373 #define SPI_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                               0xF0000000L
31374 //SPI_PERFCOUNTER1_SELECT
31375 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
31376 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                             0xa
31377 #define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                             0x14
31378 #define SPI_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                            0x18
31379 #define SPI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                             0x1c
31380 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000003FFL
31381 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
31382 #define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
31383 #define SPI_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
31384 #define SPI_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                               0xF0000000L
31385 //SPI_PERFCOUNTER2_SELECT
31386 #define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                              0x0
31387 #define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT                                                             0xa
31388 #define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                             0x14
31389 #define SPI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT                                                            0x18
31390 #define SPI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                             0x1c
31391 #define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                0x000003FFL
31392 #define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
31393 #define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
31394 #define SPI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
31395 #define SPI_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                               0xF0000000L
31396 //SPI_PERFCOUNTER3_SELECT
31397 #define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                              0x0
31398 #define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT                                                             0xa
31399 #define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                             0x14
31400 #define SPI_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT                                                            0x18
31401 #define SPI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                             0x1c
31402 #define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                0x000003FFL
31403 #define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
31404 #define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
31405 #define SPI_PERFCOUNTER3_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
31406 #define SPI_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                               0xF0000000L
31407 //SPI_PERFCOUNTER0_SELECT1
31408 #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
31409 #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
31410 #define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                           0x18
31411 #define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
31412 #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
31413 #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
31414 #define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
31415 #define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
31416 //SPI_PERFCOUNTER1_SELECT1
31417 #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                            0x0
31418 #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                            0xa
31419 #define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                           0x18
31420 #define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
31421 #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
31422 #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
31423 #define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
31424 #define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
31425 //SPI_PERFCOUNTER2_SELECT1
31426 #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT                                                            0x0
31427 #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT                                                            0xa
31428 #define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT                                                           0x18
31429 #define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
31430 #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
31431 #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
31432 #define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
31433 #define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
31434 //SPI_PERFCOUNTER3_SELECT1
31435 #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT                                                            0x0
31436 #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT                                                            0xa
31437 #define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT                                                           0x18
31438 #define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
31439 #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
31440 #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
31441 #define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
31442 #define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
31443 //SPI_PERFCOUNTER4_SELECT
31444 #define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT                                                              0x0
31445 #define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK                                                                0x000003FFL
31446 //SPI_PERFCOUNTER5_SELECT
31447 #define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT                                                              0x0
31448 #define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK                                                                0x000003FFL
31449 //SPI_PERFCOUNTER_BINS
31450 #define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT                                                                 0x0
31451 #define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT                                                                 0x4
31452 #define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT                                                                 0x8
31453 #define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT                                                                 0xc
31454 #define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT                                                                 0x10
31455 #define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT                                                                 0x14
31456 #define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT                                                                 0x18
31457 #define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT                                                                 0x1c
31458 #define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK                                                                   0x0000000FL
31459 #define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK                                                                   0x000000F0L
31460 #define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK                                                                   0x00000F00L
31461 #define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK                                                                   0x0000F000L
31462 #define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK                                                                   0x000F0000L
31463 #define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK                                                                   0x00F00000L
31464 #define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK                                                                   0x0F000000L
31465 #define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK                                                                   0xF0000000L
31466 //SQ_PERFCOUNTER0_SELECT
31467 #define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                               0x0
31468 #define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
31469 #define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT                                                               0x14
31470 #define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                              0x1c
31471 #define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
31472 #define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
31473 #define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
31474 #define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                                0xF0000000L
31475 //SQ_PERFCOUNTER1_SELECT
31476 #define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                               0x0
31477 #define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
31478 #define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT                                                               0x14
31479 #define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                              0x1c
31480 #define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
31481 #define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
31482 #define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
31483 #define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                                0xF0000000L
31484 //SQ_PERFCOUNTER2_SELECT
31485 #define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                               0x0
31486 #define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
31487 #define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT                                                               0x14
31488 #define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                              0x1c
31489 #define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
31490 #define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
31491 #define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
31492 #define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                                0xF0000000L
31493 //SQ_PERFCOUNTER3_SELECT
31494 #define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                               0x0
31495 #define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
31496 #define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT                                                               0x14
31497 #define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                              0x1c
31498 #define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
31499 #define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
31500 #define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
31501 #define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                                0xF0000000L
31502 //SQ_PERFCOUNTER4_SELECT
31503 #define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT                                                               0x0
31504 #define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
31505 #define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT                                                               0x14
31506 #define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT                                                              0x1c
31507 #define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
31508 #define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
31509 #define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
31510 #define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK                                                                0xF0000000L
31511 //SQ_PERFCOUNTER5_SELECT
31512 #define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT                                                               0x0
31513 #define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
31514 #define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT                                                               0x14
31515 #define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT                                                              0x1c
31516 #define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
31517 #define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
31518 #define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
31519 #define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK                                                                0xF0000000L
31520 //SQ_PERFCOUNTER6_SELECT
31521 #define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT                                                               0x0
31522 #define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
31523 #define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT                                                               0x14
31524 #define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT                                                              0x1c
31525 #define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
31526 #define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
31527 #define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
31528 #define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK                                                                0xF0000000L
31529 //SQ_PERFCOUNTER7_SELECT
31530 #define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT                                                               0x0
31531 #define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
31532 #define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT                                                               0x14
31533 #define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT                                                              0x1c
31534 #define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
31535 #define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
31536 #define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
31537 #define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK                                                                0xF0000000L
31538 //SQ_PERFCOUNTER8_SELECT
31539 #define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT                                                               0x0
31540 #define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
31541 #define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT                                                               0x14
31542 #define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT                                                              0x1c
31543 #define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
31544 #define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
31545 #define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
31546 #define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK                                                                0xF0000000L
31547 //SQ_PERFCOUNTER9_SELECT
31548 #define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT                                                               0x0
31549 #define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
31550 #define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT                                                               0x14
31551 #define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT                                                              0x1c
31552 #define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
31553 #define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
31554 #define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
31555 #define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK                                                                0xF0000000L
31556 //SQ_PERFCOUNTER10_SELECT
31557 #define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT                                                              0x0
31558 #define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT                                                         0xc
31559 #define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT                                                              0x14
31560 #define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT                                                             0x1c
31561 #define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK                                                                0x000001FFL
31562 #define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK                                                           0x0000F000L
31563 #define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK                                                                0x00F00000L
31564 #define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK                                                               0xF0000000L
31565 //SQ_PERFCOUNTER11_SELECT
31566 #define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT                                                              0x0
31567 #define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT                                                         0xc
31568 #define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT                                                              0x14
31569 #define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT                                                             0x1c
31570 #define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK                                                                0x000001FFL
31571 #define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK                                                           0x0000F000L
31572 #define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK                                                                0x00F00000L
31573 #define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK                                                               0xF0000000L
31574 //SQ_PERFCOUNTER12_SELECT
31575 #define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT                                                              0x0
31576 #define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT                                                         0xc
31577 #define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT                                                              0x14
31578 #define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT                                                             0x1c
31579 #define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK                                                                0x000001FFL
31580 #define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK                                                           0x0000F000L
31581 #define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK                                                                0x00F00000L
31582 #define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK                                                               0xF0000000L
31583 //SQ_PERFCOUNTER13_SELECT
31584 #define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT                                                              0x0
31585 #define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT                                                         0xc
31586 #define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT                                                              0x14
31587 #define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT                                                             0x1c
31588 #define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK                                                                0x000001FFL
31589 #define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK                                                           0x0000F000L
31590 #define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK                                                                0x00F00000L
31591 #define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK                                                               0xF0000000L
31592 //SQ_PERFCOUNTER14_SELECT
31593 #define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT                                                              0x0
31594 #define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT                                                         0xc
31595 #define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT                                                              0x14
31596 #define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT                                                             0x1c
31597 #define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK                                                                0x000001FFL
31598 #define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK                                                           0x0000F000L
31599 #define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK                                                                0x00F00000L
31600 #define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK                                                               0xF0000000L
31601 //SQ_PERFCOUNTER15_SELECT
31602 #define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT                                                              0x0
31603 #define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT                                                         0xc
31604 #define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT                                                              0x14
31605 #define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT                                                             0x1c
31606 #define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK                                                                0x000001FFL
31607 #define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK                                                           0x0000F000L
31608 #define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK                                                                0x00F00000L
31609 #define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK                                                               0xF0000000L
31610 //SQ_PERFCOUNTER_CTRL
31611 #define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT                                                                     0x0
31612 #define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT                                                                     0x1
31613 #define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT                                                                     0x2
31614 #define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT                                                                     0x3
31615 #define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT                                                                     0x4
31616 #define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT                                                                     0x5
31617 #define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT                                                                     0x6
31618 #define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT                                                                 0x8
31619 #define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT                                                             0xd
31620 #define SQ_PERFCOUNTER_CTRL__PS_EN_MASK                                                                       0x00000001L
31621 #define SQ_PERFCOUNTER_CTRL__VS_EN_MASK                                                                       0x00000002L
31622 #define SQ_PERFCOUNTER_CTRL__GS_EN_MASK                                                                       0x00000004L
31623 #define SQ_PERFCOUNTER_CTRL__ES_EN_MASK                                                                       0x00000008L
31624 #define SQ_PERFCOUNTER_CTRL__HS_EN_MASK                                                                       0x00000010L
31625 #define SQ_PERFCOUNTER_CTRL__LS_EN_MASK                                                                       0x00000020L
31626 #define SQ_PERFCOUNTER_CTRL__CS_EN_MASK                                                                       0x00000040L
31627 #define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK                                                                   0x00000300L
31628 #define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK                                                               0x00002000L
31629 //SQ_PERFCOUNTER_CTRL2
31630 #define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT                                                                 0x0
31631 #define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK                                                                   0x00000001L
31632 //GCEA_PERFCOUNTER2_SELECT
31633 #define GCEA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                             0x0
31634 #define GCEA_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT                                                            0xa
31635 #define GCEA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                            0x14
31636 #define GCEA_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT                                                           0x18
31637 #define GCEA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                            0x1c
31638 #define GCEA_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                               0x000003FFL
31639 #define GCEA_PERFCOUNTER2_SELECT__PERF_SEL1_MASK                                                              0x000FFC00L
31640 #define GCEA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
31641 #define GCEA_PERFCOUNTER2_SELECT__PERF_MODE1_MASK                                                             0x0F000000L
31642 #define GCEA_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                              0xF0000000L
31643 //GCEA_PERFCOUNTER2_SELECT1
31644 #define GCEA_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT                                                           0x0
31645 #define GCEA_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT                                                           0xa
31646 #define GCEA_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT                                                          0x18
31647 #define GCEA_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT                                                          0x1c
31648 #define GCEA_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK                                                             0x000003FFL
31649 #define GCEA_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK                                                             0x000FFC00L
31650 #define GCEA_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK                                                            0x0F000000L
31651 #define GCEA_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK                                                            0xF0000000L
31652 //GCEA_PERFCOUNTER2_MODE
31653 #define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE0__SHIFT                                                          0x0
31654 #define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE1__SHIFT                                                          0x2
31655 #define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE2__SHIFT                                                          0x4
31656 #define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE3__SHIFT                                                          0x6
31657 #define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE0__SHIFT                                                         0x8
31658 #define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE1__SHIFT                                                         0xc
31659 #define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE2__SHIFT                                                         0x10
31660 #define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE3__SHIFT                                                         0x14
31661 #define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE0_MASK                                                            0x00000003L
31662 #define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE1_MASK                                                            0x0000000CL
31663 #define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE2_MASK                                                            0x00000030L
31664 #define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE3_MASK                                                            0x000000C0L
31665 #define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE0_MASK                                                           0x00000F00L
31666 #define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE1_MASK                                                           0x0000F000L
31667 #define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE2_MASK                                                           0x000F0000L
31668 #define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE3_MASK                                                           0x00F00000L
31669 //SX_PERFCOUNTER0_SELECT
31670 #define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT                                                     0x0
31671 #define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT                                                    0xa
31672 #define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                              0x14
31673 #define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK                                                       0x000003FFL
31674 #define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK                                                      0x000FFC00L
31675 #define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
31676 //SX_PERFCOUNTER1_SELECT
31677 #define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT                                                     0x0
31678 #define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT                                                    0xa
31679 #define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                              0x14
31680 #define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK                                                       0x000003FFL
31681 #define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK                                                      0x000FFC00L
31682 #define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
31683 //SX_PERFCOUNTER2_SELECT
31684 #define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT                                                     0x0
31685 #define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT                                                    0xa
31686 #define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                              0x14
31687 #define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK                                                       0x000003FFL
31688 #define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK                                                      0x000FFC00L
31689 #define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
31690 //SX_PERFCOUNTER3_SELECT
31691 #define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT                                                     0x0
31692 #define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT                                                    0xa
31693 #define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                              0x14
31694 #define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK                                                       0x000003FFL
31695 #define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK                                                      0x000FFC00L
31696 #define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
31697 //SX_PERFCOUNTER0_SELECT1
31698 #define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT                                                   0x0
31699 #define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT                                                   0xa
31700 #define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK                                                     0x000003FFL
31701 #define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK                                                     0x000FFC00L
31702 //SX_PERFCOUNTER1_SELECT1
31703 #define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2__SHIFT                                                   0x0
31704 #define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3__SHIFT                                                   0xa
31705 #define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2_MASK                                                     0x000003FFL
31706 #define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3_MASK                                                     0x000FFC00L
31707 //GDS_PERFCOUNTER0_SELECT
31708 #define GDS_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
31709 #define GDS_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
31710 #define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                             0x14
31711 #define GDS_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                            0x18
31712 #define GDS_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                             0x1c
31713 #define GDS_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000003FFL
31714 #define GDS_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
31715 #define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
31716 #define GDS_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
31717 #define GDS_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                               0xF0000000L
31718 //GDS_PERFCOUNTER1_SELECT
31719 #define GDS_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
31720 #define GDS_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                             0xa
31721 #define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                             0x14
31722 #define GDS_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                            0x18
31723 #define GDS_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                             0x1c
31724 #define GDS_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000003FFL
31725 #define GDS_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
31726 #define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
31727 #define GDS_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
31728 #define GDS_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                               0xF0000000L
31729 //GDS_PERFCOUNTER2_SELECT
31730 #define GDS_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                              0x0
31731 #define GDS_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT                                                             0xa
31732 #define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                             0x14
31733 #define GDS_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT                                                            0x18
31734 #define GDS_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                             0x1c
31735 #define GDS_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                0x000003FFL
31736 #define GDS_PERFCOUNTER2_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
31737 #define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
31738 #define GDS_PERFCOUNTER2_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
31739 #define GDS_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                               0xF0000000L
31740 //GDS_PERFCOUNTER3_SELECT
31741 #define GDS_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                              0x0
31742 #define GDS_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT                                                             0xa
31743 #define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                             0x14
31744 #define GDS_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT                                                            0x18
31745 #define GDS_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                             0x1c
31746 #define GDS_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                0x000003FFL
31747 #define GDS_PERFCOUNTER3_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
31748 #define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
31749 #define GDS_PERFCOUNTER3_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
31750 #define GDS_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                               0xF0000000L
31751 //GDS_PERFCOUNTER0_SELECT1
31752 #define GDS_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
31753 #define GDS_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
31754 #define GDS_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                           0x18
31755 #define GDS_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
31756 #define GDS_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
31757 #define GDS_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
31758 #define GDS_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
31759 #define GDS_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
31760 //TA_PERFCOUNTER0_SELECT
31761 #define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                               0x0
31762 #define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                              0xa
31763 #define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                              0x14
31764 #define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                             0x18
31765 #define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                              0x1c
31766 #define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                 0x000000FFL
31767 #define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                                0x0003FC00L
31768 #define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
31769 #define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
31770 #define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                                0xF0000000L
31771 //TA_PERFCOUNTER0_SELECT1
31772 #define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                             0x0
31773 #define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                             0xa
31774 #define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                            0x18
31775 #define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                            0x1c
31776 #define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                               0x000000FFL
31777 #define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                               0x0003FC00L
31778 #define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                              0x0F000000L
31779 #define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                              0xF0000000L
31780 //TA_PERFCOUNTER1_SELECT
31781 #define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                               0x0
31782 #define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                              0x14
31783 #define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                              0x1c
31784 #define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                 0x000000FFL
31785 #define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
31786 #define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                                0xF0000000L
31787 //TD_PERFCOUNTER0_SELECT
31788 #define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                               0x0
31789 #define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                              0xa
31790 #define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                              0x14
31791 #define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                             0x18
31792 #define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                              0x1c
31793 #define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                 0x000000FFL
31794 #define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                                0x0003FC00L
31795 #define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
31796 #define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
31797 #define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                                0xF0000000L
31798 //TD_PERFCOUNTER0_SELECT1
31799 #define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                             0x0
31800 #define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                             0xa
31801 #define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                            0x18
31802 #define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                            0x1c
31803 #define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                               0x000000FFL
31804 #define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                               0x0003FC00L
31805 #define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                              0x0F000000L
31806 #define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                              0xF0000000L
31807 //TD_PERFCOUNTER1_SELECT
31808 #define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                               0x0
31809 #define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                              0x14
31810 #define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                              0x1c
31811 #define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                 0x000000FFL
31812 #define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
31813 #define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                                0xF0000000L
31814 //TCP_PERFCOUNTER0_SELECT
31815 #define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
31816 #define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
31817 #define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                             0x14
31818 #define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                            0x18
31819 #define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                             0x1c
31820 #define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000003FFL
31821 #define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
31822 #define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
31823 #define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
31824 #define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                               0xF0000000L
31825 //TCP_PERFCOUNTER0_SELECT1
31826 #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
31827 #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
31828 #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                           0x18
31829 #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
31830 #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
31831 #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
31832 #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
31833 #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
31834 //TCP_PERFCOUNTER1_SELECT
31835 #define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
31836 #define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                             0xa
31837 #define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                             0x14
31838 #define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                            0x18
31839 #define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                             0x1c
31840 #define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000003FFL
31841 #define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
31842 #define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
31843 #define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
31844 #define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                               0xF0000000L
31845 //TCP_PERFCOUNTER1_SELECT1
31846 #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                            0x0
31847 #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                            0xa
31848 #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                           0x18
31849 #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
31850 #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
31851 #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
31852 #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
31853 #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
31854 //TCP_PERFCOUNTER2_SELECT
31855 #define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                              0x0
31856 #define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                             0x14
31857 #define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                             0x1c
31858 #define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                0x000003FFL
31859 #define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
31860 #define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                               0xF0000000L
31861 //TCP_PERFCOUNTER3_SELECT
31862 #define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                              0x0
31863 #define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                             0x14
31864 #define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                             0x1c
31865 #define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                0x000003FFL
31866 #define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
31867 #define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                               0xF0000000L
31868 //GL2C_PERFCOUNTER0_SELECT
31869 #define GL2C_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                             0x0
31870 #define GL2C_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                            0xa
31871 #define GL2C_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                            0x14
31872 #define GL2C_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                           0x18
31873 #define GL2C_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                            0x1c
31874 #define GL2C_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                               0x000003FFL
31875 #define GL2C_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                              0x000FFC00L
31876 #define GL2C_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
31877 #define GL2C_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                             0x0F000000L
31878 #define GL2C_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                              0xF0000000L
31879 //GL2C_PERFCOUNTER0_SELECT1
31880 #define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                           0x0
31881 #define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                           0xa
31882 #define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                          0x18
31883 #define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                          0x1c
31884 #define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                             0x000003FFL
31885 #define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                             0x000FFC00L
31886 #define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                            0x0F000000L
31887 #define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                            0xF0000000L
31888 //GL2C_PERFCOUNTER1_SELECT
31889 #define GL2C_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                             0x0
31890 #define GL2C_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                            0xa
31891 #define GL2C_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                            0x14
31892 #define GL2C_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                           0x18
31893 #define GL2C_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                            0x1c
31894 #define GL2C_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                               0x000003FFL
31895 #define GL2C_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                              0x000FFC00L
31896 #define GL2C_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
31897 #define GL2C_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                             0x0F000000L
31898 #define GL2C_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                              0xF0000000L
31899 //GL2C_PERFCOUNTER1_SELECT1
31900 #define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                           0x0
31901 #define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                           0xa
31902 #define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                          0x18
31903 #define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                          0x1c
31904 #define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                             0x000003FFL
31905 #define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                             0x000FFC00L
31906 #define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                            0x0F000000L
31907 #define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                            0xF0000000L
31908 //GL2C_PERFCOUNTER2_SELECT
31909 #define GL2C_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                             0x0
31910 #define GL2C_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                            0x14
31911 #define GL2C_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                            0x1c
31912 #define GL2C_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                               0x000003FFL
31913 #define GL2C_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
31914 #define GL2C_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                              0xF0000000L
31915 //GL2C_PERFCOUNTER3_SELECT
31916 #define GL2C_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                             0x0
31917 #define GL2C_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                            0x14
31918 #define GL2C_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                            0x1c
31919 #define GL2C_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                               0x000003FFL
31920 #define GL2C_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
31921 #define GL2C_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                              0xF0000000L
31922 //GL2A_PERFCOUNTER0_SELECT
31923 #define GL2A_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                             0x0
31924 #define GL2A_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                            0xa
31925 #define GL2A_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                            0x14
31926 #define GL2A_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                           0x18
31927 #define GL2A_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                            0x1c
31928 #define GL2A_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                               0x000003FFL
31929 #define GL2A_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                              0x000FFC00L
31930 #define GL2A_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
31931 #define GL2A_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                             0x0F000000L
31932 #define GL2A_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                              0xF0000000L
31933 //GL2A_PERFCOUNTER0_SELECT1
31934 #define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                           0x0
31935 #define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                           0xa
31936 #define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                          0x18
31937 #define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                          0x1c
31938 #define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                             0x000003FFL
31939 #define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                             0x000FFC00L
31940 #define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                            0x0F000000L
31941 #define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                            0xF0000000L
31942 //GL2A_PERFCOUNTER1_SELECT
31943 #define GL2A_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                             0x0
31944 #define GL2A_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                            0xa
31945 #define GL2A_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                            0x14
31946 #define GL2A_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                           0x18
31947 #define GL2A_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                            0x1c
31948 #define GL2A_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                               0x000003FFL
31949 #define GL2A_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                              0x000FFC00L
31950 #define GL2A_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
31951 #define GL2A_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                             0x0F000000L
31952 #define GL2A_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                              0xF0000000L
31953 //GL2A_PERFCOUNTER1_SELECT1
31954 #define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                           0x0
31955 #define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                           0xa
31956 #define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                          0x18
31957 #define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                          0x1c
31958 #define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                             0x000003FFL
31959 #define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                             0x000FFC00L
31960 #define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                            0x0F000000L
31961 #define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                            0xF0000000L
31962 //GL2A_PERFCOUNTER2_SELECT
31963 #define GL2A_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                             0x0
31964 #define GL2A_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                            0x14
31965 #define GL2A_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                            0x1c
31966 #define GL2A_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                               0x000003FFL
31967 #define GL2A_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
31968 #define GL2A_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                              0xF0000000L
31969 //GL2A_PERFCOUNTER3_SELECT
31970 #define GL2A_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                             0x0
31971 #define GL2A_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                            0x14
31972 #define GL2A_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                            0x1c
31973 #define GL2A_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                               0x000003FFL
31974 #define GL2A_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
31975 #define GL2A_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                              0xF0000000L
31976 //GL1C_PERFCOUNTER0_SELECT
31977 #define GL1C_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                             0x0
31978 #define GL1C_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                            0xa
31979 #define GL1C_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                            0x14
31980 #define GL1C_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                           0x18
31981 #define GL1C_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                            0x1c
31982 #define GL1C_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                               0x000003FFL
31983 #define GL1C_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                              0x000FFC00L
31984 #define GL1C_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
31985 #define GL1C_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                             0x0F000000L
31986 #define GL1C_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                              0xF0000000L
31987 //GL1C_PERFCOUNTER0_SELECT1
31988 #define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                           0x0
31989 #define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                           0xa
31990 #define GL1C_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                          0x18
31991 #define GL1C_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                          0x1c
31992 #define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                             0x000003FFL
31993 #define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                             0x000FFC00L
31994 #define GL1C_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                            0x0F000000L
31995 #define GL1C_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                            0xF0000000L
31996 //GL1C_PERFCOUNTER1_SELECT
31997 #define GL1C_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                             0x0
31998 #define GL1C_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                            0x14
31999 #define GL1C_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                            0x1c
32000 #define GL1C_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                               0x000003FFL
32001 #define GL1C_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
32002 #define GL1C_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                              0xF0000000L
32003 //GL1C_PERFCOUNTER2_SELECT
32004 #define GL1C_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                             0x0
32005 #define GL1C_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                            0x14
32006 #define GL1C_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                            0x1c
32007 #define GL1C_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                               0x000003FFL
32008 #define GL1C_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
32009 #define GL1C_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                              0xF0000000L
32010 //GL1C_PERFCOUNTER3_SELECT
32011 #define GL1C_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                             0x0
32012 #define GL1C_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                            0x14
32013 #define GL1C_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                            0x1c
32014 #define GL1C_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                               0x000003FFL
32015 #define GL1C_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
32016 #define GL1C_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                              0xF0000000L
32017 //CHC_PERFCOUNTER0_SELECT
32018 #define CHC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
32019 #define CHC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
32020 #define CHC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                             0x14
32021 #define CHC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                            0x18
32022 #define CHC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                             0x1c
32023 #define CHC_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000003FFL
32024 #define CHC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
32025 #define CHC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
32026 #define CHC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
32027 #define CHC_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                               0xF0000000L
32028 //CHC_PERFCOUNTER0_SELECT1
32029 #define CHC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
32030 #define CHC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
32031 #define CHC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                           0x18
32032 #define CHC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                           0x1c
32033 #define CHC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
32034 #define CHC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
32035 #define CHC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                             0x0F000000L
32036 #define CHC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                             0xF0000000L
32037 //CHC_PERFCOUNTER1_SELECT
32038 #define CHC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
32039 #define CHC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                             0x14
32040 #define CHC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                             0x1c
32041 #define CHC_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000003FFL
32042 #define CHC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
32043 #define CHC_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                               0xF0000000L
32044 //CHC_PERFCOUNTER2_SELECT
32045 #define CHC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                              0x0
32046 #define CHC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                             0x14
32047 #define CHC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                             0x1c
32048 #define CHC_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                0x000003FFL
32049 #define CHC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
32050 #define CHC_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                               0xF0000000L
32051 //CHC_PERFCOUNTER3_SELECT
32052 #define CHC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                              0x0
32053 #define CHC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                             0x14
32054 #define CHC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                             0x1c
32055 #define CHC_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                0x000003FFL
32056 #define CHC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
32057 #define CHC_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                               0xF0000000L
32058 //CHCG_PERFCOUNTER0_SELECT
32059 #define CHCG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                             0x0
32060 #define CHCG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                            0xa
32061 #define CHCG_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                            0x14
32062 #define CHCG_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                           0x18
32063 #define CHCG_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                            0x1c
32064 #define CHCG_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                               0x000003FFL
32065 #define CHCG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                              0x000FFC00L
32066 #define CHCG_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
32067 #define CHCG_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                             0x0F000000L
32068 #define CHCG_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                              0xF0000000L
32069 //CHCG_PERFCOUNTER0_SELECT1
32070 #define CHCG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                           0x0
32071 #define CHCG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                           0xa
32072 #define CHCG_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                          0x18
32073 #define CHCG_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                          0x1c
32074 #define CHCG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                             0x000003FFL
32075 #define CHCG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                             0x000FFC00L
32076 #define CHCG_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                            0x0F000000L
32077 #define CHCG_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                            0xF0000000L
32078 //CHCG_PERFCOUNTER1_SELECT
32079 #define CHCG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                             0x0
32080 #define CHCG_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                            0x14
32081 #define CHCG_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                            0x1c
32082 #define CHCG_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                               0x000003FFL
32083 #define CHCG_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
32084 #define CHCG_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                              0xF0000000L
32085 //CHCG_PERFCOUNTER2_SELECT
32086 #define CHCG_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                             0x0
32087 #define CHCG_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                            0x14
32088 #define CHCG_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                            0x1c
32089 #define CHCG_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                               0x000003FFL
32090 #define CHCG_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
32091 #define CHCG_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                              0xF0000000L
32092 //CHCG_PERFCOUNTER3_SELECT
32093 #define CHCG_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                             0x0
32094 #define CHCG_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                            0x14
32095 #define CHCG_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                            0x1c
32096 #define CHCG_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                               0x000003FFL
32097 #define CHCG_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
32098 #define CHCG_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                              0xF0000000L
32099 //CB_PERFCOUNTER_FILTER
32100 #define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT                                                        0x0
32101 #define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT                                                           0x1
32102 #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT                                                    0x4
32103 #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT                                                       0x5
32104 #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT                                                     0xa
32105 #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT                                                        0xb
32106 #define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT                                                       0xc
32107 #define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT                                                          0xd
32108 #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT                                               0x11
32109 #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT                                                  0x12
32110 #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT                                             0x15
32111 #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT                                                0x16
32112 #define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK                                                          0x00000001L
32113 #define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK                                                             0x0000000EL
32114 #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK                                                      0x00000010L
32115 #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK                                                         0x000003E0L
32116 #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK                                                       0x00000400L
32117 #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK                                                          0x00000800L
32118 #define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK                                                         0x00001000L
32119 #define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK                                                            0x0000E000L
32120 #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK                                                 0x00020000L
32121 #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK                                                    0x001C0000L
32122 #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK                                               0x00200000L
32123 #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK                                                  0x00C00000L
32124 //CB_PERFCOUNTER0_SELECT
32125 #define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                               0x0
32126 #define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                              0xa
32127 #define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                              0x14
32128 #define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                             0x18
32129 #define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                              0x1c
32130 #define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
32131 #define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                                0x0007FC00L
32132 #define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
32133 #define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
32134 #define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                                0xF0000000L
32135 //CB_PERFCOUNTER0_SELECT1
32136 #define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                             0x0
32137 #define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                             0xa
32138 #define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                            0x18
32139 #define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                            0x1c
32140 #define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                               0x000001FFL
32141 #define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                               0x0007FC00L
32142 #define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                              0x0F000000L
32143 #define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                              0xF0000000L
32144 //CB_PERFCOUNTER1_SELECT
32145 #define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                               0x0
32146 #define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                              0x1c
32147 #define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
32148 #define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                                0xF0000000L
32149 //CB_PERFCOUNTER2_SELECT
32150 #define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                               0x0
32151 #define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                              0x1c
32152 #define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
32153 #define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                                0xF0000000L
32154 //CB_PERFCOUNTER3_SELECT
32155 #define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                               0x0
32156 #define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                              0x1c
32157 #define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
32158 #define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                                0xF0000000L
32159 //DB_PERFCOUNTER0_SELECT
32160 #define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                               0x0
32161 #define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                              0xa
32162 #define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                              0x14
32163 #define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                             0x18
32164 #define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                              0x1c
32165 #define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                 0x000003FFL
32166 #define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                                0x000FFC00L
32167 #define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
32168 #define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
32169 #define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                                0xF0000000L
32170 //DB_PERFCOUNTER0_SELECT1
32171 #define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                             0x0
32172 #define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                             0xa
32173 #define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                            0x18
32174 #define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                            0x1c
32175 #define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                               0x000003FFL
32176 #define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                               0x000FFC00L
32177 #define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                              0x0F000000L
32178 #define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                              0xF0000000L
32179 //DB_PERFCOUNTER1_SELECT
32180 #define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                               0x0
32181 #define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                              0xa
32182 #define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                              0x14
32183 #define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                             0x18
32184 #define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                              0x1c
32185 #define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                 0x000003FFL
32186 #define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                                0x000FFC00L
32187 #define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
32188 #define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
32189 #define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                                0xF0000000L
32190 //DB_PERFCOUNTER1_SELECT1
32191 #define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                             0x0
32192 #define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                             0xa
32193 #define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                            0x18
32194 #define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                            0x1c
32195 #define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                               0x000003FFL
32196 #define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                               0x000FFC00L
32197 #define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                              0x0F000000L
32198 #define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                              0xF0000000L
32199 //DB_PERFCOUNTER2_SELECT
32200 #define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                               0x0
32201 #define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT                                                              0xa
32202 #define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                              0x14
32203 #define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT                                                             0x18
32204 #define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                              0x1c
32205 #define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                 0x000003FFL
32206 #define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK                                                                0x000FFC00L
32207 #define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
32208 #define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
32209 #define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                                0xF0000000L
32210 //DB_PERFCOUNTER3_SELECT
32211 #define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                               0x0
32212 #define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT                                                              0xa
32213 #define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                              0x14
32214 #define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT                                                             0x18
32215 #define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                              0x1c
32216 #define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                 0x000003FFL
32217 #define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK                                                                0x000FFC00L
32218 #define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
32219 #define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
32220 #define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                                0xF0000000L
32221 //RLC_SPM_PERFMON_CNTL
32222 #define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT                                                                0x0
32223 #define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT                                                        0xc
32224 #define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT                                                                 0xe
32225 #define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT                                                  0x10
32226 #define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK                                                                  0x00000FFFL
32227 #define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK                                                          0x00003000L
32228 #define RLC_SPM_PERFMON_CNTL__RESERVED_MASK                                                                   0x0000C000L
32229 #define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK                                                    0xFFFF0000L
32230 //RLC_SPM_PERFMON_RING_BASE_LO
32231 #define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT                                                     0x0
32232 #define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK                                                       0xFFFFFFFFL
32233 //RLC_SPM_PERFMON_RING_BASE_HI
32234 #define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT                                                     0x0
32235 #define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT                                                         0x10
32236 #define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK                                                       0x0000FFFFL
32237 #define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK                                                           0xFFFF0000L
32238 //RLC_SPM_PERFMON_RING_SIZE
32239 #define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT                                                      0x0
32240 #define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK                                                        0xFFFFFFFFL
32241 //RLC_SPM_PERFMON_SEGMENT_SIZE
32242 #define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT                                             0x0
32243 #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT                                                        0x8
32244 #define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT                                                  0xb
32245 #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT                                                     0x10
32246 #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT                                                     0x15
32247 #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT                                                     0x1a
32248 #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT                                                         0x1f
32249 #define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK                                               0x000000FFL
32250 #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK                                                          0x00000700L
32251 #define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK                                                    0x0000F800L
32252 #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK                                                       0x001F0000L
32253 #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK                                                       0x03E00000L
32254 #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK                                                       0x7C000000L
32255 #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK                                                           0x80000000L
32256 //RLC_SPM_RING_RDPTR
32257 #define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT                                                         0x0
32258 #define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK                                                           0xFFFFFFFFL
32259 //RLC_SPM_SEGMENT_THRESHOLD
32260 #define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT                                               0x0
32261 #define RLC_SPM_SEGMENT_THRESHOLD__RESERVED__SHIFT                                                            0x8
32262 #define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK                                                 0x000000FFL
32263 #define RLC_SPM_SEGMENT_THRESHOLD__RESERVED_MASK                                                              0xFFFFFF00L
32264 //RLC_SPM_SE_MUXSEL_ADDR
32265 #define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT                                                       0x0
32266 #define RLC_SPM_SE_MUXSEL_ADDR__RESERVED__SHIFT                                                               0x9
32267 #define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK                                                         0x000001FFL
32268 #define RLC_SPM_SE_MUXSEL_ADDR__RESERVED_MASK                                                                 0xFFFFFE00L
32269 //RLC_SPM_SE_MUXSEL_DATA
32270 #define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT                                                       0x0
32271 #define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK                                                         0xFFFFFFFFL
32272 //RLC_SPM_GLOBAL_MUXSEL_ADDR
32273 #define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT                                                   0x0
32274 #define RLC_SPM_GLOBAL_MUXSEL_ADDR__RESERVED__SHIFT                                                           0x8
32275 #define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK                                                     0x000000FFL
32276 #define RLC_SPM_GLOBAL_MUXSEL_ADDR__RESERVED_MASK                                                             0xFFFFFF00L
32277 //RLC_SPM_GLOBAL_MUXSEL_DATA
32278 #define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT                                                   0x0
32279 #define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK                                                     0xFFFFFFFFL
32280 //RLC_SPM_DESER_START_SKEW
32281 #define RLC_SPM_DESER_START_SKEW__DESER_START_SKEW__SHIFT                                                     0x0
32282 #define RLC_SPM_DESER_START_SKEW__RESERVED__SHIFT                                                             0x7
32283 #define RLC_SPM_DESER_START_SKEW__DESER_START_SKEW_MASK                                                       0x0000007FL
32284 #define RLC_SPM_DESER_START_SKEW__RESERVED_MASK                                                               0xFFFFFF80L
32285 //RLC_SPM_GLOBALS_SAMPLE_SKEW
32286 #define RLC_SPM_GLOBALS_SAMPLE_SKEW__GLOBALS_SAMPLE_SKEW__SHIFT                                               0x0
32287 #define RLC_SPM_GLOBALS_SAMPLE_SKEW__RESERVED__SHIFT                                                          0x7
32288 #define RLC_SPM_GLOBALS_SAMPLE_SKEW__GLOBALS_SAMPLE_SKEW_MASK                                                 0x0000007FL
32289 #define RLC_SPM_GLOBALS_SAMPLE_SKEW__RESERVED_MASK                                                            0xFFFFFF80L
32290 //RLC_SPM_GLOBALS_MUXSEL_SKEW
32291 #define RLC_SPM_GLOBALS_MUXSEL_SKEW__GLOBALS_MUXSEL_SKEW__SHIFT                                               0x0
32292 #define RLC_SPM_GLOBALS_MUXSEL_SKEW__RESERVED__SHIFT                                                          0x7
32293 #define RLC_SPM_GLOBALS_MUXSEL_SKEW__GLOBALS_MUXSEL_SKEW_MASK                                                 0x0000007FL
32294 #define RLC_SPM_GLOBALS_MUXSEL_SKEW__RESERVED_MASK                                                            0xFFFFFF80L
32295 //RLC_SPM_SE_SAMPLE_SKEW
32296 #define RLC_SPM_SE_SAMPLE_SKEW__SE_SAMPLE_SKEW__SHIFT                                                         0x0
32297 #define RLC_SPM_SE_SAMPLE_SKEW__RESERVED__SHIFT                                                               0x7
32298 #define RLC_SPM_SE_SAMPLE_SKEW__SE_SAMPLE_SKEW_MASK                                                           0x0000007FL
32299 #define RLC_SPM_SE_SAMPLE_SKEW__RESERVED_MASK                                                                 0xFFFFFF80L
32300 //RLC_SPM_SE_MUXSEL_SKEW
32301 #define RLC_SPM_SE_MUXSEL_SKEW__SE_MUXSEL_SKEW__SHIFT                                                         0x0
32302 #define RLC_SPM_SE_MUXSEL_SKEW__RESERVED__SHIFT                                                               0x7
32303 #define RLC_SPM_SE_MUXSEL_SKEW__SE_MUXSEL_SKEW_MASK                                                           0x0000007FL
32304 #define RLC_SPM_SE_MUXSEL_SKEW__RESERVED_MASK                                                                 0xFFFFFF80L
32305 //RLC_SPM_GLB_SAMPLEDELAY_IND_ADDR
32306 #define RLC_SPM_GLB_SAMPLEDELAY_IND_ADDR__GLB_SAMPLEDELAY_INDEX__SHIFT                                        0x0
32307 #define RLC_SPM_GLB_SAMPLEDELAY_IND_ADDR__GLB_SAMPLEDELAY_INDEX_MASK                                          0xFFFFFFFFL
32308 //RLC_SPM_GLB_SAMPLEDELAY_IND_DATA
32309 #define RLC_SPM_GLB_SAMPLEDELAY_IND_DATA__data__SHIFT                                                         0x0
32310 #define RLC_SPM_GLB_SAMPLEDELAY_IND_DATA__RESERVED__SHIFT                                                     0x7
32311 #define RLC_SPM_GLB_SAMPLEDELAY_IND_DATA__data_MASK                                                           0x0000007FL
32312 #define RLC_SPM_GLB_SAMPLEDELAY_IND_DATA__RESERVED_MASK                                                       0xFFFFFF80L
32313 //RLC_SPM_SE_SAMPLEDELAY_IND_ADDR
32314 #define RLC_SPM_SE_SAMPLEDELAY_IND_ADDR__SE_SAMPLEDELAY_INDEX__SHIFT                                          0x0
32315 #define RLC_SPM_SE_SAMPLEDELAY_IND_ADDR__SE_SAMPLEDELAY_INDEX_MASK                                            0xFFFFFFFFL
32316 //RLC_SPM_SE_SAMPLEDELAY_IND_DATA
32317 #define RLC_SPM_SE_SAMPLEDELAY_IND_DATA__data__SHIFT                                                          0x0
32318 #define RLC_SPM_SE_SAMPLEDELAY_IND_DATA__RESERVED__SHIFT                                                      0x7
32319 #define RLC_SPM_SE_SAMPLEDELAY_IND_DATA__data_MASK                                                            0x0000007FL
32320 #define RLC_SPM_SE_SAMPLEDELAY_IND_DATA__RESERVED_MASK                                                        0xFFFFFF80L
32321 //RLC_SPM_RING_WRPTR
32322 #define RLC_SPM_RING_WRPTR__RESERVED__SHIFT                                                                   0x0
32323 #define RLC_SPM_RING_WRPTR__PERFMON_RING_WRPTR__SHIFT                                                         0x5
32324 #define RLC_SPM_RING_WRPTR__RESERVED_MASK                                                                     0x0000001FL
32325 #define RLC_SPM_RING_WRPTR__PERFMON_RING_WRPTR_MASK                                                           0xFFFFFFE0L
32326 //RLC_SPM_ACCUM_DATARAM_ADDR
32327 #define RLC_SPM_ACCUM_DATARAM_ADDR__addr__SHIFT                                                               0x0
32328 #define RLC_SPM_ACCUM_DATARAM_ADDR__RESERVED__SHIFT                                                           0x7
32329 #define RLC_SPM_ACCUM_DATARAM_ADDR__addr_MASK                                                                 0x0000007FL
32330 #define RLC_SPM_ACCUM_DATARAM_ADDR__RESERVED_MASK                                                             0xFFFFFF80L
32331 //RLC_SPM_ACCUM_DATARAM_DATA
32332 #define RLC_SPM_ACCUM_DATARAM_DATA__data__SHIFT                                                               0x0
32333 #define RLC_SPM_ACCUM_DATARAM_DATA__data_MASK                                                                 0xFFFFFFFFL
32334 //RLC_SPM_ACCUM_CTRLRAM_ADDR
32335 #define RLC_SPM_ACCUM_CTRLRAM_ADDR__addr__SHIFT                                                               0x0
32336 #define RLC_SPM_ACCUM_CTRLRAM_ADDR__RESERVED__SHIFT                                                           0x9
32337 #define RLC_SPM_ACCUM_CTRLRAM_ADDR__addr_MASK                                                                 0x000001FFL
32338 #define RLC_SPM_ACCUM_CTRLRAM_ADDR__RESERVED_MASK                                                             0xFFFFFE00L
32339 //RLC_SPM_ACCUM_CTRLRAM_DATA
32340 #define RLC_SPM_ACCUM_CTRLRAM_DATA__data__SHIFT                                                               0x0
32341 #define RLC_SPM_ACCUM_CTRLRAM_DATA__RESERVED__SHIFT                                                           0x8
32342 #define RLC_SPM_ACCUM_CTRLRAM_DATA__data_MASK                                                                 0x000000FFL
32343 #define RLC_SPM_ACCUM_CTRLRAM_DATA__RESERVED_MASK                                                             0xFFFFFF00L
32344 //RLC_SPM_ACCUM_STATUS
32345 #define RLC_SPM_ACCUM_STATUS__NumbSamplesCompleted__SHIFT                                                     0x0
32346 #define RLC_SPM_ACCUM_STATUS__AccumDone__SHIFT                                                                0x8
32347 #define RLC_SPM_ACCUM_STATUS__SpmDone__SHIFT                                                                  0x9
32348 #define RLC_SPM_ACCUM_STATUS__AccumOverflow__SHIFT                                                            0xa
32349 #define RLC_SPM_ACCUM_STATUS__AccumArmed__SHIFT                                                               0xb
32350 #define RLC_SPM_ACCUM_STATUS__SequenceInProgress__SHIFT                                                       0xc
32351 #define RLC_SPM_ACCUM_STATUS__FinalSequenceInProgress__SHIFT                                                  0xd
32352 #define RLC_SPM_ACCUM_STATUS__AllFifosEmpty__SHIFT                                                            0xe
32353 #define RLC_SPM_ACCUM_STATUS__FSMIsIdle__SHIFT                                                                0xf
32354 #define RLC_SPM_ACCUM_STATUS__RESERVED__SHIFT                                                                 0x10
32355 #define RLC_SPM_ACCUM_STATUS__NumbSamplesCompleted_MASK                                                       0x000000FFL
32356 #define RLC_SPM_ACCUM_STATUS__AccumDone_MASK                                                                  0x00000100L
32357 #define RLC_SPM_ACCUM_STATUS__SpmDone_MASK                                                                    0x00000200L
32358 #define RLC_SPM_ACCUM_STATUS__AccumOverflow_MASK                                                              0x00000400L
32359 #define RLC_SPM_ACCUM_STATUS__AccumArmed_MASK                                                                 0x00000800L
32360 #define RLC_SPM_ACCUM_STATUS__SequenceInProgress_MASK                                                         0x00001000L
32361 #define RLC_SPM_ACCUM_STATUS__FinalSequenceInProgress_MASK                                                    0x00002000L
32362 #define RLC_SPM_ACCUM_STATUS__AllFifosEmpty_MASK                                                              0x00004000L
32363 #define RLC_SPM_ACCUM_STATUS__FSMIsIdle_MASK                                                                  0x00008000L
32364 #define RLC_SPM_ACCUM_STATUS__RESERVED_MASK                                                                   0xFFFF0000L
32365 //RLC_SPM_ACCUM_CTRL
32366 #define RLC_SPM_ACCUM_CTRL__StrobeResetPerfMonitors__SHIFT                                                    0x0
32367 #define RLC_SPM_ACCUM_CTRL__StrobeStartAccumulation__SHIFT                                                    0x1
32368 #define RLC_SPM_ACCUM_CTRL__StrobeRearmAccum__SHIFT                                                           0x2
32369 #define RLC_SPM_ACCUM_CTRL__StrobeSpmDoneInt__SHIFT                                                           0x3
32370 #define RLC_SPM_ACCUM_CTRL__StrobeAccumDoneInt__SHIFT                                                         0x4
32371 #define RLC_SPM_ACCUM_CTRL__StrobeResetAccum__SHIFT                                                           0x5
32372 #define RLC_SPM_ACCUM_CTRL__StrobeStartSpm__SHIFT                                                             0x6
32373 #define RLC_SPM_ACCUM_CTRL__RESERVED__SHIFT                                                                   0xa
32374 #define RLC_SPM_ACCUM_CTRL__StrobeResetPerfMonitors_MASK                                                      0x00000001L
32375 #define RLC_SPM_ACCUM_CTRL__StrobeStartAccumulation_MASK                                                      0x00000002L
32376 #define RLC_SPM_ACCUM_CTRL__StrobeRearmAccum_MASK                                                             0x00000004L
32377 #define RLC_SPM_ACCUM_CTRL__StrobeSpmDoneInt_MASK                                                             0x00000008L
32378 #define RLC_SPM_ACCUM_CTRL__StrobeAccumDoneInt_MASK                                                           0x00000010L
32379 #define RLC_SPM_ACCUM_CTRL__StrobeResetAccum_MASK                                                             0x00000020L
32380 #define RLC_SPM_ACCUM_CTRL__StrobeStartSpm_MASK                                                               0x000003C0L
32381 #define RLC_SPM_ACCUM_CTRL__RESERVED_MASK                                                                     0xFFFFFC00L
32382 //RLC_SPM_ACCUM_MODE
32383 #define RLC_SPM_ACCUM_MODE__EnableAccum__SHIFT                                                                0x0
32384 #define RLC_SPM_ACCUM_MODE__AutoAccumEn__SHIFT                                                                0x1
32385 #define RLC_SPM_ACCUM_MODE__AutoSpmEn__SHIFT                                                                  0x2
32386 #define RLC_SPM_ACCUM_MODE__Globals_LoadOverride__SHIFT                                                       0x3
32387 #define RLC_SPM_ACCUM_MODE__SE0_LoadOverride__SHIFT                                                           0x4
32388 #define RLC_SPM_ACCUM_MODE__SE1_LoadOverride__SHIFT                                                           0x5
32389 #define RLC_SPM_ACCUM_MODE__AutoResetPerfmonDisable__SHIFT                                                    0x6
32390 #define RLC_SPM_ACCUM_MODE__RESERVED__SHIFT                                                                   0x7
32391 #define RLC_SPM_ACCUM_MODE__EnableAccum_MASK                                                                  0x00000001L
32392 #define RLC_SPM_ACCUM_MODE__AutoAccumEn_MASK                                                                  0x00000002L
32393 #define RLC_SPM_ACCUM_MODE__AutoSpmEn_MASK                                                                    0x00000004L
32394 #define RLC_SPM_ACCUM_MODE__Globals_LoadOverride_MASK                                                         0x00000008L
32395 #define RLC_SPM_ACCUM_MODE__SE0_LoadOverride_MASK                                                             0x00000010L
32396 #define RLC_SPM_ACCUM_MODE__SE1_LoadOverride_MASK                                                             0x00000020L
32397 #define RLC_SPM_ACCUM_MODE__AutoResetPerfmonDisable_MASK                                                      0x00000040L
32398 #define RLC_SPM_ACCUM_MODE__RESERVED_MASK                                                                     0xFFFFFF80L
32399 //RLC_SPM_ACCUM_THRESHOLD
32400 #define RLC_SPM_ACCUM_THRESHOLD__Threshold__SHIFT                                                             0x0
32401 #define RLC_SPM_ACCUM_THRESHOLD__RESERVED__SHIFT                                                              0x10
32402 #define RLC_SPM_ACCUM_THRESHOLD__Threshold_MASK                                                               0x0000FFFFL
32403 #define RLC_SPM_ACCUM_THRESHOLD__RESERVED_MASK                                                                0xFFFF0000L
32404 //RLC_SPM_ACCUM_SAMPLES_REQUESTED
32405 #define RLC_SPM_ACCUM_SAMPLES_REQUESTED__SamplesRequested__SHIFT                                              0x0
32406 #define RLC_SPM_ACCUM_SAMPLES_REQUESTED__RESERVED__SHIFT                                                      0x8
32407 #define RLC_SPM_ACCUM_SAMPLES_REQUESTED__SamplesRequested_MASK                                                0x000000FFL
32408 #define RLC_SPM_ACCUM_SAMPLES_REQUESTED__RESERVED_MASK                                                        0xFFFFFF00L
32409 //RLC_SPM_ACCUM_DATARAM_WRCOUNT
32410 #define RLC_SPM_ACCUM_DATARAM_WRCOUNT__DataRamWrCount__SHIFT                                                  0x0
32411 #define RLC_SPM_ACCUM_DATARAM_WRCOUNT__RESERVED__SHIFT                                                        0x13
32412 #define RLC_SPM_ACCUM_DATARAM_WRCOUNT__DataRamWrCount_MASK                                                    0x0007FFFFL
32413 #define RLC_SPM_ACCUM_DATARAM_WRCOUNT__RESERVED_MASK                                                          0xFFF80000L
32414 //RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE
32415 #define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT                                              0x0
32416 #define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT                                              0x8
32417 #define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT                                              0x10
32418 #define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE3_NUM_LINE__SHIFT                                              0x18
32419 #define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE0_NUM_LINE_MASK                                                0x000000FFL
32420 #define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE1_NUM_LINE_MASK                                                0x0000FF00L
32421 #define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE2_NUM_LINE_MASK                                                0x00FF0000L
32422 #define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE3_NUM_LINE_MASK                                                0xFF000000L
32423 //RLC_SPM_PERFMON_GLB_SEGMENT_SIZE
32424 #define RLC_SPM_PERFMON_GLB_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT                                         0x0
32425 #define RLC_SPM_PERFMON_GLB_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT                                              0x8
32426 #define RLC_SPM_PERFMON_GLB_SEGMENT_SIZE__RESERVED__SHIFT                                                     0x10
32427 #define RLC_SPM_PERFMON_GLB_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK                                           0x000000FFL
32428 #define RLC_SPM_PERFMON_GLB_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK                                                0x0000FF00L
32429 #define RLC_SPM_PERFMON_GLB_SEGMENT_SIZE__RESERVED_MASK                                                       0xFFFF0000L
32430 //RLC_SPM_VIRT_CTRL
32431 #define RLC_SPM_VIRT_CTRL__PauseSpmSamplingRequest__SHIFT                                                     0x0
32432 #define RLC_SPM_VIRT_CTRL__PauseSpmSamplingRequest_MASK                                                       0x00000001L
32433 //RLC_SPM_VIRT_STATUS
32434 #define RLC_SPM_VIRT_STATUS__SpmSamplingPaused__SHIFT                                                         0x0
32435 #define RLC_SPM_VIRT_STATUS__SpmSamplingPaused_MASK                                                           0x00000001L
32436 //RLC_PERFMON_CNTL
32437 #define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                                0x0
32438 #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT                                                        0xa
32439 #define RLC_PERFMON_CNTL__PERFMON_STATE_MASK                                                                  0x00000007L
32440 #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK                                                          0x00000400L
32441 //RLC_PERFCOUNTER0_SELECT
32442 #define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT                                                    0x0
32443 #define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK                                                      0x000000FFL
32444 //RLC_PERFCOUNTER1_SELECT
32445 #define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT                                                    0x0
32446 #define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK                                                      0x000000FFL
32447 //RLC_GPU_IOV_PERF_CNT_CNTL
32448 #define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE__SHIFT                                                              0x0
32449 #define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT__SHIFT                                                         0x1
32450 #define RLC_GPU_IOV_PERF_CNT_CNTL__RESET__SHIFT                                                               0x2
32451 #define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED__SHIFT                                                            0x3
32452 #define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE_MASK                                                                0x00000001L
32453 #define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT_MASK                                                           0x00000002L
32454 #define RLC_GPU_IOV_PERF_CNT_CNTL__RESET_MASK                                                                 0x00000004L
32455 #define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED_MASK                                                              0xFFFFFFF8L
32456 //RLC_GPU_IOV_PERF_CNT_WR_ADDR
32457 #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID__SHIFT                                                             0x0
32458 #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID__SHIFT                                                           0x4
32459 #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED__SHIFT                                                         0x6
32460 #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID_MASK                                                               0x0000000FL
32461 #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID_MASK                                                             0x00000030L
32462 #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED_MASK                                                           0xFFFFFFC0L
32463 //RLC_GPU_IOV_PERF_CNT_WR_DATA
32464 #define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA__SHIFT                                                             0x0
32465 #define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA_MASK                                                               0xFFFFFFFFL
32466 //RLC_GPU_IOV_PERF_CNT_RD_ADDR
32467 #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID__SHIFT                                                             0x0
32468 #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID__SHIFT                                                           0x4
32469 #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED__SHIFT                                                         0x6
32470 #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID_MASK                                                               0x0000000FL
32471 #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID_MASK                                                             0x00000030L
32472 #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED_MASK                                                           0xFFFFFFC0L
32473 //RLC_GPU_IOV_PERF_CNT_RD_DATA
32474 #define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA__SHIFT                                                             0x0
32475 #define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA_MASK                                                               0xFFFFFFFFL
32476 //RLC_PERFMON_CLK_CNTL
32477 #define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE__SHIFT                                                      0x0
32478 #define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK                                                        0x00000001L
32479 //RLC_PERFMON_CLK_CNTL_UCODE
32480 #define RLC_PERFMON_CLK_CNTL_UCODE__PERFMON_CLOCK_STATE__SHIFT                                                0x0
32481 #define RLC_PERFMON_CLK_CNTL_UCODE__PERFMON_CLOCK_STATE_MASK                                                  0x00000001L
32482 //RMI_PERFCOUNTER0_SELECT
32483 #define RMI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
32484 #define RMI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
32485 #define RMI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                             0x14
32486 #define RMI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                            0x18
32487 #define RMI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                             0x1c
32488 #define RMI_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000001FFL
32489 #define RMI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x0007FC00L
32490 #define RMI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
32491 #define RMI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
32492 #define RMI_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                               0xF0000000L
32493 //RMI_PERFCOUNTER0_SELECT1
32494 #define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
32495 #define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
32496 #define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                           0x18
32497 #define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
32498 #define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000001FFL
32499 #define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x0007FC00L
32500 #define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
32501 #define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
32502 //RMI_PERFCOUNTER1_SELECT
32503 #define RMI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
32504 #define RMI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                             0x1c
32505 #define RMI_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000001FFL
32506 #define RMI_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                               0xF0000000L
32507 //RMI_PERFCOUNTER2_SELECT
32508 #define RMI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                              0x0
32509 #define RMI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT                                                             0xa
32510 #define RMI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                             0x14
32511 #define RMI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT                                                            0x18
32512 #define RMI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                             0x1c
32513 #define RMI_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                0x000001FFL
32514 #define RMI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK                                                               0x0007FC00L
32515 #define RMI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
32516 #define RMI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
32517 #define RMI_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                               0xF0000000L
32518 //RMI_PERFCOUNTER2_SELECT1
32519 #define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT                                                            0x0
32520 #define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT                                                            0xa
32521 #define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT                                                           0x18
32522 #define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
32523 #define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK                                                              0x000001FFL
32524 #define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK                                                              0x0007FC00L
32525 #define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
32526 #define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
32527 //RMI_PERFCOUNTER3_SELECT
32528 #define RMI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                              0x0
32529 #define RMI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                             0x1c
32530 #define RMI_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                0x000001FFL
32531 #define RMI_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                               0xF0000000L
32532 //RMI_PERF_COUNTER_CNTL
32533 #define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL__SHIFT                                                 0x0
32534 #define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL__SHIFT                                                 0x2
32535 #define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL__SHIFT                                                          0x4
32536 #define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0__SHIFT                                                 0x6
32537 #define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1__SHIFT                                                 0x8
32538 #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID__SHIFT                                                        0xa
32539 #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID__SHIFT                                                       0xe
32540 #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD__SHIFT                                     0x13
32541 #define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET__SHIFT                                                         0x19
32542 #define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL__SHIFT                                                       0x1a
32543 #define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL_MASK                                                   0x00000003L
32544 #define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL_MASK                                                   0x0000000CL
32545 #define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL_MASK                                                            0x00000030L
32546 #define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0_MASK                                                   0x000000C0L
32547 #define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1_MASK                                                   0x00000300L
32548 #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID_MASK                                                          0x00003C00L
32549 #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID_MASK                                                         0x0007C000L
32550 #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD_MASK                                       0x01F80000L
32551 #define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET_MASK                                                           0x02000000L
32552 #define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL_MASK                                                         0x04000000L
32553 //GCR_PERFCOUNTER0_SELECT
32554 #define GCR_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
32555 #define GCR_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
32556 #define GCR_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                             0x14
32557 #define GCR_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                            0x18
32558 #define GCR_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                             0x1c
32559 #define GCR_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000001FFL
32560 #define GCR_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x0007FC00L
32561 #define GCR_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
32562 #define GCR_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
32563 #define GCR_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                               0xF0000000L
32564 //GCR_PERFCOUNTER0_SELECT1
32565 #define GCR_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
32566 #define GCR_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
32567 #define GCR_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                           0x18
32568 #define GCR_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
32569 #define GCR_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000001FFL
32570 #define GCR_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x0007FC00L
32571 #define GCR_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
32572 #define GCR_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
32573 //GCR_PERFCOUNTER1_SELECT
32574 #define GCR_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
32575 #define GCR_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                             0x18
32576 #define GCR_PERFCOUNTER1_SELECT__CNTL_MODE__SHIFT                                                             0x1c
32577 #define GCR_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000001FFL
32578 #define GCR_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                               0x0F000000L
32579 #define GCR_PERFCOUNTER1_SELECT__CNTL_MODE_MASK                                                               0xF0000000L
32580 //UTCL1_PERFCOUNTER0_SELECT
32581 #define UTCL1_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                            0x0
32582 #define UTCL1_PERFCOUNTER0_SELECT__COUNTER_MODE__SHIFT                                                        0x1c
32583 #define UTCL1_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                              0x000003FFL
32584 #define UTCL1_PERFCOUNTER0_SELECT__COUNTER_MODE_MASK                                                          0xF0000000L
32585 //UTCL1_PERFCOUNTER1_SELECT
32586 #define UTCL1_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                            0x0
32587 #define UTCL1_PERFCOUNTER1_SELECT__COUNTER_MODE__SHIFT                                                        0x1c
32588 #define UTCL1_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                              0x000003FFL
32589 #define UTCL1_PERFCOUNTER1_SELECT__COUNTER_MODE_MASK                                                          0xF0000000L
32590 //PA_PH_PERFCOUNTER0_SELECT
32591 #define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                            0x0
32592 #define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                           0xa
32593 #define PA_PH_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                           0x14
32594 #define PA_PH_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                          0x18
32595 #define PA_PH_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                           0x1c
32596 #define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                              0x000003FFL
32597 #define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
32598 #define PA_PH_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
32599 #define PA_PH_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                            0x0F000000L
32600 #define PA_PH_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                             0xF0000000L
32601 //PA_PH_PERFCOUNTER0_SELECT1
32602 #define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                          0x0
32603 #define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                          0xa
32604 #define PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                         0x18
32605 #define PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                         0x1c
32606 #define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
32607 #define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
32608 #define PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                           0x0F000000L
32609 #define PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                           0xF0000000L
32610 //PA_PH_PERFCOUNTER1_SELECT
32611 #define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                            0x0
32612 #define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                           0xa
32613 #define PA_PH_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                           0x14
32614 #define PA_PH_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                          0x18
32615 #define PA_PH_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                           0x1c
32616 #define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                              0x000003FFL
32617 #define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
32618 #define PA_PH_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
32619 #define PA_PH_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                            0x0F000000L
32620 #define PA_PH_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                             0xF0000000L
32621 //PA_PH_PERFCOUNTER2_SELECT
32622 #define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                            0x0
32623 #define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT                                                           0xa
32624 #define PA_PH_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                           0x14
32625 #define PA_PH_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT                                                          0x18
32626 #define PA_PH_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                           0x1c
32627 #define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                              0x000003FFL
32628 #define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
32629 #define PA_PH_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
32630 #define PA_PH_PERFCOUNTER2_SELECT__PERF_MODE1_MASK                                                            0x0F000000L
32631 #define PA_PH_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                             0xF0000000L
32632 //PA_PH_PERFCOUNTER3_SELECT
32633 #define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                            0x0
32634 #define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT                                                           0xa
32635 #define PA_PH_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                           0x14
32636 #define PA_PH_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT                                                          0x18
32637 #define PA_PH_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                           0x1c
32638 #define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                              0x000003FFL
32639 #define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
32640 #define PA_PH_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
32641 #define PA_PH_PERFCOUNTER3_SELECT__PERF_MODE1_MASK                                                            0x0F000000L
32642 #define PA_PH_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                             0xF0000000L
32643 //PA_PH_PERFCOUNTER4_SELECT
32644 #define PA_PH_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT                                                            0x0
32645 #define PA_PH_PERFCOUNTER4_SELECT__PERF_SEL_MASK                                                              0x000003FFL
32646 //PA_PH_PERFCOUNTER5_SELECT
32647 #define PA_PH_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT                                                            0x0
32648 #define PA_PH_PERFCOUNTER5_SELECT__PERF_SEL_MASK                                                              0x000003FFL
32649 //PA_PH_PERFCOUNTER6_SELECT
32650 #define PA_PH_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT                                                            0x0
32651 #define PA_PH_PERFCOUNTER6_SELECT__PERF_SEL_MASK                                                              0x000003FFL
32652 //PA_PH_PERFCOUNTER7_SELECT
32653 #define PA_PH_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT                                                            0x0
32654 #define PA_PH_PERFCOUNTER7_SELECT__PERF_SEL_MASK                                                              0x000003FFL
32655 //PA_PH_PERFCOUNTER1_SELECT1
32656 #define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                          0x0
32657 #define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                          0xa
32658 #define PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                         0x18
32659 #define PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                         0x1c
32660 #define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
32661 #define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
32662 #define PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                           0x0F000000L
32663 #define PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                           0xF0000000L
32664 //PA_PH_PERFCOUNTER2_SELECT1
32665 #define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT                                                          0x0
32666 #define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT                                                          0xa
32667 #define PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT                                                         0x18
32668 #define PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT                                                         0x1c
32669 #define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
32670 #define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
32671 #define PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK                                                           0x0F000000L
32672 #define PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK                                                           0xF0000000L
32673 //PA_PH_PERFCOUNTER3_SELECT1
32674 #define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT                                                          0x0
32675 #define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT                                                          0xa
32676 #define PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT                                                         0x18
32677 #define PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT                                                         0x1c
32678 #define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
32679 #define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
32680 #define PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK                                                           0x0F000000L
32681 #define PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK                                                           0xF0000000L
32682 //GL1A_PERFCOUNTER0_SELECT
32683 #define GL1A_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                             0x0
32684 #define GL1A_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                            0xa
32685 #define GL1A_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                            0x14
32686 #define GL1A_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                           0x18
32687 #define GL1A_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                            0x1c
32688 #define GL1A_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                               0x000003FFL
32689 #define GL1A_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                              0x000FFC00L
32690 #define GL1A_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
32691 #define GL1A_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                             0x0F000000L
32692 #define GL1A_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                              0xF0000000L
32693 //GL1A_PERFCOUNTER0_SELECT1
32694 #define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                           0x0
32695 #define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                           0xa
32696 #define GL1A_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                          0x18
32697 #define GL1A_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                          0x1c
32698 #define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                             0x000003FFL
32699 #define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                             0x000FFC00L
32700 #define GL1A_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                            0x0F000000L
32701 #define GL1A_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                            0xF0000000L
32702 //GL1A_PERFCOUNTER1_SELECT
32703 #define GL1A_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                             0x0
32704 #define GL1A_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                            0x14
32705 #define GL1A_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                            0x1c
32706 #define GL1A_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                               0x000003FFL
32707 #define GL1A_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
32708 #define GL1A_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                              0xF0000000L
32709 //GL1A_PERFCOUNTER2_SELECT
32710 #define GL1A_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                             0x0
32711 #define GL1A_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                            0x14
32712 #define GL1A_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                            0x1c
32713 #define GL1A_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                               0x000003FFL
32714 #define GL1A_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
32715 #define GL1A_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                              0xF0000000L
32716 //GL1A_PERFCOUNTER3_SELECT
32717 #define GL1A_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                             0x0
32718 #define GL1A_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                            0x14
32719 #define GL1A_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                            0x1c
32720 #define GL1A_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                               0x000003FFL
32721 #define GL1A_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
32722 #define GL1A_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                              0xF0000000L
32723 //CHA_PERFCOUNTER0_SELECT
32724 #define CHA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
32725 #define CHA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
32726 #define CHA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                             0x14
32727 #define CHA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                            0x18
32728 #define CHA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                             0x1c
32729 #define CHA_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000003FFL
32730 #define CHA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
32731 #define CHA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
32732 #define CHA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
32733 #define CHA_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                               0xF0000000L
32734 //CHA_PERFCOUNTER0_SELECT1
32735 #define CHA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
32736 #define CHA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
32737 #define CHA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                           0x18
32738 #define CHA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                           0x1c
32739 #define CHA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
32740 #define CHA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
32741 #define CHA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                             0x0F000000L
32742 #define CHA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                             0xF0000000L
32743 //CHA_PERFCOUNTER1_SELECT
32744 #define CHA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
32745 #define CHA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                             0x14
32746 #define CHA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                             0x1c
32747 #define CHA_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000003FFL
32748 #define CHA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
32749 #define CHA_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                               0xF0000000L
32750 //CHA_PERFCOUNTER2_SELECT
32751 #define CHA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                              0x0
32752 #define CHA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                             0x14
32753 #define CHA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                             0x1c
32754 #define CHA_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                0x000003FFL
32755 #define CHA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
32756 #define CHA_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                               0xF0000000L
32757 //CHA_PERFCOUNTER3_SELECT
32758 #define CHA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                              0x0
32759 #define CHA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                             0x14
32760 #define CHA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                             0x1c
32761 #define CHA_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                0x000003FFL
32762 #define CHA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
32763 #define CHA_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                               0xF0000000L
32764 //GUS_PERFCOUNTER2_SELECT
32765 #define GUS_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                              0x0
32766 #define GUS_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT                                                             0xa
32767 #define GUS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                             0x14
32768 #define GUS_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT                                                            0x18
32769 #define GUS_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                             0x1c
32770 #define GUS_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                0x000003FFL
32771 #define GUS_PERFCOUNTER2_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
32772 #define GUS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
32773 #define GUS_PERFCOUNTER2_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
32774 #define GUS_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                               0xF0000000L
32775 //GUS_PERFCOUNTER2_SELECT1
32776 #define GUS_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT                                                            0x0
32777 #define GUS_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT                                                            0xa
32778 #define GUS_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT                                                           0x18
32779 #define GUS_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
32780 #define GUS_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
32781 #define GUS_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
32782 #define GUS_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
32783 #define GUS_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
32784 //GUS_PERFCOUNTER2_MODE
32785 #define GUS_PERFCOUNTER2_MODE__COMPARE_MODE0__SHIFT                                                           0x0
32786 #define GUS_PERFCOUNTER2_MODE__COMPARE_MODE1__SHIFT                                                           0x2
32787 #define GUS_PERFCOUNTER2_MODE__COMPARE_MODE2__SHIFT                                                           0x4
32788 #define GUS_PERFCOUNTER2_MODE__COMPARE_MODE3__SHIFT                                                           0x6
32789 #define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE0__SHIFT                                                          0x8
32790 #define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE1__SHIFT                                                          0xc
32791 #define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE2__SHIFT                                                          0x10
32792 #define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE3__SHIFT                                                          0x14
32793 #define GUS_PERFCOUNTER2_MODE__COMPARE_MODE0_MASK                                                             0x00000003L
32794 #define GUS_PERFCOUNTER2_MODE__COMPARE_MODE1_MASK                                                             0x0000000CL
32795 #define GUS_PERFCOUNTER2_MODE__COMPARE_MODE2_MASK                                                             0x00000030L
32796 #define GUS_PERFCOUNTER2_MODE__COMPARE_MODE3_MASK                                                             0x000000C0L
32797 #define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE0_MASK                                                            0x00000F00L
32798 #define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE1_MASK                                                            0x0000F000L
32799 #define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE2_MASK                                                            0x000F0000L
32800 #define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE3_MASK                                                            0x00F00000L
32801 
32802 
32803 // addressBlock: gc_gcatcl2pfcntldec
32804 //GC_ATC_L2_PERFCOUNTER0_CFG
32805 #define GC_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                           0x0
32806 #define GC_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                       0x8
32807 #define GC_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                          0x18
32808 #define GC_ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                             0x1c
32809 #define GC_ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                              0x1d
32810 #define GC_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                             0x000000FFL
32811 #define GC_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                         0x0000FF00L
32812 #define GC_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                            0x0F000000L
32813 #define GC_ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK                                                               0x10000000L
32814 #define GC_ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK                                                                0x20000000L
32815 //GC_ATC_L2_PERFCOUNTER1_CFG
32816 #define GC_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                           0x0
32817 #define GC_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                       0x8
32818 #define GC_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                          0x18
32819 #define GC_ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                             0x1c
32820 #define GC_ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                              0x1d
32821 #define GC_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                             0x000000FFL
32822 #define GC_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                         0x0000FF00L
32823 #define GC_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                            0x0F000000L
32824 #define GC_ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK                                                               0x10000000L
32825 #define GC_ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK                                                                0x20000000L
32826 //GC_ATC_L2_PERFCOUNTER_RSLT_CNTL
32827 #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                           0x0
32828 #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                 0x8
32829 #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                  0x10
32830 #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                    0x18
32831 #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                     0x19
32832 #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                          0x1a
32833 #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                             0x0000000FL
32834 #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                   0x0000FF00L
32835 #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                    0x00FF0000L
32836 #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                      0x01000000L
32837 #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                       0x02000000L
32838 #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                            0x04000000L
32839 
32840 
32841 // addressBlock: gc_gcvml2pldec
32842 //GCMC_VM_L2_PERFCOUNTER0_CFG
32843 #define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                          0x0
32844 #define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                      0x8
32845 #define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                         0x18
32846 #define GCMC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                            0x1c
32847 #define GCMC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                             0x1d
32848 #define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                            0x000000FFL
32849 #define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
32850 #define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                           0x0F000000L
32851 #define GCMC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK                                                              0x10000000L
32852 #define GCMC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK                                                               0x20000000L
32853 //GCMC_VM_L2_PERFCOUNTER1_CFG
32854 #define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                          0x0
32855 #define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                      0x8
32856 #define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                         0x18
32857 #define GCMC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                            0x1c
32858 #define GCMC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                             0x1d
32859 #define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                            0x000000FFL
32860 #define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
32861 #define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                           0x0F000000L
32862 #define GCMC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK                                                              0x10000000L
32863 #define GCMC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK                                                               0x20000000L
32864 //GCMC_VM_L2_PERFCOUNTER2_CFG
32865 #define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                          0x0
32866 #define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                      0x8
32867 #define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                         0x18
32868 #define GCMC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                            0x1c
32869 #define GCMC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                             0x1d
32870 #define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                            0x000000FFL
32871 #define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
32872 #define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                           0x0F000000L
32873 #define GCMC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK                                                              0x10000000L
32874 #define GCMC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK                                                               0x20000000L
32875 //GCMC_VM_L2_PERFCOUNTER3_CFG
32876 #define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT                                                          0x0
32877 #define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT                                                      0x8
32878 #define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT                                                         0x18
32879 #define GCMC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT                                                            0x1c
32880 #define GCMC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT                                                             0x1d
32881 #define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK                                                            0x000000FFL
32882 #define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
32883 #define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK                                                           0x0F000000L
32884 #define GCMC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK                                                              0x10000000L
32885 #define GCMC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK                                                               0x20000000L
32886 //GCMC_VM_L2_PERFCOUNTER4_CFG
32887 #define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT                                                          0x0
32888 #define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT                                                      0x8
32889 #define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT                                                         0x18
32890 #define GCMC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT                                                            0x1c
32891 #define GCMC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT                                                             0x1d
32892 #define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK                                                            0x000000FFL
32893 #define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
32894 #define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK                                                           0x0F000000L
32895 #define GCMC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK                                                              0x10000000L
32896 #define GCMC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK                                                               0x20000000L
32897 //GCMC_VM_L2_PERFCOUNTER5_CFG
32898 #define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT                                                          0x0
32899 #define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT                                                      0x8
32900 #define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT                                                         0x18
32901 #define GCMC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT                                                            0x1c
32902 #define GCMC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT                                                             0x1d
32903 #define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK                                                            0x000000FFL
32904 #define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
32905 #define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK                                                           0x0F000000L
32906 #define GCMC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK                                                              0x10000000L
32907 #define GCMC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK                                                               0x20000000L
32908 //GCMC_VM_L2_PERFCOUNTER6_CFG
32909 #define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT                                                          0x0
32910 #define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT                                                      0x8
32911 #define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT                                                         0x18
32912 #define GCMC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT                                                            0x1c
32913 #define GCMC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT                                                             0x1d
32914 #define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK                                                            0x000000FFL
32915 #define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
32916 #define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK                                                           0x0F000000L
32917 #define GCMC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK                                                              0x10000000L
32918 #define GCMC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK                                                               0x20000000L
32919 //GCMC_VM_L2_PERFCOUNTER7_CFG
32920 #define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT                                                          0x0
32921 #define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT                                                      0x8
32922 #define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT                                                         0x18
32923 #define GCMC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT                                                            0x1c
32924 #define GCMC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT                                                             0x1d
32925 #define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK                                                            0x000000FFL
32926 #define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
32927 #define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK                                                           0x0F000000L
32928 #define GCMC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK                                                              0x10000000L
32929 #define GCMC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK                                                               0x20000000L
32930 //GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL
32931 #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                          0x0
32932 #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                0x8
32933 #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                 0x10
32934 #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                   0x18
32935 #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                    0x19
32936 #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                         0x1a
32937 #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                            0x0000000FL
32938 #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                  0x0000FF00L
32939 #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                   0x00FF0000L
32940 #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                     0x01000000L
32941 #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                      0x02000000L
32942 #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                           0x04000000L
32943 
32944 
32945 // addressBlock: gc_gcvml2perfsdec
32946 //GCVML2_PERFCOUNTER2_0_SELECT
32947 #define GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL__SHIFT                                                         0x0
32948 #define GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL1__SHIFT                                                        0xa
32949 #define GCVML2_PERFCOUNTER2_0_SELECT__CNTR_MODE__SHIFT                                                        0x14
32950 #define GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE1__SHIFT                                                       0x18
32951 #define GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE__SHIFT                                                        0x1c
32952 #define GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL_MASK                                                           0x000003FFL
32953 #define GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL1_MASK                                                          0x000FFC00L
32954 #define GCVML2_PERFCOUNTER2_0_SELECT__CNTR_MODE_MASK                                                          0x00F00000L
32955 #define GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE1_MASK                                                         0x0F000000L
32956 #define GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE_MASK                                                          0xF0000000L
32957 //GCVML2_PERFCOUNTER2_1_SELECT
32958 #define GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL__SHIFT                                                         0x0
32959 #define GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL1__SHIFT                                                        0xa
32960 #define GCVML2_PERFCOUNTER2_1_SELECT__CNTR_MODE__SHIFT                                                        0x14
32961 #define GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE1__SHIFT                                                       0x18
32962 #define GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE__SHIFT                                                        0x1c
32963 #define GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL_MASK                                                           0x000003FFL
32964 #define GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL1_MASK                                                          0x000FFC00L
32965 #define GCVML2_PERFCOUNTER2_1_SELECT__CNTR_MODE_MASK                                                          0x00F00000L
32966 #define GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE1_MASK                                                         0x0F000000L
32967 #define GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE_MASK                                                          0xF0000000L
32968 //GCVML2_PERFCOUNTER2_0_SELECT1
32969 #define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL2__SHIFT                                                       0x0
32970 #define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL3__SHIFT                                                       0xa
32971 #define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE3__SHIFT                                                      0x18
32972 #define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE2__SHIFT                                                      0x1c
32973 #define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL2_MASK                                                         0x000003FFL
32974 #define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL3_MASK                                                         0x000FFC00L
32975 #define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE3_MASK                                                        0x0F000000L
32976 #define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE2_MASK                                                        0xF0000000L
32977 //GCVML2_PERFCOUNTER2_1_SELECT1
32978 #define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL2__SHIFT                                                       0x0
32979 #define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL3__SHIFT                                                       0xa
32980 #define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE3__SHIFT                                                      0x18
32981 #define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE2__SHIFT                                                      0x1c
32982 #define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL2_MASK                                                         0x000003FFL
32983 #define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL3_MASK                                                         0x000FFC00L
32984 #define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE3_MASK                                                        0x0F000000L
32985 #define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE2_MASK                                                        0xF0000000L
32986 //GCVML2_PERFCOUNTER2_0_MODE
32987 #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE0__SHIFT                                                      0x0
32988 #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE1__SHIFT                                                      0x2
32989 #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE2__SHIFT                                                      0x4
32990 #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE3__SHIFT                                                      0x6
32991 #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE0__SHIFT                                                     0x8
32992 #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE1__SHIFT                                                     0xc
32993 #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE2__SHIFT                                                     0x10
32994 #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE3__SHIFT                                                     0x14
32995 #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE0_MASK                                                        0x00000003L
32996 #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE1_MASK                                                        0x0000000CL
32997 #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE2_MASK                                                        0x00000030L
32998 #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE3_MASK                                                        0x000000C0L
32999 #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE0_MASK                                                       0x00000F00L
33000 #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE1_MASK                                                       0x0000F000L
33001 #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE2_MASK                                                       0x000F0000L
33002 #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE3_MASK                                                       0x00F00000L
33003 //GCVML2_PERFCOUNTER2_1_MODE
33004 #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE0__SHIFT                                                      0x0
33005 #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE1__SHIFT                                                      0x2
33006 #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE2__SHIFT                                                      0x4
33007 #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE3__SHIFT                                                      0x6
33008 #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE0__SHIFT                                                     0x8
33009 #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE1__SHIFT                                                     0xc
33010 #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE2__SHIFT                                                     0x10
33011 #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE3__SHIFT                                                     0x14
33012 #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE0_MASK                                                        0x00000003L
33013 #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE1_MASK                                                        0x0000000CL
33014 #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE2_MASK                                                        0x00000030L
33015 #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE3_MASK                                                        0x000000C0L
33016 #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE0_MASK                                                       0x00000F00L
33017 #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE1_MASK                                                       0x0000F000L
33018 #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE2_MASK                                                       0x000F0000L
33019 #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE3_MASK                                                       0x00F00000L
33020 
33021 
33022 // addressBlock: gc_gcatcl2perfsdec
33023 //GC_ATC_L2_PERFCOUNTER2_SELECT
33024 #define GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                        0x0
33025 #define GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT                                                       0xa
33026 #define GC_ATC_L2_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                       0x14
33027 #define GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT                                                      0x18
33028 #define GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                       0x1c
33029 #define GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                          0x000003FFL
33030 #define GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_SEL1_MASK                                                         0x000FFC00L
33031 #define GC_ATC_L2_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                         0x00F00000L
33032 #define GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_MODE1_MASK                                                        0x0F000000L
33033 #define GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                         0xF0000000L
33034 //GC_ATC_L2_PERFCOUNTER2_SELECT1
33035 #define GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT                                                      0x0
33036 #define GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT                                                      0xa
33037 #define GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT                                                     0x18
33038 #define GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT                                                     0x1c
33039 #define GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK                                                        0x000003FFL
33040 #define GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK                                                        0x000FFC00L
33041 #define GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK                                                       0x0F000000L
33042 #define GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK                                                       0xF0000000L
33043 //GC_ATC_L2_PERFCOUNTER2_MODE
33044 #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE0__SHIFT                                                     0x0
33045 #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE1__SHIFT                                                     0x2
33046 #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE2__SHIFT                                                     0x4
33047 #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE3__SHIFT                                                     0x6
33048 #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE0__SHIFT                                                    0x8
33049 #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE1__SHIFT                                                    0xc
33050 #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE2__SHIFT                                                    0x10
33051 #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE3__SHIFT                                                    0x14
33052 #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE0_MASK                                                       0x00000003L
33053 #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE1_MASK                                                       0x0000000CL
33054 #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE2_MASK                                                       0x00000030L
33055 #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE3_MASK                                                       0x000000C0L
33056 #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE0_MASK                                                      0x00000F00L
33057 #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE1_MASK                                                      0x0000F000L
33058 #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE2_MASK                                                      0x000F0000L
33059 #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE3_MASK                                                      0x00F00000L
33060 
33061 
33062 // addressBlock: gc_rlcdec
33063 //RLC_CNTL
33064 #define RLC_CNTL__RLC_ENABLE_F32__SHIFT                                                                       0x0
33065 #define RLC_CNTL__FORCE_RETRY__SHIFT                                                                          0x1
33066 #define RLC_CNTL__READ_CACHE_DISABLE__SHIFT                                                                   0x2
33067 #define RLC_CNTL__RLC_STEP_F32__SHIFT                                                                         0x3
33068 #define RLC_CNTL__RESERVED__SHIFT                                                                             0x4
33069 #define RLC_CNTL__RLC_ENABLE_F32_MASK                                                                         0x00000001L
33070 #define RLC_CNTL__FORCE_RETRY_MASK                                                                            0x00000002L
33071 #define RLC_CNTL__READ_CACHE_DISABLE_MASK                                                                     0x00000004L
33072 #define RLC_CNTL__RLC_STEP_F32_MASK                                                                           0x00000008L
33073 #define RLC_CNTL__RESERVED_MASK                                                                               0xFFFFFFF0L
33074 //RLC_F32_UCODE_VERSION
33075 #define RLC_F32_UCODE_VERSION__THREAD0_VERSION__SHIFT                                                         0x0
33076 #define RLC_F32_UCODE_VERSION__THREAD1_VERSION__SHIFT                                                         0xa
33077 #define RLC_F32_UCODE_VERSION__THREAD2_VERSION__SHIFT                                                         0x14
33078 #define RLC_F32_UCODE_VERSION__THREAD0_VERSION_MASK                                                           0x000003FFL
33079 #define RLC_F32_UCODE_VERSION__THREAD1_VERSION_MASK                                                           0x000FFC00L
33080 #define RLC_F32_UCODE_VERSION__THREAD2_VERSION_MASK                                                           0x3FF00000L
33081 //RLC_STAT
33082 #define RLC_STAT__RLC_BUSY__SHIFT                                                                             0x0
33083 #define RLC_STAT__RLC_SRM_BUSY__SHIFT                                                                         0x1
33084 #define RLC_STAT__RLC_GPM_BUSY__SHIFT                                                                         0x2
33085 #define RLC_STAT__RLC_SPM_BUSY__SHIFT                                                                         0x3
33086 #define RLC_STAT__MC_BUSY__SHIFT                                                                              0x4
33087 #define RLC_STAT__RLC_THREAD_0_BUSY__SHIFT                                                                    0x5
33088 #define RLC_STAT__RLC_THREAD_1_BUSY__SHIFT                                                                    0x6
33089 #define RLC_STAT__RLC_THREAD_2_BUSY__SHIFT                                                                    0x7
33090 #define RLC_STAT__RESERVED__SHIFT                                                                             0x8
33091 #define RLC_STAT__RLC_BUSY_MASK                                                                               0x00000001L
33092 #define RLC_STAT__RLC_SRM_BUSY_MASK                                                                           0x00000002L
33093 #define RLC_STAT__RLC_GPM_BUSY_MASK                                                                           0x00000004L
33094 #define RLC_STAT__RLC_SPM_BUSY_MASK                                                                           0x00000008L
33095 #define RLC_STAT__MC_BUSY_MASK                                                                                0x00000010L
33096 #define RLC_STAT__RLC_THREAD_0_BUSY_MASK                                                                      0x00000020L
33097 #define RLC_STAT__RLC_THREAD_1_BUSY_MASK                                                                      0x00000040L
33098 #define RLC_STAT__RLC_THREAD_2_BUSY_MASK                                                                      0x00000080L
33099 #define RLC_STAT__RESERVED_MASK                                                                               0xFFFFFF00L
33100 //RLC_SAFE_MODE
33101 #define RLC_SAFE_MODE__CMD__SHIFT                                                                             0x0
33102 #define RLC_SAFE_MODE__MESSAGE__SHIFT                                                                         0x1
33103 #define RLC_SAFE_MODE__RESERVED1__SHIFT                                                                       0x5
33104 #define RLC_SAFE_MODE__RESPONSE__SHIFT                                                                        0x8
33105 #define RLC_SAFE_MODE__RESERVED__SHIFT                                                                        0xc
33106 #define RLC_SAFE_MODE__CMD_MASK                                                                               0x00000001L
33107 #define RLC_SAFE_MODE__MESSAGE_MASK                                                                           0x0000001EL
33108 #define RLC_SAFE_MODE__RESERVED1_MASK                                                                         0x000000E0L
33109 #define RLC_SAFE_MODE__RESPONSE_MASK                                                                          0x00000F00L
33110 #define RLC_SAFE_MODE__RESERVED_MASK                                                                          0xFFFFF000L
33111 //RLC_MEM_SLP_CNTL
33112 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT                                                                0x0
33113 #define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT                                                                0x1
33114 #define RLC_MEM_SLP_CNTL__RESERVED__SHIFT                                                                     0x2
33115 #define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT                                                      0x7
33116 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT                                                          0x8
33117 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT                                                         0x10
33118 #define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT                                                                    0x18
33119 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK                                                                  0x00000001L
33120 #define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK                                                                  0x00000002L
33121 #define RLC_MEM_SLP_CNTL__RESERVED_MASK                                                                       0x0000007CL
33122 #define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK                                                        0x00000080L
33123 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK                                                            0x0000FF00L
33124 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK                                                           0x00FF0000L
33125 #define RLC_MEM_SLP_CNTL__RESERVED1_MASK                                                                      0xFF000000L
33126 //SMU_RLC_RESPONSE
33127 #define SMU_RLC_RESPONSE__RESP__SHIFT                                                                         0x0
33128 #define SMU_RLC_RESPONSE__RESP_MASK                                                                           0xFFFFFFFFL
33129 //RLC_RLCV_SAFE_MODE
33130 #define RLC_RLCV_SAFE_MODE__CMD__SHIFT                                                                        0x0
33131 #define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT                                                                    0x1
33132 #define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT                                                                  0x5
33133 #define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT                                                                   0x8
33134 #define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT                                                                   0xc
33135 #define RLC_RLCV_SAFE_MODE__CMD_MASK                                                                          0x00000001L
33136 #define RLC_RLCV_SAFE_MODE__MESSAGE_MASK                                                                      0x0000001EL
33137 #define RLC_RLCV_SAFE_MODE__RESERVED1_MASK                                                                    0x000000E0L
33138 #define RLC_RLCV_SAFE_MODE__RESPONSE_MASK                                                                     0x00000F00L
33139 #define RLC_RLCV_SAFE_MODE__RESERVED_MASK                                                                     0xFFFFF000L
33140 //RLC_SMU_SAFE_MODE
33141 #define RLC_SMU_SAFE_MODE__CMD__SHIFT                                                                         0x0
33142 #define RLC_SMU_SAFE_MODE__MESSAGE__SHIFT                                                                     0x1
33143 #define RLC_SMU_SAFE_MODE__RESERVED1__SHIFT                                                                   0x5
33144 #define RLC_SMU_SAFE_MODE__RESPONSE__SHIFT                                                                    0x8
33145 #define RLC_SMU_SAFE_MODE__RESERVED__SHIFT                                                                    0xc
33146 #define RLC_SMU_SAFE_MODE__CMD_MASK                                                                           0x00000001L
33147 #define RLC_SMU_SAFE_MODE__MESSAGE_MASK                                                                       0x0000001EL
33148 #define RLC_SMU_SAFE_MODE__RESERVED1_MASK                                                                     0x000000E0L
33149 #define RLC_SMU_SAFE_MODE__RESPONSE_MASK                                                                      0x00000F00L
33150 #define RLC_SMU_SAFE_MODE__RESERVED_MASK                                                                      0xFFFFF000L
33151 //RLC_RLCV_COMMAND
33152 #define RLC_RLCV_COMMAND__CMD__SHIFT                                                                          0x0
33153 #define RLC_RLCV_COMMAND__RESERVED__SHIFT                                                                     0x4
33154 #define RLC_RLCV_COMMAND__CMD_MASK                                                                            0x0000000FL
33155 #define RLC_RLCV_COMMAND__RESERVED_MASK                                                                       0xFFFFFFF0L
33156 //RLC_REFCLOCK_TIMESTAMP_LSB
33157 #define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB__SHIFT                                                      0x0
33158 #define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB_MASK                                                        0xFFFFFFFFL
33159 //RLC_REFCLOCK_TIMESTAMP_MSB
33160 #define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB__SHIFT                                                      0x0
33161 #define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB_MASK                                                        0xFFFFFFFFL
33162 //RLC_GPM_TIMER_INT_0
33163 #define RLC_GPM_TIMER_INT_0__TIMER__SHIFT                                                                     0x0
33164 #define RLC_GPM_TIMER_INT_0__TIMER_MASK                                                                       0xFFFFFFFFL
33165 //RLC_GPM_TIMER_INT_1
33166 #define RLC_GPM_TIMER_INT_1__TIMER__SHIFT                                                                     0x0
33167 #define RLC_GPM_TIMER_INT_1__TIMER_MASK                                                                       0xFFFFFFFFL
33168 //RLC_GPM_TIMER_INT_2
33169 #define RLC_GPM_TIMER_INT_2__TIMER__SHIFT                                                                     0x0
33170 #define RLC_GPM_TIMER_INT_2__TIMER_MASK                                                                       0xFFFFFFFFL
33171 //RLC_GPM_TIMER_CTRL
33172 #define RLC_GPM_TIMER_CTRL__TIMER_0_EN__SHIFT                                                                 0x0
33173 #define RLC_GPM_TIMER_CTRL__TIMER_1_EN__SHIFT                                                                 0x1
33174 #define RLC_GPM_TIMER_CTRL__TIMER_2_EN__SHIFT                                                                 0x2
33175 #define RLC_GPM_TIMER_CTRL__TIMER_3_EN__SHIFT                                                                 0x3
33176 #define RLC_GPM_TIMER_CTRL__TIMER_0_AUTO_REARM__SHIFT                                                         0x4
33177 #define RLC_GPM_TIMER_CTRL__TIMER_1_AUTO_REARM__SHIFT                                                         0x5
33178 #define RLC_GPM_TIMER_CTRL__TIMER_2_AUTO_REARM__SHIFT                                                         0x6
33179 #define RLC_GPM_TIMER_CTRL__TIMER_3_AUTO_REARM__SHIFT                                                         0x7
33180 #define RLC_GPM_TIMER_CTRL__TIMER_0_INT_CLEAR__SHIFT                                                          0x8
33181 #define RLC_GPM_TIMER_CTRL__TIMER_1_INT_CLEAR__SHIFT                                                          0x9
33182 #define RLC_GPM_TIMER_CTRL__TIMER_2_INT_CLEAR__SHIFT                                                          0xa
33183 #define RLC_GPM_TIMER_CTRL__TIMER_3_INT_CLEAR__SHIFT                                                          0xb
33184 #define RLC_GPM_TIMER_CTRL__RESERVED__SHIFT                                                                   0xc
33185 #define RLC_GPM_TIMER_CTRL__TIMER_0_EN_MASK                                                                   0x00000001L
33186 #define RLC_GPM_TIMER_CTRL__TIMER_1_EN_MASK                                                                   0x00000002L
33187 #define RLC_GPM_TIMER_CTRL__TIMER_2_EN_MASK                                                                   0x00000004L
33188 #define RLC_GPM_TIMER_CTRL__TIMER_3_EN_MASK                                                                   0x00000008L
33189 #define RLC_GPM_TIMER_CTRL__TIMER_0_AUTO_REARM_MASK                                                           0x00000010L
33190 #define RLC_GPM_TIMER_CTRL__TIMER_1_AUTO_REARM_MASK                                                           0x00000020L
33191 #define RLC_GPM_TIMER_CTRL__TIMER_2_AUTO_REARM_MASK                                                           0x00000040L
33192 #define RLC_GPM_TIMER_CTRL__TIMER_3_AUTO_REARM_MASK                                                           0x00000080L
33193 #define RLC_GPM_TIMER_CTRL__TIMER_0_INT_CLEAR_MASK                                                            0x00000100L
33194 #define RLC_GPM_TIMER_CTRL__TIMER_1_INT_CLEAR_MASK                                                            0x00000200L
33195 #define RLC_GPM_TIMER_CTRL__TIMER_2_INT_CLEAR_MASK                                                            0x00000400L
33196 #define RLC_GPM_TIMER_CTRL__TIMER_3_INT_CLEAR_MASK                                                            0x00000800L
33197 #define RLC_GPM_TIMER_CTRL__RESERVED_MASK                                                                     0xFFFFF000L
33198 //RLC_LB_CNTR_MAX_1
33199 #define RLC_LB_CNTR_MAX_1__LB_CNTR_MAX__SHIFT                                                                 0x0
33200 #define RLC_LB_CNTR_MAX_1__LB_CNTR_MAX_MASK                                                                   0xFFFFFFFFL
33201 //RLC_GPM_TIMER_STAT
33202 #define RLC_GPM_TIMER_STAT__TIMER_0_STAT__SHIFT                                                               0x0
33203 #define RLC_GPM_TIMER_STAT__TIMER_1_STAT__SHIFT                                                               0x1
33204 #define RLC_GPM_TIMER_STAT__TIMER_2_STAT__SHIFT                                                               0x2
33205 #define RLC_GPM_TIMER_STAT__TIMER_3_STAT__SHIFT                                                               0x3
33206 #define RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT                                                        0x8
33207 #define RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT                                                        0x9
33208 #define RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC__SHIFT                                                        0xa
33209 #define RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC__SHIFT                                                        0xb
33210 #define RLC_GPM_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC__SHIFT                                                    0xc
33211 #define RLC_GPM_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC__SHIFT                                                    0xd
33212 #define RLC_GPM_TIMER_STAT__TIMER_2_AUTO_REARM_SYNC__SHIFT                                                    0xe
33213 #define RLC_GPM_TIMER_STAT__TIMER_3_AUTO_REARM_SYNC__SHIFT                                                    0xf
33214 #define RLC_GPM_TIMER_STAT__RESERVED__SHIFT                                                                   0x10
33215 #define RLC_GPM_TIMER_STAT__TIMER_0_STAT_MASK                                                                 0x00000001L
33216 #define RLC_GPM_TIMER_STAT__TIMER_1_STAT_MASK                                                                 0x00000002L
33217 #define RLC_GPM_TIMER_STAT__TIMER_2_STAT_MASK                                                                 0x00000004L
33218 #define RLC_GPM_TIMER_STAT__TIMER_3_STAT_MASK                                                                 0x00000008L
33219 #define RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK                                                          0x00000100L
33220 #define RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK                                                          0x00000200L
33221 #define RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC_MASK                                                          0x00000400L
33222 #define RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC_MASK                                                          0x00000800L
33223 #define RLC_GPM_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC_MASK                                                      0x00001000L
33224 #define RLC_GPM_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC_MASK                                                      0x00002000L
33225 #define RLC_GPM_TIMER_STAT__TIMER_2_AUTO_REARM_SYNC_MASK                                                      0x00004000L
33226 #define RLC_GPM_TIMER_STAT__TIMER_3_AUTO_REARM_SYNC_MASK                                                      0x00008000L
33227 #define RLC_GPM_TIMER_STAT__RESERVED_MASK                                                                     0xFFFF0000L
33228 //RLC_GPM_TIMER_INT_3
33229 #define RLC_GPM_TIMER_INT_3__TIMER__SHIFT                                                                     0x0
33230 #define RLC_GPM_TIMER_INT_3__TIMER_MASK                                                                       0xFFFFFFFFL
33231 //RLC_INT_STAT
33232 #define RLC_INT_STAT__LAST_CP_RLC_INT_ID__SHIFT                                                               0x0
33233 #define RLC_INT_STAT__CP_RLC_INT_PENDING__SHIFT                                                               0x8
33234 #define RLC_INT_STAT__RESERVED__SHIFT                                                                         0x9
33235 #define RLC_INT_STAT__LAST_CP_RLC_INT_ID_MASK                                                                 0x000000FFL
33236 #define RLC_INT_STAT__CP_RLC_INT_PENDING_MASK                                                                 0x00000100L
33237 #define RLC_INT_STAT__RESERVED_MASK                                                                           0xFFFFFE00L
33238 //RLC_LB_CNTL
33239 #define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT                                                               0x0
33240 #define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT                                                                    0x1
33241 #define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT                                                                0x2
33242 #define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT                                                                    0x3
33243 #define RLC_LB_CNTL__RESERVED__SHIFT                                                                          0x4
33244 #define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK                                                                 0x00000001L
33245 #define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK                                                                      0x00000002L
33246 #define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK                                                                  0x00000004L
33247 #define RLC_LB_CNTL__LB_CNT_REG_INC_MASK                                                                      0x00000008L
33248 #define RLC_LB_CNTL__RESERVED_MASK                                                                            0xFFFFFFF0L
33249 //RLC_MGCG_CTRL
33250 #define RLC_MGCG_CTRL__MGCG_EN__SHIFT                                                                         0x0
33251 #define RLC_MGCG_CTRL__SILICON_EN__SHIFT                                                                      0x1
33252 #define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT                                                                   0x2
33253 #define RLC_MGCG_CTRL__ON_DELAY__SHIFT                                                                        0x3
33254 #define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT                                                                  0x7
33255 #define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL__SHIFT                                                            0xf
33256 #define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL__SHIFT                                                            0x10
33257 #define RLC_MGCG_CTRL__SPARE__SHIFT                                                                           0x11
33258 #define RLC_MGCG_CTRL__MGCG_EN_MASK                                                                           0x00000001L
33259 #define RLC_MGCG_CTRL__SILICON_EN_MASK                                                                        0x00000002L
33260 #define RLC_MGCG_CTRL__SIMULATION_EN_MASK                                                                     0x00000004L
33261 #define RLC_MGCG_CTRL__ON_DELAY_MASK                                                                          0x00000078L
33262 #define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK                                                                    0x00007F80L
33263 #define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL_MASK                                                              0x00008000L
33264 #define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL_MASK                                                              0x00010000L
33265 #define RLC_MGCG_CTRL__SPARE_MASK                                                                             0xFFFE0000L
33266 //RLC_LB_CNTR_INIT_1
33267 #define RLC_LB_CNTR_INIT_1__LB_CNTR_INIT__SHIFT                                                               0x0
33268 #define RLC_LB_CNTR_INIT_1__LB_CNTR_INIT_MASK                                                                 0xFFFFFFFFL
33269 //RLC_LB_CNTR_1
33270 #define RLC_LB_CNTR_1__RLC_LOAD_BALANCE_CNTR__SHIFT                                                           0x0
33271 #define RLC_LB_CNTR_1__RLC_LOAD_BALANCE_CNTR_MASK                                                             0xFFFFFFFFL
33272 //RLC_JUMP_TABLE_RESTORE
33273 #define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT                                                                   0x0
33274 #define RLC_JUMP_TABLE_RESTORE__ADDR_MASK                                                                     0xFFFFFFFFL
33275 //RLC_PG_DELAY_2
33276 #define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT                                                           0x0
33277 #define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT                                                               0x8
33278 #define RLC_PG_DELAY_2__PERWGP_TIMEOUT_VALUE__SHIFT                                                           0x10
33279 #define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK                                                             0x000000FFL
33280 #define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK                                                                 0x0000FF00L
33281 #define RLC_PG_DELAY_2__PERWGP_TIMEOUT_VALUE_MASK                                                             0xFFFF0000L
33282 //RLC_GPU_CLOCK_COUNT_LSB
33283 #define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT                                                        0x0
33284 #define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK                                                          0xFFFFFFFFL
33285 //RLC_GPU_CLOCK_COUNT_MSB
33286 #define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT                                                        0x0
33287 #define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK                                                          0xFFFFFFFFL
33288 //RLC_CAPTURE_GPU_CLOCK_COUNT
33289 #define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT                                                           0x0
33290 #define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT                                                          0x1
33291 #define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK                                                             0x00000001L
33292 #define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK                                                            0xFFFFFFFEL
33293 //RLC_UCODE_CNTL
33294 #define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT                                                                0x0
33295 #define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK                                                                  0xFFFFFFFFL
33296 //RLC_GPM_THREAD_RESET
33297 #define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT                                                            0x0
33298 #define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT                                                            0x1
33299 #define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT                                                            0x2
33300 #define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT                                                            0x3
33301 #define RLC_GPM_THREAD_RESET__RESERVED__SHIFT                                                                 0x4
33302 #define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK                                                              0x00000001L
33303 #define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK                                                              0x00000002L
33304 #define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK                                                              0x00000004L
33305 #define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK                                                              0x00000008L
33306 #define RLC_GPM_THREAD_RESET__RESERVED_MASK                                                                   0xFFFFFFF0L
33307 //RLC_GPM_CP_DMA_COMPLETE_T0
33308 #define RLC_GPM_CP_DMA_COMPLETE_T0__DATA__SHIFT                                                               0x0
33309 #define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED__SHIFT                                                           0x1
33310 #define RLC_GPM_CP_DMA_COMPLETE_T0__DATA_MASK                                                                 0x00000001L
33311 #define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED_MASK                                                             0xFFFFFFFEL
33312 //RLC_GPM_CP_DMA_COMPLETE_T1
33313 #define RLC_GPM_CP_DMA_COMPLETE_T1__DATA__SHIFT                                                               0x0
33314 #define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED__SHIFT                                                           0x1
33315 #define RLC_GPM_CP_DMA_COMPLETE_T1__DATA_MASK                                                                 0x00000001L
33316 #define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED_MASK                                                             0xFFFFFFFEL
33317 //RLC_LB_CNTR_INIT_2
33318 #define RLC_LB_CNTR_INIT_2__LB_CNTR_INIT__SHIFT                                                               0x0
33319 #define RLC_LB_CNTR_INIT_2__LB_CNTR_INIT_MASK                                                                 0xFFFFFFFFL
33320 //RLC_LB_CNTR_MAX_2
33321 #define RLC_LB_CNTR_MAX_2__LB_CNTR_MAX__SHIFT                                                                 0x0
33322 #define RLC_LB_CNTR_MAX_2__LB_CNTR_MAX_MASK                                                                   0xFFFFFFFFL
33323 //RLC_LB_CONFIG_5
33324 #define RLC_LB_CONFIG_5__DATA__SHIFT                                                                          0x0
33325 #define RLC_LB_CONFIG_5__DATA_MASK                                                                            0xFFFFFFFFL
33326 //RLC_CLK_COUNT_GFXCLK_LSB
33327 #define RLC_CLK_COUNT_GFXCLK_LSB__COUNTER__SHIFT                                                              0x0
33328 #define RLC_CLK_COUNT_GFXCLK_LSB__COUNTER_MASK                                                                0xFFFFFFFFL
33329 //RLC_CLK_COUNT_GFXCLK_MSB
33330 #define RLC_CLK_COUNT_GFXCLK_MSB__COUNTER__SHIFT                                                              0x0
33331 #define RLC_CLK_COUNT_GFXCLK_MSB__COUNTER_MASK                                                                0xFFFFFFFFL
33332 //RLC_CLK_COUNT_REFCLK_LSB
33333 #define RLC_CLK_COUNT_REFCLK_LSB__COUNTER__SHIFT                                                              0x0
33334 #define RLC_CLK_COUNT_REFCLK_LSB__COUNTER_MASK                                                                0xFFFFFFFFL
33335 //RLC_CLK_COUNT_REFCLK_MSB
33336 #define RLC_CLK_COUNT_REFCLK_MSB__COUNTER__SHIFT                                                              0x0
33337 #define RLC_CLK_COUNT_REFCLK_MSB__COUNTER_MASK                                                                0xFFFFFFFFL
33338 //RLC_CLK_COUNT_CTRL
33339 #define RLC_CLK_COUNT_CTRL__GFXCLK_RUN__SHIFT                                                                 0x0
33340 #define RLC_CLK_COUNT_CTRL__GFXCLK_RESET__SHIFT                                                               0x1
33341 #define RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE__SHIFT                                                              0x2
33342 #define RLC_CLK_COUNT_CTRL__REFCLK_RUN__SHIFT                                                                 0x3
33343 #define RLC_CLK_COUNT_CTRL__REFCLK_RESET__SHIFT                                                               0x4
33344 #define RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE__SHIFT                                                              0x5
33345 #define RLC_CLK_COUNT_CTRL__GFXCLK_RUN_MASK                                                                   0x00000001L
33346 #define RLC_CLK_COUNT_CTRL__GFXCLK_RESET_MASK                                                                 0x00000002L
33347 #define RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE_MASK                                                                0x00000004L
33348 #define RLC_CLK_COUNT_CTRL__REFCLK_RUN_MASK                                                                   0x00000008L
33349 #define RLC_CLK_COUNT_CTRL__REFCLK_RESET_MASK                                                                 0x00000010L
33350 #define RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE_MASK                                                                0x00000020L
33351 //RLC_CLK_COUNT_STAT
33352 #define RLC_CLK_COUNT_STAT__GFXCLK_VALID__SHIFT                                                               0x0
33353 #define RLC_CLK_COUNT_STAT__REFCLK_VALID__SHIFT                                                               0x1
33354 #define RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC__SHIFT                                                          0x2
33355 #define RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC__SHIFT                                                        0x3
33356 #define RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC__SHIFT                                                       0x4
33357 #define RLC_CLK_COUNT_STAT__RESERVED__SHIFT                                                                   0x5
33358 #define RLC_CLK_COUNT_STAT__GFXCLK_VALID_MASK                                                                 0x00000001L
33359 #define RLC_CLK_COUNT_STAT__REFCLK_VALID_MASK                                                                 0x00000002L
33360 #define RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC_MASK                                                            0x00000004L
33361 #define RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC_MASK                                                          0x00000008L
33362 #define RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC_MASK                                                         0x00000010L
33363 #define RLC_CLK_COUNT_STAT__RESERVED_MASK                                                                     0xFFFFFFE0L
33364 //RLC_GPU_CLOCK_32_RES_SEL
33365 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT                                                              0x0
33366 #define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT                                                             0x6
33367 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK                                                                0x0000003FL
33368 #define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK                                                               0xFFFFFFC0L
33369 //RLC_GPU_CLOCK_32
33370 #define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT                                                                 0x0
33371 #define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK                                                                   0xFFFFFFFFL
33372 //RLC_PG_CNTL
33373 #define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT                                                           0x0
33374 #define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT                                                              0x1
33375 #define RLC_PG_CNTL__DYN_PER_WGP_PG_ENABLE__SHIFT                                                             0x2
33376 #define RLC_PG_CNTL__STATIC_PER_WGP_PG_ENABLE__SHIFT                                                          0x3
33377 #define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT                                                            0x4
33378 #define RLC_PG_CNTL__RESERVED__SHIFT                                                                          0x5
33379 #define RLC_PG_CNTL__PG_OVERRIDE__SHIFT                                                                       0xe
33380 #define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT                                                                     0xf
33381 #define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT                                                             0x10
33382 #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT                                                     0x11
33383 #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT                                                     0x12
33384 #define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE__SHIFT                                                              0x13
33385 #define RLC_PG_CNTL__RESERVED1__SHIFT                                                                         0x14
33386 #define RLC_PG_CNTL__Ultra_Low_Voltage_Enable__SHIFT                                                          0x15
33387 #define RLC_PG_CNTL__RESERVED2__SHIFT                                                                         0x16
33388 #define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK                                                             0x00000001L
33389 #define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK                                                                0x00000002L
33390 #define RLC_PG_CNTL__DYN_PER_WGP_PG_ENABLE_MASK                                                               0x00000004L
33391 #define RLC_PG_CNTL__STATIC_PER_WGP_PG_ENABLE_MASK                                                            0x00000008L
33392 #define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK                                                              0x00000010L
33393 #define RLC_PG_CNTL__RESERVED_MASK                                                                            0x00003FE0L
33394 #define RLC_PG_CNTL__PG_OVERRIDE_MASK                                                                         0x00004000L
33395 #define RLC_PG_CNTL__CP_PG_DISABLE_MASK                                                                       0x00008000L
33396 #define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK                                                               0x00010000L
33397 #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK                                                       0x00020000L
33398 #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK                                                       0x00040000L
33399 #define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE_MASK                                                                0x00080000L
33400 #define RLC_PG_CNTL__RESERVED1_MASK                                                                           0x00100000L
33401 #define RLC_PG_CNTL__Ultra_Low_Voltage_Enable_MASK                                                            0x00200000L
33402 #define RLC_PG_CNTL__RESERVED2_MASK                                                                           0x00C00000L
33403 //RLC_GPM_THREAD_PRIORITY
33404 #define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT                                                      0x0
33405 #define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT                                                      0x8
33406 #define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT                                                      0x10
33407 #define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT                                                      0x18
33408 #define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK                                                        0x000000FFL
33409 #define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK                                                        0x0000FF00L
33410 #define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK                                                        0x00FF0000L
33411 #define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK                                                        0xFF000000L
33412 //RLC_GPM_THREAD_ENABLE
33413 #define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT                                                          0x0
33414 #define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT                                                          0x1
33415 #define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT                                                          0x2
33416 #define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT                                                          0x3
33417 #define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT                                                                0x4
33418 #define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK                                                            0x00000001L
33419 #define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK                                                            0x00000002L
33420 #define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK                                                            0x00000004L
33421 #define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK                                                            0x00000008L
33422 #define RLC_GPM_THREAD_ENABLE__RESERVED_MASK                                                                  0xFFFFFFF0L
33423 //RLC_CGTT_MGCG_OVERRIDE
33424 #define RLC_CGTT_MGCG_OVERRIDE__RESERVED_0__SHIFT                                                             0x0
33425 #define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE__SHIFT                                                 0x1
33426 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE__SHIFT                                                    0x2
33427 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE__SHIFT                                                    0x3
33428 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE__SHIFT                                                    0x4
33429 #define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE__SHIFT                                                0x5
33430 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE__SHIFT                                                    0x6
33431 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE__SHIFT                                                0x7
33432 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE__SHIFT                                                    0x8
33433 #define RLC_CGTT_MGCG_OVERRIDE__RESERVED_15_9__SHIFT                                                          0x9
33434 #define RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY__SHIFT                                                     0x10
33435 #define RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_17__SHIFT                                                         0x11
33436 #define RLC_CGTT_MGCG_OVERRIDE__RESERVED_0_MASK                                                               0x00000001L
33437 #define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK                                                   0x00000002L
33438 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK                                                      0x00000004L
33439 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK                                                      0x00000008L
33440 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK                                                      0x00000010L
33441 #define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK                                                  0x00000020L
33442 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK                                                      0x00000040L
33443 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK                                                  0x00000080L
33444 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK                                                      0x00000100L
33445 #define RLC_CGTT_MGCG_OVERRIDE__RESERVED_15_9_MASK                                                            0x0000FE00L
33446 #define RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK                                                       0x00010000L
33447 #define RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_17_MASK                                                           0xFFFE0000L
33448 //RLC_CGCG_CGLS_CTRL
33449 #define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT                                                                    0x0
33450 #define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT                                                                    0x1
33451 #define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT                                                   0x2
33452 #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT                                                    0x8
33453 #define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT                                                            0x1b
33454 #define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT                                                              0x1c
33455 #define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT                                                                 0x1d
33456 #define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT                                                             0x1f
33457 #define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK                                                                      0x00000001L
33458 #define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK                                                                      0x00000002L
33459 #define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK                                                     0x000000FCL
33460 #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK                                                      0x07FFFF00L
33461 #define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK                                                              0x08000000L
33462 #define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK                                                                0x10000000L
33463 #define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK                                                                   0x60000000L
33464 #define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK                                                               0x80000000L
33465 //RLC_CGCG_RAMP_CTRL
33466 #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT                                                        0x0
33467 #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT                                                         0x4
33468 #define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT                                                          0x8
33469 #define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT                                                           0xc
33470 #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT                                                             0x10
33471 #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT                                                            0x1c
33472 #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK                                                          0x0000000FL
33473 #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK                                                           0x000000F0L
33474 #define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK                                                            0x00000F00L
33475 #define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK                                                             0x0000F000L
33476 #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK                                                               0x0FFF0000L
33477 #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK                                                              0xF0000000L
33478 //RLC_DYN_PG_STATUS
33479 #define RLC_DYN_PG_STATUS__PG_STATUS_WGP_MASK__SHIFT                                                          0x0
33480 #define RLC_DYN_PG_STATUS__PG_STATUS_WGP_MASK_MASK                                                            0xFFFFFFFFL
33481 //RLC_DYN_PG_REQUEST
33482 #define RLC_DYN_PG_REQUEST__PG_REQUEST_WGP_MASK__SHIFT                                                        0x0
33483 #define RLC_DYN_PG_REQUEST__PG_REQUEST_WGP_MASK_MASK                                                          0xFFFFFFFFL
33484 //RLC_PG_DELAY
33485 #define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT                                                                   0x0
33486 #define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT                                                                 0x8
33487 #define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT                                                              0x10
33488 #define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT                                                                  0x18
33489 #define RLC_PG_DELAY__POWER_UP_DELAY_MASK                                                                     0x000000FFL
33490 #define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK                                                                   0x0000FF00L
33491 #define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK                                                                0x00FF0000L
33492 #define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK                                                                    0xFF000000L
33493 //RLC_WGP_STATUS
33494 #define RLC_WGP_STATUS__WORK_PENDING__SHIFT                                                                   0x0
33495 #define RLC_WGP_STATUS__WORK_PENDING_MASK                                                                     0xFFFFFFFFL
33496 //RLC_LB_INIT_WGP_MASK
33497 #define RLC_LB_INIT_WGP_MASK__INIT_WGP_MASK__SHIFT                                                            0x0
33498 #define RLC_LB_INIT_WGP_MASK__INIT_WGP_MASK_MASK                                                              0xFFFFFFFFL
33499 //RLC_LB_ALWAYS_ACTIVE_WGP_MASK
33500 #define RLC_LB_ALWAYS_ACTIVE_WGP_MASK__ALWAYS_ACTIVE_WGP_MASK__SHIFT                                          0x0
33501 #define RLC_LB_ALWAYS_ACTIVE_WGP_MASK__ALWAYS_ACTIVE_WGP_MASK_MASK                                            0xFFFFFFFFL
33502 //RLC_LB_PARAMS
33503 #define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT                                                                   0x0
33504 #define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT                                                                    0x1
33505 #define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT                                                                 0x8
33506 #define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT                                                         0x10
33507 #define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK                                                                     0x00000001L
33508 #define RLC_LB_PARAMS__FIFO_SAMPLES_MASK                                                                      0x000000FEL
33509 #define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK                                                                   0x0000FF00L
33510 #define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK                                                           0xFFFF0000L
33511 //RLC_LB_DELAY
33512 #define RLC_LB_DELAY__WGP_IDLE_DELAY__SHIFT                                                                   0x0
33513 #define RLC_LB_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT                                                            0x8
33514 #define RLC_LB_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT                                                            0x10
33515 #define RLC_LB_DELAY__SPARE__SHIFT                                                                            0x18
33516 #define RLC_LB_DELAY__WGP_IDLE_DELAY_MASK                                                                     0x000000FFL
33517 #define RLC_LB_DELAY__LBPW_INNER_LOOP_DELAY_MASK                                                              0x0000FF00L
33518 #define RLC_LB_DELAY__LBPW_OUTER_LOOP_DELAY_MASK                                                              0x00FF0000L
33519 #define RLC_LB_DELAY__SPARE_MASK                                                                              0xFF000000L
33520 //RLC_PG_ALWAYS_ON_WGP_MASK
33521 #define RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK__SHIFT                                                        0x0
33522 #define RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK_MASK                                                          0xFFFFFFFFL
33523 //RLC_MAX_PG_WGP
33524 #define RLC_MAX_PG_WGP__MAX_POWERED_UP_WGP__SHIFT                                                             0x0
33525 #define RLC_MAX_PG_WGP__SPARE__SHIFT                                                                          0x8
33526 #define RLC_MAX_PG_WGP__MAX_POWERED_UP_WGP_MASK                                                               0x000000FFL
33527 #define RLC_MAX_PG_WGP__SPARE_MASK                                                                            0xFFFFFF00L
33528 //RLC_AUTO_PG_CTRL
33529 #define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT                                                                   0x0
33530 #define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT                                                0x1
33531 #define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT                                                              0x2
33532 #define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT                                             0x3
33533 #define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT                                             0x13
33534 #define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK                                                                     0x00000001L
33535 #define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK                                                  0x00000002L
33536 #define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK                                                                0x00000004L
33537 #define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK                                               0x0007FFF8L
33538 #define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK                                               0xFFF80000L
33539 //RLC_SMU_GRBM_REG_SAVE_CTRL
33540 #define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT                                                0x0
33541 #define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT                                                              0x1
33542 #define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK                                                  0x00000001L
33543 #define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK                                                                0xFFFFFFFEL
33544 //RLC_SERDES_RD_INDEX
33545 #define RLC_SERDES_RD_INDEX__DATA_REG_ID__SHIFT                                                               0x0
33546 #define RLC_SERDES_RD_INDEX__SPARE__SHIFT                                                                     0x2
33547 #define RLC_SERDES_RD_INDEX__DATA_REG_ID_MASK                                                                 0x00000003L
33548 #define RLC_SERDES_RD_INDEX__SPARE_MASK                                                                       0xFFFFFFFCL
33549 //RLC_SERDES_RD_DATA_0
33550 #define RLC_SERDES_RD_DATA_0__DATA__SHIFT                                                                     0x0
33551 #define RLC_SERDES_RD_DATA_0__DATA_MASK                                                                       0xFFFFFFFFL
33552 //RLC_SERDES_RD_DATA_1
33553 #define RLC_SERDES_RD_DATA_1__DATA__SHIFT                                                                     0x0
33554 #define RLC_SERDES_RD_DATA_1__DATA_MASK                                                                       0xFFFFFFFFL
33555 //RLC_SERDES_RD_DATA_2
33556 #define RLC_SERDES_RD_DATA_2__DATA__SHIFT                                                                     0x0
33557 #define RLC_SERDES_RD_DATA_2__DATA_MASK                                                                       0xFFFFFFFFL
33558 //RLC_SERDES_RD_DATA_3
33559 #define RLC_SERDES_RD_DATA_3__DATA__SHIFT                                                                     0x0
33560 #define RLC_SERDES_RD_DATA_3__DATA_MASK                                                                       0xFFFFFFFFL
33561 //RLC_SERDES_MASK
33562 #define RLC_SERDES_MASK__GC_CENTER_HUB_0__SHIFT                                                               0x0
33563 #define RLC_SERDES_MASK__GC_CENTER_HUB_1__SHIFT                                                               0x1
33564 #define RLC_SERDES_MASK__RESERVED__SHIFT                                                                      0x2
33565 #define RLC_SERDES_MASK__GC_SE_0__SHIFT                                                                       0x10
33566 #define RLC_SERDES_MASK__GC_SE_1__SHIFT                                                                       0x11
33567 #define RLC_SERDES_MASK__GC_SE_2__SHIFT                                                                       0x12
33568 #define RLC_SERDES_MASK__GC_SE_3__SHIFT                                                                       0x13
33569 #define RLC_SERDES_MASK__RESERVED_1__SHIFT                                                                    0x14
33570 #define RLC_SERDES_MASK__GC_CENTER_HUB_0_MASK                                                                 0x00000001L
33571 #define RLC_SERDES_MASK__GC_CENTER_HUB_1_MASK                                                                 0x00000002L
33572 #define RLC_SERDES_MASK__RESERVED_MASK                                                                        0x0000FFFCL
33573 #define RLC_SERDES_MASK__GC_SE_0_MASK                                                                         0x00010000L
33574 #define RLC_SERDES_MASK__GC_SE_1_MASK                                                                         0x00020000L
33575 #define RLC_SERDES_MASK__GC_SE_2_MASK                                                                         0x00040000L
33576 #define RLC_SERDES_MASK__GC_SE_3_MASK                                                                         0x00080000L
33577 #define RLC_SERDES_MASK__RESERVED_1_MASK                                                                      0xFFF00000L
33578 //RLC_SERDES_CTRL
33579 #define RLC_SERDES_CTRL__BPM_BROADCAST__SHIFT                                                                 0x0
33580 #define RLC_SERDES_CTRL__BPM_REG_WRITE__SHIFT                                                                 0x1
33581 #define RLC_SERDES_CTRL__BPM_LONG_CMD__SHIFT                                                                  0x2
33582 #define RLC_SERDES_CTRL__BPM_ADDR__SHIFT                                                                      0x3
33583 #define RLC_SERDES_CTRL__REG_ADDR__SHIFT                                                                      0x10
33584 #define RLC_SERDES_CTRL__BPM_BROADCAST_MASK                                                                   0x000001L
33585 #define RLC_SERDES_CTRL__BPM_REG_WRITE_MASK                                                                   0x000002L
33586 #define RLC_SERDES_CTRL__BPM_LONG_CMD_MASK                                                                    0x000004L
33587 #define RLC_SERDES_CTRL__BPM_ADDR_MASK                                                                        0x00FFF8L
33588 #define RLC_SERDES_CTRL__REG_ADDR_MASK                                                                        0xFF0000L
33589 //RLC_SERDES_DATA
33590 #define RLC_SERDES_DATA__DATA__SHIFT                                                                          0x0
33591 #define RLC_SERDES_DATA__DATA_MASK                                                                            0xFFFFFFFFL
33592 //RLC_SERDES_BUSY
33593 #define RLC_SERDES_BUSY__GC_CENTER_HUB_0__SHIFT                                                               0x0
33594 #define RLC_SERDES_BUSY__GC_CENTER_HUB_1__SHIFT                                                               0x1
33595 #define RLC_SERDES_BUSY__RESERVED__SHIFT                                                                      0x2
33596 #define RLC_SERDES_BUSY__GC_SE_0__SHIFT                                                                       0x10
33597 #define RLC_SERDES_BUSY__GC_SE_1__SHIFT                                                                       0x11
33598 #define RLC_SERDES_BUSY__GC_SE_2__SHIFT                                                                       0x12
33599 #define RLC_SERDES_BUSY__GC_SE_3__SHIFT                                                                       0x13
33600 #define RLC_SERDES_BUSY__RESERVED_29_20__SHIFT                                                                0x14
33601 #define RLC_SERDES_BUSY__RD_FIFO_NOT_EMPTY__SHIFT                                                             0x1e
33602 #define RLC_SERDES_BUSY__RD_PENDING__SHIFT                                                                    0x1f
33603 #define RLC_SERDES_BUSY__GC_CENTER_HUB_0_MASK                                                                 0x00000001L
33604 #define RLC_SERDES_BUSY__GC_CENTER_HUB_1_MASK                                                                 0x00000002L
33605 #define RLC_SERDES_BUSY__RESERVED_MASK                                                                        0x0000FFFCL
33606 #define RLC_SERDES_BUSY__GC_SE_0_MASK                                                                         0x00010000L
33607 #define RLC_SERDES_BUSY__GC_SE_1_MASK                                                                         0x00020000L
33608 #define RLC_SERDES_BUSY__GC_SE_2_MASK                                                                         0x00040000L
33609 #define RLC_SERDES_BUSY__GC_SE_3_MASK                                                                         0x00080000L
33610 #define RLC_SERDES_BUSY__RESERVED_29_20_MASK                                                                  0x3FF00000L
33611 #define RLC_SERDES_BUSY__RD_FIFO_NOT_EMPTY_MASK                                                               0x40000000L
33612 #define RLC_SERDES_BUSY__RD_PENDING_MASK                                                                      0x80000000L
33613 //RLC_GPM_GENERAL_0
33614 #define RLC_GPM_GENERAL_0__DATA__SHIFT                                                                        0x0
33615 #define RLC_GPM_GENERAL_0__DATA_MASK                                                                          0xFFFFFFFFL
33616 //RLC_GPM_GENERAL_1
33617 #define RLC_GPM_GENERAL_1__DATA__SHIFT                                                                        0x0
33618 #define RLC_GPM_GENERAL_1__DATA_MASK                                                                          0xFFFFFFFFL
33619 //RLC_GPM_GENERAL_2
33620 #define RLC_GPM_GENERAL_2__DATA__SHIFT                                                                        0x0
33621 #define RLC_GPM_GENERAL_2__DATA_MASK                                                                          0xFFFFFFFFL
33622 //RLC_GPM_GENERAL_3
33623 #define RLC_GPM_GENERAL_3__DATA__SHIFT                                                                        0x0
33624 #define RLC_GPM_GENERAL_3__DATA_MASK                                                                          0xFFFFFFFFL
33625 //RLC_GPM_GENERAL_4
33626 #define RLC_GPM_GENERAL_4__DATA__SHIFT                                                                        0x0
33627 #define RLC_GPM_GENERAL_4__DATA_MASK                                                                          0xFFFFFFFFL
33628 //RLC_GPM_GENERAL_5
33629 #define RLC_GPM_GENERAL_5__DATA__SHIFT                                                                        0x0
33630 #define RLC_GPM_GENERAL_5__DATA_MASK                                                                          0xFFFFFFFFL
33631 //RLC_GPM_GENERAL_6
33632 #define RLC_GPM_GENERAL_6__DATA__SHIFT                                                                        0x0
33633 #define RLC_GPM_GENERAL_6__DATA_MASK                                                                          0xFFFFFFFFL
33634 //RLC_GPM_GENERAL_7
33635 #define RLC_GPM_GENERAL_7__DATA__SHIFT                                                                        0x0
33636 #define RLC_GPM_GENERAL_7__DATA_MASK                                                                          0xFFFFFFFFL
33637 //RLC_STATIC_PG_STATUS
33638 #define RLC_STATIC_PG_STATUS__PG_STATUS_WGP_MASK__SHIFT                                                       0x0
33639 #define RLC_STATIC_PG_STATUS__PG_STATUS_WGP_MASK_MASK                                                         0xFFFFFFFFL
33640 //RLC_SPM_INT_INFO_1
33641 #define RLC_SPM_INT_INFO_1__INTERRUPT_INFO_1__SHIFT                                                           0x0
33642 #define RLC_SPM_INT_INFO_1__INTERRUPT_INFO_1_MASK                                                             0xFFFFFFFFL
33643 //RLC_SPM_INT_INFO_2
33644 #define RLC_SPM_INT_INFO_2__INTERRUPT_INFO_2__SHIFT                                                           0x0
33645 #define RLC_SPM_INT_INFO_2__INTERRUPT_ID__SHIFT                                                               0x10
33646 #define RLC_SPM_INT_INFO_2__RESERVED__SHIFT                                                                   0x18
33647 #define RLC_SPM_INT_INFO_2__INTERRUPT_INFO_2_MASK                                                             0x0000FFFFL
33648 #define RLC_SPM_INT_INFO_2__INTERRUPT_ID_MASK                                                                 0x00FF0000L
33649 #define RLC_SPM_INT_INFO_2__RESERVED_MASK                                                                     0xFF000000L
33650 //RLC_SPM_MC_CNTL
33651 #define RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT                                                                  0x0
33652 #define RLC_SPM_MC_CNTL__RLC_SPM_POLICY__SHIFT                                                                0x4
33653 #define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR__SHIFT                                                             0x6
33654 #define RLC_SPM_MC_CNTL__RLC_SPM_FED__SHIFT                                                                   0x7
33655 #define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER__SHIFT                                                            0x8
33656 #define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE__SHIFT                                                                 0x9
33657 #define RLC_SPM_MC_CNTL__RLC_SPM_BC__SHIFT                                                                    0xc
33658 #define RLC_SPM_MC_CNTL__RESERVED_2__SHIFT                                                                    0xd
33659 #define RLC_SPM_MC_CNTL__RLC_SPM_VOL__SHIFT                                                                   0xe
33660 #define RLC_SPM_MC_CNTL__RLC_SPM_NOFILL__SHIFT                                                                0xf
33661 #define RLC_SPM_MC_CNTL__RESERVED__SHIFT                                                                      0x10
33662 #define RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK                                                                    0x0000000FL
33663 #define RLC_SPM_MC_CNTL__RLC_SPM_POLICY_MASK                                                                  0x00000030L
33664 #define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR_MASK                                                               0x00000040L
33665 #define RLC_SPM_MC_CNTL__RLC_SPM_FED_MASK                                                                     0x00000080L
33666 #define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER_MASK                                                              0x00000100L
33667 #define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_MASK                                                                   0x00000E00L
33668 #define RLC_SPM_MC_CNTL__RLC_SPM_BC_MASK                                                                      0x00001000L
33669 #define RLC_SPM_MC_CNTL__RESERVED_2_MASK                                                                      0x00002000L
33670 #define RLC_SPM_MC_CNTL__RLC_SPM_VOL_MASK                                                                     0x00004000L
33671 #define RLC_SPM_MC_CNTL__RLC_SPM_NOFILL_MASK                                                                  0x00008000L
33672 #define RLC_SPM_MC_CNTL__RESERVED_MASK                                                                        0xFFFF0000L
33673 //RLC_SPM_INT_CNTL
33674 #define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT                                                             0x0
33675 #define RLC_SPM_INT_CNTL__RESERVED__SHIFT                                                                     0x1
33676 #define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK                                                               0x00000001L
33677 #define RLC_SPM_INT_CNTL__RESERVED_MASK                                                                       0xFFFFFFFEL
33678 //RLC_SPM_INT_STATUS
33679 #define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT                                                         0x0
33680 #define RLC_SPM_INT_STATUS__RESERVED__SHIFT                                                                   0x1
33681 #define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK                                                           0x00000001L
33682 #define RLC_SPM_INT_STATUS__RESERVED_MASK                                                                     0xFFFFFFFEL
33683 //RLC_SMU_MESSAGE
33684 #define RLC_SMU_MESSAGE__CMD__SHIFT                                                                           0x0
33685 #define RLC_SMU_MESSAGE__CMD_MASK                                                                             0xFFFFFFFFL
33686 //RLC_GPM_LOG_SIZE
33687 #define RLC_GPM_LOG_SIZE__SIZE__SHIFT                                                                         0x0
33688 #define RLC_GPM_LOG_SIZE__SIZE_MASK                                                                           0xFFFFFFFFL
33689 //RLC_PG_DELAY_3
33690 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT                                                        0x0
33691 #define RLC_PG_DELAY_3__RESERVED__SHIFT                                                                       0x8
33692 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK                                                          0x000000FFL
33693 #define RLC_PG_DELAY_3__RESERVED_MASK                                                                         0xFFFFFF00L
33694 //RLC_GPR_REG1
33695 #define RLC_GPR_REG1__DATA__SHIFT                                                                             0x0
33696 #define RLC_GPR_REG1__DATA_MASK                                                                               0xFFFFFFFFL
33697 //RLC_GPR_REG2
33698 #define RLC_GPR_REG2__DATA__SHIFT                                                                             0x0
33699 #define RLC_GPR_REG2__DATA_MASK                                                                               0xFFFFFFFFL
33700 //RLC_GPM_LOG_CONT
33701 #define RLC_GPM_LOG_CONT__CONT__SHIFT                                                                         0x0
33702 #define RLC_GPM_LOG_CONT__CONT_MASK                                                                           0xFFFFFFFFL
33703 //RLC_GPM_INT_DISABLE_TH0
33704 #define RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT                                                               0x0
33705 #define RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK                                                                 0xFFFFFFFFL
33706 //RLC_GPM_INT_FORCE_TH0
33707 #define RLC_GPM_INT_FORCE_TH0__FORCE__SHIFT                                                                   0x0
33708 #define RLC_GPM_INT_FORCE_TH0__FORCE_MASK                                                                     0xFFFFFFFFL
33709 //RLC_SRM_CNTL
33710 #define RLC_SRM_CNTL__SRM_ENABLE__SHIFT                                                                       0x0
33711 #define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT                                                                   0x1
33712 #define RLC_SRM_CNTL__RESERVED__SHIFT                                                                         0x2
33713 #define RLC_SRM_CNTL__SRM_ENABLE_MASK                                                                         0x00000001L
33714 #define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK                                                                     0x00000002L
33715 #define RLC_SRM_CNTL__RESERVED_MASK                                                                           0xFFFFFFFCL
33716 //RLC_SRM_GPM_COMMAND
33717 #define RLC_SRM_GPM_COMMAND__OP__SHIFT                                                                        0x0
33718 #define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT                                                                0x1
33719 #define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT                                                            0x2
33720 #define RLC_SRM_GPM_COMMAND__SIZE__SHIFT                                                                      0x5
33721 #define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT                                                              0x11
33722 #define RLC_SRM_GPM_COMMAND__RESERVED1__SHIFT                                                                 0x1d
33723 #define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT                                                               0x1f
33724 #define RLC_SRM_GPM_COMMAND__OP_MASK                                                                          0x00000001L
33725 #define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK                                                                  0x00000002L
33726 #define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK                                                              0x0000001CL
33727 #define RLC_SRM_GPM_COMMAND__SIZE_MASK                                                                        0x0001FFE0L
33728 #define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK                                                                0x1FFE0000L
33729 #define RLC_SRM_GPM_COMMAND__RESERVED1_MASK                                                                   0x60000000L
33730 #define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK                                                                 0x80000000L
33731 //RLC_SRM_GPM_COMMAND_STATUS
33732 #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT                                                         0x0
33733 #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT                                                          0x1
33734 #define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT                                                           0x2
33735 #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK                                                           0x00000001L
33736 #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK                                                            0x00000002L
33737 #define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK                                                             0xFFFFFFFCL
33738 //RLC_SRM_RLCV_COMMAND
33739 #define RLC_SRM_RLCV_COMMAND__OP__SHIFT                                                                       0x0
33740 #define RLC_SRM_RLCV_COMMAND__RESERVED__SHIFT                                                                 0x1
33741 #define RLC_SRM_RLCV_COMMAND__SIZE__SHIFT                                                                     0x4
33742 #define RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT                                                             0x10
33743 #define RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT                                                                0x1c
33744 #define RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT                                                              0x1f
33745 #define RLC_SRM_RLCV_COMMAND__OP_MASK                                                                         0x00000001L
33746 #define RLC_SRM_RLCV_COMMAND__RESERVED_MASK                                                                   0x0000000EL
33747 #define RLC_SRM_RLCV_COMMAND__SIZE_MASK                                                                       0x0000FFF0L
33748 #define RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK                                                               0x0FFF0000L
33749 #define RLC_SRM_RLCV_COMMAND__RESERVED1_MASK                                                                  0x70000000L
33750 #define RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK                                                                0x80000000L
33751 //RLC_SRM_RLCV_COMMAND_STATUS
33752 #define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT                                                        0x0
33753 #define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT                                                         0x1
33754 #define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT                                                          0x2
33755 #define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK                                                          0x00000001L
33756 #define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK                                                           0x00000002L
33757 #define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK                                                            0xFFFFFFFCL
33758 //RLC_SRM_INDEX_CNTL_ADDR_0
33759 #define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT                                                             0x0
33760 #define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT                                                            0x10
33761 #define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK                                                               0x0000FFFFL
33762 #define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK                                                              0xFFFF0000L
33763 //RLC_SRM_INDEX_CNTL_ADDR_1
33764 #define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT                                                             0x0
33765 #define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT                                                            0x10
33766 #define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK                                                               0x0000FFFFL
33767 #define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK                                                              0xFFFF0000L
33768 //RLC_SRM_INDEX_CNTL_ADDR_2
33769 #define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT                                                             0x0
33770 #define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT                                                            0x10
33771 #define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK                                                               0x0000FFFFL
33772 #define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK                                                              0xFFFF0000L
33773 //RLC_SRM_INDEX_CNTL_ADDR_3
33774 #define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT                                                             0x0
33775 #define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT                                                            0x10
33776 #define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK                                                               0x0000FFFFL
33777 #define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK                                                              0xFFFF0000L
33778 //RLC_SRM_INDEX_CNTL_ADDR_4
33779 #define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT                                                             0x0
33780 #define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT                                                            0x10
33781 #define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK                                                               0x0000FFFFL
33782 #define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK                                                              0xFFFF0000L
33783 //RLC_SRM_INDEX_CNTL_ADDR_5
33784 #define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT                                                             0x0
33785 #define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT                                                            0x10
33786 #define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK                                                               0x0000FFFFL
33787 #define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK                                                              0xFFFF0000L
33788 //RLC_SRM_INDEX_CNTL_ADDR_6
33789 #define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT                                                             0x0
33790 #define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT                                                            0x10
33791 #define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK                                                               0x0000FFFFL
33792 #define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK                                                              0xFFFF0000L
33793 //RLC_SRM_INDEX_CNTL_ADDR_7
33794 #define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT                                                             0x0
33795 #define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT                                                            0x10
33796 #define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK                                                               0x0000FFFFL
33797 #define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK                                                              0xFFFF0000L
33798 //RLC_SRM_INDEX_CNTL_DATA_0
33799 #define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT                                                                0x0
33800 #define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK                                                                  0xFFFFFFFFL
33801 //RLC_SRM_INDEX_CNTL_DATA_1
33802 #define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT                                                                0x0
33803 #define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK                                                                  0xFFFFFFFFL
33804 //RLC_SRM_INDEX_CNTL_DATA_2
33805 #define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT                                                                0x0
33806 #define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK                                                                  0xFFFFFFFFL
33807 //RLC_SRM_INDEX_CNTL_DATA_3
33808 #define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT                                                                0x0
33809 #define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK                                                                  0xFFFFFFFFL
33810 //RLC_SRM_INDEX_CNTL_DATA_4
33811 #define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT                                                                0x0
33812 #define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK                                                                  0xFFFFFFFFL
33813 //RLC_SRM_INDEX_CNTL_DATA_5
33814 #define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT                                                                0x0
33815 #define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK                                                                  0xFFFFFFFFL
33816 //RLC_SRM_INDEX_CNTL_DATA_6
33817 #define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT                                                                0x0
33818 #define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK                                                                  0xFFFFFFFFL
33819 //RLC_SRM_INDEX_CNTL_DATA_7
33820 #define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT                                                                0x0
33821 #define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK                                                                  0xFFFFFFFFL
33822 //RLC_SRM_STAT
33823 #define RLC_SRM_STAT__SRM_BUSY__SHIFT                                                                         0x0
33824 #define RLC_SRM_STAT__SRM_BUSY_DELAY__SHIFT                                                                   0x1
33825 #define RLC_SRM_STAT__RESERVED__SHIFT                                                                         0x2
33826 #define RLC_SRM_STAT__SRM_BUSY_MASK                                                                           0x00000001L
33827 #define RLC_SRM_STAT__SRM_BUSY_DELAY_MASK                                                                     0x00000002L
33828 #define RLC_SRM_STAT__RESERVED_MASK                                                                           0xFFFFFFFCL
33829 //RLC_SRM_GPM_ABORT
33830 #define RLC_SRM_GPM_ABORT__ABORT__SHIFT                                                                       0x0
33831 #define RLC_SRM_GPM_ABORT__RESERVED__SHIFT                                                                    0x1
33832 #define RLC_SRM_GPM_ABORT__ABORT_MASK                                                                         0x00000001L
33833 #define RLC_SRM_GPM_ABORT__RESERVED_MASK                                                                      0xFFFFFFFEL
33834 //RLC_CSIB_ADDR_LO
33835 #define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT                                                                      0x0
33836 #define RLC_CSIB_ADDR_LO__ADDRESS_MASK                                                                        0xFFFFFFFFL
33837 //RLC_CSIB_ADDR_HI
33838 #define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT                                                                      0x0
33839 #define RLC_CSIB_ADDR_HI__ADDRESS_MASK                                                                        0x0000FFFFL
33840 //RLC_CSIB_LENGTH
33841 #define RLC_CSIB_LENGTH__LENGTH__SHIFT                                                                        0x0
33842 #define RLC_CSIB_LENGTH__LENGTH_MASK                                                                          0xFFFFFFFFL
33843 //RLC_PACE_INT_STAT
33844 #define RLC_PACE_INT_STAT__STATUS__SHIFT                                                                      0x0
33845 #define RLC_PACE_INT_STAT__STATUS_MASK                                                                        0xFFFFFFFFL
33846 //RLC_SMU_COMMAND
33847 #define RLC_SMU_COMMAND__CMD__SHIFT                                                                           0x0
33848 #define RLC_SMU_COMMAND__CMD_MASK                                                                             0xFFFFFFFFL
33849 //RLC_CP_SCHEDULERS
33850 #define RLC_CP_SCHEDULERS__scheduler0__SHIFT                                                                  0x0
33851 #define RLC_CP_SCHEDULERS__scheduler1__SHIFT                                                                  0x8
33852 #define RLC_CP_SCHEDULERS__scheduler2__SHIFT                                                                  0x10
33853 #define RLC_CP_SCHEDULERS__scheduler3__SHIFT                                                                  0x18
33854 #define RLC_CP_SCHEDULERS__scheduler0_MASK                                                                    0x000000FFL
33855 #define RLC_CP_SCHEDULERS__scheduler1_MASK                                                                    0x0000FF00L
33856 #define RLC_CP_SCHEDULERS__scheduler2_MASK                                                                    0x00FF0000L
33857 #define RLC_CP_SCHEDULERS__scheduler3_MASK                                                                    0xFF000000L
33858 //RLC_SMU_ARGUMENT_1
33859 #define RLC_SMU_ARGUMENT_1__ARG__SHIFT                                                                        0x0
33860 #define RLC_SMU_ARGUMENT_1__ARG_MASK                                                                          0xFFFFFFFFL
33861 //RLC_SMU_ARGUMENT_2
33862 #define RLC_SMU_ARGUMENT_2__ARG__SHIFT                                                                        0x0
33863 #define RLC_SMU_ARGUMENT_2__ARG_MASK                                                                          0xFFFFFFFFL
33864 //RLC_GPM_GENERAL_8
33865 #define RLC_GPM_GENERAL_8__DATA__SHIFT                                                                        0x0
33866 #define RLC_GPM_GENERAL_8__DATA_MASK                                                                          0xFFFFFFFFL
33867 //RLC_GPM_GENERAL_9
33868 #define RLC_GPM_GENERAL_9__DATA__SHIFT                                                                        0x0
33869 #define RLC_GPM_GENERAL_9__DATA_MASK                                                                          0xFFFFFFFFL
33870 //RLC_GPM_GENERAL_10
33871 #define RLC_GPM_GENERAL_10__DATA__SHIFT                                                                       0x0
33872 #define RLC_GPM_GENERAL_10__DATA_MASK                                                                         0xFFFFFFFFL
33873 //RLC_GPM_GENERAL_11
33874 #define RLC_GPM_GENERAL_11__DATA__SHIFT                                                                       0x0
33875 #define RLC_GPM_GENERAL_11__DATA_MASK                                                                         0xFFFFFFFFL
33876 //RLC_GPM_GENERAL_12
33877 #define RLC_GPM_GENERAL_12__DATA__SHIFT                                                                       0x0
33878 #define RLC_GPM_GENERAL_12__DATA_MASK                                                                         0xFFFFFFFFL
33879 //RLC_GPM_UTCL1_CNTL_0
33880 #define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT__SHIFT                                                     0x0
33881 #define RLC_GPM_UTCL1_CNTL_0__DROP_MODE__SHIFT                                                                0x18
33882 #define RLC_GPM_UTCL1_CNTL_0__BYPASS__SHIFT                                                                   0x19
33883 #define RLC_GPM_UTCL1_CNTL_0__INVALIDATE__SHIFT                                                               0x1a
33884 #define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE__SHIFT                                                          0x1b
33885 #define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP__SHIFT                                                              0x1c
33886 #define RLC_GPM_UTCL1_CNTL_0__RESERVED__SHIFT                                                                 0x1e
33887 #define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT_MASK                                                       0x000FFFFFL
33888 #define RLC_GPM_UTCL1_CNTL_0__DROP_MODE_MASK                                                                  0x01000000L
33889 #define RLC_GPM_UTCL1_CNTL_0__BYPASS_MASK                                                                     0x02000000L
33890 #define RLC_GPM_UTCL1_CNTL_0__INVALIDATE_MASK                                                                 0x04000000L
33891 #define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE_MASK                                                            0x08000000L
33892 #define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP_MASK                                                                0x10000000L
33893 #define RLC_GPM_UTCL1_CNTL_0__RESERVED_MASK                                                                   0xC0000000L
33894 //RLC_GPM_UTCL1_CNTL_1
33895 #define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT__SHIFT                                                     0x0
33896 #define RLC_GPM_UTCL1_CNTL_1__DROP_MODE__SHIFT                                                                0x18
33897 #define RLC_GPM_UTCL1_CNTL_1__BYPASS__SHIFT                                                                   0x19
33898 #define RLC_GPM_UTCL1_CNTL_1__INVALIDATE__SHIFT                                                               0x1a
33899 #define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE__SHIFT                                                          0x1b
33900 #define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP__SHIFT                                                              0x1c
33901 #define RLC_GPM_UTCL1_CNTL_1__RESERVED__SHIFT                                                                 0x1e
33902 #define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT_MASK                                                       0x000FFFFFL
33903 #define RLC_GPM_UTCL1_CNTL_1__DROP_MODE_MASK                                                                  0x01000000L
33904 #define RLC_GPM_UTCL1_CNTL_1__BYPASS_MASK                                                                     0x02000000L
33905 #define RLC_GPM_UTCL1_CNTL_1__INVALIDATE_MASK                                                                 0x04000000L
33906 #define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE_MASK                                                            0x08000000L
33907 #define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP_MASK                                                                0x10000000L
33908 #define RLC_GPM_UTCL1_CNTL_1__RESERVED_MASK                                                                   0xC0000000L
33909 //RLC_GPM_UTCL1_CNTL_2
33910 #define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT__SHIFT                                                     0x0
33911 #define RLC_GPM_UTCL1_CNTL_2__DROP_MODE__SHIFT                                                                0x18
33912 #define RLC_GPM_UTCL1_CNTL_2__BYPASS__SHIFT                                                                   0x19
33913 #define RLC_GPM_UTCL1_CNTL_2__INVALIDATE__SHIFT                                                               0x1a
33914 #define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE__SHIFT                                                          0x1b
33915 #define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP__SHIFT                                                              0x1c
33916 #define RLC_GPM_UTCL1_CNTL_2__RESERVED__SHIFT                                                                 0x1e
33917 #define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT_MASK                                                       0x000FFFFFL
33918 #define RLC_GPM_UTCL1_CNTL_2__DROP_MODE_MASK                                                                  0x01000000L
33919 #define RLC_GPM_UTCL1_CNTL_2__BYPASS_MASK                                                                     0x02000000L
33920 #define RLC_GPM_UTCL1_CNTL_2__INVALIDATE_MASK                                                                 0x04000000L
33921 #define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE_MASK                                                            0x08000000L
33922 #define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP_MASK                                                                0x10000000L
33923 #define RLC_GPM_UTCL1_CNTL_2__RESERVED_MASK                                                                   0xC0000000L
33924 //RLC_SPM_UTCL1_CNTL
33925 #define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT                                                       0x0
33926 #define RLC_SPM_UTCL1_CNTL__DROP_MODE__SHIFT                                                                  0x18
33927 #define RLC_SPM_UTCL1_CNTL__BYPASS__SHIFT                                                                     0x19
33928 #define RLC_SPM_UTCL1_CNTL__INVALIDATE__SHIFT                                                                 0x1a
33929 #define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT                                                            0x1b
33930 #define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP__SHIFT                                                                0x1c
33931 #define RLC_SPM_UTCL1_CNTL__RESERVED__SHIFT                                                                   0x1e
33932 #define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK                                                         0x000FFFFFL
33933 #define RLC_SPM_UTCL1_CNTL__DROP_MODE_MASK                                                                    0x01000000L
33934 #define RLC_SPM_UTCL1_CNTL__BYPASS_MASK                                                                       0x02000000L
33935 #define RLC_SPM_UTCL1_CNTL__INVALIDATE_MASK                                                                   0x04000000L
33936 #define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK                                                              0x08000000L
33937 #define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP_MASK                                                                  0x10000000L
33938 #define RLC_SPM_UTCL1_CNTL__RESERVED_MASK                                                                     0xC0000000L
33939 //RLC_UTCL1_STATUS_2
33940 #define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY__SHIFT                                                         0x0
33941 #define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY__SHIFT                                                         0x1
33942 #define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY__SHIFT                                                         0x2
33943 #define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY__SHIFT                                                             0x3
33944 #define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY__SHIFT                                                       0x4
33945 #define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans__SHIFT                                                 0x5
33946 #define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans__SHIFT                                                 0x6
33947 #define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans__SHIFT                                                 0x7
33948 #define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans__SHIFT                                                     0x8
33949 #define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans__SHIFT                                               0x9
33950 #define RLC_UTCL1_STATUS_2__RESERVED__SHIFT                                                                   0xa
33951 #define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY_MASK                                                           0x00000001L
33952 #define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY_MASK                                                           0x00000002L
33953 #define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY_MASK                                                           0x00000004L
33954 #define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY_MASK                                                               0x00000008L
33955 #define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY_MASK                                                         0x00000010L
33956 #define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans_MASK                                                   0x00000020L
33957 #define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans_MASK                                                   0x00000040L
33958 #define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans_MASK                                                   0x00000080L
33959 #define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans_MASK                                                       0x00000100L
33960 #define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans_MASK                                                 0x00000200L
33961 #define RLC_UTCL1_STATUS_2__RESERVED_MASK                                                                     0xFFFFFC00L
33962 //RLC_LB_CONFIG_2
33963 #define RLC_LB_CONFIG_2__DATA__SHIFT                                                                          0x0
33964 #define RLC_LB_CONFIG_2__DATA_MASK                                                                            0xFFFFFFFFL
33965 //RLC_LB_CONFIG_3
33966 #define RLC_LB_CONFIG_3__DATA__SHIFT                                                                          0x0
33967 #define RLC_LB_CONFIG_3__DATA_MASK                                                                            0xFFFFFFFFL
33968 //RLC_LB_CONFIG_4
33969 #define RLC_LB_CONFIG_4__DATA__SHIFT                                                                          0x0
33970 #define RLC_LB_CONFIG_4__DATA_MASK                                                                            0xFFFFFFFFL
33971 //RLC_SPM_UTCL1_ERROR_1
33972 #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError__SHIFT                                                     0x0
33973 #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT                                                 0x2
33974 #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT                                             0x6
33975 #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError_MASK                                                       0x00000003L
33976 #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK                                                   0x0000003CL
33977 #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK                                               0x000003C0L
33978 //RLC_SPM_UTCL1_ERROR_2
33979 #define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT                                             0x0
33980 #define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK                                               0xFFFFFFFFL
33981 //RLC_GPM_UTCL1_TH0_ERROR_1
33982 #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError__SHIFT                                                 0x0
33983 #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid__SHIFT                                             0x2
33984 #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT                                         0x6
33985 #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError_MASK                                                   0x00000003L
33986 #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid_MASK                                               0x0000003CL
33987 #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB_MASK                                           0x000003C0L
33988 //RLC_LB_CONFIG_1
33989 #define RLC_LB_CONFIG_1__DATA__SHIFT                                                                          0x0
33990 #define RLC_LB_CONFIG_1__DATA_MASK                                                                            0xFFFFFFFFL
33991 //RLC_GPM_UTCL1_TH0_ERROR_2
33992 #define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT                                         0x0
33993 #define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB_MASK                                           0xFFFFFFFFL
33994 //RLC_GPM_UTCL1_TH1_ERROR_1
33995 #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError__SHIFT                                                 0x0
33996 #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid__SHIFT                                             0x2
33997 #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT                                         0x6
33998 #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError_MASK                                                   0x00000003L
33999 #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid_MASK                                               0x0000003CL
34000 #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK                                           0x000003C0L
34001 //RLC_GPM_UTCL1_TH1_ERROR_2
34002 #define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT                                         0x0
34003 #define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK                                           0xFFFFFFFFL
34004 //RLC_GPM_UTCL1_TH2_ERROR_1
34005 #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError__SHIFT                                                 0x0
34006 #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid__SHIFT                                             0x2
34007 #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT                                         0x6
34008 #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError_MASK                                                   0x00000003L
34009 #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid_MASK                                               0x0000003CL
34010 #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB_MASK                                           0x000003C0L
34011 //RLC_GPM_UTCL1_TH2_ERROR_2
34012 #define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT                                         0x0
34013 #define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB_MASK                                           0xFFFFFFFFL
34014 //RLC_CGCG_CGLS_CTRL_3D
34015 #define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN__SHIFT                                                                 0x0
34016 #define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN__SHIFT                                                                 0x1
34017 #define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT                                                0x2
34018 #define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT                                                 0x8
34019 #define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER__SHIFT                                                         0x1b
34020 #define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL__SHIFT                                                           0x1c
34021 #define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE__SHIFT                                                              0x1d
34022 #define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN__SHIFT                                                          0x1f
34023 #define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK                                                                   0x00000001L
34024 #define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK                                                                   0x00000002L
34025 #define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK                                                  0x000000FCL
34026 #define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK                                                   0x07FFFF00L
34027 #define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER_MASK                                                           0x08000000L
34028 #define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL_MASK                                                             0x10000000L
34029 #define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE_MASK                                                                0x60000000L
34030 #define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN_MASK                                                            0x80000000L
34031 //RLC_CGCG_RAMP_CTRL_3D
34032 #define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT__SHIFT                                                     0x0
34033 #define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT__SHIFT                                                      0x4
34034 #define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT__SHIFT                                                       0x8
34035 #define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT__SHIFT                                                        0xc
34036 #define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT__SHIFT                                                          0x10
34037 #define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT__SHIFT                                                         0x1c
34038 #define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT_MASK                                                       0x0000000FL
34039 #define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT_MASK                                                        0x000000F0L
34040 #define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT_MASK                                                         0x00000F00L
34041 #define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT_MASK                                                          0x0000F000L
34042 #define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT_MASK                                                            0x0FFF0000L
34043 #define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT_MASK                                                           0xF0000000L
34044 //RLC_SEMAPHORE_0
34045 #define RLC_SEMAPHORE_0__CLIENT_ID__SHIFT                                                                     0x0
34046 #define RLC_SEMAPHORE_0__RESERVED__SHIFT                                                                      0x5
34047 #define RLC_SEMAPHORE_0__CLIENT_ID_MASK                                                                       0x0000001FL
34048 #define RLC_SEMAPHORE_0__RESERVED_MASK                                                                        0xFFFFFFE0L
34049 //RLC_SEMAPHORE_1
34050 #define RLC_SEMAPHORE_1__CLIENT_ID__SHIFT                                                                     0x0
34051 #define RLC_SEMAPHORE_1__RESERVED__SHIFT                                                                      0x5
34052 #define RLC_SEMAPHORE_1__CLIENT_ID_MASK                                                                       0x0000001FL
34053 #define RLC_SEMAPHORE_1__RESERVED_MASK                                                                        0xFFFFFFE0L
34054 //RLC_CP_EOF_INT
34055 #define RLC_CP_EOF_INT__INTERRUPT__SHIFT                                                                      0x0
34056 #define RLC_CP_EOF_INT__RESERVED__SHIFT                                                                       0x1
34057 #define RLC_CP_EOF_INT__INTERRUPT_MASK                                                                        0x00000001L
34058 #define RLC_CP_EOF_INT__RESERVED_MASK                                                                         0xFFFFFFFEL
34059 //RLC_CP_EOF_INT_CNT
34060 #define RLC_CP_EOF_INT_CNT__CNT__SHIFT                                                                        0x0
34061 #define RLC_CP_EOF_INT_CNT__CNT_MASK                                                                          0xFFFFFFFFL
34062 //RLC_SPARE_INT
34063 #define RLC_SPARE_INT__INTERRUPT__SHIFT                                                                       0x0
34064 #define RLC_SPARE_INT__RESERVED__SHIFT                                                                        0x1
34065 #define RLC_SPARE_INT__INTERRUPT_MASK                                                                         0x00000001L
34066 #define RLC_SPARE_INT__RESERVED_MASK                                                                          0xFFFFFFFEL
34067 //RLC_PREWALKER_UTCL1_CNTL
34068 #define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT                                                 0x0
34069 #define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE__SHIFT                                                            0x18
34070 #define RLC_PREWALKER_UTCL1_CNTL__BYPASS__SHIFT                                                               0x19
34071 #define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE__SHIFT                                                           0x1a
34072 #define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT                                                      0x1b
34073 #define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP__SHIFT                                                          0x1c
34074 #define RLC_PREWALKER_UTCL1_CNTL__RESERVED__SHIFT                                                             0x1e
34075 #define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK                                                   0x000FFFFFL
34076 #define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE_MASK                                                              0x01000000L
34077 #define RLC_PREWALKER_UTCL1_CNTL__BYPASS_MASK                                                                 0x02000000L
34078 #define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE_MASK                                                             0x04000000L
34079 #define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK                                                        0x08000000L
34080 #define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP_MASK                                                            0x10000000L
34081 #define RLC_PREWALKER_UTCL1_CNTL__RESERVED_MASK                                                               0xC0000000L
34082 //RLC_PREWALKER_UTCL1_TRIG
34083 #define RLC_PREWALKER_UTCL1_TRIG__VALID__SHIFT                                                                0x0
34084 #define RLC_PREWALKER_UTCL1_TRIG__VMID__SHIFT                                                                 0x1
34085 #define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE__SHIFT                                                           0x5
34086 #define RLC_PREWALKER_UTCL1_TRIG__READ_PERM__SHIFT                                                            0x6
34087 #define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM__SHIFT                                                           0x7
34088 #define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM__SHIFT                                                            0x8
34089 #define RLC_PREWALKER_UTCL1_TRIG__RESERVED__SHIFT                                                             0x9
34090 #define RLC_PREWALKER_UTCL1_TRIG__READY__SHIFT                                                                0x1f
34091 #define RLC_PREWALKER_UTCL1_TRIG__VALID_MASK                                                                  0x00000001L
34092 #define RLC_PREWALKER_UTCL1_TRIG__VMID_MASK                                                                   0x0000001EL
34093 #define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE_MASK                                                             0x00000020L
34094 #define RLC_PREWALKER_UTCL1_TRIG__READ_PERM_MASK                                                              0x00000040L
34095 #define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM_MASK                                                             0x00000080L
34096 #define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM_MASK                                                              0x00000100L
34097 #define RLC_PREWALKER_UTCL1_TRIG__RESERVED_MASK                                                               0x7FFFFE00L
34098 #define RLC_PREWALKER_UTCL1_TRIG__READY_MASK                                                                  0x80000000L
34099 //RLC_PREWALKER_UTCL1_ADDR_LSB
34100 #define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB__SHIFT                                                         0x0
34101 #define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB_MASK                                                           0xFFFFFFFFL
34102 //RLC_PREWALKER_UTCL1_ADDR_MSB
34103 #define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB__SHIFT                                                         0x0
34104 #define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB_MASK                                                           0x0000FFFFL
34105 //RLC_PREWALKER_UTCL1_SIZE_LSB
34106 #define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB__SHIFT                                                         0x0
34107 #define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB_MASK                                                           0xFFFFFFFFL
34108 //RLC_PREWALKER_UTCL1_SIZE_MSB
34109 #define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB__SHIFT                                                         0x0
34110 #define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB_MASK                                                           0x00000003L
34111 //RLC_UTCL1_STATUS
34112 #define RLC_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                               0x0
34113 #define RLC_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                               0x1
34114 #define RLC_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                 0x2
34115 #define RLC_UTCL1_STATUS__RESERVED__SHIFT                                                                     0x3
34116 #define RLC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT                                                                0x8
34117 #define RLC_UTCL1_STATUS__RESERVED_1__SHIFT                                                                   0xe
34118 #define RLC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT                                                                0x10
34119 #define RLC_UTCL1_STATUS__RESERVED_2__SHIFT                                                                   0x16
34120 #define RLC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT                                                                  0x18
34121 #define RLC_UTCL1_STATUS__RESERVED_3__SHIFT                                                                   0x1e
34122 #define RLC_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                 0x00000001L
34123 #define RLC_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                 0x00000002L
34124 #define RLC_UTCL1_STATUS__PRT_DETECTED_MASK                                                                   0x00000004L
34125 #define RLC_UTCL1_STATUS__RESERVED_MASK                                                                       0x000000F8L
34126 #define RLC_UTCL1_STATUS__FAULT_UTCL1ID_MASK                                                                  0x00003F00L
34127 #define RLC_UTCL1_STATUS__RESERVED_1_MASK                                                                     0x0000C000L
34128 #define RLC_UTCL1_STATUS__RETRY_UTCL1ID_MASK                                                                  0x003F0000L
34129 #define RLC_UTCL1_STATUS__RESERVED_2_MASK                                                                     0x00C00000L
34130 #define RLC_UTCL1_STATUS__PRT_UTCL1ID_MASK                                                                    0x3F000000L
34131 #define RLC_UTCL1_STATUS__RESERVED_3_MASK                                                                     0xC0000000L
34132 //RLC_R2I_CNTL_0
34133 #define RLC_R2I_CNTL_0__Data__SHIFT                                                                           0x0
34134 #define RLC_R2I_CNTL_0__Data_MASK                                                                             0xFFFFFFFFL
34135 //RLC_R2I_CNTL_1
34136 #define RLC_R2I_CNTL_1__Data__SHIFT                                                                           0x0
34137 #define RLC_R2I_CNTL_1__Data_MASK                                                                             0xFFFFFFFFL
34138 //RLC_R2I_CNTL_2
34139 #define RLC_R2I_CNTL_2__Data__SHIFT                                                                           0x0
34140 #define RLC_R2I_CNTL_2__Data_MASK                                                                             0xFFFFFFFFL
34141 //RLC_R2I_CNTL_3
34142 #define RLC_R2I_CNTL_3__Data__SHIFT                                                                           0x0
34143 #define RLC_R2I_CNTL_3__Data_MASK                                                                             0xFFFFFFFFL
34144 //RLC_LB_WGP_STAT
34145 #define RLC_LB_WGP_STAT__MAX_WGP__SHIFT                                                                       0x0
34146 #define RLC_LB_WGP_STAT__ON_WGP__SHIFT                                                                        0x10
34147 #define RLC_LB_WGP_STAT__MAX_WGP_MASK                                                                         0x0000FFFFL
34148 #define RLC_LB_WGP_STAT__ON_WGP_MASK                                                                          0xFFFF0000L
34149 //RLC_GPM_INT_STAT_TH0
34150 #define RLC_GPM_INT_STAT_TH0__STATUS__SHIFT                                                                   0x0
34151 #define RLC_GPM_INT_STAT_TH0__STATUS_MASK                                                                     0xFFFFFFFFL
34152 //RLC_GPM_GENERAL_13
34153 #define RLC_GPM_GENERAL_13__DATA__SHIFT                                                                       0x0
34154 #define RLC_GPM_GENERAL_13__DATA_MASK                                                                         0xFFFFFFFFL
34155 //RLC_GPM_GENERAL_14
34156 #define RLC_GPM_GENERAL_14__DATA__SHIFT                                                                       0x0
34157 #define RLC_GPM_GENERAL_14__DATA_MASK                                                                         0xFFFFFFFFL
34158 //RLC_GPM_GENERAL_15
34159 #define RLC_GPM_GENERAL_15__DATA__SHIFT                                                                       0x0
34160 #define RLC_GPM_GENERAL_15__DATA_MASK                                                                         0xFFFFFFFFL
34161 //RLC_SPARE_INT_1
34162 #define RLC_SPARE_INT_1__INTERRUPT__SHIFT                                                                     0x0
34163 #define RLC_SPARE_INT_1__RESERVED__SHIFT                                                                      0x1
34164 #define RLC_SPARE_INT_1__INTERRUPT_MASK                                                                       0x00000001L
34165 #define RLC_SPARE_INT_1__RESERVED_MASK                                                                        0xFFFFFFFEL
34166 //RLC_RLCV_SPARE_INT_1
34167 #define RLC_RLCV_SPARE_INT_1__INTERRUPT__SHIFT                                                                0x0
34168 #define RLC_RLCV_SPARE_INT_1__RESERVED__SHIFT                                                                 0x1
34169 #define RLC_RLCV_SPARE_INT_1__INTERRUPT_MASK                                                                  0x00000001L
34170 #define RLC_RLCV_SPARE_INT_1__RESERVED_MASK                                                                   0xFFFFFFFEL
34171 //RLC_PACE_SPARE_INT_1
34172 #define RLC_PACE_SPARE_INT_1__INTERRUPT__SHIFT                                                                0x0
34173 #define RLC_PACE_SPARE_INT_1__RESERVED__SHIFT                                                                 0x1
34174 #define RLC_PACE_SPARE_INT_1__INTERRUPT_MASK                                                                  0x00000001L
34175 #define RLC_PACE_SPARE_INT_1__RESERVED_MASK                                                                   0xFFFFFFFEL
34176 //RLC_SEMAPHORE_2
34177 #define RLC_SEMAPHORE_2__CLIENT_ID__SHIFT                                                                     0x0
34178 #define RLC_SEMAPHORE_2__RESERVED__SHIFT                                                                      0x5
34179 #define RLC_SEMAPHORE_2__CLIENT_ID_MASK                                                                       0x0000001FL
34180 #define RLC_SEMAPHORE_2__RESERVED_MASK                                                                        0xFFFFFFE0L
34181 //RLC_SEMAPHORE_3
34182 #define RLC_SEMAPHORE_3__CLIENT_ID__SHIFT                                                                     0x0
34183 #define RLC_SEMAPHORE_3__RESERVED__SHIFT                                                                      0x5
34184 #define RLC_SEMAPHORE_3__CLIENT_ID_MASK                                                                       0x0000001FL
34185 #define RLC_SEMAPHORE_3__RESERVED_MASK                                                                        0xFFFFFFE0L
34186 //RLC_SMU_ARGUMENT_3
34187 #define RLC_SMU_ARGUMENT_3__ARG__SHIFT                                                                        0x0
34188 #define RLC_SMU_ARGUMENT_3__ARG_MASK                                                                          0xFFFFFFFFL
34189 //RLC_SMU_ARGUMENT_4
34190 #define RLC_SMU_ARGUMENT_4__ARG__SHIFT                                                                        0x0
34191 #define RLC_SMU_ARGUMENT_4__ARG_MASK                                                                          0xFFFFFFFFL
34192 //RLC_GPU_CLOCK_COUNT_LSB_1
34193 #define RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB__SHIFT                                                      0x0
34194 #define RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB_MASK                                                        0xFFFFFFFFL
34195 //RLC_GPU_CLOCK_COUNT_MSB_1
34196 #define RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB__SHIFT                                                      0x0
34197 #define RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB_MASK                                                        0xFFFFFFFFL
34198 //RLC_CAPTURE_GPU_CLOCK_COUNT_1
34199 #define RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE__SHIFT                                                         0x0
34200 #define RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED__SHIFT                                                        0x1
34201 #define RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE_MASK                                                           0x00000001L
34202 #define RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED_MASK                                                          0xFFFFFFFEL
34203 //RLC_GPU_CLOCK_COUNT_LSB_2
34204 #define RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB__SHIFT                                                      0x0
34205 #define RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB_MASK                                                        0xFFFFFFFFL
34206 //RLC_GPU_CLOCK_COUNT_MSB_2
34207 #define RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB__SHIFT                                                      0x0
34208 #define RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB_MASK                                                        0xFFFFFFFFL
34209 //RLC_PACE_INT_DISABLE
34210 #define RLC_PACE_INT_DISABLE__DISABLE__SHIFT                                                                  0x0
34211 #define RLC_PACE_INT_DISABLE__DISABLE_MASK                                                                    0xFFFFFFFFL
34212 //RLC_CAPTURE_GPU_CLOCK_COUNT_2
34213 #define RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE__SHIFT                                                         0x0
34214 #define RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED__SHIFT                                                        0x1
34215 #define RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE_MASK                                                           0x00000001L
34216 #define RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED_MASK                                                          0xFFFFFFFEL
34217 //RLC_RLCV_SPARE_INT
34218 #define RLC_RLCV_SPARE_INT__INTERRUPT__SHIFT                                                                  0x0
34219 #define RLC_RLCV_SPARE_INT__RESERVED__SHIFT                                                                   0x1
34220 #define RLC_RLCV_SPARE_INT__INTERRUPT_MASK                                                                    0x00000001L
34221 #define RLC_RLCV_SPARE_INT__RESERVED_MASK                                                                     0xFFFFFFFEL
34222 //RLC_PACE_TIMER_INT_0
34223 #define RLC_PACE_TIMER_INT_0__TIMER__SHIFT                                                                    0x0
34224 #define RLC_PACE_TIMER_INT_0__TIMER_MASK                                                                      0xFFFFFFFFL
34225 //RLC_PACE_TIMER_CTRL
34226 #define RLC_PACE_TIMER_CTRL__TIMER_0_EN__SHIFT                                                                0x0
34227 #define RLC_PACE_TIMER_CTRL__TIMER_1_EN__SHIFT                                                                0x1
34228 #define RLC_PACE_TIMER_CTRL__TIMER_0_AUTO_REARM__SHIFT                                                        0x2
34229 #define RLC_PACE_TIMER_CTRL__TIMER_1_AUTO_REARM__SHIFT                                                        0x3
34230 #define RLC_PACE_TIMER_CTRL__TIMER_0_INT_CLEAR__SHIFT                                                         0x4
34231 #define RLC_PACE_TIMER_CTRL__TIMER_1_INT_CLEAR__SHIFT                                                         0x5
34232 #define RLC_PACE_TIMER_CTRL__RESERVED__SHIFT                                                                  0x6
34233 #define RLC_PACE_TIMER_CTRL__TIMER_0_EN_MASK                                                                  0x00000001L
34234 #define RLC_PACE_TIMER_CTRL__TIMER_1_EN_MASK                                                                  0x00000002L
34235 #define RLC_PACE_TIMER_CTRL__TIMER_0_AUTO_REARM_MASK                                                          0x00000004L
34236 #define RLC_PACE_TIMER_CTRL__TIMER_1_AUTO_REARM_MASK                                                          0x00000008L
34237 #define RLC_PACE_TIMER_CTRL__TIMER_0_INT_CLEAR_MASK                                                           0x00000010L
34238 #define RLC_PACE_TIMER_CTRL__TIMER_1_INT_CLEAR_MASK                                                           0x00000020L
34239 #define RLC_PACE_TIMER_CTRL__RESERVED_MASK                                                                    0xFFFFFFC0L
34240 //RLC_PACE_TIMER_INT_1
34241 #define RLC_PACE_TIMER_INT_1__TIMER__SHIFT                                                                    0x0
34242 #define RLC_PACE_TIMER_INT_1__TIMER_MASK                                                                      0xFFFFFFFFL
34243 //RLC_PACE_SPARE_INT
34244 #define RLC_PACE_SPARE_INT__INTERRUPT__SHIFT                                                                  0x0
34245 #define RLC_PACE_SPARE_INT__RESERVED__SHIFT                                                                   0x1
34246 #define RLC_PACE_SPARE_INT__INTERRUPT_MASK                                                                    0x00000001L
34247 #define RLC_PACE_SPARE_INT__RESERVED_MASK                                                                     0xFFFFFFFEL
34248 //RLC_SMU_CLK_REQ
34249 #define RLC_SMU_CLK_REQ__VALID__SHIFT                                                                         0x0
34250 #define RLC_SMU_CLK_REQ__VALID_MASK                                                                           0x00000001L
34251 //RLC_CP_STAT_INVAL_STAT
34252 #define RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND__SHIFT                                                    0x0
34253 #define RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND__SHIFT                                                    0x1
34254 #define RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND__SHIFT                                                    0x2
34255 #define RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND_CHANGED__SHIFT                                            0x3
34256 #define RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND_CHANGED__SHIFT                                            0x4
34257 #define RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND_CHANGED__SHIFT                                            0x5
34258 #define RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND_MASK                                                      0x00000001L
34259 #define RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND_MASK                                                      0x00000002L
34260 #define RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND_MASK                                                      0x00000004L
34261 #define RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND_CHANGED_MASK                                              0x00000008L
34262 #define RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND_CHANGED_MASK                                              0x00000010L
34263 #define RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND_CHANGED_MASK                                              0x00000020L
34264 //RLC_CP_STAT_INVAL_CTRL
34265 #define RLC_CP_STAT_INVAL_CTRL__CPG_STAT_INVAL_PEND_EN__SHIFT                                                 0x0
34266 #define RLC_CP_STAT_INVAL_CTRL__CPC_STAT_INVAL_PEND_EN__SHIFT                                                 0x1
34267 #define RLC_CP_STAT_INVAL_CTRL__CPF_STAT_INVAL_PEND_EN__SHIFT                                                 0x2
34268 #define RLC_CP_STAT_INVAL_CTRL__CPG_STAT_INVAL_PEND_EN_MASK                                                   0x00000001L
34269 #define RLC_CP_STAT_INVAL_CTRL__CPC_STAT_INVAL_PEND_EN_MASK                                                   0x00000002L
34270 #define RLC_CP_STAT_INVAL_CTRL__CPF_STAT_INVAL_PEND_EN_MASK                                                   0x00000004L
34271 //RLC_SPP_CTRL
34272 #define RLC_SPP_CTRL__ENABLE__SHIFT                                                                           0x0
34273 #define RLC_SPP_CTRL__ENABLE_PPROF__SHIFT                                                                     0x1
34274 #define RLC_SPP_CTRL__ENABLE_PWR_OPT__SHIFT                                                                   0x2
34275 #define RLC_SPP_CTRL__PAUSE__SHIFT                                                                            0x3
34276 #define RLC_SPP_CTRL__ENABLE_MASK                                                                             0x00000001L
34277 #define RLC_SPP_CTRL__ENABLE_PPROF_MASK                                                                       0x00000002L
34278 #define RLC_SPP_CTRL__ENABLE_PWR_OPT_MASK                                                                     0x00000004L
34279 #define RLC_SPP_CTRL__PAUSE_MASK                                                                              0x00000008L
34280 //RLC_SPP_SHADER_PROFILE_EN
34281 #define RLC_SPP_SHADER_PROFILE_EN__PS_ENABLE__SHIFT                                                           0x0
34282 #define RLC_SPP_SHADER_PROFILE_EN__VS_ENABLE__SHIFT                                                           0x1
34283 #define RLC_SPP_SHADER_PROFILE_EN__GS_ENABLE__SHIFT                                                           0x2
34284 #define RLC_SPP_SHADER_PROFILE_EN__HS_ENABLE__SHIFT                                                           0x3
34285 #define RLC_SPP_SHADER_PROFILE_EN__CSG_ENABLE__SHIFT                                                          0x4
34286 #define RLC_SPP_SHADER_PROFILE_EN__CS_ENABLE__SHIFT                                                           0x5
34287 #define RLC_SPP_SHADER_PROFILE_EN__PS_STOP_CONDITION__SHIFT                                                   0x6
34288 #define RLC_SPP_SHADER_PROFILE_EN__VS_STOP_CONDITION__SHIFT                                                   0x7
34289 #define RLC_SPP_SHADER_PROFILE_EN__GS_STOP_CONDITION__SHIFT                                                   0x8
34290 #define RLC_SPP_SHADER_PROFILE_EN__HS_STOP_CONDITION__SHIFT                                                   0x9
34291 #define RLC_SPP_SHADER_PROFILE_EN__CSG_STOP_CONDITION__SHIFT                                                  0xa
34292 #define RLC_SPP_SHADER_PROFILE_EN__CS_STOP_CONDITION__SHIFT                                                   0xb
34293 #define RLC_SPP_SHADER_PROFILE_EN__PS_START_CONDITION__SHIFT                                                  0xc
34294 #define RLC_SPP_SHADER_PROFILE_EN__CS_START_CONDITION__SHIFT                                                  0xd
34295 #define RLC_SPP_SHADER_PROFILE_EN__FORCE_MISS__SHIFT                                                          0xe
34296 #define RLC_SPP_SHADER_PROFILE_EN__FORCE_UNLOCKED__SHIFT                                                      0xf
34297 #define RLC_SPP_SHADER_PROFILE_EN__ENABLE_PROF_INFO_LOCK__SHIFT                                               0x10
34298 #define RLC_SPP_SHADER_PROFILE_EN__PS_ENABLE_MASK                                                             0x00000001L
34299 #define RLC_SPP_SHADER_PROFILE_EN__VS_ENABLE_MASK                                                             0x00000002L
34300 #define RLC_SPP_SHADER_PROFILE_EN__GS_ENABLE_MASK                                                             0x00000004L
34301 #define RLC_SPP_SHADER_PROFILE_EN__HS_ENABLE_MASK                                                             0x00000008L
34302 #define RLC_SPP_SHADER_PROFILE_EN__CSG_ENABLE_MASK                                                            0x00000010L
34303 #define RLC_SPP_SHADER_PROFILE_EN__CS_ENABLE_MASK                                                             0x00000020L
34304 #define RLC_SPP_SHADER_PROFILE_EN__PS_STOP_CONDITION_MASK                                                     0x00000040L
34305 #define RLC_SPP_SHADER_PROFILE_EN__VS_STOP_CONDITION_MASK                                                     0x00000080L
34306 #define RLC_SPP_SHADER_PROFILE_EN__GS_STOP_CONDITION_MASK                                                     0x00000100L
34307 #define RLC_SPP_SHADER_PROFILE_EN__HS_STOP_CONDITION_MASK                                                     0x00000200L
34308 #define RLC_SPP_SHADER_PROFILE_EN__CSG_STOP_CONDITION_MASK                                                    0x00000400L
34309 #define RLC_SPP_SHADER_PROFILE_EN__CS_STOP_CONDITION_MASK                                                     0x00000800L
34310 #define RLC_SPP_SHADER_PROFILE_EN__PS_START_CONDITION_MASK                                                    0x00001000L
34311 #define RLC_SPP_SHADER_PROFILE_EN__CS_START_CONDITION_MASK                                                    0x00002000L
34312 #define RLC_SPP_SHADER_PROFILE_EN__FORCE_MISS_MASK                                                            0x00004000L
34313 #define RLC_SPP_SHADER_PROFILE_EN__FORCE_UNLOCKED_MASK                                                        0x00008000L
34314 #define RLC_SPP_SHADER_PROFILE_EN__ENABLE_PROF_INFO_LOCK_MASK                                                 0x00010000L
34315 //RLC_SPP_SSF_CAPTURE_EN
34316 #define RLC_SPP_SSF_CAPTURE_EN__PS_ENABLE__SHIFT                                                              0x0
34317 #define RLC_SPP_SSF_CAPTURE_EN__VS_ENABLE__SHIFT                                                              0x1
34318 #define RLC_SPP_SSF_CAPTURE_EN__GS_ENABLE__SHIFT                                                              0x2
34319 #define RLC_SPP_SSF_CAPTURE_EN__HS_ENABLE__SHIFT                                                              0x3
34320 #define RLC_SPP_SSF_CAPTURE_EN__CGS_ENABLE__SHIFT                                                             0x4
34321 #define RLC_SPP_SSF_CAPTURE_EN__CS_ENABLE__SHIFT                                                              0x5
34322 #define RLC_SPP_SSF_CAPTURE_EN__PS_ENABLE_MASK                                                                0x00000001L
34323 #define RLC_SPP_SSF_CAPTURE_EN__VS_ENABLE_MASK                                                                0x00000002L
34324 #define RLC_SPP_SSF_CAPTURE_EN__GS_ENABLE_MASK                                                                0x00000004L
34325 #define RLC_SPP_SSF_CAPTURE_EN__HS_ENABLE_MASK                                                                0x00000008L
34326 #define RLC_SPP_SSF_CAPTURE_EN__CGS_ENABLE_MASK                                                               0x00000010L
34327 #define RLC_SPP_SSF_CAPTURE_EN__CS_ENABLE_MASK                                                                0x00000020L
34328 //RLC_SPP_SSF_THRESHOLD_0
34329 #define RLC_SPP_SSF_THRESHOLD_0__PS_THRESHOLD__SHIFT                                                          0x0
34330 #define RLC_SPP_SSF_THRESHOLD_0__VS_THRESHOLD__SHIFT                                                          0x10
34331 #define RLC_SPP_SSF_THRESHOLD_0__PS_THRESHOLD_MASK                                                            0x0000FFFFL
34332 #define RLC_SPP_SSF_THRESHOLD_0__VS_THRESHOLD_MASK                                                            0xFFFF0000L
34333 //RLC_SPP_SSF_THRESHOLD_1
34334 #define RLC_SPP_SSF_THRESHOLD_1__GS_THRESHOLD__SHIFT                                                          0x0
34335 #define RLC_SPP_SSF_THRESHOLD_1__HS_THRESHOLD__SHIFT                                                          0x10
34336 #define RLC_SPP_SSF_THRESHOLD_1__GS_THRESHOLD_MASK                                                            0x0000FFFFL
34337 #define RLC_SPP_SSF_THRESHOLD_1__HS_THRESHOLD_MASK                                                            0xFFFF0000L
34338 //RLC_SPP_SSF_THRESHOLD_2
34339 #define RLC_SPP_SSF_THRESHOLD_2__CSG_THRESHOLD__SHIFT                                                         0x0
34340 #define RLC_SPP_SSF_THRESHOLD_2__CS_THRESHOLD__SHIFT                                                          0x10
34341 #define RLC_SPP_SSF_THRESHOLD_2__CSG_THRESHOLD_MASK                                                           0x0000FFFFL
34342 #define RLC_SPP_SSF_THRESHOLD_2__CS_THRESHOLD_MASK                                                            0xFFFF0000L
34343 //RLC_SPP_INFLIGHT_RD_ADDR
34344 #define RLC_SPP_INFLIGHT_RD_ADDR__ADDR__SHIFT                                                                 0x0
34345 #define RLC_SPP_INFLIGHT_RD_ADDR__ADDR_MASK                                                                   0x0000001FL
34346 //RLC_SPP_INFLIGHT_RD_DATA
34347 #define RLC_SPP_INFLIGHT_RD_DATA__DATA__SHIFT                                                                 0x0
34348 #define RLC_SPP_INFLIGHT_RD_DATA__DATA_MASK                                                                   0xFFFFFFFFL
34349 //RLC_SPP_PROF_INFO_1
34350 #define RLC_SPP_PROF_INFO_1__SH_ID__SHIFT                                                                     0x0
34351 #define RLC_SPP_PROF_INFO_1__SH_ID_MASK                                                                       0xFFFFFFFFL
34352 //RLC_SPP_PROF_INFO_2
34353 #define RLC_SPP_PROF_INFO_2__SH_TYPE__SHIFT                                                                   0x0
34354 #define RLC_SPP_PROF_INFO_2__CAM_HIT__SHIFT                                                                   0x4
34355 #define RLC_SPP_PROF_INFO_2__CAM_LOCK__SHIFT                                                                  0x5
34356 #define RLC_SPP_PROF_INFO_2__CAM_CONFLICT__SHIFT                                                              0x6
34357 #define RLC_SPP_PROF_INFO_2__SH_TYPE_MASK                                                                     0x0000000FL
34358 #define RLC_SPP_PROF_INFO_2__CAM_HIT_MASK                                                                     0x00000010L
34359 #define RLC_SPP_PROF_INFO_2__CAM_LOCK_MASK                                                                    0x00000020L
34360 #define RLC_SPP_PROF_INFO_2__CAM_CONFLICT_MASK                                                                0x00000040L
34361 //RLC_SPP_GLOBAL_SH_ID
34362 #define RLC_SPP_GLOBAL_SH_ID__SH_ID__SHIFT                                                                    0x0
34363 #define RLC_SPP_GLOBAL_SH_ID__SH_ID_MASK                                                                      0xFFFFFFFFL
34364 //RLC_SPP_GLOBAL_SH_ID_VALID
34365 #define RLC_SPP_GLOBAL_SH_ID_VALID__VALID__SHIFT                                                              0x0
34366 #define RLC_SPP_GLOBAL_SH_ID_VALID__VALID_MASK                                                                0x00000001L
34367 //RLC_SPP_STATUS
34368 #define RLC_SPP_STATUS__RESERVED_0__SHIFT                                                                     0x0
34369 #define RLC_SPP_STATUS__SSF_BUSY__SHIFT                                                                       0x1
34370 #define RLC_SPP_STATUS__EVENT_ARB_BUSY__SHIFT                                                                 0x2
34371 #define RLC_SPP_STATUS__SPP_BUSY__SHIFT                                                                       0x1f
34372 #define RLC_SPP_STATUS__RESERVED_0_MASK                                                                       0x00000001L
34373 #define RLC_SPP_STATUS__SSF_BUSY_MASK                                                                         0x00000002L
34374 #define RLC_SPP_STATUS__EVENT_ARB_BUSY_MASK                                                                   0x00000004L
34375 #define RLC_SPP_STATUS__SPP_BUSY_MASK                                                                         0x80000000L
34376 //RLC_SPP_PVT_STAT_0
34377 #define RLC_SPP_PVT_STAT_0__LEVEL_0_COUNTER__SHIFT                                                            0x0
34378 #define RLC_SPP_PVT_STAT_0__LEVEL_1_COUNTER__SHIFT                                                            0x6
34379 #define RLC_SPP_PVT_STAT_0__LEVEL_2_COUNTER__SHIFT                                                            0xc
34380 #define RLC_SPP_PVT_STAT_0__LEVEL_3_COUNTER__SHIFT                                                            0x12
34381 #define RLC_SPP_PVT_STAT_0__LEVEL_4_COUNTER__SHIFT                                                            0x18
34382 #define RLC_SPP_PVT_STAT_0__LEVEL_0_COUNTER_MASK                                                              0x0000003FL
34383 #define RLC_SPP_PVT_STAT_0__LEVEL_1_COUNTER_MASK                                                              0x00000FC0L
34384 #define RLC_SPP_PVT_STAT_0__LEVEL_2_COUNTER_MASK                                                              0x0003F000L
34385 #define RLC_SPP_PVT_STAT_0__LEVEL_3_COUNTER_MASK                                                              0x00FC0000L
34386 #define RLC_SPP_PVT_STAT_0__LEVEL_4_COUNTER_MASK                                                              0x7F000000L
34387 //RLC_SPP_PVT_STAT_1
34388 #define RLC_SPP_PVT_STAT_1__LEVEL_5_COUNTER__SHIFT                                                            0x0
34389 #define RLC_SPP_PVT_STAT_1__LEVEL_6_COUNTER__SHIFT                                                            0x6
34390 #define RLC_SPP_PVT_STAT_1__LEVEL_7_COUNTER__SHIFT                                                            0xc
34391 #define RLC_SPP_PVT_STAT_1__LEVEL_8_COUNTER__SHIFT                                                            0x12
34392 #define RLC_SPP_PVT_STAT_1__LEVEL_9_COUNTER__SHIFT                                                            0x18
34393 #define RLC_SPP_PVT_STAT_1__LEVEL_5_COUNTER_MASK                                                              0x0000003FL
34394 #define RLC_SPP_PVT_STAT_1__LEVEL_6_COUNTER_MASK                                                              0x00000FC0L
34395 #define RLC_SPP_PVT_STAT_1__LEVEL_7_COUNTER_MASK                                                              0x0003F000L
34396 #define RLC_SPP_PVT_STAT_1__LEVEL_8_COUNTER_MASK                                                              0x00FC0000L
34397 #define RLC_SPP_PVT_STAT_1__LEVEL_9_COUNTER_MASK                                                              0x7F000000L
34398 //RLC_SPP_PVT_STAT_2
34399 #define RLC_SPP_PVT_STAT_2__LEVEL_10_COUNTER__SHIFT                                                           0x0
34400 #define RLC_SPP_PVT_STAT_2__LEVEL_11_COUNTER__SHIFT                                                           0x6
34401 #define RLC_SPP_PVT_STAT_2__LEVEL_12_COUNTER__SHIFT                                                           0xc
34402 #define RLC_SPP_PVT_STAT_2__LEVEL_13_COUNTER__SHIFT                                                           0x12
34403 #define RLC_SPP_PVT_STAT_2__LEVEL_14_COUNTER__SHIFT                                                           0x18
34404 #define RLC_SPP_PVT_STAT_2__LEVEL_10_COUNTER_MASK                                                             0x0000003FL
34405 #define RLC_SPP_PVT_STAT_2__LEVEL_11_COUNTER_MASK                                                             0x00000FC0L
34406 #define RLC_SPP_PVT_STAT_2__LEVEL_12_COUNTER_MASK                                                             0x0003F000L
34407 #define RLC_SPP_PVT_STAT_2__LEVEL_13_COUNTER_MASK                                                             0x00FC0000L
34408 #define RLC_SPP_PVT_STAT_2__LEVEL_14_COUNTER_MASK                                                             0x7F000000L
34409 //RLC_SPP_PVT_STAT_3
34410 #define RLC_SPP_PVT_STAT_3__LEVEL_15_COUNTER__SHIFT                                                           0x0
34411 #define RLC_SPP_PVT_STAT_3__LEVEL_15_COUNTER_MASK                                                             0x0000003FL
34412 //RLC_SPP_PVT_LEVEL_MAX
34413 #define RLC_SPP_PVT_LEVEL_MAX__LEVEL__SHIFT                                                                   0x0
34414 #define RLC_SPP_PVT_LEVEL_MAX__LEVEL_MASK                                                                     0x0000000FL
34415 //RLC_SPP_STALL_STATE_UPDATE
34416 #define RLC_SPP_STALL_STATE_UPDATE__STALL__SHIFT                                                              0x0
34417 #define RLC_SPP_STALL_STATE_UPDATE__ENABLE__SHIFT                                                             0x1
34418 #define RLC_SPP_STALL_STATE_UPDATE__STALL_MASK                                                                0x00000001L
34419 #define RLC_SPP_STALL_STATE_UPDATE__ENABLE_MASK                                                               0x00000002L
34420 //RLC_SPP_PBB_INFO
34421 #define RLC_SPP_PBB_INFO__PIPE0_OVERRIDE__SHIFT                                                               0x0
34422 #define RLC_SPP_PBB_INFO__PIPE0_OVERRIDE_VALID__SHIFT                                                         0x1
34423 #define RLC_SPP_PBB_INFO__PIPE1_OVERRIDE__SHIFT                                                               0x2
34424 #define RLC_SPP_PBB_INFO__PIPE1_OVERRIDE_VALID__SHIFT                                                         0x3
34425 #define RLC_SPP_PBB_INFO__PIPE0_OVERRIDE_MASK                                                                 0x00000001L
34426 #define RLC_SPP_PBB_INFO__PIPE0_OVERRIDE_VALID_MASK                                                           0x00000002L
34427 #define RLC_SPP_PBB_INFO__PIPE1_OVERRIDE_MASK                                                                 0x00000004L
34428 #define RLC_SPP_PBB_INFO__PIPE1_OVERRIDE_VALID_MASK                                                           0x00000008L
34429 //RLC_SPP_RESET
34430 #define RLC_SPP_RESET__SSF_RESET__SHIFT                                                                       0x0
34431 #define RLC_SPP_RESET__EVENT_ARB_RESET__SHIFT                                                                 0x1
34432 #define RLC_SPP_RESET__CAM_RESET__SHIFT                                                                       0x2
34433 #define RLC_SPP_RESET__PVT_RESET__SHIFT                                                                       0x3
34434 #define RLC_SPP_RESET__SSF_RESET_MASK                                                                         0x00000001L
34435 #define RLC_SPP_RESET__EVENT_ARB_RESET_MASK                                                                   0x00000002L
34436 #define RLC_SPP_RESET__CAM_RESET_MASK                                                                         0x00000004L
34437 #define RLC_SPP_RESET__PVT_RESET_MASK                                                                         0x00000008L
34438 //RLC_SPM_SAMPLE_CNT
34439 #define RLC_SPM_SAMPLE_CNT__COUNT__SHIFT                                                                      0x0
34440 #define RLC_SPM_SAMPLE_CNT__COUNT_MASK                                                                        0xFFFFFFFFL
34441 //RLC_PCC_STRETCH_HYSTERESIS_CNTL
34442 #define RLC_PCC_STRETCH_HYSTERESIS_CNTL__MAX_HYSTERESIS__SHIFT                                                0x0
34443 #define RLC_PCC_STRETCH_HYSTERESIS_CNTL__HYSTERESIS_CNT__SHIFT                                                0x8
34444 #define RLC_PCC_STRETCH_HYSTERESIS_CNTL__MAX_HYSTERESIS_MASK                                                  0x000000FFL
34445 #define RLC_PCC_STRETCH_HYSTERESIS_CNTL__HYSTERESIS_CNT_MASK                                                  0x0000FF00L
34446 //RLC_GPU_CLOCK_COUNT_SPM_LSB
34447 #define RLC_GPU_CLOCK_COUNT_SPM_LSB__GPU_CLOCKS_LSB__SHIFT                                                    0x0
34448 #define RLC_GPU_CLOCK_COUNT_SPM_LSB__GPU_CLOCKS_LSB_MASK                                                      0xFFFFFFFFL
34449 //RLC_GPU_CLOCK_COUNT_SPM_MSB
34450 #define RLC_GPU_CLOCK_COUNT_SPM_MSB__GPU_CLOCKS_MSB__SHIFT                                                    0x0
34451 #define RLC_GPU_CLOCK_COUNT_SPM_MSB__GPU_CLOCKS_MSB_MASK                                                      0xFFFFFFFFL
34452 //RLC_SPM_THREAD_TRACE_CTRL
34453 #define RLC_SPM_THREAD_TRACE_CTRL__THREAD_TRACE_INT_EN__SHIFT                                                 0x0
34454 #define RLC_SPM_THREAD_TRACE_CTRL__THREAD_TRACE_INT_EN_MASK                                                   0x00000001L
34455 //RLC_LB_CNTR_2
34456 #define RLC_LB_CNTR_2__RLC_LOAD_BALANCE_CNTR__SHIFT                                                           0x0
34457 #define RLC_LB_CNTR_2__RLC_LOAD_BALANCE_CNTR_MASK                                                             0xFFFFFFFFL
34458 //RLC_CPAXI_DOORBELL_MON_CTRL
34459 #define RLC_CPAXI_DOORBELL_MON_CTRL__EN__SHIFT                                                                0x0
34460 #define RLC_CPAXI_DOORBELL_MON_CTRL__ID__SHIFT                                                                0x1
34461 #define RLC_CPAXI_DOORBELL_MON_CTRL__EN_MASK                                                                  0x00000001L
34462 #define RLC_CPAXI_DOORBELL_MON_CTRL__ID_MASK                                                                  0x0000003EL
34463 //RLC_CPAXI_DOORBELL_MON_STAT
34464 #define RLC_CPAXI_DOORBELL_MON_STAT__ID_MATCH__SHIFT                                                          0x0
34465 #define RLC_CPAXI_DOORBELL_MON_STAT__MATCH_CLEAR__SHIFT                                                       0x1
34466 #define RLC_CPAXI_DOORBELL_MON_STAT__ADDR__SHIFT                                                              0x2
34467 #define RLC_CPAXI_DOORBELL_MON_STAT__ID_MATCH_MASK                                                            0x00000001L
34468 #define RLC_CPAXI_DOORBELL_MON_STAT__MATCH_CLEAR_MASK                                                         0x00000002L
34469 #define RLC_CPAXI_DOORBELL_MON_STAT__ADDR_MASK                                                                0x0FFFFFFCL
34470 //RLC_CPAXI_DOORBELL_MON_DATA_LSB
34471 #define RLC_CPAXI_DOORBELL_MON_DATA_LSB__DATA__SHIFT                                                          0x0
34472 #define RLC_CPAXI_DOORBELL_MON_DATA_LSB__DATA_MASK                                                            0xFFFFFFFFL
34473 //RLC_CPAXI_DOORBELL_MON_DATA_MSB
34474 #define RLC_CPAXI_DOORBELL_MON_DATA_MSB__DATA__SHIFT                                                          0x0
34475 #define RLC_CPAXI_DOORBELL_MON_DATA_MSB__DATA_MASK                                                            0xFFFFFFFFL
34476 
34477 
34478 // addressBlock: gc_rlcrdec
34479 //RLC_SPP_CAM_ADDR
34480 #define RLC_SPP_CAM_ADDR__ADDR__SHIFT                                                                         0x0
34481 #define RLC_SPP_CAM_ADDR__ADDR_MASK                                                                           0x000000FFL
34482 //RLC_SPP_CAM_DATA
34483 #define RLC_SPP_CAM_DATA__DATA__SHIFT                                                                         0x0
34484 #define RLC_SPP_CAM_DATA__TAG__SHIFT                                                                          0x8
34485 #define RLC_SPP_CAM_DATA__DATA_MASK                                                                           0x000000FFL
34486 #define RLC_SPP_CAM_DATA__TAG_MASK                                                                            0xFFFFFF00L
34487 //RLC_SPP_CAM_EXT_ADDR
34488 #define RLC_SPP_CAM_EXT_ADDR__ADDR__SHIFT                                                                     0x0
34489 #define RLC_SPP_CAM_EXT_ADDR__ADDR_MASK                                                                       0x000000FFL
34490 //RLC_SPP_CAM_EXT_DATA
34491 #define RLC_SPP_CAM_EXT_DATA__VALID__SHIFT                                                                    0x0
34492 #define RLC_SPP_CAM_EXT_DATA__LOCK__SHIFT                                                                     0x1
34493 #define RLC_SPP_CAM_EXT_DATA__VALID_MASK                                                                      0x00000001L
34494 #define RLC_SPP_CAM_EXT_DATA__LOCK_MASK                                                                       0x00000002L
34495 //RLC_PACE_SCRATCH_ADDR
34496 #define RLC_PACE_SCRATCH_ADDR__ADDR__SHIFT                                                                    0x0
34497 #define RLC_PACE_SCRATCH_ADDR__ADDR_MASK                                                                      0xFFFFFFFFL
34498 //RLC_PACE_SCRATCH_DATA
34499 #define RLC_PACE_SCRATCH_DATA__DATA__SHIFT                                                                    0x0
34500 #define RLC_PACE_SCRATCH_DATA__DATA_MASK                                                                      0xFFFFFFFFL
34501 
34502 
34503 // addressBlock: gc_rlcsdec
34504 //RLC_RLCS_DEC_START
34505 //RLC_RLCS_DEC_DUMP_ADDR
34506 //RLC_RLCS_EXCEPTION_REG_1
34507 #define RLC_RLCS_EXCEPTION_REG_1__ADDR__SHIFT                                                                 0x0
34508 #define RLC_RLCS_EXCEPTION_REG_1__RESERVED__SHIFT                                                             0x12
34509 #define RLC_RLCS_EXCEPTION_REG_1__ADDR_MASK                                                                   0x0003FFFFL
34510 #define RLC_RLCS_EXCEPTION_REG_1__RESERVED_MASK                                                               0xFFFC0000L
34511 //RLC_RLCS_EXCEPTION_REG_2
34512 #define RLC_RLCS_EXCEPTION_REG_2__ADDR__SHIFT                                                                 0x0
34513 #define RLC_RLCS_EXCEPTION_REG_2__RESERVED__SHIFT                                                             0x12
34514 #define RLC_RLCS_EXCEPTION_REG_2__ADDR_MASK                                                                   0x0003FFFFL
34515 #define RLC_RLCS_EXCEPTION_REG_2__RESERVED_MASK                                                               0xFFFC0000L
34516 //RLC_RLCS_EXCEPTION_REG_3
34517 #define RLC_RLCS_EXCEPTION_REG_3__ADDR__SHIFT                                                                 0x0
34518 #define RLC_RLCS_EXCEPTION_REG_3__RESERVED__SHIFT                                                             0x12
34519 #define RLC_RLCS_EXCEPTION_REG_3__ADDR_MASK                                                                   0x0003FFFFL
34520 #define RLC_RLCS_EXCEPTION_REG_3__RESERVED_MASK                                                               0xFFFC0000L
34521 //RLC_RLCS_EXCEPTION_REG_4
34522 #define RLC_RLCS_EXCEPTION_REG_4__ADDR__SHIFT                                                                 0x0
34523 #define RLC_RLCS_EXCEPTION_REG_4__RESERVED__SHIFT                                                             0x12
34524 #define RLC_RLCS_EXCEPTION_REG_4__ADDR_MASK                                                                   0x0003FFFFL
34525 #define RLC_RLCS_EXCEPTION_REG_4__RESERVED_MASK                                                               0xFFFC0000L
34526 //RLC_RLCS_GENERAL_6
34527 #define RLC_RLCS_GENERAL_6__DATA__SHIFT                                                                       0x0
34528 #define RLC_RLCS_GENERAL_6__DATA_MASK                                                                         0xFFFFFFFFL
34529 //RLC_RLCS_GENERAL_7
34530 #define RLC_RLCS_GENERAL_7__DATA__SHIFT                                                                       0x0
34531 #define RLC_RLCS_GENERAL_7__DATA_MASK                                                                         0xFFFFFFFFL
34532 //RLC_RLCS_CGCG_REQUEST
34533 #define RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST__SHIFT                                                            0x0
34534 #define RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST_3D__SHIFT                                                         0x1
34535 #define RLC_RLCS_CGCG_REQUEST__RESERVED__SHIFT                                                                0x2
34536 #define RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST_MASK                                                              0x00000001L
34537 #define RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST_3D_MASK                                                           0x00000002L
34538 #define RLC_RLCS_CGCG_REQUEST__RESERVED_MASK                                                                  0xFFFFFFFCL
34539 //RLC_RLCS_CGCG_STATUS
34540 #define RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS__SHIFT                                                         0x0
34541 #define RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS__SHIFT                                                           0x2
34542 #define RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS_3D__SHIFT                                                      0x3
34543 #define RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS_3D__SHIFT                                                        0x5
34544 #define RLC_RLCS_CGCG_STATUS__RESERVED__SHIFT                                                                 0x6
34545 #define RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS_MASK                                                           0x00000003L
34546 #define RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS_MASK                                                             0x00000004L
34547 #define RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS_3D_MASK                                                        0x00000018L
34548 #define RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS_3D_MASK                                                          0x00000020L
34549 #define RLC_RLCS_CGCG_STATUS__RESERVED_MASK                                                                   0xFFFFFFC0L
34550 //RLC_RLCS_SMU_GFXCLK_STATUS
34551 #define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXCLK_DONETOG__SHIFT                                                 0x0
34552 #define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXMUX_CUR_VALUE__SHIFT                                               0x1
34553 #define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXCLK_STRETCH_PCC__SHIFT                                             0x2
34554 #define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXCLK_PCC_CTRL__SHIFT                                                0x3
34555 #define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXCLK_DONETOG_MASK                                                   0x00000001L
34556 #define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXMUX_CUR_VALUE_MASK                                                 0x00000002L
34557 #define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXCLK_STRETCH_PCC_MASK                                               0x00000004L
34558 #define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXCLK_PCC_CTRL_MASK                                                  0x00000008L
34559 //RLC_RLCS_SMU_GFXCLK_CONTROL
34560 #define RLC_RLCS_SMU_GFXCLK_CONTROL__SMU_GFXCLK_CHGTOG__SHIFT                                                 0x0
34561 #define RLC_RLCS_SMU_GFXCLK_CONTROL__SMU_GFXCLK_DIVIDER__SHIFT                                                0x1
34562 #define RLC_RLCS_SMU_GFXCLK_CONTROL__SMU_GFXMUX_SEL__SHIFT                                                    0x8
34563 #define RLC_RLCS_SMU_GFXCLK_CONTROL__RESERVED__SHIFT                                                          0x9
34564 #define RLC_RLCS_SMU_GFXCLK_CONTROL__SMU_GFXCLK_CHGTOG_MASK                                                   0x00000001L
34565 #define RLC_RLCS_SMU_GFXCLK_CONTROL__SMU_GFXCLK_DIVIDER_MASK                                                  0x000000FEL
34566 #define RLC_RLCS_SMU_GFXCLK_CONTROL__SMU_GFXMUX_SEL_MASK                                                      0x00000100L
34567 #define RLC_RLCS_SMU_GFXCLK_CONTROL__RESERVED_MASK                                                            0xFFFFFE00L
34568 //RLC_RLCS_SOC_DS_CNTL
34569 #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_ALLOW__SHIFT                                                         0x0
34570 #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK__SHIFT                                                 0x1
34571 #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK__SHIFT                                                  0x2
34572 #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_0_BUSY_MASK__SHIFT                                              0x3
34573 #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_1_BUSY_MASK__SHIFT                                              0x4
34574 #define RLC_RLCS_SOC_DS_CNTL__RESERVED_5__SHIFT                                                               0x5
34575 #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_GFX_PWR_STALLED_MASK__SHIFT                                          0x6
34576 #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_NON3D_PWR_STALLED_MASK__SHIFT                                        0x7
34577 #define RLC_RLCS_SOC_DS_CNTL__RESERVED__SHIFT                                                                 0x8
34578 #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_ALLOW_MASK                                                           0x00000001L
34579 #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK_MASK                                                   0x00000002L
34580 #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK_MASK                                                    0x00000004L
34581 #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_0_BUSY_MASK_MASK                                                0x00000008L
34582 #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_1_BUSY_MASK_MASK                                                0x00000010L
34583 #define RLC_RLCS_SOC_DS_CNTL__RESERVED_5_MASK                                                                 0x00000020L
34584 #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_GFX_PWR_STALLED_MASK_MASK                                            0x00000040L
34585 #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_NON3D_PWR_STALLED_MASK_MASK                                          0x00000080L
34586 #define RLC_RLCS_SOC_DS_CNTL__RESERVED_MASK                                                                   0xFFFFFF00L
34587 //RLC_RLCS_GFX_DS_CNTL
34588 #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_ALLOW__SHIFT                                                         0x0
34589 #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK__SHIFT                                                 0x1
34590 #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK__SHIFT                                                  0x2
34591 #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_0_BUSY_MASK__SHIFT                                              0x3
34592 #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_1_BUSY_MASK__SHIFT                                              0x4
34593 #define RLC_RLCS_GFX_DS_CNTL__RESERVED_5__SHIFT                                                               0x5
34594 #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_GFX_PWR_STALLED_MASK__SHIFT                                          0x6
34595 #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_NON3D_PWR_STALLED_MASK__SHIFT                                        0x7
34596 #define RLC_RLCS_GFX_DS_CNTL__RESERVED__SHIFT                                                                 0x8
34597 #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_ALLOW_MASK                                                           0x00000001L
34598 #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK_MASK                                                   0x00000002L
34599 #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK_MASK                                                    0x00000004L
34600 #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_0_BUSY_MASK_MASK                                                0x00000008L
34601 #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_1_BUSY_MASK_MASK                                                0x00000010L
34602 #define RLC_RLCS_GFX_DS_CNTL__RESERVED_5_MASK                                                                 0x00000020L
34603 #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_GFX_PWR_STALLED_MASK_MASK                                            0x00000040L
34604 #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_NON3D_PWR_STALLED_MASK_MASK                                          0x00000080L
34605 #define RLC_RLCS_GFX_DS_CNTL__RESERVED_MASK                                                                   0xFFFFFF00L
34606 //RLC_GPM_STAT
34607 #define RLC_GPM_STAT__RLC_BUSY__SHIFT                                                                         0x0
34608 #define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT                                                                 0x1
34609 #define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT                                                                 0x2
34610 #define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT                                                                    0x3
34611 #define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT                                                        0x4
34612 #define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT                                                        0x5
34613 #define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT                                                        0x6
34614 #define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT                                                         0x7
34615 #define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT                                                         0x8
34616 #define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT                                                                 0x9
34617 #define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT                                                              0xa
34618 #define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT                                                0xb
34619 #define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT                                                  0xc
34620 #define RLC_GPM_STAT__STATIC_WGP_POWERING_UP__SHIFT                                                           0xd
34621 #define RLC_GPM_STAT__STATIC_WGP_POWERING_DOWN__SHIFT                                                         0xe
34622 #define RLC_GPM_STAT__DYN_WGP_POWERING_UP__SHIFT                                                              0xf
34623 #define RLC_GPM_STAT__DYN_WGP_POWERING_DOWN__SHIFT                                                            0x10
34624 #define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT                                                              0x11
34625 #define RLC_GPM_STAT__CMP_power_status__SHIFT                                                                 0x12
34626 #define RLC_GPM_STAT__GFX_LS_STATUS_3D__SHIFT                                                                 0x13
34627 #define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D__SHIFT                                                              0x14
34628 #define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT                                                             0x15
34629 #define RLC_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT                                                                0x16
34630 #define RLC_GPM_STAT__FGCG_OVERRIDE_STATUS__SHIFT                                                             0x17
34631 #define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT                                                                  0x18
34632 #define RLC_GPM_STAT__RLC_BUSY_MASK                                                                           0x00000001L
34633 #define RLC_GPM_STAT__GFX_POWER_STATUS_MASK                                                                   0x00000002L
34634 #define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK                                                                   0x00000004L
34635 #define RLC_GPM_STAT__GFX_LS_STATUS_MASK                                                                      0x00000008L
34636 #define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK                                                          0x00000010L
34637 #define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK                                                          0x00000020L
34638 #define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK                                                          0x00000040L
34639 #define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK                                                           0x00000080L
34640 #define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK                                                           0x00000100L
34641 #define RLC_GPM_STAT__SAVING_REGISTERS_MASK                                                                   0x00000200L
34642 #define RLC_GPM_STAT__RESTORING_REGISTERS_MASK                                                                0x00000400L
34643 #define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK                                                  0x00000800L
34644 #define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK                                                    0x00001000L
34645 #define RLC_GPM_STAT__STATIC_WGP_POWERING_UP_MASK                                                             0x00002000L
34646 #define RLC_GPM_STAT__STATIC_WGP_POWERING_DOWN_MASK                                                           0x00004000L
34647 #define RLC_GPM_STAT__DYN_WGP_POWERING_UP_MASK                                                                0x00008000L
34648 #define RLC_GPM_STAT__DYN_WGP_POWERING_DOWN_MASK                                                              0x00010000L
34649 #define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK                                                                0x00020000L
34650 #define RLC_GPM_STAT__CMP_power_status_MASK                                                                   0x00040000L
34651 #define RLC_GPM_STAT__GFX_LS_STATUS_3D_MASK                                                                   0x00080000L
34652 #define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D_MASK                                                                0x00100000L
34653 #define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK                                                               0x00200000L
34654 #define RLC_GPM_STAT__RLC_EXEC_ROM_CODE_MASK                                                                  0x00400000L
34655 #define RLC_GPM_STAT__FGCG_OVERRIDE_STATUS_MASK                                                               0x00800000L
34656 #define RLC_GPM_STAT__PG_ERROR_STATUS_MASK                                                                    0xFF000000L
34657 //RLC_RLCS_GPM_STAT
34658 #define RLC_RLCS_GPM_STAT__RLC_BUSY__SHIFT                                                                    0x0
34659 #define RLC_RLCS_GPM_STAT__GFX_POWER_STATUS__SHIFT                                                            0x1
34660 #define RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS__SHIFT                                                            0x2
34661 #define RLC_RLCS_GPM_STAT__GFX_LS_STATUS__SHIFT                                                               0x3
34662 #define RLC_RLCS_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT                                                   0x4
34663 #define RLC_RLCS_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT                                                   0x5
34664 #define RLC_RLCS_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT                                                   0x6
34665 #define RLC_RLCS_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT                                                    0x7
34666 #define RLC_RLCS_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT                                                    0x8
34667 #define RLC_RLCS_GPM_STAT__SAVING_REGISTERS__SHIFT                                                            0x9
34668 #define RLC_RLCS_GPM_STAT__RESTORING_REGISTERS__SHIFT                                                         0xa
34669 #define RLC_RLCS_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT                                           0xb
34670 #define RLC_RLCS_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT                                             0xc
34671 #define RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_UP__SHIFT                                                      0xd
34672 #define RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_DOWN__SHIFT                                                    0xe
34673 #define RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_UP__SHIFT                                                         0xf
34674 #define RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_DOWN__SHIFT                                                       0x10
34675 #define RLC_RLCS_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT                                                         0x11
34676 #define RLC_RLCS_GPM_STAT__CMP_POWER_STATUS__SHIFT                                                            0x12
34677 #define RLC_RLCS_GPM_STAT__GFX_LS_STATUS_3D__SHIFT                                                            0x13
34678 #define RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS_3D__SHIFT                                                         0x14
34679 #define RLC_RLCS_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT                                                        0x15
34680 #define RLC_RLCS_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT                                                           0x16
34681 #define RLC_RLCS_GPM_STAT__FGCG_OVERRIDE_STATUS__SHIFT                                                        0x17
34682 #define RLC_RLCS_GPM_STAT__PG_ERROR_STATUS__SHIFT                                                             0x18
34683 #define RLC_RLCS_GPM_STAT__RLC_BUSY_MASK                                                                      0x00000001L
34684 #define RLC_RLCS_GPM_STAT__GFX_POWER_STATUS_MASK                                                              0x00000002L
34685 #define RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS_MASK                                                              0x00000004L
34686 #define RLC_RLCS_GPM_STAT__GFX_LS_STATUS_MASK                                                                 0x00000008L
34687 #define RLC_RLCS_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK                                                     0x00000010L
34688 #define RLC_RLCS_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK                                                     0x00000020L
34689 #define RLC_RLCS_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK                                                     0x00000040L
34690 #define RLC_RLCS_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK                                                      0x00000080L
34691 #define RLC_RLCS_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK                                                      0x00000100L
34692 #define RLC_RLCS_GPM_STAT__SAVING_REGISTERS_MASK                                                              0x00000200L
34693 #define RLC_RLCS_GPM_STAT__RESTORING_REGISTERS_MASK                                                           0x00000400L
34694 #define RLC_RLCS_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK                                             0x00000800L
34695 #define RLC_RLCS_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK                                               0x00001000L
34696 #define RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_UP_MASK                                                        0x00002000L
34697 #define RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_DOWN_MASK                                                      0x00004000L
34698 #define RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_UP_MASK                                                           0x00008000L
34699 #define RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_DOWN_MASK                                                         0x00010000L
34700 #define RLC_RLCS_GPM_STAT__ABORTED_PD_SEQUENCE_MASK                                                           0x00020000L
34701 #define RLC_RLCS_GPM_STAT__CMP_POWER_STATUS_MASK                                                              0x00040000L
34702 #define RLC_RLCS_GPM_STAT__GFX_LS_STATUS_3D_MASK                                                              0x00080000L
34703 #define RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS_3D_MASK                                                           0x00100000L
34704 #define RLC_RLCS_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK                                                          0x00200000L
34705 #define RLC_RLCS_GPM_STAT__RLC_EXEC_ROM_CODE_MASK                                                             0x00400000L
34706 #define RLC_RLCS_GPM_STAT__FGCG_OVERRIDE_STATUS_MASK                                                          0x00800000L
34707 #define RLC_RLCS_GPM_STAT__PG_ERROR_STATUS_MASK                                                               0xFF000000L
34708 //RLC_RLCS_ABORTED_PD_SEQUENCE
34709 #define RLC_RLCS_ABORTED_PD_SEQUENCE__APS__SHIFT                                                              0x0
34710 #define RLC_RLCS_ABORTED_PD_SEQUENCE__RESERVED__SHIFT                                                         0x10
34711 #define RLC_RLCS_ABORTED_PD_SEQUENCE__APS_MASK                                                                0x0000FFFFL
34712 #define RLC_RLCS_ABORTED_PD_SEQUENCE__RESERVED_MASK                                                           0xFFFF0000L
34713 //RLC_RLCS_DIDT_FORCE_STALL
34714 #define RLC_RLCS_DIDT_FORCE_STALL__DFS__SHIFT                                                                 0x0
34715 #define RLC_RLCS_DIDT_FORCE_STALL__RESERVED__SHIFT                                                            0x3
34716 #define RLC_RLCS_DIDT_FORCE_STALL__DFS_MASK                                                                   0x00000007L
34717 #define RLC_RLCS_DIDT_FORCE_STALL__RESERVED_MASK                                                              0xFFFFFFF8L
34718 //RLC_RLCS_IOV_CMD_STATUS
34719 #define RLC_RLCS_IOV_CMD_STATUS__DATA__SHIFT                                                                  0x0
34720 #define RLC_RLCS_IOV_CMD_STATUS__DATA_MASK                                                                    0xFFFFFFFFL
34721 //RLC_RLCS_IOV_CNTX_LOC_SIZE
34722 #define RLC_RLCS_IOV_CNTX_LOC_SIZE__DATA__SHIFT                                                               0x0
34723 #define RLC_RLCS_IOV_CNTX_LOC_SIZE__RESERVED__SHIFT                                                           0x8
34724 #define RLC_RLCS_IOV_CNTX_LOC_SIZE__DATA_MASK                                                                 0x000000FFL
34725 #define RLC_RLCS_IOV_CNTX_LOC_SIZE__RESERVED_MASK                                                             0xFFFFFF00L
34726 //RLC_RLCS_IOV_SCH_BLOCK
34727 #define RLC_RLCS_IOV_SCH_BLOCK__DATA__SHIFT                                                                   0x0
34728 #define RLC_RLCS_IOV_SCH_BLOCK__DATA_MASK                                                                     0xFFFFFFFFL
34729 //RLC_RLCS_IOV_VM_BUSY_STATUS
34730 #define RLC_RLCS_IOV_VM_BUSY_STATUS__DATA__SHIFT                                                              0x0
34731 #define RLC_RLCS_IOV_VM_BUSY_STATUS__DATA_MASK                                                                0xFFFFFFFFL
34732 //RLC_RLCS_GPM_STAT_2
34733 #define RLC_RLCS_GPM_STAT_2__TC_TRANS_ERROR__SHIFT                                                            0x0
34734 #define RLC_RLCS_GPM_STAT_2__RLC_PWR_NON3D_STALLED__SHIFT                                                     0x1
34735 #define RLC_RLCS_GPM_STAT_2__GFX_PWR_STALLED_STATUS__SHIFT                                                    0x2
34736 #define RLC_RLCS_GPM_STAT_2__GFX_ULV_STATUS__SHIFT                                                            0x3
34737 #define RLC_RLCS_GPM_STAT_2__RESERVED__SHIFT                                                                  0x4
34738 #define RLC_RLCS_GPM_STAT_2__TC_TRANS_ERROR_MASK                                                              0x00000001L
34739 #define RLC_RLCS_GPM_STAT_2__RLC_PWR_NON3D_STALLED_MASK                                                       0x00000002L
34740 #define RLC_RLCS_GPM_STAT_2__GFX_PWR_STALLED_STATUS_MASK                                                      0x00000004L
34741 #define RLC_RLCS_GPM_STAT_2__GFX_ULV_STATUS_MASK                                                              0x00000008L
34742 #define RLC_RLCS_GPM_STAT_2__RESERVED_MASK                                                                    0xFFFFFFF0L
34743 //RLC_RLCS_GRBM_SOFT_RESET
34744 #define RLC_RLCS_GRBM_SOFT_RESET__RESET__SHIFT                                                                0x0
34745 #define RLC_RLCS_GRBM_SOFT_RESET__RESERVED__SHIFT                                                             0x1
34746 #define RLC_RLCS_GRBM_SOFT_RESET__RESET_MASK                                                                  0x00000001L
34747 #define RLC_RLCS_GRBM_SOFT_RESET__RESERVED_MASK                                                               0xFFFFFFFEL
34748 //RLC_RLCS_PG_CHANGE_STATUS
34749 #define RLC_RLCS_PG_CHANGE_STATUS__PG_CNTL_CHANGED__SHIFT                                                     0x0
34750 #define RLC_RLCS_PG_CHANGE_STATUS__PG_REG_CHANGED__SHIFT                                                      0x1
34751 #define RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_STATUS_CHANGED__SHIFT                                               0x2
34752 #define RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_REQ_CHANGED__SHIFT                                                  0x3
34753 #define RLC_RLCS_PG_CHANGE_STATUS__RESERVED__SHIFT                                                            0x4
34754 #define RLC_RLCS_PG_CHANGE_STATUS__PG_CNTL_CHANGED_MASK                                                       0x00000001L
34755 #define RLC_RLCS_PG_CHANGE_STATUS__PG_REG_CHANGED_MASK                                                        0x00000002L
34756 #define RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_STATUS_CHANGED_MASK                                                 0x00000004L
34757 #define RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_REQ_CHANGED_MASK                                                    0x00000008L
34758 #define RLC_RLCS_PG_CHANGE_STATUS__RESERVED_MASK                                                              0xFFFFFFF0L
34759 //RLC_RLCS_PG_CHANGE_READ
34760 #define RLC_RLCS_PG_CHANGE_READ__PG_CNTL_CHANGED__SHIFT                                                       0x0
34761 #define RLC_RLCS_PG_CHANGE_READ__PG_REG_CHANGED__SHIFT                                                        0x1
34762 #define RLC_RLCS_PG_CHANGE_READ__DYN_PG_STATUS_CHANGED__SHIFT                                                 0x2
34763 #define RLC_RLCS_PG_CHANGE_READ__DYN_PG_REQ_CHANGED__SHIFT                                                    0x3
34764 #define RLC_RLCS_PG_CHANGE_READ__RESERVED__SHIFT                                                              0x4
34765 #define RLC_RLCS_PG_CHANGE_READ__PG_CNTL_CHANGED_MASK                                                         0x00000001L
34766 #define RLC_RLCS_PG_CHANGE_READ__PG_REG_CHANGED_MASK                                                          0x00000002L
34767 #define RLC_RLCS_PG_CHANGE_READ__DYN_PG_STATUS_CHANGED_MASK                                                   0x00000004L
34768 #define RLC_RLCS_PG_CHANGE_READ__DYN_PG_REQ_CHANGED_MASK                                                      0x00000008L
34769 #define RLC_RLCS_PG_CHANGE_READ__RESERVED_MASK                                                                0xFFFFFFF0L
34770 //RLC_RLCS_LB_STATUS
34771 #define RLC_RLCS_LB_STATUS__LB_CNTR_START__SHIFT                                                              0x0
34772 #define RLC_RLCS_LB_STATUS__LB_CNTR_STOP__SHIFT                                                               0x1
34773 #define RLC_RLCS_LB_STATUS__LB_CNTR_1_MAX_FLAG__SHIFT                                                         0x2
34774 #define RLC_RLCS_LB_STATUS__LB_CNTR_2_MAX_FLAG__SHIFT                                                         0x3
34775 #define RLC_RLCS_LB_STATUS__LBPW_DISABLE_FLAG__SHIFT                                                          0x4
34776 #define RLC_RLCS_LB_STATUS__RESERVED__SHIFT                                                                   0x5
34777 #define RLC_RLCS_LB_STATUS__LB_CNTR_START_MASK                                                                0x00000001L
34778 #define RLC_RLCS_LB_STATUS__LB_CNTR_STOP_MASK                                                                 0x00000002L
34779 #define RLC_RLCS_LB_STATUS__LB_CNTR_1_MAX_FLAG_MASK                                                           0x00000004L
34780 #define RLC_RLCS_LB_STATUS__LB_CNTR_2_MAX_FLAG_MASK                                                           0x00000008L
34781 #define RLC_RLCS_LB_STATUS__LBPW_DISABLE_FLAG_MASK                                                            0x00000010L
34782 #define RLC_RLCS_LB_STATUS__RESERVED_MASK                                                                     0xFFFFFFE0L
34783 //RLC_RLCS_LB_READ
34784 #define RLC_RLCS_LB_READ__LB_CNTR_START__SHIFT                                                                0x0
34785 #define RLC_RLCS_LB_READ__LB_CNTR_STOP__SHIFT                                                                 0x1
34786 #define RLC_RLCS_LB_READ__LB_CNTR_1_MAX_FLAG__SHIFT                                                           0x2
34787 #define RLC_RLCS_LB_READ__LB_CNTR_2_MAX_FLAG__SHIFT                                                           0x3
34788 #define RLC_RLCS_LB_READ__LBPW_DISABLE_FLAG__SHIFT                                                            0x4
34789 #define RLC_RLCS_LB_READ__RESERVED__SHIFT                                                                     0x5
34790 #define RLC_RLCS_LB_READ__LB_CNTR_START_MASK                                                                  0x00000001L
34791 #define RLC_RLCS_LB_READ__LB_CNTR_STOP_MASK                                                                   0x00000002L
34792 #define RLC_RLCS_LB_READ__LB_CNTR_1_MAX_FLAG_MASK                                                             0x00000004L
34793 #define RLC_RLCS_LB_READ__LB_CNTR_2_MAX_FLAG_MASK                                                             0x00000008L
34794 #define RLC_RLCS_LB_READ__LBPW_DISABLE_FLAG_MASK                                                              0x00000010L
34795 #define RLC_RLCS_LB_READ__RESERVED_MASK                                                                       0xFFFFFFE0L
34796 //RLC_RLCS_LB_CONTROL
34797 #define RLC_RLCS_LB_CONTROL__NEW_LBPW_REQ__SHIFT                                                              0x0
34798 #define RLC_RLCS_LB_CONTROL__LB_CNTR_INC_CP_BUSY__SHIFT                                                       0x1
34799 #define RLC_RLCS_LB_CONTROL__RESERVED__SHIFT                                                                  0x2
34800 #define RLC_RLCS_LB_CONTROL__NEW_LBPW_REQ_MASK                                                                0x00000001L
34801 #define RLC_RLCS_LB_CONTROL__LB_CNTR_INC_CP_BUSY_MASK                                                         0x00000002L
34802 #define RLC_RLCS_LB_CONTROL__RESERVED_MASK                                                                    0xFFFFFFFCL
34803 //RLC_RLCS_IH_SEMAPHORE
34804 #define RLC_RLCS_IH_SEMAPHORE__CLIENT_ID__SHIFT                                                               0x0
34805 #define RLC_RLCS_IH_SEMAPHORE__RESERVED__SHIFT                                                                0x5
34806 #define RLC_RLCS_IH_SEMAPHORE__CLIENT_ID_MASK                                                                 0x0000001FL
34807 #define RLC_RLCS_IH_SEMAPHORE__RESERVED_MASK                                                                  0xFFFFFFE0L
34808 //RLC_RLCS_IH_COOKIE_SEMAPHORE
34809 #define RLC_RLCS_IH_COOKIE_SEMAPHORE__CLIENT_ID__SHIFT                                                        0x0
34810 #define RLC_RLCS_IH_COOKIE_SEMAPHORE__RESERVED__SHIFT                                                         0x5
34811 #define RLC_RLCS_IH_COOKIE_SEMAPHORE__CLIENT_ID_MASK                                                          0x0000001FL
34812 #define RLC_RLCS_IH_COOKIE_SEMAPHORE__RESERVED_MASK                                                           0xFFFFFFE0L
34813 //RLC_RLCS_IH_CTRL_1
34814 #define RLC_RLCS_IH_CTRL_1__IH_CONTEXT_ID_1__SHIFT                                                            0x0
34815 #define RLC_RLCS_IH_CTRL_1__IH_CONTEXT_ID_1_MASK                                                              0xFFFFFFFFL
34816 //RLC_RLCS_IH_CTRL_2
34817 #define RLC_RLCS_IH_CTRL_2__IH_CONTEXT_ID_2__SHIFT                                                            0x0
34818 #define RLC_RLCS_IH_CTRL_2__IH_RING_ID__SHIFT                                                                 0x8
34819 #define RLC_RLCS_IH_CTRL_2__IH_VM_ID__SHIFT                                                                   0x10
34820 #define RLC_RLCS_IH_CTRL_2__RESERVED__SHIFT                                                                   0x14
34821 #define RLC_RLCS_IH_CTRL_2__IH_CONTEXT_ID_2_MASK                                                              0x000000FFL
34822 #define RLC_RLCS_IH_CTRL_2__IH_RING_ID_MASK                                                                   0x0000FF00L
34823 #define RLC_RLCS_IH_CTRL_2__IH_VM_ID_MASK                                                                     0x000F0000L
34824 #define RLC_RLCS_IH_CTRL_2__RESERVED_MASK                                                                     0xFFF00000L
34825 //RLC_RLCS_IH_CTRL_3
34826 #define RLC_RLCS_IH_CTRL_3__IH_SOURCE_ID__SHIFT                                                               0x0
34827 #define RLC_RLCS_IH_CTRL_3__IH_VF_ID__SHIFT                                                                   0x8
34828 #define RLC_RLCS_IH_CTRL_3__IH_VF__SHIFT                                                                      0xd
34829 #define RLC_RLCS_IH_CTRL_3__RESERVED__SHIFT                                                                   0xe
34830 #define RLC_RLCS_IH_CTRL_3__IH_SOURCE_ID_MASK                                                                 0x000000FFL
34831 #define RLC_RLCS_IH_CTRL_3__IH_VF_ID_MASK                                                                     0x00001F00L
34832 #define RLC_RLCS_IH_CTRL_3__IH_VF_MASK                                                                        0x00002000L
34833 #define RLC_RLCS_IH_CTRL_3__RESERVED_MASK                                                                     0xFFFFC000L
34834 //RLC_RLCS_IH_STATUS
34835 #define RLC_RLCS_IH_STATUS__IH_CREDIT_COUNT__SHIFT                                                            0x0
34836 #define RLC_RLCS_IH_STATUS__IH_BUSY__SHIFT                                                                    0x6
34837 #define RLC_RLCS_IH_STATUS__RESERVED__SHIFT                                                                   0x7
34838 #define RLC_RLCS_IH_STATUS__IH_CREDIT_COUNT_MASK                                                              0x0000003FL
34839 #define RLC_RLCS_IH_STATUS__IH_BUSY_MASK                                                                      0x00000040L
34840 #define RLC_RLCS_IH_STATUS__RESERVED_MASK                                                                     0xFFFFFF80L
34841 //RLC_RLCS_WGP_STATUS
34842 #define RLC_RLCS_WGP_STATUS__CS_WORK_ACTIVE__SHIFT                                                            0x0
34843 #define RLC_RLCS_WGP_STATUS__STATIC_WGP_STATUS_CHANGED__SHIFT                                                 0x1
34844 #define RLC_RLCS_WGP_STATUS__DYMANIC_WGP_STATUS_CHANGED__SHIFT                                                0x2
34845 #define RLC_RLCS_WGP_STATUS__STATIC_PERWGP_PD_INCOMPLETE__SHIFT                                               0x3
34846 #define RLC_RLCS_WGP_STATUS__RESERVED__SHIFT                                                                  0x4
34847 #define RLC_RLCS_WGP_STATUS__CS_WORK_ACTIVE_MASK                                                              0x00000001L
34848 #define RLC_RLCS_WGP_STATUS__STATIC_WGP_STATUS_CHANGED_MASK                                                   0x00000002L
34849 #define RLC_RLCS_WGP_STATUS__DYMANIC_WGP_STATUS_CHANGED_MASK                                                  0x00000004L
34850 #define RLC_RLCS_WGP_STATUS__STATIC_PERWGP_PD_INCOMPLETE_MASK                                                 0x00000008L
34851 #define RLC_RLCS_WGP_STATUS__RESERVED_MASK                                                                    0xFFFFFFF0L
34852 //RLC_RLCS_WGP_READ
34853 #define RLC_RLCS_WGP_READ__CS_WORK_ACTIVE__SHIFT                                                              0x0
34854 #define RLC_RLCS_WGP_READ__STATIC_WGP_STATUS_CHANGED__SHIFT                                                   0x1
34855 #define RLC_RLCS_WGP_READ__DYMANIC_WGP_STATUS_CHANGED__SHIFT                                                  0x2
34856 #define RLC_RLCS_WGP_READ__RESERVED__SHIFT                                                                    0x3
34857 #define RLC_RLCS_WGP_READ__CS_WORK_ACTIVE_MASK                                                                0x00000001L
34858 #define RLC_RLCS_WGP_READ__STATIC_WGP_STATUS_CHANGED_MASK                                                     0x00000002L
34859 #define RLC_RLCS_WGP_READ__DYMANIC_WGP_STATUS_CHANGED_MASK                                                    0x00000004L
34860 #define RLC_RLCS_WGP_READ__RESERVED_MASK                                                                      0xFFFFFFF8L
34861 //RLC_RLCS_CP_INT_CTRL_1
34862 #define RLC_RLCS_CP_INT_CTRL_1__INTERRUPT_ACK__SHIFT                                                          0x0
34863 #define RLC_RLCS_CP_INT_CTRL_1__RESERVED__SHIFT                                                               0x1
34864 #define RLC_RLCS_CP_INT_CTRL_1__INTERRUPT_ACK_MASK                                                            0x00000001L
34865 #define RLC_RLCS_CP_INT_CTRL_1__RESERVED_MASK                                                                 0xFFFFFFFEL
34866 //RLC_RLCS_CP_INT_CTRL_2
34867 #define RLC_RLCS_CP_INT_CTRL_2__IDLE_AUTO_ACK_EN__SHIFT                                                       0x0
34868 #define RLC_RLCS_CP_INT_CTRL_2__BUSY_AUTO_ACK_EN__SHIFT                                                       0x1
34869 #define RLC_RLCS_CP_INT_CTRL_2__RESERVED__SHIFT                                                               0x2
34870 #define RLC_RLCS_CP_INT_CTRL_2__IDLE_AUTO_ACK_EN_MASK                                                         0x00000001L
34871 #define RLC_RLCS_CP_INT_CTRL_2__BUSY_AUTO_ACK_EN_MASK                                                         0x00000002L
34872 #define RLC_RLCS_CP_INT_CTRL_2__RESERVED_MASK                                                                 0xFFFFFFFCL
34873 //RLC_RLCS_CP_INT_INFO_1
34874 #define RLC_RLCS_CP_INT_INFO_1__INTERRUPT_INFO_1__SHIFT                                                       0x0
34875 #define RLC_RLCS_CP_INT_INFO_1__INTERRUPT_INFO_1_MASK                                                         0xFFFFFFFFL
34876 //RLC_RLCS_CP_INT_INFO_2
34877 #define RLC_RLCS_CP_INT_INFO_2__INTERRUPT_INFO_2__SHIFT                                                       0x0
34878 #define RLC_RLCS_CP_INT_INFO_2__INTERRUPT_ID__SHIFT                                                           0x10
34879 #define RLC_RLCS_CP_INT_INFO_2__RESERVED__SHIFT                                                               0x19
34880 #define RLC_RLCS_CP_INT_INFO_2__INTERRUPT_INFO_2_MASK                                                         0x0000FFFFL
34881 #define RLC_RLCS_CP_INT_INFO_2__INTERRUPT_ID_MASK                                                             0x01FF0000L
34882 #define RLC_RLCS_CP_INT_INFO_2__RESERVED_MASK                                                                 0xFE000000L
34883 //RLC_RLCS_SPM_INT_CTRL
34884 #define RLC_RLCS_SPM_INT_CTRL__INTERRUPT_ACK__SHIFT                                                           0x0
34885 #define RLC_RLCS_SPM_INT_CTRL__RESERVED__SHIFT                                                                0x1
34886 #define RLC_RLCS_SPM_INT_CTRL__INTERRUPT_ACK_MASK                                                             0x00000001L
34887 #define RLC_RLCS_SPM_INT_CTRL__RESERVED_MASK                                                                  0xFFFFFFFEL
34888 //RLC_RLCS_SPM_INT_INFO_1
34889 #define RLC_RLCS_SPM_INT_INFO_1__INTERRUPT_INFO_1__SHIFT                                                      0x0
34890 #define RLC_RLCS_SPM_INT_INFO_1__INTERRUPT_INFO_1_MASK                                                        0xFFFFFFFFL
34891 //RLC_RLCS_SPM_INT_INFO_2
34892 #define RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_INFO_2__SHIFT                                                      0x0
34893 #define RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_ID__SHIFT                                                          0x10
34894 #define RLC_RLCS_SPM_INT_INFO_2__RESERVED__SHIFT                                                              0x19
34895 #define RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_INFO_2_MASK                                                        0x0000FFFFL
34896 #define RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_ID_MASK                                                            0x01FF0000L
34897 #define RLC_RLCS_SPM_INT_INFO_2__RESERVED_MASK                                                                0xFE000000L
34898 //RLC_RLCS_DSM_TRIG
34899 #define RLC_RLCS_DSM_TRIG__START__SHIFT                                                                       0x0
34900 #define RLC_RLCS_DSM_TRIG__RESERVED__SHIFT                                                                    0x1
34901 #define RLC_RLCS_DSM_TRIG__START_MASK                                                                         0x00000001L
34902 #define RLC_RLCS_DSM_TRIG__RESERVED_MASK                                                                      0xFFFFFFFEL
34903 //RLC_RLCS_GE_FAST_CLOCK
34904 #define RLC_RLCS_GE_FAST_CLOCK__FAST_CLKS_CHANGED__SHIFT                                                      0x0
34905 #define RLC_RLCS_GE_FAST_CLOCK__FAST_CLKS__SHIFT                                                              0x1
34906 #define RLC_RLCS_GE_FAST_CLOCK__INT_CLEAR__SHIFT                                                              0x2
34907 #define RLC_RLCS_GE_FAST_CLOCK__RESERVED__SHIFT                                                               0x3
34908 #define RLC_RLCS_GE_FAST_CLOCK__FAST_CLKS_CHANGED_MASK                                                        0x00000001L
34909 #define RLC_RLCS_GE_FAST_CLOCK__FAST_CLKS_MASK                                                                0x00000002L
34910 #define RLC_RLCS_GE_FAST_CLOCK__INT_CLEAR_MASK                                                                0x00000004L
34911 #define RLC_RLCS_GE_FAST_CLOCK__RESERVED_MASK                                                                 0xFFFFFFF8L
34912 //RLC_RLCS_BOOTLOAD_STATUS
34913 #define RLC_RLCS_BOOTLOAD_STATUS__RLC_RLCG_IRAM_LOADED__SHIFT                                                 0x0
34914 #define RLC_RLCS_BOOTLOAD_STATUS__RESERVED__SHIFT                                                             0x1
34915 #define RLC_RLCS_BOOTLOAD_STATUS__BOOTLOAD_COMPLETE__SHIFT                                                    0x1f
34916 #define RLC_RLCS_BOOTLOAD_STATUS__RLC_RLCG_IRAM_LOADED_MASK                                                   0x00000001L
34917 #define RLC_RLCS_BOOTLOAD_STATUS__RESERVED_MASK                                                               0x7FFFFFFEL
34918 #define RLC_RLCS_BOOTLOAD_STATUS__BOOTLOAD_COMPLETE_MASK                                                      0x80000000L
34919 //RLC_RLCS_POWER_BRAKE_CNTL
34920 #define RLC_RLCS_POWER_BRAKE_CNTL__POWER_BRAKE__SHIFT                                                         0x0
34921 #define RLC_RLCS_POWER_BRAKE_CNTL__INT_CLEAR__SHIFT                                                           0x1
34922 #define RLC_RLCS_POWER_BRAKE_CNTL__MAX_HYSTERESIS__SHIFT                                                      0x2
34923 #define RLC_RLCS_POWER_BRAKE_CNTL__HYSTERESIS_CNT__SHIFT                                                      0xa
34924 #define RLC_RLCS_POWER_BRAKE_CNTL__RESERVED__SHIFT                                                            0x12
34925 #define RLC_RLCS_POWER_BRAKE_CNTL__POWER_BRAKE_MASK                                                           0x00000001L
34926 #define RLC_RLCS_POWER_BRAKE_CNTL__INT_CLEAR_MASK                                                             0x00000002L
34927 #define RLC_RLCS_POWER_BRAKE_CNTL__MAX_HYSTERESIS_MASK                                                        0x000003FCL
34928 #define RLC_RLCS_POWER_BRAKE_CNTL__HYSTERESIS_CNT_MASK                                                        0x0003FC00L
34929 #define RLC_RLCS_POWER_BRAKE_CNTL__RESERVED_MASK                                                              0xFFFC0000L
34930 //RLC_RLCS_GENERAL_0
34931 #define RLC_RLCS_GENERAL_0__DATA__SHIFT                                                                       0x0
34932 #define RLC_RLCS_GENERAL_0__DATA_MASK                                                                         0xFFFFFFFFL
34933 //RLC_RLCS_GENERAL_1
34934 #define RLC_RLCS_GENERAL_1__DATA__SHIFT                                                                       0x0
34935 #define RLC_RLCS_GENERAL_1__DATA_MASK                                                                         0xFFFFFFFFL
34936 //RLC_RLCS_GENERAL_2
34937 #define RLC_RLCS_GENERAL_2__DATA__SHIFT                                                                       0x0
34938 #define RLC_RLCS_GENERAL_2__DATA_MASK                                                                         0xFFFFFFFFL
34939 //RLC_RLCS_GENERAL_3
34940 #define RLC_RLCS_GENERAL_3__DATA__SHIFT                                                                       0x0
34941 #define RLC_RLCS_GENERAL_3__DATA_MASK                                                                         0xFFFFFFFFL
34942 //RLC_RLCS_GENERAL_4
34943 #define RLC_RLCS_GENERAL_4__DATA__SHIFT                                                                       0x0
34944 #define RLC_RLCS_GENERAL_4__DATA_MASK                                                                         0xFFFFFFFFL
34945 //RLC_RLCS_GENERAL_5
34946 #define RLC_RLCS_GENERAL_5__DATA__SHIFT                                                                       0x0
34947 #define RLC_RLCS_GENERAL_5__DATA_MASK                                                                         0xFFFFFFFFL
34948 //RLC_RLCS_GRBM_IDLE_BUSY_STAT
34949 #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__GRBM_RLC_gc_stat_idle__SHIFT                                            0x0
34950 #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY__SHIFT                                                      0x2
34951 #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY__SHIFT                                                      0x3
34952 #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__RESERVED_4__SHIFT                                                       0x4
34953 #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY_CHANGED__SHIFT                                              0x5
34954 #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY_CHANGED__SHIFT                                              0x6
34955 #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__RESERVED_7__SHIFT                                                       0x7
34956 #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__RESERVED__SHIFT                                                         0x8
34957 #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__GRBM_RLC_gc_stat_idle_MASK                                              0x00000003L
34958 #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY_MASK                                                        0x00000004L
34959 #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY_MASK                                                        0x00000008L
34960 #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__RESERVED_4_MASK                                                         0x00000010L
34961 #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY_CHANGED_MASK                                                0x00000020L
34962 #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY_CHANGED_MASK                                                0x00000040L
34963 #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__RESERVED_7_MASK                                                         0x00000080L
34964 #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__RESERVED_MASK                                                           0xFFFFFF00L
34965 //RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL
34966 #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA0_BUSY_INT_CLEAR__SHIFT                                         0x0
34967 #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA1_BUSY_INT_CLEAR__SHIFT                                         0x1
34968 #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__RESERVED_2__SHIFT                                                   0x2
34969 #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA0_BUSY_INT_CLEAR_MASK                                           0x00000001L
34970 #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA1_BUSY_INT_CLEAR_MASK                                           0x00000002L
34971 #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__RESERVED_2_MASK                                                     0x00000004L
34972 //RLC_RLCS_CMP_IDLE_CNTL
34973 #define RLC_RLCS_CMP_IDLE_CNTL__INT_CLEAR__SHIFT                                                              0x0
34974 #define RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE_HYST__SHIFT                                                          0x1
34975 #define RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE__SHIFT                                                               0x2
34976 #define RLC_RLCS_CMP_IDLE_CNTL__MAX_HYSTERESIS__SHIFT                                                         0x3
34977 #define RLC_RLCS_CMP_IDLE_CNTL__HYSTERESIS_CNT__SHIFT                                                         0xb
34978 #define RLC_RLCS_CMP_IDLE_CNTL__RESERVED__SHIFT                                                               0x13
34979 #define RLC_RLCS_CMP_IDLE_CNTL__INT_CLEAR_MASK                                                                0x00000001L
34980 #define RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE_HYST_MASK                                                            0x00000002L
34981 #define RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE_MASK                                                                 0x00000004L
34982 #define RLC_RLCS_CMP_IDLE_CNTL__MAX_HYSTERESIS_MASK                                                           0x000007F8L
34983 #define RLC_RLCS_CMP_IDLE_CNTL__HYSTERESIS_CNT_MASK                                                           0x0007F800L
34984 #define RLC_RLCS_CMP_IDLE_CNTL__RESERVED_MASK                                                                 0xFFF80000L
34985 //RLC_RLCS_POWER_BRAKE_CNTL_TH1
34986 #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__POWER_BRAKE__SHIFT                                                     0x0
34987 #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__INT_CLEAR__SHIFT                                                       0x1
34988 #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__MAX_HYSTERESIS__SHIFT                                                  0x2
34989 #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__HYSTERESIS_CNT__SHIFT                                                  0xa
34990 #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__RESERVED__SHIFT                                                        0x12
34991 #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__POWER_BRAKE_MASK                                                       0x00000001L
34992 #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__INT_CLEAR_MASK                                                         0x00000002L
34993 #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__MAX_HYSTERESIS_MASK                                                    0x000003FCL
34994 #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__HYSTERESIS_CNT_MASK                                                    0x0003FC00L
34995 #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__RESERVED_MASK                                                          0xFFFC0000L
34996 //RLC_RLCS_AUXILIARY_REG_1
34997 #define RLC_RLCS_AUXILIARY_REG_1__ADDR__SHIFT                                                                 0x0
34998 #define RLC_RLCS_AUXILIARY_REG_1__RESERVED__SHIFT                                                             0x12
34999 #define RLC_RLCS_AUXILIARY_REG_1__ADDR_MASK                                                                   0x0003FFFFL
35000 #define RLC_RLCS_AUXILIARY_REG_1__RESERVED_MASK                                                               0xFFFC0000L
35001 //RLC_RLCS_AUXILIARY_REG_2
35002 #define RLC_RLCS_AUXILIARY_REG_2__ADDR__SHIFT                                                                 0x0
35003 #define RLC_RLCS_AUXILIARY_REG_2__RESERVED__SHIFT                                                             0x12
35004 #define RLC_RLCS_AUXILIARY_REG_2__ADDR_MASK                                                                   0x0003FFFFL
35005 #define RLC_RLCS_AUXILIARY_REG_2__RESERVED_MASK                                                               0xFFFC0000L
35006 //RLC_RLCS_AUXILIARY_REG_3
35007 #define RLC_RLCS_AUXILIARY_REG_3__ADDR__SHIFT                                                                 0x0
35008 #define RLC_RLCS_AUXILIARY_REG_3__RESERVED__SHIFT                                                             0x12
35009 #define RLC_RLCS_AUXILIARY_REG_3__ADDR_MASK                                                                   0x0003FFFFL
35010 #define RLC_RLCS_AUXILIARY_REG_3__RESERVED_MASK                                                               0xFFFC0000L
35011 //RLC_RLCS_AUXILIARY_REG_4
35012 #define RLC_RLCS_AUXILIARY_REG_4__ADDR__SHIFT                                                                 0x0
35013 #define RLC_RLCS_AUXILIARY_REG_4__RESERVED__SHIFT                                                             0x12
35014 #define RLC_RLCS_AUXILIARY_REG_4__ADDR_MASK                                                                   0x0003FFFFL
35015 #define RLC_RLCS_AUXILIARY_REG_4__RESERVED_MASK                                                               0xFFFC0000L
35016 //RLC_RLCS_SPM_SQTT_MODE
35017 #define RLC_RLCS_SPM_SQTT_MODE__MODE__SHIFT                                                                   0x0
35018 #define RLC_RLCS_SPM_SQTT_MODE__MODE_MASK                                                                     0x00000001L
35019 //RLC_RLCS_CP_DMA_SRCID_OVER
35020 #define RLC_RLCS_CP_DMA_SRCID_OVER__SRCID_OVERRIDE__SHIFT                                                     0x0
35021 #define RLC_RLCS_CP_DMA_SRCID_OVER__SRCID_OVERRIDE_MASK                                                       0x00000001L
35022 //RLC_RLCS_UTCL2_CNTL
35023 #define RLC_RLCS_UTCL2_CNTL__MTYPE_NO_PTE_MODE__SHIFT                                                         0x0
35024 #define RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE__SHIFT                                                              0x1
35025 #define RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE__SHIFT                                                               0x2
35026 #define RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE_VALUE__SHIFT                                                        0x3
35027 #define RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE_VALUE__SHIFT                                                         0x5
35028 #define RLC_RLCS_UTCL2_CNTL__RESERVED__SHIFT                                                                  0x6
35029 #define RLC_RLCS_UTCL2_CNTL__MTYPE_NO_PTE_MODE_MASK                                                           0x00000001L
35030 #define RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE_MASK                                                                0x00000002L
35031 #define RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE_MASK                                                                 0x00000004L
35032 #define RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE_VALUE_MASK                                                          0x00000018L
35033 #define RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE_VALUE_MASK                                                           0x00000020L
35034 #define RLC_RLCS_UTCL2_CNTL__RESERVED_MASK                                                                    0xFFFFFFC0L
35035 //RLC_RLCS_MP1_RLC_DOORBELL_CTRL
35036 #define RLC_RLCS_MP1_RLC_DOORBELL_CTRL__INT_CLEAR__SHIFT                                                      0x0
35037 #define RLC_RLCS_MP1_RLC_DOORBELL_CTRL__DOORBELL__SHIFT                                                       0x1
35038 #define RLC_RLCS_MP1_RLC_DOORBELL_CTRL__RESERVED__SHIFT                                                       0x2
35039 #define RLC_RLCS_MP1_RLC_DOORBELL_CTRL__INT_CLEAR_MASK                                                        0x00000001L
35040 #define RLC_RLCS_MP1_RLC_DOORBELL_CTRL__DOORBELL_MASK                                                         0x00000002L
35041 #define RLC_RLCS_MP1_RLC_DOORBELL_CTRL__RESERVED_MASK                                                         0xFFFFFFFCL
35042 //RLC_RLCS_BOOTLOAD_ID_STATUS1
35043 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_0_LOADED__SHIFT                                                      0x0
35044 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_1_LOADED__SHIFT                                                      0x1
35045 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_2_LOADED__SHIFT                                                      0x2
35046 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_3_LOADED__SHIFT                                                      0x3
35047 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_4_LOADED__SHIFT                                                      0x4
35048 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_5_LOADED__SHIFT                                                      0x5
35049 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_6_LOADED__SHIFT                                                      0x6
35050 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_7_LOADED__SHIFT                                                      0x7
35051 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_8_LOADED__SHIFT                                                      0x8
35052 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_9_LOADED__SHIFT                                                      0x9
35053 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_10_LOADED__SHIFT                                                     0xa
35054 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_11_LOADED__SHIFT                                                     0xb
35055 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_12_LOADED__SHIFT                                                     0xc
35056 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_13_LOADED__SHIFT                                                     0xd
35057 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_14_LOADED__SHIFT                                                     0xe
35058 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_15_LOADED__SHIFT                                                     0xf
35059 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_16_LOADED__SHIFT                                                     0x10
35060 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_17_LOADED__SHIFT                                                     0x11
35061 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_18_LOADED__SHIFT                                                     0x12
35062 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_19_LOADED__SHIFT                                                     0x13
35063 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_20_LOADED__SHIFT                                                     0x14
35064 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_21_LOADED__SHIFT                                                     0x15
35065 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_22_LOADED__SHIFT                                                     0x16
35066 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_23_LOADED__SHIFT                                                     0x17
35067 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_24_LOADED__SHIFT                                                     0x18
35068 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_25_LOADED__SHIFT                                                     0x19
35069 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_26_LOADED__SHIFT                                                     0x1a
35070 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_27_LOADED__SHIFT                                                     0x1b
35071 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_28_LOADED__SHIFT                                                     0x1c
35072 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_29_LOADED__SHIFT                                                     0x1d
35073 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_30_LOADED__SHIFT                                                     0x1e
35074 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_31_LOADED__SHIFT                                                     0x1f
35075 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_0_LOADED_MASK                                                        0x00000001L
35076 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_1_LOADED_MASK                                                        0x00000002L
35077 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_2_LOADED_MASK                                                        0x00000004L
35078 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_3_LOADED_MASK                                                        0x00000008L
35079 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_4_LOADED_MASK                                                        0x00000010L
35080 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_5_LOADED_MASK                                                        0x00000020L
35081 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_6_LOADED_MASK                                                        0x00000040L
35082 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_7_LOADED_MASK                                                        0x00000080L
35083 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_8_LOADED_MASK                                                        0x00000100L
35084 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_9_LOADED_MASK                                                        0x00000200L
35085 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_10_LOADED_MASK                                                       0x00000400L
35086 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_11_LOADED_MASK                                                       0x00000800L
35087 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_12_LOADED_MASK                                                       0x00001000L
35088 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_13_LOADED_MASK                                                       0x00002000L
35089 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_14_LOADED_MASK                                                       0x00004000L
35090 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_15_LOADED_MASK                                                       0x00008000L
35091 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_16_LOADED_MASK                                                       0x00010000L
35092 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_17_LOADED_MASK                                                       0x00020000L
35093 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_18_LOADED_MASK                                                       0x00040000L
35094 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_19_LOADED_MASK                                                       0x00080000L
35095 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_20_LOADED_MASK                                                       0x00100000L
35096 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_21_LOADED_MASK                                                       0x00200000L
35097 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_22_LOADED_MASK                                                       0x00400000L
35098 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_23_LOADED_MASK                                                       0x00800000L
35099 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_24_LOADED_MASK                                                       0x01000000L
35100 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_25_LOADED_MASK                                                       0x02000000L
35101 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_26_LOADED_MASK                                                       0x04000000L
35102 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_27_LOADED_MASK                                                       0x08000000L
35103 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_28_LOADED_MASK                                                       0x10000000L
35104 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_29_LOADED_MASK                                                       0x20000000L
35105 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_30_LOADED_MASK                                                       0x40000000L
35106 #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_31_LOADED_MASK                                                       0x80000000L
35107 //RLC_RLCS_BOOTLOAD_ID_STATUS2
35108 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_32_LOADED__SHIFT                                                     0x0
35109 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_33_LOADED__SHIFT                                                     0x1
35110 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_34_LOADED__SHIFT                                                     0x2
35111 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_35_LOADED__SHIFT                                                     0x3
35112 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_36_LOADED__SHIFT                                                     0x4
35113 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_37_LOADED__SHIFT                                                     0x5
35114 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_38_LOADED__SHIFT                                                     0x6
35115 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_39_LOADED__SHIFT                                                     0x7
35116 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_40_LOADED__SHIFT                                                     0x8
35117 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_41_LOADED__SHIFT                                                     0x9
35118 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_42_LOADED__SHIFT                                                     0xa
35119 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_43_LOADED__SHIFT                                                     0xb
35120 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_44_LOADED__SHIFT                                                     0xc
35121 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_45_LOADED__SHIFT                                                     0xd
35122 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_46_LOADED__SHIFT                                                     0xe
35123 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_47_LOADED__SHIFT                                                     0xf
35124 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_48_LOADED__SHIFT                                                     0x10
35125 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_49_LOADED__SHIFT                                                     0x11
35126 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_50_LOADED__SHIFT                                                     0x12
35127 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_51_LOADED__SHIFT                                                     0x13
35128 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_52_LOADED__SHIFT                                                     0x14
35129 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_53_LOADED__SHIFT                                                     0x15
35130 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_54_LOADED__SHIFT                                                     0x16
35131 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_55_LOADED__SHIFT                                                     0x17
35132 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_56_LOADED__SHIFT                                                     0x18
35133 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_57_LOADED__SHIFT                                                     0x19
35134 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_58_LOADED__SHIFT                                                     0x1a
35135 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_59_LOADED__SHIFT                                                     0x1b
35136 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_60_LOADED__SHIFT                                                     0x1c
35137 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_61_LOADED__SHIFT                                                     0x1d
35138 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_62_LOADED__SHIFT                                                     0x1e
35139 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_63_LOADED__SHIFT                                                     0x1f
35140 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_32_LOADED_MASK                                                       0x00000001L
35141 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_33_LOADED_MASK                                                       0x00000002L
35142 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_34_LOADED_MASK                                                       0x00000004L
35143 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_35_LOADED_MASK                                                       0x00000008L
35144 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_36_LOADED_MASK                                                       0x00000010L
35145 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_37_LOADED_MASK                                                       0x00000020L
35146 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_38_LOADED_MASK                                                       0x00000040L
35147 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_39_LOADED_MASK                                                       0x00000080L
35148 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_40_LOADED_MASK                                                       0x00000100L
35149 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_41_LOADED_MASK                                                       0x00000200L
35150 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_42_LOADED_MASK                                                       0x00000400L
35151 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_43_LOADED_MASK                                                       0x00000800L
35152 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_44_LOADED_MASK                                                       0x00001000L
35153 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_45_LOADED_MASK                                                       0x00002000L
35154 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_46_LOADED_MASK                                                       0x00004000L
35155 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_47_LOADED_MASK                                                       0x00008000L
35156 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_48_LOADED_MASK                                                       0x00010000L
35157 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_49_LOADED_MASK                                                       0x00020000L
35158 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_50_LOADED_MASK                                                       0x00040000L
35159 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_51_LOADED_MASK                                                       0x00080000L
35160 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_52_LOADED_MASK                                                       0x00100000L
35161 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_53_LOADED_MASK                                                       0x00200000L
35162 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_54_LOADED_MASK                                                       0x00400000L
35163 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_55_LOADED_MASK                                                       0x00800000L
35164 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_56_LOADED_MASK                                                       0x01000000L
35165 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_57_LOADED_MASK                                                       0x02000000L
35166 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_58_LOADED_MASK                                                       0x04000000L
35167 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_59_LOADED_MASK                                                       0x08000000L
35168 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_60_LOADED_MASK                                                       0x10000000L
35169 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_61_LOADED_MASK                                                       0x20000000L
35170 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_62_LOADED_MASK                                                       0x40000000L
35171 #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_63_LOADED_MASK                                                       0x80000000L
35172 //RLC_RLCS_EDC_INT_CNTL
35173 #define RLC_RLCS_EDC_INT_CNTL__EDC_EVENT_INT_CLEAR__SHIFT                                                     0x0
35174 #define RLC_RLCS_EDC_INT_CNTL__EDC_EVENT_INT_CLEAR_MASK                                                       0x00000001L
35175 //RLC_RLCS_DEC_END
35176 
35177 
35178 // addressBlock: gc_pwrdec
35179 //CGTS_SA0_QUAD0_SM_CTRL_REG
35180 #define CGTS_SA0_QUAD0_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT                                                       0x0
35181 #define CGTS_SA0_QUAD0_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT                                                      0x4
35182 #define CGTS_SA0_QUAD0_SM_CTRL_REG__MASK_OVERRIDE__SHIFT                                                      0xf
35183 #define CGTS_SA0_QUAD0_SM_CTRL_REG__BASE_MODE__SHIFT                                                          0x10
35184 #define CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT                                                            0x11
35185 #define CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT                                                     0x14
35186 #define CGTS_SA0_QUAD0_SM_CTRL_REG__OVERRIDE__SHIFT                                                           0x15
35187 #define CGTS_SA0_QUAD0_SM_CTRL_REG__LS_OVERRIDE__SHIFT                                                        0x16
35188 #define CGTS_SA0_QUAD0_SM_CTRL_REG__CGTS_MGCG_EN__SHIFT                                                       0x17
35189 #define CGTS_SA0_QUAD0_SM_CTRL_REG__CGTS_CLKEN_MODE__SHIFT                                                    0x18
35190 #define CGTS_SA0_QUAD0_SM_CTRL_REG__CGTS_SW_CLKEN__SHIFT                                                      0x19
35191 #define CGTS_SA0_QUAD0_SM_CTRL_REG__CGTS_CLKEN_DELAY__SHIFT                                                   0x1a
35192 #define CGTS_SA0_QUAD0_SM_CTRL_REG__ON_SEQ_DELAY_MASK                                                         0x0000000FL
35193 #define CGTS_SA0_QUAD0_SM_CTRL_REG__OFF_SEQ_DELAY_MASK                                                        0x00000FF0L
35194 #define CGTS_SA0_QUAD0_SM_CTRL_REG__MASK_OVERRIDE_MASK                                                        0x00008000L
35195 #define CGTS_SA0_QUAD0_SM_CTRL_REG__BASE_MODE_MASK                                                            0x00010000L
35196 #define CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK                                                              0x000E0000L
35197 #define CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_ENABLE_MASK                                                       0x00100000L
35198 #define CGTS_SA0_QUAD0_SM_CTRL_REG__OVERRIDE_MASK                                                             0x00200000L
35199 #define CGTS_SA0_QUAD0_SM_CTRL_REG__LS_OVERRIDE_MASK                                                          0x00400000L
35200 #define CGTS_SA0_QUAD0_SM_CTRL_REG__CGTS_MGCG_EN_MASK                                                         0x00800000L
35201 #define CGTS_SA0_QUAD0_SM_CTRL_REG__CGTS_CLKEN_MODE_MASK                                                      0x01000000L
35202 #define CGTS_SA0_QUAD0_SM_CTRL_REG__CGTS_SW_CLKEN_MASK                                                        0x02000000L
35203 #define CGTS_SA0_QUAD0_SM_CTRL_REG__CGTS_CLKEN_DELAY_MASK                                                     0xFC000000L
35204 //CGTS_SA0_QUAD0_CLK_MONITOR_DELAY_REG
35205 #define CGTS_SA0_QUAD0_CLK_MONITOR_DELAY_REG__OFF_MONITOR_DELAY__SHIFT                                        0x0
35206 #define CGTS_SA0_QUAD0_CLK_MONITOR_DELAY_REG__ON_MONITOR_DELAY__SHIFT                                         0xa
35207 #define CGTS_SA0_QUAD0_CLK_MONITOR_DELAY_REG__OFF_MONITOR_DELAY_MASK                                          0x000003FFL
35208 #define CGTS_SA0_QUAD0_CLK_MONITOR_DELAY_REG__ON_MONITOR_DELAY_MASK                                           0x0007FC00L
35209 //CGTS_SA0_QUAD1_SM_CTRL_REG
35210 #define CGTS_SA0_QUAD1_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT                                                       0x0
35211 #define CGTS_SA0_QUAD1_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT                                                      0x4
35212 #define CGTS_SA0_QUAD1_SM_CTRL_REG__MASK_OVERRIDE__SHIFT                                                      0xf
35213 #define CGTS_SA0_QUAD1_SM_CTRL_REG__BASE_MODE__SHIFT                                                          0x10
35214 #define CGTS_SA0_QUAD1_SM_CTRL_REG__SM_MODE__SHIFT                                                            0x11
35215 #define CGTS_SA0_QUAD1_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT                                                     0x14
35216 #define CGTS_SA0_QUAD1_SM_CTRL_REG__OVERRIDE__SHIFT                                                           0x15
35217 #define CGTS_SA0_QUAD1_SM_CTRL_REG__LS_OVERRIDE__SHIFT                                                        0x16
35218 #define CGTS_SA0_QUAD1_SM_CTRL_REG__CGTS_MGCG_EN__SHIFT                                                       0x17
35219 #define CGTS_SA0_QUAD1_SM_CTRL_REG__CGTS_CLKEN_MODE__SHIFT                                                    0x18
35220 #define CGTS_SA0_QUAD1_SM_CTRL_REG__CGTS_SW_CLKEN__SHIFT                                                      0x19
35221 #define CGTS_SA0_QUAD1_SM_CTRL_REG__CGTS_CLKEN_DELAY__SHIFT                                                   0x1a
35222 #define CGTS_SA0_QUAD1_SM_CTRL_REG__ON_SEQ_DELAY_MASK                                                         0x0000000FL
35223 #define CGTS_SA0_QUAD1_SM_CTRL_REG__OFF_SEQ_DELAY_MASK                                                        0x00000FF0L
35224 #define CGTS_SA0_QUAD1_SM_CTRL_REG__MASK_OVERRIDE_MASK                                                        0x00008000L
35225 #define CGTS_SA0_QUAD1_SM_CTRL_REG__BASE_MODE_MASK                                                            0x00010000L
35226 #define CGTS_SA0_QUAD1_SM_CTRL_REG__SM_MODE_MASK                                                              0x000E0000L
35227 #define CGTS_SA0_QUAD1_SM_CTRL_REG__SM_MODE_ENABLE_MASK                                                       0x00100000L
35228 #define CGTS_SA0_QUAD1_SM_CTRL_REG__OVERRIDE_MASK                                                             0x00200000L
35229 #define CGTS_SA0_QUAD1_SM_CTRL_REG__LS_OVERRIDE_MASK                                                          0x00400000L
35230 #define CGTS_SA0_QUAD1_SM_CTRL_REG__CGTS_MGCG_EN_MASK                                                         0x00800000L
35231 #define CGTS_SA0_QUAD1_SM_CTRL_REG__CGTS_CLKEN_MODE_MASK                                                      0x01000000L
35232 #define CGTS_SA0_QUAD1_SM_CTRL_REG__CGTS_SW_CLKEN_MASK                                                        0x02000000L
35233 #define CGTS_SA0_QUAD1_SM_CTRL_REG__CGTS_CLKEN_DELAY_MASK                                                     0xFC000000L
35234 //CGTS_SA0_QUAD1_CLK_MONITOR_DELAY_REG
35235 #define CGTS_SA0_QUAD1_CLK_MONITOR_DELAY_REG__OFF_MONITOR_DELAY__SHIFT                                        0x0
35236 #define CGTS_SA0_QUAD1_CLK_MONITOR_DELAY_REG__ON_MONITOR_DELAY__SHIFT                                         0xa
35237 #define CGTS_SA0_QUAD1_CLK_MONITOR_DELAY_REG__OFF_MONITOR_DELAY_MASK                                          0x000003FFL
35238 #define CGTS_SA0_QUAD1_CLK_MONITOR_DELAY_REG__ON_MONITOR_DELAY_MASK                                           0x0007FC00L
35239 //CGTS_SA1_QUAD0_SM_CTRL_REG
35240 #define CGTS_SA1_QUAD0_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT                                                       0x0
35241 #define CGTS_SA1_QUAD0_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT                                                      0x4
35242 #define CGTS_SA1_QUAD0_SM_CTRL_REG__MASK_OVERRIDE__SHIFT                                                      0xf
35243 #define CGTS_SA1_QUAD0_SM_CTRL_REG__BASE_MODE__SHIFT                                                          0x10
35244 #define CGTS_SA1_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT                                                            0x11
35245 #define CGTS_SA1_QUAD0_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT                                                     0x14
35246 #define CGTS_SA1_QUAD0_SM_CTRL_REG__OVERRIDE__SHIFT                                                           0x15
35247 #define CGTS_SA1_QUAD0_SM_CTRL_REG__LS_OVERRIDE__SHIFT                                                        0x16
35248 #define CGTS_SA1_QUAD0_SM_CTRL_REG__CGTS_MGCG_EN__SHIFT                                                       0x17
35249 #define CGTS_SA1_QUAD0_SM_CTRL_REG__CGTS_CLKEN_MODE__SHIFT                                                    0x18
35250 #define CGTS_SA1_QUAD0_SM_CTRL_REG__CGTS_SW_CLKEN__SHIFT                                                      0x19
35251 #define CGTS_SA1_QUAD0_SM_CTRL_REG__CGTS_CLKEN_DELAY__SHIFT                                                   0x1a
35252 #define CGTS_SA1_QUAD0_SM_CTRL_REG__ON_SEQ_DELAY_MASK                                                         0x0000000FL
35253 #define CGTS_SA1_QUAD0_SM_CTRL_REG__OFF_SEQ_DELAY_MASK                                                        0x00000FF0L
35254 #define CGTS_SA1_QUAD0_SM_CTRL_REG__MASK_OVERRIDE_MASK                                                        0x00008000L
35255 #define CGTS_SA1_QUAD0_SM_CTRL_REG__BASE_MODE_MASK                                                            0x00010000L
35256 #define CGTS_SA1_QUAD0_SM_CTRL_REG__SM_MODE_MASK                                                              0x000E0000L
35257 #define CGTS_SA1_QUAD0_SM_CTRL_REG__SM_MODE_ENABLE_MASK                                                       0x00100000L
35258 #define CGTS_SA1_QUAD0_SM_CTRL_REG__OVERRIDE_MASK                                                             0x00200000L
35259 #define CGTS_SA1_QUAD0_SM_CTRL_REG__LS_OVERRIDE_MASK                                                          0x00400000L
35260 #define CGTS_SA1_QUAD0_SM_CTRL_REG__CGTS_MGCG_EN_MASK                                                         0x00800000L
35261 #define CGTS_SA1_QUAD0_SM_CTRL_REG__CGTS_CLKEN_MODE_MASK                                                      0x01000000L
35262 #define CGTS_SA1_QUAD0_SM_CTRL_REG__CGTS_SW_CLKEN_MASK                                                        0x02000000L
35263 #define CGTS_SA1_QUAD0_SM_CTRL_REG__CGTS_CLKEN_DELAY_MASK                                                     0xFC000000L
35264 //CGTS_SA1_QUAD0_CLK_MONITOR_DELAY_REG
35265 #define CGTS_SA1_QUAD0_CLK_MONITOR_DELAY_REG__OFF_MONITOR_DELAY__SHIFT                                        0x0
35266 #define CGTS_SA1_QUAD0_CLK_MONITOR_DELAY_REG__ON_MONITOR_DELAY__SHIFT                                         0xa
35267 #define CGTS_SA1_QUAD0_CLK_MONITOR_DELAY_REG__OFF_MONITOR_DELAY_MASK                                          0x000003FFL
35268 #define CGTS_SA1_QUAD0_CLK_MONITOR_DELAY_REG__ON_MONITOR_DELAY_MASK                                           0x0007FC00L
35269 //CGTS_SA1_QUAD1_SM_CTRL_REG
35270 #define CGTS_SA1_QUAD1_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT                                                       0x0
35271 #define CGTS_SA1_QUAD1_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT                                                      0x4
35272 #define CGTS_SA1_QUAD1_SM_CTRL_REG__MASK_OVERRIDE__SHIFT                                                      0xf
35273 #define CGTS_SA1_QUAD1_SM_CTRL_REG__BASE_MODE__SHIFT                                                          0x10
35274 #define CGTS_SA1_QUAD1_SM_CTRL_REG__SM_MODE__SHIFT                                                            0x11
35275 #define CGTS_SA1_QUAD1_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT                                                     0x14
35276 #define CGTS_SA1_QUAD1_SM_CTRL_REG__OVERRIDE__SHIFT                                                           0x15
35277 #define CGTS_SA1_QUAD1_SM_CTRL_REG__LS_OVERRIDE__SHIFT                                                        0x16
35278 #define CGTS_SA1_QUAD1_SM_CTRL_REG__CGTS_MGCG_EN__SHIFT                                                       0x17
35279 #define CGTS_SA1_QUAD1_SM_CTRL_REG__CGTS_CLKEN_MODE__SHIFT                                                    0x18
35280 #define CGTS_SA1_QUAD1_SM_CTRL_REG__CGTS_SW_CLKEN__SHIFT                                                      0x19
35281 #define CGTS_SA1_QUAD1_SM_CTRL_REG__CGTS_CLKEN_DELAY__SHIFT                                                   0x1a
35282 #define CGTS_SA1_QUAD1_SM_CTRL_REG__ON_SEQ_DELAY_MASK                                                         0x0000000FL
35283 #define CGTS_SA1_QUAD1_SM_CTRL_REG__OFF_SEQ_DELAY_MASK                                                        0x00000FF0L
35284 #define CGTS_SA1_QUAD1_SM_CTRL_REG__MASK_OVERRIDE_MASK                                                        0x00008000L
35285 #define CGTS_SA1_QUAD1_SM_CTRL_REG__BASE_MODE_MASK                                                            0x00010000L
35286 #define CGTS_SA1_QUAD1_SM_CTRL_REG__SM_MODE_MASK                                                              0x000E0000L
35287 #define CGTS_SA1_QUAD1_SM_CTRL_REG__SM_MODE_ENABLE_MASK                                                       0x00100000L
35288 #define CGTS_SA1_QUAD1_SM_CTRL_REG__OVERRIDE_MASK                                                             0x00200000L
35289 #define CGTS_SA1_QUAD1_SM_CTRL_REG__LS_OVERRIDE_MASK                                                          0x00400000L
35290 #define CGTS_SA1_QUAD1_SM_CTRL_REG__CGTS_MGCG_EN_MASK                                                         0x00800000L
35291 #define CGTS_SA1_QUAD1_SM_CTRL_REG__CGTS_CLKEN_MODE_MASK                                                      0x01000000L
35292 #define CGTS_SA1_QUAD1_SM_CTRL_REG__CGTS_SW_CLKEN_MASK                                                        0x02000000L
35293 #define CGTS_SA1_QUAD1_SM_CTRL_REG__CGTS_CLKEN_DELAY_MASK                                                     0xFC000000L
35294 //CGTS_SA1_QUAD1_CLK_MONITOR_DELAY_REG
35295 #define CGTS_SA1_QUAD1_CLK_MONITOR_DELAY_REG__OFF_MONITOR_DELAY__SHIFT                                        0x0
35296 #define CGTS_SA1_QUAD1_CLK_MONITOR_DELAY_REG__ON_MONITOR_DELAY__SHIFT                                         0xa
35297 #define CGTS_SA1_QUAD1_CLK_MONITOR_DELAY_REG__OFF_MONITOR_DELAY_MASK                                          0x000003FFL
35298 #define CGTS_SA1_QUAD1_CLK_MONITOR_DELAY_REG__ON_MONITOR_DELAY_MASK                                           0x0007FC00L
35299 //CGTS_RD_CTRL_REG
35300 #define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT                                                                  0x0
35301 #define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT                                                                  0x4
35302 #define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK                                                                    0x0000000FL
35303 #define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK                                                                    0x000000F0L
35304 //CGTS_RD_REG
35305 #define CGTS_RD_REG__READ_DATA__SHIFT                                                                         0x0
35306 #define CGTS_RD_REG__READ_DATA_MASK                                                                           0xFFFFFFFFL
35307 //CGTS_TCC_DISABLE
35308 #define CGTS_TCC_DISABLE__HI_TCC_DISABLE__SHIFT                                                               0x8
35309 #define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT                                                                  0x10
35310 #define CGTS_TCC_DISABLE__HI_TCC_DISABLE_MASK                                                                 0x0000FF00L
35311 #define CGTS_TCC_DISABLE__TCC_DISABLE_MASK                                                                    0xFFFF0000L
35312 //CGTS_USER_TCC_DISABLE
35313 #define CGTS_USER_TCC_DISABLE__HI_TCC_DISABLE__SHIFT                                                          0x8
35314 #define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT                                                             0x10
35315 #define CGTS_USER_TCC_DISABLE__HI_TCC_DISABLE_MASK                                                            0x0000FF00L
35316 #define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK                                                               0xFFFF0000L
35317 //CGTS_STATUS_REG
35318 #define CGTS_STATUS_REG__SA0_QUAD0_MGCG_ENABLED__SHIFT                                                        0x0
35319 #define CGTS_STATUS_REG__SA0_QUAD0_CG_STATUS__SHIFT                                                           0x1
35320 #define CGTS_STATUS_REG__SA0_QUAD1_MGCG_ENABLED__SHIFT                                                        0x4
35321 #define CGTS_STATUS_REG__SA0_QUAD1_CG_STATUS__SHIFT                                                           0x5
35322 #define CGTS_STATUS_REG__SA1_QUAD0_MGCG_ENABLED__SHIFT                                                        0x8
35323 #define CGTS_STATUS_REG__SA1_QUAD0_CG_STATUS__SHIFT                                                           0x9
35324 #define CGTS_STATUS_REG__SA1_QUAD1_MGCG_ENABLED__SHIFT                                                        0xc
35325 #define CGTS_STATUS_REG__SA1_QUAD1_CG_STATUS__SHIFT                                                           0xd
35326 #define CGTS_STATUS_REG__SA0_QUAD0_MGCG_ENABLED_MASK                                                          0x00000001L
35327 #define CGTS_STATUS_REG__SA0_QUAD0_CG_STATUS_MASK                                                             0x00000006L
35328 #define CGTS_STATUS_REG__SA0_QUAD1_MGCG_ENABLED_MASK                                                          0x00000010L
35329 #define CGTS_STATUS_REG__SA0_QUAD1_CG_STATUS_MASK                                                             0x00000060L
35330 #define CGTS_STATUS_REG__SA1_QUAD0_MGCG_ENABLED_MASK                                                          0x00000100L
35331 #define CGTS_STATUS_REG__SA1_QUAD0_CG_STATUS_MASK                                                             0x00000600L
35332 #define CGTS_STATUS_REG__SA1_QUAD1_MGCG_ENABLED_MASK                                                          0x00001000L
35333 #define CGTS_STATUS_REG__SA1_QUAD1_CG_STATUS_MASK                                                             0x00006000L
35334 //CGTT_SPI_CGTSSM_CLK_CTRL
35335 #define CGTT_SPI_CGTSSM_CLK_CTRL__GRP3_OVERRIDE__SHIFT                                                        0x1b
35336 #define CGTT_SPI_CGTSSM_CLK_CTRL__GRP2_OVERRIDE__SHIFT                                                        0x1c
35337 #define CGTT_SPI_CGTSSM_CLK_CTRL__GRP1_OVERRIDE__SHIFT                                                        0x1d
35338 #define CGTT_SPI_CGTSSM_CLK_CTRL__GRP0_OVERRIDE__SHIFT                                                        0x1e
35339 #define CGTT_SPI_CGTSSM_CLK_CTRL__GRP3_OVERRIDE_MASK                                                          0x08000000L
35340 #define CGTT_SPI_CGTSSM_CLK_CTRL__GRP2_OVERRIDE_MASK                                                          0x10000000L
35341 #define CGTT_SPI_CGTSSM_CLK_CTRL__GRP1_OVERRIDE_MASK                                                          0x20000000L
35342 #define CGTT_SPI_CGTSSM_CLK_CTRL__GRP0_OVERRIDE_MASK                                                          0x40000000L
35343 //CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG
35344 #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SIMD0__SHIFT                                                       0x0
35345 #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT                                              0x4
35346 #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT                                         0x5
35347 #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT                                           0x7
35348 #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
35349 #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQ0__SHIFT                                                         0xa
35350 #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT                                                0xe
35351 #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT                                           0xf
35352 #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT                                             0x11
35353 #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
35354 #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQC__SHIFT                                                         0x14
35355 #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE__SHIFT                                                0x18
35356 #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT                                           0x19
35357 #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE__SHIFT                                             0x1b
35358 #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT                                       0x1c
35359 #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_MASK                                                         0x0000000FL
35360 #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK                                                0x00000010L
35361 #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK                                           0x00000060L
35362 #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK                                             0x00000080L
35363 #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
35364 #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQ0_MASK                                                           0x00003C00L
35365 #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK                                                  0x00004000L
35366 #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK                                             0x00018000L
35367 #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK                                               0x00020000L
35368 #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
35369 #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQC_MASK                                                           0x00F00000L
35370 #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE_MASK                                                  0x01000000L
35371 #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE_MASK                                             0x06000000L
35372 #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE_MASK                                               0x08000000L
35373 #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK                                         0x10000000L
35374 //CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG
35375 #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SIMD1__SHIFT                                                       0x0
35376 #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT                                              0x4
35377 #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT                                         0x5
35378 #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT                                           0x7
35379 #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
35380 #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SQ1__SHIFT                                                         0xa
35381 #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT                                                0xe
35382 #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT                                           0xf
35383 #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT                                             0x11
35384 #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
35385 #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__LDS__SHIFT                                                         0x14
35386 #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE__SHIFT                                                0x18
35387 #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                           0x19
35388 #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                             0x1b
35389 #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                       0x1c
35390 #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_MASK                                                         0x0000000FL
35391 #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK                                                0x00000010L
35392 #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK                                           0x00000060L
35393 #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK                                             0x00000080L
35394 #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
35395 #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SQ1_MASK                                                           0x00003C00L
35396 #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK                                                  0x00004000L
35397 #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK                                             0x00018000L
35398 #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK                                               0x00020000L
35399 #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
35400 #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__LDS_MASK                                                           0x00F00000L
35401 #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE_MASK                                                  0x01000000L
35402 #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                             0x06000000L
35403 #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE_MASK                                               0x08000000L
35404 #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                         0x10000000L
35405 //CGTS_SA0_WGP00_CU0_TATD_CTRL_REG
35406 #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TA__SHIFT                                                           0x0
35407 #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TA_OVERRIDE__SHIFT                                                  0x4
35408 #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                             0x5
35409 #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                               0x7
35410 #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                         0x8
35411 #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TD__SHIFT                                                           0xa
35412 #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TD_OVERRIDE__SHIFT                                                  0xe
35413 #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                             0xf
35414 #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                               0x11
35415 #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                         0x12
35416 #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TA_MASK                                                             0x0000000FL
35417 #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TA_OVERRIDE_MASK                                                    0x00000010L
35418 #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                               0x00000060L
35419 #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK                                                 0x00000080L
35420 #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                           0x00000100L
35421 #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TD_MASK                                                             0x00003C00L
35422 #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TD_OVERRIDE_MASK                                                    0x00004000L
35423 #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                               0x00018000L
35424 #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK                                                 0x00020000L
35425 #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                           0x00040000L
35426 //CGTS_SA0_WGP00_CU0_TCP_CTRL_REG
35427 #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPF__SHIFT                                                          0x0
35428 #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                 0x4
35429 #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                            0x5
35430 #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                              0x7
35431 #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                        0x8
35432 #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI__SHIFT                                                          0xa
35433 #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                 0xe
35434 #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                            0xf
35435 #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                              0x11
35436 #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                        0x12
35437 #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPF_MASK                                                            0x0000000FL
35438 #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                   0x00000010L
35439 #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                              0x00000060L
35440 #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                0x00000080L
35441 #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                          0x00000100L
35442 #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_MASK                                                            0x00003C00L
35443 #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_OVERRIDE_MASK                                                   0x00004000L
35444 #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                              0x00018000L
35445 #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                0x00020000L
35446 #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                          0x00040000L
35447 //CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG
35448 #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SIMD0__SHIFT                                                       0x0
35449 #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT                                              0x4
35450 #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT                                         0x5
35451 #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT                                           0x7
35452 #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
35453 #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SQ0__SHIFT                                                         0xa
35454 #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT                                                0xe
35455 #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT                                           0xf
35456 #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT                                             0x11
35457 #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
35458 #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_MASK                                                         0x0000000FL
35459 #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK                                                0x00000010L
35460 #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK                                           0x00000060L
35461 #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK                                             0x00000080L
35462 #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
35463 #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SQ0_MASK                                                           0x00003C00L
35464 #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK                                                  0x00004000L
35465 #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK                                             0x00018000L
35466 #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK                                               0x00020000L
35467 #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
35468 //CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG
35469 #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SIMD1__SHIFT                                                       0x0
35470 #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT                                              0x4
35471 #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT                                         0x5
35472 #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT                                           0x7
35473 #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
35474 #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SQ1__SHIFT                                                         0xa
35475 #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT                                                0xe
35476 #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT                                           0xf
35477 #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT                                             0x11
35478 #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
35479 #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_MASK                                                         0x0000000FL
35480 #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK                                                0x00000010L
35481 #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK                                           0x00000060L
35482 #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK                                             0x00000080L
35483 #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
35484 #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SQ1_MASK                                                           0x00003C00L
35485 #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK                                                  0x00004000L
35486 #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK                                             0x00018000L
35487 #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK                                               0x00020000L
35488 #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
35489 //CGTS_SA0_WGP00_CU1_TATD_CTRL_REG
35490 #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TA__SHIFT                                                           0x0
35491 #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TA_OVERRIDE__SHIFT                                                  0x4
35492 #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                             0x5
35493 #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                               0x7
35494 #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                         0x8
35495 #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TD__SHIFT                                                           0xa
35496 #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TD_OVERRIDE__SHIFT                                                  0xe
35497 #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                             0xf
35498 #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                               0x11
35499 #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                         0x12
35500 #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TA_MASK                                                             0x0000000FL
35501 #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TA_OVERRIDE_MASK                                                    0x00000010L
35502 #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                               0x00000060L
35503 #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK                                                 0x00000080L
35504 #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                           0x00000100L
35505 #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TD_MASK                                                             0x00003C00L
35506 #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TD_OVERRIDE_MASK                                                    0x00004000L
35507 #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                               0x00018000L
35508 #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK                                                 0x00020000L
35509 #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                           0x00040000L
35510 //CGTS_SA0_WGP00_CU1_TCP_CTRL_REG
35511 #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPF__SHIFT                                                          0x0
35512 #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                 0x4
35513 #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                            0x5
35514 #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                              0x7
35515 #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                        0x8
35516 #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPI__SHIFT                                                          0xa
35517 #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                 0xe
35518 #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                            0xf
35519 #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                              0x11
35520 #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                        0x12
35521 #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPF_MASK                                                            0x0000000FL
35522 #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                   0x00000010L
35523 #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                              0x00000060L
35524 #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                0x00000080L
35525 #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                          0x00000100L
35526 #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPI_MASK                                                            0x00003C00L
35527 #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPI_OVERRIDE_MASK                                                   0x00004000L
35528 #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                              0x00018000L
35529 #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                0x00020000L
35530 #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                          0x00040000L
35531 //CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG
35532 #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SIMD0__SHIFT                                                       0x0
35533 #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT                                              0x4
35534 #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT                                         0x5
35535 #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT                                           0x7
35536 #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
35537 #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQ0__SHIFT                                                         0xa
35538 #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT                                                0xe
35539 #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT                                           0xf
35540 #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT                                             0x11
35541 #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
35542 #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQC__SHIFT                                                         0x14
35543 #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE__SHIFT                                                0x18
35544 #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT                                           0x19
35545 #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE__SHIFT                                             0x1b
35546 #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT                                       0x1c
35547 #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_MASK                                                         0x0000000FL
35548 #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK                                                0x00000010L
35549 #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK                                           0x00000060L
35550 #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK                                             0x00000080L
35551 #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
35552 #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQ0_MASK                                                           0x00003C00L
35553 #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK                                                  0x00004000L
35554 #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK                                             0x00018000L
35555 #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK                                               0x00020000L
35556 #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
35557 #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQC_MASK                                                           0x00F00000L
35558 #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE_MASK                                                  0x01000000L
35559 #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE_MASK                                             0x06000000L
35560 #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE_MASK                                               0x08000000L
35561 #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK                                         0x10000000L
35562 //CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG
35563 #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SIMD1__SHIFT                                                       0x0
35564 #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT                                              0x4
35565 #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT                                         0x5
35566 #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT                                           0x7
35567 #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
35568 #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SQ1__SHIFT                                                         0xa
35569 #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT                                                0xe
35570 #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT                                           0xf
35571 #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT                                             0x11
35572 #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
35573 #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__LDS__SHIFT                                                         0x14
35574 #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE__SHIFT                                                0x18
35575 #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                           0x19
35576 #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                             0x1b
35577 #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                       0x1c
35578 #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_MASK                                                         0x0000000FL
35579 #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK                                                0x00000010L
35580 #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK                                           0x00000060L
35581 #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK                                             0x00000080L
35582 #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
35583 #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SQ1_MASK                                                           0x00003C00L
35584 #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK                                                  0x00004000L
35585 #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK                                             0x00018000L
35586 #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK                                               0x00020000L
35587 #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
35588 #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__LDS_MASK                                                           0x00F00000L
35589 #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE_MASK                                                  0x01000000L
35590 #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                             0x06000000L
35591 #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE_MASK                                               0x08000000L
35592 #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                         0x10000000L
35593 //CGTS_SA0_WGP01_CU0_TATD_CTRL_REG
35594 #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TA__SHIFT                                                           0x0
35595 #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TA_OVERRIDE__SHIFT                                                  0x4
35596 #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                             0x5
35597 #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                               0x7
35598 #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                         0x8
35599 #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TD__SHIFT                                                           0xa
35600 #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TD_OVERRIDE__SHIFT                                                  0xe
35601 #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                             0xf
35602 #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                               0x11
35603 #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                         0x12
35604 #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TA_MASK                                                             0x0000000FL
35605 #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TA_OVERRIDE_MASK                                                    0x00000010L
35606 #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                               0x00000060L
35607 #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK                                                 0x00000080L
35608 #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                           0x00000100L
35609 #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TD_MASK                                                             0x00003C00L
35610 #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TD_OVERRIDE_MASK                                                    0x00004000L
35611 #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                               0x00018000L
35612 #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK                                                 0x00020000L
35613 #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                           0x00040000L
35614 //CGTS_SA0_WGP01_CU0_TCP_CTRL_REG
35615 #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPF__SHIFT                                                          0x0
35616 #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                 0x4
35617 #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                            0x5
35618 #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                              0x7
35619 #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                        0x8
35620 #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPI__SHIFT                                                          0xa
35621 #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                 0xe
35622 #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                            0xf
35623 #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                              0x11
35624 #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                        0x12
35625 #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPF_MASK                                                            0x0000000FL
35626 #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                   0x00000010L
35627 #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                              0x00000060L
35628 #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                0x00000080L
35629 #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                          0x00000100L
35630 #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPI_MASK                                                            0x00003C00L
35631 #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPI_OVERRIDE_MASK                                                   0x00004000L
35632 #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                              0x00018000L
35633 #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                0x00020000L
35634 #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                          0x00040000L
35635 //CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG
35636 #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SIMD0__SHIFT                                                       0x0
35637 #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT                                              0x4
35638 #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT                                         0x5
35639 #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT                                           0x7
35640 #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
35641 #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SQ0__SHIFT                                                         0xa
35642 #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT                                                0xe
35643 #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT                                           0xf
35644 #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT                                             0x11
35645 #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
35646 #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_MASK                                                         0x0000000FL
35647 #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK                                                0x00000010L
35648 #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK                                           0x00000060L
35649 #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK                                             0x00000080L
35650 #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
35651 #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SQ0_MASK                                                           0x00003C00L
35652 #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK                                                  0x00004000L
35653 #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK                                             0x00018000L
35654 #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK                                               0x00020000L
35655 #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
35656 //CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG
35657 #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SIMD1__SHIFT                                                       0x0
35658 #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT                                              0x4
35659 #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT                                         0x5
35660 #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT                                           0x7
35661 #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
35662 #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SQ1__SHIFT                                                         0xa
35663 #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT                                                0xe
35664 #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT                                           0xf
35665 #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT                                             0x11
35666 #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
35667 #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_MASK                                                         0x0000000FL
35668 #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK                                                0x00000010L
35669 #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK                                           0x00000060L
35670 #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK                                             0x00000080L
35671 #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
35672 #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SQ1_MASK                                                           0x00003C00L
35673 #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK                                                  0x00004000L
35674 #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK                                             0x00018000L
35675 #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK                                               0x00020000L
35676 #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
35677 //CGTS_SA0_WGP01_CU1_TATD_CTRL_REG
35678 #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TA__SHIFT                                                           0x0
35679 #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TA_OVERRIDE__SHIFT                                                  0x4
35680 #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                             0x5
35681 #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                               0x7
35682 #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                         0x8
35683 #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TD__SHIFT                                                           0xa
35684 #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TD_OVERRIDE__SHIFT                                                  0xe
35685 #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                             0xf
35686 #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                               0x11
35687 #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                         0x12
35688 #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TA_MASK                                                             0x0000000FL
35689 #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TA_OVERRIDE_MASK                                                    0x00000010L
35690 #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                               0x00000060L
35691 #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK                                                 0x00000080L
35692 #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                           0x00000100L
35693 #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TD_MASK                                                             0x00003C00L
35694 #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TD_OVERRIDE_MASK                                                    0x00004000L
35695 #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                               0x00018000L
35696 #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK                                                 0x00020000L
35697 #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                           0x00040000L
35698 //CGTS_SA0_WGP01_CU1_TCP_CTRL_REG
35699 #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPF__SHIFT                                                          0x0
35700 #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                 0x4
35701 #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                            0x5
35702 #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                              0x7
35703 #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                        0x8
35704 #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPI__SHIFT                                                          0xa
35705 #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                 0xe
35706 #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                            0xf
35707 #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                              0x11
35708 #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                        0x12
35709 #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPF_MASK                                                            0x0000000FL
35710 #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                   0x00000010L
35711 #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                              0x00000060L
35712 #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                0x00000080L
35713 #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                          0x00000100L
35714 #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPI_MASK                                                            0x00003C00L
35715 #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPI_OVERRIDE_MASK                                                   0x00004000L
35716 #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                              0x00018000L
35717 #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                0x00020000L
35718 #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                          0x00040000L
35719 //CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG
35720 #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SIMD0__SHIFT                                                       0x0
35721 #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT                                              0x4
35722 #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT                                         0x5
35723 #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT                                           0x7
35724 #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
35725 #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQ0__SHIFT                                                         0xa
35726 #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT                                                0xe
35727 #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT                                           0xf
35728 #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT                                             0x11
35729 #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
35730 #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQC__SHIFT                                                         0x14
35731 #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE__SHIFT                                                0x18
35732 #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT                                           0x19
35733 #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE__SHIFT                                             0x1b
35734 #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT                                       0x1c
35735 #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_MASK                                                         0x0000000FL
35736 #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK                                                0x00000010L
35737 #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK                                           0x00000060L
35738 #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK                                             0x00000080L
35739 #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
35740 #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQ0_MASK                                                           0x00003C00L
35741 #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK                                                  0x00004000L
35742 #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK                                             0x00018000L
35743 #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK                                               0x00020000L
35744 #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
35745 #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQC_MASK                                                           0x00F00000L
35746 #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE_MASK                                                  0x01000000L
35747 #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE_MASK                                             0x06000000L
35748 #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE_MASK                                               0x08000000L
35749 #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK                                         0x10000000L
35750 //CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG
35751 #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SIMD1__SHIFT                                                       0x0
35752 #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT                                              0x4
35753 #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT                                         0x5
35754 #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT                                           0x7
35755 #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
35756 #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SQ1__SHIFT                                                         0xa
35757 #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT                                                0xe
35758 #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT                                           0xf
35759 #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT                                             0x11
35760 #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
35761 #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__LDS__SHIFT                                                         0x14
35762 #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE__SHIFT                                                0x18
35763 #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                           0x19
35764 #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                             0x1b
35765 #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                       0x1c
35766 #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_MASK                                                         0x0000000FL
35767 #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK                                                0x00000010L
35768 #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK                                           0x00000060L
35769 #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK                                             0x00000080L
35770 #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
35771 #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SQ1_MASK                                                           0x00003C00L
35772 #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK                                                  0x00004000L
35773 #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK                                             0x00018000L
35774 #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK                                               0x00020000L
35775 #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
35776 #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__LDS_MASK                                                           0x00F00000L
35777 #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE_MASK                                                  0x01000000L
35778 #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                             0x06000000L
35779 #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE_MASK                                               0x08000000L
35780 #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                         0x10000000L
35781 //CGTS_SA0_WGP02_CU0_TATD_CTRL_REG
35782 #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TA__SHIFT                                                           0x0
35783 #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TA_OVERRIDE__SHIFT                                                  0x4
35784 #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                             0x5
35785 #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                               0x7
35786 #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                         0x8
35787 #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TD__SHIFT                                                           0xa
35788 #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TD_OVERRIDE__SHIFT                                                  0xe
35789 #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                             0xf
35790 #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                               0x11
35791 #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                         0x12
35792 #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TA_MASK                                                             0x0000000FL
35793 #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TA_OVERRIDE_MASK                                                    0x00000010L
35794 #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                               0x00000060L
35795 #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK                                                 0x00000080L
35796 #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                           0x00000100L
35797 #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TD_MASK                                                             0x00003C00L
35798 #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TD_OVERRIDE_MASK                                                    0x00004000L
35799 #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                               0x00018000L
35800 #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK                                                 0x00020000L
35801 #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                           0x00040000L
35802 //CGTS_SA0_WGP02_CU0_TCP_CTRL_REG
35803 #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPF__SHIFT                                                          0x0
35804 #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                 0x4
35805 #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                            0x5
35806 #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                              0x7
35807 #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                        0x8
35808 #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPI__SHIFT                                                          0xa
35809 #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                 0xe
35810 #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                            0xf
35811 #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                              0x11
35812 #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                        0x12
35813 #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPF_MASK                                                            0x0000000FL
35814 #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                   0x00000010L
35815 #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                              0x00000060L
35816 #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                0x00000080L
35817 #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                          0x00000100L
35818 #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPI_MASK                                                            0x00003C00L
35819 #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPI_OVERRIDE_MASK                                                   0x00004000L
35820 #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                              0x00018000L
35821 #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                0x00020000L
35822 #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                          0x00040000L
35823 //CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG
35824 #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SIMD0__SHIFT                                                       0x0
35825 #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT                                              0x4
35826 #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT                                         0x5
35827 #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT                                           0x7
35828 #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
35829 #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SQ0__SHIFT                                                         0xa
35830 #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT                                                0xe
35831 #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT                                           0xf
35832 #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT                                             0x11
35833 #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
35834 #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_MASK                                                         0x0000000FL
35835 #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK                                                0x00000010L
35836 #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK                                           0x00000060L
35837 #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK                                             0x00000080L
35838 #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
35839 #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SQ0_MASK                                                           0x00003C00L
35840 #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK                                                  0x00004000L
35841 #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK                                             0x00018000L
35842 #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK                                               0x00020000L
35843 #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
35844 //CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG
35845 #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SIMD1__SHIFT                                                       0x0
35846 #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT                                              0x4
35847 #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT                                         0x5
35848 #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT                                           0x7
35849 #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
35850 #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SQ1__SHIFT                                                         0xa
35851 #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT                                                0xe
35852 #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT                                           0xf
35853 #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT                                             0x11
35854 #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
35855 #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_MASK                                                         0x0000000FL
35856 #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK                                                0x00000010L
35857 #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK                                           0x00000060L
35858 #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK                                             0x00000080L
35859 #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
35860 #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SQ1_MASK                                                           0x00003C00L
35861 #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK                                                  0x00004000L
35862 #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK                                             0x00018000L
35863 #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK                                               0x00020000L
35864 #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
35865 //CGTS_SA0_WGP02_CU1_TATD_CTRL_REG
35866 #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TA__SHIFT                                                           0x0
35867 #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TA_OVERRIDE__SHIFT                                                  0x4
35868 #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                             0x5
35869 #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                               0x7
35870 #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                         0x8
35871 #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TD__SHIFT                                                           0xa
35872 #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TD_OVERRIDE__SHIFT                                                  0xe
35873 #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                             0xf
35874 #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                               0x11
35875 #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                         0x12
35876 #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TA_MASK                                                             0x0000000FL
35877 #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TA_OVERRIDE_MASK                                                    0x00000010L
35878 #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                               0x00000060L
35879 #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK                                                 0x00000080L
35880 #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                           0x00000100L
35881 #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TD_MASK                                                             0x00003C00L
35882 #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TD_OVERRIDE_MASK                                                    0x00004000L
35883 #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                               0x00018000L
35884 #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK                                                 0x00020000L
35885 #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                           0x00040000L
35886 //CGTS_SA0_WGP02_CU1_TCP_CTRL_REG
35887 #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPF__SHIFT                                                          0x0
35888 #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                 0x4
35889 #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                            0x5
35890 #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                              0x7
35891 #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                        0x8
35892 #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPI__SHIFT                                                          0xa
35893 #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                 0xe
35894 #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                            0xf
35895 #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                              0x11
35896 #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                        0x12
35897 #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPF_MASK                                                            0x0000000FL
35898 #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                   0x00000010L
35899 #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                              0x00000060L
35900 #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                0x00000080L
35901 #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                          0x00000100L
35902 #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPI_MASK                                                            0x00003C00L
35903 #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPI_OVERRIDE_MASK                                                   0x00004000L
35904 #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                              0x00018000L
35905 #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                0x00020000L
35906 #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                          0x00040000L
35907 //CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG
35908 #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SIMD0__SHIFT                                                       0x0
35909 #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT                                              0x4
35910 #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT                                         0x5
35911 #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT                                           0x7
35912 #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
35913 #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQ0__SHIFT                                                         0xa
35914 #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT                                                0xe
35915 #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT                                           0xf
35916 #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT                                             0x11
35917 #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
35918 #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQC__SHIFT                                                         0x14
35919 #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE__SHIFT                                                0x18
35920 #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT                                           0x19
35921 #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE__SHIFT                                             0x1b
35922 #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT                                       0x1c
35923 #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_MASK                                                         0x0000000FL
35924 #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK                                                0x00000010L
35925 #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK                                           0x00000060L
35926 #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK                                             0x00000080L
35927 #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
35928 #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQ0_MASK                                                           0x00003C00L
35929 #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK                                                  0x00004000L
35930 #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK                                             0x00018000L
35931 #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK                                               0x00020000L
35932 #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
35933 #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQC_MASK                                                           0x00F00000L
35934 #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE_MASK                                                  0x01000000L
35935 #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE_MASK                                             0x06000000L
35936 #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE_MASK                                               0x08000000L
35937 #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK                                         0x10000000L
35938 //CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG
35939 #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SIMD1__SHIFT                                                       0x0
35940 #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT                                              0x4
35941 #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT                                         0x5
35942 #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT                                           0x7
35943 #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
35944 #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SQ1__SHIFT                                                         0xa
35945 #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT                                                0xe
35946 #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT                                           0xf
35947 #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT                                             0x11
35948 #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
35949 #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__LDS__SHIFT                                                         0x14
35950 #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE__SHIFT                                                0x18
35951 #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                           0x19
35952 #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                             0x1b
35953 #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                       0x1c
35954 #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_MASK                                                         0x0000000FL
35955 #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK                                                0x00000010L
35956 #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK                                           0x00000060L
35957 #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK                                             0x00000080L
35958 #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
35959 #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SQ1_MASK                                                           0x00003C00L
35960 #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK                                                  0x00004000L
35961 #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK                                             0x00018000L
35962 #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK                                               0x00020000L
35963 #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
35964 #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__LDS_MASK                                                           0x00F00000L
35965 #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE_MASK                                                  0x01000000L
35966 #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                             0x06000000L
35967 #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE_MASK                                               0x08000000L
35968 #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                         0x10000000L
35969 //CGTS_SA0_WGP10_CU0_TATD_CTRL_REG
35970 #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TA__SHIFT                                                           0x0
35971 #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TA_OVERRIDE__SHIFT                                                  0x4
35972 #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                             0x5
35973 #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                               0x7
35974 #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                         0x8
35975 #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TD__SHIFT                                                           0xa
35976 #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TD_OVERRIDE__SHIFT                                                  0xe
35977 #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                             0xf
35978 #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                               0x11
35979 #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                         0x12
35980 #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TA_MASK                                                             0x0000000FL
35981 #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TA_OVERRIDE_MASK                                                    0x00000010L
35982 #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                               0x00000060L
35983 #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK                                                 0x00000080L
35984 #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                           0x00000100L
35985 #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TD_MASK                                                             0x00003C00L
35986 #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TD_OVERRIDE_MASK                                                    0x00004000L
35987 #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                               0x00018000L
35988 #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK                                                 0x00020000L
35989 #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                           0x00040000L
35990 //CGTS_SA0_WGP10_CU0_TCP_CTRL_REG
35991 #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPF__SHIFT                                                          0x0
35992 #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                 0x4
35993 #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                            0x5
35994 #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                              0x7
35995 #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                        0x8
35996 #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPI__SHIFT                                                          0xa
35997 #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                 0xe
35998 #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                            0xf
35999 #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                              0x11
36000 #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                        0x12
36001 #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPF_MASK                                                            0x0000000FL
36002 #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                   0x00000010L
36003 #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                              0x00000060L
36004 #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                0x00000080L
36005 #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                          0x00000100L
36006 #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPI_MASK                                                            0x00003C00L
36007 #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPI_OVERRIDE_MASK                                                   0x00004000L
36008 #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                              0x00018000L
36009 #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                0x00020000L
36010 #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                          0x00040000L
36011 //CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG
36012 #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SIMD0__SHIFT                                                       0x0
36013 #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT                                              0x4
36014 #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT                                         0x5
36015 #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT                                           0x7
36016 #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
36017 #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SQ0__SHIFT                                                         0xa
36018 #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT                                                0xe
36019 #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT                                           0xf
36020 #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT                                             0x11
36021 #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
36022 #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_MASK                                                         0x0000000FL
36023 #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK                                                0x00000010L
36024 #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK                                           0x00000060L
36025 #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK                                             0x00000080L
36026 #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
36027 #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SQ0_MASK                                                           0x00003C00L
36028 #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK                                                  0x00004000L
36029 #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK                                             0x00018000L
36030 #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK                                               0x00020000L
36031 #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
36032 //CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG
36033 #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SIMD1__SHIFT                                                       0x0
36034 #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT                                              0x4
36035 #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT                                         0x5
36036 #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT                                           0x7
36037 #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
36038 #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SQ1__SHIFT                                                         0xa
36039 #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT                                                0xe
36040 #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT                                           0xf
36041 #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT                                             0x11
36042 #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
36043 #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_MASK                                                         0x0000000FL
36044 #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK                                                0x00000010L
36045 #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK                                           0x00000060L
36046 #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK                                             0x00000080L
36047 #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
36048 #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SQ1_MASK                                                           0x00003C00L
36049 #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK                                                  0x00004000L
36050 #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK                                             0x00018000L
36051 #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK                                               0x00020000L
36052 #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
36053 //CGTS_SA0_WGP10_CU1_TATD_CTRL_REG
36054 #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TA__SHIFT                                                           0x0
36055 #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TA_OVERRIDE__SHIFT                                                  0x4
36056 #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                             0x5
36057 #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                               0x7
36058 #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                         0x8
36059 #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TD__SHIFT                                                           0xa
36060 #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TD_OVERRIDE__SHIFT                                                  0xe
36061 #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                             0xf
36062 #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                               0x11
36063 #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                         0x12
36064 #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TA_MASK                                                             0x0000000FL
36065 #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TA_OVERRIDE_MASK                                                    0x00000010L
36066 #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                               0x00000060L
36067 #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK                                                 0x00000080L
36068 #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                           0x00000100L
36069 #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TD_MASK                                                             0x00003C00L
36070 #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TD_OVERRIDE_MASK                                                    0x00004000L
36071 #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                               0x00018000L
36072 #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK                                                 0x00020000L
36073 #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                           0x00040000L
36074 //CGTS_SA0_WGP10_CU1_TCP_CTRL_REG
36075 #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPF__SHIFT                                                          0x0
36076 #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                 0x4
36077 #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                            0x5
36078 #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                              0x7
36079 #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                        0x8
36080 #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPI__SHIFT                                                          0xa
36081 #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                 0xe
36082 #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                            0xf
36083 #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                              0x11
36084 #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                        0x12
36085 #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPF_MASK                                                            0x0000000FL
36086 #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                   0x00000010L
36087 #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                              0x00000060L
36088 #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                0x00000080L
36089 #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                          0x00000100L
36090 #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPI_MASK                                                            0x00003C00L
36091 #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPI_OVERRIDE_MASK                                                   0x00004000L
36092 #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                              0x00018000L
36093 #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                0x00020000L
36094 #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                          0x00040000L
36095 //CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG
36096 #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SIMD0__SHIFT                                                       0x0
36097 #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT                                              0x4
36098 #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT                                         0x5
36099 #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT                                           0x7
36100 #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
36101 #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQ0__SHIFT                                                         0xa
36102 #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT                                                0xe
36103 #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT                                           0xf
36104 #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT                                             0x11
36105 #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
36106 #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQC__SHIFT                                                         0x14
36107 #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE__SHIFT                                                0x18
36108 #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT                                           0x19
36109 #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE__SHIFT                                             0x1b
36110 #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT                                       0x1c
36111 #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_MASK                                                         0x0000000FL
36112 #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK                                                0x00000010L
36113 #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK                                           0x00000060L
36114 #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK                                             0x00000080L
36115 #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
36116 #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQ0_MASK                                                           0x00003C00L
36117 #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK                                                  0x00004000L
36118 #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK                                             0x00018000L
36119 #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK                                               0x00020000L
36120 #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
36121 #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQC_MASK                                                           0x00F00000L
36122 #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE_MASK                                                  0x01000000L
36123 #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE_MASK                                             0x06000000L
36124 #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE_MASK                                               0x08000000L
36125 #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK                                         0x10000000L
36126 //CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG
36127 #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SIMD1__SHIFT                                                       0x0
36128 #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT                                              0x4
36129 #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT                                         0x5
36130 #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT                                           0x7
36131 #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
36132 #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SQ1__SHIFT                                                         0xa
36133 #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT                                                0xe
36134 #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT                                           0xf
36135 #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT                                             0x11
36136 #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
36137 #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__LDS__SHIFT                                                         0x14
36138 #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE__SHIFT                                                0x18
36139 #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                           0x19
36140 #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                             0x1b
36141 #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                       0x1c
36142 #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_MASK                                                         0x0000000FL
36143 #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK                                                0x00000010L
36144 #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK                                           0x00000060L
36145 #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK                                             0x00000080L
36146 #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
36147 #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SQ1_MASK                                                           0x00003C00L
36148 #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK                                                  0x00004000L
36149 #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK                                             0x00018000L
36150 #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK                                               0x00020000L
36151 #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
36152 #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__LDS_MASK                                                           0x00F00000L
36153 #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE_MASK                                                  0x01000000L
36154 #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                             0x06000000L
36155 #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE_MASK                                               0x08000000L
36156 #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                         0x10000000L
36157 //CGTS_SA0_WGP11_CU0_TATD_CTRL_REG
36158 #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TA__SHIFT                                                           0x0
36159 #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TA_OVERRIDE__SHIFT                                                  0x4
36160 #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                             0x5
36161 #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                               0x7
36162 #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                         0x8
36163 #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TD__SHIFT                                                           0xa
36164 #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TD_OVERRIDE__SHIFT                                                  0xe
36165 #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                             0xf
36166 #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                               0x11
36167 #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                         0x12
36168 #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TA_MASK                                                             0x0000000FL
36169 #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TA_OVERRIDE_MASK                                                    0x00000010L
36170 #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                               0x00000060L
36171 #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK                                                 0x00000080L
36172 #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                           0x00000100L
36173 #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TD_MASK                                                             0x00003C00L
36174 #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TD_OVERRIDE_MASK                                                    0x00004000L
36175 #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                               0x00018000L
36176 #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK                                                 0x00020000L
36177 #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                           0x00040000L
36178 //CGTS_SA0_WGP11_CU0_TCP_CTRL_REG
36179 #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPF__SHIFT                                                          0x0
36180 #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                 0x4
36181 #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                            0x5
36182 #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                              0x7
36183 #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                        0x8
36184 #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPI__SHIFT                                                          0xa
36185 #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                 0xe
36186 #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                            0xf
36187 #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                              0x11
36188 #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                        0x12
36189 #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPF_MASK                                                            0x0000000FL
36190 #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                   0x00000010L
36191 #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                              0x00000060L
36192 #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                0x00000080L
36193 #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                          0x00000100L
36194 #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPI_MASK                                                            0x00003C00L
36195 #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPI_OVERRIDE_MASK                                                   0x00004000L
36196 #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                              0x00018000L
36197 #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                0x00020000L
36198 #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                          0x00040000L
36199 //CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG
36200 #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SIMD0__SHIFT                                                       0x0
36201 #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT                                              0x4
36202 #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT                                         0x5
36203 #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT                                           0x7
36204 #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
36205 #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SQ0__SHIFT                                                         0xa
36206 #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT                                                0xe
36207 #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT                                           0xf
36208 #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT                                             0x11
36209 #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
36210 #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_MASK                                                         0x0000000FL
36211 #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK                                                0x00000010L
36212 #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK                                           0x00000060L
36213 #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK                                             0x00000080L
36214 #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
36215 #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SQ0_MASK                                                           0x00003C00L
36216 #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK                                                  0x00004000L
36217 #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK                                             0x00018000L
36218 #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK                                               0x00020000L
36219 #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
36220 //CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG
36221 #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SIMD1__SHIFT                                                       0x0
36222 #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT                                              0x4
36223 #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT                                         0x5
36224 #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT                                           0x7
36225 #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
36226 #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SQ1__SHIFT                                                         0xa
36227 #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT                                                0xe
36228 #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT                                           0xf
36229 #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT                                             0x11
36230 #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
36231 #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_MASK                                                         0x0000000FL
36232 #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK                                                0x00000010L
36233 #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK                                           0x00000060L
36234 #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK                                             0x00000080L
36235 #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
36236 #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SQ1_MASK                                                           0x00003C00L
36237 #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK                                                  0x00004000L
36238 #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK                                             0x00018000L
36239 #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK                                               0x00020000L
36240 #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
36241 //CGTS_SA0_WGP11_CU1_TATD_CTRL_REG
36242 #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TA__SHIFT                                                           0x0
36243 #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TA_OVERRIDE__SHIFT                                                  0x4
36244 #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                             0x5
36245 #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                               0x7
36246 #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                         0x8
36247 #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TD__SHIFT                                                           0xa
36248 #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TD_OVERRIDE__SHIFT                                                  0xe
36249 #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                             0xf
36250 #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                               0x11
36251 #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                         0x12
36252 #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TA_MASK                                                             0x0000000FL
36253 #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TA_OVERRIDE_MASK                                                    0x00000010L
36254 #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                               0x00000060L
36255 #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK                                                 0x00000080L
36256 #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                           0x00000100L
36257 #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TD_MASK                                                             0x00003C00L
36258 #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TD_OVERRIDE_MASK                                                    0x00004000L
36259 #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                               0x00018000L
36260 #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK                                                 0x00020000L
36261 #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                           0x00040000L
36262 //CGTS_SA0_WGP11_CU1_TCP_CTRL_REG
36263 #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPF__SHIFT                                                          0x0
36264 #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                 0x4
36265 #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                            0x5
36266 #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                              0x7
36267 #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                        0x8
36268 #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPI__SHIFT                                                          0xa
36269 #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                 0xe
36270 #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                            0xf
36271 #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                              0x11
36272 #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                        0x12
36273 #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPF_MASK                                                            0x0000000FL
36274 #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                   0x00000010L
36275 #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                              0x00000060L
36276 #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                0x00000080L
36277 #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                          0x00000100L
36278 #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPI_MASK                                                            0x00003C00L
36279 #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPI_OVERRIDE_MASK                                                   0x00004000L
36280 #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                              0x00018000L
36281 #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                0x00020000L
36282 #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                          0x00040000L
36283 //CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG
36284 #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SIMD0__SHIFT                                                       0x0
36285 #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT                                              0x4
36286 #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT                                         0x5
36287 #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT                                           0x7
36288 #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
36289 #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQ0__SHIFT                                                         0xa
36290 #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT                                                0xe
36291 #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT                                           0xf
36292 #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT                                             0x11
36293 #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
36294 #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQC__SHIFT                                                         0x14
36295 #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE__SHIFT                                                0x18
36296 #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT                                           0x19
36297 #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE__SHIFT                                             0x1b
36298 #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT                                       0x1c
36299 #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_MASK                                                         0x0000000FL
36300 #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK                                                0x00000010L
36301 #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK                                           0x00000060L
36302 #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK                                             0x00000080L
36303 #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
36304 #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQ0_MASK                                                           0x00003C00L
36305 #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK                                                  0x00004000L
36306 #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK                                             0x00018000L
36307 #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK                                               0x00020000L
36308 #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
36309 #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQC_MASK                                                           0x00F00000L
36310 #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE_MASK                                                  0x01000000L
36311 #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE_MASK                                             0x06000000L
36312 #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE_MASK                                               0x08000000L
36313 #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK                                         0x10000000L
36314 //CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG
36315 #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SIMD1__SHIFT                                                       0x0
36316 #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT                                              0x4
36317 #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT                                         0x5
36318 #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT                                           0x7
36319 #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
36320 #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SQ1__SHIFT                                                         0xa
36321 #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT                                                0xe
36322 #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT                                           0xf
36323 #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT                                             0x11
36324 #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
36325 #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__LDS__SHIFT                                                         0x14
36326 #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE__SHIFT                                                0x18
36327 #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                           0x19
36328 #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                             0x1b
36329 #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                       0x1c
36330 #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_MASK                                                         0x0000000FL
36331 #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK                                                0x00000010L
36332 #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK                                           0x00000060L
36333 #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK                                             0x00000080L
36334 #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
36335 #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SQ1_MASK                                                           0x00003C00L
36336 #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK                                                  0x00004000L
36337 #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK                                             0x00018000L
36338 #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK                                               0x00020000L
36339 #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
36340 #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__LDS_MASK                                                           0x00F00000L
36341 #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE_MASK                                                  0x01000000L
36342 #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                             0x06000000L
36343 #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE_MASK                                               0x08000000L
36344 #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                         0x10000000L
36345 //CGTS_SA1_WGP00_CU0_TATD_CTRL_REG
36346 #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TA__SHIFT                                                           0x0
36347 #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TA_OVERRIDE__SHIFT                                                  0x4
36348 #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                             0x5
36349 #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                               0x7
36350 #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                         0x8
36351 #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TD__SHIFT                                                           0xa
36352 #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TD_OVERRIDE__SHIFT                                                  0xe
36353 #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                             0xf
36354 #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                               0x11
36355 #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                         0x12
36356 #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TA_MASK                                                             0x0000000FL
36357 #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TA_OVERRIDE_MASK                                                    0x00000010L
36358 #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                               0x00000060L
36359 #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK                                                 0x00000080L
36360 #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                           0x00000100L
36361 #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TD_MASK                                                             0x00003C00L
36362 #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TD_OVERRIDE_MASK                                                    0x00004000L
36363 #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                               0x00018000L
36364 #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK                                                 0x00020000L
36365 #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                           0x00040000L
36366 //CGTS_SA1_WGP00_CU0_TCP_CTRL_REG
36367 #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPF__SHIFT                                                          0x0
36368 #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                 0x4
36369 #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                            0x5
36370 #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                              0x7
36371 #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                        0x8
36372 #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPI__SHIFT                                                          0xa
36373 #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                 0xe
36374 #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                            0xf
36375 #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                              0x11
36376 #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                        0x12
36377 #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPF_MASK                                                            0x0000000FL
36378 #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                   0x00000010L
36379 #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                              0x00000060L
36380 #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                0x00000080L
36381 #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                          0x00000100L
36382 #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPI_MASK                                                            0x00003C00L
36383 #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPI_OVERRIDE_MASK                                                   0x00004000L
36384 #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                              0x00018000L
36385 #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                0x00020000L
36386 #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                          0x00040000L
36387 //CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG
36388 #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SIMD0__SHIFT                                                       0x0
36389 #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT                                              0x4
36390 #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT                                         0x5
36391 #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT                                           0x7
36392 #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
36393 #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SQ0__SHIFT                                                         0xa
36394 #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT                                                0xe
36395 #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT                                           0xf
36396 #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT                                             0x11
36397 #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
36398 #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_MASK                                                         0x0000000FL
36399 #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK                                                0x00000010L
36400 #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK                                           0x00000060L
36401 #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK                                             0x00000080L
36402 #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
36403 #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SQ0_MASK                                                           0x00003C00L
36404 #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK                                                  0x00004000L
36405 #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK                                             0x00018000L
36406 #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK                                               0x00020000L
36407 #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
36408 //CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG
36409 #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SIMD1__SHIFT                                                       0x0
36410 #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT                                              0x4
36411 #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT                                         0x5
36412 #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT                                           0x7
36413 #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
36414 #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SQ1__SHIFT                                                         0xa
36415 #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT                                                0xe
36416 #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT                                           0xf
36417 #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT                                             0x11
36418 #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
36419 #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_MASK                                                         0x0000000FL
36420 #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK                                                0x00000010L
36421 #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK                                           0x00000060L
36422 #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK                                             0x00000080L
36423 #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
36424 #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SQ1_MASK                                                           0x00003C00L
36425 #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK                                                  0x00004000L
36426 #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK                                             0x00018000L
36427 #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK                                               0x00020000L
36428 #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
36429 //CGTS_SA1_WGP00_CU1_TATD_CTRL_REG
36430 #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TA__SHIFT                                                           0x0
36431 #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TA_OVERRIDE__SHIFT                                                  0x4
36432 #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                             0x5
36433 #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                               0x7
36434 #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                         0x8
36435 #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TD__SHIFT                                                           0xa
36436 #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TD_OVERRIDE__SHIFT                                                  0xe
36437 #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                             0xf
36438 #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                               0x11
36439 #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                         0x12
36440 #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TA_MASK                                                             0x0000000FL
36441 #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TA_OVERRIDE_MASK                                                    0x00000010L
36442 #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                               0x00000060L
36443 #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK                                                 0x00000080L
36444 #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                           0x00000100L
36445 #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TD_MASK                                                             0x00003C00L
36446 #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TD_OVERRIDE_MASK                                                    0x00004000L
36447 #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                               0x00018000L
36448 #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK                                                 0x00020000L
36449 #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                           0x00040000L
36450 //CGTS_SA1_WGP00_CU1_TCP_CTRL_REG
36451 #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPF__SHIFT                                                          0x0
36452 #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                 0x4
36453 #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                            0x5
36454 #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                              0x7
36455 #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                        0x8
36456 #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPI__SHIFT                                                          0xa
36457 #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                 0xe
36458 #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                            0xf
36459 #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                              0x11
36460 #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                        0x12
36461 #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPF_MASK                                                            0x0000000FL
36462 #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                   0x00000010L
36463 #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                              0x00000060L
36464 #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                0x00000080L
36465 #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                          0x00000100L
36466 #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPI_MASK                                                            0x00003C00L
36467 #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPI_OVERRIDE_MASK                                                   0x00004000L
36468 #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                              0x00018000L
36469 #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                0x00020000L
36470 #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                          0x00040000L
36471 //CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG
36472 #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SIMD0__SHIFT                                                       0x0
36473 #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT                                              0x4
36474 #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT                                         0x5
36475 #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT                                           0x7
36476 #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
36477 #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQ0__SHIFT                                                         0xa
36478 #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT                                                0xe
36479 #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT                                           0xf
36480 #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT                                             0x11
36481 #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
36482 #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQC__SHIFT                                                         0x14
36483 #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE__SHIFT                                                0x18
36484 #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT                                           0x19
36485 #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE__SHIFT                                             0x1b
36486 #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT                                       0x1c
36487 #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_MASK                                                         0x0000000FL
36488 #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK                                                0x00000010L
36489 #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK                                           0x00000060L
36490 #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK                                             0x00000080L
36491 #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
36492 #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQ0_MASK                                                           0x00003C00L
36493 #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK                                                  0x00004000L
36494 #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK                                             0x00018000L
36495 #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK                                               0x00020000L
36496 #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
36497 #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQC_MASK                                                           0x00F00000L
36498 #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE_MASK                                                  0x01000000L
36499 #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE_MASK                                             0x06000000L
36500 #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE_MASK                                               0x08000000L
36501 #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK                                         0x10000000L
36502 //CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG
36503 #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SIMD1__SHIFT                                                       0x0
36504 #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT                                              0x4
36505 #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT                                         0x5
36506 #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT                                           0x7
36507 #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
36508 #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SQ1__SHIFT                                                         0xa
36509 #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT                                                0xe
36510 #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT                                           0xf
36511 #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT                                             0x11
36512 #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
36513 #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__LDS__SHIFT                                                         0x14
36514 #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE__SHIFT                                                0x18
36515 #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                           0x19
36516 #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                             0x1b
36517 #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                       0x1c
36518 #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_MASK                                                         0x0000000FL
36519 #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK                                                0x00000010L
36520 #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK                                           0x00000060L
36521 #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK                                             0x00000080L
36522 #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
36523 #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SQ1_MASK                                                           0x00003C00L
36524 #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK                                                  0x00004000L
36525 #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK                                             0x00018000L
36526 #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK                                               0x00020000L
36527 #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
36528 #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__LDS_MASK                                                           0x00F00000L
36529 #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE_MASK                                                  0x01000000L
36530 #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                             0x06000000L
36531 #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE_MASK                                               0x08000000L
36532 #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                         0x10000000L
36533 //CGTS_SA1_WGP01_CU0_TATD_CTRL_REG
36534 #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TA__SHIFT                                                           0x0
36535 #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TA_OVERRIDE__SHIFT                                                  0x4
36536 #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                             0x5
36537 #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                               0x7
36538 #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                         0x8
36539 #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TD__SHIFT                                                           0xa
36540 #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TD_OVERRIDE__SHIFT                                                  0xe
36541 #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                             0xf
36542 #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                               0x11
36543 #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                         0x12
36544 #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TA_MASK                                                             0x0000000FL
36545 #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TA_OVERRIDE_MASK                                                    0x00000010L
36546 #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                               0x00000060L
36547 #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK                                                 0x00000080L
36548 #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                           0x00000100L
36549 #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TD_MASK                                                             0x00003C00L
36550 #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TD_OVERRIDE_MASK                                                    0x00004000L
36551 #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                               0x00018000L
36552 #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK                                                 0x00020000L
36553 #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                           0x00040000L
36554 //CGTS_SA1_WGP01_CU0_TCP_CTRL_REG
36555 #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPF__SHIFT                                                          0x0
36556 #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                 0x4
36557 #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                            0x5
36558 #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                              0x7
36559 #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                        0x8
36560 #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPI__SHIFT                                                          0xa
36561 #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                 0xe
36562 #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                            0xf
36563 #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                              0x11
36564 #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                        0x12
36565 #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPF_MASK                                                            0x0000000FL
36566 #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                   0x00000010L
36567 #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                              0x00000060L
36568 #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                0x00000080L
36569 #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                          0x00000100L
36570 #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPI_MASK                                                            0x00003C00L
36571 #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPI_OVERRIDE_MASK                                                   0x00004000L
36572 #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                              0x00018000L
36573 #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                0x00020000L
36574 #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                          0x00040000L
36575 //CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG
36576 #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SIMD0__SHIFT                                                       0x0
36577 #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT                                              0x4
36578 #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT                                         0x5
36579 #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT                                           0x7
36580 #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
36581 #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SQ0__SHIFT                                                         0xa
36582 #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT                                                0xe
36583 #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT                                           0xf
36584 #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT                                             0x11
36585 #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
36586 #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_MASK                                                         0x0000000FL
36587 #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK                                                0x00000010L
36588 #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK                                           0x00000060L
36589 #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK                                             0x00000080L
36590 #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
36591 #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SQ0_MASK                                                           0x00003C00L
36592 #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK                                                  0x00004000L
36593 #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK                                             0x00018000L
36594 #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK                                               0x00020000L
36595 #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
36596 //CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG
36597 #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SIMD1__SHIFT                                                       0x0
36598 #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT                                              0x4
36599 #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT                                         0x5
36600 #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT                                           0x7
36601 #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
36602 #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SQ1__SHIFT                                                         0xa
36603 #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT                                                0xe
36604 #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT                                           0xf
36605 #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT                                             0x11
36606 #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
36607 #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_MASK                                                         0x0000000FL
36608 #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK                                                0x00000010L
36609 #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK                                           0x00000060L
36610 #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK                                             0x00000080L
36611 #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
36612 #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SQ1_MASK                                                           0x00003C00L
36613 #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK                                                  0x00004000L
36614 #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK                                             0x00018000L
36615 #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK                                               0x00020000L
36616 #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
36617 //CGTS_SA1_WGP01_CU1_TATD_CTRL_REG
36618 #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TA__SHIFT                                                           0x0
36619 #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TA_OVERRIDE__SHIFT                                                  0x4
36620 #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                             0x5
36621 #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                               0x7
36622 #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                         0x8
36623 #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TD__SHIFT                                                           0xa
36624 #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TD_OVERRIDE__SHIFT                                                  0xe
36625 #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                             0xf
36626 #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                               0x11
36627 #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                         0x12
36628 #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TA_MASK                                                             0x0000000FL
36629 #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TA_OVERRIDE_MASK                                                    0x00000010L
36630 #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                               0x00000060L
36631 #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK                                                 0x00000080L
36632 #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                           0x00000100L
36633 #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TD_MASK                                                             0x00003C00L
36634 #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TD_OVERRIDE_MASK                                                    0x00004000L
36635 #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                               0x00018000L
36636 #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK                                                 0x00020000L
36637 #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                           0x00040000L
36638 //CGTS_SA1_WGP01_CU1_TCP_CTRL_REG
36639 #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPF__SHIFT                                                          0x0
36640 #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                 0x4
36641 #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                            0x5
36642 #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                              0x7
36643 #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                        0x8
36644 #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPI__SHIFT                                                          0xa
36645 #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                 0xe
36646 #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                            0xf
36647 #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                              0x11
36648 #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                        0x12
36649 #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPF_MASK                                                            0x0000000FL
36650 #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                   0x00000010L
36651 #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                              0x00000060L
36652 #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                0x00000080L
36653 #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                          0x00000100L
36654 #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPI_MASK                                                            0x00003C00L
36655 #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPI_OVERRIDE_MASK                                                   0x00004000L
36656 #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                              0x00018000L
36657 #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                0x00020000L
36658 #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                          0x00040000L
36659 //CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG
36660 #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SIMD0__SHIFT                                                       0x0
36661 #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT                                              0x4
36662 #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT                                         0x5
36663 #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT                                           0x7
36664 #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
36665 #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQ0__SHIFT                                                         0xa
36666 #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT                                                0xe
36667 #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT                                           0xf
36668 #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT                                             0x11
36669 #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
36670 #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQC__SHIFT                                                         0x14
36671 #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE__SHIFT                                                0x18
36672 #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT                                           0x19
36673 #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE__SHIFT                                             0x1b
36674 #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT                                       0x1c
36675 #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_MASK                                                         0x0000000FL
36676 #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK                                                0x00000010L
36677 #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK                                           0x00000060L
36678 #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK                                             0x00000080L
36679 #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
36680 #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQ0_MASK                                                           0x00003C00L
36681 #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK                                                  0x00004000L
36682 #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK                                             0x00018000L
36683 #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK                                               0x00020000L
36684 #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
36685 #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQC_MASK                                                           0x00F00000L
36686 #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE_MASK                                                  0x01000000L
36687 #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE_MASK                                             0x06000000L
36688 #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE_MASK                                               0x08000000L
36689 #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK                                         0x10000000L
36690 //CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG
36691 #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SIMD1__SHIFT                                                       0x0
36692 #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT                                              0x4
36693 #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT                                         0x5
36694 #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT                                           0x7
36695 #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
36696 #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SQ1__SHIFT                                                         0xa
36697 #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT                                                0xe
36698 #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT                                           0xf
36699 #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT                                             0x11
36700 #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
36701 #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__LDS__SHIFT                                                         0x14
36702 #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE__SHIFT                                                0x18
36703 #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                           0x19
36704 #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                             0x1b
36705 #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                       0x1c
36706 #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_MASK                                                         0x0000000FL
36707 #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK                                                0x00000010L
36708 #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK                                           0x00000060L
36709 #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK                                             0x00000080L
36710 #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
36711 #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SQ1_MASK                                                           0x00003C00L
36712 #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK                                                  0x00004000L
36713 #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK                                             0x00018000L
36714 #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK                                               0x00020000L
36715 #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
36716 #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__LDS_MASK                                                           0x00F00000L
36717 #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE_MASK                                                  0x01000000L
36718 #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                             0x06000000L
36719 #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE_MASK                                               0x08000000L
36720 #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                         0x10000000L
36721 //CGTS_SA1_WGP02_CU0_TATD_CTRL_REG
36722 #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TA__SHIFT                                                           0x0
36723 #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TA_OVERRIDE__SHIFT                                                  0x4
36724 #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                             0x5
36725 #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                               0x7
36726 #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                         0x8
36727 #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TD__SHIFT                                                           0xa
36728 #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TD_OVERRIDE__SHIFT                                                  0xe
36729 #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                             0xf
36730 #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                               0x11
36731 #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                         0x12
36732 #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TA_MASK                                                             0x0000000FL
36733 #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TA_OVERRIDE_MASK                                                    0x00000010L
36734 #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                               0x00000060L
36735 #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK                                                 0x00000080L
36736 #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                           0x00000100L
36737 #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TD_MASK                                                             0x00003C00L
36738 #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TD_OVERRIDE_MASK                                                    0x00004000L
36739 #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                               0x00018000L
36740 #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK                                                 0x00020000L
36741 #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                           0x00040000L
36742 //CGTS_SA1_WGP02_CU0_TCP_CTRL_REG
36743 #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPF__SHIFT                                                          0x0
36744 #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                 0x4
36745 #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                            0x5
36746 #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                              0x7
36747 #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                        0x8
36748 #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPI__SHIFT                                                          0xa
36749 #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                 0xe
36750 #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                            0xf
36751 #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                              0x11
36752 #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                        0x12
36753 #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPF_MASK                                                            0x0000000FL
36754 #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                   0x00000010L
36755 #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                              0x00000060L
36756 #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                0x00000080L
36757 #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                          0x00000100L
36758 #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPI_MASK                                                            0x00003C00L
36759 #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPI_OVERRIDE_MASK                                                   0x00004000L
36760 #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                              0x00018000L
36761 #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                0x00020000L
36762 #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                          0x00040000L
36763 //CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG
36764 #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SIMD0__SHIFT                                                       0x0
36765 #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT                                              0x4
36766 #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT                                         0x5
36767 #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT                                           0x7
36768 #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
36769 #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SQ0__SHIFT                                                         0xa
36770 #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT                                                0xe
36771 #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT                                           0xf
36772 #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT                                             0x11
36773 #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
36774 #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_MASK                                                         0x0000000FL
36775 #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK                                                0x00000010L
36776 #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK                                           0x00000060L
36777 #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK                                             0x00000080L
36778 #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
36779 #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SQ0_MASK                                                           0x00003C00L
36780 #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK                                                  0x00004000L
36781 #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK                                             0x00018000L
36782 #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK                                               0x00020000L
36783 #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
36784 //CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG
36785 #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SIMD1__SHIFT                                                       0x0
36786 #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT                                              0x4
36787 #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT                                         0x5
36788 #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT                                           0x7
36789 #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
36790 #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SQ1__SHIFT                                                         0xa
36791 #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT                                                0xe
36792 #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT                                           0xf
36793 #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT                                             0x11
36794 #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
36795 #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_MASK                                                         0x0000000FL
36796 #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK                                                0x00000010L
36797 #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK                                           0x00000060L
36798 #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK                                             0x00000080L
36799 #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
36800 #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SQ1_MASK                                                           0x00003C00L
36801 #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK                                                  0x00004000L
36802 #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK                                             0x00018000L
36803 #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK                                               0x00020000L
36804 #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
36805 //CGTS_SA1_WGP02_CU1_TATD_CTRL_REG
36806 #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TA__SHIFT                                                           0x0
36807 #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TA_OVERRIDE__SHIFT                                                  0x4
36808 #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                             0x5
36809 #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                               0x7
36810 #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                         0x8
36811 #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TD__SHIFT                                                           0xa
36812 #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TD_OVERRIDE__SHIFT                                                  0xe
36813 #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                             0xf
36814 #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                               0x11
36815 #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                         0x12
36816 #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TA_MASK                                                             0x0000000FL
36817 #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TA_OVERRIDE_MASK                                                    0x00000010L
36818 #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                               0x00000060L
36819 #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK                                                 0x00000080L
36820 #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                           0x00000100L
36821 #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TD_MASK                                                             0x00003C00L
36822 #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TD_OVERRIDE_MASK                                                    0x00004000L
36823 #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                               0x00018000L
36824 #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK                                                 0x00020000L
36825 #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                           0x00040000L
36826 //CGTS_SA1_WGP02_CU1_TCP_CTRL_REG
36827 #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPF__SHIFT                                                          0x0
36828 #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                 0x4
36829 #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                            0x5
36830 #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                              0x7
36831 #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                        0x8
36832 #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPI__SHIFT                                                          0xa
36833 #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                 0xe
36834 #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                            0xf
36835 #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                              0x11
36836 #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                        0x12
36837 #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPF_MASK                                                            0x0000000FL
36838 #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                   0x00000010L
36839 #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                              0x00000060L
36840 #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                0x00000080L
36841 #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                          0x00000100L
36842 #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPI_MASK                                                            0x00003C00L
36843 #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPI_OVERRIDE_MASK                                                   0x00004000L
36844 #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                              0x00018000L
36845 #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                0x00020000L
36846 #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                          0x00040000L
36847 //CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG
36848 #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SIMD0__SHIFT                                                       0x0
36849 #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT                                              0x4
36850 #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT                                         0x5
36851 #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT                                           0x7
36852 #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
36853 #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQ0__SHIFT                                                         0xa
36854 #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT                                                0xe
36855 #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT                                           0xf
36856 #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT                                             0x11
36857 #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
36858 #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQC__SHIFT                                                         0x14
36859 #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE__SHIFT                                                0x18
36860 #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT                                           0x19
36861 #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE__SHIFT                                             0x1b
36862 #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT                                       0x1c
36863 #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_MASK                                                         0x0000000FL
36864 #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK                                                0x00000010L
36865 #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK                                           0x00000060L
36866 #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK                                             0x00000080L
36867 #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
36868 #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQ0_MASK                                                           0x00003C00L
36869 #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK                                                  0x00004000L
36870 #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK                                             0x00018000L
36871 #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK                                               0x00020000L
36872 #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
36873 #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQC_MASK                                                           0x00F00000L
36874 #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE_MASK                                                  0x01000000L
36875 #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE_MASK                                             0x06000000L
36876 #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE_MASK                                               0x08000000L
36877 #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK                                         0x10000000L
36878 //CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG
36879 #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SIMD1__SHIFT                                                       0x0
36880 #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT                                              0x4
36881 #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT                                         0x5
36882 #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT                                           0x7
36883 #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
36884 #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SQ1__SHIFT                                                         0xa
36885 #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT                                                0xe
36886 #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT                                           0xf
36887 #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT                                             0x11
36888 #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
36889 #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__LDS__SHIFT                                                         0x14
36890 #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE__SHIFT                                                0x18
36891 #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                           0x19
36892 #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                             0x1b
36893 #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                       0x1c
36894 #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_MASK                                                         0x0000000FL
36895 #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK                                                0x00000010L
36896 #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK                                           0x00000060L
36897 #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK                                             0x00000080L
36898 #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
36899 #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SQ1_MASK                                                           0x00003C00L
36900 #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK                                                  0x00004000L
36901 #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK                                             0x00018000L
36902 #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK                                               0x00020000L
36903 #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
36904 #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__LDS_MASK                                                           0x00F00000L
36905 #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE_MASK                                                  0x01000000L
36906 #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                             0x06000000L
36907 #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE_MASK                                               0x08000000L
36908 #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                         0x10000000L
36909 //CGTS_SA1_WGP10_CU0_TATD_CTRL_REG
36910 #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TA__SHIFT                                                           0x0
36911 #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TA_OVERRIDE__SHIFT                                                  0x4
36912 #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                             0x5
36913 #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                               0x7
36914 #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                         0x8
36915 #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TD__SHIFT                                                           0xa
36916 #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TD_OVERRIDE__SHIFT                                                  0xe
36917 #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                             0xf
36918 #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                               0x11
36919 #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                         0x12
36920 #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TA_MASK                                                             0x0000000FL
36921 #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TA_OVERRIDE_MASK                                                    0x00000010L
36922 #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                               0x00000060L
36923 #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK                                                 0x00000080L
36924 #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                           0x00000100L
36925 #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TD_MASK                                                             0x00003C00L
36926 #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TD_OVERRIDE_MASK                                                    0x00004000L
36927 #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                               0x00018000L
36928 #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK                                                 0x00020000L
36929 #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                           0x00040000L
36930 //CGTS_SA1_WGP10_CU0_TCP_CTRL_REG
36931 #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPF__SHIFT                                                          0x0
36932 #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                 0x4
36933 #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                            0x5
36934 #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                              0x7
36935 #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                        0x8
36936 #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPI__SHIFT                                                          0xa
36937 #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                 0xe
36938 #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                            0xf
36939 #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                              0x11
36940 #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                        0x12
36941 #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPF_MASK                                                            0x0000000FL
36942 #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                   0x00000010L
36943 #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                              0x00000060L
36944 #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                0x00000080L
36945 #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                          0x00000100L
36946 #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPI_MASK                                                            0x00003C00L
36947 #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPI_OVERRIDE_MASK                                                   0x00004000L
36948 #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                              0x00018000L
36949 #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                0x00020000L
36950 #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                          0x00040000L
36951 //CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG
36952 #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SIMD0__SHIFT                                                       0x0
36953 #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT                                              0x4
36954 #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT                                         0x5
36955 #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT                                           0x7
36956 #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
36957 #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SQ0__SHIFT                                                         0xa
36958 #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT                                                0xe
36959 #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT                                           0xf
36960 #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT                                             0x11
36961 #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
36962 #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_MASK                                                         0x0000000FL
36963 #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK                                                0x00000010L
36964 #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK                                           0x00000060L
36965 #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK                                             0x00000080L
36966 #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
36967 #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SQ0_MASK                                                           0x00003C00L
36968 #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK                                                  0x00004000L
36969 #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK                                             0x00018000L
36970 #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK                                               0x00020000L
36971 #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
36972 //CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG
36973 #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SIMD1__SHIFT                                                       0x0
36974 #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT                                              0x4
36975 #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT                                         0x5
36976 #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT                                           0x7
36977 #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
36978 #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SQ1__SHIFT                                                         0xa
36979 #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT                                                0xe
36980 #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT                                           0xf
36981 #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT                                             0x11
36982 #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
36983 #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_MASK                                                         0x0000000FL
36984 #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK                                                0x00000010L
36985 #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK                                           0x00000060L
36986 #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK                                             0x00000080L
36987 #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
36988 #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SQ1_MASK                                                           0x00003C00L
36989 #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK                                                  0x00004000L
36990 #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK                                             0x00018000L
36991 #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK                                               0x00020000L
36992 #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
36993 //CGTS_SA1_WGP10_CU1_TATD_CTRL_REG
36994 #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TA__SHIFT                                                           0x0
36995 #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TA_OVERRIDE__SHIFT                                                  0x4
36996 #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                             0x5
36997 #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                               0x7
36998 #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                         0x8
36999 #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TD__SHIFT                                                           0xa
37000 #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TD_OVERRIDE__SHIFT                                                  0xe
37001 #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                             0xf
37002 #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                               0x11
37003 #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                         0x12
37004 #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TA_MASK                                                             0x0000000FL
37005 #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TA_OVERRIDE_MASK                                                    0x00000010L
37006 #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                               0x00000060L
37007 #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK                                                 0x00000080L
37008 #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                           0x00000100L
37009 #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TD_MASK                                                             0x00003C00L
37010 #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TD_OVERRIDE_MASK                                                    0x00004000L
37011 #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                               0x00018000L
37012 #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK                                                 0x00020000L
37013 #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                           0x00040000L
37014 //CGTS_SA1_WGP10_CU1_TCP_CTRL_REG
37015 #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPF__SHIFT                                                          0x0
37016 #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                 0x4
37017 #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                            0x5
37018 #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                              0x7
37019 #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                        0x8
37020 #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPI__SHIFT                                                          0xa
37021 #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                 0xe
37022 #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                            0xf
37023 #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                              0x11
37024 #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                        0x12
37025 #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPF_MASK                                                            0x0000000FL
37026 #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                   0x00000010L
37027 #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                              0x00000060L
37028 #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                0x00000080L
37029 #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                          0x00000100L
37030 #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPI_MASK                                                            0x00003C00L
37031 #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPI_OVERRIDE_MASK                                                   0x00004000L
37032 #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                              0x00018000L
37033 #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                0x00020000L
37034 #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                          0x00040000L
37035 //CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG
37036 #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SIMD0__SHIFT                                                       0x0
37037 #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT                                              0x4
37038 #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT                                         0x5
37039 #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT                                           0x7
37040 #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
37041 #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQ0__SHIFT                                                         0xa
37042 #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT                                                0xe
37043 #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT                                           0xf
37044 #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT                                             0x11
37045 #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
37046 #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQC__SHIFT                                                         0x14
37047 #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE__SHIFT                                                0x18
37048 #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT                                           0x19
37049 #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE__SHIFT                                             0x1b
37050 #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT                                       0x1c
37051 #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_MASK                                                         0x0000000FL
37052 #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK                                                0x00000010L
37053 #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK                                           0x00000060L
37054 #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK                                             0x00000080L
37055 #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
37056 #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQ0_MASK                                                           0x00003C00L
37057 #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK                                                  0x00004000L
37058 #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK                                             0x00018000L
37059 #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK                                               0x00020000L
37060 #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
37061 #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQC_MASK                                                           0x00F00000L
37062 #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE_MASK                                                  0x01000000L
37063 #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE_MASK                                             0x06000000L
37064 #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE_MASK                                               0x08000000L
37065 #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK                                         0x10000000L
37066 //CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG
37067 #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SIMD1__SHIFT                                                       0x0
37068 #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT                                              0x4
37069 #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT                                         0x5
37070 #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT                                           0x7
37071 #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
37072 #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SQ1__SHIFT                                                         0xa
37073 #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT                                                0xe
37074 #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT                                           0xf
37075 #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT                                             0x11
37076 #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
37077 #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__LDS__SHIFT                                                         0x14
37078 #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE__SHIFT                                                0x18
37079 #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                           0x19
37080 #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                             0x1b
37081 #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                       0x1c
37082 #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_MASK                                                         0x0000000FL
37083 #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK                                                0x00000010L
37084 #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK                                           0x00000060L
37085 #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK                                             0x00000080L
37086 #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
37087 #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SQ1_MASK                                                           0x00003C00L
37088 #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK                                                  0x00004000L
37089 #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK                                             0x00018000L
37090 #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK                                               0x00020000L
37091 #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
37092 #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__LDS_MASK                                                           0x00F00000L
37093 #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE_MASK                                                  0x01000000L
37094 #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                             0x06000000L
37095 #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE_MASK                                               0x08000000L
37096 #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                         0x10000000L
37097 //CGTS_SA1_WGP11_CU0_TATD_CTRL_REG
37098 #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TA__SHIFT                                                           0x0
37099 #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TA_OVERRIDE__SHIFT                                                  0x4
37100 #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                             0x5
37101 #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                               0x7
37102 #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                         0x8
37103 #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TD__SHIFT                                                           0xa
37104 #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TD_OVERRIDE__SHIFT                                                  0xe
37105 #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                             0xf
37106 #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                               0x11
37107 #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                         0x12
37108 #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TA_MASK                                                             0x0000000FL
37109 #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TA_OVERRIDE_MASK                                                    0x00000010L
37110 #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                               0x00000060L
37111 #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK                                                 0x00000080L
37112 #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                           0x00000100L
37113 #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TD_MASK                                                             0x00003C00L
37114 #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TD_OVERRIDE_MASK                                                    0x00004000L
37115 #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                               0x00018000L
37116 #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK                                                 0x00020000L
37117 #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                           0x00040000L
37118 //CGTS_SA1_WGP11_CU0_TCP_CTRL_REG
37119 #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPF__SHIFT                                                          0x0
37120 #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                 0x4
37121 #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                            0x5
37122 #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                              0x7
37123 #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                        0x8
37124 #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPI__SHIFT                                                          0xa
37125 #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                 0xe
37126 #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                            0xf
37127 #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                              0x11
37128 #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                        0x12
37129 #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPF_MASK                                                            0x0000000FL
37130 #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                   0x00000010L
37131 #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                              0x00000060L
37132 #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                0x00000080L
37133 #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                          0x00000100L
37134 #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPI_MASK                                                            0x00003C00L
37135 #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPI_OVERRIDE_MASK                                                   0x00004000L
37136 #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                              0x00018000L
37137 #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                0x00020000L
37138 #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                          0x00040000L
37139 //CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG
37140 #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SIMD0__SHIFT                                                       0x0
37141 #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT                                              0x4
37142 #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT                                         0x5
37143 #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT                                           0x7
37144 #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
37145 #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SQ0__SHIFT                                                         0xa
37146 #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT                                                0xe
37147 #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT                                           0xf
37148 #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT                                             0x11
37149 #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
37150 #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_MASK                                                         0x0000000FL
37151 #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK                                                0x00000010L
37152 #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK                                           0x00000060L
37153 #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK                                             0x00000080L
37154 #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
37155 #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SQ0_MASK                                                           0x00003C00L
37156 #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK                                                  0x00004000L
37157 #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK                                             0x00018000L
37158 #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK                                               0x00020000L
37159 #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
37160 //CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG
37161 #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SIMD1__SHIFT                                                       0x0
37162 #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT                                              0x4
37163 #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT                                         0x5
37164 #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT                                           0x7
37165 #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
37166 #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SQ1__SHIFT                                                         0xa
37167 #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT                                                0xe
37168 #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT                                           0xf
37169 #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT                                             0x11
37170 #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
37171 #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_MASK                                                         0x0000000FL
37172 #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK                                                0x00000010L
37173 #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK                                           0x00000060L
37174 #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK                                             0x00000080L
37175 #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
37176 #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SQ1_MASK                                                           0x00003C00L
37177 #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK                                                  0x00004000L
37178 #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK                                             0x00018000L
37179 #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK                                               0x00020000L
37180 #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
37181 //CGTS_SA1_WGP11_CU1_TATD_CTRL_REG
37182 #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TA__SHIFT                                                           0x0
37183 #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TA_OVERRIDE__SHIFT                                                  0x4
37184 #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                             0x5
37185 #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                               0x7
37186 #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                         0x8
37187 #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TD__SHIFT                                                           0xa
37188 #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TD_OVERRIDE__SHIFT                                                  0xe
37189 #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                             0xf
37190 #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                               0x11
37191 #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                         0x12
37192 #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TA_MASK                                                             0x0000000FL
37193 #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TA_OVERRIDE_MASK                                                    0x00000010L
37194 #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                               0x00000060L
37195 #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK                                                 0x00000080L
37196 #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                           0x00000100L
37197 #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TD_MASK                                                             0x00003C00L
37198 #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TD_OVERRIDE_MASK                                                    0x00004000L
37199 #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                               0x00018000L
37200 #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK                                                 0x00020000L
37201 #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                           0x00040000L
37202 //CGTS_SA1_WGP11_CU1_TCP_CTRL_REG
37203 #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPF__SHIFT                                                          0x0
37204 #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                 0x4
37205 #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                            0x5
37206 #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                              0x7
37207 #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                        0x8
37208 #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPI__SHIFT                                                          0xa
37209 #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                 0xe
37210 #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                            0xf
37211 #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                              0x11
37212 #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                        0x12
37213 #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPF_MASK                                                            0x0000000FL
37214 #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                   0x00000010L
37215 #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                              0x00000060L
37216 #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                0x00000080L
37217 #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                          0x00000100L
37218 #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPI_MASK                                                            0x00003C00L
37219 #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPI_OVERRIDE_MASK                                                   0x00004000L
37220 #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                              0x00018000L
37221 #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                0x00020000L
37222 #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                          0x00040000L
37223 //CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG
37224 #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SIMD0__SHIFT                                                       0x0
37225 #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT                                              0x4
37226 #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT                                         0x5
37227 #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT                                           0x7
37228 #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
37229 #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQ0__SHIFT                                                         0xa
37230 #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT                                                0xe
37231 #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT                                           0xf
37232 #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT                                             0x11
37233 #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
37234 #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQC__SHIFT                                                         0x14
37235 #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE__SHIFT                                                0x18
37236 #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT                                           0x19
37237 #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE__SHIFT                                             0x1b
37238 #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT                                       0x1c
37239 #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_MASK                                                         0x0000000FL
37240 #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK                                                0x00000010L
37241 #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK                                           0x00000060L
37242 #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK                                             0x00000080L
37243 #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
37244 #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQ0_MASK                                                           0x00003C00L
37245 #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK                                                  0x00004000L
37246 #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK                                             0x00018000L
37247 #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK                                               0x00020000L
37248 #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
37249 #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQC_MASK                                                           0x00F00000L
37250 #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE_MASK                                                  0x01000000L
37251 #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE_MASK                                             0x06000000L
37252 #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE_MASK                                               0x08000000L
37253 #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK                                         0x10000000L
37254 //CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG
37255 #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SIMD1__SHIFT                                                       0x0
37256 #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT                                              0x4
37257 #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT                                         0x5
37258 #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT                                           0x7
37259 #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
37260 #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SQ1__SHIFT                                                         0xa
37261 #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT                                                0xe
37262 #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT                                           0xf
37263 #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT                                             0x11
37264 #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
37265 #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__LDS__SHIFT                                                         0x14
37266 #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE__SHIFT                                                0x18
37267 #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                           0x19
37268 #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                             0x1b
37269 #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                       0x1c
37270 #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_MASK                                                         0x0000000FL
37271 #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK                                                0x00000010L
37272 #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK                                           0x00000060L
37273 #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK                                             0x00000080L
37274 #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
37275 #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SQ1_MASK                                                           0x00003C00L
37276 #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK                                                  0x00004000L
37277 #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK                                             0x00018000L
37278 #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK                                               0x00020000L
37279 #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
37280 #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__LDS_MASK                                                           0x00F00000L
37281 #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE_MASK                                                  0x01000000L
37282 #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                             0x06000000L
37283 #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE_MASK                                               0x08000000L
37284 #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                         0x10000000L
37285 //CGTS_SA0_WGP12_CU0_TATD_CTRL_REG
37286 #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TA__SHIFT                                                           0x0
37287 #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TA_OVERRIDE__SHIFT                                                  0x4
37288 #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                             0x5
37289 #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                               0x7
37290 #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                         0x8
37291 #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TD__SHIFT                                                           0xa
37292 #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TD_OVERRIDE__SHIFT                                                  0xe
37293 #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                             0xf
37294 #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                               0x11
37295 #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                         0x12
37296 #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TA_MASK                                                             0x0000000FL
37297 #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TA_OVERRIDE_MASK                                                    0x00000010L
37298 #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                               0x00000060L
37299 #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK                                                 0x00000080L
37300 #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                           0x00000100L
37301 #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TD_MASK                                                             0x00003C00L
37302 #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TD_OVERRIDE_MASK                                                    0x00004000L
37303 #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                               0x00018000L
37304 #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK                                                 0x00020000L
37305 #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                           0x00040000L
37306 //CGTS_SA0_WGP12_CU0_TCP_CTRL_REG
37307 #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPF__SHIFT                                                          0x0
37308 #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                 0x4
37309 #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                            0x5
37310 #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                              0x7
37311 #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                        0x8
37312 #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPI__SHIFT                                                          0xa
37313 #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                 0xe
37314 #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                            0xf
37315 #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                              0x11
37316 #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                        0x12
37317 #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPF_MASK                                                            0x0000000FL
37318 #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                   0x00000010L
37319 #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                              0x00000060L
37320 #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                0x00000080L
37321 #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                          0x00000100L
37322 #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPI_MASK                                                            0x00003C00L
37323 #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPI_OVERRIDE_MASK                                                   0x00004000L
37324 #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                              0x00018000L
37325 #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                0x00020000L
37326 #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                          0x00040000L
37327 //CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG
37328 #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SIMD0__SHIFT                                                       0x0
37329 #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT                                              0x4
37330 #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT                                         0x5
37331 #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT                                           0x7
37332 #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
37333 #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SQ0__SHIFT                                                         0xa
37334 #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT                                                0xe
37335 #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT                                           0xf
37336 #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT                                             0x11
37337 #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
37338 #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_MASK                                                         0x0000000FL
37339 #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK                                                0x00000010L
37340 #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK                                           0x00000060L
37341 #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK                                             0x00000080L
37342 #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
37343 #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SQ0_MASK                                                           0x00003C00L
37344 #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK                                                  0x00004000L
37345 #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK                                             0x00018000L
37346 #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK                                               0x00020000L
37347 #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
37348 //CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG
37349 #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SIMD1__SHIFT                                                       0x0
37350 #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT                                              0x4
37351 #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT                                         0x5
37352 #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT                                           0x7
37353 #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
37354 #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SQ1__SHIFT                                                         0xa
37355 #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT                                                0xe
37356 #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT                                           0xf
37357 #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT                                             0x11
37358 #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
37359 #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_MASK                                                         0x0000000FL
37360 #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK                                                0x00000010L
37361 #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK                                           0x00000060L
37362 #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK                                             0x00000080L
37363 #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
37364 #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SQ1_MASK                                                           0x00003C00L
37365 #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK                                                  0x00004000L
37366 #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK                                             0x00018000L
37367 #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK                                               0x00020000L
37368 #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
37369 //CGTS_SA0_WGP12_CU1_TATD_CTRL_REG
37370 #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TA__SHIFT                                                           0x0
37371 #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TA_OVERRIDE__SHIFT                                                  0x4
37372 #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                             0x5
37373 #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                               0x7
37374 #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                         0x8
37375 #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TD__SHIFT                                                           0xa
37376 #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TD_OVERRIDE__SHIFT                                                  0xe
37377 #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                             0xf
37378 #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                               0x11
37379 #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                         0x12
37380 #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TA_MASK                                                             0x0000000FL
37381 #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TA_OVERRIDE_MASK                                                    0x00000010L
37382 #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                               0x00000060L
37383 #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK                                                 0x00000080L
37384 #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                           0x00000100L
37385 #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TD_MASK                                                             0x00003C00L
37386 #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TD_OVERRIDE_MASK                                                    0x00004000L
37387 #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                               0x00018000L
37388 #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK                                                 0x00020000L
37389 #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                           0x00040000L
37390 //CGTS_SA0_WGP12_CU1_TCP_CTRL_REG
37391 #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPF__SHIFT                                                          0x0
37392 #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                 0x4
37393 #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                            0x5
37394 #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                              0x7
37395 #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                        0x8
37396 #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPI__SHIFT                                                          0xa
37397 #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                 0xe
37398 #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                            0xf
37399 #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                              0x11
37400 #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                        0x12
37401 #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPF_MASK                                                            0x0000000FL
37402 #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                   0x00000010L
37403 #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                              0x00000060L
37404 #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                0x00000080L
37405 #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                          0x00000100L
37406 #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPI_MASK                                                            0x00003C00L
37407 #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPI_OVERRIDE_MASK                                                   0x00004000L
37408 #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                              0x00018000L
37409 #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                0x00020000L
37410 #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                          0x00040000L
37411 //CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG
37412 #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SIMD0__SHIFT                                                       0x0
37413 #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT                                              0x4
37414 #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT                                         0x5
37415 #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT                                           0x7
37416 #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
37417 #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQ0__SHIFT                                                         0xa
37418 #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT                                                0xe
37419 #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT                                           0xf
37420 #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT                                             0x11
37421 #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
37422 #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQC__SHIFT                                                         0x14
37423 #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE__SHIFT                                                0x18
37424 #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT                                           0x19
37425 #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE__SHIFT                                             0x1b
37426 #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT                                       0x1c
37427 #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_MASK                                                         0x0000000FL
37428 #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK                                                0x00000010L
37429 #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK                                           0x00000060L
37430 #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK                                             0x00000080L
37431 #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
37432 #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQ0_MASK                                                           0x00003C00L
37433 #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK                                                  0x00004000L
37434 #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK                                             0x00018000L
37435 #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK                                               0x00020000L
37436 #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
37437 #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQC_MASK                                                           0x00F00000L
37438 #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE_MASK                                                  0x01000000L
37439 #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE_MASK                                             0x06000000L
37440 #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE_MASK                                               0x08000000L
37441 #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK                                         0x10000000L
37442 //CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG
37443 #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SIMD1__SHIFT                                                       0x0
37444 #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT                                              0x4
37445 #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT                                         0x5
37446 #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT                                           0x7
37447 #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
37448 #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SQ1__SHIFT                                                         0xa
37449 #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT                                                0xe
37450 #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT                                           0xf
37451 #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT                                             0x11
37452 #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
37453 #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__LDS__SHIFT                                                         0x14
37454 #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE__SHIFT                                                0x18
37455 #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                           0x19
37456 #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                             0x1b
37457 #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                       0x1c
37458 #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_MASK                                                         0x0000000FL
37459 #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK                                                0x00000010L
37460 #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK                                           0x00000060L
37461 #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK                                             0x00000080L
37462 #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
37463 #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SQ1_MASK                                                           0x00003C00L
37464 #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK                                                  0x00004000L
37465 #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK                                             0x00018000L
37466 #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK                                               0x00020000L
37467 #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
37468 #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__LDS_MASK                                                           0x00F00000L
37469 #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE_MASK                                                  0x01000000L
37470 #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                             0x06000000L
37471 #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE_MASK                                               0x08000000L
37472 #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                         0x10000000L
37473 //CGTS_SA1_WGP12_CU0_TATD_CTRL_REG
37474 #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TA__SHIFT                                                           0x0
37475 #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TA_OVERRIDE__SHIFT                                                  0x4
37476 #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                             0x5
37477 #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                               0x7
37478 #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                         0x8
37479 #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TD__SHIFT                                                           0xa
37480 #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TD_OVERRIDE__SHIFT                                                  0xe
37481 #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                             0xf
37482 #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                               0x11
37483 #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                         0x12
37484 #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TA_MASK                                                             0x0000000FL
37485 #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TA_OVERRIDE_MASK                                                    0x00000010L
37486 #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                               0x00000060L
37487 #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK                                                 0x00000080L
37488 #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                           0x00000100L
37489 #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TD_MASK                                                             0x00003C00L
37490 #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TD_OVERRIDE_MASK                                                    0x00004000L
37491 #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                               0x00018000L
37492 #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK                                                 0x00020000L
37493 #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                           0x00040000L
37494 //CGTS_SA1_WGP12_CU0_TCP_CTRL_REG
37495 #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPF__SHIFT                                                          0x0
37496 #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                 0x4
37497 #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                            0x5
37498 #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                              0x7
37499 #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                        0x8
37500 #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPI__SHIFT                                                          0xa
37501 #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                 0xe
37502 #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                            0xf
37503 #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                              0x11
37504 #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                        0x12
37505 #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPF_MASK                                                            0x0000000FL
37506 #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                   0x00000010L
37507 #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                              0x00000060L
37508 #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                0x00000080L
37509 #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                          0x00000100L
37510 #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPI_MASK                                                            0x00003C00L
37511 #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPI_OVERRIDE_MASK                                                   0x00004000L
37512 #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                              0x00018000L
37513 #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                0x00020000L
37514 #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                          0x00040000L
37515 //CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG
37516 #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SIMD0__SHIFT                                                       0x0
37517 #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT                                              0x4
37518 #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT                                         0x5
37519 #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT                                           0x7
37520 #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
37521 #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SQ0__SHIFT                                                         0xa
37522 #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT                                                0xe
37523 #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT                                           0xf
37524 #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT                                             0x11
37525 #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
37526 #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_MASK                                                         0x0000000FL
37527 #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK                                                0x00000010L
37528 #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK                                           0x00000060L
37529 #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK                                             0x00000080L
37530 #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
37531 #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SQ0_MASK                                                           0x00003C00L
37532 #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK                                                  0x00004000L
37533 #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK                                             0x00018000L
37534 #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK                                               0x00020000L
37535 #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
37536 //CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG
37537 #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SIMD1__SHIFT                                                       0x0
37538 #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT                                              0x4
37539 #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT                                         0x5
37540 #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT                                           0x7
37541 #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT                                     0x8
37542 #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SQ1__SHIFT                                                         0xa
37543 #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT                                                0xe
37544 #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT                                           0xf
37545 #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT                                             0x11
37546 #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT                                       0x12
37547 #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_MASK                                                         0x0000000FL
37548 #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK                                                0x00000010L
37549 #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK                                           0x00000060L
37550 #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK                                             0x00000080L
37551 #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK                                       0x00000100L
37552 #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SQ1_MASK                                                           0x00003C00L
37553 #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK                                                  0x00004000L
37554 #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK                                             0x00018000L
37555 #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK                                               0x00020000L
37556 #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK                                         0x00040000L
37557 //CGTS_SA1_WGP12_CU1_TATD_CTRL_REG
37558 #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TA__SHIFT                                                           0x0
37559 #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TA_OVERRIDE__SHIFT                                                  0x4
37560 #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                             0x5
37561 #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                               0x7
37562 #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                         0x8
37563 #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TD__SHIFT                                                           0xa
37564 #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TD_OVERRIDE__SHIFT                                                  0xe
37565 #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                             0xf
37566 #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                               0x11
37567 #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                         0x12
37568 #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TA_MASK                                                             0x0000000FL
37569 #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TA_OVERRIDE_MASK                                                    0x00000010L
37570 #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                               0x00000060L
37571 #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK                                                 0x00000080L
37572 #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                           0x00000100L
37573 #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TD_MASK                                                             0x00003C00L
37574 #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TD_OVERRIDE_MASK                                                    0x00004000L
37575 #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                               0x00018000L
37576 #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK                                                 0x00020000L
37577 #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                           0x00040000L
37578 //CGTS_SA1_WGP12_CU1_TCP_CTRL_REG
37579 #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPF__SHIFT                                                          0x0
37580 #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                 0x4
37581 #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                            0x5
37582 #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                              0x7
37583 #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                        0x8
37584 #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPI__SHIFT                                                          0xa
37585 #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                 0xe
37586 #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                            0xf
37587 #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                              0x11
37588 #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                        0x12
37589 #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPF_MASK                                                            0x0000000FL
37590 #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                   0x00000010L
37591 #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                              0x00000060L
37592 #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                0x00000080L
37593 #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                          0x00000100L
37594 #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPI_MASK                                                            0x00003C00L
37595 #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPI_OVERRIDE_MASK                                                   0x00004000L
37596 #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                              0x00018000L
37597 #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                0x00020000L
37598 #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                          0x00040000L
37599 //CGTT_SPI_PS_CLK_CTRL
37600 #define CGTT_SPI_PS_CLK_CTRL__ON_DELAY__SHIFT                                                                 0x0
37601 #define CGTT_SPI_PS_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                           0x4
37602 #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                     0x10
37603 #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                     0x11
37604 #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                     0x12
37605 #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                     0x13
37606 #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                     0x14
37607 #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                     0x15
37608 #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                     0x16
37609 #define CGTT_SPI_PS_CLK_CTRL__GRP6_OVERRIDE__SHIFT                                                            0x18
37610 #define CGTT_SPI_PS_CLK_CTRL__GRP5_OVERRIDE__SHIFT                                                            0x19
37611 #define CGTT_SPI_PS_CLK_CTRL__GRP4_OVERRIDE__SHIFT                                                            0x1a
37612 #define CGTT_SPI_PS_CLK_CTRL__GRP3_OVERRIDE__SHIFT                                                            0x1b
37613 #define CGTT_SPI_PS_CLK_CTRL__GRP2_OVERRIDE__SHIFT                                                            0x1c
37614 #define CGTT_SPI_PS_CLK_CTRL__GRP1_OVERRIDE__SHIFT                                                            0x1d
37615 #define CGTT_SPI_PS_CLK_CTRL__GRP0_OVERRIDE__SHIFT                                                            0x1e
37616 #define CGTT_SPI_PS_CLK_CTRL__REG_OVERRIDE__SHIFT                                                             0x1f
37617 #define CGTT_SPI_PS_CLK_CTRL__ON_DELAY_MASK                                                                   0x0000000FL
37618 #define CGTT_SPI_PS_CLK_CTRL__OFF_HYSTERESIS_MASK                                                             0x00000FF0L
37619 #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                       0x00010000L
37620 #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                       0x00020000L
37621 #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                       0x00040000L
37622 #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                       0x00080000L
37623 #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                       0x00100000L
37624 #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                       0x00200000L
37625 #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                       0x00400000L
37626 #define CGTT_SPI_PS_CLK_CTRL__GRP6_OVERRIDE_MASK                                                              0x01000000L
37627 #define CGTT_SPI_PS_CLK_CTRL__GRP5_OVERRIDE_MASK                                                              0x02000000L
37628 #define CGTT_SPI_PS_CLK_CTRL__GRP4_OVERRIDE_MASK                                                              0x04000000L
37629 #define CGTT_SPI_PS_CLK_CTRL__GRP3_OVERRIDE_MASK                                                              0x08000000L
37630 #define CGTT_SPI_PS_CLK_CTRL__GRP2_OVERRIDE_MASK                                                              0x10000000L
37631 #define CGTT_SPI_PS_CLK_CTRL__GRP1_OVERRIDE_MASK                                                              0x20000000L
37632 #define CGTT_SPI_PS_CLK_CTRL__GRP0_OVERRIDE_MASK                                                              0x40000000L
37633 #define CGTT_SPI_PS_CLK_CTRL__REG_OVERRIDE_MASK                                                               0x80000000L
37634 //CGTT_SPIS_CLK_CTRL
37635 #define CGTT_SPIS_CLK_CTRL__ON_DELAY__SHIFT                                                                   0x0
37636 #define CGTT_SPIS_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                             0x4
37637 #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                       0x10
37638 #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                       0x11
37639 #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                       0x12
37640 #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                       0x13
37641 #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                       0x14
37642 #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                       0x15
37643 #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                       0x16
37644 #define CGTT_SPIS_CLK_CTRL__GRP6_OVERRIDE__SHIFT                                                              0x18
37645 #define CGTT_SPIS_CLK_CTRL__GRP5_OVERRIDE__SHIFT                                                              0x19
37646 #define CGTT_SPIS_CLK_CTRL__GRP4_OVERRIDE__SHIFT                                                              0x1a
37647 #define CGTT_SPIS_CLK_CTRL__GRP3_OVERRIDE__SHIFT                                                              0x1b
37648 #define CGTT_SPIS_CLK_CTRL__GRP2_OVERRIDE__SHIFT                                                              0x1c
37649 #define CGTT_SPIS_CLK_CTRL__GRP1_OVERRIDE__SHIFT                                                              0x1d
37650 #define CGTT_SPIS_CLK_CTRL__GRP0_OVERRIDE__SHIFT                                                              0x1e
37651 #define CGTT_SPIS_CLK_CTRL__REG_OVERRIDE__SHIFT                                                               0x1f
37652 #define CGTT_SPIS_CLK_CTRL__ON_DELAY_MASK                                                                     0x0000000FL
37653 #define CGTT_SPIS_CLK_CTRL__OFF_HYSTERESIS_MASK                                                               0x00000FF0L
37654 #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                         0x00010000L
37655 #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                         0x00020000L
37656 #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                         0x00040000L
37657 #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                         0x00080000L
37658 #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                         0x00100000L
37659 #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                         0x00200000L
37660 #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                         0x00400000L
37661 #define CGTT_SPIS_CLK_CTRL__GRP6_OVERRIDE_MASK                                                                0x01000000L
37662 #define CGTT_SPIS_CLK_CTRL__GRP5_OVERRIDE_MASK                                                                0x02000000L
37663 #define CGTT_SPIS_CLK_CTRL__GRP4_OVERRIDE_MASK                                                                0x04000000L
37664 #define CGTT_SPIS_CLK_CTRL__GRP3_OVERRIDE_MASK                                                                0x08000000L
37665 #define CGTT_SPIS_CLK_CTRL__GRP2_OVERRIDE_MASK                                                                0x10000000L
37666 #define CGTT_SPIS_CLK_CTRL__GRP1_OVERRIDE_MASK                                                                0x20000000L
37667 #define CGTT_SPIS_CLK_CTRL__GRP0_OVERRIDE_MASK                                                                0x40000000L
37668 #define CGTT_SPIS_CLK_CTRL__REG_OVERRIDE_MASK                                                                 0x80000000L
37669 //CGTT_SPI_CLK_CTRL
37670 #define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
37671 #define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
37672 #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x10
37673 #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x11
37674 #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x12
37675 #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x13
37676 #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x14
37677 #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x15
37678 #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x16
37679 #define CGTT_SPI_CLK_CTRL__GRP6_OVERRIDE__SHIFT                                                               0x18
37680 #define CGTT_SPI_CLK_CTRL__GRP5_OVERRIDE__SHIFT                                                               0x19
37681 #define CGTT_SPI_CLK_CTRL__GRP4_OVERRIDE__SHIFT                                                               0x1a
37682 #define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT                                                               0x1b
37683 #define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT                                                               0x1c
37684 #define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT                                                               0x1d
37685 #define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT                                                               0x1e
37686 #define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT                                                                0x1f
37687 #define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
37688 #define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
37689 #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                          0x00010000L
37690 #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                          0x00020000L
37691 #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                          0x00040000L
37692 #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                          0x00080000L
37693 #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                          0x00100000L
37694 #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                          0x00200000L
37695 #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                          0x00400000L
37696 #define CGTT_SPI_CLK_CTRL__GRP6_OVERRIDE_MASK                                                                 0x01000000L
37697 #define CGTT_SPI_CLK_CTRL__GRP5_OVERRIDE_MASK                                                                 0x02000000L
37698 #define CGTT_SPI_CLK_CTRL__GRP4_OVERRIDE_MASK                                                                 0x04000000L
37699 #define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK                                                                 0x08000000L
37700 #define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK                                                                 0x10000000L
37701 #define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK                                                                 0x20000000L
37702 #define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK                                                                 0x40000000L
37703 #define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK                                                                  0x80000000L
37704 //CGTT_PC_CLK_CTRL
37705 #define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT                                                                     0x0
37706 #define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                               0x4
37707 #define CGTT_PC_CLK_CTRL__PC_RAM_FGCG_OVERRIDE__SHIFT                                                         0x11
37708 #define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT                                                             0x12
37709 #define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT                                                             0x18
37710 #define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE__SHIFT                                                     0x19
37711 #define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE__SHIFT                                                      0x1a
37712 #define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT                                                               0x1b
37713 #define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT                                                               0x1c
37714 #define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT                                                               0x1d
37715 #define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT                                                               0x1e
37716 #define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT                                                                 0x1f
37717 #define CGTT_PC_CLK_CTRL__ON_DELAY_MASK                                                                       0x0000000FL
37718 #define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                 0x00000FF0L
37719 #define CGTT_PC_CLK_CTRL__PC_RAM_FGCG_OVERRIDE_MASK                                                           0x00020000L
37720 #define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK                                                               0x00FC0000L
37721 #define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK                                                               0x01000000L
37722 #define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE_MASK                                                       0x02000000L
37723 #define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE_MASK                                                        0x04000000L
37724 #define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK                                                                 0x08000000L
37725 #define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK                                                                 0x10000000L
37726 #define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK                                                                 0x20000000L
37727 #define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK                                                                 0x40000000L
37728 #define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK                                                                   0x80000000L
37729 //CGTT_BCI_CLK_CTRL
37730 #define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
37731 #define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
37732 #define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT                                                                    0xc
37733 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
37734 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
37735 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
37736 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
37737 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
37738 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
37739 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
37740 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
37741 #define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT                                                              0x18
37742 #define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT                                                              0x19
37743 #define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT                                                              0x1a
37744 #define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT                                                              0x1b
37745 #define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT                                                              0x1c
37746 #define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT                                                              0x1d
37747 #define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT                                                              0x1e
37748 #define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT                                                                0x1f
37749 #define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
37750 #define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
37751 #define CGTT_BCI_CLK_CTRL__RESERVED_MASK                                                                      0x0000F000L
37752 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
37753 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
37754 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
37755 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
37756 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
37757 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
37758 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
37759 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
37760 #define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK                                                                0x01000000L
37761 #define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK                                                                0x02000000L
37762 #define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK                                                                0x04000000L
37763 #define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK                                                                0x08000000L
37764 #define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK                                                                0x10000000L
37765 #define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK                                                                0x20000000L
37766 #define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK                                                                0x40000000L
37767 #define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK                                                                  0x80000000L
37768 //CGTT_VGT_CLK_CTRL
37769 #define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
37770 #define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
37771 #define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT                                                                 0xf
37772 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
37773 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
37774 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
37775 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
37776 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
37777 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
37778 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
37779 #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9__SHIFT                                                              0x18
37780 #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8__SHIFT                                                              0x19
37781 #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                              0x1a
37782 #define CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT                                                            0x1b
37783 #define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE__SHIFT                                                               0x1c
37784 #define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT                                                                 0x1d
37785 #define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT                                                               0x1e
37786 #define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT                                                                0x1f
37787 #define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
37788 #define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
37789 #define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK                                                                   0x00008000L
37790 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
37791 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
37792 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
37793 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
37794 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
37795 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
37796 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
37797 #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9_MASK                                                                0x01000000L
37798 #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8_MASK                                                                0x02000000L
37799 #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                                0x04000000L
37800 #define CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE_MASK                                                              0x08000000L
37801 #define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE_MASK                                                                 0x10000000L
37802 #define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK                                                                   0x20000000L
37803 #define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK                                                                 0x40000000L
37804 #define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK                                                                  0x80000000L
37805 //CGTT_IA_CLK_CTRL
37806 #define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT                                                                     0x0
37807 #define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                               0x4
37808 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                         0x10
37809 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                         0x11
37810 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                         0x12
37811 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                         0x13
37812 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                         0x14
37813 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                         0x15
37814 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                         0x16
37815 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                         0x17
37816 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                               0x18
37817 #define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT                                                                  0x19
37818 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                               0x1b
37819 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                               0x1c
37820 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                               0x1d
37821 #define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT                                                                0x1e
37822 #define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT                                                                 0x1f
37823 #define CGTT_IA_CLK_CTRL__ON_DELAY_MASK                                                                       0x0000000FL
37824 #define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                 0x00000FF0L
37825 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                           0x00010000L
37826 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                           0x00020000L
37827 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                           0x00040000L
37828 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                           0x00080000L
37829 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                           0x00100000L
37830 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                           0x00200000L
37831 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                           0x00400000L
37832 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                           0x00800000L
37833 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                                 0x01000000L
37834 #define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK                                                                    0x02000000L
37835 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                                 0x08000000L
37836 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                                 0x10000000L
37837 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                                 0x20000000L
37838 #define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK                                                                  0x40000000L
37839 #define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK                                                                   0x80000000L
37840 //CGTT_WD_CLK_CTRL
37841 #define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT                                                                     0x0
37842 #define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                               0x4
37843 #define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT                                                                  0xf
37844 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                         0x11
37845 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                         0x12
37846 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                         0x13
37847 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                         0x14
37848 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                         0x15
37849 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                         0x16
37850 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                         0x17
37851 #define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8__SHIFT                                                               0x19
37852 #define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                               0x1a
37853 #define CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT                                                             0x1b
37854 #define CGTT_WD_CLK_CTRL__TESS_OVERRIDE__SHIFT                                                                0x1c
37855 #define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT                                                                0x1d
37856 #define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT                                                          0x1e
37857 #define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT                                                                 0x1f
37858 #define CGTT_WD_CLK_CTRL__ON_DELAY_MASK                                                                       0x0000000FL
37859 #define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                 0x00000FF0L
37860 #define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK                                                                    0x00008000L
37861 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                           0x00020000L
37862 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                           0x00040000L
37863 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                           0x00080000L
37864 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                           0x00100000L
37865 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                           0x00200000L
37866 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                           0x00400000L
37867 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                           0x00800000L
37868 #define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8_MASK                                                                 0x02000000L
37869 #define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                                 0x04000000L
37870 #define CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE_MASK                                                               0x08000000L
37871 #define CGTT_WD_CLK_CTRL__TESS_OVERRIDE_MASK                                                                  0x10000000L
37872 #define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK                                                                  0x20000000L
37873 #define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK                                                            0x40000000L
37874 #define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK                                                                   0x80000000L
37875 //CGTT_GS_NGG_CLK_CTRL
37876 #define CGTT_GS_NGG_CLK_CTRL__ON_DELAY__SHIFT                                                                 0x0
37877 #define CGTT_GS_NGG_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                           0x4
37878 #define CGTT_GS_NGG_CLK_CTRL__PERF_ENABLE__SHIFT                                                              0xf
37879 #define CGTT_GS_NGG_CLK_CTRL__DBG_ENABLE__SHIFT                                                               0x10
37880 #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                     0x11
37881 #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                     0x12
37882 #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                     0x13
37883 #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                     0x14
37884 #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                     0x15
37885 #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                     0x16
37886 #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                     0x17
37887 #define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                           0x18
37888 #define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                           0x19
37889 #define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                           0x1a
37890 #define CGTT_GS_NGG_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT                                                         0x1b
37891 #define CGTT_GS_NGG_CLK_CTRL__GS1_OVERRIDE__SHIFT                                                             0x1c
37892 #define CGTT_GS_NGG_CLK_CTRL__GS0_OVERRIDE__SHIFT                                                             0x1d
37893 #define CGTT_GS_NGG_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT                                                      0x1e
37894 #define CGTT_GS_NGG_CLK_CTRL__REG_OVERRIDE__SHIFT                                                             0x1f
37895 #define CGTT_GS_NGG_CLK_CTRL__ON_DELAY_MASK                                                                   0x0000000FL
37896 #define CGTT_GS_NGG_CLK_CTRL__OFF_HYSTERESIS_MASK                                                             0x00000FF0L
37897 #define CGTT_GS_NGG_CLK_CTRL__PERF_ENABLE_MASK                                                                0x00008000L
37898 #define CGTT_GS_NGG_CLK_CTRL__DBG_ENABLE_MASK                                                                 0x00010000L
37899 #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                       0x00020000L
37900 #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                       0x00040000L
37901 #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                       0x00080000L
37902 #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                       0x00100000L
37903 #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                       0x00200000L
37904 #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                       0x00400000L
37905 #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                       0x00800000L
37906 #define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                             0x01000000L
37907 #define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                             0x02000000L
37908 #define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                             0x04000000L
37909 #define CGTT_GS_NGG_CLK_CTRL__PRIMGEN_OVERRIDE_MASK                                                           0x08000000L
37910 #define CGTT_GS_NGG_CLK_CTRL__GS1_OVERRIDE_MASK                                                               0x10000000L
37911 #define CGTT_GS_NGG_CLK_CTRL__GS0_OVERRIDE_MASK                                                               0x20000000L
37912 #define CGTT_GS_NGG_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK                                                        0x40000000L
37913 #define CGTT_GS_NGG_CLK_CTRL__REG_OVERRIDE_MASK                                                               0x80000000L
37914 //CGTT_PA_CLK_CTRL
37915 #define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT                                                                     0x0
37916 #define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                               0x4
37917 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                         0x10
37918 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                         0x11
37919 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                         0x12
37920 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                         0x13
37921 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                         0x14
37922 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                         0x15
37923 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                         0x16
37924 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                               0x18
37925 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                               0x19
37926 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                               0x1a
37927 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                               0x1b
37928 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                               0x1c
37929 #define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT                                                              0x1d
37930 #define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT                                                              0x1e
37931 #define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT                                                             0x1f
37932 #define CGTT_PA_CLK_CTRL__ON_DELAY_MASK                                                                       0x0000000FL
37933 #define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                 0x00000FF0L
37934 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                           0x00010000L
37935 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                           0x00020000L
37936 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                           0x00040000L
37937 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                           0x00080000L
37938 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                           0x00100000L
37939 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                           0x00200000L
37940 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                           0x00400000L
37941 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                                 0x01000000L
37942 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                                 0x02000000L
37943 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                                 0x04000000L
37944 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                                 0x08000000L
37945 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                                 0x10000000L
37946 #define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK                                                                0x20000000L
37947 #define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK                                                                0x40000000L
37948 #define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK                                                               0x80000000L
37949 //CGTT_SC_CLK_CTRL0
37950 #define CGTT_SC_CLK_CTRL0__ON_DELAY__SHIFT                                                                    0x0
37951 #define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS__SHIFT                                                              0x4
37952 #define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE__SHIFT                                              0x10
37953 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x11
37954 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x12
37955 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x13
37956 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x14
37957 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x15
37958 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x16
37959 #define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE__SHIFT                                                      0x17
37960 #define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE__SHIFT                                                    0x18
37961 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT                                                              0x19
37962 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT                                                              0x1a
37963 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT                                                              0x1b
37964 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT                                                              0x1c
37965 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT                                                              0x1d
37966 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT                                                              0x1e
37967 #define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT                                                            0x1f
37968 #define CGTT_SC_CLK_CTRL0__ON_DELAY_MASK                                                                      0x0000000FL
37969 #define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
37970 #define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE_MASK                                                0x00010000L
37971 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK                                                          0x00020000L
37972 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK                                                          0x00040000L
37973 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK                                                          0x00080000L
37974 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK                                                          0x00100000L
37975 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK                                                          0x00200000L
37976 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK                                                          0x00400000L
37977 #define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE_MASK                                                        0x00800000L
37978 #define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE_MASK                                                      0x01000000L
37979 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5_MASK                                                                0x02000000L
37980 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4_MASK                                                                0x04000000L
37981 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3_MASK                                                                0x08000000L
37982 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2_MASK                                                                0x10000000L
37983 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1_MASK                                                                0x20000000L
37984 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0_MASK                                                                0x40000000L
37985 #define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE_MASK                                                              0x80000000L
37986 //CGTT_SC_CLK_CTRL1
37987 #define CGTT_SC_CLK_CTRL1__ON_DELAY__SHIFT                                                                    0x0
37988 #define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS__SHIFT                                                              0x4
37989 #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE0__SHIFT                                             0x10
37990 #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE__SHIFT                                              0x11
37991 #define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE__SHIFT                                              0x12
37992 #define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE__SHIFT                                     0x13
37993 #define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE__SHIFT                                           0x14
37994 #define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE__SHIFT                                            0x15
37995 #define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE__SHIFT                                                      0x16
37996 #define CGTT_SC_CLK_CTRL1__PBB_WARP_CLK_STALL_OVERRIDE__SHIFT                                                 0x17
37997 #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE0__SHIFT                                                   0x18
37998 #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE__SHIFT                                                    0x19
37999 #define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE__SHIFT                                                    0x1a
38000 #define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE__SHIFT                                           0x1b
38001 #define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE__SHIFT                                                 0x1c
38002 #define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE__SHIFT                                                  0x1d
38003 #define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE__SHIFT                                                            0x1e
38004 #define CGTT_SC_CLK_CTRL1__PBB_WARP_CLK_OVERRIDE__SHIFT                                                       0x1f
38005 #define CGTT_SC_CLK_CTRL1__ON_DELAY_MASK                                                                      0x0000000FL
38006 #define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
38007 #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE0_MASK                                               0x00010000L
38008 #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE_MASK                                                0x00020000L
38009 #define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE_MASK                                                0x00040000L
38010 #define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE_MASK                                       0x00080000L
38011 #define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE_MASK                                             0x00100000L
38012 #define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE_MASK                                              0x00200000L
38013 #define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE_MASK                                                        0x00400000L
38014 #define CGTT_SC_CLK_CTRL1__PBB_WARP_CLK_STALL_OVERRIDE_MASK                                                   0x00800000L
38015 #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE0_MASK                                                     0x01000000L
38016 #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE_MASK                                                      0x02000000L
38017 #define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE_MASK                                                      0x04000000L
38018 #define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE_MASK                                             0x08000000L
38019 #define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE_MASK                                                   0x10000000L
38020 #define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE_MASK                                                    0x20000000L
38021 #define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE_MASK                                                              0x40000000L
38022 #define CGTT_SC_CLK_CTRL1__PBB_WARP_CLK_OVERRIDE_MASK                                                         0x80000000L
38023 //CGTT_SC_CLK_CTRL2
38024 #define CGTT_SC_CLK_CTRL2__ON_DELAY__SHIFT                                                                    0x0
38025 #define CGTT_SC_CLK_CTRL2__OFF_HYSTERESIS__SHIFT                                                              0x4
38026 #define CGTT_SC_CLK_CTRL2__DBR_CLK_OVERRIDE__SHIFT                                                            0x1a
38027 #define CGTT_SC_CLK_CTRL2__SCF_SCB_INTF_CLK_OVERRIDE__SHIFT                                                   0x1b
38028 #define CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE__SHIFT                                                    0x1c
38029 #define CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE__SHIFT                                                     0x1d
38030 #define CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE__SHIFT                                                     0x1e
38031 #define CGTT_SC_CLK_CTRL2__ON_DELAY_MASK                                                                      0x0000000FL
38032 #define CGTT_SC_CLK_CTRL2__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
38033 #define CGTT_SC_CLK_CTRL2__DBR_CLK_OVERRIDE_MASK                                                              0x04000000L
38034 #define CGTT_SC_CLK_CTRL2__SCF_SCB_INTF_CLK_OVERRIDE_MASK                                                     0x08000000L
38035 #define CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE_MASK                                                      0x10000000L
38036 #define CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE_MASK                                                       0x20000000L
38037 #define CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE_MASK                                                       0x40000000L
38038 //CGTT_SQ_CLK_CTRL
38039 #define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT                                                                     0x0
38040 #define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                               0x4
38041 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                         0x10
38042 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                         0x11
38043 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                         0x12
38044 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                         0x13
38045 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                         0x14
38046 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                         0x15
38047 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                         0x16
38048 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                         0x17
38049 #define CGTT_SQ_CLK_CTRL__WCLK2DCLK_OVERRIDE__SHIFT                                                           0x1b
38050 #define CGTT_SQ_CLK_CTRL__WCLK_OVERRIDE__SHIFT                                                                0x1c
38051 #define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE__SHIFT                                                             0x1d
38052 #define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT                                                                0x1e
38053 #define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT                                                                 0x1f
38054 #define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK                                                                       0x0000000FL
38055 #define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                 0x00000FF0L
38056 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                           0x00010000L
38057 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                           0x00020000L
38058 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                           0x00040000L
38059 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                           0x00080000L
38060 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                           0x00100000L
38061 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                           0x00200000L
38062 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                           0x00400000L
38063 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                           0x00800000L
38064 #define CGTT_SQ_CLK_CTRL__WCLK2DCLK_OVERRIDE_MASK                                                             0x08000000L
38065 #define CGTT_SQ_CLK_CTRL__WCLK_OVERRIDE_MASK                                                                  0x10000000L
38066 #define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE_MASK                                                               0x20000000L
38067 #define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK                                                                  0x40000000L
38068 #define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK                                                                   0x80000000L
38069 //CGTT_SQG_CLK_CTRL
38070 #define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
38071 #define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
38072 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
38073 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
38074 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
38075 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
38076 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
38077 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
38078 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
38079 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
38080 #define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT                                                             0x1c
38081 #define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT                                                            0x1d
38082 #define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT                                                               0x1e
38083 #define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT                                                                0x1f
38084 #define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
38085 #define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
38086 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
38087 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
38088 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
38089 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
38090 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
38091 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
38092 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
38093 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
38094 #define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK                                                               0x10000000L
38095 #define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK                                                              0x20000000L
38096 #define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK                                                                 0x40000000L
38097 #define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK                                                                  0x80000000L
38098 //SQ_ALU_CLK_CTRL
38099 #define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA0__SHIFT                                                              0x0
38100 #define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA1__SHIFT                                                              0x10
38101 #define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA0_MASK                                                                0x0000FFFFL
38102 #define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA1_MASK                                                                0xFFFF0000L
38103 //SQ_TEX_CLK_CTRL
38104 #define SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA0__SHIFT                                                              0x0
38105 #define SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA1__SHIFT                                                              0x10
38106 #define SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA0_MASK                                                                0x0000FFFFL
38107 #define SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA1_MASK                                                                0xFFFF0000L
38108 //SQ_LDS_CLK_CTRL
38109 #define SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA0__SHIFT                                                              0x0
38110 #define SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA1__SHIFT                                                              0x10
38111 #define SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA0_MASK                                                                0x0000FFFFL
38112 #define SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA1_MASK                                                                0xFFFF0000L
38113 //CGTT_SX_CLK_CTRL0
38114 #define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT                                                                    0x0
38115 #define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT                                                              0x4
38116 #define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT                                                                    0xc
38117 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
38118 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
38119 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
38120 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
38121 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
38122 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
38123 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
38124 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
38125 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT                                                              0x18
38126 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT                                                              0x19
38127 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT                                                              0x1a
38128 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT                                                              0x1b
38129 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT                                                              0x1c
38130 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT                                                              0x1d
38131 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT                                                              0x1e
38132 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT                                                              0x1f
38133 #define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK                                                                      0x0000000FL
38134 #define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
38135 #define CGTT_SX_CLK_CTRL0__RESERVED_MASK                                                                      0x0000F000L
38136 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
38137 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
38138 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
38139 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
38140 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
38141 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
38142 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
38143 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
38144 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK                                                                0x01000000L
38145 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK                                                                0x02000000L
38146 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK                                                                0x04000000L
38147 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK                                                                0x08000000L
38148 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK                                                                0x10000000L
38149 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK                                                                0x20000000L
38150 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK                                                                0x40000000L
38151 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK                                                                0x80000000L
38152 //CGTT_SX_CLK_CTRL1
38153 #define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT                                                                    0x0
38154 #define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT                                                              0x4
38155 #define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT                                                                    0xc
38156 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
38157 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
38158 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
38159 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
38160 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
38161 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
38162 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
38163 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
38164 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT                                                              0x19
38165 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT                                                              0x1a
38166 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT                                                              0x1b
38167 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT                                                              0x1c
38168 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT                                                              0x1d
38169 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT                                                              0x1e
38170 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT                                                              0x1f
38171 #define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK                                                                      0x0000000FL
38172 #define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
38173 #define CGTT_SX_CLK_CTRL1__RESERVED_MASK                                                                      0x0000F000L
38174 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
38175 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
38176 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
38177 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
38178 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
38179 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
38180 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
38181 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
38182 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK                                                                0x02000000L
38183 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK                                                                0x04000000L
38184 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK                                                                0x08000000L
38185 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK                                                                0x10000000L
38186 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK                                                                0x20000000L
38187 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK                                                                0x40000000L
38188 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK                                                                0x80000000L
38189 //CGTT_SX_CLK_CTRL2
38190 #define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT                                                                    0x0
38191 #define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT                                                              0x4
38192 #define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT                                                                    0xd
38193 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
38194 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
38195 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
38196 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
38197 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
38198 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
38199 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
38200 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
38201 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT                                                              0x19
38202 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT                                                              0x1a
38203 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT                                                              0x1b
38204 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT                                                              0x1c
38205 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT                                                              0x1d
38206 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT                                                              0x1e
38207 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT                                                              0x1f
38208 #define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK                                                                      0x0000000FL
38209 #define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
38210 #define CGTT_SX_CLK_CTRL2__RESERVED_MASK                                                                      0x0000E000L
38211 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
38212 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
38213 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
38214 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
38215 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
38216 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
38217 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
38218 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
38219 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK                                                                0x02000000L
38220 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK                                                                0x04000000L
38221 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK                                                                0x08000000L
38222 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK                                                                0x10000000L
38223 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK                                                                0x20000000L
38224 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK                                                                0x40000000L
38225 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK                                                                0x80000000L
38226 //CGTT_SX_CLK_CTRL3
38227 #define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT                                                                    0x0
38228 #define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT                                                              0x4
38229 #define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT                                                                    0xd
38230 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
38231 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
38232 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
38233 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
38234 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
38235 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
38236 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
38237 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
38238 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT                                                              0x19
38239 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT                                                              0x1a
38240 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT                                                              0x1b
38241 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT                                                              0x1c
38242 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT                                                              0x1d
38243 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT                                                              0x1e
38244 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT                                                              0x1f
38245 #define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK                                                                      0x0000000FL
38246 #define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
38247 #define CGTT_SX_CLK_CTRL3__RESERVED_MASK                                                                      0x0000E000L
38248 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
38249 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
38250 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
38251 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
38252 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
38253 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
38254 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
38255 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
38256 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK                                                                0x02000000L
38257 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK                                                                0x04000000L
38258 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK                                                                0x08000000L
38259 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK                                                                0x10000000L
38260 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK                                                                0x20000000L
38261 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK                                                                0x40000000L
38262 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK                                                                0x80000000L
38263 //CGTT_SX_CLK_CTRL4
38264 #define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT                                                                    0x0
38265 #define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT                                                              0x4
38266 #define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT                                                                    0xc
38267 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
38268 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
38269 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
38270 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
38271 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
38272 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
38273 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
38274 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
38275 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT                                                              0x19
38276 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT                                                              0x1a
38277 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT                                                              0x1b
38278 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT                                                              0x1c
38279 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT                                                              0x1d
38280 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT                                                              0x1e
38281 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT                                                              0x1f
38282 #define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK                                                                      0x0000000FL
38283 #define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
38284 #define CGTT_SX_CLK_CTRL4__RESERVED_MASK                                                                      0x0000F000L
38285 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
38286 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
38287 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
38288 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
38289 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
38290 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
38291 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
38292 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
38293 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK                                                                0x02000000L
38294 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK                                                                0x04000000L
38295 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK                                                                0x08000000L
38296 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK                                                                0x10000000L
38297 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK                                                                0x20000000L
38298 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK                                                                0x40000000L
38299 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK                                                                0x80000000L
38300 //TD_CGTT_CTRL
38301 #define TD_CGTT_CTRL__ON_DELAY__SHIFT                                                                         0x0
38302 #define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT                                                                   0x4
38303 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                             0x10
38304 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                             0x11
38305 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                             0x12
38306 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                             0x13
38307 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                             0x14
38308 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                             0x15
38309 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                             0x16
38310 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                             0x17
38311 #define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT                                                                   0x18
38312 #define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT                                                                   0x19
38313 #define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT                                                                   0x1a
38314 #define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT                                                                   0x1b
38315 #define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT                                                                   0x1c
38316 #define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT                                                                   0x1d
38317 #define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT                                                                   0x1e
38318 #define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT                                                                   0x1f
38319 #define TD_CGTT_CTRL__ON_DELAY_MASK                                                                           0x0000000FL
38320 #define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK                                                                     0x00000FF0L
38321 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                               0x00010000L
38322 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                               0x00020000L
38323 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                               0x00040000L
38324 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                               0x00080000L
38325 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                               0x00100000L
38326 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                               0x00200000L
38327 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                               0x00400000L
38328 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                               0x00800000L
38329 #define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK                                                                     0x01000000L
38330 #define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK                                                                     0x02000000L
38331 #define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK                                                                     0x04000000L
38332 #define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK                                                                     0x08000000L
38333 #define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK                                                                     0x10000000L
38334 #define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK                                                                     0x20000000L
38335 #define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK                                                                     0x40000000L
38336 #define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK                                                                     0x80000000L
38337 //TA_CGTT_CTRL
38338 #define TA_CGTT_CTRL__ON_DELAY__SHIFT                                                                         0x0
38339 #define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT                                                                   0x4
38340 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                             0x10
38341 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                             0x11
38342 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                             0x12
38343 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                             0x13
38344 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                             0x14
38345 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                             0x15
38346 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                             0x16
38347 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                             0x17
38348 #define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT                                                                   0x18
38349 #define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT                                                                   0x19
38350 #define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT                                                                   0x1a
38351 #define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT                                                                   0x1b
38352 #define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT                                                                   0x1c
38353 #define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT                                                                   0x1d
38354 #define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT                                                                   0x1e
38355 #define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT                                                                   0x1f
38356 #define TA_CGTT_CTRL__ON_DELAY_MASK                                                                           0x0000000FL
38357 #define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK                                                                     0x00000FF0L
38358 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                               0x00010000L
38359 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                               0x00020000L
38360 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                               0x00040000L
38361 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                               0x00080000L
38362 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                               0x00100000L
38363 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                               0x00200000L
38364 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                               0x00400000L
38365 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                               0x00800000L
38366 #define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK                                                                     0x01000000L
38367 #define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK                                                                     0x02000000L
38368 #define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK                                                                     0x04000000L
38369 #define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK                                                                     0x08000000L
38370 #define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK                                                                     0x10000000L
38371 #define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK                                                                     0x20000000L
38372 #define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK                                                                     0x40000000L
38373 #define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK                                                                     0x80000000L
38374 //CGTT_TCPI_CLK_CTRL
38375 #define CGTT_TCPI_CLK_CTRL__ON_DELAY__SHIFT                                                                   0x0
38376 #define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                             0x4
38377 #define CGTT_TCPI_CLK_CTRL__SPARE__SHIFT                                                                      0xc
38378 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                       0x10
38379 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                       0x11
38380 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                       0x12
38381 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                       0x13
38382 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                       0x14
38383 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                       0x15
38384 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                       0x16
38385 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                       0x17
38386 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                             0x18
38387 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                             0x19
38388 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                             0x1a
38389 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                             0x1b
38390 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                             0x1c
38391 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                             0x1d
38392 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                             0x1e
38393 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                             0x1f
38394 #define CGTT_TCPI_CLK_CTRL__ON_DELAY_MASK                                                                     0x0000000FL
38395 #define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS_MASK                                                               0x00000FF0L
38396 #define CGTT_TCPI_CLK_CTRL__SPARE_MASK                                                                        0x0000F000L
38397 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                         0x00010000L
38398 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                         0x00020000L
38399 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                         0x00040000L
38400 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                         0x00080000L
38401 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                         0x00100000L
38402 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                         0x00200000L
38403 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                         0x00400000L
38404 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                         0x00800000L
38405 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                               0x01000000L
38406 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                               0x02000000L
38407 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                               0x04000000L
38408 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                               0x08000000L
38409 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                               0x10000000L
38410 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                               0x20000000L
38411 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1_MASK                                                               0x40000000L
38412 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0_MASK                                                               0x80000000L
38413 //CGTT_TCI_CLK_CTRL
38414 #define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
38415 #define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
38416 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
38417 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
38418 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
38419 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
38420 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
38421 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
38422 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
38423 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
38424 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                              0x18
38425 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                              0x19
38426 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                              0x1a
38427 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                              0x1b
38428 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                              0x1c
38429 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                              0x1d
38430 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                              0x1e
38431 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                              0x1f
38432 #define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
38433 #define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
38434 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
38435 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
38436 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
38437 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
38438 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
38439 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
38440 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
38441 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
38442 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                                0x01000000L
38443 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                                0x02000000L
38444 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                                0x04000000L
38445 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                                0x08000000L
38446 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                                0x10000000L
38447 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                                0x20000000L
38448 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK                                                                0x40000000L
38449 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK                                                                0x80000000L
38450 //CGTT_GDS_CLK_CTRL
38451 #define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
38452 #define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
38453 #define CGTT_GDS_CLK_CTRL__UNUSED__SHIFT                                                                      0xc
38454 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
38455 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
38456 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
38457 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
38458 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
38459 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
38460 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
38461 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
38462 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                              0x18
38463 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                              0x19
38464 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                              0x1a
38465 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                              0x1b
38466 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                              0x1c
38467 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                              0x1d
38468 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                              0x1e
38469 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                              0x1f
38470 #define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
38471 #define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
38472 #define CGTT_GDS_CLK_CTRL__UNUSED_MASK                                                                        0x0000F000L
38473 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
38474 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
38475 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
38476 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
38477 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
38478 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
38479 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
38480 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
38481 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                                0x01000000L
38482 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                                0x02000000L
38483 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                                0x04000000L
38484 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                                0x08000000L
38485 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                                0x10000000L
38486 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                                0x20000000L
38487 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK                                                                0x40000000L
38488 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK                                                                0x80000000L
38489 //DB_CGTT_CLK_CTRL_0
38490 #define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT                                                                   0x0
38491 #define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT                                                             0x4
38492 #define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT                                                                   0xc
38493 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7__SHIFT                                                       0x10
38494 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6__SHIFT                                                       0x11
38495 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5__SHIFT                                                       0x12
38496 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4__SHIFT                                                       0x13
38497 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3__SHIFT                                                       0x14
38498 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2__SHIFT                                                       0x15
38499 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1__SHIFT                                                       0x16
38500 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0__SHIFT                                                       0x17
38501 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT                                                             0x18
38502 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT                                                             0x19
38503 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT                                                             0x1a
38504 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT                                                             0x1b
38505 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT                                                             0x1c
38506 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT                                                             0x1d
38507 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT                                                             0x1e
38508 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT                                                             0x1f
38509 #define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK                                                                     0x0000000FL
38510 #define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK                                                               0x00000FF0L
38511 #define DB_CGTT_CLK_CTRL_0__RESERVED_MASK                                                                     0x0000F000L
38512 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7_MASK                                                         0x00010000L
38513 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6_MASK                                                         0x00020000L
38514 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5_MASK                                                         0x00040000L
38515 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4_MASK                                                         0x00080000L
38516 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3_MASK                                                         0x00100000L
38517 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2_MASK                                                         0x00200000L
38518 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1_MASK                                                         0x00400000L
38519 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0_MASK                                                         0x00800000L
38520 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK                                                               0x01000000L
38521 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK                                                               0x02000000L
38522 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK                                                               0x04000000L
38523 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK                                                               0x08000000L
38524 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK                                                               0x10000000L
38525 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK                                                               0x20000000L
38526 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK                                                               0x40000000L
38527 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK                                                               0x80000000L
38528 //CB_CGTT_SCLK_CTRL
38529 #define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
38530 #define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
38531 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
38532 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
38533 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
38534 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
38535 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
38536 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
38537 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
38538 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
38539 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                              0x18
38540 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                              0x19
38541 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                              0x1a
38542 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                              0x1b
38543 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                              0x1c
38544 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                              0x1d
38545 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                              0x1e
38546 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                              0x1f
38547 #define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
38548 #define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
38549 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
38550 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
38551 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
38552 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
38553 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
38554 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
38555 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
38556 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
38557 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK                                                                0x01000000L
38558 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK                                                                0x02000000L
38559 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK                                                                0x04000000L
38560 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK                                                                0x08000000L
38561 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK                                                                0x10000000L
38562 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK                                                                0x20000000L
38563 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK                                                                0x40000000L
38564 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK                                                                0x80000000L
38565 //GL2C_CGTT_SCLK_CTRL
38566 #define GL2C_CGTT_SCLK_CTRL__ON_DELAY__SHIFT                                                                  0x0
38567 #define GL2C_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT                                                            0x4
38568 #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                      0x10
38569 #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                      0x11
38570 #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                      0x12
38571 #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                      0x13
38572 #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                      0x14
38573 #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                      0x15
38574 #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                      0x16
38575 #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                      0x17
38576 #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                            0x18
38577 #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                            0x19
38578 #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                            0x1a
38579 #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                            0x1b
38580 #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                            0x1c
38581 #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                            0x1d
38582 #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                            0x1e
38583 #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                            0x1f
38584 #define GL2C_CGTT_SCLK_CTRL__ON_DELAY_MASK                                                                    0x0000000FL
38585 #define GL2C_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK                                                              0x00000FF0L
38586 #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                        0x00010000L
38587 #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                        0x00020000L
38588 #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                        0x00040000L
38589 #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                        0x00080000L
38590 #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                        0x00100000L
38591 #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                        0x00200000L
38592 #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                        0x00400000L
38593 #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                        0x00800000L
38594 #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK                                                              0x01000000L
38595 #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK                                                              0x02000000L
38596 #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK                                                              0x04000000L
38597 #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK                                                              0x08000000L
38598 #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK                                                              0x10000000L
38599 #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK                                                              0x20000000L
38600 #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK                                                              0x40000000L
38601 #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK                                                              0x80000000L
38602 //GL2A_CGTT_SCLK_CTRL
38603 #define GL2A_CGTT_SCLK_CTRL__ON_DELAY__SHIFT                                                                  0x0
38604 #define GL2A_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT                                                            0x4
38605 #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                      0x10
38606 #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                      0x11
38607 #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                      0x12
38608 #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                      0x13
38609 #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                      0x14
38610 #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                      0x15
38611 #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                      0x16
38612 #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                      0x17
38613 #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                            0x18
38614 #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                            0x19
38615 #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                            0x1a
38616 #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                            0x1b
38617 #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                            0x1c
38618 #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                            0x1d
38619 #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                            0x1e
38620 #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                            0x1f
38621 #define GL2A_CGTT_SCLK_CTRL__ON_DELAY_MASK                                                                    0x0000000FL
38622 #define GL2A_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK                                                              0x00000FF0L
38623 #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                        0x00010000L
38624 #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                        0x00020000L
38625 #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                        0x00040000L
38626 #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                        0x00080000L
38627 #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                        0x00100000L
38628 #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                        0x00200000L
38629 #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                        0x00400000L
38630 #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                        0x00800000L
38631 #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK                                                              0x01000000L
38632 #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK                                                              0x02000000L
38633 #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK                                                              0x04000000L
38634 #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK                                                              0x08000000L
38635 #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK                                                              0x10000000L
38636 #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK                                                              0x20000000L
38637 #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK                                                              0x40000000L
38638 #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK                                                              0x80000000L
38639 //GL2A_CGTT_SCLK_CTRL_1
38640 #define GL2A_CGTT_SCLK_CTRL_1__ON_DELAY__SHIFT                                                                0x0
38641 #define GL2A_CGTT_SCLK_CTRL_1__OFF_HYSTERESIS__SHIFT                                                          0x4
38642 #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE7__SHIFT                                                    0x10
38643 #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE6__SHIFT                                                    0x11
38644 #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE5__SHIFT                                                    0x12
38645 #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE4__SHIFT                                                    0x13
38646 #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE3__SHIFT                                                    0x14
38647 #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE2__SHIFT                                                    0x15
38648 #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE1__SHIFT                                                    0x16
38649 #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE0__SHIFT                                                    0x17
38650 #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE7__SHIFT                                                          0x18
38651 #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE6__SHIFT                                                          0x19
38652 #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE5__SHIFT                                                          0x1a
38653 #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE4__SHIFT                                                          0x1b
38654 #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE3__SHIFT                                                          0x1c
38655 #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE2__SHIFT                                                          0x1d
38656 #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE1__SHIFT                                                          0x1e
38657 #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE0__SHIFT                                                          0x1f
38658 #define GL2A_CGTT_SCLK_CTRL_1__ON_DELAY_MASK                                                                  0x0000000FL
38659 #define GL2A_CGTT_SCLK_CTRL_1__OFF_HYSTERESIS_MASK                                                            0x00000FF0L
38660 #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE7_MASK                                                      0x00010000L
38661 #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE6_MASK                                                      0x00020000L
38662 #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE5_MASK                                                      0x00040000L
38663 #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE4_MASK                                                      0x00080000L
38664 #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE3_MASK                                                      0x00100000L
38665 #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE2_MASK                                                      0x00200000L
38666 #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE1_MASK                                                      0x00400000L
38667 #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE0_MASK                                                      0x00800000L
38668 #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE7_MASK                                                            0x01000000L
38669 #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE6_MASK                                                            0x02000000L
38670 #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE5_MASK                                                            0x04000000L
38671 #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE4_MASK                                                            0x08000000L
38672 #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE3_MASK                                                            0x10000000L
38673 #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE2_MASK                                                            0x20000000L
38674 #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE1_MASK                                                            0x40000000L
38675 #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE0_MASK                                                            0x80000000L
38676 //CGTT_CP_CLK_CTRL
38677 #define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT                                                                     0x0
38678 #define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                               0x4
38679 #define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                                0xf
38680 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                         0x10
38681 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                         0x11
38682 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                         0x12
38683 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                         0x13
38684 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                         0x14
38685 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                         0x15
38686 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                         0x16
38687 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                         0x17
38688 #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT                                                        0x1d
38689 #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT                                                            0x1e
38690 #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT                                                            0x1f
38691 #define CGTT_CP_CLK_CTRL__ON_DELAY_MASK                                                                       0x0000000FL
38692 #define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                 0x00000FF0L
38693 #define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE_MASK                                                                  0x00008000L
38694 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                           0x00010000L
38695 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                           0x00020000L
38696 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                           0x00040000L
38697 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                           0x00080000L
38698 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                           0x00100000L
38699 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                           0x00200000L
38700 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                           0x00400000L
38701 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                           0x00800000L
38702 #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK                                                          0x20000000L
38703 #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK                                                              0x40000000L
38704 #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK                                                              0x80000000L
38705 //CGTT_CPF_CLK_CTRL
38706 #define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
38707 #define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
38708 #define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                               0xf
38709 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
38710 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
38711 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
38712 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
38713 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
38714 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
38715 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
38716 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
38717 #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT                                                       0x1a
38718 #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PRT__SHIFT                                                           0x1b
38719 #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_CMP__SHIFT                                                           0x1c
38720 #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_GFX__SHIFT                                                           0x1d
38721 #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT                                                           0x1e
38722 #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT                                                           0x1f
38723 #define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
38724 #define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
38725 #define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE_MASK                                                                 0x00008000L
38726 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
38727 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
38728 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
38729 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
38730 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
38731 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
38732 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
38733 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
38734 #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK                                                         0x04000000L
38735 #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PRT_MASK                                                             0x08000000L
38736 #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_CMP_MASK                                                             0x10000000L
38737 #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_GFX_MASK                                                             0x20000000L
38738 #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK                                                             0x40000000L
38739 #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK                                                             0x80000000L
38740 //CGTT_CPC_CLK_CTRL
38741 #define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
38742 #define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
38743 #define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                               0xf
38744 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
38745 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
38746 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
38747 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
38748 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
38749 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
38750 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
38751 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
38752 #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT                                                       0x1d
38753 #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT                                                           0x1e
38754 #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT                                                           0x1f
38755 #define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
38756 #define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
38757 #define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE_MASK                                                                 0x00008000L
38758 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
38759 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
38760 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
38761 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
38762 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
38763 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
38764 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
38765 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
38766 #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK                                                         0x20000000L
38767 #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK                                                             0x40000000L
38768 #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK                                                             0x80000000L
38769 //CGTT_RLC_CLK_CTRL
38770 #define CGTT_RLC_CLK_CTRL__RESERVED__SHIFT                                                                    0x0
38771 #define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
38772 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
38773 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
38774 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
38775 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
38776 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
38777 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
38778 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
38779 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
38780 #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT                                                           0x1e
38781 #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT                                                           0x1f
38782 #define CGTT_RLC_CLK_CTRL__RESERVED_MASK                                                                      0x0000000FL
38783 #define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
38784 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
38785 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
38786 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
38787 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
38788 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
38789 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
38790 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
38791 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
38792 #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK                                                             0x40000000L
38793 #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK                                                             0x80000000L
38794 //RLC_GFX_RM_CNTL
38795 #define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID__SHIFT                                                              0x0
38796 #define RLC_GFX_RM_CNTL__RESERVED__SHIFT                                                                      0x1
38797 #define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID_MASK                                                                0x00000001L
38798 #define RLC_GFX_RM_CNTL__RESERVED_MASK                                                                        0xFFFFFFFEL
38799 //RMI_CGTT_SCLK_CTRL
38800 #define RMI_CGTT_SCLK_CTRL__ON_DELAY__SHIFT                                                                   0x0
38801 #define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT                                                             0x4
38802 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                       0x10
38803 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                       0x11
38804 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                       0x12
38805 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                       0x13
38806 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                       0x14
38807 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                       0x15
38808 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                       0x16
38809 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                       0x17
38810 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                             0x19
38811 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                             0x1a
38812 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                             0x1b
38813 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                             0x1c
38814 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                             0x1d
38815 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                             0x1e
38816 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                             0x1f
38817 #define RMI_CGTT_SCLK_CTRL__ON_DELAY_MASK                                                                     0x0000000FL
38818 #define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK                                                               0x00000FF0L
38819 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                         0x00010000L
38820 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                         0x00020000L
38821 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                         0x00040000L
38822 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                         0x00080000L
38823 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                         0x00100000L
38824 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                         0x00200000L
38825 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                         0x00400000L
38826 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                         0x00800000L
38827 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK                                                               0x02000000L
38828 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK                                                               0x04000000L
38829 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK                                                               0x08000000L
38830 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK                                                               0x10000000L
38831 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK                                                               0x20000000L
38832 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK                                                               0x40000000L
38833 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK                                                               0x80000000L
38834 //CGTT_TCPF_CLK_CTRL
38835 #define CGTT_TCPF_CLK_CTRL__ON_DELAY__SHIFT                                                                   0x0
38836 #define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                             0x4
38837 #define CGTT_TCPF_CLK_CTRL__SPARE__SHIFT                                                                      0xc
38838 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                       0x10
38839 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                       0x11
38840 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                       0x12
38841 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                       0x13
38842 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                       0x14
38843 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                       0x15
38844 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                       0x16
38845 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                       0x17
38846 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                             0x18
38847 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                             0x19
38848 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                             0x1a
38849 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                             0x1b
38850 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                             0x1c
38851 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                             0x1d
38852 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                             0x1e
38853 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                             0x1f
38854 #define CGTT_TCPF_CLK_CTRL__ON_DELAY_MASK                                                                     0x0000000FL
38855 #define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS_MASK                                                               0x00000FF0L
38856 #define CGTT_TCPF_CLK_CTRL__SPARE_MASK                                                                        0x0000F000L
38857 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                         0x00010000L
38858 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                         0x00020000L
38859 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                         0x00040000L
38860 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                         0x00080000L
38861 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                         0x00100000L
38862 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                         0x00200000L
38863 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                         0x00400000L
38864 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                         0x00800000L
38865 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                               0x01000000L
38866 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                               0x02000000L
38867 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                               0x04000000L
38868 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                               0x08000000L
38869 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                               0x10000000L
38870 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                               0x20000000L
38871 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1_MASK                                                               0x40000000L
38872 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0_MASK                                                               0x80000000L
38873 //GCR_CGTT_SCLK_CTRL
38874 #define GCR_CGTT_SCLK_CTRL__ON_DELAY__SHIFT                                                                   0x0
38875 #define GCR_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT                                                             0x4
38876 #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                       0x10
38877 #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                       0x11
38878 #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                       0x12
38879 #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                       0x13
38880 #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                       0x14
38881 #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                       0x15
38882 #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                       0x16
38883 #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                       0x17
38884 #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                             0x19
38885 #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                             0x1a
38886 #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                             0x1b
38887 #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                             0x1c
38888 #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                             0x1d
38889 #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                             0x1e
38890 #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                             0x1f
38891 #define GCR_CGTT_SCLK_CTRL__ON_DELAY_MASK                                                                     0x0000000FL
38892 #define GCR_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK                                                               0x00000FF0L
38893 #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                         0x00010000L
38894 #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                         0x00020000L
38895 #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                         0x00040000L
38896 #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                         0x00080000L
38897 #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                         0x00100000L
38898 #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                         0x00200000L
38899 #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                         0x00400000L
38900 #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                         0x00800000L
38901 #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK                                                               0x02000000L
38902 #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK                                                               0x04000000L
38903 #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK                                                               0x08000000L
38904 #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK                                                               0x10000000L
38905 #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK                                                               0x20000000L
38906 #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK                                                               0x40000000L
38907 #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK                                                               0x80000000L
38908 //UTCL1_CGTT_CLK_CTRL
38909 #define UTCL1_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                  0x0
38910 #define UTCL1_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                            0x4
38911 #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                      0x10
38912 #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                      0x11
38913 #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                      0x12
38914 #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                      0x13
38915 #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                      0x14
38916 #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                      0x15
38917 #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                      0x16
38918 #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                      0x17
38919 #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                            0x19
38920 #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                            0x1a
38921 #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                            0x1b
38922 #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                            0x1c
38923 #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                            0x1d
38924 #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                            0x1e
38925 #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                            0x1f
38926 #define UTCL1_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                    0x0000000FL
38927 #define UTCL1_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                              0x00000FF0L
38928 #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                        0x00010000L
38929 #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                        0x00020000L
38930 #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                        0x00040000L
38931 #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                        0x00080000L
38932 #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                        0x00100000L
38933 #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                        0x00200000L
38934 #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                        0x00400000L
38935 #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                        0x00800000L
38936 #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                              0x02000000L
38937 #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                              0x04000000L
38938 #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                              0x08000000L
38939 #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                              0x10000000L
38940 #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                              0x20000000L
38941 #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE1_MASK                                                              0x40000000L
38942 #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE0_MASK                                                              0x80000000L
38943 //GCEA_CGTT_CLK_CTRL
38944 #define GCEA_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                   0x0
38945 #define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                             0x4
38946 #define GCEA_CGTT_CLK_CTRL__SPARE0__SHIFT                                                                     0xc
38947 #define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT                                                  0x14
38948 #define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT                                                   0x15
38949 #define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT                                                 0x16
38950 #define GCEA_CGTT_CLK_CTRL__SPARE1__SHIFT                                                                     0x17
38951 #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT                                                        0x1c
38952 #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT                                                         0x1d
38953 #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT                                                       0x1e
38954 #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT                                                     0x1f
38955 #define GCEA_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                     0x0000000FL
38956 #define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                               0x00000FF0L
38957 #define GCEA_CGTT_CLK_CTRL__SPARE0_MASK                                                                       0x000FF000L
38958 #define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK                                                    0x00100000L
38959 #define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK                                                     0x00200000L
38960 #define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK                                                   0x00400000L
38961 #define GCEA_CGTT_CLK_CTRL__SPARE1_MASK                                                                       0x0F800000L
38962 #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK                                                          0x10000000L
38963 #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK                                                           0x20000000L
38964 #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK                                                         0x40000000L
38965 #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK                                                       0x80000000L
38966 //SE_CAC_CGTT_CLK_CTRL
38967 #define SE_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                 0x0
38968 #define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                           0x4
38969 #define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT                                                        0x1e
38970 #define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT                                                        0x1f
38971 #define SE_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                   0x0000000FL
38972 #define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                             0x00000FF0L
38973 #define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK                                                          0x40000000L
38974 #define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK                                                          0x80000000L
38975 //GC_CAC_CGTT_CLK_CTRL
38976 #define GC_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                 0x0
38977 #define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                           0x4
38978 #define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT                                                        0x1e
38979 #define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT                                                        0x1f
38980 #define GC_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                   0x0000000FL
38981 #define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                             0x00000FF0L
38982 #define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK                                                          0x40000000L
38983 #define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK                                                          0x80000000L
38984 //GRBM_CGTT_CLK_CNTL
38985 #define GRBM_CGTT_CLK_CNTL__ON_DELAY__SHIFT                                                                   0x0
38986 #define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS__SHIFT                                                             0x4
38987 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7__SHIFT                                                       0x10
38988 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6__SHIFT                                                       0x11
38989 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5__SHIFT                                                       0x12
38990 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4__SHIFT                                                       0x13
38991 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3__SHIFT                                                       0x14
38992 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2__SHIFT                                                       0x15
38993 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1__SHIFT                                                       0x16
38994 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0__SHIFT                                                       0x17
38995 #define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN__SHIFT                                                          0x1e
38996 #define GRBM_CGTT_CLK_CNTL__ON_DELAY_MASK                                                                     0x0000000FL
38997 #define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS_MASK                                                               0x00000FF0L
38998 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7_MASK                                                         0x00010000L
38999 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6_MASK                                                         0x00020000L
39000 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5_MASK                                                         0x00040000L
39001 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4_MASK                                                         0x00080000L
39002 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3_MASK                                                         0x00100000L
39003 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2_MASK                                                         0x00200000L
39004 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1_MASK                                                         0x00400000L
39005 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0_MASK                                                         0x00800000L
39006 #define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN_MASK                                                            0x40000000L
39007 //CGTT_GL1C_CLK_CTRL
39008 #define CGTT_GL1C_CLK_CTRL__ON_DELAY__SHIFT                                                                   0x0
39009 #define CGTT_GL1C_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                             0x4
39010 #define CGTT_GL1C_CLK_CTRL__RESERVED__SHIFT                                                                   0xc
39011 #define CGTT_GL1C_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                              0xf
39012 #define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                       0x10
39013 #define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                       0x11
39014 #define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                       0x12
39015 #define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                       0x13
39016 #define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                       0x14
39017 #define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                       0x15
39018 #define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                       0x16
39019 #define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                       0x17
39020 #define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                             0x18
39021 #define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                             0x19
39022 #define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                             0x1a
39023 #define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                             0x1b
39024 #define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                             0x1c
39025 #define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                             0x1d
39026 #define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                             0x1e
39027 #define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                             0x1f
39028 #define CGTT_GL1C_CLK_CTRL__ON_DELAY_MASK                                                                     0x0000000FL
39029 #define CGTT_GL1C_CLK_CTRL__OFF_HYSTERESIS_MASK                                                               0x00000FF0L
39030 #define CGTT_GL1C_CLK_CTRL__RESERVED_MASK                                                                     0x00007000L
39031 #define CGTT_GL1C_CLK_CTRL__MGLS_OVERRIDE_MASK                                                                0x00008000L
39032 #define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                         0x00010000L
39033 #define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                         0x00020000L
39034 #define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                         0x00040000L
39035 #define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                         0x00080000L
39036 #define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                         0x00100000L
39037 #define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                         0x00200000L
39038 #define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                         0x00400000L
39039 #define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                         0x00800000L
39040 #define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                               0x01000000L
39041 #define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                               0x02000000L
39042 #define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                               0x04000000L
39043 #define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                               0x08000000L
39044 #define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                               0x10000000L
39045 #define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                               0x20000000L
39046 #define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE1_MASK                                                               0x40000000L
39047 #define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE0_MASK                                                               0x80000000L
39048 //CGTT_CHC_CLK_CTRL
39049 #define CGTT_CHC_CLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
39050 #define CGTT_CHC_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
39051 #define CGTT_CHC_CLK_CTRL__RESERVED__SHIFT                                                                    0xc
39052 #define CGTT_CHC_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                               0xf
39053 #define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
39054 #define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
39055 #define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
39056 #define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
39057 #define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
39058 #define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
39059 #define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
39060 #define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
39061 #define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                              0x18
39062 #define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                              0x19
39063 #define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                              0x1a
39064 #define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                              0x1b
39065 #define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                              0x1c
39066 #define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                              0x1d
39067 #define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                              0x1e
39068 #define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                              0x1f
39069 #define CGTT_CHC_CLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
39070 #define CGTT_CHC_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
39071 #define CGTT_CHC_CLK_CTRL__RESERVED_MASK                                                                      0x00007000L
39072 #define CGTT_CHC_CLK_CTRL__MGLS_OVERRIDE_MASK                                                                 0x00008000L
39073 #define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
39074 #define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
39075 #define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
39076 #define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
39077 #define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
39078 #define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
39079 #define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
39080 #define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
39081 #define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                                0x01000000L
39082 #define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                                0x02000000L
39083 #define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                                0x04000000L
39084 #define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                                0x08000000L
39085 #define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                                0x10000000L
39086 #define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                                0x20000000L
39087 #define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE1_MASK                                                                0x40000000L
39088 #define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE0_MASK                                                                0x80000000L
39089 //CGTT_CHCG_CLK_CTRL
39090 #define CGTT_CHCG_CLK_CTRL__ON_DELAY__SHIFT                                                                   0x0
39091 #define CGTT_CHCG_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                             0x4
39092 #define CGTT_CHCG_CLK_CTRL__RESERVED__SHIFT                                                                   0xc
39093 #define CGTT_CHCG_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                              0xf
39094 #define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                       0x10
39095 #define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                       0x11
39096 #define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                       0x12
39097 #define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                       0x13
39098 #define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                       0x14
39099 #define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                       0x15
39100 #define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                       0x16
39101 #define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                       0x17
39102 #define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                             0x18
39103 #define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                             0x19
39104 #define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                             0x1a
39105 #define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                             0x1b
39106 #define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                             0x1c
39107 #define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                             0x1d
39108 #define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                             0x1e
39109 #define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                             0x1f
39110 #define CGTT_CHCG_CLK_CTRL__ON_DELAY_MASK                                                                     0x0000000FL
39111 #define CGTT_CHCG_CLK_CTRL__OFF_HYSTERESIS_MASK                                                               0x00000FF0L
39112 #define CGTT_CHCG_CLK_CTRL__RESERVED_MASK                                                                     0x00007000L
39113 #define CGTT_CHCG_CLK_CTRL__MGLS_OVERRIDE_MASK                                                                0x00008000L
39114 #define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                         0x00010000L
39115 #define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                         0x00020000L
39116 #define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                         0x00040000L
39117 #define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                         0x00080000L
39118 #define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                         0x00100000L
39119 #define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                         0x00200000L
39120 #define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                         0x00400000L
39121 #define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                         0x00800000L
39122 #define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                               0x01000000L
39123 #define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                               0x02000000L
39124 #define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                               0x04000000L
39125 #define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                               0x08000000L
39126 #define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                               0x10000000L
39127 #define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                               0x20000000L
39128 #define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE1_MASK                                                               0x40000000L
39129 #define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE0_MASK                                                               0x80000000L
39130 //CGTT_GL1A_CLK_CTRL
39131 #define CGTT_GL1A_CLK_CTRL__ON_DELAY__SHIFT                                                                   0x0
39132 #define CGTT_GL1A_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                             0x4
39133 #define CGTT_GL1A_CLK_CTRL__RESERVED__SHIFT                                                                   0xc
39134 #define CGTT_GL1A_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                              0xf
39135 #define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                       0x10
39136 #define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                       0x11
39137 #define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                       0x12
39138 #define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                       0x13
39139 #define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                       0x14
39140 #define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                       0x15
39141 #define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                       0x16
39142 #define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                       0x17
39143 #define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                             0x18
39144 #define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                             0x19
39145 #define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                             0x1a
39146 #define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                             0x1b
39147 #define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                             0x1c
39148 #define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                             0x1d
39149 #define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                             0x1e
39150 #define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                             0x1f
39151 #define CGTT_GL1A_CLK_CTRL__ON_DELAY_MASK                                                                     0x0000000FL
39152 #define CGTT_GL1A_CLK_CTRL__OFF_HYSTERESIS_MASK                                                               0x00000FF0L
39153 #define CGTT_GL1A_CLK_CTRL__RESERVED_MASK                                                                     0x00007000L
39154 #define CGTT_GL1A_CLK_CTRL__MGLS_OVERRIDE_MASK                                                                0x00008000L
39155 #define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                         0x00010000L
39156 #define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                         0x00020000L
39157 #define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                         0x00040000L
39158 #define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                         0x00080000L
39159 #define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                         0x00100000L
39160 #define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                         0x00200000L
39161 #define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                         0x00400000L
39162 #define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                         0x00800000L
39163 #define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                               0x01000000L
39164 #define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                               0x02000000L
39165 #define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                               0x04000000L
39166 #define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                               0x08000000L
39167 #define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                               0x10000000L
39168 #define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                               0x20000000L
39169 #define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE1_MASK                                                               0x40000000L
39170 #define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE0_MASK                                                               0x80000000L
39171 //CGTT_CHA_CLK_CTRL
39172 #define CGTT_CHA_CLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
39173 #define CGTT_CHA_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
39174 #define CGTT_CHA_CLK_CTRL__RESERVED__SHIFT                                                                    0xc
39175 #define CGTT_CHA_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                               0xf
39176 #define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
39177 #define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
39178 #define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
39179 #define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
39180 #define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
39181 #define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
39182 #define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
39183 #define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
39184 #define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                              0x18
39185 #define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                              0x19
39186 #define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                              0x1a
39187 #define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                              0x1b
39188 #define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                              0x1c
39189 #define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                              0x1d
39190 #define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                              0x1e
39191 #define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                              0x1f
39192 #define CGTT_CHA_CLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
39193 #define CGTT_CHA_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
39194 #define CGTT_CHA_CLK_CTRL__RESERVED_MASK                                                                      0x00007000L
39195 #define CGTT_CHA_CLK_CTRL__MGLS_OVERRIDE_MASK                                                                 0x00008000L
39196 #define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
39197 #define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
39198 #define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
39199 #define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
39200 #define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
39201 #define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
39202 #define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
39203 #define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
39204 #define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                                0x01000000L
39205 #define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                                0x02000000L
39206 #define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                                0x04000000L
39207 #define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                                0x08000000L
39208 #define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                                0x10000000L
39209 #define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                                0x20000000L
39210 #define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE1_MASK                                                                0x40000000L
39211 #define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE0_MASK                                                                0x80000000L
39212 //GUS_CGTT_CLK_CTRL
39213 #define GUS_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
39214 #define GUS_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
39215 #define GUS_CGTT_CLK_CTRL__SPARE0__SHIFT                                                                      0xc
39216 #define GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_DRAM__SHIFT                                                    0x13
39217 #define GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT                                                   0x14
39218 #define GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT                                                    0x15
39219 #define GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT                                                  0x16
39220 #define GUS_CGTT_CLK_CTRL__SPARE1__SHIFT                                                                      0x17
39221 #define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_DRAM__SHIFT                                                          0x1b
39222 #define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT                                                         0x1c
39223 #define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT                                                          0x1d
39224 #define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT                                                        0x1e
39225 #define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT                                                      0x1f
39226 #define GUS_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
39227 #define GUS_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
39228 #define GUS_CGTT_CLK_CTRL__SPARE0_MASK                                                                        0x0007F000L
39229 #define GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_DRAM_MASK                                                      0x00080000L
39230 #define GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK                                                     0x00100000L
39231 #define GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK                                                      0x00200000L
39232 #define GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK                                                    0x00400000L
39233 #define GUS_CGTT_CLK_CTRL__SPARE1_MASK                                                                        0x07800000L
39234 #define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_DRAM_MASK                                                            0x08000000L
39235 #define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK                                                           0x10000000L
39236 #define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK                                                            0x20000000L
39237 #define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK                                                          0x40000000L
39238 #define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK                                                        0x80000000L
39239 //CGTT_PH_CLK_CTRL0
39240 #define CGTT_PH_CLK_CTRL0__ON_DELAY__SHIFT                                                                    0x0
39241 #define CGTT_PH_CLK_CTRL0__OFF_HYSTERESIS__SHIFT                                                              0x4
39242 #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
39243 #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
39244 #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
39245 #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
39246 #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
39247 #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
39248 #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
39249 #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT                                                              0x18
39250 #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT                                                              0x19
39251 #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT                                                              0x1a
39252 #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT                                                              0x1b
39253 #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT                                                              0x1c
39254 #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT                                                              0x1d
39255 #define CGTT_PH_CLK_CTRL0__PERFMON_CLK_OVERRIDE__SHIFT                                                        0x1e
39256 #define CGTT_PH_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT                                                            0x1f
39257 #define CGTT_PH_CLK_CTRL0__ON_DELAY_MASK                                                                      0x0000000FL
39258 #define CGTT_PH_CLK_CTRL0__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
39259 #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
39260 #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
39261 #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
39262 #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
39263 #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
39264 #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
39265 #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
39266 #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE7_MASK                                                                0x01000000L
39267 #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE6_MASK                                                                0x02000000L
39268 #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE5_MASK                                                                0x04000000L
39269 #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE4_MASK                                                                0x08000000L
39270 #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE3_MASK                                                                0x10000000L
39271 #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE2_MASK                                                                0x20000000L
39272 #define CGTT_PH_CLK_CTRL0__PERFMON_CLK_OVERRIDE_MASK                                                          0x40000000L
39273 #define CGTT_PH_CLK_CTRL0__REG_CLK_OVERRIDE_MASK                                                              0x80000000L
39274 //CGTT_PH_CLK_CTRL1
39275 #define CGTT_PH_CLK_CTRL1__ON_DELAY__SHIFT                                                                    0x0
39276 #define CGTT_PH_CLK_CTRL1__OFF_HYSTERESIS__SHIFT                                                              0x4
39277 #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE7__SHIFT                                                              0x18
39278 #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT                                                              0x19
39279 #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT                                                              0x1a
39280 #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT                                                              0x1b
39281 #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT                                                              0x1c
39282 #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT                                                              0x1d
39283 #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT                                                              0x1e
39284 #define CGTT_PH_CLK_CTRL1__ON_DELAY_MASK                                                                      0x0000000FL
39285 #define CGTT_PH_CLK_CTRL1__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
39286 #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE7_MASK                                                                0x01000000L
39287 #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE6_MASK                                                                0x02000000L
39288 #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE5_MASK                                                                0x04000000L
39289 #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE4_MASK                                                                0x08000000L
39290 #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE3_MASK                                                                0x10000000L
39291 #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE2_MASK                                                                0x20000000L
39292 #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE1_MASK                                                                0x40000000L
39293 //CGTT_PH_CLK_CTRL2
39294 #define CGTT_PH_CLK_CTRL2__ON_DELAY__SHIFT                                                                    0x0
39295 #define CGTT_PH_CLK_CTRL2__OFF_HYSTERESIS__SHIFT                                                              0x4
39296 #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE7__SHIFT                                                              0x18
39297 #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT                                                              0x19
39298 #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT                                                              0x1a
39299 #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT                                                              0x1b
39300 #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT                                                              0x1c
39301 #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT                                                              0x1d
39302 #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT                                                              0x1e
39303 #define CGTT_PH_CLK_CTRL2__ON_DELAY_MASK                                                                      0x0000000FL
39304 #define CGTT_PH_CLK_CTRL2__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
39305 #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE7_MASK                                                                0x01000000L
39306 #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE6_MASK                                                                0x02000000L
39307 #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE5_MASK                                                                0x04000000L
39308 #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE4_MASK                                                                0x08000000L
39309 #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE3_MASK                                                                0x10000000L
39310 #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE2_MASK                                                                0x20000000L
39311 #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE1_MASK                                                                0x40000000L
39312 //CGTT_PH_CLK_CTRL3
39313 #define CGTT_PH_CLK_CTRL3__ON_DELAY__SHIFT                                                                    0x0
39314 #define CGTT_PH_CLK_CTRL3__OFF_HYSTERESIS__SHIFT                                                              0x4
39315 #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE7__SHIFT                                                              0x18
39316 #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT                                                              0x19
39317 #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT                                                              0x1a
39318 #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT                                                              0x1b
39319 #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT                                                              0x1c
39320 #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT                                                              0x1d
39321 #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT                                                              0x1e
39322 #define CGTT_PH_CLK_CTRL3__ON_DELAY_MASK                                                                      0x0000000FL
39323 #define CGTT_PH_CLK_CTRL3__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
39324 #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE7_MASK                                                                0x01000000L
39325 #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE6_MASK                                                                0x02000000L
39326 #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE5_MASK                                                                0x04000000L
39327 #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE4_MASK                                                                0x08000000L
39328 #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE3_MASK                                                                0x10000000L
39329 #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE2_MASK                                                                0x20000000L
39330 #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE1_MASK                                                                0x40000000L
39331 
39332 
39333 // addressBlock: gc_hypdec
39334 //CP_PFP_UCODE_ADDR
39335 #define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT                                                                  0x0
39336 #define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK                                                                    0x000FFFFFL
39337 //CP_PFP_UCODE_DATA
39338 #define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT                                                                  0x0
39339 #define CP_PFP_UCODE_DATA__UCODE_DATA_MASK                                                                    0xFFFFFFFFL
39340 //CP_ME_RAM_RADDR
39341 #define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT                                                                  0x0
39342 #define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK                                                                    0x000FFFFFL
39343 //CP_ME_RAM_WADDR
39344 #define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT                                                                  0x0
39345 #define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK                                                                    0x001FFFFFL
39346 //CP_ME_RAM_DATA
39347 #define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT                                                                    0x0
39348 #define CP_ME_RAM_DATA__ME_RAM_DATA_MASK                                                                      0xFFFFFFFFL
39349 //CP_CE_UCODE_ADDR
39350 #define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT                                                                   0x0
39351 #define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK                                                                     0x000FFFFFL
39352 //CP_CE_UCODE_DATA
39353 #define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT                                                                   0x0
39354 #define CP_CE_UCODE_DATA__UCODE_DATA_MASK                                                                     0xFFFFFFFFL
39355 //CP_MEC_ME1_UCODE_ADDR
39356 #define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT                                                              0x0
39357 #define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK                                                                0x000FFFFFL
39358 //CP_MEC_ME1_UCODE_DATA
39359 #define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT                                                              0x0
39360 #define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK                                                                0xFFFFFFFFL
39361 //CP_MEC_ME2_UCODE_ADDR
39362 #define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT                                                              0x0
39363 #define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK                                                                0x000FFFFFL
39364 //CP_MEC_ME2_UCODE_DATA
39365 #define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT                                                              0x0
39366 #define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK                                                                0xFFFFFFFFL
39367 //CP_PFP_IC_BASE_LO
39368 #define CP_PFP_IC_BASE_LO__IC_BASE_LO__SHIFT                                                                  0xc
39369 #define CP_PFP_IC_BASE_LO__IC_BASE_LO_MASK                                                                    0xFFFFF000L
39370 //CP_PFP_IC_BASE_HI
39371 #define CP_PFP_IC_BASE_HI__IC_BASE_HI__SHIFT                                                                  0x0
39372 #define CP_PFP_IC_BASE_HI__IC_BASE_HI_MASK                                                                    0x0000FFFFL
39373 //CP_PFP_IC_BASE_CNTL
39374 #define CP_PFP_IC_BASE_CNTL__VMID__SHIFT                                                                      0x0
39375 #define CP_PFP_IC_BASE_CNTL__ADDRESS_CLAMP__SHIFT                                                             0x4
39376 #define CP_PFP_IC_BASE_CNTL__EXE_DISABLE__SHIFT                                                               0x17
39377 #define CP_PFP_IC_BASE_CNTL__CACHE_POLICY__SHIFT                                                              0x18
39378 #define CP_PFP_IC_BASE_CNTL__VMID_MASK                                                                        0x0000000FL
39379 #define CP_PFP_IC_BASE_CNTL__ADDRESS_CLAMP_MASK                                                               0x00000010L
39380 #define CP_PFP_IC_BASE_CNTL__EXE_DISABLE_MASK                                                                 0x00800000L
39381 #define CP_PFP_IC_BASE_CNTL__CACHE_POLICY_MASK                                                                0x03000000L
39382 //CP_PFP_IC_OP_CNTL
39383 #define CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT                                                            0x0
39384 #define CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT                                                   0x1
39385 #define CP_PFP_IC_OP_CNTL__PRIME_ICACHE__SHIFT                                                                0x4
39386 #define CP_PFP_IC_OP_CNTL__ICACHE_PRIMED__SHIFT                                                               0x5
39387 #define CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE_MASK                                                              0x00000001L
39388 #define CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK                                                     0x00000002L
39389 #define CP_PFP_IC_OP_CNTL__PRIME_ICACHE_MASK                                                                  0x00000010L
39390 #define CP_PFP_IC_OP_CNTL__ICACHE_PRIMED_MASK                                                                 0x00000020L
39391 //CP_ME_IC_BASE_LO
39392 #define CP_ME_IC_BASE_LO__IC_BASE_LO__SHIFT                                                                   0xc
39393 #define CP_ME_IC_BASE_LO__IC_BASE_LO_MASK                                                                     0xFFFFF000L
39394 //CP_ME_IC_BASE_HI
39395 #define CP_ME_IC_BASE_HI__IC_BASE_HI__SHIFT                                                                   0x0
39396 #define CP_ME_IC_BASE_HI__IC_BASE_HI_MASK                                                                     0x0000FFFFL
39397 //CP_ME_IC_BASE_CNTL
39398 #define CP_ME_IC_BASE_CNTL__VMID__SHIFT                                                                       0x0
39399 #define CP_ME_IC_BASE_CNTL__ADDRESS_CLAMP__SHIFT                                                              0x4
39400 #define CP_ME_IC_BASE_CNTL__EXE_DISABLE__SHIFT                                                                0x17
39401 #define CP_ME_IC_BASE_CNTL__CACHE_POLICY__SHIFT                                                               0x18
39402 #define CP_ME_IC_BASE_CNTL__VMID_MASK                                                                         0x0000000FL
39403 #define CP_ME_IC_BASE_CNTL__ADDRESS_CLAMP_MASK                                                                0x00000010L
39404 #define CP_ME_IC_BASE_CNTL__EXE_DISABLE_MASK                                                                  0x00800000L
39405 #define CP_ME_IC_BASE_CNTL__CACHE_POLICY_MASK                                                                 0x03000000L
39406 //CP_ME_IC_OP_CNTL
39407 #define CP_ME_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT                                                             0x0
39408 #define CP_ME_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT                                                    0x1
39409 #define CP_ME_IC_OP_CNTL__PRIME_ICACHE__SHIFT                                                                 0x4
39410 #define CP_ME_IC_OP_CNTL__ICACHE_PRIMED__SHIFT                                                                0x5
39411 #define CP_ME_IC_OP_CNTL__INVALIDATE_CACHE_MASK                                                               0x00000001L
39412 #define CP_ME_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK                                                      0x00000002L
39413 #define CP_ME_IC_OP_CNTL__PRIME_ICACHE_MASK                                                                   0x00000010L
39414 #define CP_ME_IC_OP_CNTL__ICACHE_PRIMED_MASK                                                                  0x00000020L
39415 //CP_CE_IC_BASE_LO
39416 #define CP_CE_IC_BASE_LO__IC_BASE_LO__SHIFT                                                                   0xc
39417 #define CP_CE_IC_BASE_LO__IC_BASE_LO_MASK                                                                     0xFFFFF000L
39418 //CP_CE_IC_BASE_HI
39419 #define CP_CE_IC_BASE_HI__IC_BASE_HI__SHIFT                                                                   0x0
39420 #define CP_CE_IC_BASE_HI__IC_BASE_HI_MASK                                                                     0x0000FFFFL
39421 //CP_CE_IC_BASE_CNTL
39422 #define CP_CE_IC_BASE_CNTL__VMID__SHIFT                                                                       0x0
39423 #define CP_CE_IC_BASE_CNTL__ADDRESS_CLAMP__SHIFT                                                              0x4
39424 #define CP_CE_IC_BASE_CNTL__EXE_DISABLE__SHIFT                                                                0x17
39425 #define CP_CE_IC_BASE_CNTL__CACHE_POLICY__SHIFT                                                               0x18
39426 #define CP_CE_IC_BASE_CNTL__VMID_MASK                                                                         0x0000000FL
39427 #define CP_CE_IC_BASE_CNTL__ADDRESS_CLAMP_MASK                                                                0x00000010L
39428 #define CP_CE_IC_BASE_CNTL__EXE_DISABLE_MASK                                                                  0x00800000L
39429 #define CP_CE_IC_BASE_CNTL__CACHE_POLICY_MASK                                                                 0x03000000L
39430 //CP_CE_IC_OP_CNTL
39431 #define CP_CE_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT                                                             0x0
39432 #define CP_CE_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT                                                    0x1
39433 #define CP_CE_IC_OP_CNTL__PRIME_ICACHE__SHIFT                                                                 0x4
39434 #define CP_CE_IC_OP_CNTL__ICACHE_PRIMED__SHIFT                                                                0x5
39435 #define CP_CE_IC_OP_CNTL__INVALIDATE_CACHE_MASK                                                               0x00000001L
39436 #define CP_CE_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK                                                      0x00000002L
39437 #define CP_CE_IC_OP_CNTL__PRIME_ICACHE_MASK                                                                   0x00000010L
39438 #define CP_CE_IC_OP_CNTL__ICACHE_PRIMED_MASK                                                                  0x00000020L
39439 //CP_CPC_IC_BASE_LO
39440 #define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT                                                                  0xc
39441 #define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK                                                                    0xFFFFF000L
39442 //CP_CPC_IC_BASE_HI
39443 #define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT                                                                  0x0
39444 #define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK                                                                    0x0000FFFFL
39445 //CP_CPC_IC_BASE_CNTL
39446 #define CP_CPC_IC_BASE_CNTL__VMID__SHIFT                                                                      0x0
39447 #define CP_CPC_IC_BASE_CNTL__ADDRESS_CLAMP__SHIFT                                                             0x4
39448 #define CP_CPC_IC_BASE_CNTL__EXE_DISABLE__SHIFT                                                               0x17
39449 #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT                                                              0x18
39450 #define CP_CPC_IC_BASE_CNTL__VMID_MASK                                                                        0x0000000FL
39451 #define CP_CPC_IC_BASE_CNTL__ADDRESS_CLAMP_MASK                                                               0x00000010L
39452 #define CP_CPC_IC_BASE_CNTL__EXE_DISABLE_MASK                                                                 0x00800000L
39453 #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK                                                                0x03000000L
39454 //CP_CPC_IC_OP_CNTL
39455 #define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT                                                            0x0
39456 #define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT                                                   0x1
39457 #define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT                                                                0x4
39458 #define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT                                                               0x5
39459 #define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK                                                              0x00000001L
39460 #define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK                                                     0x00000002L
39461 #define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK                                                                  0x00000010L
39462 #define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK                                                                 0x00000020L
39463 //CP_MES_IC_BASE_LO
39464 #define CP_MES_IC_BASE_LO__IC_BASE_LO__SHIFT                                                                  0xc
39465 #define CP_MES_IC_BASE_LO__IC_BASE_LO_MASK                                                                    0xFFFFF000L
39466 //CP_MES_MIBASE_LO
39467 #define CP_MES_MIBASE_LO__IC_BASE_LO__SHIFT                                                                   0xc
39468 #define CP_MES_MIBASE_LO__IC_BASE_LO_MASK                                                                     0xFFFFF000L
39469 //CP_MES_IC_BASE_HI
39470 #define CP_MES_IC_BASE_HI__IC_BASE_HI__SHIFT                                                                  0x0
39471 #define CP_MES_IC_BASE_HI__IC_BASE_HI_MASK                                                                    0x0000FFFFL
39472 //CP_MES_MIBASE_HI
39473 #define CP_MES_MIBASE_HI__IC_BASE_HI__SHIFT                                                                   0x0
39474 #define CP_MES_MIBASE_HI__IC_BASE_HI_MASK                                                                     0x0000FFFFL
39475 //CP_MES_IC_BASE_CNTL
39476 #define CP_MES_IC_BASE_CNTL__VMID__SHIFT                                                                      0x0
39477 #define CP_MES_IC_BASE_CNTL__EXE_DISABLE__SHIFT                                                               0x17
39478 #define CP_MES_IC_BASE_CNTL__CACHE_POLICY__SHIFT                                                              0x18
39479 #define CP_MES_IC_BASE_CNTL__VMID_MASK                                                                        0x0000000FL
39480 #define CP_MES_IC_BASE_CNTL__EXE_DISABLE_MASK                                                                 0x00800000L
39481 #define CP_MES_IC_BASE_CNTL__CACHE_POLICY_MASK                                                                0x03000000L
39482 //CP_MES_IC_OP_CNTL
39483 #define CP_MES_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT                                                            0x0
39484 #define CP_MES_IC_OP_CNTL__PRIME_ICACHE__SHIFT                                                                0x4
39485 #define CP_MES_IC_OP_CNTL__ICACHE_PRIMED__SHIFT                                                               0x5
39486 #define CP_MES_IC_OP_CNTL__INVALIDATE_CACHE_MASK                                                              0x00000001L
39487 #define CP_MES_IC_OP_CNTL__PRIME_ICACHE_MASK                                                                  0x00000010L
39488 #define CP_MES_IC_OP_CNTL__ICACHE_PRIMED_MASK                                                                 0x00000020L
39489 //CP_MES_DC_BASE_LO
39490 #define CP_MES_DC_BASE_LO__DC_BASE_LO__SHIFT                                                                  0x10
39491 #define CP_MES_DC_BASE_LO__DC_BASE_LO_MASK                                                                    0xFFFF0000L
39492 //CP_MES_MDBASE_LO
39493 #define CP_MES_MDBASE_LO__BASE_LO__SHIFT                                                                      0x10
39494 #define CP_MES_MDBASE_LO__BASE_LO_MASK                                                                        0xFFFF0000L
39495 //CP_MES_DC_BASE_HI
39496 #define CP_MES_DC_BASE_HI__DC_BASE_HI__SHIFT                                                                  0x0
39497 #define CP_MES_DC_BASE_HI__DC_BASE_HI_MASK                                                                    0x0000FFFFL
39498 //CP_MES_MDBASE_HI
39499 #define CP_MES_MDBASE_HI__BASE_HI__SHIFT                                                                      0x0
39500 #define CP_MES_MDBASE_HI__BASE_HI_MASK                                                                        0x0000FFFFL
39501 //CP_MES_LOCAL_BASE0_LO
39502 #define CP_MES_LOCAL_BASE0_LO__BASE0_LO__SHIFT                                                                0x10
39503 #define CP_MES_LOCAL_BASE0_LO__BASE0_LO_MASK                                                                  0xFFFF0000L
39504 //CP_MES_LOCAL_BASE0_HI
39505 #define CP_MES_LOCAL_BASE0_HI__BASE0_HI__SHIFT                                                                0x0
39506 #define CP_MES_LOCAL_BASE0_HI__BASE0_HI_MASK                                                                  0x0000FFFFL
39507 //CP_MES_LOCAL_MASK0_LO
39508 #define CP_MES_LOCAL_MASK0_LO__MASK0_LO__SHIFT                                                                0x10
39509 #define CP_MES_LOCAL_MASK0_LO__MASK0_LO_MASK                                                                  0xFFFF0000L
39510 //CP_MES_LOCAL_MASK0_HI
39511 #define CP_MES_LOCAL_MASK0_HI__MASK0_HI__SHIFT                                                                0x0
39512 #define CP_MES_LOCAL_MASK0_HI__MASK0_HI_MASK                                                                  0x0000FFFFL
39513 //CP_MES_LOCAL_APERTURE
39514 #define CP_MES_LOCAL_APERTURE__APERTURE__SHIFT                                                                0x0
39515 #define CP_MES_LOCAL_APERTURE__APERTURE_MASK                                                                  0x00000003L
39516 //CP_MES_MIBOUND_LO
39517 #define CP_MES_MIBOUND_LO__BOUND_LO__SHIFT                                                                    0x0
39518 #define CP_MES_MIBOUND_LO__BOUND_LO_MASK                                                                      0xFFFFFFFFL
39519 //CP_MES_MIBOUND_HI
39520 #define CP_MES_MIBOUND_HI__BOUND_HI__SHIFT                                                                    0x0
39521 #define CP_MES_MIBOUND_HI__BOUND_HI_MASK                                                                      0xFFFFFFFFL
39522 //CP_MES_MDBOUND_LO
39523 #define CP_MES_MDBOUND_LO__BOUND_LO__SHIFT                                                                    0x0
39524 #define CP_MES_MDBOUND_LO__BOUND_LO_MASK                                                                      0xFFFFFFFFL
39525 //CP_MES_MDBOUND_HI
39526 #define CP_MES_MDBOUND_HI__BOUND_HI__SHIFT                                                                    0x0
39527 #define CP_MES_MDBOUND_HI__BOUND_HI_MASK                                                                      0xFFFFFFFFL
39528 //GFX_PIPE_PRIORITY
39529 #define GFX_PIPE_PRIORITY__HP_PIPE_SELECT__SHIFT                                                              0x0
39530 #define GFX_PIPE_PRIORITY__HP_PIPE_SELECT_MASK                                                                0x00000001L
39531 //GRBM_GFX_INDEX_SR_SELECT
39532 #define GRBM_GFX_INDEX_SR_SELECT__INDEX__SHIFT                                                                0x0
39533 #define GRBM_GFX_INDEX_SR_SELECT__INDEX_MASK                                                                  0x00000007L
39534 //GRBM_GFX_INDEX_SR_DATA
39535 #define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX__SHIFT                                                         0x0
39536 #define GRBM_GFX_INDEX_SR_DATA__SA_INDEX__SHIFT                                                               0x8
39537 #define GRBM_GFX_INDEX_SR_DATA__SE_INDEX__SHIFT                                                               0x10
39538 #define GRBM_GFX_INDEX_SR_DATA__SA_BROADCAST_WRITES__SHIFT                                                    0x1d
39539 #define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES__SHIFT                                              0x1e
39540 #define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES__SHIFT                                                    0x1f
39541 #define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX_MASK                                                           0x000000FFL
39542 #define GRBM_GFX_INDEX_SR_DATA__SA_INDEX_MASK                                                                 0x0000FF00L
39543 #define GRBM_GFX_INDEX_SR_DATA__SE_INDEX_MASK                                                                 0x00FF0000L
39544 #define GRBM_GFX_INDEX_SR_DATA__SA_BROADCAST_WRITES_MASK                                                      0x20000000L
39545 #define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES_MASK                                                0x40000000L
39546 #define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES_MASK                                                      0x80000000L
39547 //GRBM_GFX_CNTL_SR_SELECT
39548 #define GRBM_GFX_CNTL_SR_SELECT__INDEX__SHIFT                                                                 0x0
39549 #define GRBM_GFX_CNTL_SR_SELECT__INDEX_MASK                                                                   0x00000007L
39550 //GRBM_GFX_CNTL_SR_DATA
39551 #define GRBM_GFX_CNTL_SR_DATA__PIPEID__SHIFT                                                                  0x0
39552 #define GRBM_GFX_CNTL_SR_DATA__MEID__SHIFT                                                                    0x2
39553 #define GRBM_GFX_CNTL_SR_DATA__VMID__SHIFT                                                                    0x4
39554 #define GRBM_GFX_CNTL_SR_DATA__QUEUEID__SHIFT                                                                 0x8
39555 #define GRBM_GFX_CNTL_SR_DATA__PIPEID_MASK                                                                    0x00000003L
39556 #define GRBM_GFX_CNTL_SR_DATA__MEID_MASK                                                                      0x0000000CL
39557 #define GRBM_GFX_CNTL_SR_DATA__VMID_MASK                                                                      0x000000F0L
39558 #define GRBM_GFX_CNTL_SR_DATA__QUEUEID_MASK                                                                   0x00000700L
39559 //GRBM_CAM_INDEX
39560 #define GRBM_CAM_INDEX__CAM_INDEX__SHIFT                                                                      0x0
39561 #define GRBM_CAM_INDEX__CAM_INDEX_MASK                                                                        0x0000000FL
39562 //GRBM_HYP_CAM_INDEX
39563 #define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT                                                                  0x0
39564 #define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK                                                                    0x0000000FL
39565 //GRBM_CAM_DATA
39566 #define GRBM_CAM_DATA__CAM_ADDR__SHIFT                                                                        0x0
39567 #define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT                                                                   0x10
39568 #define GRBM_CAM_DATA__CAM_ADDR_MASK                                                                          0x0000FFFFL
39569 #define GRBM_CAM_DATA__CAM_REMAPADDR_MASK                                                                     0xFFFF0000L
39570 //GRBM_HYP_CAM_DATA
39571 #define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT                                                                    0x0
39572 #define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT                                                               0x10
39573 #define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK                                                                      0x0000FFFFL
39574 #define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK                                                                 0xFFFF0000L
39575 //GRBM_CAM_DATA_UPPER
39576 #define GRBM_CAM_DATA_UPPER__CAM_ADDR__SHIFT                                                                  0x0
39577 #define GRBM_CAM_DATA_UPPER__CAM_REMAPADDR__SHIFT                                                             0x10
39578 #define GRBM_CAM_DATA_UPPER__CAM_ADDR_MASK                                                                    0x00000003L
39579 #define GRBM_CAM_DATA_UPPER__CAM_REMAPADDR_MASK                                                               0x00030000L
39580 //GRBM_HYP_CAM_DATA_UPPER
39581 #define GRBM_HYP_CAM_DATA_UPPER__CAM_ADDR__SHIFT                                                              0x0
39582 #define GRBM_HYP_CAM_DATA_UPPER__CAM_REMAPADDR__SHIFT                                                         0x10
39583 #define GRBM_HYP_CAM_DATA_UPPER__CAM_ADDR_MASK                                                                0x00000003L
39584 #define GRBM_HYP_CAM_DATA_UPPER__CAM_REMAPADDR_MASK                                                           0x00030000L
39585 //GC_IH_COOKIE_0_PTR
39586 #define GC_IH_COOKIE_0_PTR__ADDR__SHIFT                                                                       0x0
39587 #define GC_IH_COOKIE_0_PTR__ADDR_MASK                                                                         0x000FFFFFL
39588 //RLC_GPU_IOV_VF_ENABLE
39589 #define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT                                                               0x0
39590 #define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT                                                                0x1
39591 #define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT                                                                  0x10
39592 #define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK                                                                 0x00000001L
39593 #define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK                                                                  0x0000FFFEL
39594 #define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK                                                                    0xFFFF0000L
39595 //RLC_GPU_IOV_CFG_REG6
39596 #define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT                                                               0x0
39597 #define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT                                                           0x7
39598 #define RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT                                                                 0x8
39599 #define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT                                                             0xa
39600 #define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK                                                                 0x0000007FL
39601 #define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK                                                             0x00000080L
39602 #define RLC_GPU_IOV_CFG_REG6__RESERVED_MASK                                                                   0x00000300L
39603 #define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK                                                               0xFFFFFC00L
39604 //RLC_GPU_IOV_CFG_REG8
39605 #define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT                                                           0x0
39606 #define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK                                                             0xFFFFFFFFL
39607 //RLC_RLCV_TIMER_INT_0
39608 #define RLC_RLCV_TIMER_INT_0__TIMER__SHIFT                                                                    0x0
39609 #define RLC_RLCV_TIMER_INT_0__TIMER_MASK                                                                      0xFFFFFFFFL
39610 //RLC_RLCV_TIMER_CTRL
39611 #define RLC_RLCV_TIMER_CTRL__TIMER_0_EN__SHIFT                                                                0x0
39612 #define RLC_RLCV_TIMER_CTRL__TIMER_1_EN__SHIFT                                                                0x1
39613 #define RLC_RLCV_TIMER_CTRL__TIMER_0_AUTO_REARM__SHIFT                                                        0x2
39614 #define RLC_RLCV_TIMER_CTRL__TIMER_1_AUTO_REARM__SHIFT                                                        0x3
39615 #define RLC_RLCV_TIMER_CTRL__TIMER_0_INT_CLEAR__SHIFT                                                         0x4
39616 #define RLC_RLCV_TIMER_CTRL__TIMER_1_INT_CLEAR__SHIFT                                                         0x5
39617 #define RLC_RLCV_TIMER_CTRL__RESERVED__SHIFT                                                                  0x6
39618 #define RLC_RLCV_TIMER_CTRL__TIMER_0_EN_MASK                                                                  0x00000001L
39619 #define RLC_RLCV_TIMER_CTRL__TIMER_1_EN_MASK                                                                  0x00000002L
39620 #define RLC_RLCV_TIMER_CTRL__TIMER_0_AUTO_REARM_MASK                                                          0x00000004L
39621 #define RLC_RLCV_TIMER_CTRL__TIMER_1_AUTO_REARM_MASK                                                          0x00000008L
39622 #define RLC_RLCV_TIMER_CTRL__TIMER_0_INT_CLEAR_MASK                                                           0x00000010L
39623 #define RLC_RLCV_TIMER_CTRL__TIMER_1_INT_CLEAR_MASK                                                           0x00000020L
39624 #define RLC_RLCV_TIMER_CTRL__RESERVED_MASK                                                                    0xFFFFFFC0L
39625 //RLC_RLCV_TIMER_STAT
39626 #define RLC_RLCV_TIMER_STAT__TIMER_0_STAT__SHIFT                                                              0x0
39627 #define RLC_RLCV_TIMER_STAT__TIMER_1_STAT__SHIFT                                                              0x1
39628 #define RLC_RLCV_TIMER_STAT__RESERVED__SHIFT                                                                  0x2
39629 #define RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT                                                       0x8
39630 #define RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT                                                       0x9
39631 #define RLC_RLCV_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC__SHIFT                                                   0xa
39632 #define RLC_RLCV_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC__SHIFT                                                   0xb
39633 #define RLC_RLCV_TIMER_STAT__TIMER_0_STAT_MASK                                                                0x00000001L
39634 #define RLC_RLCV_TIMER_STAT__TIMER_1_STAT_MASK                                                                0x00000002L
39635 #define RLC_RLCV_TIMER_STAT__RESERVED_MASK                                                                    0x000000FCL
39636 #define RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK                                                         0x00000100L
39637 #define RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK                                                         0x00000200L
39638 #define RLC_RLCV_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC_MASK                                                     0x00000400L
39639 #define RLC_RLCV_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC_MASK                                                     0x00000800L
39640 //RLC_GPU_IOV_VF_DOORBELL_STATUS
39641 #define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS__SHIFT                                             0x0
39642 #define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS__SHIFT                                             0x1f
39643 #define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_MASK                                               0x7FFFFFFFL
39644 #define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS_MASK                                               0x80000000L
39645 //RLC_GPU_IOV_VF_DOORBELL_STATUS_SET
39646 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET__SHIFT                                     0x0
39647 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET__SHIFT                                     0x1f
39648 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET_MASK                                       0x7FFFFFFFL
39649 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET_MASK                                       0x80000000L
39650 //RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR
39651 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR__SHIFT                                     0x0
39652 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR__SHIFT                                     0x1f
39653 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR_MASK                                       0x7FFFFFFFL
39654 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR_MASK                                       0x80000000L
39655 //RLC_GPU_IOV_VF_MASK
39656 #define RLC_GPU_IOV_VF_MASK__VF_MASK__SHIFT                                                                   0x0
39657 #define RLC_GPU_IOV_VF_MASK__VF_MASK_MASK                                                                     0x7FFFFFFFL
39658 //RLC_HYP_SEMAPHORE_0
39659 #define RLC_HYP_SEMAPHORE_0__CLIENT_ID__SHIFT                                                                 0x0
39660 #define RLC_HYP_SEMAPHORE_0__RESERVED__SHIFT                                                                  0x5
39661 #define RLC_HYP_SEMAPHORE_0__CLIENT_ID_MASK                                                                   0x0000001FL
39662 #define RLC_HYP_SEMAPHORE_0__RESERVED_MASK                                                                    0xFFFFFFE0L
39663 //RLC_HYP_SEMAPHORE_1
39664 #define RLC_HYP_SEMAPHORE_1__CLIENT_ID__SHIFT                                                                 0x0
39665 #define RLC_HYP_SEMAPHORE_1__RESERVED__SHIFT                                                                  0x5
39666 #define RLC_HYP_SEMAPHORE_1__CLIENT_ID_MASK                                                                   0x0000001FL
39667 #define RLC_HYP_SEMAPHORE_1__RESERVED_MASK                                                                    0xFFFFFFE0L
39668 //RLC_BUSY_CLK_CNTL
39669 #define RLC_BUSY_CLK_CNTL__BUSY_OFF_LATENCY__SHIFT                                                            0x0
39670 #define RLC_BUSY_CLK_CNTL__BUSY_OFF_LATENCY_MASK                                                              0x0000003FL
39671 //RLC_CLK_CNTL
39672 #define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL__SHIFT                                                                 0x0
39673 #define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL__SHIFT                                                                 0x2
39674 #define RLC_CLK_CNTL__RLC_GPM_CLK_CNTL__SHIFT                                                                 0x4
39675 #define RLC_CLK_CNTL__RLC_CMN_CLK_CNTL__SHIFT                                                                 0x5
39676 #define RLC_CLK_CNTL__RLC_TC_CLK_CNTL__SHIFT                                                                  0x6
39677 #define RLC_CLK_CNTL__RESERVED_7__SHIFT                                                                       0x7
39678 #define RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE__SHIFT                                                      0x8
39679 #define RLC_CLK_CNTL__RESERVED_9__SHIFT                                                                       0x9
39680 #define RLC_CLK_CNTL__RLC_SPP_CLK_CNTL__SHIFT                                                                 0xa
39681 #define RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE__SHIFT                                                         0xc
39682 #define RLC_CLK_CNTL__RLC_DFLL_CLK_CNTL__SHIFT                                                                0xd
39683 #define RLC_CLK_CNTL__RESERVED_15__SHIFT                                                                      0xf
39684 #define RLC_CLK_CNTL__RESERVED__SHIFT                                                                         0x12
39685 #define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL_MASK                                                                   0x00000003L
39686 #define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL_MASK                                                                   0x0000000CL
39687 #define RLC_CLK_CNTL__RLC_GPM_CLK_CNTL_MASK                                                                   0x00000010L
39688 #define RLC_CLK_CNTL__RLC_CMN_CLK_CNTL_MASK                                                                   0x00000020L
39689 #define RLC_CLK_CNTL__RLC_TC_CLK_CNTL_MASK                                                                    0x00000040L
39690 #define RLC_CLK_CNTL__RESERVED_7_MASK                                                                         0x00000080L
39691 #define RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK                                                        0x00000100L
39692 #define RLC_CLK_CNTL__RESERVED_9_MASK                                                                         0x00000200L
39693 #define RLC_CLK_CNTL__RLC_SPP_CLK_CNTL_MASK                                                                   0x00000C00L
39694 #define RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE_MASK                                                           0x00001000L
39695 #define RLC_CLK_CNTL__RLC_DFLL_CLK_CNTL_MASK                                                                  0x00002000L
39696 #define RLC_CLK_CNTL__RESERVED_15_MASK                                                                        0x00008000L
39697 #define RLC_CLK_CNTL__RESERVED_MASK                                                                           0xFFFC0000L
39698 //RLC_PACE_TIMER_STAT
39699 #define RLC_PACE_TIMER_STAT__TIMER_0_STAT__SHIFT                                                              0x0
39700 #define RLC_PACE_TIMER_STAT__TIMER_1_STAT__SHIFT                                                              0x1
39701 #define RLC_PACE_TIMER_STAT__RESERVED__SHIFT                                                                  0x2
39702 #define RLC_PACE_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT                                                       0x8
39703 #define RLC_PACE_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT                                                       0x9
39704 #define RLC_PACE_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC__SHIFT                                                   0xa
39705 #define RLC_PACE_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC__SHIFT                                                   0xb
39706 #define RLC_PACE_TIMER_STAT__TIMER_0_STAT_MASK                                                                0x00000001L
39707 #define RLC_PACE_TIMER_STAT__TIMER_1_STAT_MASK                                                                0x00000002L
39708 #define RLC_PACE_TIMER_STAT__RESERVED_MASK                                                                    0x000000FCL
39709 #define RLC_PACE_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK                                                         0x00000100L
39710 #define RLC_PACE_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK                                                         0x00000200L
39711 #define RLC_PACE_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC_MASK                                                     0x00000400L
39712 #define RLC_PACE_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC_MASK                                                     0x00000800L
39713 //RLC_GPU_IOV_SCH_BLOCK
39714 #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID__SHIFT                                                            0x0
39715 #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver__SHIFT                                                           0x4
39716 #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size__SHIFT                                                          0x8
39717 #define RLC_GPU_IOV_SCH_BLOCK__RESERVED__SHIFT                                                                0x10
39718 #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID_MASK                                                              0x0000000FL
39719 #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver_MASK                                                             0x000000F0L
39720 #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size_MASK                                                            0x00007F00L
39721 #define RLC_GPU_IOV_SCH_BLOCK__RESERVED_MASK                                                                  0x7FFF0000L
39722 //RLC_GPU_IOV_CFG_REG1
39723 #define RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT                                                                 0x0
39724 #define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT                                                              0x4
39725 #define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT                                                      0x5
39726 #define RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT                                                                 0x6
39727 #define RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT                                                                   0x8
39728 #define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT                                                              0x10
39729 #define RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT                                                                0x18
39730 #define RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK                                                                   0x0000000FL
39731 #define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK                                                                0x00000010L
39732 #define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK                                                        0x00000020L
39733 #define RLC_GPU_IOV_CFG_REG1__RESERVED_MASK                                                                   0x000000C0L
39734 #define RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK                                                                     0x0000FF00L
39735 #define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK                                                                0x00FF0000L
39736 #define RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK                                                                  0xFF000000L
39737 //RLC_GPU_IOV_CFG_REG2
39738 #define RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT                                                               0x0
39739 #define RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT                                                                 0x4
39740 #define RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK                                                                 0x0000000FL
39741 #define RLC_GPU_IOV_CFG_REG2__RESERVED_MASK                                                                   0xFFFFFFF0L
39742 //RLC_GPU_IOV_VM_BUSY_STATUS
39743 #define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT                                                     0x0
39744 #define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK                                                       0xFFFFFFFFL
39745 //RLC_GPU_IOV_SCH_0
39746 #define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS__SHIFT                                                            0x0
39747 #define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS_MASK                                                              0xFFFFFFFFL
39748 //RLC_GPU_IOV_ACTIVE_FCN_ID
39749 #define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT                                                               0x0
39750 #define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT                                                            0x5
39751 #define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT                                                               0x1f
39752 #define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK                                                                 0x0000001FL
39753 #define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK                                                              0x7FFFFFE0L
39754 #define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK                                                                 0x80000000L
39755 //RLC_GPU_IOV_SCH_3
39756 #define RLC_GPU_IOV_SCH_3__Time_Quanta_Def__SHIFT                                                             0x0
39757 #define RLC_GPU_IOV_SCH_3__Time_Quanta_Def_MASK                                                               0xFFFFFFFFL
39758 //RLC_GPU_IOV_SCH_1
39759 #define RLC_GPU_IOV_SCH_1__DATA__SHIFT                                                                        0x0
39760 #define RLC_GPU_IOV_SCH_1__DATA_MASK                                                                          0xFFFFFFFFL
39761 //RLC_GPU_IOV_SCH_2
39762 #define RLC_GPU_IOV_SCH_2__DATA__SHIFT                                                                        0x0
39763 #define RLC_GPU_IOV_SCH_2__DATA_MASK                                                                          0xFFFFFFFFL
39764 //RLC_PACE_INT_FORCE
39765 #define RLC_PACE_INT_FORCE__FORCE__SHIFT                                                                      0x0
39766 #define RLC_PACE_INT_FORCE__FORCE_MASK                                                                        0xFFFFFFFFL
39767 //RLC_GPU_IOV_INT_STAT
39768 #define RLC_GPU_IOV_INT_STAT__STATUS__SHIFT                                                                   0x0
39769 #define RLC_GPU_IOV_INT_STAT__STATUS_MASK                                                                     0xFFFFFFFFL
39770 //RLC_RLCV_TIMER_INT_1
39771 #define RLC_RLCV_TIMER_INT_1__TIMER__SHIFT                                                                    0x0
39772 #define RLC_RLCV_TIMER_INT_1__TIMER_MASK                                                                      0xFFFFFFFFL
39773 //RLC_IH_COOKIE
39774 #define RLC_IH_COOKIE__DATA__SHIFT                                                                            0x0
39775 #define RLC_IH_COOKIE__DATA_MASK                                                                              0xFFFFFFFFL
39776 //RLC_IH_COOKIE_CNTL
39777 #define RLC_IH_COOKIE_CNTL__CREDIT__SHIFT                                                                     0x0
39778 #define RLC_IH_COOKIE_CNTL__RESET_COUNTER__SHIFT                                                              0x2
39779 #define RLC_IH_COOKIE_CNTL__CREDIT_MASK                                                                       0x00000003L
39780 #define RLC_IH_COOKIE_CNTL__RESET_COUNTER_MASK                                                                0x00000004L
39781 //RLC_HYP_RLCG_UCODE_CHKSUM
39782 #define RLC_HYP_RLCG_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT                                                        0x0
39783 #define RLC_HYP_RLCG_UCODE_CHKSUM__UCODE_CHKSUM_MASK                                                          0xFFFFFFFFL
39784 //RLC_HYP_RLCP_UCODE_CHKSUM
39785 #define RLC_HYP_RLCP_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT                                                        0x0
39786 #define RLC_HYP_RLCP_UCODE_CHKSUM__UCODE_CHKSUM_MASK                                                          0xFFFFFFFFL
39787 //RLC_HYP_RLCV_UCODE_CHKSUM
39788 #define RLC_HYP_RLCV_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT                                                        0x0
39789 #define RLC_HYP_RLCV_UCODE_CHKSUM__UCODE_CHKSUM_MASK                                                          0xFFFFFFFFL
39790 //RLC_GPU_IOV_F32_CNTL
39791 #define RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT                                                                   0x0
39792 #define RLC_GPU_IOV_F32_CNTL__ENABLE_MASK                                                                     0x00000001L
39793 //RLC_GPU_IOV_F32_RESET
39794 #define RLC_GPU_IOV_F32_RESET__RESET__SHIFT                                                                   0x0
39795 #define RLC_GPU_IOV_F32_RESET__RESET_MASK                                                                     0x00000001L
39796 //RLC_GPU_IOV_SDMA0_STATUS
39797 #define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED__SHIFT                                                            0x0
39798 #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_7_1__SHIFT                                                         0x1
39799 #define RLC_GPU_IOV_SDMA0_STATUS__SAVED__SHIFT                                                                0x8
39800 #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_11_9__SHIFT                                                        0x9
39801 #define RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT                                                             0xc
39802 #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_31_13__SHIFT                                                       0xd
39803 #define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED_MASK                                                              0x00000001L
39804 #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_7_1_MASK                                                           0x000000FEL
39805 #define RLC_GPU_IOV_SDMA0_STATUS__SAVED_MASK                                                                  0x00000100L
39806 #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_11_9_MASK                                                          0x00000E00L
39807 #define RLC_GPU_IOV_SDMA0_STATUS__RESTORED_MASK                                                               0x00001000L
39808 #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_31_13_MASK                                                         0xFFFFE000L
39809 //RLC_GPU_IOV_SDMA1_STATUS
39810 #define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED__SHIFT                                                            0x0
39811 #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_7_1__SHIFT                                                         0x1
39812 #define RLC_GPU_IOV_SDMA1_STATUS__SAVED__SHIFT                                                                0x8
39813 #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_11_9__SHIFT                                                        0x9
39814 #define RLC_GPU_IOV_SDMA1_STATUS__RESTORED__SHIFT                                                             0xc
39815 #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_31_13__SHIFT                                                       0xd
39816 #define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED_MASK                                                              0x00000001L
39817 #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_7_1_MASK                                                           0x000000FEL
39818 #define RLC_GPU_IOV_SDMA1_STATUS__SAVED_MASK                                                                  0x00000100L
39819 #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_11_9_MASK                                                          0x00000E00L
39820 #define RLC_GPU_IOV_SDMA1_STATUS__RESTORED_MASK                                                               0x00001000L
39821 #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_31_13_MASK                                                         0xFFFFE000L
39822 //RLC_GPU_IOV_SMU_RESPONSE
39823 #define RLC_GPU_IOV_SMU_RESPONSE__RESP__SHIFT                                                                 0x0
39824 #define RLC_GPU_IOV_SMU_RESPONSE__RESP_MASK                                                                   0xFFFFFFFFL
39825 //RLC_GPU_IOV_VIRT_RESET_REQ
39826 #define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR__SHIFT                                                             0x0
39827 #define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED__SHIFT                                                           0x10
39828 #define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR__SHIFT                                                        0x1f
39829 #define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR_MASK                                                               0x0000FFFFL
39830 #define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED_MASK                                                             0x7FFF0000L
39831 #define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR_MASK                                                          0x80000000L
39832 //RLC_GPU_IOV_RLC_RESPONSE
39833 #define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT                                                                 0x0
39834 #define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK                                                                   0xFFFFFFFFL
39835 //RLC_GPU_IOV_INT_DISABLE
39836 #define RLC_GPU_IOV_INT_DISABLE__DISABLE__SHIFT                                                               0x0
39837 #define RLC_GPU_IOV_INT_DISABLE__DISABLE_MASK                                                                 0xFFFFFFFFL
39838 //RLC_GPU_IOV_INT_FORCE
39839 #define RLC_GPU_IOV_INT_FORCE__FORCE__SHIFT                                                                   0x0
39840 #define RLC_GPU_IOV_INT_FORCE__FORCE_MASK                                                                     0xFFFFFFFFL
39841 //RLC_GPU_IOV_SDMA0_BUSY_STATUS
39842 #define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT                                                  0x0
39843 #define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK                                                    0xFFFFFFFFL
39844 //RLC_GPU_IOV_SDMA1_BUSY_STATUS
39845 #define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT                                                  0x0
39846 #define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK                                                    0xFFFFFFFFL
39847 //RLC_HYP_SEMAPHORE_2
39848 #define RLC_HYP_SEMAPHORE_2__CLIENT_ID__SHIFT                                                                 0x0
39849 #define RLC_HYP_SEMAPHORE_2__RESERVED__SHIFT                                                                  0x5
39850 #define RLC_HYP_SEMAPHORE_2__CLIENT_ID_MASK                                                                   0x0000001FL
39851 #define RLC_HYP_SEMAPHORE_2__RESERVED_MASK                                                                    0xFFFFFFE0L
39852 //RLC_HYP_SEMAPHORE_3
39853 #define RLC_HYP_SEMAPHORE_3__CLIENT_ID__SHIFT                                                                 0x0
39854 #define RLC_HYP_SEMAPHORE_3__RESERVED__SHIFT                                                                  0x5
39855 #define RLC_HYP_SEMAPHORE_3__CLIENT_ID_MASK                                                                   0x0000001FL
39856 #define RLC_HYP_SEMAPHORE_3__RESERVED_MASK                                                                    0xFFFFFFE0L
39857 //RLC_HYP_RESET_VECTOR
39858 #define RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT__SHIFT                                                           0x0
39859 #define RLC_HYP_RESET_VECTOR__VDDGFX_EXIT__SHIFT                                                              0x1
39860 #define RLC_HYP_RESET_VECTOR__WARM_RESET_EXIT__SHIFT                                                          0x2
39861 #define RLC_HYP_RESET_VECTOR__VF_FLR_EXIT__SHIFT                                                              0x3
39862 #define RLC_HYP_RESET_VECTOR__RESERVED_4__SHIFT                                                               0x4
39863 #define RLC_HYP_RESET_VECTOR__RESERVED_5__SHIFT                                                               0x5
39864 #define RLC_HYP_RESET_VECTOR__RESERVED_6__SHIFT                                                               0x6
39865 #define RLC_HYP_RESET_VECTOR__RESERVED_7__SHIFT                                                               0x7
39866 #define RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK                                                             0x00000001L
39867 #define RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK                                                                0x00000002L
39868 #define RLC_HYP_RESET_VECTOR__WARM_RESET_EXIT_MASK                                                            0x00000004L
39869 #define RLC_HYP_RESET_VECTOR__VF_FLR_EXIT_MASK                                                                0x00000008L
39870 #define RLC_HYP_RESET_VECTOR__RESERVED_4_MASK                                                                 0x00000010L
39871 #define RLC_HYP_RESET_VECTOR__RESERVED_5_MASK                                                                 0x00000020L
39872 #define RLC_HYP_RESET_VECTOR__RESERVED_6_MASK                                                                 0x00000040L
39873 #define RLC_HYP_RESET_VECTOR__RESERVED_7_MASK                                                                 0x00000080L
39874 //RLC_HYP_BOOTLOAD_SIZE
39875 #define RLC_HYP_BOOTLOAD_SIZE__SIZE__SHIFT                                                                    0x0
39876 #define RLC_HYP_BOOTLOAD_SIZE__SIZE_MASK                                                                      0x03FFFFFFL
39877 //RLC_HYP_BOOTLOAD_ADDR_LO
39878 #define RLC_HYP_BOOTLOAD_ADDR_LO__ADDR_LO__SHIFT                                                              0x0
39879 #define RLC_HYP_BOOTLOAD_ADDR_LO__ADDR_LO_MASK                                                                0xFFFFFFFFL
39880 //RLC_HYP_BOOTLOAD_ADDR_HI
39881 #define RLC_HYP_BOOTLOAD_ADDR_HI__ADDR_HI__SHIFT                                                              0x0
39882 #define RLC_HYP_BOOTLOAD_ADDR_HI__ADDR_HI_MASK                                                                0xFFFFFFFFL
39883 //RLC_GPM_IRAM_ADDR
39884 #define RLC_GPM_IRAM_ADDR__ADDR__SHIFT                                                                        0x0
39885 #define RLC_GPM_IRAM_ADDR__ADDR_MASK                                                                          0xFFFFFFFFL
39886 //RLC_GPM_IRAM_DATA
39887 #define RLC_GPM_IRAM_DATA__DATA__SHIFT                                                                        0x0
39888 #define RLC_GPM_IRAM_DATA__DATA_MASK                                                                          0xFFFFFFFFL
39889 //RLC_GPM_UCODE_ADDR
39890 #define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT                                                                 0x0
39891 #define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT                                                                   0xe
39892 #define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK                                                                   0x00003FFFL
39893 #define RLC_GPM_UCODE_ADDR__RESERVED_MASK                                                                     0xFFFFC000L
39894 //RLC_GPM_UCODE_DATA
39895 #define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT                                                                 0x0
39896 #define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK                                                                   0xFFFFFFFFL
39897 //RLC_PACE_UCODE_ADDR
39898 #define RLC_PACE_UCODE_ADDR__UCODE_ADDR__SHIFT                                                                0x0
39899 #define RLC_PACE_UCODE_ADDR__RESERVED__SHIFT                                                                  0xc
39900 #define RLC_PACE_UCODE_ADDR__UCODE_ADDR_MASK                                                                  0x00000FFFL
39901 #define RLC_PACE_UCODE_ADDR__RESERVED_MASK                                                                    0xFFFFF000L
39902 //RLC_PACE_UCODE_DATA
39903 #define RLC_PACE_UCODE_DATA__UCODE_DATA__SHIFT                                                                0x0
39904 #define RLC_PACE_UCODE_DATA__UCODE_DATA_MASK                                                                  0xFFFFFFFFL
39905 //RLC_GPU_IOV_UCODE_ADDR
39906 #define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT                                                             0x0
39907 #define RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT                                                               0xc
39908 #define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK                                                               0x00000FFFL
39909 #define RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK                                                                 0xFFFFF000L
39910 //RLC_GPU_IOV_UCODE_DATA
39911 #define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT                                                             0x0
39912 #define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK                                                               0xFFFFFFFFL
39913 //RLC_GPU_IOV_SCRATCH_ADDR
39914 #define RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT                                                                 0x0
39915 #define RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK                                                                   0xFFFFFFFFL
39916 //RLC_GPU_IOV_SCRATCH_DATA
39917 #define RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT                                                                 0x0
39918 #define RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK                                                                   0xFFFFFFFFL
39919 //RLC_RLCV_IRAM_ADDR
39920 #define RLC_RLCV_IRAM_ADDR__ADDR__SHIFT                                                                       0x0
39921 #define RLC_RLCV_IRAM_ADDR__ADDR_MASK                                                                         0xFFFFFFFFL
39922 //RLC_RLCV_IRAM_DATA
39923 #define RLC_RLCV_IRAM_DATA__DATA__SHIFT                                                                       0x0
39924 #define RLC_RLCV_IRAM_DATA__DATA_MASK                                                                         0xFFFFFFFFL
39925 //RLC_RLCP_IRAM_ADDR
39926 #define RLC_RLCP_IRAM_ADDR__ADDR__SHIFT                                                                       0x0
39927 #define RLC_RLCP_IRAM_ADDR__ADDR_MASK                                                                         0xFFFFFFFFL
39928 //RLC_RLCP_IRAM_DATA
39929 #define RLC_RLCP_IRAM_DATA__DATA__SHIFT                                                                       0x0
39930 #define RLC_RLCP_IRAM_DATA__DATA_MASK                                                                         0xFFFFFFFFL
39931 //RLC_SRM_DRAM_ADDR
39932 #define RLC_SRM_DRAM_ADDR__ADDR__SHIFT                                                                        0x0
39933 #define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT                                                                    0xc
39934 #define RLC_SRM_DRAM_ADDR__ADDR_MASK                                                                          0x00000FFFL
39935 #define RLC_SRM_DRAM_ADDR__RESERVED_MASK                                                                      0xFFFFF000L
39936 //RLC_SRM_DRAM_DATA
39937 #define RLC_SRM_DRAM_DATA__DATA__SHIFT                                                                        0x0
39938 #define RLC_SRM_DRAM_DATA__DATA_MASK                                                                          0xFFFFFFFFL
39939 //RLC_SRM_ARAM_ADDR
39940 #define RLC_SRM_ARAM_ADDR__ADDR__SHIFT                                                                        0x0
39941 #define RLC_SRM_ARAM_ADDR__RESERVED__SHIFT                                                                    0xc
39942 #define RLC_SRM_ARAM_ADDR__ADDR_MASK                                                                          0x00000FFFL
39943 #define RLC_SRM_ARAM_ADDR__RESERVED_MASK                                                                      0xFFFFF000L
39944 //RLC_SRM_ARAM_DATA
39945 #define RLC_SRM_ARAM_DATA__DATA__SHIFT                                                                        0x0
39946 #define RLC_SRM_ARAM_DATA__DATA_MASK                                                                          0xFFFFFFFFL
39947 //RLC_GPM_SCRATCH_ADDR
39948 #define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT                                                                     0x0
39949 #define RLC_GPM_SCRATCH_ADDR__ADDR_MASK                                                                       0xFFFFFFFFL
39950 //RLC_GPM_SCRATCH_DATA
39951 #define RLC_GPM_SCRATCH_DATA__DATA__SHIFT                                                                     0x0
39952 #define RLC_GPM_SCRATCH_DATA__DATA_MASK                                                                       0xFFFFFFFFL
39953 //RLC_GTS_OFFSET_LSB
39954 #define RLC_GTS_OFFSET_LSB__DATA__SHIFT                                                                       0x0
39955 #define RLC_GTS_OFFSET_LSB__DATA_MASK                                                                         0xFFFFFFFFL
39956 //RLC_GTS_OFFSET_MSB
39957 #define RLC_GTS_OFFSET_MSB__DATA__SHIFT                                                                       0x0
39958 #define RLC_GTS_OFFSET_MSB__DATA_MASK                                                                         0xFFFFFFFFL
39959 
39960 
39961 // addressBlock: gc_sdma0_sdma0hypdec
39962 //SDMA0_UCODE_ADDR
39963 #define SDMA0_UCODE_ADDR__VALUE__SHIFT                                                                        0x0
39964 #define SDMA0_UCODE_ADDR__VALUE_MASK                                                                          0x00003FFFL
39965 //SDMA0_UCODE_DATA
39966 #define SDMA0_UCODE_DATA__VALUE__SHIFT                                                                        0x0
39967 #define SDMA0_UCODE_DATA__VALUE_MASK                                                                          0xFFFFFFFFL
39968 //SDMA0_VM_CTX_LO
39969 #define SDMA0_VM_CTX_LO__ADDR__SHIFT                                                                          0x2
39970 #define SDMA0_VM_CTX_LO__ADDR_MASK                                                                            0xFFFFFFFCL
39971 //SDMA0_VM_CTX_HI
39972 #define SDMA0_VM_CTX_HI__ADDR__SHIFT                                                                          0x0
39973 #define SDMA0_VM_CTX_HI__ADDR_MASK                                                                            0xFFFFFFFFL
39974 //SDMA0_ACTIVE_FCN_ID
39975 #define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT                                                                      0x0
39976 #define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT                                                                  0x5
39977 #define SDMA0_ACTIVE_FCN_ID__VF__SHIFT                                                                        0x1f
39978 #define SDMA0_ACTIVE_FCN_ID__VFID_MASK                                                                        0x0000001FL
39979 #define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK                                                                    0x7FFFFFE0L
39980 #define SDMA0_ACTIVE_FCN_ID__VF_MASK                                                                          0x80000000L
39981 //SDMA0_VM_CTX_CNTL
39982 #define SDMA0_VM_CTX_CNTL__PRIV__SHIFT                                                                        0x0
39983 #define SDMA0_VM_CTX_CNTL__VMID__SHIFT                                                                        0x4
39984 #define SDMA0_VM_CTX_CNTL__PRIV_MASK                                                                          0x00000001L
39985 #define SDMA0_VM_CTX_CNTL__VMID_MASK                                                                          0x000000F0L
39986 //SDMA0_VIRT_RESET_REQ
39987 #define SDMA0_VIRT_RESET_REQ__VF__SHIFT                                                                       0x0
39988 #define SDMA0_VIRT_RESET_REQ__PF__SHIFT                                                                       0x1f
39989 #define SDMA0_VIRT_RESET_REQ__VF_MASK                                                                         0x7FFFFFFFL
39990 #define SDMA0_VIRT_RESET_REQ__PF_MASK                                                                         0x80000000L
39991 //SDMA0_VF_ENABLE
39992 #define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT                                                                     0x0
39993 #define SDMA0_VF_ENABLE__VF_ENABLE_MASK                                                                       0x00000001L
39994 //SDMA0_CONTEXT_REG_TYPE0
39995 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT                                                     0x0
39996 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT                                                     0x1
39997 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT                                                  0x2
39998 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT                                                     0x3
39999 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI__SHIFT                                                  0x4
40000 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT                                                     0x5
40001 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI__SHIFT                                                  0x6
40002 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT                                           0x7
40003 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT                                             0x8
40004 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT                                             0x9
40005 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT                                                     0xa
40006 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT                                                     0xb
40007 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT                                                   0xc
40008 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT                                                  0xd
40009 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT                                                  0xe
40010 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT                                                     0xf
40011 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT                                                   0x10
40012 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT                                              0x11
40013 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT                                                    0x12
40014 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT                                                0x13
40015 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK                                                       0x00000001L
40016 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK                                                       0x00000002L
40017 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK                                                    0x00000004L
40018 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK                                                       0x00000008L
40019 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI_MASK                                                    0x00000010L
40020 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK                                                       0x00000020L
40021 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI_MASK                                                    0x00000040L
40022 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK                                             0x00000080L
40023 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK                                               0x00000100L
40024 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK                                               0x00000200L
40025 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK                                                       0x00000400L
40026 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK                                                       0x00000800L
40027 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK                                                     0x00001000L
40028 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK                                                    0x00002000L
40029 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK                                                    0x00004000L
40030 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK                                                       0x00008000L
40031 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK                                                     0x00010000L
40032 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK                                                0x00020000L
40033 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK                                                      0x00040000L
40034 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK                                                  0x00080000L
40035 //SDMA0_CONTEXT_REG_TYPE1
40036 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS__SHIFT                                                      0x8
40037 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT                                                   0xa
40038 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET__SHIFT                                             0xb
40039 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT                                                 0xc
40040 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT                                                 0xd
40041 #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT                                                             0xe
40042 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT                                               0xf
40043 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT                                                     0x10
40044 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT                                                   0x11
40045 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT                                        0x12
40046 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT                                        0x13
40047 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL__SHIFT                                                 0x14
40048 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE__SHIFT                                            0x15
40049 #define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT                                                              0x18
40050 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS_MASK                                                        0x00000100L
40051 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK                                                     0x00000400L
40052 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET_MASK                                               0x00000800L
40053 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK                                                   0x00001000L
40054 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK                                                   0x00002000L
40055 #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK                                                               0x00004000L
40056 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK                                                 0x00008000L
40057 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK                                                       0x00010000L
40058 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK                                                     0x00020000L
40059 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK                                          0x00040000L
40060 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK                                          0x00080000L
40061 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL_MASK                                                   0x00100000L
40062 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE_MASK                                              0x00200000L
40063 #define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK                                                                0xFF000000L
40064 //SDMA0_CONTEXT_REG_TYPE2
40065 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT                                                0x0
40066 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT                                                0x1
40067 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT                                                0x2
40068 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT                                                0x3
40069 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT                                                0x4
40070 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT                                                0x5
40071 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT                                                0x6
40072 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT                                                0x7
40073 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT                                                0x8
40074 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT                                                 0x9
40075 #define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT                                                              0xa
40076 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK                                                  0x00000001L
40077 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK                                                  0x00000002L
40078 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK                                                  0x00000004L
40079 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK                                                  0x00000008L
40080 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK                                                  0x00000010L
40081 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK                                                  0x00000020L
40082 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK                                                  0x00000040L
40083 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK                                                  0x00000080L
40084 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK                                                  0x00000100L
40085 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK                                                   0x00000200L
40086 #define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK                                                                0xFFFFFC00L
40087 //SDMA0_CONTEXT_REG_TYPE3
40088 #define SDMA0_CONTEXT_REG_TYPE3__RESERVED__SHIFT                                                              0x0
40089 #define SDMA0_CONTEXT_REG_TYPE3__RESERVED_MASK                                                                0xFFFFFFFFL
40090 //SDMA0_VM_CNTL
40091 #define SDMA0_VM_CNTL__CMD__SHIFT                                                                             0x0
40092 #define SDMA0_VM_CNTL__CMD_MASK                                                                               0x0000000FL
40093 
40094 
40095 // addressBlock: gc_sdma1_sdma1hypdec
40096 //SDMA1_UCODE_ADDR
40097 #define SDMA1_UCODE_ADDR__VALUE__SHIFT                                                                        0x0
40098 #define SDMA1_UCODE_ADDR__VALUE_MASK                                                                          0x00003FFFL
40099 //SDMA1_UCODE_DATA
40100 #define SDMA1_UCODE_DATA__VALUE__SHIFT                                                                        0x0
40101 #define SDMA1_UCODE_DATA__VALUE_MASK                                                                          0xFFFFFFFFL
40102 //SDMA1_VM_CTX_LO
40103 #define SDMA1_VM_CTX_LO__ADDR__SHIFT                                                                          0x2
40104 #define SDMA1_VM_CTX_LO__ADDR_MASK                                                                            0xFFFFFFFCL
40105 //SDMA1_VM_CTX_HI
40106 #define SDMA1_VM_CTX_HI__ADDR__SHIFT                                                                          0x0
40107 #define SDMA1_VM_CTX_HI__ADDR_MASK                                                                            0xFFFFFFFFL
40108 //SDMA1_ACTIVE_FCN_ID
40109 #define SDMA1_ACTIVE_FCN_ID__VFID__SHIFT                                                                      0x0
40110 #define SDMA1_ACTIVE_FCN_ID__RESERVED__SHIFT                                                                  0x5
40111 #define SDMA1_ACTIVE_FCN_ID__VF__SHIFT                                                                        0x1f
40112 #define SDMA1_ACTIVE_FCN_ID__VFID_MASK                                                                        0x0000001FL
40113 #define SDMA1_ACTIVE_FCN_ID__RESERVED_MASK                                                                    0x7FFFFFE0L
40114 #define SDMA1_ACTIVE_FCN_ID__VF_MASK                                                                          0x80000000L
40115 //SDMA1_VM_CTX_CNTL
40116 #define SDMA1_VM_CTX_CNTL__PRIV__SHIFT                                                                        0x0
40117 #define SDMA1_VM_CTX_CNTL__VMID__SHIFT                                                                        0x4
40118 #define SDMA1_VM_CTX_CNTL__PRIV_MASK                                                                          0x00000001L
40119 #define SDMA1_VM_CTX_CNTL__VMID_MASK                                                                          0x000000F0L
40120 //SDMA1_VIRT_RESET_REQ
40121 #define SDMA1_VIRT_RESET_REQ__VF__SHIFT                                                                       0x0
40122 #define SDMA1_VIRT_RESET_REQ__PF__SHIFT                                                                       0x1f
40123 #define SDMA1_VIRT_RESET_REQ__VF_MASK                                                                         0x7FFFFFFFL
40124 #define SDMA1_VIRT_RESET_REQ__PF_MASK                                                                         0x80000000L
40125 //SDMA1_VF_ENABLE
40126 #define SDMA1_VF_ENABLE__VF_ENABLE__SHIFT                                                                     0x0
40127 #define SDMA1_VF_ENABLE__VF_ENABLE_MASK                                                                       0x00000001L
40128 //SDMA1_CONTEXT_REG_TYPE0
40129 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL__SHIFT                                                     0x0
40130 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE__SHIFT                                                     0x1
40131 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI__SHIFT                                                  0x2
40132 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR__SHIFT                                                     0x3
40133 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI__SHIFT                                                  0x4
40134 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR__SHIFT                                                     0x5
40135 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI__SHIFT                                                  0x6
40136 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL__SHIFT                                           0x7
40137 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI__SHIFT                                             0x8
40138 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO__SHIFT                                             0x9
40139 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT                                                     0xa
40140 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR__SHIFT                                                     0xb
40141 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET__SHIFT                                                   0xc
40142 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO__SHIFT                                                  0xd
40143 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI__SHIFT                                                  0xe
40144 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE__SHIFT                                                     0xf
40145 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL__SHIFT                                                   0x10
40146 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS__SHIFT                                              0x11
40147 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL__SHIFT                                                    0x12
40148 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL__SHIFT                                                0x13
40149 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL_MASK                                                       0x00000001L
40150 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_MASK                                                       0x00000002L
40151 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI_MASK                                                    0x00000004L
40152 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_MASK                                                       0x00000008L
40153 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI_MASK                                                    0x00000010L
40154 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_MASK                                                       0x00000020L
40155 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI_MASK                                                    0x00000040L
40156 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL_MASK                                             0x00000080L
40157 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI_MASK                                               0x00000100L
40158 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO_MASK                                               0x00000200L
40159 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL_MASK                                                       0x00000400L
40160 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR_MASK                                                       0x00000800L
40161 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET_MASK                                                     0x00001000L
40162 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO_MASK                                                    0x00002000L
40163 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI_MASK                                                    0x00004000L
40164 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE_MASK                                                       0x00008000L
40165 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL_MASK                                                     0x00010000L
40166 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS_MASK                                                0x00020000L
40167 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL_MASK                                                      0x00040000L
40168 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL_MASK                                                  0x00080000L
40169 //SDMA1_CONTEXT_REG_TYPE1
40170 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS__SHIFT                                                      0x8
40171 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT                                                   0xa
40172 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET__SHIFT                                             0xb
40173 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO__SHIFT                                                 0xc
40174 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI__SHIFT                                                 0xd
40175 #define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT                                                             0xe
40176 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN__SHIFT                                               0xf
40177 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT__SHIFT                                                     0x10
40178 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG__SHIFT                                                   0x11
40179 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT                                        0x12
40180 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT                                        0x13
40181 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL__SHIFT                                                 0x14
40182 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE__SHIFT                                            0x15
40183 #define SDMA1_CONTEXT_REG_TYPE1__RESERVED__SHIFT                                                              0x18
40184 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS_MASK                                                        0x00000100L
40185 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK_MASK                                                     0x00000400L
40186 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET_MASK                                               0x00000800L
40187 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO_MASK                                                   0x00001000L
40188 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI_MASK                                                   0x00002000L
40189 #define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2_MASK                                                               0x00004000L
40190 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN_MASK                                                 0x00008000L
40191 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT_MASK                                                       0x00010000L
40192 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG_MASK                                                     0x00020000L
40193 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI_MASK                                          0x00040000L
40194 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO_MASK                                          0x00080000L
40195 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL_MASK                                                   0x00100000L
40196 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE_MASK                                              0x00200000L
40197 #define SDMA1_CONTEXT_REG_TYPE1__RESERVED_MASK                                                                0xFF000000L
40198 //SDMA1_CONTEXT_REG_TYPE2
40199 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0__SHIFT                                                0x0
40200 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1__SHIFT                                                0x1
40201 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2__SHIFT                                                0x2
40202 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3__SHIFT                                                0x3
40203 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4__SHIFT                                                0x4
40204 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5__SHIFT                                                0x5
40205 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6__SHIFT                                                0x6
40206 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7__SHIFT                                                0x7
40207 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8__SHIFT                                                0x8
40208 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL__SHIFT                                                 0x9
40209 #define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT                                                              0xa
40210 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0_MASK                                                  0x00000001L
40211 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1_MASK                                                  0x00000002L
40212 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2_MASK                                                  0x00000004L
40213 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3_MASK                                                  0x00000008L
40214 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4_MASK                                                  0x00000010L
40215 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5_MASK                                                  0x00000020L
40216 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6_MASK                                                  0x00000040L
40217 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7_MASK                                                  0x00000080L
40218 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8_MASK                                                  0x00000100L
40219 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL_MASK                                                   0x00000200L
40220 #define SDMA1_CONTEXT_REG_TYPE2__RESERVED_MASK                                                                0xFFFFFC00L
40221 //SDMA1_CONTEXT_REG_TYPE3
40222 #define SDMA1_CONTEXT_REG_TYPE3__RESERVED__SHIFT                                                              0x0
40223 #define SDMA1_CONTEXT_REG_TYPE3__RESERVED_MASK                                                                0xFFFFFFFFL
40224 //SDMA1_VM_CNTL
40225 #define SDMA1_VM_CNTL__CMD__SHIFT                                                                             0x0
40226 #define SDMA1_VM_CNTL__CMD_MASK                                                                               0x0000000FL
40227 
40228 
40229 // addressBlock: gc_gcvmsharedhvdec
40230 //GCMC_VM_FB_SIZE_OFFSET_VF0
40231 #define GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT                                                         0x0
40232 #define GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT                                                       0x10
40233 #define GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK                                                           0x0000FFFFL
40234 #define GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK                                                         0xFFFF0000L
40235 //GCMC_VM_FB_SIZE_OFFSET_VF1
40236 #define GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT                                                         0x0
40237 #define GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT                                                       0x10
40238 #define GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK                                                           0x0000FFFFL
40239 #define GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK                                                         0xFFFF0000L
40240 //GCMC_VM_FB_SIZE_OFFSET_VF2
40241 #define GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT                                                         0x0
40242 #define GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT                                                       0x10
40243 #define GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK                                                           0x0000FFFFL
40244 #define GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK                                                         0xFFFF0000L
40245 //GCMC_VM_FB_SIZE_OFFSET_VF3
40246 #define GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT                                                         0x0
40247 #define GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT                                                       0x10
40248 #define GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK                                                           0x0000FFFFL
40249 #define GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK                                                         0xFFFF0000L
40250 //GCMC_VM_FB_SIZE_OFFSET_VF4
40251 #define GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT                                                         0x0
40252 #define GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT                                                       0x10
40253 #define GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK                                                           0x0000FFFFL
40254 #define GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK                                                         0xFFFF0000L
40255 //GCMC_VM_FB_SIZE_OFFSET_VF5
40256 #define GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT                                                         0x0
40257 #define GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT                                                       0x10
40258 #define GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK                                                           0x0000FFFFL
40259 #define GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK                                                         0xFFFF0000L
40260 //GCMC_VM_FB_SIZE_OFFSET_VF6
40261 #define GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT                                                         0x0
40262 #define GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT                                                       0x10
40263 #define GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK                                                           0x0000FFFFL
40264 #define GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK                                                         0xFFFF0000L
40265 //GCMC_VM_FB_SIZE_OFFSET_VF7
40266 #define GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT                                                         0x0
40267 #define GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT                                                       0x10
40268 #define GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK                                                           0x0000FFFFL
40269 #define GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK                                                         0xFFFF0000L
40270 //GCMC_VM_FB_SIZE_OFFSET_VF8
40271 #define GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT                                                         0x0
40272 #define GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT                                                       0x10
40273 #define GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK                                                           0x0000FFFFL
40274 #define GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK                                                         0xFFFF0000L
40275 //GCMC_VM_FB_SIZE_OFFSET_VF9
40276 #define GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT                                                         0x0
40277 #define GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT                                                       0x10
40278 #define GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK                                                           0x0000FFFFL
40279 #define GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK                                                         0xFFFF0000L
40280 //GCMC_VM_FB_SIZE_OFFSET_VF10
40281 #define GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT                                                        0x0
40282 #define GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT                                                      0x10
40283 #define GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK                                                          0x0000FFFFL
40284 #define GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
40285 //GCMC_VM_FB_SIZE_OFFSET_VF11
40286 #define GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT                                                        0x0
40287 #define GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT                                                      0x10
40288 #define GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK                                                          0x0000FFFFL
40289 #define GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
40290 //GCMC_VM_FB_SIZE_OFFSET_VF12
40291 #define GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT                                                        0x0
40292 #define GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT                                                      0x10
40293 #define GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK                                                          0x0000FFFFL
40294 #define GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
40295 //GCMC_VM_FB_SIZE_OFFSET_VF13
40296 #define GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT                                                        0x0
40297 #define GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT                                                      0x10
40298 #define GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK                                                          0x0000FFFFL
40299 #define GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
40300 //GCMC_VM_FB_SIZE_OFFSET_VF14
40301 #define GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT                                                        0x0
40302 #define GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT                                                      0x10
40303 #define GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK                                                          0x0000FFFFL
40304 #define GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
40305 //GCMC_VM_FB_SIZE_OFFSET_VF15
40306 #define GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT                                                        0x0
40307 #define GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT                                                      0x10
40308 #define GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK                                                          0x0000FFFFL
40309 #define GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
40310 //GCMC_VM_FB_SIZE_OFFSET_VF16
40311 #define GCMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_SIZE__SHIFT                                                        0x0
40312 #define GCMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_OFFSET__SHIFT                                                      0x10
40313 #define GCMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_SIZE_MASK                                                          0x0000FFFFL
40314 #define GCMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
40315 //GCMC_VM_FB_SIZE_OFFSET_VF17
40316 #define GCMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_SIZE__SHIFT                                                        0x0
40317 #define GCMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_OFFSET__SHIFT                                                      0x10
40318 #define GCMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_SIZE_MASK                                                          0x0000FFFFL
40319 #define GCMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
40320 //GCMC_VM_FB_SIZE_OFFSET_VF18
40321 #define GCMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_SIZE__SHIFT                                                        0x0
40322 #define GCMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_OFFSET__SHIFT                                                      0x10
40323 #define GCMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_SIZE_MASK                                                          0x0000FFFFL
40324 #define GCMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
40325 //GCMC_VM_FB_SIZE_OFFSET_VF19
40326 #define GCMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_SIZE__SHIFT                                                        0x0
40327 #define GCMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_OFFSET__SHIFT                                                      0x10
40328 #define GCMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_SIZE_MASK                                                          0x0000FFFFL
40329 #define GCMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
40330 //GCMC_VM_FB_SIZE_OFFSET_VF20
40331 #define GCMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_SIZE__SHIFT                                                        0x0
40332 #define GCMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_OFFSET__SHIFT                                                      0x10
40333 #define GCMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_SIZE_MASK                                                          0x0000FFFFL
40334 #define GCMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
40335 //GCMC_VM_FB_SIZE_OFFSET_VF21
40336 #define GCMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_SIZE__SHIFT                                                        0x0
40337 #define GCMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_OFFSET__SHIFT                                                      0x10
40338 #define GCMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_SIZE_MASK                                                          0x0000FFFFL
40339 #define GCMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
40340 //GCMC_VM_FB_SIZE_OFFSET_VF22
40341 #define GCMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_SIZE__SHIFT                                                        0x0
40342 #define GCMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_OFFSET__SHIFT                                                      0x10
40343 #define GCMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_SIZE_MASK                                                          0x0000FFFFL
40344 #define GCMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
40345 //GCMC_VM_FB_SIZE_OFFSET_VF23
40346 #define GCMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_SIZE__SHIFT                                                        0x0
40347 #define GCMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_OFFSET__SHIFT                                                      0x10
40348 #define GCMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_SIZE_MASK                                                          0x0000FFFFL
40349 #define GCMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
40350 //GCMC_VM_FB_SIZE_OFFSET_VF24
40351 #define GCMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_SIZE__SHIFT                                                        0x0
40352 #define GCMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_OFFSET__SHIFT                                                      0x10
40353 #define GCMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_SIZE_MASK                                                          0x0000FFFFL
40354 #define GCMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
40355 //GCMC_VM_FB_SIZE_OFFSET_VF25
40356 #define GCMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_SIZE__SHIFT                                                        0x0
40357 #define GCMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_OFFSET__SHIFT                                                      0x10
40358 #define GCMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_SIZE_MASK                                                          0x0000FFFFL
40359 #define GCMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
40360 //GCMC_VM_FB_SIZE_OFFSET_VF26
40361 #define GCMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_SIZE__SHIFT                                                        0x0
40362 #define GCMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_OFFSET__SHIFT                                                      0x10
40363 #define GCMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_SIZE_MASK                                                          0x0000FFFFL
40364 #define GCMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
40365 //GCMC_VM_FB_SIZE_OFFSET_VF27
40366 #define GCMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_SIZE__SHIFT                                                        0x0
40367 #define GCMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_OFFSET__SHIFT                                                      0x10
40368 #define GCMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_SIZE_MASK                                                          0x0000FFFFL
40369 #define GCMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
40370 //GCMC_VM_FB_SIZE_OFFSET_VF28
40371 #define GCMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_SIZE__SHIFT                                                        0x0
40372 #define GCMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_OFFSET__SHIFT                                                      0x10
40373 #define GCMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_SIZE_MASK                                                          0x0000FFFFL
40374 #define GCMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
40375 //GCMC_VM_FB_SIZE_OFFSET_VF29
40376 #define GCMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_SIZE__SHIFT                                                        0x0
40377 #define GCMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_OFFSET__SHIFT                                                      0x10
40378 #define GCMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_SIZE_MASK                                                          0x0000FFFFL
40379 #define GCMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
40380 //GCMC_VM_FB_SIZE_OFFSET_VF30
40381 #define GCMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_SIZE__SHIFT                                                        0x0
40382 #define GCMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_OFFSET__SHIFT                                                      0x10
40383 #define GCMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_SIZE_MASK                                                          0x0000FFFFL
40384 #define GCMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
40385 //GCMC_VM_FB_SIZE_OFFSET_VF31
40386 #define GCMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_SIZE__SHIFT                                                        0x0
40387 #define GCMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_OFFSET__SHIFT                                                      0x10
40388 #define GCMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_SIZE_MASK                                                          0x0000FFFFL
40389 #define GCMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
40390 //GCVM_IOMMU_MMIO_CNTRL_1
40391 #define GCVM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT                                                               0x8
40392 #define GCVM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK                                                                 0x00000100L
40393 //GCMC_VM_MARC_BASE_LO_0
40394 #define GCMC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT                                                         0xc
40395 #define GCMC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK                                                           0xFFFFF000L
40396 //GCMC_VM_MARC_BASE_LO_1
40397 #define GCMC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT                                                         0xc
40398 #define GCMC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK                                                           0xFFFFF000L
40399 //GCMC_VM_MARC_BASE_LO_2
40400 #define GCMC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT                                                         0xc
40401 #define GCMC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK                                                           0xFFFFF000L
40402 //GCMC_VM_MARC_BASE_LO_3
40403 #define GCMC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT                                                         0xc
40404 #define GCMC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK                                                           0xFFFFF000L
40405 //GCMC_VM_MARC_BASE_HI_0
40406 #define GCMC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT                                                         0x0
40407 #define GCMC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK                                                           0x000FFFFFL
40408 //GCMC_VM_MARC_BASE_HI_1
40409 #define GCMC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT                                                         0x0
40410 #define GCMC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK                                                           0x000FFFFFL
40411 //GCMC_VM_MARC_BASE_HI_2
40412 #define GCMC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT                                                         0x0
40413 #define GCMC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK                                                           0x000FFFFFL
40414 //GCMC_VM_MARC_BASE_HI_3
40415 #define GCMC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT                                                         0x0
40416 #define GCMC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK                                                           0x000FFFFFL
40417 //GCMC_VM_MARC_RELOC_LO_0
40418 #define GCMC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT                                                         0x0
40419 #define GCMC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT                                                       0x1
40420 #define GCMC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT                                                       0xc
40421 #define GCMC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK                                                           0x00000001L
40422 #define GCMC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK                                                         0x00000002L
40423 #define GCMC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK                                                         0xFFFFF000L
40424 //GCMC_VM_MARC_RELOC_LO_1
40425 #define GCMC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT                                                         0x0
40426 #define GCMC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT                                                       0x1
40427 #define GCMC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT                                                       0xc
40428 #define GCMC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK                                                           0x00000001L
40429 #define GCMC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK                                                         0x00000002L
40430 #define GCMC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK                                                         0xFFFFF000L
40431 //GCMC_VM_MARC_RELOC_LO_2
40432 #define GCMC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT                                                         0x0
40433 #define GCMC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT                                                       0x1
40434 #define GCMC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT                                                       0xc
40435 #define GCMC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK                                                           0x00000001L
40436 #define GCMC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK                                                         0x00000002L
40437 #define GCMC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK                                                         0xFFFFF000L
40438 //GCMC_VM_MARC_RELOC_LO_3
40439 #define GCMC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT                                                         0x0
40440 #define GCMC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT                                                       0x1
40441 #define GCMC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT                                                       0xc
40442 #define GCMC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK                                                           0x00000001L
40443 #define GCMC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK                                                         0x00000002L
40444 #define GCMC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK                                                         0xFFFFF000L
40445 //GCMC_VM_MARC_RELOC_HI_0
40446 #define GCMC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT                                                       0x0
40447 #define GCMC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK                                                         0x000FFFFFL
40448 //GCMC_VM_MARC_RELOC_HI_1
40449 #define GCMC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT                                                       0x0
40450 #define GCMC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK                                                         0x000FFFFFL
40451 //GCMC_VM_MARC_RELOC_HI_2
40452 #define GCMC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT                                                       0x0
40453 #define GCMC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK                                                         0x000FFFFFL
40454 //GCMC_VM_MARC_RELOC_HI_3
40455 #define GCMC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT                                                       0x0
40456 #define GCMC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK                                                         0x000FFFFFL
40457 //GCMC_VM_MARC_LEN_LO_0
40458 #define GCMC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT                                                           0xc
40459 #define GCMC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK                                                             0xFFFFF000L
40460 //GCMC_VM_MARC_LEN_LO_1
40461 #define GCMC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT                                                           0xc
40462 #define GCMC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK                                                             0xFFFFF000L
40463 //GCMC_VM_MARC_LEN_LO_2
40464 #define GCMC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT                                                           0xc
40465 #define GCMC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK                                                             0xFFFFF000L
40466 //GCMC_VM_MARC_LEN_LO_3
40467 #define GCMC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT                                                           0xc
40468 #define GCMC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK                                                             0xFFFFF000L
40469 //GCMC_VM_MARC_LEN_HI_0
40470 #define GCMC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT                                                           0x0
40471 #define GCMC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK                                                             0x000FFFFFL
40472 //GCMC_VM_MARC_LEN_HI_1
40473 #define GCMC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT                                                           0x0
40474 #define GCMC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK                                                             0x000FFFFFL
40475 //GCMC_VM_MARC_LEN_HI_2
40476 #define GCMC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT                                                           0x0
40477 #define GCMC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK                                                             0x000FFFFFL
40478 //GCMC_VM_MARC_LEN_HI_3
40479 #define GCMC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT                                                           0x0
40480 #define GCMC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK                                                             0x000FFFFFL
40481 //GCVM_IOMMU_CONTROL_REGISTER
40482 #define GCVM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT                                                           0x0
40483 #define GCVM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK                                                             0x00000001L
40484 //GCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER
40485 #define GCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT                                0xd
40486 #define GCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK                                  0x00002000L
40487 //GCVM_PCIE_ATS_CNTL
40488 #define GCVM_PCIE_ATS_CNTL__STU__SHIFT                                                                        0x10
40489 #define GCVM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                                                 0x1f
40490 #define GCVM_PCIE_ATS_CNTL__STU_MASK                                                                          0x001F0000L
40491 #define GCVM_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                                   0x80000000L
40492 //GCVM_PCIE_ATS_CNTL_VF_0
40493 #define GCVM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT                                                            0x1f
40494 #define GCVM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK                                                              0x80000000L
40495 //GCVM_PCIE_ATS_CNTL_VF_1
40496 #define GCVM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT                                                            0x1f
40497 #define GCVM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK                                                              0x80000000L
40498 //GCVM_PCIE_ATS_CNTL_VF_2
40499 #define GCVM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT                                                            0x1f
40500 #define GCVM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK                                                              0x80000000L
40501 //GCVM_PCIE_ATS_CNTL_VF_3
40502 #define GCVM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT                                                            0x1f
40503 #define GCVM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK                                                              0x80000000L
40504 //GCVM_PCIE_ATS_CNTL_VF_4
40505 #define GCVM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT                                                            0x1f
40506 #define GCVM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK                                                              0x80000000L
40507 //GCVM_PCIE_ATS_CNTL_VF_5
40508 #define GCVM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT                                                            0x1f
40509 #define GCVM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK                                                              0x80000000L
40510 //GCVM_PCIE_ATS_CNTL_VF_6
40511 #define GCVM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT                                                            0x1f
40512 #define GCVM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK                                                              0x80000000L
40513 //GCVM_PCIE_ATS_CNTL_VF_7
40514 #define GCVM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT                                                            0x1f
40515 #define GCVM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK                                                              0x80000000L
40516 //GCVM_PCIE_ATS_CNTL_VF_8
40517 #define GCVM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT                                                            0x1f
40518 #define GCVM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK                                                              0x80000000L
40519 //GCVM_PCIE_ATS_CNTL_VF_9
40520 #define GCVM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT                                                            0x1f
40521 #define GCVM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK                                                              0x80000000L
40522 //GCVM_PCIE_ATS_CNTL_VF_10
40523 #define GCVM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT                                                           0x1f
40524 #define GCVM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK                                                             0x80000000L
40525 //GCVM_PCIE_ATS_CNTL_VF_11
40526 #define GCVM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT                                                           0x1f
40527 #define GCVM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK                                                             0x80000000L
40528 //GCVM_PCIE_ATS_CNTL_VF_12
40529 #define GCVM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT                                                           0x1f
40530 #define GCVM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK                                                             0x80000000L
40531 //GCVM_PCIE_ATS_CNTL_VF_13
40532 #define GCVM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT                                                           0x1f
40533 #define GCVM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK                                                             0x80000000L
40534 //GCVM_PCIE_ATS_CNTL_VF_14
40535 #define GCVM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT                                                           0x1f
40536 #define GCVM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK                                                             0x80000000L
40537 //GCVM_PCIE_ATS_CNTL_VF_15
40538 #define GCVM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT                                                           0x1f
40539 #define GCVM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK                                                             0x80000000L
40540 //GCVM_PCIE_ATS_CNTL_VF_16
40541 #define GCVM_PCIE_ATS_CNTL_VF_16__ATC_ENABLE__SHIFT                                                           0x1f
40542 #define GCVM_PCIE_ATS_CNTL_VF_16__ATC_ENABLE_MASK                                                             0x80000000L
40543 //GCVM_PCIE_ATS_CNTL_VF_17
40544 #define GCVM_PCIE_ATS_CNTL_VF_17__ATC_ENABLE__SHIFT                                                           0x1f
40545 #define GCVM_PCIE_ATS_CNTL_VF_17__ATC_ENABLE_MASK                                                             0x80000000L
40546 //GCVM_PCIE_ATS_CNTL_VF_18
40547 #define GCVM_PCIE_ATS_CNTL_VF_18__ATC_ENABLE__SHIFT                                                           0x1f
40548 #define GCVM_PCIE_ATS_CNTL_VF_18__ATC_ENABLE_MASK                                                             0x80000000L
40549 //GCVM_PCIE_ATS_CNTL_VF_19
40550 #define GCVM_PCIE_ATS_CNTL_VF_19__ATC_ENABLE__SHIFT                                                           0x1f
40551 #define GCVM_PCIE_ATS_CNTL_VF_19__ATC_ENABLE_MASK                                                             0x80000000L
40552 //GCVM_PCIE_ATS_CNTL_VF_20
40553 #define GCVM_PCIE_ATS_CNTL_VF_20__ATC_ENABLE__SHIFT                                                           0x1f
40554 #define GCVM_PCIE_ATS_CNTL_VF_20__ATC_ENABLE_MASK                                                             0x80000000L
40555 //GCVM_PCIE_ATS_CNTL_VF_21
40556 #define GCVM_PCIE_ATS_CNTL_VF_21__ATC_ENABLE__SHIFT                                                           0x1f
40557 #define GCVM_PCIE_ATS_CNTL_VF_21__ATC_ENABLE_MASK                                                             0x80000000L
40558 //GCVM_PCIE_ATS_CNTL_VF_22
40559 #define GCVM_PCIE_ATS_CNTL_VF_22__ATC_ENABLE__SHIFT                                                           0x1f
40560 #define GCVM_PCIE_ATS_CNTL_VF_22__ATC_ENABLE_MASK                                                             0x80000000L
40561 //GCVM_PCIE_ATS_CNTL_VF_23
40562 #define GCVM_PCIE_ATS_CNTL_VF_23__ATC_ENABLE__SHIFT                                                           0x1f
40563 #define GCVM_PCIE_ATS_CNTL_VF_23__ATC_ENABLE_MASK                                                             0x80000000L
40564 //GCVM_PCIE_ATS_CNTL_VF_24
40565 #define GCVM_PCIE_ATS_CNTL_VF_24__ATC_ENABLE__SHIFT                                                           0x1f
40566 #define GCVM_PCIE_ATS_CNTL_VF_24__ATC_ENABLE_MASK                                                             0x80000000L
40567 //GCVM_PCIE_ATS_CNTL_VF_25
40568 #define GCVM_PCIE_ATS_CNTL_VF_25__ATC_ENABLE__SHIFT                                                           0x1f
40569 #define GCVM_PCIE_ATS_CNTL_VF_25__ATC_ENABLE_MASK                                                             0x80000000L
40570 //GCVM_PCIE_ATS_CNTL_VF_26
40571 #define GCVM_PCIE_ATS_CNTL_VF_26__ATC_ENABLE__SHIFT                                                           0x1f
40572 #define GCVM_PCIE_ATS_CNTL_VF_26__ATC_ENABLE_MASK                                                             0x80000000L
40573 //GCVM_PCIE_ATS_CNTL_VF_27
40574 #define GCVM_PCIE_ATS_CNTL_VF_27__ATC_ENABLE__SHIFT                                                           0x1f
40575 #define GCVM_PCIE_ATS_CNTL_VF_27__ATC_ENABLE_MASK                                                             0x80000000L
40576 //GCVM_PCIE_ATS_CNTL_VF_28
40577 #define GCVM_PCIE_ATS_CNTL_VF_28__ATC_ENABLE__SHIFT                                                           0x1f
40578 #define GCVM_PCIE_ATS_CNTL_VF_28__ATC_ENABLE_MASK                                                             0x80000000L
40579 //GCVM_PCIE_ATS_CNTL_VF_29
40580 #define GCVM_PCIE_ATS_CNTL_VF_29__ATC_ENABLE__SHIFT                                                           0x1f
40581 #define GCVM_PCIE_ATS_CNTL_VF_29__ATC_ENABLE_MASK                                                             0x80000000L
40582 //GCVM_PCIE_ATS_CNTL_VF_30
40583 #define GCVM_PCIE_ATS_CNTL_VF_30__ATC_ENABLE__SHIFT                                                           0x1f
40584 #define GCVM_PCIE_ATS_CNTL_VF_30__ATC_ENABLE_MASK                                                             0x80000000L
40585 //GCVM_PCIE_ATS_CNTL_VF_31
40586 #define GCVM_PCIE_ATS_CNTL_VF_31__ATC_ENABLE__SHIFT                                                           0x1f
40587 #define GCVM_PCIE_ATS_CNTL_VF_31__ATC_ENABLE_MASK                                                             0x80000000L
40588 //GCUTCL2_CGTT_CLK_CTRL
40589 #define GCUTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                0x0
40590 #define GCUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                          0x4
40591 #define GCUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT                                                     0xc
40592 #define GCUTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                           0xf
40593 #define GCUTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                     0x10
40594 #define GCUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT                                                           0x18
40595 #define GCUTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                  0x0000000FL
40596 #define GCUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                            0x00000FF0L
40597 #define GCUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK                                                       0x00007000L
40598 #define GCUTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK                                                             0x00008000L
40599 #define GCUTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                       0x00FF0000L
40600 #define GCUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK                                                             0xFF000000L
40601 //GCMC_SHARED_ACTIVE_FCN_ID
40602 #define GCMC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT                                                                0x0
40603 #define GCMC_SHARED_ACTIVE_FCN_ID__VF__SHIFT                                                                  0x1f
40604 #define GCMC_SHARED_ACTIVE_FCN_ID__VFID_MASK                                                                  0x0000001FL
40605 #define GCMC_SHARED_ACTIVE_FCN_ID__VF_MASK                                                                    0x80000000L
40606 
40607 
40608 // addressBlock: gccacind
40609 //PCC_STALL_PATTERN_CTRL
40610 #define PCC_STALL_PATTERN_CTRL__PCC_STEP_INTERVAL__SHIFT                                                      0x0
40611 #define PCC_STALL_PATTERN_CTRL__PCC_BEGIN_STEP__SHIFT                                                         0xa
40612 #define PCC_STALL_PATTERN_CTRL__PCC_END_STEP__SHIFT                                                           0xf
40613 #define PCC_STALL_PATTERN_CTRL__PCC_THROTTLE_PATTERN_BIT_NUMS__SHIFT                                          0x14
40614 #define PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_INCR__SHIFT                                                    0x18
40615 #define PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_DECR__SHIFT                                                    0x19
40616 #define PCC_STALL_PATTERN_CTRL__PCC_DITHER_MODE__SHIFT                                                        0x1a
40617 #define PCC_STALL_PATTERN_CTRL__PCC_STEP_INTERVAL_MASK                                                        0x000003FFL
40618 #define PCC_STALL_PATTERN_CTRL__PCC_BEGIN_STEP_MASK                                                           0x00007C00L
40619 #define PCC_STALL_PATTERN_CTRL__PCC_END_STEP_MASK                                                             0x000F8000L
40620 #define PCC_STALL_PATTERN_CTRL__PCC_THROTTLE_PATTERN_BIT_NUMS_MASK                                            0x00F00000L
40621 #define PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_INCR_MASK                                                      0x01000000L
40622 #define PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_DECR_MASK                                                      0x02000000L
40623 #define PCC_STALL_PATTERN_CTRL__PCC_DITHER_MODE_MASK                                                          0x04000000L
40624 //PWRBRK_STALL_PATTERN_CTRL
40625 #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT                                                0x0
40626 #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT                                                   0xa
40627 #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT                                                     0xf
40628 #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT                                    0x14
40629 #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL_MASK                                                  0x000003FFL
40630 #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP_MASK                                                     0x00007C00L
40631 #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP_MASK                                                       0x000F8000L
40632 #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS_MASK                                      0x00F00000L
40633 //PCC_STALL_PATTERN_1_2
40634 #define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_1__SHIFT                                                     0x0
40635 #define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_2__SHIFT                                                     0x10
40636 #define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_1_MASK                                                       0x00007FFFL
40637 #define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_2_MASK                                                       0x7FFF0000L
40638 //PCC_STALL_PATTERN_3_4
40639 #define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_3__SHIFT                                                     0x0
40640 #define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_4__SHIFT                                                     0x10
40641 #define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_3_MASK                                                       0x00007FFFL
40642 #define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_4_MASK                                                       0x7FFF0000L
40643 //PCC_STALL_PATTERN_5_6
40644 #define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_5__SHIFT                                                     0x0
40645 #define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_6__SHIFT                                                     0x10
40646 #define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_5_MASK                                                       0x00007FFFL
40647 #define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_6_MASK                                                       0x7FFF0000L
40648 //PCC_STALL_PATTERN_7
40649 #define PCC_STALL_PATTERN_7__PCC_STALL_PATTERN_7__SHIFT                                                       0x0
40650 #define PCC_STALL_PATTERN_7__PCC_STALL_PATTERN_7_MASK                                                         0x00007FFFL
40651 //PWRBRK_STALL_PATTERN_1_2
40652 #define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_1__SHIFT                                               0x0
40653 #define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_2__SHIFT                                               0x10
40654 #define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_1_MASK                                                 0x00007FFFL
40655 #define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_2_MASK                                                 0x7FFF0000L
40656 //PWRBRK_STALL_PATTERN_3_4
40657 #define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_3__SHIFT                                               0x0
40658 #define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_4__SHIFT                                               0x10
40659 #define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_3_MASK                                                 0x00007FFFL
40660 #define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_4_MASK                                                 0x7FFF0000L
40661 //PWRBRK_STALL_PATTERN_5_6
40662 #define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_5__SHIFT                                               0x0
40663 #define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_6__SHIFT                                               0x10
40664 #define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_5_MASK                                                 0x00007FFFL
40665 #define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_6_MASK                                                 0x7FFF0000L
40666 //PWRBRK_STALL_PATTERN_7
40667 #define PWRBRK_STALL_PATTERN_7__PWRBRK_STALL_PATTERN_7__SHIFT                                                 0x0
40668 #define PWRBRK_STALL_PATTERN_7__PWRBRK_STALL_PATTERN_7_MASK                                                   0x00007FFFL
40669 //GC_CAC_ID
40670 #define GC_CAC_ID__CAC_BLOCK_ID__SHIFT                                                                        0x0
40671 #define GC_CAC_ID__CAC_SIGNAL_ID__SHIFT                                                                       0x6
40672 #define GC_CAC_ID__UNUSED_0__SHIFT                                                                            0xe
40673 #define GC_CAC_ID__CAC_BLOCK_ID_MASK                                                                          0x0000003FL
40674 #define GC_CAC_ID__CAC_SIGNAL_ID_MASK                                                                         0x00003FC0L
40675 #define GC_CAC_ID__UNUSED_0_MASK                                                                              0xFFFFC000L
40676 //GC_CAC_CNTL
40677 #define GC_CAC_CNTL__CAC_FORCE_DISABLE__SHIFT                                                                 0x0
40678 #define GC_CAC_CNTL__CAC_THRESHOLD__SHIFT                                                                     0x1
40679 #define GC_CAC_CNTL__UNUSED_0__SHIFT                                                                          0x11
40680 #define GC_CAC_CNTL__CAC_FORCE_DISABLE_MASK                                                                   0x00000001L
40681 #define GC_CAC_CNTL__CAC_THRESHOLD_MASK                                                                       0x0001FFFEL
40682 #define GC_CAC_CNTL__UNUSED_0_MASK                                                                            0xFFFE0000L
40683 //GC_CAC_OVR_SEL
40684 #define GC_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT                                                                    0x0
40685 #define GC_CAC_OVR_SEL__CAC_OVR_SEL_MASK                                                                      0xFFFFFFFFL
40686 //GC_CAC_OVR_VAL
40687 #define GC_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT                                                                    0x0
40688 #define GC_CAC_OVR_VAL__CAC_OVR_VAL_MASK                                                                      0xFFFFFFFFL
40689 //GC_CAC_WEIGHT_BCI_0
40690 #define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0__SHIFT                                                           0x0
40691 #define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1__SHIFT                                                           0x10
40692 #define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0_MASK                                                             0x0000FFFFL
40693 #define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1_MASK                                                             0xFFFF0000L
40694 //GC_CAC_WEIGHT_CB_0
40695 #define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0__SHIFT                                                             0x0
40696 #define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1__SHIFT                                                             0x10
40697 #define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0_MASK                                                               0x0000FFFFL
40698 #define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1_MASK                                                               0xFFFF0000L
40699 //GC_CAC_WEIGHT_CB_1
40700 #define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2__SHIFT                                                             0x0
40701 #define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3__SHIFT                                                             0x10
40702 #define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2_MASK                                                               0x0000FFFFL
40703 #define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3_MASK                                                               0xFFFF0000L
40704 //GC_CAC_WEIGHT_CBR_0
40705 #define GC_CAC_WEIGHT_CBR_0__WEIGHT_CBR_SIG0__SHIFT                                                           0x0
40706 #define GC_CAC_WEIGHT_CBR_0__WEIGHT_CBR_SIG1__SHIFT                                                           0x10
40707 #define GC_CAC_WEIGHT_CBR_0__WEIGHT_CBR_SIG0_MASK                                                             0x0000FFFFL
40708 #define GC_CAC_WEIGHT_CBR_0__WEIGHT_CBR_SIG1_MASK                                                             0xFFFF0000L
40709 //GC_CAC_WEIGHT_CBR_1
40710 #define GC_CAC_WEIGHT_CBR_1__WEIGHT_CBR_SIG2__SHIFT                                                           0x0
40711 #define GC_CAC_WEIGHT_CBR_1__WEIGHT_CBR_SIG3__SHIFT                                                           0x10
40712 #define GC_CAC_WEIGHT_CBR_1__WEIGHT_CBR_SIG2_MASK                                                             0x0000FFFFL
40713 #define GC_CAC_WEIGHT_CBR_1__WEIGHT_CBR_SIG3_MASK                                                             0xFFFF0000L
40714 //GC_CAC_WEIGHT_CP_0
40715 #define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0__SHIFT                                                             0x0
40716 #define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1__SHIFT                                                             0x10
40717 #define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0_MASK                                                               0x0000FFFFL
40718 #define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1_MASK                                                               0xFFFF0000L
40719 //GC_CAC_WEIGHT_CP_1
40720 #define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2__SHIFT                                                             0x0
40721 #define GC_CAC_WEIGHT_CP_1__UNUSED_0__SHIFT                                                                   0x10
40722 #define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2_MASK                                                               0x0000FFFFL
40723 #define GC_CAC_WEIGHT_CP_1__UNUSED_0_MASK                                                                     0xFFFF0000L
40724 //GC_CAC_WEIGHT_DB_0
40725 #define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0__SHIFT                                                             0x0
40726 #define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1__SHIFT                                                             0x10
40727 #define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0_MASK                                                               0x0000FFFFL
40728 #define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1_MASK                                                               0xFFFF0000L
40729 //GC_CAC_WEIGHT_DB_1
40730 #define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2__SHIFT                                                             0x0
40731 #define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3__SHIFT                                                             0x10
40732 #define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2_MASK                                                               0x0000FFFFL
40733 #define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3_MASK                                                               0xFFFF0000L
40734 //GC_CAC_WEIGHT_DBR_0
40735 #define GC_CAC_WEIGHT_DBR_0__WEIGHT_DBR_SIG0__SHIFT                                                           0x0
40736 #define GC_CAC_WEIGHT_DBR_0__WEIGHT_DBR_SIG1__SHIFT                                                           0x10
40737 #define GC_CAC_WEIGHT_DBR_0__WEIGHT_DBR_SIG0_MASK                                                             0x0000FFFFL
40738 #define GC_CAC_WEIGHT_DBR_0__WEIGHT_DBR_SIG1_MASK                                                             0xFFFF0000L
40739 //GC_CAC_WEIGHT_DBR_1
40740 #define GC_CAC_WEIGHT_DBR_1__WEIGHT_DBR_SIG2__SHIFT                                                           0x0
40741 #define GC_CAC_WEIGHT_DBR_1__WEIGHT_DBR_SIG3__SHIFT                                                           0x10
40742 #define GC_CAC_WEIGHT_DBR_1__WEIGHT_DBR_SIG2_MASK                                                             0x0000FFFFL
40743 #define GC_CAC_WEIGHT_DBR_1__WEIGHT_DBR_SIG3_MASK                                                             0xFFFF0000L
40744 //GC_CAC_WEIGHT_GDS_0
40745 #define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0__SHIFT                                                           0x0
40746 #define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1__SHIFT                                                           0x10
40747 #define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0_MASK                                                             0x0000FFFFL
40748 #define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1_MASK                                                             0xFFFF0000L
40749 //GC_CAC_WEIGHT_GDS_1
40750 #define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2__SHIFT                                                           0x0
40751 #define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3__SHIFT                                                           0x10
40752 #define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2_MASK                                                             0x0000FFFFL
40753 #define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3_MASK                                                             0xFFFF0000L
40754 //GC_CAC_WEIGHT_LDS_0
40755 #define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0__SHIFT                                                           0x0
40756 #define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1__SHIFT                                                           0x10
40757 #define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0_MASK                                                             0x0000FFFFL
40758 #define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1_MASK                                                             0xFFFF0000L
40759 //GC_CAC_WEIGHT_LDS_1
40760 #define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2__SHIFT                                                           0x0
40761 #define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3__SHIFT                                                           0x10
40762 #define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2_MASK                                                             0x0000FFFFL
40763 #define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3_MASK                                                             0xFFFF0000L
40764 //GC_CAC_WEIGHT_PA_0
40765 #define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0__SHIFT                                                             0x0
40766 #define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1__SHIFT                                                             0x10
40767 #define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0_MASK                                                               0x0000FFFFL
40768 #define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1_MASK                                                               0xFFFF0000L
40769 //GC_CAC_WEIGHT_PC_0
40770 #define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0__SHIFT                                                             0x0
40771 #define GC_CAC_WEIGHT_PC_0__UNUSED_0__SHIFT                                                                   0x10
40772 #define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0_MASK                                                               0x0000FFFFL
40773 #define GC_CAC_WEIGHT_PC_0__UNUSED_0_MASK                                                                     0xFFFF0000L
40774 //GC_CAC_WEIGHT_SC_0
40775 #define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0__SHIFT                                                             0x0
40776 #define GC_CAC_WEIGHT_SC_0__UNUSED_0__SHIFT                                                                   0x10
40777 #define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0_MASK                                                               0x0000FFFFL
40778 #define GC_CAC_WEIGHT_SC_0__UNUSED_0_MASK                                                                     0xFFFF0000L
40779 //GC_CAC_WEIGHT_SPI_0
40780 #define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0__SHIFT                                                           0x0
40781 #define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1__SHIFT                                                           0x10
40782 #define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0_MASK                                                             0x0000FFFFL
40783 #define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1_MASK                                                             0xFFFF0000L
40784 //GC_CAC_WEIGHT_SPI_1
40785 #define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2__SHIFT                                                           0x0
40786 #define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3__SHIFT                                                           0x10
40787 #define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2_MASK                                                             0x0000FFFFL
40788 #define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3_MASK                                                             0xFFFF0000L
40789 //GC_CAC_WEIGHT_SPI_2
40790 #define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4__SHIFT                                                           0x0
40791 #define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5__SHIFT                                                           0x10
40792 #define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4_MASK                                                             0x0000FFFFL
40793 #define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5_MASK                                                             0xFFFF0000L
40794 //GC_CAC_WEIGHT_SQ_0
40795 #define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0__SHIFT                                                             0x0
40796 #define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1__SHIFT                                                             0x10
40797 #define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0_MASK                                                               0x0000FFFFL
40798 #define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1_MASK                                                               0xFFFF0000L
40799 //GC_CAC_WEIGHT_SQ_1
40800 #define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2__SHIFT                                                             0x0
40801 #define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3__SHIFT                                                             0x10
40802 #define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2_MASK                                                               0x0000FFFFL
40803 #define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3_MASK                                                               0xFFFF0000L
40804 //GC_CAC_WEIGHT_SQ_2
40805 #define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4__SHIFT                                                             0x0
40806 #define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5__SHIFT                                                             0x10
40807 #define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4_MASK                                                               0x0000FFFFL
40808 #define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5_MASK                                                               0xFFFF0000L
40809 //GC_CAC_WEIGHT_SX_0
40810 #define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0__SHIFT                                                             0x0
40811 #define GC_CAC_WEIGHT_SX_0__UNUSED_0__SHIFT                                                                   0x10
40812 #define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0_MASK                                                               0x0000FFFFL
40813 #define GC_CAC_WEIGHT_SX_0__UNUSED_0_MASK                                                                     0xFFFF0000L
40814 //GC_CAC_WEIGHT_SXRB_0
40815 #define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0__SHIFT                                                         0x0
40816 #define GC_CAC_WEIGHT_SXRB_0__UNUSED_0__SHIFT                                                                 0x10
40817 #define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0_MASK                                                           0x0000FFFFL
40818 #define GC_CAC_WEIGHT_SXRB_0__UNUSED_0_MASK                                                                   0xFFFF0000L
40819 //GC_CAC_WEIGHT_TA_0
40820 #define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0__SHIFT                                                             0x0
40821 #define GC_CAC_WEIGHT_TA_0__UNUSED_0__SHIFT                                                                   0x10
40822 #define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0_MASK                                                               0x0000FFFFL
40823 #define GC_CAC_WEIGHT_TA_0__UNUSED_0_MASK                                                                     0xFFFF0000L
40824 //GC_CAC_WEIGHT_TCP_0
40825 #define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0__SHIFT                                                           0x0
40826 #define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1__SHIFT                                                           0x10
40827 #define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0_MASK                                                             0x0000FFFFL
40828 #define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1_MASK                                                             0xFFFF0000L
40829 //GC_CAC_WEIGHT_TCP_1
40830 #define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2__SHIFT                                                           0x0
40831 #define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3__SHIFT                                                           0x10
40832 #define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2_MASK                                                             0x0000FFFFL
40833 #define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3_MASK                                                             0xFFFF0000L
40834 //GC_CAC_WEIGHT_TCP_2
40835 #define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4__SHIFT                                                           0x0
40836 #define GC_CAC_WEIGHT_TCP_2__UNUSED_0__SHIFT                                                                  0x10
40837 #define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4_MASK                                                             0x0000FFFFL
40838 #define GC_CAC_WEIGHT_TCP_2__UNUSED_0_MASK                                                                    0xFFFF0000L
40839 //GC_CAC_WEIGHT_TD_0
40840 #define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0__SHIFT                                                             0x0
40841 #define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1__SHIFT                                                             0x10
40842 #define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0_MASK                                                               0x0000FFFFL
40843 #define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1_MASK                                                               0xFFFF0000L
40844 //GC_CAC_WEIGHT_TD_1
40845 #define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2__SHIFT                                                             0x0
40846 #define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3__SHIFT                                                             0x10
40847 #define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2_MASK                                                               0x0000FFFFL
40848 #define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3_MASK                                                               0xFFFF0000L
40849 //GC_CAC_WEIGHT_TD_2
40850 #define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4__SHIFT                                                             0x0
40851 #define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5__SHIFT                                                             0x10
40852 #define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4_MASK                                                               0x0000FFFFL
40853 #define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5_MASK                                                               0xFFFF0000L
40854 //GC_CAC_WEIGHT_TD_3
40855 #define GC_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG6__SHIFT                                                             0x0
40856 #define GC_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG7__SHIFT                                                             0x10
40857 #define GC_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG6_MASK                                                               0x0000FFFFL
40858 #define GC_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG7_MASK                                                               0xFFFF0000L
40859 //GC_CAC_WEIGHT_TD_4
40860 #define GC_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG8__SHIFT                                                             0x0
40861 #define GC_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG9__SHIFT                                                             0x10
40862 #define GC_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG8_MASK                                                               0x0000FFFFL
40863 #define GC_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG9_MASK                                                               0xFFFF0000L
40864 //GC_CAC_WEIGHT_RMI_0
40865 #define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0__SHIFT                                                           0x0
40866 #define GC_CAC_WEIGHT_RMI_0__UNUSED_0__SHIFT                                                                  0x10
40867 #define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0_MASK                                                             0x0000FFFFL
40868 #define GC_CAC_WEIGHT_RMI_0__UNUSED_0_MASK                                                                    0xFFFF0000L
40869 //GC_CAC_WEIGHT_EA_0
40870 #define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0__SHIFT                                                             0x0
40871 #define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1__SHIFT                                                             0x10
40872 #define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0_MASK                                                               0x0000FFFFL
40873 #define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1_MASK                                                               0xFFFF0000L
40874 //GC_CAC_WEIGHT_EA_1
40875 #define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2__SHIFT                                                             0x0
40876 #define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3__SHIFT                                                             0x10
40877 #define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2_MASK                                                               0x0000FFFFL
40878 #define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3_MASK                                                               0xFFFF0000L
40879 //GC_CAC_WEIGHT_EA_2
40880 #define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4__SHIFT                                                             0x0
40881 #define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5__SHIFT                                                             0x10
40882 #define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4_MASK                                                               0x0000FFFFL
40883 #define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5_MASK                                                               0xFFFF0000L
40884 //GC_CAC_WEIGHT_UTCL2_ATCL2_0
40885 #define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0__SHIFT                                           0x0
40886 #define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1__SHIFT                                           0x10
40887 #define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0_MASK                                             0x0000FFFFL
40888 #define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1_MASK                                             0xFFFF0000L
40889 //GC_CAC_WEIGHT_UTCL2_ATCL2_1
40890 #define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2__SHIFT                                           0x0
40891 #define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3__SHIFT                                           0x10
40892 #define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2_MASK                                             0x0000FFFFL
40893 #define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3_MASK                                             0xFFFF0000L
40894 //GC_CAC_WEIGHT_UTCL2_ATCL2_2
40895 #define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4__SHIFT                                           0x0
40896 #define GC_CAC_WEIGHT_UTCL2_ATCL2_2__UNUSED_0__SHIFT                                                          0x10
40897 #define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4_MASK                                             0x0000FFFFL
40898 #define GC_CAC_WEIGHT_UTCL2_ATCL2_2__UNUSED_0_MASK                                                            0xFFFF0000L
40899 //GC_CAC_WEIGHT_UTCL2_ROUTER_0
40900 #define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0__SHIFT                                         0x0
40901 #define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1__SHIFT                                         0x10
40902 #define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0_MASK                                           0x0000FFFFL
40903 #define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1_MASK                                           0xFFFF0000L
40904 //GC_CAC_WEIGHT_UTCL2_ROUTER_1
40905 #define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2__SHIFT                                         0x0
40906 #define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3__SHIFT                                         0x10
40907 #define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2_MASK                                           0x0000FFFFL
40908 #define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3_MASK                                           0xFFFF0000L
40909 //GC_CAC_WEIGHT_UTCL2_ROUTER_2
40910 #define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4__SHIFT                                         0x0
40911 #define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5__SHIFT                                         0x10
40912 #define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4_MASK                                           0x0000FFFFL
40913 #define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5_MASK                                           0xFFFF0000L
40914 //GC_CAC_WEIGHT_UTCL2_ROUTER_3
40915 #define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6__SHIFT                                         0x0
40916 #define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7__SHIFT                                         0x10
40917 #define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6_MASK                                           0x0000FFFFL
40918 #define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7_MASK                                           0xFFFF0000L
40919 //GC_CAC_WEIGHT_UTCL2_ROUTER_4
40920 #define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8__SHIFT                                         0x0
40921 #define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9__SHIFT                                         0x10
40922 #define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8_MASK                                           0x0000FFFFL
40923 #define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9_MASK                                           0xFFFF0000L
40924 //GC_CAC_WEIGHT_UTCL2_VML2_0
40925 #define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0__SHIFT                                             0x0
40926 #define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1__SHIFT                                             0x10
40927 #define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0_MASK                                               0x0000FFFFL
40928 #define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1_MASK                                               0xFFFF0000L
40929 //GC_CAC_WEIGHT_UTCL2_VML2_1
40930 #define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2__SHIFT                                             0x0
40931 #define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3__SHIFT                                             0x10
40932 #define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2_MASK                                               0x0000FFFFL
40933 #define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3_MASK                                               0xFFFF0000L
40934 //GC_CAC_WEIGHT_UTCL2_VML2_2
40935 #define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4__SHIFT                                             0x0
40936 #define GC_CAC_WEIGHT_UTCL2_VML2_2__UNUSED_0__SHIFT                                                           0x10
40937 #define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4_MASK                                               0x0000FFFFL
40938 #define GC_CAC_WEIGHT_UTCL2_VML2_2__UNUSED_0_MASK                                                             0xFFFF0000L
40939 //GC_CAC_WEIGHT_UTCL2_WALKER_0
40940 #define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0__SHIFT                                         0x0
40941 #define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1__SHIFT                                         0x10
40942 #define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0_MASK                                           0x0000FFFFL
40943 #define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1_MASK                                           0xFFFF0000L
40944 //GC_CAC_WEIGHT_UTCL2_WALKER_1
40945 #define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2__SHIFT                                         0x0
40946 #define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3__SHIFT                                         0x10
40947 #define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2_MASK                                           0x0000FFFFL
40948 #define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3_MASK                                           0xFFFF0000L
40949 //GC_CAC_WEIGHT_UTCL2_WALKER_2
40950 #define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4__SHIFT                                         0x0
40951 #define GC_CAC_WEIGHT_UTCL2_WALKER_2__UNUSED_0__SHIFT                                                         0x10
40952 #define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4_MASK                                           0x0000FFFFL
40953 #define GC_CAC_WEIGHT_UTCL2_WALKER_2__UNUSED_0_MASK                                                           0xFFFF0000L
40954 //GC_CAC_WEIGHT_CU_0
40955 #define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0__SHIFT                                                             0x0
40956 #define GC_CAC_WEIGHT_CU_0__UNUSED_0__SHIFT                                                                   0x10
40957 #define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0_MASK                                                               0x0000FFFFL
40958 #define GC_CAC_WEIGHT_CU_0__UNUSED_0_MASK                                                                     0xFFFF0000L
40959 //GC_CAC_WEIGHT_UTCL1_0
40960 #define GC_CAC_WEIGHT_UTCL1_0__WEIGHT_UTCL1_SIG0__SHIFT                                                       0x0
40961 #define GC_CAC_WEIGHT_UTCL1_0__WEIGHT_UTCL1_SIG0_MASK                                                         0x0000FFFFL
40962 //GC_CAC_WEIGHT_GE_0
40963 #define GC_CAC_WEIGHT_GE_0__WEIGHT_GE_SIG0__SHIFT                                                             0x0
40964 #define GC_CAC_WEIGHT_GE_0__WEIGHT_GE_SIG0_MASK                                                               0x0000FFFFL
40965 //GC_CAC_WEIGHT_PMM_0
40966 #define GC_CAC_WEIGHT_PMM_0__WEIGHT_PMM_SIG0__SHIFT                                                           0x0
40967 #define GC_CAC_WEIGHT_PMM_0__WEIGHT_PMM_SIG0_MASK                                                             0x0000FFFFL
40968 //GC_CAC_WEIGHT_GL2C_0
40969 #define GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG0__SHIFT                                                         0x0
40970 #define GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG1__SHIFT                                                         0x10
40971 #define GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG0_MASK                                                           0x0000FFFFL
40972 #define GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG1_MASK                                                           0xFFFF0000L
40973 //GC_CAC_WEIGHT_GL2C_1
40974 #define GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG2__SHIFT                                                         0x0
40975 #define GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG3__SHIFT                                                         0x10
40976 #define GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG2_MASK                                                           0x0000FFFFL
40977 #define GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG3_MASK                                                           0xFFFF0000L
40978 //GC_CAC_WEIGHT_GL2C_2
40979 #define GC_CAC_WEIGHT_GL2C_2__WEIGHT_GL2C_SIG4__SHIFT                                                         0x0
40980 #define GC_CAC_WEIGHT_GL2C_2__WEIGHT_GL2C_SIG4_MASK                                                           0x0000FFFFL
40981 //GC_CAC_WEIGHT_GUS_0
40982 #define GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG0__SHIFT                                                           0x0
40983 #define GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG1__SHIFT                                                           0x10
40984 #define GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG0_MASK                                                             0x0000FFFFL
40985 #define GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG1_MASK                                                             0xFFFF0000L
40986 //GC_CAC_WEIGHT_GUS_1
40987 #define GC_CAC_WEIGHT_GUS_1__WEIGHT_GUS_SIG2__SHIFT                                                           0x0
40988 #define GC_CAC_WEIGHT_GUS_1__WEIGHT_GUS_SIG2_MASK                                                             0x0000FFFFL
40989 //GC_CAC_WEIGHT_PH_0
40990 #define GC_CAC_WEIGHT_PH_0__WEIGHT_PH_SIG0__SHIFT                                                             0x0
40991 #define GC_CAC_WEIGHT_PH_0__WEIGHT_PH_SIG0_MASK                                                               0x0000FFFFL
40992 //GC_CAC_ACC_BCI0
40993 #define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0__SHIFT                                                              0x0
40994 #define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
40995 //GC_CAC_ACC_BCI1
40996 #define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0__SHIFT                                                              0x0
40997 #define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
40998 //GC_CAC_ACC_CB0
40999 #define GC_CAC_ACC_CB0__ACCUMULATOR_31_0__SHIFT                                                               0x0
41000 #define GC_CAC_ACC_CB0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
41001 //GC_CAC_ACC_CB1
41002 #define GC_CAC_ACC_CB1__ACCUMULATOR_31_0__SHIFT                                                               0x0
41003 #define GC_CAC_ACC_CB1__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
41004 //GC_CAC_ACC_CB2
41005 #define GC_CAC_ACC_CB2__ACCUMULATOR_31_0__SHIFT                                                               0x0
41006 #define GC_CAC_ACC_CB2__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
41007 //GC_CAC_ACC_CB3
41008 #define GC_CAC_ACC_CB3__ACCUMULATOR_31_0__SHIFT                                                               0x0
41009 #define GC_CAC_ACC_CB3__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
41010 //GC_CAC_ACC_CBR0
41011 #define GC_CAC_ACC_CBR0__ACCUMULATOR_31_0__SHIFT                                                              0x0
41012 #define GC_CAC_ACC_CBR0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
41013 //GC_CAC_ACC_CBR1
41014 #define GC_CAC_ACC_CBR1__ACCUMULATOR_31_0__SHIFT                                                              0x0
41015 #define GC_CAC_ACC_CBR1__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
41016 //GC_CAC_ACC_CBR2
41017 #define GC_CAC_ACC_CBR2__ACCUMULATOR_31_0__SHIFT                                                              0x0
41018 #define GC_CAC_ACC_CBR2__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
41019 //GC_CAC_ACC_CBR3
41020 #define GC_CAC_ACC_CBR3__ACCUMULATOR_31_0__SHIFT                                                              0x0
41021 #define GC_CAC_ACC_CBR3__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
41022 //GC_CAC_ACC_CP0
41023 #define GC_CAC_ACC_CP0__ACCUMULATOR_31_0__SHIFT                                                               0x0
41024 #define GC_CAC_ACC_CP0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
41025 //GC_CAC_ACC_CP1
41026 #define GC_CAC_ACC_CP1__ACCUMULATOR_31_0__SHIFT                                                               0x0
41027 #define GC_CAC_ACC_CP1__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
41028 //GC_CAC_ACC_CP2
41029 #define GC_CAC_ACC_CP2__ACCUMULATOR_31_0__SHIFT                                                               0x0
41030 #define GC_CAC_ACC_CP2__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
41031 //GC_CAC_ACC_DB0
41032 #define GC_CAC_ACC_DB0__ACCUMULATOR_31_0__SHIFT                                                               0x0
41033 #define GC_CAC_ACC_DB0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
41034 //GC_CAC_ACC_DB1
41035 #define GC_CAC_ACC_DB1__ACCUMULATOR_31_0__SHIFT                                                               0x0
41036 #define GC_CAC_ACC_DB1__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
41037 //GC_CAC_ACC_DB2
41038 #define GC_CAC_ACC_DB2__ACCUMULATOR_31_0__SHIFT                                                               0x0
41039 #define GC_CAC_ACC_DB2__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
41040 //GC_CAC_ACC_DB3
41041 #define GC_CAC_ACC_DB3__ACCUMULATOR_31_0__SHIFT                                                               0x0
41042 #define GC_CAC_ACC_DB3__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
41043 //GC_CAC_ACC_DBR0
41044 #define GC_CAC_ACC_DBR0__ACCUMULATOR_31_0__SHIFT                                                              0x0
41045 #define GC_CAC_ACC_DBR0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
41046 //GC_CAC_ACC_DBR1
41047 #define GC_CAC_ACC_DBR1__ACCUMULATOR_31_0__SHIFT                                                              0x0
41048 #define GC_CAC_ACC_DBR1__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
41049 //GC_CAC_ACC_DBR2
41050 #define GC_CAC_ACC_DBR2__ACCUMULATOR_31_0__SHIFT                                                              0x0
41051 #define GC_CAC_ACC_DBR2__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
41052 //GC_CAC_ACC_DBR3
41053 #define GC_CAC_ACC_DBR3__ACCUMULATOR_31_0__SHIFT                                                              0x0
41054 #define GC_CAC_ACC_DBR3__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
41055 //GC_CAC_ACC_GDS0
41056 #define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0__SHIFT                                                              0x0
41057 #define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
41058 //GC_CAC_ACC_GDS1
41059 #define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0__SHIFT                                                              0x0
41060 #define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
41061 //GC_CAC_ACC_GDS2
41062 #define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0__SHIFT                                                              0x0
41063 #define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
41064 //GC_CAC_ACC_GDS3
41065 #define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0__SHIFT                                                              0x0
41066 #define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
41067 //GC_CAC_ACC_LDS0
41068 #define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0__SHIFT                                                              0x0
41069 #define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
41070 //GC_CAC_ACC_LDS1
41071 #define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0__SHIFT                                                              0x0
41072 #define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
41073 //GC_CAC_ACC_LDS2
41074 #define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0__SHIFT                                                              0x0
41075 #define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
41076 //GC_CAC_ACC_LDS3
41077 #define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0__SHIFT                                                              0x0
41078 #define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
41079 //GC_CAC_ACC_PA0
41080 #define GC_CAC_ACC_PA0__ACCUMULATOR_31_0__SHIFT                                                               0x0
41081 #define GC_CAC_ACC_PA0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
41082 //GC_CAC_ACC_PA1
41083 #define GC_CAC_ACC_PA1__ACCUMULATOR_31_0__SHIFT                                                               0x0
41084 #define GC_CAC_ACC_PA1__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
41085 //GC_CAC_ACC_PC0
41086 #define GC_CAC_ACC_PC0__ACCUMULATOR_31_0__SHIFT                                                               0x0
41087 #define GC_CAC_ACC_PC0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
41088 //GC_CAC_ACC_SC0
41089 #define GC_CAC_ACC_SC0__ACCUMULATOR_31_0__SHIFT                                                               0x0
41090 #define GC_CAC_ACC_SC0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
41091 //GC_CAC_ACC_SPI0
41092 #define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0__SHIFT                                                              0x0
41093 #define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
41094 //GC_CAC_ACC_SPI1
41095 #define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0__SHIFT                                                              0x0
41096 #define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
41097 //GC_CAC_ACC_SPI2
41098 #define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0__SHIFT                                                              0x0
41099 #define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
41100 //GC_CAC_ACC_SPI3
41101 #define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0__SHIFT                                                              0x0
41102 #define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
41103 //GC_CAC_ACC_SPI4
41104 #define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0__SHIFT                                                              0x0
41105 #define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
41106 //GC_CAC_ACC_SPI5
41107 #define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0__SHIFT                                                              0x0
41108 #define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
41109 //GC_CAC_ACC_SQ0_LOWER
41110 #define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
41111 #define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
41112 //GC_CAC_ACC_SQ0_UPPER
41113 #define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
41114 #define GC_CAC_ACC_SQ0_UPPER__UNUSED_0__SHIFT                                                                 0x8
41115 #define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
41116 #define GC_CAC_ACC_SQ0_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
41117 //GC_CAC_ACC_SQ1_LOWER
41118 #define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
41119 #define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
41120 //GC_CAC_ACC_SQ1_UPPER
41121 #define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
41122 #define GC_CAC_ACC_SQ1_UPPER__UNUSED_0__SHIFT                                                                 0x8
41123 #define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
41124 #define GC_CAC_ACC_SQ1_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
41125 //GC_CAC_ACC_SQ2_LOWER
41126 #define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
41127 #define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
41128 //GC_CAC_ACC_SQ2_UPPER
41129 #define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
41130 #define GC_CAC_ACC_SQ2_UPPER__UNUSED_0__SHIFT                                                                 0x8
41131 #define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
41132 #define GC_CAC_ACC_SQ2_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
41133 //GC_CAC_ACC_SQ3_LOWER
41134 #define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
41135 #define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
41136 //GC_CAC_ACC_SQ3_UPPER
41137 #define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
41138 #define GC_CAC_ACC_SQ3_UPPER__UNUSED_0__SHIFT                                                                 0x8
41139 #define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
41140 #define GC_CAC_ACC_SQ3_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
41141 //GC_CAC_ACC_SQ4_LOWER
41142 #define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
41143 #define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
41144 //GC_CAC_ACC_SQ4_UPPER
41145 #define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
41146 #define GC_CAC_ACC_SQ4_UPPER__UNUSED_0__SHIFT                                                                 0x8
41147 #define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
41148 #define GC_CAC_ACC_SQ4_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
41149 //GC_CAC_ACC_SQ5_LOWER
41150 #define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
41151 #define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
41152 //GC_CAC_ACC_SQ5_UPPER
41153 #define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
41154 #define GC_CAC_ACC_SQ5_UPPER__UNUSED_0__SHIFT                                                                 0x8
41155 #define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
41156 #define GC_CAC_ACC_SQ5_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
41157 //GC_CAC_ACC_SQ6_LOWER
41158 #define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
41159 #define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
41160 //GC_CAC_ACC_SQ6_UPPER
41161 #define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
41162 #define GC_CAC_ACC_SQ6_UPPER__UNUSED_0__SHIFT                                                                 0x8
41163 #define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
41164 #define GC_CAC_ACC_SQ6_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
41165 //GC_CAC_ACC_SQ7_LOWER
41166 #define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
41167 #define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
41168 //GC_CAC_ACC_SQ7_UPPER
41169 #define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
41170 #define GC_CAC_ACC_SQ7_UPPER__UNUSED_0__SHIFT                                                                 0x8
41171 #define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
41172 #define GC_CAC_ACC_SQ7_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
41173 //GC_CAC_ACC_SQ8_LOWER
41174 #define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
41175 #define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
41176 //GC_CAC_ACC_SQ8_UPPER
41177 #define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
41178 #define GC_CAC_ACC_SQ8_UPPER__UNUSED_0__SHIFT                                                                 0x8
41179 #define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
41180 #define GC_CAC_ACC_SQ8_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
41181 //GC_CAC_ACC_SX0
41182 #define GC_CAC_ACC_SX0__ACCUMULATOR_31_0__SHIFT                                                               0x0
41183 #define GC_CAC_ACC_SX0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
41184 //GC_CAC_ACC_SXRB0
41185 #define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0__SHIFT                                                             0x0
41186 #define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0_MASK                                                               0xFFFFFFFFL
41187 //GC_CAC_ACC_TA0
41188 #define GC_CAC_ACC_TA0__ACCUMULATOR_31_0__SHIFT                                                               0x0
41189 #define GC_CAC_ACC_TA0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
41190 //GC_CAC_ACC_TCP0
41191 #define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0__SHIFT                                                              0x0
41192 #define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
41193 //GC_CAC_ACC_TCP1
41194 #define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0__SHIFT                                                              0x0
41195 #define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
41196 //GC_CAC_ACC_TCP2
41197 #define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0__SHIFT                                                              0x0
41198 #define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
41199 //GC_CAC_ACC_TCP3
41200 #define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0__SHIFT                                                              0x0
41201 #define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
41202 //GC_CAC_ACC_TCP4
41203 #define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0__SHIFT                                                              0x0
41204 #define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
41205 //GC_CAC_ACC_TD0
41206 #define GC_CAC_ACC_TD0__ACCUMULATOR_31_0__SHIFT                                                               0x0
41207 #define GC_CAC_ACC_TD0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
41208 //GC_CAC_ACC_TD1
41209 #define GC_CAC_ACC_TD1__ACCUMULATOR_31_0__SHIFT                                                               0x0
41210 #define GC_CAC_ACC_TD1__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
41211 //GC_CAC_ACC_TD2
41212 #define GC_CAC_ACC_TD2__ACCUMULATOR_31_0__SHIFT                                                               0x0
41213 #define GC_CAC_ACC_TD2__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
41214 //GC_CAC_ACC_TD3
41215 #define GC_CAC_ACC_TD3__ACCUMULATOR_31_0__SHIFT                                                               0x0
41216 #define GC_CAC_ACC_TD3__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
41217 //GC_CAC_ACC_TD4
41218 #define GC_CAC_ACC_TD4__ACCUMULATOR_31_0__SHIFT                                                               0x0
41219 #define GC_CAC_ACC_TD4__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
41220 //GC_CAC_ACC_TD5
41221 #define GC_CAC_ACC_TD5__ACCUMULATOR_31_0__SHIFT                                                               0x0
41222 #define GC_CAC_ACC_TD5__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
41223 //GC_CAC_ACC_TD6
41224 #define GC_CAC_ACC_TD6__ACCUMULATOR_31_0__SHIFT                                                               0x0
41225 #define GC_CAC_ACC_TD6__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
41226 //GC_CAC_ACC_TD7
41227 #define GC_CAC_ACC_TD7__ACCUMULATOR_31_0__SHIFT                                                               0x0
41228 #define GC_CAC_ACC_TD7__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
41229 //GC_CAC_ACC_TD8
41230 #define GC_CAC_ACC_TD8__ACCUMULATOR_31_0__SHIFT                                                               0x0
41231 #define GC_CAC_ACC_TD8__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
41232 //GC_CAC_ACC_TD9
41233 #define GC_CAC_ACC_TD9__ACCUMULATOR_31_0__SHIFT                                                               0x0
41234 #define GC_CAC_ACC_TD9__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
41235 //GC_CAC_ACC_RMI0
41236 #define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0__SHIFT                                                              0x0
41237 #define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
41238 //GC_CAC_ACC_EA0
41239 #define GC_CAC_ACC_EA0__ACCUMULATOR_31_0__SHIFT                                                               0x0
41240 #define GC_CAC_ACC_EA0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
41241 //GC_CAC_ACC_EA1
41242 #define GC_CAC_ACC_EA1__ACCUMULATOR_31_0__SHIFT                                                               0x0
41243 #define GC_CAC_ACC_EA1__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
41244 //GC_CAC_ACC_EA2
41245 #define GC_CAC_ACC_EA2__ACCUMULATOR_31_0__SHIFT                                                               0x0
41246 #define GC_CAC_ACC_EA2__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
41247 //GC_CAC_ACC_EA3
41248 #define GC_CAC_ACC_EA3__ACCUMULATOR_31_0__SHIFT                                                               0x0
41249 #define GC_CAC_ACC_EA3__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
41250 //GC_CAC_ACC_EA4
41251 #define GC_CAC_ACC_EA4__ACCUMULATOR_31_0__SHIFT                                                               0x0
41252 #define GC_CAC_ACC_EA4__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
41253 //GC_CAC_ACC_EA5
41254 #define GC_CAC_ACC_EA5__ACCUMULATOR_31_0__SHIFT                                                               0x0
41255 #define GC_CAC_ACC_EA5__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
41256 //GC_CAC_ACC_UTCL2_ATCL20
41257 #define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0__SHIFT                                                      0x0
41258 #define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0_MASK                                                        0xFFFFFFFFL
41259 //GC_CAC_ACC_UTCL2_ATCL21
41260 #define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0__SHIFT                                                      0x0
41261 #define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0_MASK                                                        0xFFFFFFFFL
41262 //GC_CAC_ACC_UTCL2_ATCL22
41263 #define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0__SHIFT                                                      0x0
41264 #define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0_MASK                                                        0xFFFFFFFFL
41265 //GC_CAC_ACC_UTCL2_ATCL23
41266 #define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0__SHIFT                                                      0x0
41267 #define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0_MASK                                                        0xFFFFFFFFL
41268 //GC_CAC_ACC_UTCL2_ATCL24
41269 #define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0__SHIFT                                                      0x0
41270 #define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0_MASK                                                        0xFFFFFFFFL
41271 //GC_CAC_ACC_UTCL2_ROUTER0
41272 #define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0__SHIFT                                                     0x0
41273 #define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
41274 //GC_CAC_ACC_UTCL2_ROUTER1
41275 #define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0__SHIFT                                                     0x0
41276 #define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
41277 //GC_CAC_ACC_UTCL2_ROUTER2
41278 #define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0__SHIFT                                                     0x0
41279 #define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
41280 //GC_CAC_ACC_UTCL2_ROUTER3
41281 #define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0__SHIFT                                                     0x0
41282 #define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
41283 //GC_CAC_ACC_UTCL2_ROUTER4
41284 #define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0__SHIFT                                                     0x0
41285 #define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
41286 //GC_CAC_ACC_UTCL2_ROUTER5
41287 #define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0__SHIFT                                                     0x0
41288 #define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
41289 //GC_CAC_ACC_UTCL2_ROUTER6
41290 #define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0__SHIFT                                                     0x0
41291 #define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
41292 //GC_CAC_ACC_UTCL2_ROUTER7
41293 #define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0__SHIFT                                                     0x0
41294 #define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
41295 //GC_CAC_ACC_UTCL2_ROUTER8
41296 #define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0__SHIFT                                                     0x0
41297 #define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
41298 //GC_CAC_ACC_UTCL2_ROUTER9
41299 #define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0__SHIFT                                                     0x0
41300 #define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
41301 //GC_CAC_ACC_UTCL2_VML20
41302 #define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0__SHIFT                                                       0x0
41303 #define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0_MASK                                                         0xFFFFFFFFL
41304 //GC_CAC_ACC_UTCL2_VML21
41305 #define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0__SHIFT                                                       0x0
41306 #define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0_MASK                                                         0xFFFFFFFFL
41307 //GC_CAC_ACC_UTCL2_VML22
41308 #define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0__SHIFT                                                       0x0
41309 #define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0_MASK                                                         0xFFFFFFFFL
41310 //GC_CAC_ACC_UTCL2_VML23
41311 #define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0__SHIFT                                                       0x0
41312 #define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0_MASK                                                         0xFFFFFFFFL
41313 //GC_CAC_ACC_UTCL2_VML24
41314 #define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0__SHIFT                                                       0x0
41315 #define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0_MASK                                                         0xFFFFFFFFL
41316 //GC_CAC_ACC_UTCL2_WALKER0
41317 #define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0__SHIFT                                                     0x0
41318 #define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
41319 //GC_CAC_ACC_UTCL2_WALKER1
41320 #define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0__SHIFT                                                     0x0
41321 #define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
41322 //GC_CAC_ACC_UTCL2_WALKER2
41323 #define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0__SHIFT                                                     0x0
41324 #define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
41325 //GC_CAC_ACC_UTCL2_WALKER3
41326 #define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0__SHIFT                                                     0x0
41327 #define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
41328 //GC_CAC_ACC_UTCL2_WALKER4
41329 #define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0__SHIFT                                                     0x0
41330 #define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
41331 //GC_CAC_ACC_CU0
41332 #define GC_CAC_ACC_CU0__ACCUMULATOR_31_0__SHIFT                                                               0x0
41333 #define GC_CAC_ACC_CU0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
41334 //GC_CAC_ACC_UTCL10
41335 #define GC_CAC_ACC_UTCL10__ACCUMULATOR_31_0__SHIFT                                                            0x0
41336 #define GC_CAC_ACC_UTCL10__ACCUMULATOR_31_0_MASK                                                              0xFFFFFFFFL
41337 //GC_CAC_ACC_CH0
41338 #define GC_CAC_ACC_CH0__ACCUMULATOR_31_0__SHIFT                                                               0x0
41339 #define GC_CAC_ACC_CH0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
41340 //GC_CAC_ACC_GE0
41341 #define GC_CAC_ACC_GE0__ACCUMULATOR_31_0__SHIFT                                                               0x0
41342 #define GC_CAC_ACC_GE0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
41343 //GC_CAC_ACC_PMM0
41344 #define GC_CAC_ACC_PMM0__ACCUMULATOR_31_0__SHIFT                                                              0x0
41345 #define GC_CAC_ACC_PMM0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
41346 //GC_CAC_ACC_GL2C0
41347 #define GC_CAC_ACC_GL2C0__ACCUMULATOR_31_0__SHIFT                                                             0x0
41348 #define GC_CAC_ACC_GL2C0__ACCUMULATOR_31_0_MASK                                                               0xFFFFFFFFL
41349 //GC_CAC_ACC_GL2C1
41350 #define GC_CAC_ACC_GL2C1__ACCUMULATOR_31_0__SHIFT                                                             0x0
41351 #define GC_CAC_ACC_GL2C1__ACCUMULATOR_31_0_MASK                                                               0xFFFFFFFFL
41352 //GC_CAC_ACC_GL2C2
41353 #define GC_CAC_ACC_GL2C2__ACCUMULATOR_31_0__SHIFT                                                             0x0
41354 #define GC_CAC_ACC_GL2C2__ACCUMULATOR_31_0_MASK                                                               0xFFFFFFFFL
41355 //GC_CAC_ACC_GL2C3
41356 #define GC_CAC_ACC_GL2C3__ACCUMULATOR_31_0__SHIFT                                                             0x0
41357 #define GC_CAC_ACC_GL2C3__ACCUMULATOR_31_0_MASK                                                               0xFFFFFFFFL
41358 //GC_CAC_ACC_GL2C4
41359 #define GC_CAC_ACC_GL2C4__ACCUMULATOR_31_0__SHIFT                                                             0x0
41360 #define GC_CAC_ACC_GL2C4__ACCUMULATOR_31_0_MASK                                                               0xFFFFFFFFL
41361 //GC_CAC_ACC_GUS0
41362 #define GC_CAC_ACC_GUS0__ACCUMULATOR_31_0__SHIFT                                                              0x0
41363 #define GC_CAC_ACC_GUS0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
41364 //GC_CAC_ACC_GUS1
41365 #define GC_CAC_ACC_GUS1__ACCUMULATOR_31_0__SHIFT                                                              0x0
41366 #define GC_CAC_ACC_GUS1__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
41367 //GC_CAC_ACC_GUS2
41368 #define GC_CAC_ACC_GUS2__ACCUMULATOR_31_0__SHIFT                                                              0x0
41369 #define GC_CAC_ACC_GUS2__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
41370 //GC_CAC_ACC_PH0
41371 #define GC_CAC_ACC_PH0__ACCUMULATOR_31_0__SHIFT                                                               0x0
41372 #define GC_CAC_ACC_PH0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
41373 //GC_CAC_OVRD_BCI
41374 #define GC_CAC_OVRD_BCI__OVRRD_SELECT__SHIFT                                                                  0x0
41375 #define GC_CAC_OVRD_BCI__OVRRD_VALUE__SHIFT                                                                   0x2
41376 #define GC_CAC_OVRD_BCI__OVRRD_SELECT_MASK                                                                    0x00000003L
41377 #define GC_CAC_OVRD_BCI__OVRRD_VALUE_MASK                                                                     0x0000000CL
41378 //GC_CAC_OVRD_CB
41379 #define GC_CAC_OVRD_CB__OVRRD_SELECT__SHIFT                                                                   0x0
41380 #define GC_CAC_OVRD_CB__OVRRD_VALUE__SHIFT                                                                    0x4
41381 #define GC_CAC_OVRD_CB__OVRRD_SELECT_MASK                                                                     0x0000000FL
41382 #define GC_CAC_OVRD_CB__OVRRD_VALUE_MASK                                                                      0x000000F0L
41383 //GC_CAC_OVRD_CBR
41384 #define GC_CAC_OVRD_CBR__OVRRD_SELECT__SHIFT                                                                  0x0
41385 #define GC_CAC_OVRD_CBR__OVRRD_VALUE__SHIFT                                                                   0x4
41386 #define GC_CAC_OVRD_CBR__OVRRD_SELECT_MASK                                                                    0x0000000FL
41387 #define GC_CAC_OVRD_CBR__OVRRD_VALUE_MASK                                                                     0x000000F0L
41388 //GC_CAC_OVRD_CP
41389 #define GC_CAC_OVRD_CP__OVRRD_SELECT__SHIFT                                                                   0x0
41390 #define GC_CAC_OVRD_CP__OVRRD_VALUE__SHIFT                                                                    0x3
41391 #define GC_CAC_OVRD_CP__OVRRD_SELECT_MASK                                                                     0x00000007L
41392 #define GC_CAC_OVRD_CP__OVRRD_VALUE_MASK                                                                      0x00000038L
41393 //GC_CAC_OVRD_DB
41394 #define GC_CAC_OVRD_DB__OVRRD_SELECT__SHIFT                                                                   0x0
41395 #define GC_CAC_OVRD_DB__OVRRD_VALUE__SHIFT                                                                    0x4
41396 #define GC_CAC_OVRD_DB__OVRRD_SELECT_MASK                                                                     0x0000000FL
41397 #define GC_CAC_OVRD_DB__OVRRD_VALUE_MASK                                                                      0x000000F0L
41398 //GC_CAC_OVRD_DBR
41399 #define GC_CAC_OVRD_DBR__OVRRD_SELECT__SHIFT                                                                  0x0
41400 #define GC_CAC_OVRD_DBR__OVRRD_VALUE__SHIFT                                                                   0x4
41401 #define GC_CAC_OVRD_DBR__OVRRD_SELECT_MASK                                                                    0x0000000FL
41402 #define GC_CAC_OVRD_DBR__OVRRD_VALUE_MASK                                                                     0x000000F0L
41403 //GC_CAC_OVRD_GDS
41404 #define GC_CAC_OVRD_GDS__OVRRD_SELECT__SHIFT                                                                  0x0
41405 #define GC_CAC_OVRD_GDS__OVRRD_VALUE__SHIFT                                                                   0x4
41406 #define GC_CAC_OVRD_GDS__OVRRD_SELECT_MASK                                                                    0x0000000FL
41407 #define GC_CAC_OVRD_GDS__OVRRD_VALUE_MASK                                                                     0x000000F0L
41408 //GC_CAC_OVRD_LDS
41409 #define GC_CAC_OVRD_LDS__OVRRD_SELECT__SHIFT                                                                  0x0
41410 #define GC_CAC_OVRD_LDS__OVRRD_VALUE__SHIFT                                                                   0x4
41411 #define GC_CAC_OVRD_LDS__OVRRD_SELECT_MASK                                                                    0x0000000FL
41412 #define GC_CAC_OVRD_LDS__OVRRD_VALUE_MASK                                                                     0x000000F0L
41413 //GC_CAC_OVRD_PA
41414 #define GC_CAC_OVRD_PA__OVRRD_SELECT__SHIFT                                                                   0x0
41415 #define GC_CAC_OVRD_PA__OVRRD_VALUE__SHIFT                                                                    0x2
41416 #define GC_CAC_OVRD_PA__OVRRD_SELECT_MASK                                                                     0x00000003L
41417 #define GC_CAC_OVRD_PA__OVRRD_VALUE_MASK                                                                      0x0000000CL
41418 //GC_CAC_OVRD_PC
41419 #define GC_CAC_OVRD_PC__OVRRD_SELECT__SHIFT                                                                   0x0
41420 #define GC_CAC_OVRD_PC__OVRRD_VALUE__SHIFT                                                                    0x1
41421 #define GC_CAC_OVRD_PC__OVRRD_SELECT_MASK                                                                     0x00000001L
41422 #define GC_CAC_OVRD_PC__OVRRD_VALUE_MASK                                                                      0x00000002L
41423 //GC_CAC_OVRD_SC
41424 #define GC_CAC_OVRD_SC__OVRRD_SELECT__SHIFT                                                                   0x0
41425 #define GC_CAC_OVRD_SC__OVRRD_VALUE__SHIFT                                                                    0x1
41426 #define GC_CAC_OVRD_SC__OVRRD_SELECT_MASK                                                                     0x00000001L
41427 #define GC_CAC_OVRD_SC__OVRRD_VALUE_MASK                                                                      0x00000002L
41428 //GC_CAC_OVRD_SPI
41429 #define GC_CAC_OVRD_SPI__OVRRD_SELECT__SHIFT                                                                  0x0
41430 #define GC_CAC_OVRD_SPI__OVRRD_VALUE__SHIFT                                                                   0x6
41431 #define GC_CAC_OVRD_SPI__OVRRD_SELECT_MASK                                                                    0x0000003FL
41432 #define GC_CAC_OVRD_SPI__OVRRD_VALUE_MASK                                                                     0x00000FC0L
41433 //GC_CAC_OVRD_CU
41434 #define GC_CAC_OVRD_CU__OVRRD_SELECT__SHIFT                                                                   0x0
41435 #define GC_CAC_OVRD_CU__OVRRD_VALUE__SHIFT                                                                    0x1
41436 #define GC_CAC_OVRD_CU__OVRRD_SELECT_MASK                                                                     0x00000001L
41437 #define GC_CAC_OVRD_CU__OVRRD_VALUE_MASK                                                                      0x00000002L
41438 //GC_CAC_OVRD_SQ
41439 #define GC_CAC_OVRD_SQ__OVRRD_SELECT__SHIFT                                                                   0x0
41440 #define GC_CAC_OVRD_SQ__OVRRD_VALUE__SHIFT                                                                    0x6
41441 #define GC_CAC_OVRD_SQ__OVRRD_SELECT_MASK                                                                     0x0000003FL
41442 #define GC_CAC_OVRD_SQ__OVRRD_VALUE_MASK                                                                      0x00000FC0L
41443 //GC_CAC_OVRD_SX
41444 #define GC_CAC_OVRD_SX__OVRRD_SELECT__SHIFT                                                                   0x0
41445 #define GC_CAC_OVRD_SX__OVRRD_VALUE__SHIFT                                                                    0x1
41446 #define GC_CAC_OVRD_SX__OVRRD_SELECT_MASK                                                                     0x00000001L
41447 #define GC_CAC_OVRD_SX__OVRRD_VALUE_MASK                                                                      0x00000002L
41448 //GC_CAC_OVRD_SXRB
41449 #define GC_CAC_OVRD_SXRB__OVRRD_SELECT__SHIFT                                                                 0x0
41450 #define GC_CAC_OVRD_SXRB__OVRRD_VALUE__SHIFT                                                                  0x1
41451 #define GC_CAC_OVRD_SXRB__OVRRD_SELECT_MASK                                                                   0x00000001L
41452 #define GC_CAC_OVRD_SXRB__OVRRD_VALUE_MASK                                                                    0x00000002L
41453 //GC_CAC_OVRD_TA
41454 #define GC_CAC_OVRD_TA__OVRRD_SELECT__SHIFT                                                                   0x0
41455 #define GC_CAC_OVRD_TA__OVRRD_VALUE__SHIFT                                                                    0x1
41456 #define GC_CAC_OVRD_TA__OVRRD_SELECT_MASK                                                                     0x00000001L
41457 #define GC_CAC_OVRD_TA__OVRRD_VALUE_MASK                                                                      0x00000002L
41458 //GC_CAC_OVRD_TCP
41459 #define GC_CAC_OVRD_TCP__OVRRD_SELECT__SHIFT                                                                  0x0
41460 #define GC_CAC_OVRD_TCP__OVRRD_VALUE__SHIFT                                                                   0x5
41461 #define GC_CAC_OVRD_TCP__OVRRD_SELECT_MASK                                                                    0x0000001FL
41462 #define GC_CAC_OVRD_TCP__OVRRD_VALUE_MASK                                                                     0x000003E0L
41463 //GC_CAC_OVRD_TD
41464 #define GC_CAC_OVRD_TD__OVRRD_SELECT__SHIFT                                                                   0x0
41465 #define GC_CAC_OVRD_TD__OVRRD_VALUE__SHIFT                                                                    0xa
41466 #define GC_CAC_OVRD_TD__OVRRD_SELECT_MASK                                                                     0x000003FFL
41467 #define GC_CAC_OVRD_TD__OVRRD_VALUE_MASK                                                                      0x000FFC00L
41468 //GC_CAC_OVRD_RMI
41469 #define GC_CAC_OVRD_RMI__OVRRD_SELECT__SHIFT                                                                  0x0
41470 #define GC_CAC_OVRD_RMI__OVRRD_VALUE__SHIFT                                                                   0x1
41471 #define GC_CAC_OVRD_RMI__OVRRD_SELECT_MASK                                                                    0x00000001L
41472 #define GC_CAC_OVRD_RMI__OVRRD_VALUE_MASK                                                                     0x00000002L
41473 //GC_CAC_OVRD_EA
41474 #define GC_CAC_OVRD_EA__OVRRD_SELECT__SHIFT                                                                   0x0
41475 #define GC_CAC_OVRD_EA__OVRRD_VALUE__SHIFT                                                                    0x6
41476 #define GC_CAC_OVRD_EA__OVRRD_SELECT_MASK                                                                     0x0000003FL
41477 #define GC_CAC_OVRD_EA__OVRRD_VALUE_MASK                                                                      0x00000FC0L
41478 //GC_CAC_OVRD_UTCL2_ATCL2
41479 #define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT__SHIFT                                                          0x0
41480 #define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE__SHIFT                                                           0x5
41481 #define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT_MASK                                                            0x0000001FL
41482 #define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE_MASK                                                             0x000003E0L
41483 //GC_CAC_OVRD_UTCL2_ROUTER
41484 #define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT__SHIFT                                                         0x0
41485 #define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE__SHIFT                                                          0xa
41486 #define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT_MASK                                                           0x000003FFL
41487 #define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE_MASK                                                            0x000FFC00L
41488 //GC_CAC_OVRD_UTCL2_VML2
41489 #define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT__SHIFT                                                           0x0
41490 #define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE__SHIFT                                                            0x5
41491 #define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT_MASK                                                             0x0000001FL
41492 #define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE_MASK                                                              0x000003E0L
41493 //GC_CAC_OVRD_UTCL2_WALKER
41494 #define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT__SHIFT                                                         0x0
41495 #define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE__SHIFT                                                          0x5
41496 #define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT_MASK                                                           0x0000001FL
41497 #define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE_MASK                                                            0x000003E0L
41498 //GC_CAC_OVRD_UTCL1
41499 #define GC_CAC_OVRD_UTCL1__OVRRD_SELECT__SHIFT                                                                0x0
41500 #define GC_CAC_OVRD_UTCL1__OVRRD_VALUE__SHIFT                                                                 0x1
41501 #define GC_CAC_OVRD_UTCL1__OVRRD_SELECT_MASK                                                                  0x00000001L
41502 #define GC_CAC_OVRD_UTCL1__OVRRD_VALUE_MASK                                                                   0x00000002L
41503 //GC_CAC_OVRD_GE
41504 #define GC_CAC_OVRD_GE__OVRRD_SELECT__SHIFT                                                                   0x0
41505 #define GC_CAC_OVRD_GE__OVRRD_VALUE__SHIFT                                                                    0x1
41506 #define GC_CAC_OVRD_GE__OVRRD_SELECT_MASK                                                                     0x00000001L
41507 #define GC_CAC_OVRD_GE__OVRRD_VALUE_MASK                                                                      0x00000002L
41508 //GC_CAC_OVRD_PMM
41509 #define GC_CAC_OVRD_PMM__OVRRD_SELECT__SHIFT                                                                  0x0
41510 #define GC_CAC_OVRD_PMM__OVRRD_VALUE__SHIFT                                                                   0x1
41511 #define GC_CAC_OVRD_PMM__OVRRD_SELECT_MASK                                                                    0x00000001L
41512 #define GC_CAC_OVRD_PMM__OVRRD_VALUE_MASK                                                                     0x00000002L
41513 //GC_CAC_OVRD_GL2C
41514 #define GC_CAC_OVRD_GL2C__OVRRD_SELECT__SHIFT                                                                 0x0
41515 #define GC_CAC_OVRD_GL2C__OVRRD_VALUE__SHIFT                                                                  0x5
41516 #define GC_CAC_OVRD_GL2C__OVRRD_SELECT_MASK                                                                   0x0000001FL
41517 #define GC_CAC_OVRD_GL2C__OVRRD_VALUE_MASK                                                                    0x000003E0L
41518 //GC_CAC_OVRD_GUS
41519 #define GC_CAC_OVRD_GUS__OVRRD_SELECT__SHIFT                                                                  0x0
41520 #define GC_CAC_OVRD_GUS__OVRRD_VALUE__SHIFT                                                                   0x3
41521 #define GC_CAC_OVRD_GUS__OVRRD_SELECT_MASK                                                                    0x00000007L
41522 #define GC_CAC_OVRD_GUS__OVRRD_VALUE_MASK                                                                     0x00000038L
41523 //GC_CAC_OVRD_PH
41524 #define GC_CAC_OVRD_PH__OVRRD_SELECT__SHIFT                                                                   0x0
41525 #define GC_CAC_OVRD_PH__OVRRD_VALUE__SHIFT                                                                    0x1
41526 #define GC_CAC_OVRD_PH__OVRRD_SELECT_MASK                                                                     0x00000001L
41527 #define GC_CAC_OVRD_PH__OVRRD_VALUE_MASK                                                                      0x00000002L
41528 //RELEASE_TO_STALL_LUT_1_8
41529 #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1__SHIFT                                                      0x0
41530 #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2__SHIFT                                                      0x4
41531 #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3__SHIFT                                                      0x8
41532 #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4__SHIFT                                                      0xc
41533 #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5__SHIFT                                                      0x10
41534 #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6__SHIFT                                                      0x14
41535 #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7__SHIFT                                                      0x18
41536 #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8__SHIFT                                                      0x1c
41537 #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1_MASK                                                        0x00000007L
41538 #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2_MASK                                                        0x00000070L
41539 #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3_MASK                                                        0x00000700L
41540 #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4_MASK                                                        0x00007000L
41541 #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5_MASK                                                        0x00070000L
41542 #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6_MASK                                                        0x00700000L
41543 #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7_MASK                                                        0x07000000L
41544 #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8_MASK                                                        0x70000000L
41545 //RELEASE_TO_STALL_LUT_9_16
41546 #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9__SHIFT                                                     0x0
41547 #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10__SHIFT                                                    0x4
41548 #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11__SHIFT                                                    0x8
41549 #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12__SHIFT                                                    0xc
41550 #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13__SHIFT                                                    0x10
41551 #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14__SHIFT                                                    0x14
41552 #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15__SHIFT                                                    0x18
41553 #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16__SHIFT                                                    0x1c
41554 #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9_MASK                                                       0x00000007L
41555 #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10_MASK                                                      0x00000070L
41556 #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11_MASK                                                      0x00000700L
41557 #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12_MASK                                                      0x00007000L
41558 #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13_MASK                                                      0x00070000L
41559 #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14_MASK                                                      0x00700000L
41560 #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15_MASK                                                      0x07000000L
41561 #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16_MASK                                                      0x70000000L
41562 //RELEASE_TO_STALL_LUT_17_20
41563 #define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17__SHIFT                                                   0x0
41564 #define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18__SHIFT                                                   0x4
41565 #define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19__SHIFT                                                   0x8
41566 #define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20__SHIFT                                                   0xc
41567 #define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17_MASK                                                     0x00000007L
41568 #define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18_MASK                                                     0x00000070L
41569 #define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19_MASK                                                     0x00000700L
41570 #define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20_MASK                                                     0x00007000L
41571 //STALL_TO_RELEASE_LUT_1_4
41572 #define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1__SHIFT                                                      0x0
41573 #define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2__SHIFT                                                      0x8
41574 #define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3__SHIFT                                                      0x10
41575 #define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4__SHIFT                                                      0x18
41576 #define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1_MASK                                                        0x0000001FL
41577 #define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2_MASK                                                        0x00001F00L
41578 #define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3_MASK                                                        0x001F0000L
41579 #define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4_MASK                                                        0x1F000000L
41580 //STALL_TO_RELEASE_LUT_5_7
41581 #define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5__SHIFT                                                      0x0
41582 #define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6__SHIFT                                                      0x8
41583 #define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7__SHIFT                                                      0x10
41584 #define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5_MASK                                                        0x0000001FL
41585 #define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6_MASK                                                        0x00001F00L
41586 #define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7_MASK                                                        0x001F0000L
41587 //STALL_TO_PWRBRK_LUT_1_4
41588 #define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_1__SHIFT                                                       0x0
41589 #define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_2__SHIFT                                                       0x8
41590 #define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_3__SHIFT                                                       0x10
41591 #define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_4__SHIFT                                                       0x18
41592 #define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_1_MASK                                                         0x00000007L
41593 #define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_2_MASK                                                         0x00000700L
41594 #define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_3_MASK                                                         0x00070000L
41595 #define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_4_MASK                                                         0x07000000L
41596 //STALL_TO_PWRBRK_LUT_5_7
41597 #define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_5__SHIFT                                                       0x0
41598 #define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_6__SHIFT                                                       0x8
41599 #define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_7__SHIFT                                                       0x10
41600 #define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_5_MASK                                                         0x00000007L
41601 #define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_6_MASK                                                         0x00000700L
41602 #define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_7_MASK                                                         0x00070000L
41603 //PWRBRK_STALL_TO_RELEASE_LUT_1_4
41604 #define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1__SHIFT                                               0x0
41605 #define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2__SHIFT                                               0x8
41606 #define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3__SHIFT                                               0x10
41607 #define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4__SHIFT                                               0x18
41608 #define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1_MASK                                                 0x0000001FL
41609 #define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2_MASK                                                 0x00001F00L
41610 #define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3_MASK                                                 0x001F0000L
41611 #define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4_MASK                                                 0x1F000000L
41612 //PWRBRK_STALL_TO_RELEASE_LUT_5_7
41613 #define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5__SHIFT                                               0x0
41614 #define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6__SHIFT                                               0x8
41615 #define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7__SHIFT                                               0x10
41616 #define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5_MASK                                                 0x0000001FL
41617 #define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6_MASK                                                 0x00001F00L
41618 #define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7_MASK                                                 0x001F0000L
41619 //PWRBRK_RELEASE_TO_STALL_LUT_1_8
41620 #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1__SHIFT                                               0x0
41621 #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2__SHIFT                                               0x4
41622 #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3__SHIFT                                               0x8
41623 #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4__SHIFT                                               0xc
41624 #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5__SHIFT                                               0x10
41625 #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6__SHIFT                                               0x14
41626 #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7__SHIFT                                               0x18
41627 #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8__SHIFT                                               0x1c
41628 #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1_MASK                                                 0x00000007L
41629 #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2_MASK                                                 0x00000070L
41630 #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3_MASK                                                 0x00000700L
41631 #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4_MASK                                                 0x00007000L
41632 #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5_MASK                                                 0x00070000L
41633 #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6_MASK                                                 0x00700000L
41634 #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7_MASK                                                 0x07000000L
41635 #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8_MASK                                                 0x70000000L
41636 //PWRBRK_RELEASE_TO_STALL_LUT_9_16
41637 #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9__SHIFT                                              0x0
41638 #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10__SHIFT                                             0x4
41639 #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11__SHIFT                                             0x8
41640 #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12__SHIFT                                             0xc
41641 #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13__SHIFT                                             0x10
41642 #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14__SHIFT                                             0x14
41643 #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15__SHIFT                                             0x18
41644 #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16__SHIFT                                             0x1c
41645 #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9_MASK                                                0x00000007L
41646 #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10_MASK                                               0x00000070L
41647 #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11_MASK                                               0x00000700L
41648 #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12_MASK                                               0x00007000L
41649 #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13_MASK                                               0x00070000L
41650 #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14_MASK                                               0x00700000L
41651 #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15_MASK                                               0x07000000L
41652 #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16_MASK                                               0x70000000L
41653 //PWRBRK_RELEASE_TO_STALL_LUT_17_20
41654 #define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17__SHIFT                                            0x0
41655 #define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18__SHIFT                                            0x4
41656 #define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19__SHIFT                                            0x8
41657 #define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20__SHIFT                                            0xc
41658 #define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17_MASK                                              0x00000007L
41659 #define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18_MASK                                              0x00000070L
41660 #define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19_MASK                                              0x00000700L
41661 #define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20_MASK                                              0x00007000L
41662 //FIXED_PATTERN_PERF_COUNTER_1
41663 #define FIXED_PATTERN_PERF_COUNTER_1__PERF_COUNTER__SHIFT                                                     0x0
41664 #define FIXED_PATTERN_PERF_COUNTER_1__PERF_COUNTER_MASK                                                       0x0001FFFFL
41665 //FIXED_PATTERN_PERF_COUNTER_2
41666 #define FIXED_PATTERN_PERF_COUNTER_2__PERF_COUNTER__SHIFT                                                     0x0
41667 #define FIXED_PATTERN_PERF_COUNTER_2__PERF_COUNTER_MASK                                                       0x0001FFFFL
41668 //FIXED_PATTERN_PERF_COUNTER_3
41669 #define FIXED_PATTERN_PERF_COUNTER_3__PERF_COUNTER__SHIFT                                                     0x0
41670 #define FIXED_PATTERN_PERF_COUNTER_3__PERF_COUNTER_MASK                                                       0x0001FFFFL
41671 //FIXED_PATTERN_PERF_COUNTER_4
41672 #define FIXED_PATTERN_PERF_COUNTER_4__PERF_COUNTER__SHIFT                                                     0x0
41673 #define FIXED_PATTERN_PERF_COUNTER_4__PERF_COUNTER_MASK                                                       0x0001FFFFL
41674 //FIXED_PATTERN_PERF_COUNTER_5
41675 #define FIXED_PATTERN_PERF_COUNTER_5__PERF_COUNTER__SHIFT                                                     0x0
41676 #define FIXED_PATTERN_PERF_COUNTER_5__PERF_COUNTER_MASK                                                       0x0001FFFFL
41677 //FIXED_PATTERN_PERF_COUNTER_6
41678 #define FIXED_PATTERN_PERF_COUNTER_6__PERF_COUNTER__SHIFT                                                     0x0
41679 #define FIXED_PATTERN_PERF_COUNTER_6__PERF_COUNTER_MASK                                                       0x0001FFFFL
41680 //FIXED_PATTERN_PERF_COUNTER_7
41681 #define FIXED_PATTERN_PERF_COUNTER_7__PERF_COUNTER__SHIFT                                                     0x0
41682 #define FIXED_PATTERN_PERF_COUNTER_7__PERF_COUNTER_MASK                                                       0x0001FFFFL
41683 //FIXED_PATTERN_PERF_COUNTER_8
41684 #define FIXED_PATTERN_PERF_COUNTER_8__PERF_COUNTER__SHIFT                                                     0x0
41685 #define FIXED_PATTERN_PERF_COUNTER_8__PERF_COUNTER_MASK                                                       0x0001FFFFL
41686 //FIXED_PATTERN_PERF_COUNTER_9
41687 #define FIXED_PATTERN_PERF_COUNTER_9__PERF_COUNTER__SHIFT                                                     0x0
41688 #define FIXED_PATTERN_PERF_COUNTER_9__PERF_COUNTER_MASK                                                       0x0001FFFFL
41689 //FIXED_PATTERN_PERF_COUNTER_10
41690 #define FIXED_PATTERN_PERF_COUNTER_10__PERF_COUNTER__SHIFT                                                    0x0
41691 #define FIXED_PATTERN_PERF_COUNTER_10__PERF_COUNTER_MASK                                                      0x0001FFFFL
41692 //HW_LUT_UPDATE_STATUS
41693 #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_DONE__SHIFT                                                      0x0
41694 #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR__SHIFT                                                     0x1
41695 #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR_STEP__SHIFT                                                0x2
41696 #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_DONE__SHIFT                                                      0x5
41697 #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR__SHIFT                                                     0x6
41698 #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR_STEP__SHIFT                                                0x7
41699 #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_DONE__SHIFT                                                      0xa
41700 #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR__SHIFT                                                     0xb
41701 #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR_STEP__SHIFT                                                0xc
41702 #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_DONE__SHIFT                                                      0x11
41703 #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR__SHIFT                                                     0x12
41704 #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR_STEP__SHIFT                                                0x13
41705 #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_DONE__SHIFT                                                      0x16
41706 #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR__SHIFT                                                     0x17
41707 #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR_STEP__SHIFT                                                0x18
41708 #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_DONE_MASK                                                        0x00000001L
41709 #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR_MASK                                                       0x00000002L
41710 #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR_STEP_MASK                                                  0x0000001CL
41711 #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_DONE_MASK                                                        0x00000020L
41712 #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR_MASK                                                       0x00000040L
41713 #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR_STEP_MASK                                                  0x00000380L
41714 #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_DONE_MASK                                                        0x00000400L
41715 #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR_MASK                                                       0x00000800L
41716 #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR_STEP_MASK                                                  0x0001F000L
41717 #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_DONE_MASK                                                        0x00020000L
41718 #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR_MASK                                                       0x00040000L
41719 #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR_STEP_MASK                                                  0x00380000L
41720 #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_DONE_MASK                                                        0x00400000L
41721 #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR_MASK                                                       0x00800000L
41722 #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR_STEP_MASK                                                  0x1F000000L
41723 
41724 
41725 // addressBlock: secacind
41726 //SE_CAC_ID
41727 #define SE_CAC_ID__CAC_BLOCK_ID__SHIFT                                                                        0x0
41728 #define SE_CAC_ID__CAC_SIGNAL_ID__SHIFT                                                                       0x6
41729 #define SE_CAC_ID__UNUSED_0__SHIFT                                                                            0xe
41730 #define SE_CAC_ID__CAC_BLOCK_ID_MASK                                                                          0x0000003FL
41731 #define SE_CAC_ID__CAC_SIGNAL_ID_MASK                                                                         0x00003FC0L
41732 #define SE_CAC_ID__UNUSED_0_MASK                                                                              0xFFFFC000L
41733 //SE_CAC_CNTL
41734 #define SE_CAC_CNTL__CAC_FORCE_DISABLE__SHIFT                                                                 0x0
41735 #define SE_CAC_CNTL__CAC_THRESHOLD__SHIFT                                                                     0x1
41736 #define SE_CAC_CNTL__UNUSED_0__SHIFT                                                                          0x11
41737 #define SE_CAC_CNTL__CAC_FORCE_DISABLE_MASK                                                                   0x00000001L
41738 #define SE_CAC_CNTL__CAC_THRESHOLD_MASK                                                                       0x0001FFFEL
41739 #define SE_CAC_CNTL__UNUSED_0_MASK                                                                            0xFFFE0000L
41740 //SE_CAC_OVR_SEL
41741 #define SE_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT                                                                    0x0
41742 #define SE_CAC_OVR_SEL__CAC_OVR_SEL_MASK                                                                      0xFFFFFFFFL
41743 //SE_CAC_OVR_VAL
41744 #define SE_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT                                                                    0x0
41745 #define SE_CAC_OVR_VAL__CAC_OVR_VAL_MASK                                                                      0xFFFFFFFFL
41746 
41747 
41748 // addressBlock: spmglbind
41749 //GLB_CPG_SAMPLEDELAY
41750 #define GLB_CPG_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                               0x0
41751 #define GLB_CPG_SAMPLEDELAY__RESERVED__SHIFT                                                                  0x6
41752 #define GLB_CPG_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                 0x0000003FL
41753 #define GLB_CPG_SAMPLEDELAY__RESERVED_MASK                                                                    0xFFFFFFC0L
41754 //GLB_CPC_SAMPLEDELAY
41755 #define GLB_CPC_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                               0x0
41756 #define GLB_CPC_SAMPLEDELAY__RESERVED__SHIFT                                                                  0x6
41757 #define GLB_CPC_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                 0x0000003FL
41758 #define GLB_CPC_SAMPLEDELAY__RESERVED_MASK                                                                    0xFFFFFFC0L
41759 //GLB_CPF_SAMPLEDELAY
41760 #define GLB_CPF_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                               0x0
41761 #define GLB_CPF_SAMPLEDELAY__RESERVED__SHIFT                                                                  0x6
41762 #define GLB_CPF_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                 0x0000003FL
41763 #define GLB_CPF_SAMPLEDELAY__RESERVED_MASK                                                                    0xFFFFFFC0L
41764 //GLB_GDS_SAMPLEDELAY
41765 #define GLB_GDS_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                               0x0
41766 #define GLB_GDS_SAMPLEDELAY__RESERVED__SHIFT                                                                  0x6
41767 #define GLB_GDS_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                 0x0000003FL
41768 #define GLB_GDS_SAMPLEDELAY__RESERVED_MASK                                                                    0xFFFFFFC0L
41769 //GLB_GCR_SAMPLEDELAY
41770 #define GLB_GCR_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                               0x0
41771 #define GLB_GCR_SAMPLEDELAY__RESERVED__SHIFT                                                                  0x6
41772 #define GLB_GCR_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                 0x0000003FL
41773 #define GLB_GCR_SAMPLEDELAY__RESERVED_MASK                                                                    0xFFFFFFC0L
41774 //GLB_PH_SAMPLEDELAY
41775 #define GLB_PH_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                                0x0
41776 #define GLB_PH_SAMPLEDELAY__RESERVED__SHIFT                                                                   0x6
41777 #define GLB_PH_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                  0x0000003FL
41778 #define GLB_PH_SAMPLEDELAY__RESERVED_MASK                                                                     0xFFFFFFC0L
41779 //GLB_GE_SAMPLEDELAY
41780 #define GLB_GE_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                                0x0
41781 #define GLB_GE_SAMPLEDELAY__RESERVED__SHIFT                                                                   0x6
41782 #define GLB_GE_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                  0x0000003FL
41783 #define GLB_GE_SAMPLEDELAY__RESERVED_MASK                                                                     0xFFFFFFC0L
41784 //GLB_GUS_SAMPLEDELAY
41785 #define GLB_GUS_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                               0x0
41786 #define GLB_GUS_SAMPLEDELAY__RESERVED__SHIFT                                                                  0x6
41787 #define GLB_GUS_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                 0x0000003FL
41788 #define GLB_GUS_SAMPLEDELAY__RESERVED_MASK                                                                    0xFFFFFFC0L
41789 //GLB_CHA_SAMPLEDELAY
41790 #define GLB_CHA_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                               0x0
41791 #define GLB_CHA_SAMPLEDELAY__RESERVED__SHIFT                                                                  0x6
41792 #define GLB_CHA_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                 0x0000003FL
41793 #define GLB_CHA_SAMPLEDELAY__RESERVED_MASK                                                                    0xFFFFFFC0L
41794 //GLB_CHCG_SAMPLEDELAY
41795 #define GLB_CHCG_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                              0x0
41796 #define GLB_CHCG_SAMPLEDELAY__RESERVED__SHIFT                                                                 0x6
41797 #define GLB_CHCG_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                0x0000003FL
41798 #define GLB_CHCG_SAMPLEDELAY__RESERVED_MASK                                                                   0xFFFFFFC0L
41799 //GLB_ATCL2_SAMPLEDELAY
41800 #define GLB_ATCL2_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
41801 #define GLB_ATCL2_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
41802 #define GLB_ATCL2_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
41803 #define GLB_ATCL2_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
41804 //GLB_VML2_SAMPLEDELAY
41805 #define GLB_VML2_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                              0x0
41806 #define GLB_VML2_SAMPLEDELAY__RESERVED__SHIFT                                                                 0x6
41807 #define GLB_VML2_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                0x0000003FL
41808 #define GLB_VML2_SAMPLEDELAY__RESERVED_MASK                                                                   0xFFFFFFC0L
41809 //GLB_SDMA0_SAMPLEDELAY
41810 #define GLB_SDMA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
41811 #define GLB_SDMA0_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
41812 #define GLB_SDMA0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
41813 #define GLB_SDMA0_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
41814 //GLB_SDMA1_SAMPLEDELAY
41815 #define GLB_SDMA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
41816 #define GLB_SDMA1_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
41817 #define GLB_SDMA1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
41818 #define GLB_SDMA1_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
41819 //GLB_GL2A0_SAMPLEDELAY
41820 #define GLB_GL2A0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
41821 #define GLB_GL2A0_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
41822 #define GLB_GL2A0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
41823 #define GLB_GL2A0_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
41824 //GLB_GL2A1_SAMPLEDELAY
41825 #define GLB_GL2A1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
41826 #define GLB_GL2A1_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
41827 #define GLB_GL2A1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
41828 #define GLB_GL2A1_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
41829 //GLB_GL2A2_SAMPLEDELAY
41830 #define GLB_GL2A2_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
41831 #define GLB_GL2A2_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
41832 #define GLB_GL2A2_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
41833 #define GLB_GL2A2_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
41834 //GLB_GL2A3_SAMPLEDELAY
41835 #define GLB_GL2A3_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
41836 #define GLB_GL2A3_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
41837 #define GLB_GL2A3_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
41838 #define GLB_GL2A3_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
41839 //GLB_GL2C0_SAMPLEDELAY
41840 #define GLB_GL2C0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
41841 #define GLB_GL2C0_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
41842 #define GLB_GL2C0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
41843 #define GLB_GL2C0_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
41844 //GLB_GL2C1_SAMPLEDELAY
41845 #define GLB_GL2C1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
41846 #define GLB_GL2C1_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
41847 #define GLB_GL2C1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
41848 #define GLB_GL2C1_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
41849 //GLB_GL2C2_SAMPLEDELAY
41850 #define GLB_GL2C2_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
41851 #define GLB_GL2C2_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
41852 #define GLB_GL2C2_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
41853 #define GLB_GL2C2_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
41854 //GLB_GL2C3_SAMPLEDELAY
41855 #define GLB_GL2C3_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
41856 #define GLB_GL2C3_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
41857 #define GLB_GL2C3_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
41858 #define GLB_GL2C3_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
41859 //GLB_GL2C4_SAMPLEDELAY
41860 #define GLB_GL2C4_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
41861 #define GLB_GL2C4_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
41862 #define GLB_GL2C4_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
41863 #define GLB_GL2C4_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
41864 //GLB_GL2C5_SAMPLEDELAY
41865 #define GLB_GL2C5_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
41866 #define GLB_GL2C5_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
41867 #define GLB_GL2C5_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
41868 #define GLB_GL2C5_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
41869 //GLB_GL2C6_SAMPLEDELAY
41870 #define GLB_GL2C6_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
41871 #define GLB_GL2C6_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
41872 #define GLB_GL2C6_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
41873 #define GLB_GL2C6_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
41874 //GLB_GL2C7_SAMPLEDELAY
41875 #define GLB_GL2C7_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
41876 #define GLB_GL2C7_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
41877 #define GLB_GL2C7_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
41878 #define GLB_GL2C7_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
41879 //GLB_GL2C8_SAMPLEDELAY
41880 #define GLB_GL2C8_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
41881 #define GLB_GL2C8_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
41882 #define GLB_GL2C8_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
41883 #define GLB_GL2C8_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
41884 //GLB_GL2C9_SAMPLEDELAY
41885 #define GLB_GL2C9_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
41886 #define GLB_GL2C9_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
41887 #define GLB_GL2C9_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
41888 #define GLB_GL2C9_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
41889 //GLB_GL2C10_SAMPLEDELAY
41890 #define GLB_GL2C10_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                            0x0
41891 #define GLB_GL2C10_SAMPLEDELAY__RESERVED__SHIFT                                                               0x6
41892 #define GLB_GL2C10_SAMPLEDELAY__SAMPLEDELAY_MASK                                                              0x0000003FL
41893 #define GLB_GL2C10_SAMPLEDELAY__RESERVED_MASK                                                                 0xFFFFFFC0L
41894 //GLB_GL2C11_SAMPLEDELAY
41895 #define GLB_GL2C11_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                            0x0
41896 #define GLB_GL2C11_SAMPLEDELAY__RESERVED__SHIFT                                                               0x6
41897 #define GLB_GL2C11_SAMPLEDELAY__SAMPLEDELAY_MASK                                                              0x0000003FL
41898 #define GLB_GL2C11_SAMPLEDELAY__RESERVED_MASK                                                                 0xFFFFFFC0L
41899 //GLB_GL2C12_SAMPLEDELAY
41900 #define GLB_GL2C12_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                            0x0
41901 #define GLB_GL2C12_SAMPLEDELAY__RESERVED__SHIFT                                                               0x6
41902 #define GLB_GL2C12_SAMPLEDELAY__SAMPLEDELAY_MASK                                                              0x0000003FL
41903 #define GLB_GL2C12_SAMPLEDELAY__RESERVED_MASK                                                                 0xFFFFFFC0L
41904 //GLB_GL2C13_SAMPLEDELAY
41905 #define GLB_GL2C13_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                            0x0
41906 #define GLB_GL2C13_SAMPLEDELAY__RESERVED__SHIFT                                                               0x6
41907 #define GLB_GL2C13_SAMPLEDELAY__SAMPLEDELAY_MASK                                                              0x0000003FL
41908 #define GLB_GL2C13_SAMPLEDELAY__RESERVED_MASK                                                                 0xFFFFFFC0L
41909 //GLB_GL2C14_SAMPLEDELAY
41910 #define GLB_GL2C14_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                            0x0
41911 #define GLB_GL2C14_SAMPLEDELAY__RESERVED__SHIFT                                                               0x6
41912 #define GLB_GL2C14_SAMPLEDELAY__SAMPLEDELAY_MASK                                                              0x0000003FL
41913 #define GLB_GL2C14_SAMPLEDELAY__RESERVED_MASK                                                                 0xFFFFFFC0L
41914 //GLB_GL2C15_SAMPLEDELAY
41915 #define GLB_GL2C15_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                            0x0
41916 #define GLB_GL2C15_SAMPLEDELAY__RESERVED__SHIFT                                                               0x6
41917 #define GLB_GL2C15_SAMPLEDELAY__SAMPLEDELAY_MASK                                                              0x0000003FL
41918 #define GLB_GL2C15_SAMPLEDELAY__RESERVED_MASK                                                                 0xFFFFFFC0L
41919 //GLB_EA0_SAMPLEDELAY
41920 #define GLB_EA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                               0x0
41921 #define GLB_EA0_SAMPLEDELAY__RESERVED__SHIFT                                                                  0x6
41922 #define GLB_EA0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                 0x0000003FL
41923 #define GLB_EA0_SAMPLEDELAY__RESERVED_MASK                                                                    0xFFFFFFC0L
41924 //GLB_EA1_SAMPLEDELAY
41925 #define GLB_EA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                               0x0
41926 #define GLB_EA1_SAMPLEDELAY__RESERVED__SHIFT                                                                  0x6
41927 #define GLB_EA1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                 0x0000003FL
41928 #define GLB_EA1_SAMPLEDELAY__RESERVED_MASK                                                                    0xFFFFFFC0L
41929 //GLB_EA2_SAMPLEDELAY
41930 #define GLB_EA2_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                               0x0
41931 #define GLB_EA2_SAMPLEDELAY__RESERVED__SHIFT                                                                  0x6
41932 #define GLB_EA2_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                 0x0000003FL
41933 #define GLB_EA2_SAMPLEDELAY__RESERVED_MASK                                                                    0xFFFFFFC0L
41934 //GLB_EA3_SAMPLEDELAY
41935 #define GLB_EA3_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                               0x0
41936 #define GLB_EA3_SAMPLEDELAY__RESERVED__SHIFT                                                                  0x6
41937 #define GLB_EA3_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                 0x0000003FL
41938 #define GLB_EA3_SAMPLEDELAY__RESERVED_MASK                                                                    0xFFFFFFC0L
41939 //GLB_EA4_SAMPLEDELAY
41940 #define GLB_EA4_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                               0x0
41941 #define GLB_EA4_SAMPLEDELAY__RESERVED__SHIFT                                                                  0x6
41942 #define GLB_EA4_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                 0x0000003FL
41943 #define GLB_EA4_SAMPLEDELAY__RESERVED_MASK                                                                    0xFFFFFFC0L
41944 //GLB_EA5_SAMPLEDELAY
41945 #define GLB_EA5_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                               0x0
41946 #define GLB_EA5_SAMPLEDELAY__RESERVED__SHIFT                                                                  0x6
41947 #define GLB_EA5_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                 0x0000003FL
41948 #define GLB_EA5_SAMPLEDELAY__RESERVED_MASK                                                                    0xFFFFFFC0L
41949 //GLB_EA6_SAMPLEDELAY
41950 #define GLB_EA6_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                               0x0
41951 #define GLB_EA6_SAMPLEDELAY__RESERVED__SHIFT                                                                  0x6
41952 #define GLB_EA6_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                 0x0000003FL
41953 #define GLB_EA6_SAMPLEDELAY__RESERVED_MASK                                                                    0xFFFFFFC0L
41954 //GLB_EA7_SAMPLEDELAY
41955 #define GLB_EA7_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                               0x0
41956 #define GLB_EA7_SAMPLEDELAY__RESERVED__SHIFT                                                                  0x6
41957 #define GLB_EA7_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                 0x0000003FL
41958 #define GLB_EA7_SAMPLEDELAY__RESERVED_MASK                                                                    0xFFFFFFC0L
41959 //GLB_EA8_SAMPLEDELAY
41960 #define GLB_EA8_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                               0x0
41961 #define GLB_EA8_SAMPLEDELAY__RESERVED__SHIFT                                                                  0x6
41962 #define GLB_EA8_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                 0x0000003FL
41963 #define GLB_EA8_SAMPLEDELAY__RESERVED_MASK                                                                    0xFFFFFFC0L
41964 //GLB_EA9_SAMPLEDELAY
41965 #define GLB_EA9_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                               0x0
41966 #define GLB_EA9_SAMPLEDELAY__RESERVED__SHIFT                                                                  0x6
41967 #define GLB_EA9_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                 0x0000003FL
41968 #define GLB_EA9_SAMPLEDELAY__RESERVED_MASK                                                                    0xFFFFFFC0L
41969 //GLB_EA10_SAMPLEDELAY
41970 #define GLB_EA10_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                              0x0
41971 #define GLB_EA10_SAMPLEDELAY__RESERVED__SHIFT                                                                 0x6
41972 #define GLB_EA10_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                0x0000003FL
41973 #define GLB_EA10_SAMPLEDELAY__RESERVED_MASK                                                                   0xFFFFFFC0L
41974 //GLB_EA11_SAMPLEDELAY
41975 #define GLB_EA11_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                              0x0
41976 #define GLB_EA11_SAMPLEDELAY__RESERVED__SHIFT                                                                 0x6
41977 #define GLB_EA11_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                0x0000003FL
41978 #define GLB_EA11_SAMPLEDELAY__RESERVED_MASK                                                                   0xFFFFFFC0L
41979 //GLB_EA12_SAMPLEDELAY
41980 #define GLB_EA12_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                              0x0
41981 #define GLB_EA12_SAMPLEDELAY__RESERVED__SHIFT                                                                 0x6
41982 #define GLB_EA12_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                0x0000003FL
41983 #define GLB_EA12_SAMPLEDELAY__RESERVED_MASK                                                                   0xFFFFFFC0L
41984 //GLB_EA13_SAMPLEDELAY
41985 #define GLB_EA13_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                              0x0
41986 #define GLB_EA13_SAMPLEDELAY__RESERVED__SHIFT                                                                 0x6
41987 #define GLB_EA13_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                0x0000003FL
41988 #define GLB_EA13_SAMPLEDELAY__RESERVED_MASK                                                                   0xFFFFFFC0L
41989 //GLB_EA14_SAMPLEDELAY
41990 #define GLB_EA14_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                              0x0
41991 #define GLB_EA14_SAMPLEDELAY__RESERVED__SHIFT                                                                 0x6
41992 #define GLB_EA14_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                0x0000003FL
41993 #define GLB_EA14_SAMPLEDELAY__RESERVED_MASK                                                                   0xFFFFFFC0L
41994 //GLB_EA15_SAMPLEDELAY
41995 #define GLB_EA15_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                              0x0
41996 #define GLB_EA15_SAMPLEDELAY__RESERVED__SHIFT                                                                 0x6
41997 #define GLB_EA15_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                0x0000003FL
41998 #define GLB_EA15_SAMPLEDELAY__RESERVED_MASK                                                                   0xFFFFFFC0L
41999 //GLB_CHC0_SAMPLEDELAY
42000 #define GLB_CHC0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                              0x0
42001 #define GLB_CHC0_SAMPLEDELAY__RESERVED__SHIFT                                                                 0x6
42002 #define GLB_CHC0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                0x0000003FL
42003 #define GLB_CHC0_SAMPLEDELAY__RESERVED_MASK                                                                   0xFFFFFFC0L
42004 //GLB_CHC1_SAMPLEDELAY
42005 #define GLB_CHC1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                              0x0
42006 #define GLB_CHC1_SAMPLEDELAY__RESERVED__SHIFT                                                                 0x6
42007 #define GLB_CHC1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                0x0000003FL
42008 #define GLB_CHC1_SAMPLEDELAY__RESERVED_MASK                                                                   0xFFFFFFC0L
42009 //GLB_CHC2_SAMPLEDELAY
42010 #define GLB_CHC2_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                              0x0
42011 #define GLB_CHC2_SAMPLEDELAY__RESERVED__SHIFT                                                                 0x6
42012 #define GLB_CHC2_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                0x0000003FL
42013 #define GLB_CHC2_SAMPLEDELAY__RESERVED_MASK                                                                   0xFFFFFFC0L
42014 //GLB_CHC3_SAMPLEDELAY
42015 #define GLB_CHC3_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                              0x0
42016 #define GLB_CHC3_SAMPLEDELAY__RESERVED__SHIFT                                                                 0x6
42017 #define GLB_CHC3_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                0x0000003FL
42018 #define GLB_CHC3_SAMPLEDELAY__RESERVED_MASK                                                                   0xFFFFFFC0L
42019 
42020 
42021 // addressBlock: spmind
42022 //SE_SPI_SAMPLEDELAY
42023 #define SE_SPI_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                                0x0
42024 #define SE_SPI_SAMPLEDELAY__RESERVED__SHIFT                                                                   0x6
42025 #define SE_SPI_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                  0x0000003FL
42026 #define SE_SPI_SAMPLEDELAY__RESERVED_MASK                                                                     0xFFFFFFC0L
42027 //SE_SQG_SAMPLEDELAY
42028 #define SE_SQG_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                                0x0
42029 #define SE_SQG_SAMPLEDELAY__RESERVED__SHIFT                                                                   0x6
42030 #define SE_SQG_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                  0x0000003FL
42031 #define SE_SQG_SAMPLEDELAY__RESERVED_MASK                                                                     0xFFFFFFC0L
42032 //SE_CBR_SAMPLEDELAY
42033 #define SE_CBR_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                                0x0
42034 #define SE_CBR_SAMPLEDELAY__RESERVED__SHIFT                                                                   0x6
42035 #define SE_CBR_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                  0x0000003FL
42036 #define SE_CBR_SAMPLEDELAY__RESERVED_MASK                                                                     0xFFFFFFC0L
42037 //SE_DBR_SAMPLEDELAY
42038 #define SE_DBR_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                                0x0
42039 #define SE_DBR_SAMPLEDELAY__RESERVED__SHIFT                                                                   0x6
42040 #define SE_DBR_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                  0x0000003FL
42041 #define SE_DBR_SAMPLEDELAY__RESERVED_MASK                                                                     0xFFFFFFC0L
42042 //SE_SA0SX_SAMPLEDELAY
42043 #define SE_SA0SX_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                              0x0
42044 #define SE_SA0SX_SAMPLEDELAY__RESERVED__SHIFT                                                                 0x6
42045 #define SE_SA0SX_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                0x0000003FL
42046 #define SE_SA0SX_SAMPLEDELAY__RESERVED_MASK                                                                   0xFFFFFFC0L
42047 //SE_SA0PA_SAMPLEDELAY
42048 #define SE_SA0PA_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                              0x0
42049 #define SE_SA0PA_SAMPLEDELAY__RESERVED__SHIFT                                                                 0x6
42050 #define SE_SA0PA_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                0x0000003FL
42051 #define SE_SA0PA_SAMPLEDELAY__RESERVED_MASK                                                                   0xFFFFFFC0L
42052 //SE_SA0GL1A_SAMPLEDELAY
42053 #define SE_SA0GL1A_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                            0x0
42054 #define SE_SA0GL1A_SAMPLEDELAY__RESERVED__SHIFT                                                               0x6
42055 #define SE_SA0GL1A_SAMPLEDELAY__SAMPLEDELAY_MASK                                                              0x0000003FL
42056 #define SE_SA0GL1A_SAMPLEDELAY__RESERVED_MASK                                                                 0xFFFFFFC0L
42057 //SE_SA0GL1CG_SAMPLEDELAY
42058 #define SE_SA0GL1CG_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                           0x0
42059 #define SE_SA0GL1CG_SAMPLEDELAY__RESERVED__SHIFT                                                              0x6
42060 #define SE_SA0GL1CG_SAMPLEDELAY__SAMPLEDELAY_MASK                                                             0x0000003FL
42061 #define SE_SA0GL1CG_SAMPLEDELAY__RESERVED_MASK                                                                0xFFFFFFC0L
42062 //SE_SA0CB0_SAMPLEDELAY
42063 #define SE_SA0CB0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
42064 #define SE_SA0CB0_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
42065 #define SE_SA0CB0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
42066 #define SE_SA0CB0_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
42067 //SE_SA0CB1_SAMPLEDELAY
42068 #define SE_SA0CB1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
42069 #define SE_SA0CB1_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
42070 #define SE_SA0CB1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
42071 #define SE_SA0CB1_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
42072 //SE_SA0CB2_SAMPLEDELAY
42073 #define SE_SA0CB2_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
42074 #define SE_SA0CB2_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
42075 #define SE_SA0CB2_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
42076 #define SE_SA0CB2_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
42077 //SE_SA0CB3_SAMPLEDELAY
42078 #define SE_SA0CB3_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
42079 #define SE_SA0CB3_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
42080 #define SE_SA0CB3_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
42081 #define SE_SA0CB3_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
42082 //SE_SA0DB0_SAMPLEDELAY
42083 #define SE_SA0DB0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
42084 #define SE_SA0DB0_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
42085 #define SE_SA0DB0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
42086 #define SE_SA0DB0_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
42087 //SE_SA0DB1_SAMPLEDELAY
42088 #define SE_SA0DB1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
42089 #define SE_SA0DB1_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
42090 #define SE_SA0DB1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
42091 #define SE_SA0DB1_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
42092 //SE_SA0DB2_SAMPLEDELAY
42093 #define SE_SA0DB2_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
42094 #define SE_SA0DB2_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
42095 #define SE_SA0DB2_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
42096 #define SE_SA0DB2_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
42097 //SE_SA0DB3_SAMPLEDELAY
42098 #define SE_SA0DB3_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
42099 #define SE_SA0DB3_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
42100 #define SE_SA0DB3_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
42101 #define SE_SA0DB3_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
42102 //SE_SA0SC0_SAMPLEDELAY
42103 #define SE_SA0SC0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
42104 #define SE_SA0SC0_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
42105 #define SE_SA0SC0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
42106 #define SE_SA0SC0_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
42107 //SE_SA0SC1_SAMPLEDELAY
42108 #define SE_SA0SC1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
42109 #define SE_SA0SC1_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
42110 #define SE_SA0SC1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
42111 #define SE_SA0SC1_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
42112 //SE_SA0RMI0_SAMPLEDELAY
42113 #define SE_SA0RMI0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                            0x0
42114 #define SE_SA0RMI0_SAMPLEDELAY__RESERVED__SHIFT                                                               0x6
42115 #define SE_SA0RMI0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                              0x0000003FL
42116 #define SE_SA0RMI0_SAMPLEDELAY__RESERVED_MASK                                                                 0xFFFFFFC0L
42117 //SE_SA0RMI1_SAMPLEDELAY
42118 #define SE_SA0RMI1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                            0x0
42119 #define SE_SA0RMI1_SAMPLEDELAY__RESERVED__SHIFT                                                               0x6
42120 #define SE_SA0RMI1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                              0x0000003FL
42121 #define SE_SA0RMI1_SAMPLEDELAY__RESERVED_MASK                                                                 0xFFFFFFC0L
42122 //SE_SA0GL1C0_SAMPLEDELAY
42123 #define SE_SA0GL1C0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                           0x0
42124 #define SE_SA0GL1C0_SAMPLEDELAY__RESERVED__SHIFT                                                              0x6
42125 #define SE_SA0GL1C0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                             0x0000003FL
42126 #define SE_SA0GL1C0_SAMPLEDELAY__RESERVED_MASK                                                                0xFFFFFFC0L
42127 //SE_SA0GL1C1_SAMPLEDELAY
42128 #define SE_SA0GL1C1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                           0x0
42129 #define SE_SA0GL1C1_SAMPLEDELAY__RESERVED__SHIFT                                                              0x6
42130 #define SE_SA0GL1C1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                             0x0000003FL
42131 #define SE_SA0GL1C1_SAMPLEDELAY__RESERVED_MASK                                                                0xFFFFFFC0L
42132 //SE_SA0GL1C2_SAMPLEDELAY
42133 #define SE_SA0GL1C2_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                           0x0
42134 #define SE_SA0GL1C2_SAMPLEDELAY__RESERVED__SHIFT                                                              0x6
42135 #define SE_SA0GL1C2_SAMPLEDELAY__SAMPLEDELAY_MASK                                                             0x0000003FL
42136 #define SE_SA0GL1C2_SAMPLEDELAY__RESERVED_MASK                                                                0xFFFFFFC0L
42137 //SE_SA0GL1C3_SAMPLEDELAY
42138 #define SE_SA0GL1C3_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                           0x0
42139 #define SE_SA0GL1C3_SAMPLEDELAY__RESERVED__SHIFT                                                              0x6
42140 #define SE_SA0GL1C3_SAMPLEDELAY__SAMPLEDELAY_MASK                                                             0x0000003FL
42141 #define SE_SA0GL1C3_SAMPLEDELAY__RESERVED_MASK                                                                0xFFFFFFC0L
42142 //SE_SA0WGP00TA0_SAMPLEDELAY
42143 #define SE_SA0WGP00TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42144 #define SE_SA0WGP00TA0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42145 #define SE_SA0WGP00TA0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42146 #define SE_SA0WGP00TA0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42147 //SE_SA0WGP00TA1_SAMPLEDELAY
42148 #define SE_SA0WGP00TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42149 #define SE_SA0WGP00TA1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42150 #define SE_SA0WGP00TA1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42151 #define SE_SA0WGP00TA1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42152 //SE_SA0WGP00TD0_SAMPLEDELAY
42153 #define SE_SA0WGP00TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42154 #define SE_SA0WGP00TD0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42155 #define SE_SA0WGP00TD0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42156 #define SE_SA0WGP00TD0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42157 //SE_SA0WGP00TD1_SAMPLEDELAY
42158 #define SE_SA0WGP00TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42159 #define SE_SA0WGP00TD1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42160 #define SE_SA0WGP00TD1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42161 #define SE_SA0WGP00TD1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42162 //SE_SA0WGP00TCP0_SAMPLEDELAY
42163 #define SE_SA0WGP00TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
42164 #define SE_SA0WGP00TCP0_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
42165 #define SE_SA0WGP00TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
42166 #define SE_SA0WGP00TCP0_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
42167 //SE_SA0WGP00TCP1_SAMPLEDELAY
42168 #define SE_SA0WGP00TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
42169 #define SE_SA0WGP00TCP1_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
42170 #define SE_SA0WGP00TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
42171 #define SE_SA0WGP00TCP1_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
42172 //SE_SA0WGP01TA0_SAMPLEDELAY
42173 #define SE_SA0WGP01TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42174 #define SE_SA0WGP01TA0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42175 #define SE_SA0WGP01TA0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42176 #define SE_SA0WGP01TA0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42177 //SE_SA0WGP01TA1_SAMPLEDELAY
42178 #define SE_SA0WGP01TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42179 #define SE_SA0WGP01TA1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42180 #define SE_SA0WGP01TA1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42181 #define SE_SA0WGP01TA1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42182 //SE_SA0WGP01TD0_SAMPLEDELAY
42183 #define SE_SA0WGP01TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42184 #define SE_SA0WGP01TD0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42185 #define SE_SA0WGP01TD0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42186 #define SE_SA0WGP01TD0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42187 //SE_SA0WGP01TD1_SAMPLEDELAY
42188 #define SE_SA0WGP01TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42189 #define SE_SA0WGP01TD1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42190 #define SE_SA0WGP01TD1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42191 #define SE_SA0WGP01TD1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42192 //SE_SA0WGP01TCP0_SAMPLEDELAY
42193 #define SE_SA0WGP01TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
42194 #define SE_SA0WGP01TCP0_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
42195 #define SE_SA0WGP01TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
42196 #define SE_SA0WGP01TCP0_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
42197 //SE_SA0WGP01TCP1_SAMPLEDELAY
42198 #define SE_SA0WGP01TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
42199 #define SE_SA0WGP01TCP1_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
42200 #define SE_SA0WGP01TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
42201 #define SE_SA0WGP01TCP1_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
42202 //SE_SA0WGP02TA0_SAMPLEDELAY
42203 #define SE_SA0WGP02TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42204 #define SE_SA0WGP02TA0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42205 #define SE_SA0WGP02TA0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42206 #define SE_SA0WGP02TA0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42207 //SE_SA0WGP02TA1_SAMPLEDELAY
42208 #define SE_SA0WGP02TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42209 #define SE_SA0WGP02TA1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42210 #define SE_SA0WGP02TA1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42211 #define SE_SA0WGP02TA1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42212 //SE_SA0WGP02TD0_SAMPLEDELAY
42213 #define SE_SA0WGP02TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42214 #define SE_SA0WGP02TD0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42215 #define SE_SA0WGP02TD0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42216 #define SE_SA0WGP02TD0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42217 //SE_SA0WGP02TD1_SAMPLEDELAY
42218 #define SE_SA0WGP02TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42219 #define SE_SA0WGP02TD1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42220 #define SE_SA0WGP02TD1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42221 #define SE_SA0WGP02TD1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42222 //SE_SA0WGP02TCP0_SAMPLEDELAY
42223 #define SE_SA0WGP02TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
42224 #define SE_SA0WGP02TCP0_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
42225 #define SE_SA0WGP02TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
42226 #define SE_SA0WGP02TCP0_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
42227 //SE_SA0WGP02TCP1_SAMPLEDELAY
42228 #define SE_SA0WGP02TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
42229 #define SE_SA0WGP02TCP1_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
42230 #define SE_SA0WGP02TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
42231 #define SE_SA0WGP02TCP1_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
42232 //SE_SA0WGP10TA0_SAMPLEDELAY
42233 #define SE_SA0WGP10TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42234 #define SE_SA0WGP10TA0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42235 #define SE_SA0WGP10TA0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42236 #define SE_SA0WGP10TA0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42237 //SE_SA0WGP10TA1_SAMPLEDELAY
42238 #define SE_SA0WGP10TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42239 #define SE_SA0WGP10TA1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42240 #define SE_SA0WGP10TA1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42241 #define SE_SA0WGP10TA1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42242 //SE_SA0WGP10TD0_SAMPLEDELAY
42243 #define SE_SA0WGP10TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42244 #define SE_SA0WGP10TD0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42245 #define SE_SA0WGP10TD0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42246 #define SE_SA0WGP10TD0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42247 //SE_SA0WGP10TD1_SAMPLEDELAY
42248 #define SE_SA0WGP10TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42249 #define SE_SA0WGP10TD1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42250 #define SE_SA0WGP10TD1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42251 #define SE_SA0WGP10TD1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42252 //SE_SA0WGP10TCP0_SAMPLEDELAY
42253 #define SE_SA0WGP10TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
42254 #define SE_SA0WGP10TCP0_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
42255 #define SE_SA0WGP10TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
42256 #define SE_SA0WGP10TCP0_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
42257 //SE_SA0WGP10TCP1_SAMPLEDELAY
42258 #define SE_SA0WGP10TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
42259 #define SE_SA0WGP10TCP1_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
42260 #define SE_SA0WGP10TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
42261 #define SE_SA0WGP10TCP1_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
42262 //SE_SA0WGP11TA0_SAMPLEDELAY
42263 #define SE_SA0WGP11TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42264 #define SE_SA0WGP11TA0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42265 #define SE_SA0WGP11TA0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42266 #define SE_SA0WGP11TA0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42267 //SE_SA0WGP11TA1_SAMPLEDELAY
42268 #define SE_SA0WGP11TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42269 #define SE_SA0WGP11TA1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42270 #define SE_SA0WGP11TA1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42271 #define SE_SA0WGP11TA1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42272 //SE_SA0WGP11TD0_SAMPLEDELAY
42273 #define SE_SA0WGP11TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42274 #define SE_SA0WGP11TD0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42275 #define SE_SA0WGP11TD0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42276 #define SE_SA0WGP11TD0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42277 //SE_SA0WGP11TD1_SAMPLEDELAY
42278 #define SE_SA0WGP11TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42279 #define SE_SA0WGP11TD1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42280 #define SE_SA0WGP11TD1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42281 #define SE_SA0WGP11TD1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42282 //SE_SA0WGP11TCP0_SAMPLEDELAY
42283 #define SE_SA0WGP11TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
42284 #define SE_SA0WGP11TCP0_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
42285 #define SE_SA0WGP11TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
42286 #define SE_SA0WGP11TCP0_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
42287 //SE_SA0WGP11TCP1_SAMPLEDELAY
42288 #define SE_SA0WGP11TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
42289 #define SE_SA0WGP11TCP1_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
42290 #define SE_SA0WGP11TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
42291 #define SE_SA0WGP11TCP1_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
42292 //SE_SA1SX_SAMPLEDELAY
42293 #define SE_SA1SX_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                              0x0
42294 #define SE_SA1SX_SAMPLEDELAY__RESERVED__SHIFT                                                                 0x6
42295 #define SE_SA1SX_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                0x0000003FL
42296 #define SE_SA1SX_SAMPLEDELAY__RESERVED_MASK                                                                   0xFFFFFFC0L
42297 //SE_SA1PA_SAMPLEDELAY
42298 #define SE_SA1PA_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                              0x0
42299 #define SE_SA1PA_SAMPLEDELAY__RESERVED__SHIFT                                                                 0x6
42300 #define SE_SA1PA_SAMPLEDELAY__SAMPLEDELAY_MASK                                                                0x0000003FL
42301 #define SE_SA1PA_SAMPLEDELAY__RESERVED_MASK                                                                   0xFFFFFFC0L
42302 //SE_SA1GL1A_SAMPLEDELAY
42303 #define SE_SA1GL1A_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                            0x0
42304 #define SE_SA1GL1A_SAMPLEDELAY__RESERVED__SHIFT                                                               0x6
42305 #define SE_SA1GL1A_SAMPLEDELAY__SAMPLEDELAY_MASK                                                              0x0000003FL
42306 #define SE_SA1GL1A_SAMPLEDELAY__RESERVED_MASK                                                                 0xFFFFFFC0L
42307 //SE_SA1GL1CG_SAMPLEDELAY
42308 #define SE_SA1GL1CG_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                           0x0
42309 #define SE_SA1GL1CG_SAMPLEDELAY__RESERVED__SHIFT                                                              0x6
42310 #define SE_SA1GL1CG_SAMPLEDELAY__SAMPLEDELAY_MASK                                                             0x0000003FL
42311 #define SE_SA1GL1CG_SAMPLEDELAY__RESERVED_MASK                                                                0xFFFFFFC0L
42312 //SE_SA1CB0_SAMPLEDELAY
42313 #define SE_SA1CB0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
42314 #define SE_SA1CB0_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
42315 #define SE_SA1CB0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
42316 #define SE_SA1CB0_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
42317 //SE_SA1CB1_SAMPLEDELAY
42318 #define SE_SA1CB1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
42319 #define SE_SA1CB1_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
42320 #define SE_SA1CB1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
42321 #define SE_SA1CB1_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
42322 //SE_SA1CB2_SAMPLEDELAY
42323 #define SE_SA1CB2_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
42324 #define SE_SA1CB2_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
42325 #define SE_SA1CB2_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
42326 #define SE_SA1CB2_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
42327 //SE_SA1CB3_SAMPLEDELAY
42328 #define SE_SA1CB3_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
42329 #define SE_SA1CB3_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
42330 #define SE_SA1CB3_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
42331 #define SE_SA1CB3_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
42332 //SE_SA1DB0_SAMPLEDELAY
42333 #define SE_SA1DB0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
42334 #define SE_SA1DB0_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
42335 #define SE_SA1DB0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
42336 #define SE_SA1DB0_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
42337 //SE_SA1DB1_SAMPLEDELAY
42338 #define SE_SA1DB1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
42339 #define SE_SA1DB1_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
42340 #define SE_SA1DB1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
42341 #define SE_SA1DB1_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
42342 //SE_SA1DB2_SAMPLEDELAY
42343 #define SE_SA1DB2_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
42344 #define SE_SA1DB2_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
42345 #define SE_SA1DB2_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
42346 #define SE_SA1DB2_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
42347 //SE_SA1DB3_SAMPLEDELAY
42348 #define SE_SA1DB3_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
42349 #define SE_SA1DB3_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
42350 #define SE_SA1DB3_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
42351 #define SE_SA1DB3_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
42352 //SE_SA1SC0_SAMPLEDELAY
42353 #define SE_SA1SC0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
42354 #define SE_SA1SC0_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
42355 #define SE_SA1SC0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
42356 #define SE_SA1SC0_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
42357 //SE_SA1SC1_SAMPLEDELAY
42358 #define SE_SA1SC1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                             0x0
42359 #define SE_SA1SC1_SAMPLEDELAY__RESERVED__SHIFT                                                                0x6
42360 #define SE_SA1SC1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                               0x0000003FL
42361 #define SE_SA1SC1_SAMPLEDELAY__RESERVED_MASK                                                                  0xFFFFFFC0L
42362 //SE_SA1RMI0_SAMPLEDELAY
42363 #define SE_SA1RMI0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                            0x0
42364 #define SE_SA1RMI0_SAMPLEDELAY__RESERVED__SHIFT                                                               0x6
42365 #define SE_SA1RMI0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                              0x0000003FL
42366 #define SE_SA1RMI0_SAMPLEDELAY__RESERVED_MASK                                                                 0xFFFFFFC0L
42367 //SE_SA1RMI1_SAMPLEDELAY
42368 #define SE_SA1RMI1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                            0x0
42369 #define SE_SA1RMI1_SAMPLEDELAY__RESERVED__SHIFT                                                               0x6
42370 #define SE_SA1RMI1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                              0x0000003FL
42371 #define SE_SA1RMI1_SAMPLEDELAY__RESERVED_MASK                                                                 0xFFFFFFC0L
42372 //SE_SA1GL1C0_SAMPLEDELAY
42373 #define SE_SA1GL1C0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                           0x0
42374 #define SE_SA1GL1C0_SAMPLEDELAY__RESERVED__SHIFT                                                              0x6
42375 #define SE_SA1GL1C0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                             0x0000003FL
42376 #define SE_SA1GL1C0_SAMPLEDELAY__RESERVED_MASK                                                                0xFFFFFFC0L
42377 //SE_SA1GL1C1_SAMPLEDELAY
42378 #define SE_SA1GL1C1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                           0x0
42379 #define SE_SA1GL1C1_SAMPLEDELAY__RESERVED__SHIFT                                                              0x6
42380 #define SE_SA1GL1C1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                             0x0000003FL
42381 #define SE_SA1GL1C1_SAMPLEDELAY__RESERVED_MASK                                                                0xFFFFFFC0L
42382 //SE_SA1GL1C2_SAMPLEDELAY
42383 #define SE_SA1GL1C2_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                           0x0
42384 #define SE_SA1GL1C2_SAMPLEDELAY__RESERVED__SHIFT                                                              0x6
42385 #define SE_SA1GL1C2_SAMPLEDELAY__SAMPLEDELAY_MASK                                                             0x0000003FL
42386 #define SE_SA1GL1C2_SAMPLEDELAY__RESERVED_MASK                                                                0xFFFFFFC0L
42387 //SE_SA1GL1C3_SAMPLEDELAY
42388 #define SE_SA1GL1C3_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                           0x0
42389 #define SE_SA1GL1C3_SAMPLEDELAY__RESERVED__SHIFT                                                              0x6
42390 #define SE_SA1GL1C3_SAMPLEDELAY__SAMPLEDELAY_MASK                                                             0x0000003FL
42391 #define SE_SA1GL1C3_SAMPLEDELAY__RESERVED_MASK                                                                0xFFFFFFC0L
42392 //SE_SA1WGP00TA0_SAMPLEDELAY
42393 #define SE_SA1WGP00TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42394 #define SE_SA1WGP00TA0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42395 #define SE_SA1WGP00TA0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42396 #define SE_SA1WGP00TA0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42397 //SE_SA1WGP00TA1_SAMPLEDELAY
42398 #define SE_SA1WGP00TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42399 #define SE_SA1WGP00TA1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42400 #define SE_SA1WGP00TA1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42401 #define SE_SA1WGP00TA1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42402 //SE_SA1WGP00TD0_SAMPLEDELAY
42403 #define SE_SA1WGP00TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42404 #define SE_SA1WGP00TD0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42405 #define SE_SA1WGP00TD0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42406 #define SE_SA1WGP00TD0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42407 //SE_SA1WGP00TD1_SAMPLEDELAY
42408 #define SE_SA1WGP00TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42409 #define SE_SA1WGP00TD1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42410 #define SE_SA1WGP00TD1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42411 #define SE_SA1WGP00TD1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42412 //SE_SA1WGP00TCP0_SAMPLEDELAY
42413 #define SE_SA1WGP00TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
42414 #define SE_SA1WGP00TCP0_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
42415 #define SE_SA1WGP00TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
42416 #define SE_SA1WGP00TCP0_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
42417 //SE_SA1WGP00TCP1_SAMPLEDELAY
42418 #define SE_SA1WGP00TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
42419 #define SE_SA1WGP00TCP1_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
42420 #define SE_SA1WGP00TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
42421 #define SE_SA1WGP00TCP1_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
42422 //SE_SA1WGP01TA0_SAMPLEDELAY
42423 #define SE_SA1WGP01TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42424 #define SE_SA1WGP01TA0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42425 #define SE_SA1WGP01TA0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42426 #define SE_SA1WGP01TA0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42427 //SE_SA1WGP01TA1_SAMPLEDELAY
42428 #define SE_SA1WGP01TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42429 #define SE_SA1WGP01TA1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42430 #define SE_SA1WGP01TA1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42431 #define SE_SA1WGP01TA1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42432 //SE_SA1WGP01TD0_SAMPLEDELAY
42433 #define SE_SA1WGP01TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42434 #define SE_SA1WGP01TD0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42435 #define SE_SA1WGP01TD0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42436 #define SE_SA1WGP01TD0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42437 //SE_SA1WGP01TD1_SAMPLEDELAY
42438 #define SE_SA1WGP01TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42439 #define SE_SA1WGP01TD1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42440 #define SE_SA1WGP01TD1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42441 #define SE_SA1WGP01TD1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42442 //SE_SA1WGP01TCP0_SAMPLEDELAY
42443 #define SE_SA1WGP01TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
42444 #define SE_SA1WGP01TCP0_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
42445 #define SE_SA1WGP01TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
42446 #define SE_SA1WGP01TCP0_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
42447 //SE_SA1WGP01TCP1_SAMPLEDELAY
42448 #define SE_SA1WGP01TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
42449 #define SE_SA1WGP01TCP1_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
42450 #define SE_SA1WGP01TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
42451 #define SE_SA1WGP01TCP1_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
42452 //SE_SA1WGP02TA0_SAMPLEDELAY
42453 #define SE_SA1WGP02TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42454 #define SE_SA1WGP02TA0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42455 #define SE_SA1WGP02TA0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42456 #define SE_SA1WGP02TA0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42457 //SE_SA1WGP02TA1_SAMPLEDELAY
42458 #define SE_SA1WGP02TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42459 #define SE_SA1WGP02TA1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42460 #define SE_SA1WGP02TA1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42461 #define SE_SA1WGP02TA1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42462 //SE_SA1WGP02TD0_SAMPLEDELAY
42463 #define SE_SA1WGP02TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42464 #define SE_SA1WGP02TD0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42465 #define SE_SA1WGP02TD0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42466 #define SE_SA1WGP02TD0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42467 //SE_SA1WGP02TD1_SAMPLEDELAY
42468 #define SE_SA1WGP02TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42469 #define SE_SA1WGP02TD1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42470 #define SE_SA1WGP02TD1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42471 #define SE_SA1WGP02TD1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42472 //SE_SA1WGP02TCP0_SAMPLEDELAY
42473 #define SE_SA1WGP02TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
42474 #define SE_SA1WGP02TCP0_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
42475 #define SE_SA1WGP02TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
42476 #define SE_SA1WGP02TCP0_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
42477 //SE_SA1WGP02TCP1_SAMPLEDELAY
42478 #define SE_SA1WGP02TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
42479 #define SE_SA1WGP02TCP1_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
42480 #define SE_SA1WGP02TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
42481 #define SE_SA1WGP02TCP1_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
42482 //SE_SA1WGP10TA0_SAMPLEDELAY
42483 #define SE_SA1WGP10TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42484 #define SE_SA1WGP10TA0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42485 #define SE_SA1WGP10TA0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42486 #define SE_SA1WGP10TA0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42487 //SE_SA1WGP10TA1_SAMPLEDELAY
42488 #define SE_SA1WGP10TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42489 #define SE_SA1WGP10TA1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42490 #define SE_SA1WGP10TA1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42491 #define SE_SA1WGP10TA1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42492 //SE_SA1WGP10TD0_SAMPLEDELAY
42493 #define SE_SA1WGP10TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42494 #define SE_SA1WGP10TD0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42495 #define SE_SA1WGP10TD0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42496 #define SE_SA1WGP10TD0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42497 //SE_SA1WGP10TD1_SAMPLEDELAY
42498 #define SE_SA1WGP10TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42499 #define SE_SA1WGP10TD1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42500 #define SE_SA1WGP10TD1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42501 #define SE_SA1WGP10TD1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42502 //SE_SA1WGP10TCP0_SAMPLEDELAY
42503 #define SE_SA1WGP10TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
42504 #define SE_SA1WGP10TCP0_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
42505 #define SE_SA1WGP10TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
42506 #define SE_SA1WGP10TCP0_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
42507 //SE_SA1WGP10TCP1_SAMPLEDELAY
42508 #define SE_SA1WGP10TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
42509 #define SE_SA1WGP10TCP1_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
42510 #define SE_SA1WGP10TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
42511 #define SE_SA1WGP10TCP1_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
42512 //SE_SA1WGP11TA0_SAMPLEDELAY
42513 #define SE_SA1WGP11TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42514 #define SE_SA1WGP11TA0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42515 #define SE_SA1WGP11TA0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42516 #define SE_SA1WGP11TA0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42517 //SE_SA1WGP11TA1_SAMPLEDELAY
42518 #define SE_SA1WGP11TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42519 #define SE_SA1WGP11TA1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42520 #define SE_SA1WGP11TA1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42521 #define SE_SA1WGP11TA1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42522 //SE_SA1WGP11TD0_SAMPLEDELAY
42523 #define SE_SA1WGP11TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42524 #define SE_SA1WGP11TD0_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42525 #define SE_SA1WGP11TD0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42526 #define SE_SA1WGP11TD0_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42527 //SE_SA1WGP11TD1_SAMPLEDELAY
42528 #define SE_SA1WGP11TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                        0x0
42529 #define SE_SA1WGP11TD1_SAMPLEDELAY__RESERVED__SHIFT                                                           0x6
42530 #define SE_SA1WGP11TD1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                          0x0000003FL
42531 #define SE_SA1WGP11TD1_SAMPLEDELAY__RESERVED_MASK                                                             0xFFFFFFC0L
42532 //SE_SA1WGP11TCP0_SAMPLEDELAY
42533 #define SE_SA1WGP11TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
42534 #define SE_SA1WGP11TCP0_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
42535 #define SE_SA1WGP11TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
42536 #define SE_SA1WGP11TCP0_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
42537 //SE_SA1WGP11TCP1_SAMPLEDELAY
42538 #define SE_SA1WGP11TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT                                                       0x0
42539 #define SE_SA1WGP11TCP1_SAMPLEDELAY__RESERVED__SHIFT                                                          0x6
42540 #define SE_SA1WGP11TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK                                                         0x0000003FL
42541 #define SE_SA1WGP11TCP1_SAMPLEDELAY__RESERVED_MASK                                                            0xFFFFFFC0L
42542 
42543 
42544 // addressBlock: sqind
42545 //SQ_WAVE_MODE
42546 #define SQ_WAVE_MODE__FP_ROUND__SHIFT                                                                         0x0
42547 #define SQ_WAVE_MODE__FP_DENORM__SHIFT                                                                        0x4
42548 #define SQ_WAVE_MODE__DX10_CLAMP__SHIFT                                                                       0x8
42549 #define SQ_WAVE_MODE__IEEE__SHIFT                                                                             0x9
42550 #define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT                                                                      0xa
42551 #define SQ_WAVE_MODE__EXCP_EN__SHIFT                                                                          0xc
42552 #define SQ_WAVE_MODE__FP16_OVFL__SHIFT                                                                        0x17
42553 #define SQ_WAVE_MODE__DISABLE_PERF__SHIFT                                                                     0x1b
42554 #define SQ_WAVE_MODE__VSKIP__SHIFT                                                                            0x1c
42555 #define SQ_WAVE_MODE__CSP__SHIFT                                                                              0x1d
42556 #define SQ_WAVE_MODE__FP_ROUND_MASK                                                                           0x0000000FL
42557 #define SQ_WAVE_MODE__FP_DENORM_MASK                                                                          0x000000F0L
42558 #define SQ_WAVE_MODE__DX10_CLAMP_MASK                                                                         0x00000100L
42559 #define SQ_WAVE_MODE__IEEE_MASK                                                                               0x00000200L
42560 #define SQ_WAVE_MODE__LOD_CLAMPED_MASK                                                                        0x00000400L
42561 #define SQ_WAVE_MODE__EXCP_EN_MASK                                                                            0x001FF000L
42562 #define SQ_WAVE_MODE__FP16_OVFL_MASK                                                                          0x00800000L
42563 #define SQ_WAVE_MODE__DISABLE_PERF_MASK                                                                       0x08000000L
42564 #define SQ_WAVE_MODE__VSKIP_MASK                                                                              0x10000000L
42565 #define SQ_WAVE_MODE__CSP_MASK                                                                                0xE0000000L
42566 //SQ_WAVE_STATUS
42567 #define SQ_WAVE_STATUS__SCC__SHIFT                                                                            0x0
42568 #define SQ_WAVE_STATUS__SPI_PRIO__SHIFT                                                                       0x1
42569 #define SQ_WAVE_STATUS__USER_PRIO__SHIFT                                                                      0x3
42570 #define SQ_WAVE_STATUS__PRIV__SHIFT                                                                           0x5
42571 #define SQ_WAVE_STATUS__TRAP_EN__SHIFT                                                                        0x6
42572 #define SQ_WAVE_STATUS__TTRACE_EN__SHIFT                                                                      0x7
42573 #define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT                                                                     0x8
42574 #define SQ_WAVE_STATUS__EXECZ__SHIFT                                                                          0x9
42575 #define SQ_WAVE_STATUS__VCCZ__SHIFT                                                                           0xa
42576 #define SQ_WAVE_STATUS__IN_TG__SHIFT                                                                          0xb
42577 #define SQ_WAVE_STATUS__IN_BARRIER__SHIFT                                                                     0xc
42578 #define SQ_WAVE_STATUS__HALT__SHIFT                                                                           0xd
42579 #define SQ_WAVE_STATUS__TRAP__SHIFT                                                                           0xe
42580 #define SQ_WAVE_STATUS__TTRACE_SIMD_EN__SHIFT                                                                 0xf
42581 #define SQ_WAVE_STATUS__VALID__SHIFT                                                                          0x10
42582 #define SQ_WAVE_STATUS__ECC_ERR__SHIFT                                                                        0x11
42583 #define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT                                                                    0x12
42584 #define SQ_WAVE_STATUS__PERF_EN__SHIFT                                                                        0x13
42585 #define SQ_WAVE_STATUS__FATAL_HALT__SHIFT                                                                     0x17
42586 #define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT                                                                    0x1b
42587 #define SQ_WAVE_STATUS__SCC_MASK                                                                              0x00000001L
42588 #define SQ_WAVE_STATUS__SPI_PRIO_MASK                                                                         0x00000006L
42589 #define SQ_WAVE_STATUS__USER_PRIO_MASK                                                                        0x00000018L
42590 #define SQ_WAVE_STATUS__PRIV_MASK                                                                             0x00000020L
42591 #define SQ_WAVE_STATUS__TRAP_EN_MASK                                                                          0x00000040L
42592 #define SQ_WAVE_STATUS__TTRACE_EN_MASK                                                                        0x00000080L
42593 #define SQ_WAVE_STATUS__EXPORT_RDY_MASK                                                                       0x00000100L
42594 #define SQ_WAVE_STATUS__EXECZ_MASK                                                                            0x00000200L
42595 #define SQ_WAVE_STATUS__VCCZ_MASK                                                                             0x00000400L
42596 #define SQ_WAVE_STATUS__IN_TG_MASK                                                                            0x00000800L
42597 #define SQ_WAVE_STATUS__IN_BARRIER_MASK                                                                       0x00001000L
42598 #define SQ_WAVE_STATUS__HALT_MASK                                                                             0x00002000L
42599 #define SQ_WAVE_STATUS__TRAP_MASK                                                                             0x00004000L
42600 #define SQ_WAVE_STATUS__TTRACE_SIMD_EN_MASK                                                                   0x00008000L
42601 #define SQ_WAVE_STATUS__VALID_MASK                                                                            0x00010000L
42602 #define SQ_WAVE_STATUS__ECC_ERR_MASK                                                                          0x00020000L
42603 #define SQ_WAVE_STATUS__SKIP_EXPORT_MASK                                                                      0x00040000L
42604 #define SQ_WAVE_STATUS__PERF_EN_MASK                                                                          0x00080000L
42605 #define SQ_WAVE_STATUS__FATAL_HALT_MASK                                                                       0x00800000L
42606 #define SQ_WAVE_STATUS__MUST_EXPORT_MASK                                                                      0x08000000L
42607 //SQ_WAVE_TRAPSTS
42608 #define SQ_WAVE_TRAPSTS__EXCP__SHIFT                                                                          0x0
42609 #define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT                                                                       0xa
42610 #define SQ_WAVE_TRAPSTS__ILLEGAL_INST__SHIFT                                                                  0xb
42611 #define SQ_WAVE_TRAPSTS__EXCP_HI__SHIFT                                                                       0xc
42612 #define SQ_WAVE_TRAPSTS__BUFFER_OOB__SHIFT                                                                    0xf
42613 #define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT                                                                    0x10
42614 #define SQ_WAVE_TRAPSTS__EXCP_GROUP_MASK__SHIFT                                                               0x14
42615 #define SQ_WAVE_TRAPSTS__EXCP_WAVE64HI__SHIFT                                                                 0x18
42616 #define SQ_WAVE_TRAPSTS__XNACK_ERROR__SHIFT                                                                   0x1c
42617 #define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT                                                                       0x1d
42618 #define SQ_WAVE_TRAPSTS__EXCP_MASK                                                                            0x000001FFL
42619 #define SQ_WAVE_TRAPSTS__SAVECTX_MASK                                                                         0x00000400L
42620 #define SQ_WAVE_TRAPSTS__ILLEGAL_INST_MASK                                                                    0x00000800L
42621 #define SQ_WAVE_TRAPSTS__EXCP_HI_MASK                                                                         0x00007000L
42622 #define SQ_WAVE_TRAPSTS__BUFFER_OOB_MASK                                                                      0x00008000L
42623 #define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK                                                                      0x000F0000L
42624 #define SQ_WAVE_TRAPSTS__EXCP_GROUP_MASK_MASK                                                                 0x00F00000L
42625 #define SQ_WAVE_TRAPSTS__EXCP_WAVE64HI_MASK                                                                   0x01000000L
42626 #define SQ_WAVE_TRAPSTS__XNACK_ERROR_MASK                                                                     0x10000000L
42627 #define SQ_WAVE_TRAPSTS__DP_RATE_MASK                                                                         0xE0000000L
42628 //SQ_WAVE_HW_ID_LEGACY
42629 #define SQ_WAVE_HW_ID_LEGACY__WAVE_ID__SHIFT                                                                  0x0
42630 #define SQ_WAVE_HW_ID_LEGACY__SIMD_ID__SHIFT                                                                  0x4
42631 #define SQ_WAVE_HW_ID_LEGACY__PIPE_ID__SHIFT                                                                  0x6
42632 #define SQ_WAVE_HW_ID_LEGACY__CU_ID__SHIFT                                                                    0x8
42633 #define SQ_WAVE_HW_ID_LEGACY__SH_ID__SHIFT                                                                    0xc
42634 #define SQ_WAVE_HW_ID_LEGACY__SE_ID__SHIFT                                                                    0xd
42635 #define SQ_WAVE_HW_ID_LEGACY__WAVE_ID_MSB__SHIFT                                                              0xf
42636 #define SQ_WAVE_HW_ID_LEGACY__TG_ID__SHIFT                                                                    0x10
42637 #define SQ_WAVE_HW_ID_LEGACY__VM_ID__SHIFT                                                                    0x14
42638 #define SQ_WAVE_HW_ID_LEGACY__QUEUE_ID__SHIFT                                                                 0x18
42639 #define SQ_WAVE_HW_ID_LEGACY__STATE_ID__SHIFT                                                                 0x1b
42640 #define SQ_WAVE_HW_ID_LEGACY__ME_ID__SHIFT                                                                    0x1e
42641 #define SQ_WAVE_HW_ID_LEGACY__WAVE_ID_MASK                                                                    0x0000000FL
42642 #define SQ_WAVE_HW_ID_LEGACY__SIMD_ID_MASK                                                                    0x00000030L
42643 #define SQ_WAVE_HW_ID_LEGACY__PIPE_ID_MASK                                                                    0x000000C0L
42644 #define SQ_WAVE_HW_ID_LEGACY__CU_ID_MASK                                                                      0x00000F00L
42645 #define SQ_WAVE_HW_ID_LEGACY__SH_ID_MASK                                                                      0x00001000L
42646 #define SQ_WAVE_HW_ID_LEGACY__SE_ID_MASK                                                                      0x00006000L
42647 #define SQ_WAVE_HW_ID_LEGACY__WAVE_ID_MSB_MASK                                                                0x00008000L
42648 #define SQ_WAVE_HW_ID_LEGACY__TG_ID_MASK                                                                      0x000F0000L
42649 #define SQ_WAVE_HW_ID_LEGACY__VM_ID_MASK                                                                      0x00F00000L
42650 #define SQ_WAVE_HW_ID_LEGACY__QUEUE_ID_MASK                                                                   0x07000000L
42651 #define SQ_WAVE_HW_ID_LEGACY__STATE_ID_MASK                                                                   0x38000000L
42652 #define SQ_WAVE_HW_ID_LEGACY__ME_ID_MASK                                                                      0xC0000000L
42653 //SQ_WAVE_GPR_ALLOC
42654 #define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT                                                                   0x0
42655 #define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT                                                                   0x8
42656 #define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT                                                                   0x10
42657 #define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT                                                                   0x18
42658 #define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK                                                                     0x000000FFL
42659 #define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK                                                                     0x0000FF00L
42660 #define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK                                                                     0x00FF0000L
42661 #define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK                                                                     0x0F000000L
42662 //SQ_WAVE_LDS_ALLOC
42663 #define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT                                                                    0x0
42664 #define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT                                                                    0xc
42665 #define SQ_WAVE_LDS_ALLOC__VGPR_SHARED_SIZE__SHIFT                                                            0x18
42666 #define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK                                                                      0x000001FFL
42667 #define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK                                                                      0x001FF000L
42668 #define SQ_WAVE_LDS_ALLOC__VGPR_SHARED_SIZE_MASK                                                              0x0F000000L
42669 //SQ_WAVE_IB_STS
42670 #define SQ_WAVE_IB_STS__VM_CNT__SHIFT                                                                         0x0
42671 #define SQ_WAVE_IB_STS__EXP_CNT__SHIFT                                                                        0x4
42672 #define SQ_WAVE_IB_STS__LGKM_CNT_BIT4__SHIFT                                                                  0x7
42673 #define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT                                                                       0x8
42674 #define SQ_WAVE_IB_STS__VALU_CNT__SHIFT                                                                       0xc
42675 #define SQ_WAVE_IB_STS__FIRST_REPLAY__SHIFT                                                                   0xf
42676 #define SQ_WAVE_IB_STS__RCNT__SHIFT                                                                           0x10
42677 #define SQ_WAVE_IB_STS__VM_CNT_HI__SHIFT                                                                      0x16
42678 #define SQ_WAVE_IB_STS__LGKM_CNT_BIT5__SHIFT                                                                  0x18
42679 #define SQ_WAVE_IB_STS__REPLAY_W64H__SHIFT                                                                    0x19
42680 #define SQ_WAVE_IB_STS__VS_CNT__SHIFT                                                                         0x1a
42681 #define SQ_WAVE_IB_STS__VM_CNT_MASK                                                                           0x0000000FL
42682 #define SQ_WAVE_IB_STS__EXP_CNT_MASK                                                                          0x00000070L
42683 #define SQ_WAVE_IB_STS__LGKM_CNT_BIT4_MASK                                                                    0x00000080L
42684 #define SQ_WAVE_IB_STS__LGKM_CNT_MASK                                                                         0x00000F00L
42685 #define SQ_WAVE_IB_STS__VALU_CNT_MASK                                                                         0x00007000L
42686 #define SQ_WAVE_IB_STS__FIRST_REPLAY_MASK                                                                     0x00008000L
42687 #define SQ_WAVE_IB_STS__RCNT_MASK                                                                             0x003F0000L
42688 #define SQ_WAVE_IB_STS__VM_CNT_HI_MASK                                                                        0x00C00000L
42689 #define SQ_WAVE_IB_STS__LGKM_CNT_BIT5_MASK                                                                    0x01000000L
42690 #define SQ_WAVE_IB_STS__REPLAY_W64H_MASK                                                                      0x02000000L
42691 #define SQ_WAVE_IB_STS__VS_CNT_MASK                                                                           0xFC000000L
42692 //SQ_WAVE_PC_LO
42693 #define SQ_WAVE_PC_LO__PC_LO__SHIFT                                                                           0x0
42694 #define SQ_WAVE_PC_LO__PC_LO_MASK                                                                             0xFFFFFFFFL
42695 //SQ_WAVE_PC_HI
42696 #define SQ_WAVE_PC_HI__PC_HI__SHIFT                                                                           0x0
42697 #define SQ_WAVE_PC_HI__PC_HI_MASK                                                                             0x0000FFFFL
42698 //SQ_WAVE_INST_DW0
42699 #define SQ_WAVE_INST_DW0__INST_DW0__SHIFT                                                                     0x0
42700 #define SQ_WAVE_INST_DW0__INST_DW0_MASK                                                                       0xFFFFFFFFL
42701 //SQ_WAVE_IB_DBG1
42702 #define SQ_WAVE_IB_DBG1__XNACK_ERROR__SHIFT                                                                   0x0
42703 #define SQ_WAVE_IB_DBG1__XNACK__SHIFT                                                                         0x1
42704 #define SQ_WAVE_IB_DBG1__TA_NEED_RESET__SHIFT                                                                 0x2
42705 #define SQ_WAVE_IB_DBG1__XNACK_OVERRIDE__SHIFT                                                                0x3
42706 #define SQ_WAVE_IB_DBG1__XCNT__SHIFT                                                                          0x4
42707 #define SQ_WAVE_IB_DBG1__QCNT__SHIFT                                                                          0xb
42708 #define SQ_WAVE_IB_DBG1__RCNT__SHIFT                                                                          0x12
42709 #define SQ_WAVE_IB_DBG1__WAVE_IDLE__SHIFT                                                                     0x18
42710 #define SQ_WAVE_IB_DBG1__MISC_CNT__SHIFT                                                                      0x19
42711 #define SQ_WAVE_IB_DBG1__XNACK_ERROR_MASK                                                                     0x00000001L
42712 #define SQ_WAVE_IB_DBG1__XNACK_MASK                                                                           0x00000002L
42713 #define SQ_WAVE_IB_DBG1__TA_NEED_RESET_MASK                                                                   0x00000004L
42714 #define SQ_WAVE_IB_DBG1__XNACK_OVERRIDE_MASK                                                                  0x00000008L
42715 #define SQ_WAVE_IB_DBG1__XCNT_MASK                                                                            0x000003F0L
42716 #define SQ_WAVE_IB_DBG1__QCNT_MASK                                                                            0x0001F800L
42717 #define SQ_WAVE_IB_DBG1__RCNT_MASK                                                                            0x00FC0000L
42718 #define SQ_WAVE_IB_DBG1__WAVE_IDLE_MASK                                                                       0x01000000L
42719 #define SQ_WAVE_IB_DBG1__MISC_CNT_MASK                                                                        0xFE000000L
42720 //SQ_WAVE_FLUSH_IB
42721 #define SQ_WAVE_FLUSH_IB__UNUSED__SHIFT                                                                       0x0
42722 #define SQ_WAVE_FLUSH_IB__UNUSED_MASK                                                                         0xFFFFFFFFL
42723 //SQ_WAVE_HW_ID1
42724 #define SQ_WAVE_HW_ID1__WAVE_ID__SHIFT                                                                        0x0
42725 #define SQ_WAVE_HW_ID1__SIMD_ID__SHIFT                                                                        0x8
42726 #define SQ_WAVE_HW_ID1__WGP_ID__SHIFT                                                                         0xa
42727 #define SQ_WAVE_HW_ID1__SA_ID__SHIFT                                                                          0x10
42728 #define SQ_WAVE_HW_ID1__SE_ID__SHIFT                                                                          0x12
42729 #define SQ_WAVE_HW_ID1__WAVE_ID_MASK                                                                          0x0000001FL
42730 #define SQ_WAVE_HW_ID1__SIMD_ID_MASK                                                                          0x00000300L
42731 #define SQ_WAVE_HW_ID1__WGP_ID_MASK                                                                           0x00003C00L
42732 #define SQ_WAVE_HW_ID1__SA_ID_MASK                                                                            0x00010000L
42733 #define SQ_WAVE_HW_ID1__SE_ID_MASK                                                                            0x000C0000L
42734 //SQ_WAVE_HW_ID2
42735 #define SQ_WAVE_HW_ID2__QUEUE_ID__SHIFT                                                                       0x0
42736 #define SQ_WAVE_HW_ID2__PIPE_ID__SHIFT                                                                        0x4
42737 #define SQ_WAVE_HW_ID2__ME_ID__SHIFT                                                                          0x8
42738 #define SQ_WAVE_HW_ID2__STATE_ID__SHIFT                                                                       0xc
42739 #define SQ_WAVE_HW_ID2__WG_ID__SHIFT                                                                          0x10
42740 #define SQ_WAVE_HW_ID2__VM_ID__SHIFT                                                                          0x18
42741 #define SQ_WAVE_HW_ID2__COMPAT_LEVEL__SHIFT                                                                   0x1d
42742 #define SQ_WAVE_HW_ID2__QUEUE_ID_MASK                                                                         0x0000000FL
42743 #define SQ_WAVE_HW_ID2__PIPE_ID_MASK                                                                          0x00000030L
42744 #define SQ_WAVE_HW_ID2__ME_ID_MASK                                                                            0x00000300L
42745 #define SQ_WAVE_HW_ID2__STATE_ID_MASK                                                                         0x00007000L
42746 #define SQ_WAVE_HW_ID2__WG_ID_MASK                                                                            0x001F0000L
42747 #define SQ_WAVE_HW_ID2__VM_ID_MASK                                                                            0x0F000000L
42748 #define SQ_WAVE_HW_ID2__COMPAT_LEVEL_MASK                                                                     0x60000000L
42749 //SQ_WAVE_POPS_PACKER
42750 #define SQ_WAVE_POPS_PACKER__POPS_EN__SHIFT                                                                   0x0
42751 #define SQ_WAVE_POPS_PACKER__POPS_PACKER_ID__SHIFT                                                            0x1
42752 #define SQ_WAVE_POPS_PACKER__POPS_EN_MASK                                                                     0x00000001L
42753 #define SQ_WAVE_POPS_PACKER__POPS_PACKER_ID_MASK                                                              0x00000006L
42754 //SQ_WAVE_SCHED_MODE
42755 #define SQ_WAVE_SCHED_MODE__DEP_MODE__SHIFT                                                                   0x0
42756 #define SQ_WAVE_SCHED_MODE__DEP_MODE_MASK                                                                     0x00000003L
42757 //SQ_WAVE_VGPR_OFFSET
42758 #define SQ_WAVE_VGPR_OFFSET__SRC0__SHIFT                                                                      0x0
42759 #define SQ_WAVE_VGPR_OFFSET__SRC1__SHIFT                                                                      0x6
42760 #define SQ_WAVE_VGPR_OFFSET__SRC2__SHIFT                                                                      0xc
42761 #define SQ_WAVE_VGPR_OFFSET__DST__SHIFT                                                                       0x12
42762 #define SQ_WAVE_VGPR_OFFSET__SRC0_MASK                                                                        0x0000003FL
42763 #define SQ_WAVE_VGPR_OFFSET__SRC1_MASK                                                                        0x00000FC0L
42764 #define SQ_WAVE_VGPR_OFFSET__SRC2_MASK                                                                        0x0003F000L
42765 #define SQ_WAVE_VGPR_OFFSET__DST_MASK                                                                         0x00FC0000L
42766 //SQ_WAVE_IB_STS2
42767 #define SQ_WAVE_IB_STS2__INST_PREFETCH__SHIFT                                                                 0x0
42768 #define SQ_WAVE_IB_STS2__RESOURCE_OVERRIDE__SHIFT                                                             0x7
42769 #define SQ_WAVE_IB_STS2__MEM_ORDER__SHIFT                                                                     0x8
42770 #define SQ_WAVE_IB_STS2__FWD_PROGRESS__SHIFT                                                                  0xa
42771 #define SQ_WAVE_IB_STS2__WAVE64__SHIFT                                                                        0xb
42772 #define SQ_WAVE_IB_STS2__WAVE64HI__SHIFT                                                                      0xc
42773 #define SQ_WAVE_IB_STS2__SUBV_LOOP__SHIFT                                                                     0xd
42774 #define SQ_WAVE_IB_STS2__INST_PREFETCH_MASK                                                                   0x00000003L
42775 #define SQ_WAVE_IB_STS2__RESOURCE_OVERRIDE_MASK                                                               0x00000080L
42776 #define SQ_WAVE_IB_STS2__MEM_ORDER_MASK                                                                       0x00000300L
42777 #define SQ_WAVE_IB_STS2__FWD_PROGRESS_MASK                                                                    0x00000400L
42778 #define SQ_WAVE_IB_STS2__WAVE64_MASK                                                                          0x00000800L
42779 #define SQ_WAVE_IB_STS2__WAVE64HI_MASK                                                                        0x00001000L
42780 #define SQ_WAVE_IB_STS2__SUBV_LOOP_MASK                                                                       0x00002000L
42781 //SQ_WAVE_TTMP0
42782 #define SQ_WAVE_TTMP0__DATA__SHIFT                                                                            0x0
42783 #define SQ_WAVE_TTMP0__DATA_MASK                                                                              0xFFFFFFFFL
42784 //SQ_WAVE_TTMP1
42785 #define SQ_WAVE_TTMP1__DATA__SHIFT                                                                            0x0
42786 #define SQ_WAVE_TTMP1__DATA_MASK                                                                              0xFFFFFFFFL
42787 //SQ_WAVE_TTMP2
42788 #define SQ_WAVE_TTMP2__DATA__SHIFT                                                                            0x0
42789 #define SQ_WAVE_TTMP2__DATA_MASK                                                                              0xFFFFFFFFL
42790 //SQ_WAVE_TTMP3
42791 #define SQ_WAVE_TTMP3__DATA__SHIFT                                                                            0x0
42792 #define SQ_WAVE_TTMP3__DATA_MASK                                                                              0xFFFFFFFFL
42793 //SQ_WAVE_TTMP4
42794 #define SQ_WAVE_TTMP4__DATA__SHIFT                                                                            0x0
42795 #define SQ_WAVE_TTMP4__DATA_MASK                                                                              0xFFFFFFFFL
42796 //SQ_WAVE_TTMP5
42797 #define SQ_WAVE_TTMP5__DATA__SHIFT                                                                            0x0
42798 #define SQ_WAVE_TTMP5__DATA_MASK                                                                              0xFFFFFFFFL
42799 //SQ_WAVE_TTMP6
42800 #define SQ_WAVE_TTMP6__DATA__SHIFT                                                                            0x0
42801 #define SQ_WAVE_TTMP6__DATA_MASK                                                                              0xFFFFFFFFL
42802 //SQ_WAVE_TTMP7
42803 #define SQ_WAVE_TTMP7__DATA__SHIFT                                                                            0x0
42804 #define SQ_WAVE_TTMP7__DATA_MASK                                                                              0xFFFFFFFFL
42805 //SQ_WAVE_TTMP8
42806 #define SQ_WAVE_TTMP8__DATA__SHIFT                                                                            0x0
42807 #define SQ_WAVE_TTMP8__DATA_MASK                                                                              0xFFFFFFFFL
42808 //SQ_WAVE_TTMP9
42809 #define SQ_WAVE_TTMP9__DATA__SHIFT                                                                            0x0
42810 #define SQ_WAVE_TTMP9__DATA_MASK                                                                              0xFFFFFFFFL
42811 //SQ_WAVE_TTMP10
42812 #define SQ_WAVE_TTMP10__DATA__SHIFT                                                                           0x0
42813 #define SQ_WAVE_TTMP10__DATA_MASK                                                                             0xFFFFFFFFL
42814 //SQ_WAVE_TTMP11
42815 #define SQ_WAVE_TTMP11__DATA__SHIFT                                                                           0x0
42816 #define SQ_WAVE_TTMP11__DATA_MASK                                                                             0xFFFFFFFFL
42817 //SQ_WAVE_TTMP12
42818 #define SQ_WAVE_TTMP12__DATA__SHIFT                                                                           0x0
42819 #define SQ_WAVE_TTMP12__DATA_MASK                                                                             0xFFFFFFFFL
42820 //SQ_WAVE_TTMP13
42821 #define SQ_WAVE_TTMP13__DATA__SHIFT                                                                           0x0
42822 #define SQ_WAVE_TTMP13__DATA_MASK                                                                             0xFFFFFFFFL
42823 //SQ_WAVE_TTMP14
42824 #define SQ_WAVE_TTMP14__DATA__SHIFT                                                                           0x0
42825 #define SQ_WAVE_TTMP14__DATA_MASK                                                                             0xFFFFFFFFL
42826 //SQ_WAVE_TTMP15
42827 #define SQ_WAVE_TTMP15__DATA__SHIFT                                                                           0x0
42828 #define SQ_WAVE_TTMP15__DATA_MASK                                                                             0xFFFFFFFFL
42829 //SQ_WAVE_M0
42830 #define SQ_WAVE_M0__M0__SHIFT                                                                                 0x0
42831 #define SQ_WAVE_M0__M0_MASK                                                                                   0xFFFFFFFFL
42832 //SQ_WAVE_EXEC_LO
42833 #define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT                                                                       0x0
42834 #define SQ_WAVE_EXEC_LO__EXEC_LO_MASK                                                                         0xFFFFFFFFL
42835 //SQ_WAVE_EXEC_HI
42836 #define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT                                                                       0x0
42837 #define SQ_WAVE_EXEC_HI__EXEC_HI_MASK                                                                         0xFFFFFFFFL
42838 //SQ_WAVE_FLAT_SCRATCH_LO
42839 #define SQ_WAVE_FLAT_SCRATCH_LO__DATA__SHIFT                                                                  0x0
42840 #define SQ_WAVE_FLAT_SCRATCH_LO__DATA_MASK                                                                    0xFFFFFFFFL
42841 //SQ_WAVE_FLAT_SCRATCH_HI
42842 #define SQ_WAVE_FLAT_SCRATCH_HI__DATA__SHIFT                                                                  0x0
42843 #define SQ_WAVE_FLAT_SCRATCH_HI__DATA_MASK                                                                    0xFFFFFFFFL
42844 //SQ_WAVE_FLAT_XNACK_MASK
42845 #define SQ_WAVE_FLAT_XNACK_MASK__MASK__SHIFT                                                                  0x0
42846 #define SQ_WAVE_FLAT_XNACK_MASK__MASK_MASK                                                                    0xFFFFFFFFL
42847 //SQ_INTERRUPT_WORD_AUTO
42848 #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE__SHIFT                                                           0x0
42849 #define SQ_INTERRUPT_WORD_AUTO__WLT__SHIFT                                                                    0x1
42850 #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF0_FULL__SHIFT                                                 0x2
42851 #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF1_FULL__SHIFT                                                 0x3
42852 #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_UTC_ERROR__SHIFT                                                 0x8
42853 #define SQ_INTERRUPT_WORD_AUTO__SE_ID__SHIFT                                                                  0x24
42854 #define SQ_INTERRUPT_WORD_AUTO__ENCODING__SHIFT                                                               0x26
42855 #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_MASK                                                             0x0000000001L
42856 #define SQ_INTERRUPT_WORD_AUTO__WLT_MASK                                                                      0x0000000002L
42857 #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF0_FULL_MASK                                                   0x0000000004L
42858 #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF1_FULL_MASK                                                   0x0000000008L
42859 #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_UTC_ERROR_MASK                                                   0x0000000100L
42860 #define SQ_INTERRUPT_WORD_AUTO__SE_ID_MASK                                                                    0x3000000000L
42861 #define SQ_INTERRUPT_WORD_AUTO__ENCODING_MASK                                                                 0xC000000000L
42862 //SQ_INTERRUPT_WORD_ERROR
42863 #define SQ_INTERRUPT_WORD_ERROR__ERR_DETAIL__SHIFT                                                            0x0
42864 #define SQ_INTERRUPT_WORD_ERROR__ERR_TYPE__SHIFT                                                              0x13
42865 #define SQ_INTERRUPT_WORD_ERROR__SA_ID__SHIFT                                                                 0x17
42866 #define SQ_INTERRUPT_WORD_ERROR__PRIV__SHIFT                                                                  0x18
42867 #define SQ_INTERRUPT_WORD_ERROR__WAVE_ID__SHIFT                                                               0x19
42868 #define SQ_INTERRUPT_WORD_ERROR__SIMD_ID__SHIFT                                                               0x1e
42869 #define SQ_INTERRUPT_WORD_ERROR__WGP_ID__SHIFT                                                                0x20
42870 #define SQ_INTERRUPT_WORD_ERROR__SE_ID__SHIFT                                                                 0x24
42871 #define SQ_INTERRUPT_WORD_ERROR__ENCODING__SHIFT                                                              0x26
42872 #define SQ_INTERRUPT_WORD_ERROR__ERR_DETAIL_MASK                                                              0x000007FFFFL
42873 #define SQ_INTERRUPT_WORD_ERROR__ERR_TYPE_MASK                                                                0x0000780000L
42874 #define SQ_INTERRUPT_WORD_ERROR__SA_ID_MASK                                                                   0x0000800000L
42875 #define SQ_INTERRUPT_WORD_ERROR__PRIV_MASK                                                                    0x0001000000L
42876 #define SQ_INTERRUPT_WORD_ERROR__WAVE_ID_MASK                                                                 0x003E000000L
42877 #define SQ_INTERRUPT_WORD_ERROR__SIMD_ID_MASK                                                                 0x00C0000000L
42878 #define SQ_INTERRUPT_WORD_ERROR__WGP_ID_MASK                                                                  0x0F00000000L
42879 #define SQ_INTERRUPT_WORD_ERROR__SE_ID_MASK                                                                   0x3000000000L
42880 #define SQ_INTERRUPT_WORD_ERROR__ENCODING_MASK                                                                0xC000000000L
42881 //SQ_INTERRUPT_WORD_WAVE
42882 #define SQ_INTERRUPT_WORD_WAVE__DATA__SHIFT                                                                   0x0
42883 #define SQ_INTERRUPT_WORD_WAVE__SA_ID__SHIFT                                                                  0x17
42884 #define SQ_INTERRUPT_WORD_WAVE__PRIV__SHIFT                                                                   0x18
42885 #define SQ_INTERRUPT_WORD_WAVE__WAVE_ID__SHIFT                                                                0x19
42886 #define SQ_INTERRUPT_WORD_WAVE__SIMD_ID__SHIFT                                                                0x1e
42887 #define SQ_INTERRUPT_WORD_WAVE__WGP_ID__SHIFT                                                                 0x20
42888 #define SQ_INTERRUPT_WORD_WAVE__SE_ID__SHIFT                                                                  0x24
42889 #define SQ_INTERRUPT_WORD_WAVE__ENCODING__SHIFT                                                               0x26
42890 #define SQ_INTERRUPT_WORD_WAVE__DATA_MASK                                                                     0x00007FFFFFL
42891 #define SQ_INTERRUPT_WORD_WAVE__SA_ID_MASK                                                                    0x0000800000L
42892 #define SQ_INTERRUPT_WORD_WAVE__PRIV_MASK                                                                     0x0001000000L
42893 #define SQ_INTERRUPT_WORD_WAVE__WAVE_ID_MASK                                                                  0x003E000000L
42894 #define SQ_INTERRUPT_WORD_WAVE__SIMD_ID_MASK                                                                  0x00C0000000L
42895 #define SQ_INTERRUPT_WORD_WAVE__WGP_ID_MASK                                                                   0x0F00000000L
42896 #define SQ_INTERRUPT_WORD_WAVE__SE_ID_MASK                                                                    0x3000000000L
42897 #define SQ_INTERRUPT_WORD_WAVE__ENCODING_MASK                                                                 0xC000000000L
42898 
42899 
42900 
42901 
42902 
42903 
42904 // addressBlock: didtind
42905 //DIDT_SQ_CTRL0
42906 #define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT                                                                    0x0
42907 #define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT                                                                    0x1
42908 #define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT                                                                   0x3
42909 #define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT                                                            0x4
42910 #define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN__SHIFT                                                              0x5
42911 #define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT                                                             0x6
42912 #define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT                                                      0x7
42913 #define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT                                                         0x8
42914 #define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN__SHIFT                                                                0x18
42915 #define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN__SHIFT                                                             0x19
42916 #define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT                                                  0x1a
42917 #define DIDT_SQ_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT                                                         0x1b
42918 #define DIDT_SQ_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT                                                        0x1c
42919 #define DIDT_SQ_CTRL0__DIDT_THROTTLE_MODE__SHIFT                                                              0x1d
42920 #define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK                                                                      0x00000001L
42921 #define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK                                                                      0x00000006L
42922 #define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK                                                                     0x00000008L
42923 #define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK                                                              0x00000010L
42924 #define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN_MASK                                                                0x00000020L
42925 #define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN_MASK                                                               0x00000040L
42926 #define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK                                                        0x00000080L
42927 #define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK                                                           0x00FFFF00L
42928 #define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN_MASK                                                                  0x01000000L
42929 #define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN_MASK                                                               0x02000000L
42930 #define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK                                                    0x04000000L
42931 #define DIDT_SQ_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK                                                           0x08000000L
42932 #define DIDT_SQ_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK                                                          0x10000000L
42933 #define DIDT_SQ_CTRL0__DIDT_THROTTLE_MODE_MASK                                                                0x20000000L
42934 //DIDT_SQ_CTRL1
42935 #define DIDT_SQ_CTRL1__MIN_POWER__SHIFT                                                                       0x0
42936 #define DIDT_SQ_CTRL1__MAX_POWER__SHIFT                                                                       0x10
42937 #define DIDT_SQ_CTRL1__MIN_POWER_MASK                                                                         0x0000FFFFL
42938 #define DIDT_SQ_CTRL1__MAX_POWER_MASK                                                                         0xFFFF0000L
42939 //DIDT_SQ_CTRL2
42940 #define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT                                                                 0x0
42941 #define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT                                                        0x10
42942 #define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT                                                        0x1b
42943 #define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK                                                                   0x00003FFFL
42944 #define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK                                                          0x03FF0000L
42945 #define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK                                                          0x78000000L
42946 //DIDT_SQ_CTRL_OCP
42947 #define DIDT_SQ_CTRL_OCP__OCP_MAX_POWER__SHIFT                                                                0x0
42948 #define DIDT_SQ_CTRL_OCP__OCP_MAX_POWER_MASK                                                                  0x0000FFFFL
42949 //DIDT_SQ_STALL_CTRL
42950 #define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT                                                        0x0
42951 #define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT                                                        0x6
42952 #define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT                                                 0xc
42953 #define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT                                                 0x12
42954 #define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK                                                          0x0000003FL
42955 #define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK                                                          0x00000FC0L
42956 #define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK                                                   0x0003F000L
42957 #define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK                                                   0x00FC0000L
42958 //DIDT_SQ_TUNING_CTRL
42959 #define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT                                                        0x0
42960 #define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT                                                        0xe
42961 #define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK                                                          0x00003FFFL
42962 #define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK                                                          0x0FFFC000L
42963 //DIDT_SQ_STALL_AUTO_RELEASE_CTRL
42964 #define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT                                  0x0
42965 #define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK                                    0x00FFFFFFL
42966 //DIDT_SQ_CTRL3
42967 #define DIDT_SQ_CTRL3__GC_DIDT_ENABLE__SHIFT                                                                  0x0
42968 #define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT                                                         0x1
42969 #define DIDT_SQ_CTRL3__THROTTLE_POLICY__SHIFT                                                                 0x2
42970 #define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                    0x4
42971 #define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT                                                         0x9
42972 #define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT                                                     0xe
42973 #define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT                                                           0x16
42974 #define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT                                                           0x17
42975 #define DIDT_SQ_CTRL3__QUALIFY_STALL_EN__SHIFT                                                                0x18
42976 #define DIDT_SQ_CTRL3__DIDT_STALL_SEL__SHIFT                                                                  0x19
42977 #define DIDT_SQ_CTRL3__DIDT_FORCE_STALL__SHIFT                                                                0x1b
42978 #define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN__SHIFT                                                             0x1c
42979 #define DIDT_SQ_CTRL3__GC_DIDT_ENABLE_MASK                                                                    0x00000001L
42980 #define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK                                                           0x00000002L
42981 #define DIDT_SQ_CTRL3__THROTTLE_POLICY_MASK                                                                   0x0000000CL
42982 #define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK                                                      0x000001F0L
42983 #define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK                                                           0x00003E00L
42984 #define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK                                                       0x003FC000L
42985 #define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK                                                             0x00400000L
42986 #define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK                                                             0x00800000L
42987 #define DIDT_SQ_CTRL3__QUALIFY_STALL_EN_MASK                                                                  0x01000000L
42988 #define DIDT_SQ_CTRL3__DIDT_STALL_SEL_MASK                                                                    0x06000000L
42989 #define DIDT_SQ_CTRL3__DIDT_FORCE_STALL_MASK                                                                  0x08000000L
42990 #define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN_MASK                                                               0x10000000L
42991 //DIDT_SQ_STALL_PATTERN_1_2
42992 #define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT                                                0x0
42993 #define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT                                                0x10
42994 #define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK                                                  0x00007FFFL
42995 #define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK                                                  0x7FFF0000L
42996 //DIDT_SQ_STALL_PATTERN_3_4
42997 #define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT                                                0x0
42998 #define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT                                                0x10
42999 #define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK                                                  0x00007FFFL
43000 #define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK                                                  0x7FFF0000L
43001 //DIDT_SQ_STALL_PATTERN_5_6
43002 #define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT                                                0x0
43003 #define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT                                                0x10
43004 #define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK                                                  0x00007FFFL
43005 #define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK                                                  0x7FFF0000L
43006 //DIDT_SQ_STALL_PATTERN_7
43007 #define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT                                                  0x0
43008 #define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK                                                    0x00007FFFL
43009 //DIDT_SQ_MPD_SCALE_FACTOR
43010 #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT                                               0x0
43011 #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT                                               0x4
43012 #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT                                               0x8
43013 #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT                                               0xc
43014 #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT                                                     0x10
43015 #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT                                                     0x14
43016 #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT                                                     0x18
43017 #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT                                                     0x1c
43018 #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK                                                 0x0000000FL
43019 #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK                                                 0x000000F0L
43020 #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK                                                 0x00000F00L
43021 #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK                                                 0x0000F000L
43022 #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK                                                       0x000F0000L
43023 #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK                                                       0x00F00000L
43024 #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK                                                       0x0F000000L
43025 #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK                                                       0xF0000000L
43026 //DIDT_SQ_STALL_RELEASE_CNTL0
43027 #define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN__SHIFT                                        0x0
43028 #define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT                                               0x1
43029 #define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT                                             0x2
43030 #define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT                                             0xd
43031 #define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN_MASK                                          0x00000001L
43032 #define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL_MASK                                                 0x00000002L
43033 #define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK                                               0x00001FFCL
43034 #define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK                                               0x00FFE000L
43035 //DIDT_SQ_STALL_RELEASE_CNTL1
43036 #define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT                                      0x0
43037 #define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT                                      0x5
43038 #define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT                                      0xa
43039 #define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT                                      0xf
43040 #define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK                                        0x0000001FL
43041 #define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK                                        0x000003E0L
43042 #define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK                                        0x00007C00L
43043 #define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK                                        0x000F8000L
43044 //DIDT_SQ_STALL_RELEASE_CNTL_STATUS
43045 #define DIDT_SQ_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE__SHIFT                           0x0
43046 #define DIDT_SQ_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE_MASK                             0x00000003L
43047 //DIDT_SQ_WEIGHT0_3
43048 #define DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT                                                                     0x0
43049 #define DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT                                                                     0x8
43050 #define DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT                                                                     0x10
43051 #define DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT                                                                     0x18
43052 #define DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK                                                                       0x000000FFL
43053 #define DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK                                                                       0x0000FF00L
43054 #define DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK                                                                       0x00FF0000L
43055 #define DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK                                                                       0xFF000000L
43056 //DIDT_SQ_WEIGHT4_7
43057 #define DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT                                                                     0x0
43058 #define DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT                                                                     0x8
43059 #define DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT                                                                     0x10
43060 #define DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT                                                                     0x18
43061 #define DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK                                                                       0x000000FFL
43062 #define DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK                                                                       0x0000FF00L
43063 #define DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK                                                                       0x00FF0000L
43064 #define DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK                                                                       0xFF000000L
43065 //DIDT_SQ_WEIGHT8_11
43066 #define DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT                                                                    0x0
43067 #define DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT                                                                    0x8
43068 #define DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT                                                                   0x10
43069 #define DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT                                                                   0x18
43070 #define DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK                                                                      0x000000FFL
43071 #define DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK                                                                      0x0000FF00L
43072 #define DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK                                                                     0x00FF0000L
43073 #define DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK                                                                     0xFF000000L
43074 //DIDT_SQ_EDC_CTRL
43075 #define DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT                                                                       0x0
43076 #define DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT                                                                   0x1
43077 #define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT                                                          0x2
43078 #define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT                                                              0x3
43079 #define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                  0x4
43080 #define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT                                                   0x9
43081 #define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT                                                     0x11
43082 #define DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT                                                                    0x12
43083 #define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT                                                          0x13
43084 #define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT                                                         0x15
43085 #define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT                                                         0x16
43086 #define DIDT_SQ_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT                                                           0x17
43087 #define DIDT_SQ_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN__SHIFT                                                 0x18
43088 #define DIDT_SQ_EDC_CTRL__EDC_EN_MASK                                                                         0x00000001L
43089 #define DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK                                                                     0x00000002L
43090 #define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK                                                            0x00000004L
43091 #define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK                                                                0x00000008L
43092 #define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK                                                    0x000001F0L
43093 #define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK                                                     0x0001FE00L
43094 #define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK                                                       0x00020000L
43095 #define DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK                                                                      0x00040000L
43096 #define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK                                                            0x00180000L
43097 #define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK                                                           0x00200000L
43098 #define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK                                                           0x00400000L
43099 #define DIDT_SQ_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK                                                             0x00800000L
43100 #define DIDT_SQ_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN_MASK                                                   0x01000000L
43101 //DIDT_SQ_EDC_THRESHOLD
43102 #define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT                                                           0x0
43103 #define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD_MASK                                                             0xFFFFFFFFL
43104 //DIDT_SQ_EDC_STALL_PATTERN_1_2
43105 #define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT                                             0x0
43106 #define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT                                             0x10
43107 #define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK                                               0x00007FFFL
43108 #define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK                                               0x7FFF0000L
43109 //DIDT_SQ_EDC_STALL_PATTERN_3_4
43110 #define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT                                             0x0
43111 #define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT                                             0x10
43112 #define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK                                               0x00007FFFL
43113 #define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK                                               0x7FFF0000L
43114 //DIDT_SQ_EDC_STALL_PATTERN_5_6
43115 #define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT                                             0x0
43116 #define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT                                             0x10
43117 #define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK                                               0x00007FFFL
43118 #define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK                                               0x7FFF0000L
43119 //DIDT_SQ_EDC_STALL_PATTERN_7
43120 #define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT                                               0x0
43121 #define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK                                                 0x00007FFFL
43122 //DIDT_SQ_EDC_TIMER_PERIOD
43123 #define DIDT_SQ_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD__SHIFT                                                     0x0
43124 #define DIDT_SQ_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD_MASK                                                       0x00003FFFL
43125 //DIDT_SQ_THROTTLE_CTRL
43126 #define DIDT_SQ_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT                                                         0x0
43127 #define DIDT_SQ_THROTTLE_CTRL__PCC_STALL_EN__SHIFT                                                            0x1
43128 #define DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT                                                         0x2
43129 #define DIDT_SQ_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT                                                        0x3
43130 #define DIDT_SQ_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK                                                           0x00000001L
43131 #define DIDT_SQ_THROTTLE_CTRL__PCC_STALL_EN_MASK                                                              0x00000002L
43132 #define DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK                                                           0x00000004L
43133 #define DIDT_SQ_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK                                                          0x00000008L
43134 //DIDT_SQ_EDC_STALL_DELAY_1
43135 #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0__SHIFT                                                 0x0
43136 #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1__SHIFT                                                 0x6
43137 #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2__SHIFT                                                 0xc
43138 #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3__SHIFT                                                 0x12
43139 #define DIDT_SQ_EDC_STALL_DELAY_1__UNUSED__SHIFT                                                              0x18
43140 #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0_MASK                                                   0x0000003FL
43141 #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1_MASK                                                   0x00000FC0L
43142 #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2_MASK                                                   0x0003F000L
43143 #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3_MASK                                                   0x00FC0000L
43144 #define DIDT_SQ_EDC_STALL_DELAY_1__UNUSED_MASK                                                                0xFF000000L
43145 //DIDT_SQ_EDC_STALL_DELAY_2
43146 #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4__SHIFT                                                 0x0
43147 #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5__SHIFT                                                 0x6
43148 #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6__SHIFT                                                 0xc
43149 #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7__SHIFT                                                 0x12
43150 #define DIDT_SQ_EDC_STALL_DELAY_2__UNUSED__SHIFT                                                              0x18
43151 #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4_MASK                                                   0x0000003FL
43152 #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5_MASK                                                   0x00000FC0L
43153 #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6_MASK                                                   0x0003F000L
43154 #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7_MASK                                                   0x00FC0000L
43155 #define DIDT_SQ_EDC_STALL_DELAY_2__UNUSED_MASK                                                                0xFF000000L
43156 //DIDT_SQ_EDC_STALL_DELAY_3
43157 #define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8__SHIFT                                                 0x0
43158 #define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9__SHIFT                                                 0x6
43159 #define DIDT_SQ_EDC_STALL_DELAY_3__UNUSED__SHIFT                                                              0xc
43160 #define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8_MASK                                                   0x0000003FL
43161 #define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9_MASK                                                   0x00000FC0L
43162 #define DIDT_SQ_EDC_STALL_DELAY_3__UNUSED_MASK                                                                0xFFFFF000L
43163 //DIDT_SQ_EDC_STATUS
43164 #define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE__SHIFT                                                              0x0
43165 #define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT                                                         0x1
43166 #define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE_MASK                                                                0x00000001L
43167 #define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK                                                           0x0000000EL
43168 //DIDT_SQ_EDC_OVERFLOW
43169 #define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT                                         0x0
43170 #define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT                                      0x1
43171 #define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK                                           0x00000001L
43172 #define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK                                        0x0001FFFEL
43173 //DIDT_SQ_EDC_ROLLING_POWER_DELTA
43174 #define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT                                       0x0
43175 #define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK                                         0xFFFFFFFFL
43176 //DIDT_SQ_EDC_PCC_PERF_COUNTER
43177 #define DIDT_SQ_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER__SHIFT                                             0x0
43178 #define DIDT_SQ_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER_MASK                                               0xFFFFFFFFL
43179 //DIDT_DB_CTRL0
43180 #define DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT                                                                    0x0
43181 #define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT                                                                    0x1
43182 #define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT                                                                   0x3
43183 #define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT                                                            0x4
43184 #define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN__SHIFT                                                              0x5
43185 #define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT                                                             0x6
43186 #define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT                                                      0x7
43187 #define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT                                                         0x8
43188 #define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN__SHIFT                                                                0x18
43189 #define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN__SHIFT                                                             0x19
43190 #define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT                                                  0x1a
43191 #define DIDT_DB_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT                                                         0x1b
43192 #define DIDT_DB_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT                                                        0x1c
43193 #define DIDT_DB_CTRL0__DIDT_THROTTLE_MODE__SHIFT                                                              0x1d
43194 #define DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK                                                                      0x00000001L
43195 #define DIDT_DB_CTRL0__PHASE_OFFSET_MASK                                                                      0x00000006L
43196 #define DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK                                                                     0x00000008L
43197 #define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK                                                              0x00000010L
43198 #define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN_MASK                                                                0x00000020L
43199 #define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN_MASK                                                               0x00000040L
43200 #define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK                                                        0x00000080L
43201 #define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK                                                           0x00FFFF00L
43202 #define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN_MASK                                                                  0x01000000L
43203 #define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN_MASK                                                               0x02000000L
43204 #define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK                                                    0x04000000L
43205 #define DIDT_DB_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK                                                           0x08000000L
43206 #define DIDT_DB_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK                                                          0x10000000L
43207 #define DIDT_DB_CTRL0__DIDT_THROTTLE_MODE_MASK                                                                0x20000000L
43208 //DIDT_DB_CTRL1
43209 #define DIDT_DB_CTRL1__MIN_POWER__SHIFT                                                                       0x0
43210 #define DIDT_DB_CTRL1__MAX_POWER__SHIFT                                                                       0x10
43211 #define DIDT_DB_CTRL1__MIN_POWER_MASK                                                                         0x0000FFFFL
43212 #define DIDT_DB_CTRL1__MAX_POWER_MASK                                                                         0xFFFF0000L
43213 //DIDT_DB_CTRL2
43214 #define DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT                                                                 0x0
43215 #define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT                                                        0x10
43216 #define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT                                                        0x1b
43217 #define DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK                                                                   0x00003FFFL
43218 #define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK                                                          0x03FF0000L
43219 #define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK                                                          0x78000000L
43220 //DIDT_DB_CTRL_OCP
43221 #define DIDT_DB_CTRL_OCP__OCP_MAX_POWER__SHIFT                                                                0x0
43222 #define DIDT_DB_CTRL_OCP__OCP_MAX_POWER_MASK                                                                  0x0000FFFFL
43223 //DIDT_DB_STALL_CTRL
43224 #define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT                                                        0x0
43225 #define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT                                                        0x6
43226 #define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT                                                 0xc
43227 #define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT                                                 0x12
43228 #define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK                                                          0x0000003FL
43229 #define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK                                                          0x00000FC0L
43230 #define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK                                                   0x0003F000L
43231 #define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK                                                   0x00FC0000L
43232 //DIDT_DB_TUNING_CTRL
43233 #define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT                                                        0x0
43234 #define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT                                                        0xe
43235 #define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK                                                          0x00003FFFL
43236 #define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK                                                          0x0FFFC000L
43237 //DIDT_DB_STALL_AUTO_RELEASE_CTRL
43238 #define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT                                  0x0
43239 #define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK                                    0x00FFFFFFL
43240 //DIDT_DB_CTRL3
43241 #define DIDT_DB_CTRL3__GC_DIDT_ENABLE__SHIFT                                                                  0x0
43242 #define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT                                                         0x1
43243 #define DIDT_DB_CTRL3__THROTTLE_POLICY__SHIFT                                                                 0x2
43244 #define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                    0x4
43245 #define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT                                                         0x9
43246 #define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT                                                     0xe
43247 #define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT                                                           0x16
43248 #define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT                                                           0x17
43249 #define DIDT_DB_CTRL3__QUALIFY_STALL_EN__SHIFT                                                                0x18
43250 #define DIDT_DB_CTRL3__DIDT_STALL_SEL__SHIFT                                                                  0x19
43251 #define DIDT_DB_CTRL3__DIDT_FORCE_STALL__SHIFT                                                                0x1b
43252 #define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN__SHIFT                                                             0x1c
43253 #define DIDT_DB_CTRL3__GC_DIDT_ENABLE_MASK                                                                    0x00000001L
43254 #define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK                                                           0x00000002L
43255 #define DIDT_DB_CTRL3__THROTTLE_POLICY_MASK                                                                   0x0000000CL
43256 #define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK                                                      0x000001F0L
43257 #define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK                                                           0x00003E00L
43258 #define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK                                                       0x003FC000L
43259 #define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK                                                             0x00400000L
43260 #define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK                                                             0x00800000L
43261 #define DIDT_DB_CTRL3__QUALIFY_STALL_EN_MASK                                                                  0x01000000L
43262 #define DIDT_DB_CTRL3__DIDT_STALL_SEL_MASK                                                                    0x06000000L
43263 #define DIDT_DB_CTRL3__DIDT_FORCE_STALL_MASK                                                                  0x08000000L
43264 #define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN_MASK                                                               0x10000000L
43265 //DIDT_DB_STALL_PATTERN_1_2
43266 #define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT                                                0x0
43267 #define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT                                                0x10
43268 #define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK                                                  0x00007FFFL
43269 #define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK                                                  0x7FFF0000L
43270 //DIDT_DB_STALL_PATTERN_3_4
43271 #define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT                                                0x0
43272 #define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT                                                0x10
43273 #define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK                                                  0x00007FFFL
43274 #define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK                                                  0x7FFF0000L
43275 //DIDT_DB_STALL_PATTERN_5_6
43276 #define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT                                                0x0
43277 #define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT                                                0x10
43278 #define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK                                                  0x00007FFFL
43279 #define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK                                                  0x7FFF0000L
43280 //DIDT_DB_STALL_PATTERN_7
43281 #define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT                                                  0x0
43282 #define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK                                                    0x00007FFFL
43283 //DIDT_DB_MPD_SCALE_FACTOR
43284 #define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT                                               0x0
43285 #define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT                                               0x4
43286 #define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT                                               0x8
43287 #define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT                                               0xc
43288 #define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT                                                     0x10
43289 #define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT                                                     0x14
43290 #define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT                                                     0x18
43291 #define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT                                                     0x1c
43292 #define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK                                                 0x0000000FL
43293 #define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK                                                 0x000000F0L
43294 #define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK                                                 0x00000F00L
43295 #define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK                                                 0x0000F000L
43296 #define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK                                                       0x000F0000L
43297 #define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK                                                       0x00F00000L
43298 #define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK                                                       0x0F000000L
43299 #define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK                                                       0xF0000000L
43300 //DIDT_DB_STALL_RELEASE_CNTL0
43301 #define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN__SHIFT                                        0x0
43302 #define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT                                               0x1
43303 #define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT                                             0x2
43304 #define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT                                             0xd
43305 #define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN_MASK                                          0x00000001L
43306 #define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL_MASK                                                 0x00000002L
43307 #define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK                                               0x00001FFCL
43308 #define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK                                               0x00FFE000L
43309 //DIDT_DB_STALL_RELEASE_CNTL1
43310 #define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT                                      0x0
43311 #define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT                                      0x5
43312 #define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT                                      0xa
43313 #define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT                                      0xf
43314 #define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK                                        0x0000001FL
43315 #define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK                                        0x000003E0L
43316 #define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK                                        0x00007C00L
43317 #define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK                                        0x000F8000L
43318 //DIDT_DB_STALL_RELEASE_CNTL_STATUS
43319 #define DIDT_DB_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE__SHIFT                           0x0
43320 #define DIDT_DB_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE_MASK                             0x00000003L
43321 //DIDT_DB_WEIGHT0_3
43322 #define DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT                                                                     0x0
43323 #define DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT                                                                     0x8
43324 #define DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT                                                                     0x10
43325 #define DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT                                                                     0x18
43326 #define DIDT_DB_WEIGHT0_3__WEIGHT0_MASK                                                                       0x000000FFL
43327 #define DIDT_DB_WEIGHT0_3__WEIGHT1_MASK                                                                       0x0000FF00L
43328 #define DIDT_DB_WEIGHT0_3__WEIGHT2_MASK                                                                       0x00FF0000L
43329 #define DIDT_DB_WEIGHT0_3__WEIGHT3_MASK                                                                       0xFF000000L
43330 //DIDT_DB_WEIGHT4_7
43331 #define DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT                                                                     0x0
43332 #define DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT                                                                     0x8
43333 #define DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT                                                                     0x10
43334 #define DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT                                                                     0x18
43335 #define DIDT_DB_WEIGHT4_7__WEIGHT4_MASK                                                                       0x000000FFL
43336 #define DIDT_DB_WEIGHT4_7__WEIGHT5_MASK                                                                       0x0000FF00L
43337 #define DIDT_DB_WEIGHT4_7__WEIGHT6_MASK                                                                       0x00FF0000L
43338 #define DIDT_DB_WEIGHT4_7__WEIGHT7_MASK                                                                       0xFF000000L
43339 //DIDT_DB_WEIGHT8_11
43340 #define DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT                                                                    0x0
43341 #define DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT                                                                    0x8
43342 #define DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT                                                                   0x10
43343 #define DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT                                                                   0x18
43344 #define DIDT_DB_WEIGHT8_11__WEIGHT8_MASK                                                                      0x000000FFL
43345 #define DIDT_DB_WEIGHT8_11__WEIGHT9_MASK                                                                      0x0000FF00L
43346 #define DIDT_DB_WEIGHT8_11__WEIGHT10_MASK                                                                     0x00FF0000L
43347 #define DIDT_DB_WEIGHT8_11__WEIGHT11_MASK                                                                     0xFF000000L
43348 //DIDT_DB_EDC_CTRL
43349 #define DIDT_DB_EDC_CTRL__EDC_EN__SHIFT                                                                       0x0
43350 #define DIDT_DB_EDC_CTRL__EDC_SW_RST__SHIFT                                                                   0x1
43351 #define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT                                                          0x2
43352 #define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL__SHIFT                                                              0x3
43353 #define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                  0x4
43354 #define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT                                                   0x9
43355 #define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT                                                     0x11
43356 #define DIDT_DB_EDC_CTRL__GC_EDC_EN__SHIFT                                                                    0x12
43357 #define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT                                                          0x13
43358 #define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT                                                         0x15
43359 #define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT                                                         0x16
43360 #define DIDT_DB_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT                                                           0x17
43361 #define DIDT_DB_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN__SHIFT                                                 0x18
43362 #define DIDT_DB_EDC_CTRL__EDC_EN_MASK                                                                         0x00000001L
43363 #define DIDT_DB_EDC_CTRL__EDC_SW_RST_MASK                                                                     0x00000002L
43364 #define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK                                                            0x00000004L
43365 #define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL_MASK                                                                0x00000008L
43366 #define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK                                                    0x000001F0L
43367 #define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK                                                     0x0001FE00L
43368 #define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK                                                       0x00020000L
43369 #define DIDT_DB_EDC_CTRL__GC_EDC_EN_MASK                                                                      0x00040000L
43370 #define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY_MASK                                                            0x00180000L
43371 #define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK                                                           0x00200000L
43372 #define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK                                                           0x00400000L
43373 #define DIDT_DB_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK                                                             0x00800000L
43374 #define DIDT_DB_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN_MASK                                                   0x01000000L
43375 //DIDT_DB_EDC_THRESHOLD
43376 #define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT                                                           0x0
43377 #define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD_MASK                                                             0xFFFFFFFFL
43378 //DIDT_DB_EDC_STALL_PATTERN_1_2
43379 #define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT                                             0x0
43380 #define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT                                             0x10
43381 #define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK                                               0x00007FFFL
43382 #define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK                                               0x7FFF0000L
43383 //DIDT_DB_EDC_STALL_PATTERN_3_4
43384 #define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT                                             0x0
43385 #define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT                                             0x10
43386 #define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK                                               0x00007FFFL
43387 #define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK                                               0x7FFF0000L
43388 //DIDT_DB_EDC_STALL_PATTERN_5_6
43389 #define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT                                             0x0
43390 #define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT                                             0x10
43391 #define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK                                               0x00007FFFL
43392 #define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK                                               0x7FFF0000L
43393 //DIDT_DB_EDC_STALL_PATTERN_7
43394 #define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT                                               0x0
43395 #define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK                                                 0x00007FFFL
43396 //DIDT_DB_EDC_TIMER_PERIOD
43397 #define DIDT_DB_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD__SHIFT                                                     0x0
43398 #define DIDT_DB_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD_MASK                                                       0x00003FFFL
43399 //DIDT_DB_THROTTLE_CTRL
43400 #define DIDT_DB_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT                                                         0x0
43401 #define DIDT_DB_THROTTLE_CTRL__PCC_STALL_EN__SHIFT                                                            0x1
43402 #define DIDT_DB_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT                                                         0x2
43403 #define DIDT_DB_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT                                                        0x3
43404 #define DIDT_DB_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK                                                           0x00000001L
43405 #define DIDT_DB_THROTTLE_CTRL__PCC_STALL_EN_MASK                                                              0x00000002L
43406 #define DIDT_DB_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK                                                           0x00000004L
43407 #define DIDT_DB_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK                                                          0x00000008L
43408 //DIDT_DB_EDC_STALL_DELAY_1
43409 #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0__SHIFT                                                 0x0
43410 #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1__SHIFT                                                 0x5
43411 #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB2__SHIFT                                                 0xa
43412 #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB3__SHIFT                                                 0xf
43413 #define DIDT_DB_EDC_STALL_DELAY_1__UNUSED__SHIFT                                                              0x14
43414 #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0_MASK                                                   0x0000001FL
43415 #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1_MASK                                                   0x000003E0L
43416 #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB2_MASK                                                   0x00007C00L
43417 #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB3_MASK                                                   0x000F8000L
43418 #define DIDT_DB_EDC_STALL_DELAY_1__UNUSED_MASK                                                                0xFFF00000L
43419 //DIDT_DB_EDC_STATUS
43420 #define DIDT_DB_EDC_STATUS__EDC_FSM_STATE__SHIFT                                                              0x0
43421 #define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT                                                         0x1
43422 #define DIDT_DB_EDC_STATUS__EDC_FSM_STATE_MASK                                                                0x00000001L
43423 #define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK                                                           0x0000000EL
43424 //DIDT_DB_EDC_OVERFLOW
43425 #define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT                                         0x0
43426 #define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT                                      0x1
43427 #define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK                                           0x00000001L
43428 #define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK                                        0x0001FFFEL
43429 //DIDT_DB_EDC_ROLLING_POWER_DELTA
43430 #define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT                                       0x0
43431 #define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK                                         0xFFFFFFFFL
43432 //DIDT_DB_EDC_PCC_PERF_COUNTER
43433 #define DIDT_DB_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER__SHIFT                                             0x0
43434 #define DIDT_DB_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER_MASK                                               0xFFFFFFFFL
43435 //DIDT_TD_CTRL0
43436 #define DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT                                                                    0x0
43437 #define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT                                                                    0x1
43438 #define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT                                                                   0x3
43439 #define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT                                                            0x4
43440 #define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN__SHIFT                                                              0x5
43441 #define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT                                                             0x6
43442 #define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT                                                      0x7
43443 #define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT                                                         0x8
43444 #define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN__SHIFT                                                                0x18
43445 #define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN__SHIFT                                                             0x19
43446 #define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT                                                  0x1a
43447 #define DIDT_TD_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT                                                         0x1b
43448 #define DIDT_TD_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT                                                        0x1c
43449 #define DIDT_TD_CTRL0__DIDT_THROTTLE_MODE__SHIFT                                                              0x1d
43450 #define DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK                                                                      0x00000001L
43451 #define DIDT_TD_CTRL0__PHASE_OFFSET_MASK                                                                      0x00000006L
43452 #define DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK                                                                     0x00000008L
43453 #define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK                                                              0x00000010L
43454 #define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN_MASK                                                                0x00000020L
43455 #define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN_MASK                                                               0x00000040L
43456 #define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK                                                        0x00000080L
43457 #define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK                                                           0x00FFFF00L
43458 #define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN_MASK                                                                  0x01000000L
43459 #define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN_MASK                                                               0x02000000L
43460 #define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK                                                    0x04000000L
43461 #define DIDT_TD_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK                                                           0x08000000L
43462 #define DIDT_TD_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK                                                          0x10000000L
43463 #define DIDT_TD_CTRL0__DIDT_THROTTLE_MODE_MASK                                                                0x20000000L
43464 //DIDT_TD_CTRL1
43465 #define DIDT_TD_CTRL1__MIN_POWER__SHIFT                                                                       0x0
43466 #define DIDT_TD_CTRL1__MAX_POWER__SHIFT                                                                       0x10
43467 #define DIDT_TD_CTRL1__MIN_POWER_MASK                                                                         0x0000FFFFL
43468 #define DIDT_TD_CTRL1__MAX_POWER_MASK                                                                         0xFFFF0000L
43469 //DIDT_TD_CTRL2
43470 #define DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT                                                                 0x0
43471 #define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT                                                        0x10
43472 #define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT                                                        0x1b
43473 #define DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK                                                                   0x00003FFFL
43474 #define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK                                                          0x03FF0000L
43475 #define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK                                                          0x78000000L
43476 //DIDT_TD_CTRL_OCP
43477 #define DIDT_TD_CTRL_OCP__OCP_MAX_POWER__SHIFT                                                                0x0
43478 #define DIDT_TD_CTRL_OCP__OCP_MAX_POWER_MASK                                                                  0x0000FFFFL
43479 //DIDT_TD_STALL_CTRL
43480 #define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT                                                        0x0
43481 #define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT                                                        0x6
43482 #define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT                                                 0xc
43483 #define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT                                                 0x12
43484 #define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK                                                          0x0000003FL
43485 #define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK                                                          0x00000FC0L
43486 #define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK                                                   0x0003F000L
43487 #define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK                                                   0x00FC0000L
43488 //DIDT_TD_TUNING_CTRL
43489 #define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT                                                        0x0
43490 #define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT                                                        0xe
43491 #define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK                                                          0x00003FFFL
43492 #define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK                                                          0x0FFFC000L
43493 //DIDT_TD_STALL_AUTO_RELEASE_CTRL
43494 #define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT                                  0x0
43495 #define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK                                    0x00FFFFFFL
43496 //DIDT_TD_CTRL3
43497 #define DIDT_TD_CTRL3__GC_DIDT_ENABLE__SHIFT                                                                  0x0
43498 #define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT                                                         0x1
43499 #define DIDT_TD_CTRL3__THROTTLE_POLICY__SHIFT                                                                 0x2
43500 #define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                    0x4
43501 #define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT                                                         0x9
43502 #define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT                                                     0xe
43503 #define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT                                                           0x16
43504 #define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT                                                           0x17
43505 #define DIDT_TD_CTRL3__QUALIFY_STALL_EN__SHIFT                                                                0x18
43506 #define DIDT_TD_CTRL3__DIDT_STALL_SEL__SHIFT                                                                  0x19
43507 #define DIDT_TD_CTRL3__DIDT_FORCE_STALL__SHIFT                                                                0x1b
43508 #define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN__SHIFT                                                             0x1c
43509 #define DIDT_TD_CTRL3__GC_DIDT_ENABLE_MASK                                                                    0x00000001L
43510 #define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK                                                           0x00000002L
43511 #define DIDT_TD_CTRL3__THROTTLE_POLICY_MASK                                                                   0x0000000CL
43512 #define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK                                                      0x000001F0L
43513 #define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK                                                           0x00003E00L
43514 #define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK                                                       0x003FC000L
43515 #define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK                                                             0x00400000L
43516 #define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK                                                             0x00800000L
43517 #define DIDT_TD_CTRL3__QUALIFY_STALL_EN_MASK                                                                  0x01000000L
43518 #define DIDT_TD_CTRL3__DIDT_STALL_SEL_MASK                                                                    0x06000000L
43519 #define DIDT_TD_CTRL3__DIDT_FORCE_STALL_MASK                                                                  0x08000000L
43520 #define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN_MASK                                                               0x10000000L
43521 //DIDT_TD_STALL_PATTERN_1_2
43522 #define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT                                                0x0
43523 #define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT                                                0x10
43524 #define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK                                                  0x00007FFFL
43525 #define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK                                                  0x7FFF0000L
43526 //DIDT_TD_STALL_PATTERN_3_4
43527 #define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT                                                0x0
43528 #define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT                                                0x10
43529 #define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK                                                  0x00007FFFL
43530 #define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK                                                  0x7FFF0000L
43531 //DIDT_TD_STALL_PATTERN_5_6
43532 #define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT                                                0x0
43533 #define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT                                                0x10
43534 #define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK                                                  0x00007FFFL
43535 #define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK                                                  0x7FFF0000L
43536 //DIDT_TD_STALL_PATTERN_7
43537 #define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT                                                  0x0
43538 #define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK                                                    0x00007FFFL
43539 //DIDT_TD_MPD_SCALE_FACTOR
43540 #define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT                                               0x0
43541 #define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT                                               0x4
43542 #define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT                                               0x8
43543 #define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT                                               0xc
43544 #define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT                                                     0x10
43545 #define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT                                                     0x14
43546 #define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT                                                     0x18
43547 #define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT                                                     0x1c
43548 #define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK                                                 0x0000000FL
43549 #define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK                                                 0x000000F0L
43550 #define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK                                                 0x00000F00L
43551 #define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK                                                 0x0000F000L
43552 #define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK                                                       0x000F0000L
43553 #define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK                                                       0x00F00000L
43554 #define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK                                                       0x0F000000L
43555 #define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK                                                       0xF0000000L
43556 //DIDT_TD_STALL_RELEASE_CNTL0
43557 #define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN__SHIFT                                        0x0
43558 #define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT                                               0x1
43559 #define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT                                             0x2
43560 #define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT                                             0xd
43561 #define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN_MASK                                          0x00000001L
43562 #define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL_MASK                                                 0x00000002L
43563 #define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK                                               0x00001FFCL
43564 #define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK                                               0x00FFE000L
43565 //DIDT_TD_STALL_RELEASE_CNTL1
43566 #define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT                                      0x0
43567 #define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT                                      0x5
43568 #define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT                                      0xa
43569 #define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT                                      0xf
43570 #define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK                                        0x0000001FL
43571 #define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK                                        0x000003E0L
43572 #define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK                                        0x00007C00L
43573 #define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK                                        0x000F8000L
43574 //DIDT_TD_STALL_RELEASE_CNTL_STATUS
43575 #define DIDT_TD_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE__SHIFT                           0x0
43576 #define DIDT_TD_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE_MASK                             0x00000003L
43577 //DIDT_TD_WEIGHT0_3
43578 #define DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT                                                                     0x0
43579 #define DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT                                                                     0x8
43580 #define DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT                                                                     0x10
43581 #define DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT                                                                     0x18
43582 #define DIDT_TD_WEIGHT0_3__WEIGHT0_MASK                                                                       0x000000FFL
43583 #define DIDT_TD_WEIGHT0_3__WEIGHT1_MASK                                                                       0x0000FF00L
43584 #define DIDT_TD_WEIGHT0_3__WEIGHT2_MASK                                                                       0x00FF0000L
43585 #define DIDT_TD_WEIGHT0_3__WEIGHT3_MASK                                                                       0xFF000000L
43586 //DIDT_TD_WEIGHT4_7
43587 #define DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT                                                                     0x0
43588 #define DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT                                                                     0x8
43589 #define DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT                                                                     0x10
43590 #define DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT                                                                     0x18
43591 #define DIDT_TD_WEIGHT4_7__WEIGHT4_MASK                                                                       0x000000FFL
43592 #define DIDT_TD_WEIGHT4_7__WEIGHT5_MASK                                                                       0x0000FF00L
43593 #define DIDT_TD_WEIGHT4_7__WEIGHT6_MASK                                                                       0x00FF0000L
43594 #define DIDT_TD_WEIGHT4_7__WEIGHT7_MASK                                                                       0xFF000000L
43595 //DIDT_TD_WEIGHT8_11
43596 #define DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT                                                                    0x0
43597 #define DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT                                                                    0x8
43598 #define DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT                                                                   0x10
43599 #define DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT                                                                   0x18
43600 #define DIDT_TD_WEIGHT8_11__WEIGHT8_MASK                                                                      0x000000FFL
43601 #define DIDT_TD_WEIGHT8_11__WEIGHT9_MASK                                                                      0x0000FF00L
43602 #define DIDT_TD_WEIGHT8_11__WEIGHT10_MASK                                                                     0x00FF0000L
43603 #define DIDT_TD_WEIGHT8_11__WEIGHT11_MASK                                                                     0xFF000000L
43604 //DIDT_TD_EDC_CTRL
43605 #define DIDT_TD_EDC_CTRL__EDC_EN__SHIFT                                                                       0x0
43606 #define DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT                                                                   0x1
43607 #define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT                                                          0x2
43608 #define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT                                                              0x3
43609 #define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                  0x4
43610 #define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT                                                   0x9
43611 #define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT                                                     0x11
43612 #define DIDT_TD_EDC_CTRL__GC_EDC_EN__SHIFT                                                                    0x12
43613 #define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT                                                          0x13
43614 #define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT                                                         0x15
43615 #define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT                                                         0x16
43616 #define DIDT_TD_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT                                                           0x17
43617 #define DIDT_TD_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN__SHIFT                                                 0x18
43618 #define DIDT_TD_EDC_CTRL__EDC_EN_MASK                                                                         0x00000001L
43619 #define DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK                                                                     0x00000002L
43620 #define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK                                                            0x00000004L
43621 #define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK                                                                0x00000008L
43622 #define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK                                                    0x000001F0L
43623 #define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK                                                     0x0001FE00L
43624 #define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK                                                       0x00020000L
43625 #define DIDT_TD_EDC_CTRL__GC_EDC_EN_MASK                                                                      0x00040000L
43626 #define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY_MASK                                                            0x00180000L
43627 #define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK                                                           0x00200000L
43628 #define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK                                                           0x00400000L
43629 #define DIDT_TD_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK                                                             0x00800000L
43630 #define DIDT_TD_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN_MASK                                                   0x01000000L
43631 //DIDT_TD_EDC_THRESHOLD
43632 #define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT                                                           0x0
43633 #define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD_MASK                                                             0xFFFFFFFFL
43634 //DIDT_TD_EDC_STALL_PATTERN_1_2
43635 #define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT                                             0x0
43636 #define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT                                             0x10
43637 #define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK                                               0x00007FFFL
43638 #define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK                                               0x7FFF0000L
43639 //DIDT_TD_EDC_STALL_PATTERN_3_4
43640 #define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT                                             0x0
43641 #define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT                                             0x10
43642 #define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK                                               0x00007FFFL
43643 #define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK                                               0x7FFF0000L
43644 //DIDT_TD_EDC_STALL_PATTERN_5_6
43645 #define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT                                             0x0
43646 #define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT                                             0x10
43647 #define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK                                               0x00007FFFL
43648 #define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK                                               0x7FFF0000L
43649 //DIDT_TD_EDC_STALL_PATTERN_7
43650 #define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT                                               0x0
43651 #define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK                                                 0x00007FFFL
43652 //DIDT_TD_EDC_TIMER_PERIOD
43653 #define DIDT_TD_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD__SHIFT                                                     0x0
43654 #define DIDT_TD_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD_MASK                                                       0x00003FFFL
43655 //DIDT_TD_THROTTLE_CTRL
43656 #define DIDT_TD_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT                                                         0x0
43657 #define DIDT_TD_THROTTLE_CTRL__PCC_STALL_EN__SHIFT                                                            0x1
43658 #define DIDT_TD_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT                                                         0x2
43659 #define DIDT_TD_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT                                                        0x3
43660 #define DIDT_TD_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK                                                           0x00000001L
43661 #define DIDT_TD_THROTTLE_CTRL__PCC_STALL_EN_MASK                                                              0x00000002L
43662 #define DIDT_TD_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK                                                           0x00000004L
43663 #define DIDT_TD_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK                                                          0x00000008L
43664 //DIDT_TD_EDC_STALL_DELAY_1
43665 #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0__SHIFT                                                 0x0
43666 #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1__SHIFT                                                 0x6
43667 #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2__SHIFT                                                 0xc
43668 #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3__SHIFT                                                 0x12
43669 #define DIDT_TD_EDC_STALL_DELAY_1__UNUSED__SHIFT                                                              0x18
43670 #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0_MASK                                                   0x0000003FL
43671 #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1_MASK                                                   0x00000FC0L
43672 #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2_MASK                                                   0x0003F000L
43673 #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3_MASK                                                   0x00FC0000L
43674 #define DIDT_TD_EDC_STALL_DELAY_1__UNUSED_MASK                                                                0xFF000000L
43675 //DIDT_TD_EDC_STALL_DELAY_2
43676 #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4__SHIFT                                                 0x0
43677 #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5__SHIFT                                                 0x6
43678 #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6__SHIFT                                                 0xc
43679 #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7__SHIFT                                                 0x12
43680 #define DIDT_TD_EDC_STALL_DELAY_2__UNUSED__SHIFT                                                              0x18
43681 #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4_MASK                                                   0x0000003FL
43682 #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5_MASK                                                   0x00000FC0L
43683 #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6_MASK                                                   0x0003F000L
43684 #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7_MASK                                                   0x00FC0000L
43685 #define DIDT_TD_EDC_STALL_DELAY_2__UNUSED_MASK                                                                0xFF000000L
43686 //DIDT_TD_EDC_STALL_DELAY_3
43687 #define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8__SHIFT                                                 0x0
43688 #define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9__SHIFT                                                 0x6
43689 #define DIDT_TD_EDC_STALL_DELAY_3__UNUSED__SHIFT                                                              0xc
43690 #define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8_MASK                                                   0x0000003FL
43691 #define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9_MASK                                                   0x00000FC0L
43692 #define DIDT_TD_EDC_STALL_DELAY_3__UNUSED_MASK                                                                0xFFFFF000L
43693 //DIDT_TD_EDC_STATUS
43694 #define DIDT_TD_EDC_STATUS__EDC_FSM_STATE__SHIFT                                                              0x0
43695 #define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT                                                         0x1
43696 #define DIDT_TD_EDC_STATUS__EDC_FSM_STATE_MASK                                                                0x00000001L
43697 #define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK                                                           0x0000000EL
43698 //DIDT_TD_EDC_OVERFLOW
43699 #define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT                                         0x0
43700 #define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT                                      0x1
43701 #define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK                                           0x00000001L
43702 #define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK                                        0x0001FFFEL
43703 //DIDT_TD_EDC_ROLLING_POWER_DELTA
43704 #define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT                                       0x0
43705 #define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK                                         0xFFFFFFFFL
43706 //DIDT_TD_EDC_PCC_PERF_COUNTER
43707 #define DIDT_TD_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER__SHIFT                                             0x0
43708 #define DIDT_TD_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER_MASK                                               0xFFFFFFFFL
43709 //DIDT_TCP_CTRL0
43710 #define DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT                                                                   0x0
43711 #define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT                                                                   0x1
43712 #define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT                                                                  0x3
43713 #define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT                                                           0x4
43714 #define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN__SHIFT                                                             0x5
43715 #define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT                                                            0x6
43716 #define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT                                                     0x7
43717 #define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT                                                        0x8
43718 #define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN__SHIFT                                                               0x18
43719 #define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN__SHIFT                                                            0x19
43720 #define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT                                                 0x1a
43721 #define DIDT_TCP_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT                                                        0x1b
43722 #define DIDT_TCP_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT                                                       0x1c
43723 #define DIDT_TCP_CTRL0__DIDT_THROTTLE_MODE__SHIFT                                                             0x1d
43724 #define DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK                                                                     0x00000001L
43725 #define DIDT_TCP_CTRL0__PHASE_OFFSET_MASK                                                                     0x00000006L
43726 #define DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK                                                                    0x00000008L
43727 #define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK                                                             0x00000010L
43728 #define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN_MASK                                                               0x00000020L
43729 #define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN_MASK                                                              0x00000040L
43730 #define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK                                                       0x00000080L
43731 #define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK                                                          0x00FFFF00L
43732 #define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN_MASK                                                                 0x01000000L
43733 #define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN_MASK                                                              0x02000000L
43734 #define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK                                                   0x04000000L
43735 #define DIDT_TCP_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK                                                          0x08000000L
43736 #define DIDT_TCP_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK                                                         0x10000000L
43737 #define DIDT_TCP_CTRL0__DIDT_THROTTLE_MODE_MASK                                                               0x20000000L
43738 //DIDT_TCP_CTRL1
43739 #define DIDT_TCP_CTRL1__MIN_POWER__SHIFT                                                                      0x0
43740 #define DIDT_TCP_CTRL1__MAX_POWER__SHIFT                                                                      0x10
43741 #define DIDT_TCP_CTRL1__MIN_POWER_MASK                                                                        0x0000FFFFL
43742 #define DIDT_TCP_CTRL1__MAX_POWER_MASK                                                                        0xFFFF0000L
43743 //DIDT_TCP_CTRL2
43744 #define DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT                                                                0x0
43745 #define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT                                                       0x10
43746 #define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT                                                       0x1b
43747 #define DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK                                                                  0x00003FFFL
43748 #define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK                                                         0x03FF0000L
43749 #define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK                                                         0x78000000L
43750 //DIDT_TCP_CTRL_OCP
43751 #define DIDT_TCP_CTRL_OCP__OCP_MAX_POWER__SHIFT                                                               0x0
43752 #define DIDT_TCP_CTRL_OCP__OCP_MAX_POWER_MASK                                                                 0x0000FFFFL
43753 //DIDT_TCP_STALL_CTRL
43754 #define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT                                                       0x0
43755 #define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT                                                       0x6
43756 #define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT                                                0xc
43757 #define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT                                                0x12
43758 #define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK                                                         0x0000003FL
43759 #define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK                                                         0x00000FC0L
43760 #define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK                                                  0x0003F000L
43761 #define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK                                                  0x00FC0000L
43762 //DIDT_TCP_TUNING_CTRL
43763 #define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT                                                       0x0
43764 #define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT                                                       0xe
43765 #define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK                                                         0x00003FFFL
43766 #define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK                                                         0x0FFFC000L
43767 //DIDT_TCP_STALL_AUTO_RELEASE_CTRL
43768 #define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT                                 0x0
43769 #define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK                                   0x00FFFFFFL
43770 //DIDT_TCP_CTRL3
43771 #define DIDT_TCP_CTRL3__GC_DIDT_ENABLE__SHIFT                                                                 0x0
43772 #define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT                                                        0x1
43773 #define DIDT_TCP_CTRL3__THROTTLE_POLICY__SHIFT                                                                0x2
43774 #define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                   0x4
43775 #define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT                                                        0x9
43776 #define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT                                                    0xe
43777 #define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT                                                          0x16
43778 #define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT                                                          0x17
43779 #define DIDT_TCP_CTRL3__QUALIFY_STALL_EN__SHIFT                                                               0x18
43780 #define DIDT_TCP_CTRL3__DIDT_STALL_SEL__SHIFT                                                                 0x19
43781 #define DIDT_TCP_CTRL3__DIDT_FORCE_STALL__SHIFT                                                               0x1b
43782 #define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN__SHIFT                                                            0x1c
43783 #define DIDT_TCP_CTRL3__GC_DIDT_ENABLE_MASK                                                                   0x00000001L
43784 #define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK                                                          0x00000002L
43785 #define DIDT_TCP_CTRL3__THROTTLE_POLICY_MASK                                                                  0x0000000CL
43786 #define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK                                                     0x000001F0L
43787 #define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK                                                          0x00003E00L
43788 #define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK                                                      0x003FC000L
43789 #define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK                                                            0x00400000L
43790 #define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK                                                            0x00800000L
43791 #define DIDT_TCP_CTRL3__QUALIFY_STALL_EN_MASK                                                                 0x01000000L
43792 #define DIDT_TCP_CTRL3__DIDT_STALL_SEL_MASK                                                                   0x06000000L
43793 #define DIDT_TCP_CTRL3__DIDT_FORCE_STALL_MASK                                                                 0x08000000L
43794 #define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN_MASK                                                              0x10000000L
43795 //DIDT_TCP_STALL_PATTERN_1_2
43796 #define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT                                               0x0
43797 #define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT                                               0x10
43798 #define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK                                                 0x00007FFFL
43799 #define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK                                                 0x7FFF0000L
43800 //DIDT_TCP_STALL_PATTERN_3_4
43801 #define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT                                               0x0
43802 #define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT                                               0x10
43803 #define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK                                                 0x00007FFFL
43804 #define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK                                                 0x7FFF0000L
43805 //DIDT_TCP_STALL_PATTERN_5_6
43806 #define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT                                               0x0
43807 #define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT                                               0x10
43808 #define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK                                                 0x00007FFFL
43809 #define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK                                                 0x7FFF0000L
43810 //DIDT_TCP_STALL_PATTERN_7
43811 #define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT                                                 0x0
43812 #define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK                                                   0x00007FFFL
43813 //DIDT_TCP_MPD_SCALE_FACTOR
43814 #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT                                              0x0
43815 #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT                                              0x4
43816 #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT                                              0x8
43817 #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT                                              0xc
43818 #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT                                                    0x10
43819 #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT                                                    0x14
43820 #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT                                                    0x18
43821 #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT                                                    0x1c
43822 #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK                                                0x0000000FL
43823 #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK                                                0x000000F0L
43824 #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK                                                0x00000F00L
43825 #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK                                                0x0000F000L
43826 #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK                                                      0x000F0000L
43827 #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK                                                      0x00F00000L
43828 #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK                                                      0x0F000000L
43829 #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK                                                      0xF0000000L
43830 //DIDT_TCP_STALL_RELEASE_CNTL0
43831 #define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN__SHIFT                                       0x0
43832 #define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT                                              0x1
43833 #define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT                                            0x2
43834 #define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT                                            0xd
43835 #define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN_MASK                                         0x00000001L
43836 #define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL_MASK                                                0x00000002L
43837 #define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK                                              0x00001FFCL
43838 #define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK                                              0x00FFE000L
43839 //DIDT_TCP_STALL_RELEASE_CNTL1
43840 #define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT                                     0x0
43841 #define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT                                     0x5
43842 #define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT                                     0xa
43843 #define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT                                     0xf
43844 #define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK                                       0x0000001FL
43845 #define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK                                       0x000003E0L
43846 #define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK                                       0x00007C00L
43847 #define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK                                       0x000F8000L
43848 //DIDT_TCP_STALL_RELEASE_CNTL_STATUS
43849 #define DIDT_TCP_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE__SHIFT                          0x0
43850 #define DIDT_TCP_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE_MASK                            0x00000003L
43851 //DIDT_TCP_WEIGHT0_3
43852 #define DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT                                                                    0x0
43853 #define DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT                                                                    0x8
43854 #define DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT                                                                    0x10
43855 #define DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT                                                                    0x18
43856 #define DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK                                                                      0x000000FFL
43857 #define DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK                                                                      0x0000FF00L
43858 #define DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK                                                                      0x00FF0000L
43859 #define DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK                                                                      0xFF000000L
43860 //DIDT_TCP_WEIGHT4_7
43861 #define DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT                                                                    0x0
43862 #define DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT                                                                    0x8
43863 #define DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT                                                                    0x10
43864 #define DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT                                                                    0x18
43865 #define DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK                                                                      0x000000FFL
43866 #define DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK                                                                      0x0000FF00L
43867 #define DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK                                                                      0x00FF0000L
43868 #define DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK                                                                      0xFF000000L
43869 //DIDT_TCP_WEIGHT8_11
43870 #define DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT                                                                   0x0
43871 #define DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT                                                                   0x8
43872 #define DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT                                                                  0x10
43873 #define DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT                                                                  0x18
43874 #define DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK                                                                     0x000000FFL
43875 #define DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK                                                                     0x0000FF00L
43876 #define DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK                                                                    0x00FF0000L
43877 #define DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK                                                                    0xFF000000L
43878 //DIDT_TCP_EDC_CTRL
43879 #define DIDT_TCP_EDC_CTRL__EDC_EN__SHIFT                                                                      0x0
43880 #define DIDT_TCP_EDC_CTRL__EDC_SW_RST__SHIFT                                                                  0x1
43881 #define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT                                                         0x2
43882 #define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL__SHIFT                                                             0x3
43883 #define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                 0x4
43884 #define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT                                                  0x9
43885 #define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT                                                    0x11
43886 #define DIDT_TCP_EDC_CTRL__GC_EDC_EN__SHIFT                                                                   0x12
43887 #define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT                                                         0x13
43888 #define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT                                                        0x15
43889 #define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT                                                        0x16
43890 #define DIDT_TCP_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT                                                          0x17
43891 #define DIDT_TCP_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN__SHIFT                                                0x18
43892 #define DIDT_TCP_EDC_CTRL__EDC_EN_MASK                                                                        0x00000001L
43893 #define DIDT_TCP_EDC_CTRL__EDC_SW_RST_MASK                                                                    0x00000002L
43894 #define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK                                                           0x00000004L
43895 #define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL_MASK                                                               0x00000008L
43896 #define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK                                                   0x000001F0L
43897 #define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK                                                    0x0001FE00L
43898 #define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK                                                      0x00020000L
43899 #define DIDT_TCP_EDC_CTRL__GC_EDC_EN_MASK                                                                     0x00040000L
43900 #define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY_MASK                                                           0x00180000L
43901 #define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK                                                          0x00200000L
43902 #define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK                                                          0x00400000L
43903 #define DIDT_TCP_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK                                                            0x00800000L
43904 #define DIDT_TCP_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN_MASK                                                  0x01000000L
43905 //DIDT_TCP_EDC_THRESHOLD
43906 #define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT                                                          0x0
43907 #define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD_MASK                                                            0xFFFFFFFFL
43908 //DIDT_TCP_EDC_STALL_PATTERN_1_2
43909 #define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT                                            0x0
43910 #define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT                                            0x10
43911 #define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK                                              0x00007FFFL
43912 #define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK                                              0x7FFF0000L
43913 //DIDT_TCP_EDC_STALL_PATTERN_3_4
43914 #define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT                                            0x0
43915 #define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT                                            0x10
43916 #define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK                                              0x00007FFFL
43917 #define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK                                              0x7FFF0000L
43918 //DIDT_TCP_EDC_STALL_PATTERN_5_6
43919 #define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT                                            0x0
43920 #define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT                                            0x10
43921 #define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK                                              0x00007FFFL
43922 #define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK                                              0x7FFF0000L
43923 //DIDT_TCP_EDC_STALL_PATTERN_7
43924 #define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT                                              0x0
43925 #define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK                                                0x00007FFFL
43926 //DIDT_TCP_EDC_TIMER_PERIOD
43927 #define DIDT_TCP_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD__SHIFT                                                    0x0
43928 #define DIDT_TCP_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD_MASK                                                      0x00003FFFL
43929 //DIDT_TCP_THROTTLE_CTRL
43930 #define DIDT_TCP_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT                                                        0x0
43931 #define DIDT_TCP_THROTTLE_CTRL__PCC_STALL_EN__SHIFT                                                           0x1
43932 #define DIDT_TCP_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT                                                        0x2
43933 #define DIDT_TCP_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT                                                       0x3
43934 #define DIDT_TCP_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK                                                          0x00000001L
43935 #define DIDT_TCP_THROTTLE_CTRL__PCC_STALL_EN_MASK                                                             0x00000002L
43936 #define DIDT_TCP_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK                                                          0x00000004L
43937 #define DIDT_TCP_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK                                                         0x00000008L
43938 //DIDT_TCP_EDC_STALL_DELAY_1
43939 #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0__SHIFT                                               0x0
43940 #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1__SHIFT                                               0x6
43941 #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2__SHIFT                                               0xc
43942 #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3__SHIFT                                               0x12
43943 #define DIDT_TCP_EDC_STALL_DELAY_1__UNUSED__SHIFT                                                             0x18
43944 #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0_MASK                                                 0x0000003FL
43945 #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1_MASK                                                 0x00000FC0L
43946 #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2_MASK                                                 0x0003F000L
43947 #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3_MASK                                                 0x00FC0000L
43948 #define DIDT_TCP_EDC_STALL_DELAY_1__UNUSED_MASK                                                               0xFF000000L
43949 //DIDT_TCP_EDC_STALL_DELAY_2
43950 #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4__SHIFT                                               0x0
43951 #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5__SHIFT                                               0x6
43952 #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6__SHIFT                                               0xc
43953 #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7__SHIFT                                               0x12
43954 #define DIDT_TCP_EDC_STALL_DELAY_2__UNUSED__SHIFT                                                             0x18
43955 #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4_MASK                                                 0x0000003FL
43956 #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5_MASK                                                 0x00000FC0L
43957 #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6_MASK                                                 0x0003F000L
43958 #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7_MASK                                                 0x00FC0000L
43959 #define DIDT_TCP_EDC_STALL_DELAY_2__UNUSED_MASK                                                               0xFF000000L
43960 //DIDT_TCP_EDC_STALL_DELAY_3
43961 #define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8__SHIFT                                               0x0
43962 #define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9__SHIFT                                               0x6
43963 #define DIDT_TCP_EDC_STALL_DELAY_3__UNUSED__SHIFT                                                             0xc
43964 #define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8_MASK                                                 0x0000003FL
43965 #define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9_MASK                                                 0x00000FC0L
43966 #define DIDT_TCP_EDC_STALL_DELAY_3__UNUSED_MASK                                                               0xFFFFF000L
43967 //DIDT_TCP_EDC_STATUS
43968 #define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE__SHIFT                                                             0x0
43969 #define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT                                                        0x1
43970 #define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE_MASK                                                               0x00000001L
43971 #define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK                                                          0x0000000EL
43972 //DIDT_TCP_EDC_OVERFLOW
43973 #define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT                                        0x0
43974 #define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT                                     0x1
43975 #define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK                                          0x00000001L
43976 #define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK                                       0x0001FFFEL
43977 //DIDT_TCP_EDC_ROLLING_POWER_DELTA
43978 #define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT                                      0x0
43979 #define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK                                        0xFFFFFFFFL
43980 //DIDT_TCP_EDC_PCC_PERF_COUNTER
43981 #define DIDT_TCP_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER__SHIFT                                            0x0
43982 #define DIDT_TCP_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER_MASK                                              0xFFFFFFFFL
43983 //DIDT_SQ_STALL_EVENT_COUNTER
43984 #define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT                                          0x0
43985 #define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK                                            0xFFFFFFFFL
43986 //DIDT_DB_STALL_EVENT_COUNTER
43987 #define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT                                          0x0
43988 #define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK                                            0xFFFFFFFFL
43989 //DIDT_TD_STALL_EVENT_COUNTER
43990 #define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT                                          0x0
43991 #define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK                                            0xFFFFFFFFL
43992 //DIDT_TCP_STALL_EVENT_COUNTER
43993 #define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT                                         0x0
43994 #define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK                                           0xFFFFFFFFL
43995 
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44002 #endif